CY62136EV30LL-45BVXI [INFINEON]
Asynchronous SRAM;
| 型号： | CY62136EV30LL-45BVXI |
| 厂家： | 
Infineon |
| 描述： | Asynchronous SRAM 静态存储器 内存集成电路 |
| 文件： | 总19页 (文件大小：392K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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The document following this cover page is marked as “Cypress” document as this is the
company that originally developed the product. Please note that Infineon will continue
to offer the product to new and existing customers as part of the Infineon product
portfolio.
Continuity of document content
The fact that Infineon offers the following product as part of the Infineon product
portfolio does not lead to any changes to this document. Future revisions will occur
when appropriate, and any changes will be set out on the document history page.
Continuity of ordering part numbers
Infineon continues to support existing part numbers. Please continue to use the
ordering part numbers listed in the datasheet for ordering.
www.infineon.com
CY62136EV30 MoBL®
2-Mbit (128K × 16) Static RAM
2-Mbit (128K
× 16) Static RAM
Features
Functional Description
■ Very high speed: 45 ns
The CY62136EV30 is a high performance CMOS static RAM
organized as 128K words by 16 bits. This device features
advanced circuit design to provide ultra low active current. This
is ideal for providing More Battery Life™ (MoBL®) in portable
applications such as cellular telephones. The device also has an
automatic power down feature that significantly reduces power
consumption when addresses are not toggling. The device can
also be put into standby mode reducing power consumption by
more than 99% when deselected (CE HIGH). The input/output
pins (I/O0 through I/O15) are placed in a high impedance state
when: deselected (CE HIGH), outputs are disabled (OE HIGH),
both Byte High Enable and Byte Low Enable are disabled (BHE,
BLE HIGH), or during a write operation (CE LOW and WE LOW).
■ Wide voltage range: 2.20 V to 3.60 V
■ Pin compatible with CY62136CV30
■ Ultra low standby power
❐ Typical standby current: 1 A
❐ Maximum standby current: 7 A
■ Ultra low active power
❐ Typical active current: 2 mA at f = 1 MHz
■ Easy memory expansion with CE and OE features
■ Automatic power down when deselected
Writing to the device is accomplished by taking Chip Enable (CE)
and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is
LOW, then data from I/O pins (I/O0 through I/O7), is written into
the location specified on the address pins (A0 through A16). If
Byte High Enable (BHE) is LOW, then data from I/O pins (I/O8
through I/O15) is written into the location specified on the address
pins (A0 through A16).
■ Complementary metal oxide semiconductor (CMOS) for
optimum speed/power
■ Offered in a Pb-free 48-ball very fine ball grid array (VFBGA)
and 44-pin thin small outline package (TSOP II) packages
Reading from the device is accomplished by taking Chip Enable
(CE) and Output Enable (OE) LOW while forcing the Write
Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data
from the memory location specified by the address pins appear
on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from
memory appear on I/O8 to I/O15. See the Truth Table on page 11
for a complete description of read and write modes.
For a complete list of related documentation, click here.
Logic Block Diagram
DATA IN DRIVERS
A10
A9
A8
A7
A6
A5
A4
A3
A2
128K x 16
RAM Array
I/O0–I/O7
I/O8–I/O15
A1
A0
COLUMN DECODER
BHE
WE
CE
OE
BLE
Cypress Semiconductor Corporation
Document Number: 38-05569 Rev. *J
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised May 11, 2017
CY62136EV30 MoBL®
Contents
Pin Configurations ...........................................................3
Product Portfolio ..............................................................3
Maximum Ratings .............................................................4
Operating Range ...............................................................4
Electrical Characteristics .................................................4
Capacitance ......................................................................5
Thermal Resistance ..........................................................5
AC Test Loads and Waveforms .......................................5
Data Retention Characteristics .......................................6
Data Retention Waveform ................................................6
Switching Characteristics ................................................7
Switching Waveforms ......................................................8
Truth Table ......................................................................11
Ordering Information ......................................................12
Ordering Code Definitions .........................................12
Package Diagrams ..........................................................13
Acronyms ........................................................................15
Document Conventions .................................................15
Units of Measure .......................................................15
Document History Page .................................................16
Sales, Solutions, and Legal Information ......................18
Worldwide Sales and Design Support .......................18
Products ....................................................................18
PSoC® Solutions ......................................................18
Cypress Developer Community .................................18
Technical Support .....................................................18
Document Number: 38-05569 Rev. *J
Page 2 of 18
CY62136EV30 MoBL®
Pin Configurations
Figure 1. 48-ball VFBGA pinout (Top View) [1, 2]
Figure 2. 44-pin TSOP II pinout (Top View) [1]
1
2
4
3
5
6
NC
I/O
44
1
A
4
A
5
A
A
2
A
43
42
41
40
39
38
A
A
OE
2
3
4
5
6
BLE
0
1
A
B
C
3
6
A
A
2
7
OE
A
1
A
A
I/O BHE
CE
I/O
4
3
0
8
BHE
BLE
I/O
A
0
CE
I/O
A
A
7
I/O I/O
I/O
2
0
15
5
6
9
10
1
37
36
35
34
33
I/O
I/O
8
I/O
I/O
1
2
14
13
12
9
Vcc
Vss
A
V
I/O
I/O
3
NC
NC
D
E
F
SS
7
11
10
11
12
13
I/O
V
SS
I/O
3
CC
V
SS
V
V
A
V
CC
CC
I/O
I/O
16
12
4
32
I/O
I/O
I/O
4
5
6
7
11
10
31
30
29
28
I/O
I/O
I/O
14
15
16
A
A
15
I/O
I/O
I/O
I/O
I/O
14
13
5
14
6
9
8
I/O
NC
WE 17
A
A
G
H
I/O
I/O
NC
WE
13
12
18
27
26
25
15
7
A
16
A
8
19
20
21
22
A
14
A
9
15
A
A
11
10
A
A
A
A
NC
NC
10
9
11
8
A
A
12
24
23
13
A
NC
Product Portfolio
Power Dissipation
Operating ICC (mA)
f = 1 MHz f = fmax
VCC Range (V)
Speed
(ns)
Product [3]
Standby ISB2 (A)
Min
Typ [3]
Max
Typ [3]
Max
Typ [3]
Max
Typ [3]
Max
CY62136EV30LL
2.2
3.0
3.6
45
2
2.5
15
20
1
7
Notes
1. NC pins are not connected on the die.
2. Pins D3, H1, G2, H6 and H3 in the VFBGA package are address expansion pins for 4 Mb, 8 Mb, 16 Mb, and 32 Mb and 64 Mb respectively.
3. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V = V
, T = 25 °C.
CC
CC(typ.)
A
Document Number: 38-05569 Rev. *J
Page 3 of 18
CY62136EV30 MoBL®
DC input voltage [4, 5] ....... –0.3 V to 3.9 V (VCC MAX + 0.3 V)
Output current into outputs (LOW) ............................. 20 mA
Maximum Ratings
Exceeding the maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Static discharge voltage
(per MIL-STD-883, Method 3015) ......................... > 2001 V
Storage temperature ............................... –65 °C to + 150 °C
Latch-up current ....................................................> 200 mA
Ambient temperature
with power applied .................................. –55 °C to + 125 °C
Operating Range
Supply voltage
Ambient
Temperature
to ground potential [4, 5] ... –0.3 V to 3.9 V (VCC MAX + 0.3 V)
[6]
Device
Range
VCC
DC voltage applied to outputs
CY62136EV30LL Industrial –40 °C to +85 °C 2.2 V–3.6 V
in High Z state [4, 5] .......... –0.3 V to 3.9 V (VCC MAX + 0.3 V)
Electrical Characteristics
Over the Operating Range
45 ns
Typ [7]
Parameter
VOH
Description
Test Conditions
Unit
Min
2.0
2.4
–
Max
Output HIGH voltage
IOH = –0.1 mA
VCC = 2.20 V
VCC = 2.70 V
VCC = 2.20 V
VCC = 2.70 V
–
–
–
–
V
V
IOH = –1.0 mA
VOL
VIH
VIL
Output LOW voltage
Input HIGH voltage
Input LOW voltage
IOL = 0.1 mA
–
0.4
V
IOL = 2.1 mA
–
–
0.4
V
VCC = 2.2 V to 2.7 V
VCC= 2.7 V to 3.6 V
VCC = 2.2 V to 2.7 V
VCC= 2.7 V to 3.6 V
GND < VI < VCC
1.8
2.2
–0.3
–0.3
–1
–1
–
–
VCC + 0.3
VCC + 0.3
0.6
V
–
V
–
V
–
0.8
V
IIX
Input leakage current
–
+1
A
A
mA
IOZ
ICC
Output leakage current
VCC operating supply current
GND < VO < VCC, output disabled
–
+1
f = fmax = 1/tRC
f = 1 MHz
VCC = VCCmax,
IOUT = 0 mA
CMOS levels
15
2
20
–
2.5
[8]
[8]
ISB1
Automatic CE power-down
current – CMOS inputs
CE > VCC0.2 V,
–
1
1
7
7
A
A
V
IN > VCC – 0.2 V, VIN< 0.2 V
f = fmax (address and data only),
f = 0 (OE, and WE), VCC = 3.60 V
CE > VCC – 0.2 V,
ISB2
Automatic CE power-down
current – CMOS inputs
–
VIN > VCC – 0.2 V or VIN < 0.2V, f = 0,
VCC = 3.60 V
Notes
4.
5.
V
V
= –2.0 V for pulse durations less than 20 ns.
IL(min.)
= V + 0.75 V for pulse durations less than 20 ns.
IH(max)
CC
6. Full Device AC operation assumes a 100 s ramp time from 0 to Vcc(min) and 200 s wait time after V stabilization.
CC
7. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V = V
, T = 25 °C.
A
CC
CC(typ.)
8. Chip enable (CE) and byte enables (BHE and BLE) need to be tied to CMOS levels to meet the I
/I
/I
specification. Other inputs can be left floating.
SB1 SB2 CCDR
Document Number: 38-05569 Rev. *J
Page 4 of 18
CY62136EV30 MoBL®
Capacitance
Parameter [9]
Description
Input capacitance
Output capacitance
Test Conditions
Max
10
Unit
pF
CIN
TA = 25 °C, f = 1 MHz, VCC = VCC(typ)
COUT
10
pF
Thermal Resistance
Parameter [9]
Description
Test Conditions
48-ball VFBGA 44-pin TSOP II Unit
JA
Thermal resistance
(junction to ambient)
Still air, soldered on a 3 × 4.5 inch,
four-layer printed circuit board
54
57
C/W
JC
Thermal resistance
(junction to case)
12
17
C/W
AC Test Loads and Waveforms
Figure 3. AC Test Loads and Waveforms
R1
ALL INPUT PULSES
VCC
VCC
OUTPUT
90%
10%
90%
10%
GND
R2
Rise Time = 1 V/ns
30 pF
Fall Time = 1 V/ns
INCLUDING
JIG AND
SCOPE
Equivalent to: THÉVENIN EQUIVALENT
RTH
OUTPUT
VTH
Parameters
2.50 V
16667
15385
8000
3.0 V
1103
1554
645
Unit
R1
R2
RTH
VTH
1.20
1.75
V
Note
9. Tested initially and after any design or process changes that may affect these parameters.
Document Number: 38-05569 Rev. *J
Page 5 of 18
CY62136EV30 MoBL®
Data Retention Characteristics
Over the Operating Range
Parameter
VDR
ICCDR
Description
VCC for data retention
Data retention current
Conditions
Min
1.0
–
Typ [10]
Max
–
Unit
V
–
[11]
VCC= 1.0 V, CE > VCC – 0.2 V,
0.8
3
A
VIN > VCC – 0.2 V or VIN < 0.2 V
[12]
tCDR
Chip deselect to data
retention time
0
–
–
–
–
ns
ns
[13]
tR
Operation recovery time
45
Data Retention Waveform
Figure 4. Data Retention Waveform [14]
DATA RETENTION MODE
VCC(min)
VCC(min)
V
> 1.0 V
V
CC
DR
t
t
R
CDR
CE
Notes
10. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V = V
, T = 25 °C.
A
CC
CC(typ.)
11. Chip enable (CE) and byte enables (BHE and BLE) need to be tied to CMOS levels to meet the I
/ I
/ I
specification. Other inputs can be left floating.
SB1 SB2 CCDR
12. Tested initially and after any design or process changes that may affect these parameters.
13. Full device operation requires linear V ramp from V to V
> 100 s or stable at V > 100 s.
CC(min.)
CC
DR
CC(min.)
14. BHE.BLE is the AND of both BHE and BLE. The chip can be deselected by either disabling the chip enable signals or by disabling both BHE and BLE.
Document Number: 38-05569 Rev. *J
Page 6 of 18
CY62136EV30 MoBL®
Switching Characteristics
Over the Operating Range
45 ns
Unit
Parameter [15, 16]
Description
Min
Max
Read Cycle
tRC
Read cycle time
45
–
–
45
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAA
Address to data valid
tOHA
tACE
Data hold from address change
CE LOW to data valid
10
–
45
22
–
tDOE
tLZOE
tHZOE
tLZCE
tHZCE
tPU
OE LOW to data valid
OE LOW to Low Z [17]
OE HIGH to High Z [17, 18]
CE LOW to Low Z [17]
CE HIGH to High Z [17, 18]
–
5
–
18
–
10
–
18
–
CE LOW to power-up
0
tPD
CE HIGH to power-down
BLE/BHE LOW to data valid
BLE/BHE LOW to Low Z [17]
BLE/BHE HIGH to High Z [17, 18]
–
45
22
–
tDBE
–
tLZBE
tHZBE
Write Cycle [19, 20]
tWC
5
–
18
Write cycle time
45
35
35
0
–
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tSCE
CE LOW to write end
tAW
Address setup to write end
Address hold from write end
Address setup to write start
WE pulse width
–
tHA
–
tSA
0
–
tPWE
tBW
35
35
25
0
–
BLE/BHE LOW to write end
Data setup to write end
Data hold from write end
WE LOW to High Z [17, 18]
WE HIGH to Low Z [17]
–
tSD
–
tHD
–
tHZWE
tLZWE
–
18
–
10
Notes
15. Test conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns (1 V/ns) or less, timing reference levels of V
/2, input
CC(typ)
pulse levels of 0 to V
, and output loading of the specified I /I as shown in Figure 3 on page 5.
CC(typ.)
OL OH
16. In an earlier revision of this device, under a specific application condition, READ and WRITE operations were limited to switching of the byte enable and/or chip
enable signals as described in the Application Notes AN13842 and AN66311. However, the issue has been fixed and in production now, and hence, these Application
Notes are no longer applicable. They are available for download on our website as they contain information on the date code of the parts, beyond which the fix has
been in production.
17. At any given temperature and voltage condition, t
is less than t
, t
is less than t
, t
is less than t
, and t
is less than t
for any given
HZCE
LZCE HZBE
LZBE HZOE
LZOE
HZWE
LZWE
device.
18. t
, t
, t
, and t
transitions are measured when the outputs enter a high impedence state.
HZWE
HZOE HZCE HZBE
19. The internal write time of the memory is defined by the overlap of WE, CE = V , BHE and BLE = V . All signals must be ACTIVE to initiate a write and any of these
IL
IL
signals can terminate a write by going INACTIVE. The data input setup and hold timing should be referenced to the edge of the signal that terminates the write.
20. The minimum write pulse for Write Cycle No. 3 (WE Controlled and OE LOW) should be sum of t
and t
.
HZWE
SD
Document Number: 38-05569 Rev. *J
Page 7 of 18
CY62136EV30 MoBL®
Switching Waveforms
Figure 5. Read Cycle 1: Address Transition Controlled [21, 22]
tRC
ADDRESS
tAA
tOHA
PREVIOUS DATA VALID
DATA OUT
DATA VALID
Figure 6. Read Cycle No. 2: OE Controlled [22, 23]
ADDRESS
CE
t
RC
t
PD
HZCE
t
t
ACE
OE
t
HZOE
t
DOE
BHE/BLE
t
LZOE
t
HZBE
t
DBE
t
LZBE
HIGH
IMPEDANCE
HIGH IMPEDANCE
DATA OUT
DATA VALID
t
LZCE
t
PU
V
I
CC
CC
SUPPLY
CURRENT
50%
50%
I
SB
.
Notes
21. The device is continuously selected. OE, CE= V , BHE and/or BLE = V
.
IL
IL
22. WE is HIGH for read cycle.
23. Address valid prior to or coincident with CE and BHE, BLE transition LOW.
Document Number: 38-05569 Rev. *J
Page 8 of 18
CY62136EV30 MoBL®
Switching Waveforms (continued)
Figure 7. Write Cycle No. 1: WE Controlled [24, 25, 26]
t
WC
ADDRESS
CE
tSCE
t
t
HA
AW
t
SA
t
PWE
WE
t
BW
BHE/BLE
OE
t
SD
t
HD
DATAIN
DATA I/O
NOTE27
t
HZOE
Figure 8. Write Cycle No. 2: CE Controlled [24, 25, 26]
t
WC
ADDRESS
CE
t
SCE
tSA
t
t
HA
AW
tPWE
WE
t
BW
BHE/BLE
OE
t
t
SD
HD
DATAIN
DATA I/O
NOTE 27
t
HZOE
Notes
24. The internal write time of the memory is defined by the overlap of WE, CE = V , BHE and BLE = V . All signals must be ACTIVE to initiate a write and any of
IL
IL
these signals can terminate a write by going INACTIVE. The data input setup and hold timing should be referenced to the edge of the signal that terminates
the write.
25. Data I/O is high impedance if OE = V
.
IH
26. If CE goes HIGH simultaneously with WE = V , the output remains in a high impedance state.
IH
27. During this period, the I/Os are in output state and input signals should not be applied.
Document Number: 38-05569 Rev. *J
Page 9 of 18
CY62136EV30 MoBL®
Switching Waveforms (continued)
Figure 9. Write Cycle No. 3: WE Controlled, OE LOW [28, 29]
t
WC
ADDRESS
CE
t
SCE
t
BW
BHE/BLE
t
t
HA
AW
t
SA
t
PWE
WE
t
HD
t
SD
NOTE 30
DATAI/O
DATAIN
t
HZWE
t
LZWE
Figure 10. Write Cycle No. 4: BHE/BLE Controlled, OE LOW [28]
t
WC
ADDRESS
CE
t
SCE
t
t
HA
AW
tBW
BHE/BLE
WE
t
SA
tPWE
tHZWE
tHD
t
SD
DATA I/O
DATAIN
NOTE 30
tLZWE
Notes
28. If CE goes HIGH simultaneously with WE = V , the output remains in a high impedance state.
IH
29. The minimum write cycle pulse width should be equal to the sum of t
and t
.
HZWE
SD
30. During this period, the I/Os are in output state and input signals should not be applied.
Document Number: 38-05569 Rev. *J
Page 10 of 18
CY62136EV30 MoBL®
Truth Table
CE
WE
OE
BHE
BLE
Inputs/Outputs
Mode
Power
H[31]
X
X
X[31]
X[31] High Z
Deselect/power-down
Output disabled
Read
Standby (ISB)
L
L
L
X
H
H
X
L
L
H
L
H
L
L
High Z
Data out (I/O0–I/O15
Active (ICC
Active (ICC
Active (ICC
)
)
)
)
H
Data out (I/O0–I/O7);
I/O8–I/O15 in High Z
Read
L
H
L
L
H
Data Out (I/O8–I/O15);
I/O0–I/O7 in High Z
Read
Active (ICC
)
L
L
L
L
L
H
H
H
L
H
H
H
X
X
L
H
L
L
L
H
L
L
High Z
High Z
High Z
Output disabled
Output disabled
Output disabled
Write
Active (ICC
Active (ICC
Active (ICC
Active (ICC
Active (ICC
)
)
)
)
)
L
Data in (I/O0–I/O15)
L
H
Data in (I/O0–I/O7);
I/O8–I/O15 in High Z
Write
L
L
X
L
H
Data in (I/O8–I/O15);
I/O0–I/O7 in High Z
Write
Active (ICC
)
Note
31. Chip enable (CE) and Byte enables (BHE and BLE) must be at fixed CMOS levels (not floating). Intermediate voltage levels on these pins is not permitted.
Document Number: 38-05569 Rev. *J
Page 11 of 18
CY62136EV30 MoBL®
Ordering Information
Speed
Package
Diagram
Operating
Range
Ordering Code
(ns)
Package Type
45
CY62136EV30LL-45BVXI
CY62136EV30LL-45ZSXI
51-85150 48-ball VFBGA (Pb-free)
51-85087 44-pin TSOP II (Pb-free)
Industrial
Contact your local Cypress sales representative for availability of other parts
Ordering Code Definitions
E V30
6
LL - 45 XX
X
I
3
CY 621
Temperature Grade: I = Industrial
Pb-free
Package Type: XX = BV or ZS
BV = 48-ball VFBGA
ZS = 44-pin TSOP II
Speed Grade: 45 ns
Low Power
Voltage Range: 3 V typical
Process Technology: 90 nm
Bus width: 6 = × 16
Density: 3 = 2-Mbit
Family Code: 621 = MoBL SRAM family
Company ID: CY = Cypress
Document Number: 38-05569 Rev. *J
Page 12 of 18
CY62136EV30 MoBL®
Package Diagrams
Figure 11. 48-ball VFBGA (6 × 8 × 1 mm) BV48/BZ48 Package Outline, 51-85150
51-85150 *H
Document Number: 38-05569 Rev. *J
Page 13 of 18
CY62136EV30 MoBL®
Package Diagrams (continued)
Figure 12. 44-pin TSOP Z44-II Package Outline, 51-85087
51-85087 *E
Document Number: 38-05569 Rev. *J
Page 14 of 18
CY62136EV30 MoBL®
Acronyms
Document Conventions
Units of Measure
Symbol
Acronym
Description
BLE
Byte Low enable
Unit of Measure
BHE
CE
Byte High Enable
Chip Enable
°C
MHz
A
s
mA
mm
ns
degree Celsius
megahertz
microampere
microsecond
milliampere
millimeter
nanosecond
ohm
CMOS
I/O
Complementary Metal Oxide Semiconductor
Input/Output
OE
Output Enable
SRAM
TSOP
VFBGA
WE
Static Random Access Memory
Thin Small Outline Package
Very Fine-Pitch Ball Grid Array
Write Enable
%
percent
pF
V
picofarad
volt
W
watt
Document Number: 38-05569 Rev. *J
Page 15 of 18
CY62136EV30 MoBL®
Document History Page
Document Title: CY62136EV30 MoBL®, 2-Mbit (128K × 16) Static RAM
Document Number: 38-05569
Orig. of
Change
Submission
Date
Rev.
ECN No.
Description of Change
**
237432
419988
AJU
See ECN New data sheet.
*A
RXU
See ECN Changed status from Advanced Information to Final.
Changed the address of Cypress Semiconductor Corporation on Page #1 from
“3901 North First Street” to “198 Champion Court”
Removed 35ns Speed Bin
Removed “L” version of CY62136EV30
Changed ICC (Max) value from 2 mA to 2.5 mA and ICC (Typ) value from 1.5 mA
to 2 mA at f=1 MHz
Changed ICC (Typ) value from 12 mA to 15 mA at f = fmax
Changed ISB1 and ISB2 Typ. values from 0.7 A to 1 A and Max. values from
2.5 A to 7 A.
Changed the AC test load capacitance from 50pF to 30pF on Page# 4
Changed VDR from 1.5V to 1V on Page# 4.
Changed ICCDR from 2.5 A to 3 A.
Added ICCDR typical value.
Changed tOHA , tLZCE and tLZWE from 6 ns to 10 ns
Changed tLZBE from 6 ns to 5 ns
Changed tLZOE from 3 ns to 5 ns
Changed tHZOE, tHZCE, HZBE
t
and tHZWE from 15 ns to 18 ns
Changed tSCE,tAW and BW from 40 ns to 35 ns
t
Changed tPWE from 30 ns to 35 ns
Changed tSD from 20 ns to 25 ns
Corrected typo in the Truth Table on Page# 9
Updated the package diagram 48-pin VFBGA from *B to *D
Updated the ordering Information table and replaced the Package Name
column with Package Diagram.
*B
*C
427817
NXR
See ECN Minor change: Moved datasheet to external web
2604685
VKN /
PYRS
11/12/08
Added footnote 8 related to ISB2 and ICCDR
Added footnote 12 related to AC timing parameters
*D
3144174
RAME
01/17/2011 Added TOC
Added Ordering Code Definitions under Ordering Information.
Updated Package Diagrams:
spec 51-85150 – Changed revision from *D to *F.
Added Acronyms and Units of Measure.
Converted all tablenotes into footnotes.
Updated to new template.
*E
*F
3284728
4102185
AJU
VINI
06/16/2011 Removed the Note “For best practice recommendations, refer to the Cypress
application note “SRAM System Design Guidelines” on
http://www.cypress.com.” in page 1 and its reference in Functional Description.
Updated to new template.
08/22/2013 Updated Switching Characteristics:
Updated Note 16.
Updated Package Diagrams:
spec 51-85150 – Changed revision from *F to *H.
spec 51-85087 – Changed revision from *C to *E.
Updated to new template.
*G
4354908
VINI
04/23/2014 Updated Switching Characteristics:
Added Note 20 and referred the same note in “Write Cycle”.
Updated Switching Waveforms:
Added Note 29 and referred the same note in Figure 9.
Completing Sunset Review.
Document Number: 38-05569 Rev. *J
Page 16 of 18
CY62136EV30 MoBL®
Document History Page (continued)
Document Title: CY62136EV30 MoBL®, 2-Mbit (128K × 16) Static RAM
Document Number: 38-05569
Orig. of
Change
Submission
Date
Rev.
ECN No.
Description of Change
*H
4540616
VINI
10/16/2014 Updated Maximum Ratings:
Referred Notes 4, 5 in “Supply voltage to ground potential”.
Updated Switching Waveforms:
Updated Note 29.
*I
4576475
5734096
VINI
VINI
11/21/2014 Updated Functional Description:
Added “For a complete list of related documentation, click here.” at the end.
*J
05/11/2017 Updated Thermal Resistance:
Updated details in “Test Conditions” column and updated all values in
“48-ball BGA” and “44-pin TSOP II” columns.
Updated to new template.
Completing Sunset Review.
Document Number: 38-05569 Rev. *J
Page 17 of 18
CY62136EV30 MoBL®
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
®
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PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP
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© Cypress Semiconductor Corporation, 2004–2017. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document,
including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other
intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress
hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to
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provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation
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TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
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product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is
the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products
are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or
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Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in
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Document Number: 38-05569 Rev. *J
Revised May 11, 2017
Page 18 of 18
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