CY62146EV30LL-45ZSXI [INFINEON]
Asynchronous SRAM;
| 型号： | CY62146EV30LL-45ZSXI |
| 厂家： | 
Infineon |
| 描述： | Asynchronous SRAM 静态存储器 光电二极管 内存集成电路 |
| 文件： | 总20页 (文件大小：592K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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The document following this cover page is marked as “Cypress” document as this is the
company that originally developed the product. Please note that Infineon will continue
to offer the product to new and existing customers as part of the Infineon product
portfolio.
Continuity of document content
The fact that Infineon offers the following product as part of the Infineon product
portfolio does not lead to any changes to this document. Future revisions will occur
when appropriate, and any changes will be set out on the document history page.
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Infineon continues to support existing part numbers. Please continue to use the
ordering part numbers listed in the datasheet for ordering.
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CY62146EV30 MoBL
4-Mbit (256K × 16) Static RAM
4-Mbit (256K
× 16) Static RAM
advanced circuit design designed to provide an ultra low active
current. Ultra low active current is ideal for providing More
Battery Life™ (MoBL®) in portable applications such as cellular
telephones. The device also has an automatic power down
feature that significantly reduces power consumption by 80
percent when addresses are not toggling.The device can also be
put into standby mode reducing power consumption by more
than 99 percent when deselected (CE HIGH). The input and
output pins (I/O0 through I/O15) are placed in a high impedance
state when the device is deselected (CE HIGH), outputs are
disabled (OE HIGH), both Byte High Enable and Byte Low
Enable are disabled (BHE, BLE HIGH), or a write operation is in
progress (CE LOW and WE LOW).
Features
■ Very high speed: 45 ns
■ Temperature ranges
❐ Industrial: –40 °C to +85 °C
❐ Automotive-A: –40 °C to +85 °C
■ Wide voltage range: 2.20 V to 3.60 V
■ Pin compatible with CY62146DV30
■ Ultra low standby power
❐ Typical standby current: 2.5 A
❐ Maximum standby current: 7 A
To write to the device, take Chip Enable (CE) and Write Enable
(WE) input LOW. If Byte Low Enable (BLE) is LOW, then data
from I/O pins (I/O0 through I/O7) is written into the location
specified on the address pins (A0 through A17). If Byte High
Enable (BHE) is LOW, then data from the I/O pins (I/O8 through
I/O15) is written into the location specified on the address pins
(A0 through A17).
■ Ultra low active power
❐ Typical active current: 3.5 mA at f = 1 MHz
■ Easy memory expansion with CE and OE features
■ Automatic power down when deselected
■ Complementary metal oxide semiconductor (CMOS) for
optimum speed and power
To read from the device, take Chip Enable (CE) and Output
Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If
Byte Low Enable (BLE) is LOW, then data from the memory
location specified by the address pins appears on I/O0 to I/O7. If
Byte High Enable (BHE) is LOW, then data from memory
appears on I/O8 to I/O15. See the Truth Table on page 11 for a
complete description of read and write modes.
■ Available in a Pb-free 48-ball very fine-pitch ball grid array
(VFBGA) and 44-pin TSOP II Packages
Functional Description
The CY62146EV30 is a high performance CMOS static RAM
organized as 256K words by 16 bits. This device features an
For a complete list of related documentation, click here.
Logic Block Diagram
DATA IN DRIVERS
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
256K x 16
RAM Array
I/O0–I/O7
I/O8–I/O15
COLUMN DECODER
BHE
WE
CE
OE
BLE
Cypress Semiconductor Corporation
Document Number: 38-05567 Rev. *O
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised June 26, 2020
CY62146EV30 MoBL
Contents
Pin Configurations ...........................................................3
Product Portfolio ..............................................................3
Maximum Ratings .............................................................4
Operating Range ...............................................................4
Electrical Characteristics .................................................4
Capacitance ......................................................................5
Thermal Resistance ..........................................................5
AC Test Loads and Waveforms .......................................5
Data Retention Characteristics .......................................6
Data Retention Waveform ................................................6
Switching Characteristics ................................................7
Switching Waveforms ......................................................8
Truth Table ......................................................................11
Ordering Information ......................................................12
Ordering Code Definitions .........................................12
Package Diagrams ..........................................................13
Acronyms ........................................................................15
Document Conventions .................................................15
Units of Measure .......................................................15
Document History Page .................................................16
Sales, Solutions, and Legal Information ......................19
Worldwide Sales and Design Support .......................19
Products ....................................................................19
PSoC® Solutions ......................................................19
Cypress Developer Community .................................19
Technical Support .....................................................19
Document Number: 38-05567 Rev. *O
Page 2 of 19
CY62146EV30 MoBL
Pin Configurations
Figure 1. 48-ball VFBGA pinout [1, 2]
Figure 2. 44-pin TSOP II pinout [1]
A
A
A
A
A
7
OE
BHE
BLE
I/O
15
I/O
I/O
13
I/O
1
2
3
4
5
6
1
2
3
4
5
6
7
8
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
4
3
5
6
A
A
A
2
1
A0
A1
A2
NC
A
B
C
OE
BLE
0
A4
A6
A3
A5
I/O8 BHE
CE
I/O0
CE
I/O
I/O
I/O
I/O
0
I/O10
I/O11
I/O1 I/O2
I/O9
VSS
VCC
1
2
3
14
9
10
11
12
13
14
15
16
12
A17
VCC
A7 I/O3
D
E
F
V
V
SS
CC
V
SS
I/O
I/O
I/O
I/O
V
CC
I/O
I/O
I/O
I/O
A16 I/O4 VSS
I/O12 NC
4
11
10
5
A14
6
7
A15
I/O13
I/O5 I/O6
9
I/O14
8
WE 17
NC
A
A12 A13
I/O15 NC
I/O7
NC
WE
G
H
A
A
A
A
A
18
19
20
17
16
15
8
A
9
A
A
A9
A10 A11
A8
NC
10
11
14 21
13 22
A
12
Product Portfolio
Power Dissipation
Operating ICC (mA)
f = 1 MHz f = fmax
VCC Range (V)
Speed
(ns)
Product
Range
Standby ISB2 (A)
Min
2.2
Typ [3] Max
3.0 3.6
Typ [3]
Max
Typ [3]
Max
Typ [3]
Max
CY62146EV30LL
Industrial/
Automotive-A
45
3.5
6
15
20
2.5
7
Notes
1. NC pins are not connected on the die.
2. Pins H1, G2, and H6 in the BGA package are address expansion pins for 8Mb, 16Mb and 32Mb respectively.
3. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V = V
, T = 25 °C.
A
CC
CC(typ)
Document Number: 38-05567 Rev. *O
Page 3 of 19
CY62146EV30 MoBL
DC input voltage [4, 5] ....... –0.3 V to 3.9 V (VCC max + 0.3 V)
Output current into outputs (LOW) ............................. 20 mA
Maximum Ratings
Exceeding the maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Static Discharge Voltage
(per MIL-STD-883, Method 3015) .......................... >2001 V
Storage temperature ............................... –65 °C to + 150 °C
Latch-up Current .................................................... >200 mA
Ambient temperature
with power applied .................................. –55 °C to + 125 °C
Operating Range
Supply voltage
Ambient
[6]
to ground potential ..........–0.3 V to + 3.9 V (VCCmax + 0.3 V)
Device
Range
VCC
Temperature
DC voltage applied to outputs
CY62146EV30 Industrial/ –40 °C to +85 °C 2.2 V to 3.6 V
Automotive-A
in High-Z state [4, 5] ............ –0.3 V to 3.9 V (VCCmax + 0.3 V)
Electrical Characteristics
Over the Operating Range
45 ns (Industrial/Automotive-A)
Parameter
VOH
Description
Output high voltage
Test Conditions
Unit
Min
2.0
2.4
–
Typ [7]
Max
IOH = –0.1 mA
–
–
–
V
V
IOH = –1.0 mA, VCC > 2.70 V
IOL = 0.1 mA
–
0.4
VOL
VIH
VIL
Output low voltage
Input high voltage
Input LOW Voltage
–
V
IOL = 2.1 mA, VCC > 2.70 V
VCC = 2.2 V to 2.7 V
VCC = 2.7 V to 3.6 V
VCC = 2.2 V to 2.7 V
VCC= 2.7 V to 3.6 V
GND < VI < VCC
–
–
0.4
V
1.8
2.2
–0.3
–0.3
–1
–1
–
–
VCC + 0.3
VCC + 0.3
0.6
V
–
V
–
V
–
0.8
V
IIX
Input leakage current
–
+1
A
A
mA
IOZ
ICC
Output leakage current
VCC operating supply current
GND < VO < VCC, Output disabled
–
+1
f = fmax = 1/tRC
f = 1 MHz
VCC = VCC(max)
OUT = 0 mA
CMOS levels
,
15
3.5
20
I
–
6
ISB1
Automatic CE power down
current – CMOS inputs
CE > VCC – 0.2 V,
VIN > VCC – 0.2 V or VIN < 0.2 V,
f = fmax (Address and data only),
–
2.5
7
A
f = 0 (OE, BHE, BLE and WE),
VCC = 3.60 V
[8]
ISB2
Automatic CE power down
current – CMOS inputs
–
2.5
7
A
CE > VCC – 0.2 V,
VIN > VCC – 0.2 V or VIN < 0.2 V,
f = 0, VCC = 3.60 V
Notes
4.
5.
V
V
= –2.0 V for pulse durations less than 20 ns.
IL(min)
= V + 0.75 V for pulse durations less than 20 ns.
IH(max)
CC
6. Full device AC operation assumes a minimum of 100 s ramp time from 0 to V (min) and 200 s wait time after V stabilization.
cc
cc
7. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V = V
, T = 25 °C.
CC
CC(typ)
A
8. Chip enable (CE) and byte enables (BHE and BLE) need to be tied to CMOS levels to meet the I
/I
/I
spec. Other inputs can be left floating.
SB1 SB2 CCDR
Document Number: 38-05567 Rev. *O
Page 4 of 19
CY62146EV30 MoBL
Capacitance
Parameter [9]
Description
Input capacitance
Output capacitance
Test Conditions
Max
10
Unit
pF
CIN
TA = 25 C, f = 1 MHz, VCC = VCC(typ)
COUT
10
pF
Thermal Resistance
Parameter [9]
Description
Test Conditions
VFBGA
TSOP II
Unit
JA
Thermal resistance
(junction to ambient)
Still air, soldered on a 3 × 4.5 inch,
four-layer printed circuit board
42.10
55.52
C/W
JC
Thermal resistance
(junction to case)
23.45
16.03
C/W
AC Test Loads and Waveforms
Figure 3. AC Test Loads and Waveforms
R1
All Input Pulses
90%
VCC
VCC
GND
90%
10%
Output
10%
R2
30 pF
Rise Time = 1 V/ns
Fall Time = 1 V/ns
Including
JIG and
Scope
Equivalent to: Thevenin Equivalent
RTH
Output
VTH
Parameter
R1
2.50 V
3.0 V
1103
1554
645
Unit
16667
15385
8000
1.20
R2
RTH
VTH
1.75
V
Note
9. Tested initially and after any design or process changes that may affect these parameters.
Document Number: 38-05567 Rev. *O
Page 5 of 19
CY62146EV30 MoBL
Data Retention Characteristics
Over the Operating Range
Parameter
VDR
Description
VCC for data retention
Data retention current
Conditions
Min
1.5
–
Typ [10]
Max
–
Unit
V
–
3
[11]
ICCDR
VCC = 1.5 V,
Industrial/
Automotive-A
8.8
A
CE > VCC – 0.2 V,
VIN > VCC – 0.2 V or
VIN < 0.2 V
[12]
tCDR
Chip deselect to data retention
time
–
0
–
–
–
–
ns
ns
[13]
tR
Operation recovery time
–
45
Data Retention Waveform
Figure 4. Data Retention Waveform
DATA RETENTION MODE
VCC(min)
VCC(min)
V
DR
> 1.5 V
VCC
CE
t
t
R
CDR
Notes
10. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V = V
, T = 25 °C.
A
CC
CC(typ)
11. Chip enable (CE) and byte enables (BHE and BLE) need to be tied to CMOS levels to meet the I
12. Tested initially and after any design or process changes that may affect these parameters.
/I
/I
spec. Other inputs can be left floating.
SB1 SB2 CCDR
13. Full device operation requires linear V ramp from V to V
> 100 s or stable at V > 100 s.
CC
DR
CC(min)
CC(min)
Document Number: 38-05567 Rev. *O
Page 6 of 19
CY62146EV30 MoBL
Switching Characteristics
Over the Operating Range
45 ns
Parameter [14, 15]
Description
Unit
(Industrial/Automotive-A)
Min
Max
Read Cycle
tRC
Read cycle time
45
–
–
45
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAA
Address to data valid
tOHA
tACE
Data hold from address change
10
–
45
22
–
CE LOW to data valid
tDOE
tLZOE
tHZOE
tLZCE
tHZCE
tPU
–
OE LOW to data valid
OE LOW to Low-Z [16]
OE HIGH to High-Z [16, 17]
CE LOW to Low-Z [16]
CE HIGH to High-Z [16, 17]
5
–
18
–
10
–
18
–
0
CE LOW to power up
tPD
–
45
22
–
CE HIGH to power down
BLE / BHE LOW to data valid
BLE / BHE LOW to Low-Z [16]
BLE / BHE HIGH to High-Z [16, 17]
tDBE
tLZBE
tHZBE
Write Cycle [18, 19]
tWC
–
5
–
18
Write cycle time
45
35
35
0
–
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tSCE
CE LOW to write end
tAW
Address setup to write end
–
tHA
Address hold from write end
Address setup to write start
–
tSA
0
–
tPWE
tBW
35
35
25
0
–
WE pulse width
–
BLE / BHE LOW to write end
Data setup to write end
tSD
–
tHD
Data hold from write end
–
WE LOW to High-Z [16, 17]
WE HIGH to Low-Z [16]
tHZWE
tLZWE
–
18
–
10
Notes
14. Test conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns (1 V/ns) or less, timing reference levels of V
/2, input
CC(typ)
pulse levels of 0 to V
, and output loading of the specified I /I as shown in the Figure 3 on page 5.
CC(typ)
OL OH
15. In an earlier revision of this device, under a specific application condition, READ and WRITE operations were limited to switching of the byte enable and/or chip
enable signals as described in the Application Notes AN13842 and AN66311. However, the issue has been fixed and in production now, and hence, these Application
Notes are no longer applicable. They are available for download on our website as they contain information on the date code of the parts, beyond which the fix has
been in production.
16. At any given temperature and voltage condition, t
is less than t
, t
is less than t
, t
is less than t
, and t
is less than t
for any given
HZCE
LZCE HZBE
LZBE HZOE
LZOE
HZWE
LZWE
device.
17. t
, t
, t
, and t
transitions are measured when the outputs enter a high impedance state.
HZOE HZCE HZBE
HZWE
18. The internal write time of the memory is defined by the overlap of WE, CE = V , BHE and/or BLE = V . All signals must be ACTIVE to initiate a write and any of
IL
IL
these signals can terminate a write by going INACTIVE. The data input setup and hold timing must be referenced to the edge of the signal that terminates the write
19. The minimum write pulse width for Write Cycle No. 3 (WE Controlled, OE LOW) should be sum of t
and t
.
HZWE
SD
Document Number: 38-05567 Rev. *O
Page 7 of 19
CY62146EV30 MoBL
Switching Waveforms
Figure 5. Read Cycle 1 (Address Transition Controlled) [20, 21]
tRC
ADDRESS
tAA
tOHA
PREVIOUS DATA VALID
DATAOUT VALID
DATA I/O
Figure 6. Read Cycle No. 2 (OE Controlled) [21, 22]
ADDRESS
CE
t
RC
t
PD
HZCE
t
t
ACE
OE
t
HZOE
t
DOE
t
LZOE
BHE/BLE
t
HZBE
t
DBE
t
LZBE
HIGH
IMPEDANCE
HIGHIMPEDANCE
DATAOUT VALID
DATA I/O
t
LZCE
t
PU
V
50%
50%
CC
I
SUPPLY
SB
CURRENT
Notes
20. The device is continuously selected. OE, CE = V , BHE and/or BLE = V
.
IL
IL
21. WE is HIGH for read cycle.
22. Address valid before or similar to CE and BHE, BLE transition LOW.
Document Number: 38-05567 Rev. *O
Page 8 of 19
CY62146EV30 MoBL
Switching Waveforms (continued)
Figure 7. Write Cycle No. 1 (WE Controlled) [23, 24, 25]
t
WC
ADDRESS
CE
tSCE
t
t
HA
AW
t
SA
t
PWE
WE
t
BW
BHE/BLE
OE
t
HD
t
SD
NOTE 26
DATAIN
DATA I/O
t
HZOE
Figure 8. Write Cycle No. 2 (CE Controlled) [23, 24, 25]
t
WC
ADDRESS
CE
t
SCE
tSA
t
t
HA
AW
tPWE
WE
t
BW
BHE/BLE
OE
t
t
SD
HD
DATAIN
DATA I/O
NOTE 26
t
HZOE
Notes
23. The internal write time of the memory is defined by the overlap of WE, CE = V , BHE and/or BLE = V . All signals must be ACTIVE to initiate a write and any of these
IL
IL
signals can terminate a write by going INACTIVE. The data input setup and hold timing must be referenced to the edge of the signal that terminates the write.
24. Data I/O is high impedance if OE = V
.
IH
25. If CE goes HIGH simultaneously with WE = V , the output remains in a high impedance state.
IH
26. During this period, the I/Os are in output state and input signals must not be applied.
Document Number: 38-05567 Rev. *O
Page 9 of 19
CY62146EV30 MoBL
Switching Waveforms (continued)
Figure 9. Write Cycle No. 3 (WE Controlled, OE LOW) [27, 28]
t
WC
ADDRESS
CE
t
SCE
t
BW
BHE/BLE
t
t
HA
AW
t
SA
t
PWE
WE
t
HD
t
SD
DATA I/O
NOTE 29
DATAIN
t
LZWE
t
HZWE
Figure 10. Write Cycle No. 4 (BHE/BLE Controlled, OE LOW) [27]
t
WC
ADDRESS
CE
t
SCE
t
t
HA
AW
tBW
BHE/BLE
WE
t
SA
tPWE
tHZWE
t
HD
t
SD
NOTE 29
DATAIN
DATA I/O
tLZWE
Notes
27. If CE goes HIGH simultaneously with WE = V , the output remains in a high impedance state.
IH
28. The minimum write pulse width for Write Cycle No. 3 (WE Controlled, OE LOW) should be sum of t
29. During this period, the I/Os are in output state and input signals must not be applied.
and t
.
SD
HZWE
Document Number: 38-05567 Rev. *O
Page 10 of 19
CY62146EV30 MoBL
Truth Table
CE [30]
WE
X
OE
X
BHE
X
BLE
X
Inputs/Outputs
High-Z
Mode
Power
H
L
L
L
Deselect/power-down
Output disabled
Read
Standby (ISB
Active (ICC
Active (ICC
Active (ICC
)
X
X
H
H
High-Z
)
H
L
L
L
Data out (I/O0–I/O15
)
)
H
L
H
L
Data out (I/O0–I/O7);
I/O8–I/O15 in High-Z
Read
)
L
H
L
L
H
Data out (I/O8–I/O15);
I/O0–I/O7 in High-Z
Read
Active (ICC)
L
L
L
L
L
H
H
H
L
H
H
H
X
X
L
H
L
L
L
H
L
L
High-Z
High-Z
High-Z
Output disabled
Output disabled
Output disabled
Write
Active (ICC
Active (ICC
Active (ICC
Active (ICC
Active (ICC
)
)
)
L
Data in (I/O0–I/O15
)
)
L
H
Data in (I/O0–I/O7);
I/O8–I/O15 in High-Z
Write
)
L
L
X
L
H
Data in (I/O8–I/O15);
I/O0–I/O7 in High-Z
Write
Active (ICC)
Note
30. Chip enable must be at CMOS levels (not floating). Intermediate voltage levels on this pin is not permitted.
Document Number: 38-05567 Rev. *O
Page 11 of 19
CY62146EV30 MoBL
Ordering Information
Speed
Package
Diagram
Operating
Range
Package Type
(ns)
Ordering Code
CY62146EV30LL-45BVXI
CY62146EV30LL-45ZSXI
45
51-85150 48-ball VFBGA (Pb-free)
51-85087 44-pin TSOP II (Pb-free)
Industrial
Please contact your local Cypress sales representative for availability of other parts
Ordering Code Definitions
E
- 45 XX
V30 LL
X
X
4
621
CY
6
Temperature Grade: X = I
I = Industrial
Pb-free
Package Type: XX = BV or ZS
BV = VFBGA; ZS = TSOP II
Speed Grade: 45 ns
LL = Low Power
Voltage Range: V30 = 3 V typical
Process Technology: E = 90 nm
Bus Width: 6 = × 16
Density: 4 = 4-Mbit
Family Code: MoBL SRAM family
Company ID: CY = Cypress
Document Number: 38-05567 Rev. *O
Page 12 of 19
CY62146EV30 MoBL
Package Diagrams
Figure 11. 48-ball VFBGA (6 × 8 × 1.0 mm) Package Outline, 51-85150
51-85150 *I
Document Number: 38-05567 Rev. *O
Page 13 of 19
CY62146EV30 MoBL
Package Diagrams (continued)
Figure 12. 44-pin TSOP II (18.4 × 10.2 × 1.194 mm) Package Outline, 51-85087
51-85087 *F
Document Number: 38-05567 Rev. *O
Page 14 of 19
CY62146EV30 MoBL
Acronyms
Document Conventions
Units of Measure
Symbol
Acronym
Description
BHE
BLE
Byte High Enable
Byte Low Enable
Unit of Measure
°C
MHz
A
mA
ns
degree Celsius
megahertz
microampere
milliampere
nanosecond
ohm
CMOS
CE
Complementary Metal Oxide Semiconductor
Chip Enable
I/O
Input/Output
OE
Output Enable
SRAM
TSOP
VFBGA
WE
Static Random Access Memory
Thin Small Outline Package
Very Fine-Pitch Ball Gird Array
Write Enable
pF
V
picofarad
volt
W
watt
Document Number: 38-05567 Rev. *O
Page 15 of 19
CY62146EV30 MoBL
Document History Page
Document Title: CY62146EV30 MoBL, 4-Mbit (256K × 16) Static RAM
Document Number: 38-05567
Submission
Rev.
ECN No.
Description of Change
Date
**
223225
247373
05/05/2004 New data sheet.
*A
07/28/2004 Changed status from Advance Information to Preliminary.
Updated Operating Range:
Updated Note 6 (Replaced “100 s wait time” with “200 s wait time”).
Updated Data Retention Characteristics:
Changed maximum value of ICCDR parameter from 2.0 A to 2.5 A.
Changed minimum value of tR parameter from 100 s to tRC ns.
Updated Switching Characteristics:
Changed minimum value of tOHA parameter from 6 ns to 10 ns corresponding to both 35 ns
and 45 ns speed bin.
Changed maximum value of tDOE parameter from 15 ns to 18 ns corresponding to 35 ns
speed bin.
Changed maximum value of tHZOE, tHZBE, and tHZWE parameters from 12 ns to 15 ns
corresponding 35 ns speed bin and from 15 ns to 18 ns corresponding to 45 ns speed bin.
Changed maximum value of tHZCE parameter from 12 ns to 18 ns corresponding to 35 ns
speed bin and from 15 ns to 22 ns corresponding to 45 ns speed bin.
Changed maximum value of tDBE parameter from 15 ns to 18 ns corresponding to 35 ns
speed bin.
Changed minimum value of tSCE and tBW parameters from 25 to 30 ns corresponding to
35 ns speed bin and from 40 ns to 35 ns corresponding to 45 ns speed bin.
Changed minimum value of tSD parameter from 15 ns to 18 ns corresponding to 35 ns speed
bin and from 20 ns to 22 ns corresponding to 45 ns speed bin.
Removed Note “If both Byte Enables (BHE and BLE) are toggled together then this value
is 6 ns min. Otherwise this value is 3 ns min.” and its reference in tLZBE parameter.
Updated Ordering Information:
Updated part numbers.
*B
414807
12/16/2005 Changed status from Preliminary to Final.
Removed “L” version of CY62146EV30 part in all instances across the document.
Removed 35 ns speed bin related information in all instances across the document.
Changed the address of Cypress Semiconductor Corporation in Page 1 from “3901 North
First Street” to “198 Champion Court”.
Updated Pin Configurations:
Updated Figure 1 (Replaced DNU with NC corresponding to ball E3).
Removed Note “DNU pins have to be left floating or tied to VSS to ensure proper application.”
and its reference.
Updated Electrical Characteristics:
Changed typical value of ICC parameter from 12 mA to 15 mA corresponding to 45 ns speed
bin and Test Condition “f = fmax”.
Changed typical value of ICC parameter from 1.5 mA to 2 mA corresponding to 45 ns speed
bin and Test Condition “f = 1 MHz”.
Changed maximum value of ICC parameter from 2 mA to 2.5 mA corresponding to 45 ns
speed bin and Test Condition “f = 1 MHz”.
Changed typical value of ISB1 parameter from 0.7 A to 1 A corresponding to 45 ns speed
bin.
Changed maximum value of ISB1 parameter from 2.5 A to 7 A corresponding to 45 ns
speed bin.
Changed typical value of ISB2 parameter from 0.7 A to 1 A corresponding to 45 ns speed
bin.
Changed maximum value of ISB2 parameter from 2.5 A to 7 A corresponding to 45 ns
speed bin.
Updated AC Test Loads and Waveforms:
Updated Figure 3 (Replaced 50 pF with 30 pF).
Document Number: 38-05567 Rev. *O
Page 16 of 19
CY62146EV30 MoBL
Document History Page (continued)
Document Title: CY62146EV30 MoBL, 4-Mbit (256K × 16) Static RAM
Document Number: 38-05567
Submission
Rev.
ECN No.
Description of Change
Date
*B (cont.)
414807
12/16/2005 Updated Data Retention Characteristics:
Changed maximum value of ICCDR parameter from 2.5 A to 7 A.
Added typical value of ICCDR parameter.
Updated Switching Characteristics:
Changed minimum value of tLZOE parameter from 3 ns to 5 ns corresponding to 45 ns speed
bin.
Changed minimum value of tLZCE parameter from 6 ns to 10 ns corresponding to 45 ns
speed bin.
Changed maximum value of tHZCE parameter from 22 ns to 18 ns corresponding to 45 ns
speed bin.
Changed minimum value of tLZBE parameter from 6 ns to 5 ns corresponding to 45 ns speed
bin.
Changed minimum value of tPWE parameter from 30 ns to 35 ns corresponding to 45 ns
speed bin.
Changed minimum value of tSD parameter from 22 ns to 25 ns corresponding to 45 ns speed
bin.
Changed minimum value of tLZWE parameter from 6 ns to 10 ns corresponding to 45 ns
speed bin.
Updated Ordering Information:
Updated part numbers.
Removed “Package Name” column.
Added “Package Diagram” column.
Updated Package Diagrams:
spec 51-85150 – Changed revision from *B to *D.
Updated to new template.
*C
925501
04/09/2007 Updated Electrical Characteristics:
Added Note 8 and referred the same note in ISB2 parameter.
Updated Data Retention Characteristics:
Added Note 11 and referred the same note in ICCDR parameter.
Updated Switching Characteristics:
Added Note 15 and referred the same note in “Parameter” column.
*D
*E
2678796
2944332
03/25/2009 Added Automotive-A Temperature Range related information in all instances across the
document.
Completing Sunset Review.
06/04/2010 Updated Truth Table:
Added Note 30 and referred the same note in “CE” column.
Updated Package Diagrams:
spec 51-85150 – Changed revision from *D to *E.
spec 51-85087 – Changed revision from *A to *C.
Updated to new template.
*F
3109050
3302915
12/13/2010 Changed all Table Footnotes to Notes in all instances across the document.
Updated Ordering Information:
No change in part numbers.
Added Ordering Code Definitions.
Updated Package Diagrams:
spec 51-85150 – Changed revision from *E to *F.
*G
07/14/2011 Updated Functional Description:
Removed “For best practice recommendations, refer to the Cypress application note
AN1064, SRAM System Guidelines.” at the end.
Updated Ordering Information:
No change in part numbers.
Updated Ordering Code Definitions.
Added Units of Measure.
Updated to new template.
Document Number: 38-05567 Rev. *O
Page 17 of 19
CY62146EV30 MoBL
Document History Page (continued)
Document Title: CY62146EV30 MoBL, 4-Mbit (256K × 16) Static RAM
Document Number: 38-05567
Submission
Rev.
ECN No.
Description of Change
Date
*H
3961126
04/10/2013 Updated Package Diagrams:
spec 51-85150 – Changed revision from *F to *H.
spec 51-85087 – Changed revision from *C to *E.
Completing Sunset Review.
*I
4101995
4348752
08/22/2013 Updated Switching Characteristics:
Updated Note 15.
Updated to new template.
*J
04/16/2014 Updated Switching Characteristics:
Added Note 19 and referred the same note in “Write Cycle”.
Updated Switching Waveforms:
Added Note 28 and referred the same note in Figure 9 (for tPWE parameter in WEControlled,
OE LOW Write Cycle).
Completing Sunset Review.
*K
*L
4576526
5233278
11/21/2014 Updated Functional Description:
Added “For a complete list of related documentation, click here.” at the end.
04/21/2016 Updated Thermal Resistance:
Replaced “two-layer” with “four-layer” in “Test Conditions” column.
Updated all values in “VFBGA” and “TSOP II” columns.
Updated to new template.
Completing Sunset Review.
*M
*N
6029183
6560465
01/12/2018 Updated Ordering Information:
Updated part numbers.
Updated to new template.
04/29/2019 Updated Package Diagrams:
spec 51-85150 – Changed revision from *H to *I.
Updated to new template.
Completing Sunset Review.
*O
6906316
06/26/2020 Updated Features:
Changed value of Typical standby current from 1 µA to 2.5 µA.
Changed value of Typical active current from 2 mA to 3.5 mA.
Updated Product Portfolio:
Changed typical value of Operating ICC from 2 mA to 3.5 mA corresponding to “f = 1 MHz”.
Changed maximum value of Operating ICC from 2.5 mA to 6 mA corresponding to
“f = 1 MHz”.
Changed typical value of Standby, ISB2 from 1 µA to 2.5 µA.
Updated Electrical Characteristics:
Changed typical value of ICC parameter from 2 mA to 3.5 mA corresponding to Test
Condition “f = 1 MHz”.
Changed maximum value of ICC parameter from 2.5 mA to 6 mA corresponding to Test
Condition “f = 1 MHz”.
Changed typical value of ISB1 parameter from 1 µA to 2.5 µA.
Changed typical value of ISB2 parameter from 1 µA to 2.5 µA.
Updated Data Retention Characteristics:
Changed typical value of ICCDR parameter from 0.8 μA to 3 μA.
Changed maximum value of ICCDR parameter from 7 µA to 8.8 µA.
Updated Package Diagrams:
spec 51-85087 – Changed revision from *E to *F.
Updated to new template.
Document Number: 38-05567 Rev. *O
Page 18 of 19
CY62146EV30 MoBL
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© Cypress Semiconductor Corporation, 2004–2020. This document is the property of Cypress Semiconductor Corporation and its subsidiaries (“Cypress”). This document, including any software or
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Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in
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Document Number: 38-05567 Rev. *O
Revised June 26, 2020
Page 19 of 19
MoBL is a registered trademark, and More Battery Life is a trademark of Cypress Semiconductor Corporation.
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