CY62148EV30LL-55SXIT [INFINEON]
Asynchronous SRAM;
| 型号： | CY62148EV30LL-55SXIT |
| 厂家： | 
Infineon |
| 描述： | Asynchronous SRAM 静态存储器 |
| 文件： | 总21页 (文件大小：860K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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company that originally developed the product. Please note that Infineon will continue
to offer the product to new and existing customers as part of the Infineon product
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Continuity of document content
The fact that Infineon offers the following product as part of the Infineon product
portfolio does not lead to any changes to this document. Future revisions will occur
when appropriate, and any changes will be set out on the document history page.
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Infineon continues to support existing part numbers. Please continue to use the
ordering part numbers listed in the datasheet for ordering.
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CY62148EV30 MoBL
4-Mbit (512K × 8) Static RAM
4-Mbit (512K
× 8) Static RAM
Features
Functional Description
■ Very high speed: 45 ns
❐ Wide voltage range: 2.20 V to 3.60 V
The CY62148EV30 is a high performance CMOS static RAM
organized as 512K words by 8 bits. This device features
advanced circuit design to provide ultra low active current. This
is ideal for providing More Battery Life™ (MoBL®) in portable
applications such as cellular telephones. The device also has an
automatic power down feature that significantly reduces power
consumption. Placing the device into standby mode reduces
power consumption by more than 99 percent when deselected
(CE HIGH). The eight input and output pins (I/O0 through I/O7)
are placed in a high impedance state when the device is
deselected (CE HIGH), the outputs are disabled (OE HIGH), or
during a write operation (CE LOW and WE LOW).
■ Temperature range:
❐ Industrial: –40 °C to +85 °C
❐ Automotive-A: –40 °C to +85 °C
■ Pin compatible with CY62148DV30
■ Ultra low standby power
❐ Typical standby current: 2.5 A
❐ Maximum standby current: 7 A (Industrial)
■ Ultra low active power
❐ Typical active current: 3.5 mA at f = 1 MHz
To write to the device, take Chip Enable (CE) and Write Enable
(WE) inputs LOW. Data on the eight I/O pins (I/O0 through I/O7)
is then written into the location specified on the address pins (A0
through A18).
■ Easy memory expansion with CE and OE features
■ Automatic power down when deselected
To read from the device, take Chip Enable (CE) and Output
Enable (OE) LOW while forcing Write Enable (WE) HIGH. Under
these conditions, the contents of the memory location specified
by the address pins appear on the I/O pins.
■ Complementary metal oxide semiconductor (CMOS) for
optimum speed and power
■ Available in Pb-free 36-ball very fine-pitch ball grid array
(VFBGA), 32-pin thin small outline package (TSOP) II, and
32-pin small outline integrated circuit (SOIC)[1] packages
For a complete list of related 1documentation, click here.
Logic Block Diagram
I/O
0
1
2
3
4
5
6
7
A
0
INPUT BUFFER
A
1
I/O
A
2
A
3
I/O
A
4
A
5
I/O
A
6
512K x 8
ARRAY
A
A
A
A
A
A
7
I/O
8
9
I/O
10
11
12
I/O
I/O
CE
POWER
DOWN
COLUMN DECODER
WE
OE
Note
1. SOIC package is available only in 55 ns speed bin.
Cypress Semiconductor Corporation
Document Number: 38-05576 Rev. *X
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised June 26, 2020
CY62148EV30 MoBL
Contents
Pin Configurations ...........................................................3
Product Portfolio ..............................................................3
Maximum Ratings .............................................................4
Operating Range ...............................................................4
Electrical Characteristics .................................................4
Capacitance ......................................................................5
Thermal Resistance ..........................................................5
AC Test Loads and Waveforms .......................................5
Data Retention Characteristics .......................................6
Data Retention Waveform ................................................6
Switching Characteristics ................................................7
Switching Waveforms ......................................................8
Truth Table ......................................................................10
Ordering Information ......................................................11
Ordering Code Definitions .........................................11
Package Diagrams ..........................................................12
Acronyms ........................................................................15
Document Conventions .................................................15
Units of Measure .......................................................15
Document History Page .................................................16
Sales, Solutions, and Legal Information ......................20
Worldwide Sales and Design Support .......................20
Products ....................................................................20
PSoC® Solutions ......................................................20
Cypress Developer Community .................................20
Technical Support .....................................................20
Document Number: 38-05576 Rev. *X
Page 2 of 20
CY62148EV30 MoBL
Pin Configurations
VFBGA, SOIC and TSOP II pinouts are as follows. [2, 3]
36-ball VFBGA pinout
Top View
32-pin SOIC/TSOP II pinout
Top View
VCC
A
A
A
1
2
17
16
14
12
7
6
5
4
3
2
1
0
0
1
2
32
31
30
29
28
27
26
25
24
23
22
A
15
A
A
A8
A1
A2
NC
A0
6
A
B
C
3
A
18
3
A
4
WE
A
A
A
A
A
A
A
A
I/O
I/O
I/O
A
8
5
A
13
I/O
WE
NC
A7
I/O
0
4
4
A
6
A
9
7
A
A
11
I/O
I/O
1
8
9
10
5
5
OE
A
10
V
V
cc
D
E
F
SS
11
12
13
14
15
16
CE
21
20
19
18
17
I/O
I/O
I/O
I/O
I/O
7
6
5
4
3
Vss
I/O
V
CC
VSS
A18
CE
A
17
I/O
6
2
A
G
H
I/O
I/O
OE
A15
16
7
3
A
A
A
A
A9
A14
12
11
13
10
Product Portfolio
Power Dissipation
Operating ICC (mA)
f = 1 MHz f = fmax
Speed
(ns)
VCC Range (V)
Standby ISB2
(µA)
Product
Range
Min
Typ [4] Max
Typ [4] Max Typ [4] Max Typ [4] Max
CY62148EV30LL VFBGA
TSOP II
Industrial
2.2
3.0
3.6
45
55
3.5
6
15
20
2.5
7
Industrial /
Automotive-A
SOIC
Industrial
2.2
3.0
3.6
3.5
6
15
20
2.5
7
Notes
2. SOIC package is available only in 55 ns speed bin.
3. NC pins are not connected on the die.
4. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V = V
, T = 25 °C.
A
CC
CC(typ)
Document Number: 38-05576 Rev. *X
Page 3 of 20
CY62148EV30 MoBL
DC input voltage [5, 6] ...................–0.3 V to VCC(max) + 0.3 V
Output current into outputs (LOW) ............................. 20 mA
Maximum Ratings
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Static discharge voltage
(MIL-STD-883, Method 3015) ................................ > 2001 V
Storage temperature ................................ –65 °C to +150 °C
Latch up current .....................................................> 200 mA
Ambient temperature
with power applied ..................................... 55 °C to +125 °C
Operating Range
Supply voltage
Ambient
[7]
to ground potential .......................–0.3 V to VCC(max) + 0.3 V
Product
Range
VCC
Temperature
DC voltage applied to outputs
CY62148EV30
Industrial/ –40 °C to +85 °C 2.2 V to 3.6 V
Automotive-A
in High Z State [5, 6] ......................–0.3 V to VCC(max) + 0.3 V
Electrical Characteristics
Over the Operating Range
-45 (Industrial /
Automotive-A)
-55 [8]
Min Typ [9]
Parameter
Description
Test Conditions
Unit
Min Typ [9]
Max
–
Max
VOH
Output high voltage IOH = –0.1 mA
2.0
2.4
–
–
–
–
–
–
–
–
2.0
2.4
–
–
–
–
–
–
–
–
–
V
V
V
V
V
V
V
I
OH = –1.0 mA, VCC > 2.70 V
–
–
0.2
VOL
VIH
VIL
Output low voltage IOL = 0.1 mA
0.4
0.4
I
OL = 2.1 mA, VCC > 2.70 V
–
–
0.4
Input high voltage
Input low voltage
VCC = 2.2 V to 2.7 V
VCC = 2.7 V to 3.6 V
1.8
2.2
–0.3
VCC + 0.3 1.8
VCC + 0.3 2.2
VCC + 0.3
VCC + 0.3
–
V
= 2.2 V to 2.7 V For VFBGA and
TSOP II packages
0.6
–
CC
CC
For SOIC package
–
–
–
–
–0.3
–
–
–
0.4 [10]
–
V
V
V
= 2.7 V to 3.6 V For VFBGA and
TSOP II packages
–0.3
0.8
For SOIC package
–
–
–
–
–0.3
–1
–
–
0.6 [10]
+1
IIX
Input leakage
current
GND < VI < VC
–1
+1
A
A
IOZ
ICC
Output leakage
current
GND < VO < VCC, Output disabled
–1
–
+1
–1
–
+1
VCC operating
supply current
f = fmax = 1/tRC
f = 1 MHz
VCC = VCC(max)
IOUT = 0 mA,
CMOS levels
,
–
–
15
20
6
–
–
15
20
6
mA
3.5
3.5
[11]
ISB1
AutomaticCEpower CE > VCC – 0.2 V,
–
2.5
2.5
7
–
2.5
2.5
7
A
A
down current –
CMOS inputs
VIN > VCC – 0.2 V, VIN < 0.2 V,
f = fmax (Address and Data Only),
f = 0 (OE and WE), VCC = 3.60 V
[11]
ISB2
AutomaticCEpower CE > VCC – 0.2 V,
–
7
–
7
down current –
CMOS inputs
V
IN > VCC – 0.2 V or VIN < 0.2 V,
f = 0, VCC = 3.60 V
Notes
5.
6.
V
V
= –2.0 V for pulse durations less than 20 ns.
IL(min)
= V + 0.75 V for pulse durations less than 20 ns.
IH(max)
CC
7. Full device AC operation assumes a minimum of 100 s ramp time from 0 to V
8. SOIC package is available only in 55 ns speed bin.
and 200 s wait time after V stabilization.
CC
CC(min)
9. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V = V
, T = 25 °C.
A
CC
CC(typ)
10. Under DC conditions the device meets a V of 0.8V (for V range of 2.7 V to 3.6 V) and 0.6 V (for V range of 2.2 V to 2.7 V). However, in dynamic conditions
IL
CC
CC
Input LOW voltage applied to the device must not be higher than 0.6V and 0.4V for the above ranges. This is applicable to SOIC package only.
11. Chip Enable (CE) must be HIGH at CMOS level to meet the I
/ I
/ I
spec. Other inputs can be left floating.
SB1 SB2 CCDR
Document Number: 38-05576 Rev. *X
Page 4 of 20
CY62148EV30 MoBL
Capacitance
Parameter [12]
Description
Input capacitance
Output capacitance
Test Conditions
TA = 25 °C, f = 1 MHz, VCC = VCC(typ)
Max
10
Unit
pF
CIN
COUT
10
pF
Thermal Resistance
36-ballVFBGA 32-pin TSOP II 32-pin SOIC
Parameter [12]
Description
Test Conditions
Unit
Package
Package
Package
JA
Thermal resistance
(junction to ambient)
Still air, soldered on
3 × 4.5 inch, four-layer printed
a
44.79
59.10
51.57
C/W
circuit board
JC
Thermal resistance
(junction to case)
23.17
12.19
25.01
C/W
AC Test Loads and Waveforms
Figure 1. AC Test Loads and Waveforms
R1
ALL INPUT PULSES
VCC
OUTPUT
VCC
90%
10%
90%
10%
R2
GND
Rise Time = 1 V/ns
30 pF
Fall Time = 1 V/ns
INCLUDING
JIG AND
SCOPE
Equivalent to:
THEVENIN EQUIVALENT
RTH
TH
OUTPUT
V
Parameter
2.50 V
16667
15385
8000
3.0 V
1103
1554
645
Unit
R1
R2
V
RTH
VTH
1.20
1.75
Note
12. Tested initially and after any design or process changes that may affect these parameters.
Document Number: 38-05576 Rev. *X
Page 5 of 20
CY62148EV30 MoBL
Data Retention Characteristics
Over the Operating Range
Parameter
VDR
ICCDR
Description
Conditions
Min
1.5
–
Typ [13]
Max
–
Unit
V
VCC for data retention
–
3
[14]
Data retention current VCC = 1.5 V,
Industrial/
Automotive-A
8.8
A
CE > VCC – 0.2 V,
VIN > VCC – 0.2 V or
IN < 0.2 V
V
[15]
tCDR
Chip deselect to data
retention time
0
–
–
ns
[16]
tR
Operation recovery time
CY62148EV30LL-45
CY62148EV30LL-55
45
55
–
–
–
–
ns
ns
Data Retention Waveform
Figure 2. Data Retention Waveform
DATA RETENTION MODE
V
V
CC(min)
V
> 1.5 V
CC(min)
V
DR
CC
t
t
CDR
R
CE
Notes
13. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V = V
, T = 25 °C.
A
CC
CC(typ)
14. Chip Enable (CE) must be HIGH at CMOS level to meet the I
/ I
/ I
spec. Other inputs can be left floating.
SB1 SB2 CCDR
15. Tested initially and after any design or process changes that may affect these parameters.
16. Full device AC operation requires linear V ramp from V to V > 100 s or stable at V > 100 s.
CC(min)
CC
DR
CC(min)
Document Number: 38-05576 Rev. *X
Page 6 of 20
CY62148EV30 MoBL
Switching Characteristics
Over the Operating Range
-45 (Industrial /
Automotive-A)
-55 [19]
Parameter [17, 18]
Description
Unit
Min
Max
Min
Max
Read Cycle
tRC
Read cycle time
45
–
–
45
–
55
–
–
55
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAA
Address to data valid
tOHA
Data hold from address change
CE LOW to data valid
10
–
10
–
tACE
45
22
–
55
25
–
tDOE
OE LOW to data valid
–
–
tLZOE
OE LOW to Low Z [20]
OE HIGH to High Z [20, 21]
CE LOW to Low Z [20]
5
5
tHZOE
–
18
–
–
20
–
tLZCE
10
–
10
–
tHZCE
CE HIGH to High Z [20, 21]
18
–
20
–
tPU
CE LOW to power-up
0
0
tPD
CE HIGH to power-down
–
45
–
55
Write Cycle [22, 23]
tWC
Write cycle time
45
35
35
0
–
–
55
40
40
0
–
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tSCE
tAW
CE LOW to write end
Address setup to write end
Address hold from write end
Address setup to write start
WE pulse width
–
–
tHA
–
–
tSA
0
–
0
–
tPWE
tSD
35
25
0
–
40
25
0
–
Data setup to write end
Data hold from write end
WE LOW to High Z [20, 21]
WE HIGH to Low Z [20]
–
–
tHD
–
–
tHZWE
tLZWE
–
18
–
–
20
–
10
10
Notes
17. In an earlier revision of this device, under a specific application condition, READ and WRITE operations were limited to switching of the chip enable signal as described
in the Application Note AN66311. However, the issue has been fixed and in production now, and hence, this Application Note is no longer applicable. It is available
for download on our website as it contains information on the date code of the parts, beyond which the fix has been in production.
18. Test Conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns or less (1 V/ns), timing reference levels of V
/2, input
CC(typ)
pulse levels of 0 to V
, and output loading of the specified I /I as shown in the Figure 1 on page 5.
CC(typ)
OL OH
19. SOIC package is available only in 55 ns speed bin.
20. At any given temperature and voltage condition, t
is less than t
, t
is less than t
, and t
is less than t
for any given device.
LZWE
HZCE
LZCE HZOE
LZOE
HZWE
21. t
, t
, and t
transitions are measured when the output enter a high impedance state.
HZOE HZCE
HZWE
22. The internal write time of the memory is defined by the overlap of WE, CE = V . All signals must be ACTIVE to initiate a write and any of these signals can terminate
IL
a write by going INACTIVE. The data input setup and hold timing must be referenced to the edge of the signal that terminates the write.
23. The minimum write cycle pulse width for Write Cycle No. 3 (WE Controlled, OE LOW) should be equal to the sum of tSD and tHZWE.
Document Number: 38-05576 Rev. *X
Page 7 of 20
CY62148EV30 MoBL
Switching Waveforms
Figure 3. Read Cycle No. 1 (Address Transition Controlled) [24, 25]
tRC
ADDRESS
t
AA
t
OHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
Figure 4. Read Cycle No. 2 (OE Controlled) [25, 26]
ADDRESS
CE
t
RC
t
ACE
OE
t
HZOE
t
DOE
t
HZCE
t
LZOE
HIGH
IMPEDANCE
HIGH IMPEDANCE
DATA VALID
DATA OUT
t
LZCE
t
PD
ICC
t
V
CC
PU
50%
SUPPLY
CURRENT
50%
ISB
Figure 5. Write Cycle No. 1 (WE Controlled, OE HIGH During Write) [27, 28]
t
WC
ADDRESS
CE
t
SCE
t
t
HA
AW
t
SA
t
PWE
WE
OE
t
t
SD
HD
29
DATA I/O
NOTE
DATA VALID
t
HZOE
Notes
24. Device is continuously selected. OE, CE = V .
IL
25. WE is HIGH for read cycles.
26. Address valid before or similar to CE transition LOW.
27. Data I/O is high impedance if OE = V
.
IH
28. If CE goes HIGH simultaneously with WE HIGH, the output remains in high impedance state.
29. During this period, the I/Os are in output state. Do not apply input signals.
Document Number: 38-05576 Rev. *X
Page 8 of 20
CY62148EV30 MoBL
Switching Waveforms (continued)
Figure 6. Write Cycle No. 2 (CE Controlled) [30, 31]
t
WC
ADDRESS
CE
t
SCE
t
SA
t
t
HA
AW
t
PWE
WE
t
t
HD
SD
DATA I/O
DATA VALID
Figure 7. Write Cycle No. 3 (WE Controlled, OE LOW) [31, 32]
t
WC
ADDRESS
CE
t
SCE
t
t
HA
AW
t
SA
t
PWE
WE
t
t
HD
SD
33
NOTE
DATA VALID
DATA I/O
t
t
LZWE
HZWE
Notes
30. Data I/O is high impedance if OE = V
.
IH
31. If CE goes HIGH simultaneously with WE HIGH, the output remains in high impedance state.
32. The minimum write cycle pulse width should be equal to the sum of tSD and tHZWE.
33. During this period, the I/Os are in output state. Do not apply input signals.
Document Number: 38-05576 Rev. *X
Page 9 of 20
CY62148EV30 MoBL
Truth Table
CE [34]
WE
X
OE
X
Inputs/Outputs
High Z
Mode
Deselect/Power down
Read
Power
H
L
L
L
Standby (ISB
Active (ICC
Active (ICC
Active (ICC
)
H
L
Data out
High Z
)
H
H
Output disabled
Write
)
L
X
Data in
)
Note
34. Chip enable must be at CMOS levels (not floating). Intermediate voltage levels on this pin is not permitted.
Document Number: 38-05576 Rev. *X
Page 10 of 20
CY62148EV30 MoBL
Ordering Information
Speed
Package
Diagram
Operating
Range
Ordering Code
(ns)
Package Type
45
CY62148EV30LL-45BVI
CY62148EV30LL-45BVXI
CY62148EV30LL-45BVXIT
CY62148EV30LL-45ZSXI
CY62148EV30LL-55SXI
51-85149 36-ball VFBGA
Industrial
51-85149 36-ball VFBGA (Pb-free)
51-85149 36-ball VFBGA (Pb-free)
51-85095 32-pin TSOP II (Pb-free)
51-85081 32-pin SOIC (Pb-free)
55
Industrial
Contact your local Cypress sales representative for availability of these parts.
Ordering Code Definitions
E V30
- XX XX X
LL
X
X
4
CY 621
8
Option: X = blank or T
blank = Standard; T = Tape and Reel
Temperature Grade: X = I or A
I = Industrial; A = Automotive-A
Pb-free
Package Type: XX = BV or ZS or S
BV = 36-ball VFBGA
ZS = 32-pin TSOP II
S = 32-pin SOIC
Speed Grade: XX = 45 ns or 55 ns
LL = Low Power
V30 = 3 V (typical)
Process Technology: E = 90 nm
Bus Width: 8 = × 8
Density: 4 = 4-Mbit
Family Code: 621 = MoBL SRAM family
Company ID: CY = Cypress
Document Number: 38-05576 Rev. *X
Page 11 of 20
CY62148EV30 MoBL
Package Diagrams
Figure 8. 36-ball VFBGA (8.0 × 6.0 × 1.0 mm) Package Outline, 51-85149
2X
0.10 C
E1
4
(datum B)
A1 CORNER
E
B
A
D
6
5
3
2
1
7
A1 CORNER
A
6
B
C
D
E
F
SD
D1
(datum A)
G
H
eD
6
2X
0.10 C
eE
SE
TOP VIEW
BOTTOM VIEW
0.25 C
DETAIL A
A1
0.10 C
C
36XØb
5
A
Ø0.25 M C A B
Ø0.05 M C
SIDE VIEW
DETAIL A
NOTES:
DIMENSIONS
NOM.
SYMBOL
1. ALL DIMENSIONS ARE IN MILLIMETERS.
MIN.
MAX.
1.00
-
2. SOLDER BALL POSITION DESIGNATION PER JEP95, SECTION 3, SPP-020.
3. "e" REPRESENTS THE SOLDER BALL GRID PITCH.
A
A1
D
-
-
-
0.16
4. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D" DIRECTION.
SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION.
N IS THE NUMBER OF POPULATED SOLDER BALL POSITIONS FOR MATRIX
SIZE MD X ME.
8.00 BSC
6.00 BSC
5.25 BSC
3.75 BSC
8
E
D1
E1
MD
ME
N
5.
DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A
PLANE PARALLEL TO DATUM C.
6
6.
"SD" AND "SE" ARE MEASURED WITH RESPECT TO DATUMS A AND B AND
DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW
36
0.30
b
0.25
0.35
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW
"SD" OR "SE" = 0.
eD
eE
SD
SE
0.75 BSC
0.75 BSC
0.375 BSC
0.375 BSC
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW
"SD" = eD/2 AND "SE" = eE/2.
A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK
METALIZED MARK, INDENTATION OR OTHER MEANS.
7.
8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED SOLDER
BALLS.
51-85149 *G
Document Number: 38-05576 Rev. *X
Page 12 of 20
CY62148EV30 MoBL
Package Diagrams (continued)
Figure 9. 32-pin TSOP II (20.95 × 11.76 × 1.0 mm) Package Outline, 51-85095
51-85095 *D
Document Number: 38-05576 Rev. *X
Page 13 of 20
CY62148EV30 MoBL
Package Diagrams (continued)
Figure 10. 32-pin SOIC (450 Mils) Package Outline, 51-85081
51-85081 *F
Document Number: 38-05576 Rev. *X
Page 14 of 20
CY62148EV30 MoBL
Acronyms
Document Conventions
Units of Measure
Symbol
Acronym
Description
BHE
BLE
Byte High Enable
Byte Low Enable
Unit of Measure
°C
µA
mA
ns
pF
V
degree Celsius
microampere
milliampere
nanosecond
picofarad
volt
CMOS
CE
Complementary Metal Oxide Semiconductor
Chip Enable
I/O
Input/Output
OE
Output Enable
SRAM
TSOP
VFBGA
WE
Static Random Access Memory
Thin Small Outline Package
Very Fine-Pitch Ball Grid Array
Write Enable
W
watt
Document Number: 38-05576 Rev. *X
Page 15 of 20
CY62148EV30 MoBL
Document History Page
Document Title: CY62148EV30 MoBL, 4-Mbit (512K × 8) Static RAM
Document Number: 38-05576
Submission
Region
ECN
Description of Change
Date
**
223225
247373
05/05/2004 New data sheet.
*A
07/28/2004 Changed status from Advance Information to Preliminary.
Updated Operating Range:
Updated Note 7 (Changed VCC stabilization time from 100 s to 200 s).
Updated Data Retention Characteristics:
Changed maximum value of ICCDR parameter from 2.0 A to 2.5 A.
Changed minimum value of tR parameter from 100 s to tRC ns.
Updated Switching Characteristics:
Changed minimum value of tOHA parameter from 6 ns to 10 ns corresponding to both 35 ns
and 45 ns speed bins.
Changed maximum value of tDOE parameter from 15 ns to 18 ns corresponding to 35 ns
speed bin.
Changed maximum value of tHZOE, tHZWE parameters from 12 ns to 15 ns corresponding
to 35 ns speed bin and 15 ns to 18 ns corresponding to 45 ns speed bin.
Changed minimum value of tSCE parameter from 25 ns to 30 ns corresponding to 35 ns
speed bin and 40 ns to 35 ns corresponding to 45 ns speed bin.
Changed maximum value of tHZCE parameter from 12 ns to 18 ns corresponding to 35 ns
speed bin and 15 ns to 22 ns corresponding to 45 ns speed bin.
Changed minimum value of tSD parameter from 15 ns to 18 ns corresponding to 35 ns speed
bin and 20 ns to 22 ns corresponding to 45 ns speed bin.
Updated Ordering Information:
Updated part numbers.
*B
414807
12/16/2005 Changed status from Preliminary to Final.
Changed the address of Cypress Semiconductor Corporation on page 1 from “3901 North
First Street” to “198 Champion Court”.
Updated Features:
Removed 35 ns speed bin related information.
Updated Pin Configurations:
Changed ball C3 from DNU to NC.
Removed the Note “DNU pins have to be left floating or tied to VSS to ensure proper
application.” and its reference.
Added 32-pin SOIC pinout.
Updated Electrical Characteristics:
Removed “L” version of CY62148EV30.
Changed typical value of ICC parameter from 12 mA to 15 mA corresponding to Test
Condition “f = fmax”.
Changed typical value of ICC parameter from 1.5 mA to 2 mA corresponding to Test
Condition “f = 1 MHz”.
Changed maximum value of ICC parameter from 2 mA to 2.5 mA corresponding to Test
Condition “f = 1 MHz”.
Changed typical value of ISB1 and ISB2 parameters from 0.7 A to 1 A.
Changed maximum value of ISB1 and ISB2 parameters from 2.5 A to 7 A.
Updated AC Test Loads and Waveforms:
Changed the AC test load capacitance value from 50 pF to 30 pF.
Updated Data Retention Characteristics:
Changed maximum value of ICCDR parameter from 2.5 A to 7 A.
Added typical value of ICCDR parameter.
Updated Switching Characteristics:
Changed minimum value of tLZOE parameter from 3 ns to 5 ns.
Changed minimum value of tLZCE and tLZWE parameters from 6 ns to 10 ns.
Changed maximum value of tHZCE parameter from 22 ns to 18 ns.
Changed minimum value of tPWE parameter from 30 ns to 35 ns.
Changed minimum value of tSD parameter from 22 ns to 25 ns.
Document Number: 38-05576 Rev. *X
Page 16 of 20
CY62148EV30 MoBL
Document History Page (continued)
Document Title: CY62148EV30 MoBL, 4-Mbit (512K × 8) Static RAM
Document Number: 38-05576
Submission
Region
ECN
Description of Change
Date
*B (cont.)
414807
12/16/2005 Updated Ordering Information:
Updated part numbers.
Removed “Package Name” column.
Added “Package Diagram” column.
Updated Package Diagrams:
spec 51-85149 – Changed revision from *B to *C.
Added spec 51-85081 *B.
Updated to new template.
*C
*D
*E
464503
833080
890962
05/25/2006 Added Automotive Temperature Range related information in all instances across the
document.
Updated Ordering Information:
Updated part numbers.
03/09/2007 Updated Electrical Characteristics:
Added details of VIL parameter corresponding to Test Condition “SOIC package”.
Added Note 10 and referred the same note in the maximum value of VIL parameter
corresponding to SOIC package.
03/30/2007 Removed Automotive Temperature Range related information in all instances across the
document.
Updated Features:
Added Note 1 and referred the same note in 32-pin SOIC package.
Updated Electrical Characteristics:
Added Note 11 and referred the same note in ISB2 parameter.
Updated Switching Characteristics:
Added values for all parameters corresponding to 55 ns Industrial Temperature Range.
Updated Ordering Information:
Updated part numbers.
*F
987940
04/18/2007 Updated Electrical Characteristics:
Changed maximum value of VOL parameter from 0.4 V to 0.2 V corresponding to Industrial
Temperature Range at IOL = 0.1 mA.
Changed maximum value of VIL parameter from 0.6 V to 0.4 V corresponding to Industrial
Temperature Range, SOIC package at VCC = 2.2 V to 2.7 V.
Updated Note 10.
Updated Note 11 (made the note applicable for both ISB2 and ICCDR parameters).
*G
2548575
08/05/2008 Added Automotive-A Temperature Range related information in all instances across the
document.
Updated Ordering Information:
Updated part numbers.
Updated to new template.
*H
*I
2769239
2944332
09/25/2009 Updated Ordering Information:
Updated part numbers.
06/04/2010 Updated Truth Table:
Added Note 34 and referred the same note in “CE” column.
Updated Package Diagrams:
spec 51-85149 – Changed revision from *C to *D.
spec 51-85095 – Changed revision from ** to *A.
spec 51-85081 – Changed revision from *B to *C.
*J
3007403
08/13/2010 Updated Ordering Information:
No change in part numbers.
Added Ordering Code Definitions.
Updated to new template.
Completing Sunset Review.
Document Number: 38-05576 Rev. *X
Page 17 of 20
CY62148EV30 MoBL
Document History Page (continued)
Document Title: CY62148EV30 MoBL, 4-Mbit (512K × 8) Static RAM
Document Number: 38-05576
Submission
Region
ECN
Description of Change
Date
*K
3110202
12/14/2010 Updated Logic Block Diagram.
Updated Ordering Information:
No change in part numbers.
Updated Ordering Code Definitions.
*L
3302901
07/06/2011 Updated Functional Description:
Removed “For best practice recommendations, refer to the Cypress application note
AN1064, SRAM System Guidelines.” at the end.
Updated Ordering Information:
No change in part numbers.
Updated Ordering Code Definitions.
Updated Package Diagrams:
spec 51-85095 – Changed revision from *A to *B.
Updated to new template.
Completing Sunset Review.
*M
3363097
09/07/2011 Updated Data Retention Characteristics:
Removed reference of Note 12 in ICCDR parameter.
Added Note 14 and referred the same note in ICCDR parameter.
Updated Package Diagrams:
spec 51-85149 – Changed revision from *D to *E.
spec 51-85081 – Changed revision from *C to *D.
*N
*O
*P
3546715
3733339
4102967
03/09/2012 Updated Electrical Characteristics:
Updated Note 10 (Removed the line “Refer to AN13470 for details”.).
09/04/2012 Minor text edits.
Completing Sunset Review.
08/23/2013 Updated Switching Characteristics:
Added Note 17 and referred the same note in “Parameter” column.
Updated Package Diagrams:
spec 51-85081 – Changed revision from *D to *E.
Updated to new template.
Completing Sunset Review.
*Q
*R
4307881
4576526
04/09/2014 Updated Switching Characteristics:
Updated description of tPD parameter (Replaced “CE HIGH to power-up” with “CE HIGH to
power-down”).
11/21/2014 Updated Functional Description:
Added “For a complete list of related 1documentation, click here.” at the end.
Updated Switching Characteristics:
Added Note 23 and referred the same note in “Write Cycle”.
Updated Switching Waveforms:
Added Note 32 and referred the same note in Figure 7.
*S
*T
4802206
5234869
06/18/2015 Updated Package Diagrams:
spec 51-85149 – Changed revision from *E to *F.
spec 51-85095 – Changed revision from *B to *D.
Updated to new template.
04/22/2016 Updated Ordering Information:
Updated part numbers.
Updated Ordering Code Definitions (Added Tape and Reel option).
Updated Package Diagrams:
spec 51-85149 – Changed revision from *F to *G.
Updated to new template.
Document Number: 38-05576 Rev. *X
Page 18 of 20
CY62148EV30 MoBL
Document History Page (continued)
Document Title: CY62148EV30 MoBL, 4-Mbit (512K × 8) Static RAM
Document Number: 38-05576
Submission
Region
ECN
Description of Change
Date
*U
5480386
10/18/2016 Updated Thermal Resistance:
Replaced “two-layer” with “four-layer” in “Test Conditions” column.
Updated values of JA parameter and JC parameter corresponding to all packages.
Updated to new template.
Completing Sunset Review.
*V
6045156
01/25/2018 Updated Ordering Information:
Updated part numbers.
Updated to new template.
*W
*X
6531864
6906316
04/03/2019 Updated to new template.
06/26/2020 Updated Features:
Changed value of Typical standby current from 1 µA to 2.5 µA.
Changed value of Typical active current from 2 mA to 3.5 mA.
Updated Product Portfolio:
Changed typical value of Operating ICC from 2 mA to 3.5 mA corresponding to all packages
and “f = 1 MHz”.
Changed maximum value of Operating ICC from 2.5 mA to 6 mA corresponding to all
packages and “f = 1 MHz”.
Changed typical value of Standby, ISB2 from 1 µA to 2.5 µA corresponding to all packages.
Updated Electrical Characteristics:
Changed typical value of ICC parameter from 2 mA to 3.5 mA corresponding to all speed
bins and Test Condition “f = 1 MHz”.
Changed maximum value of ICC parameter from 2.5 mA to 6 mA corresponding to all speed
bins and Test Condition “f = 1 MHz”.
Changed typical value of ISB1 parameter from 1 µA to 2.5 µA corresponding to all speed bins.
Changed typical value of ISB2 parameter from 1 µA to 2.5 µA corresponding to all speed bins.
Updated Data Retention Characteristics:
Changed typical value of ICCDR parameter from 0.8 μA to 3 μA.
Changed maximum value of ICCDR parameter from 7 µA to 8.8 µA.
Updated Package Diagrams:
spec 51-85081 – Changed revision from *E to *F.
Updated to new template.
Document Number: 38-05576 Rev. *X
Page 19 of 20
CY62148EV30 MoBL
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
®
Products
PSoC Solutions
Arm® Cortex® Microcontrollers
cypress.com/arm
cypress.com/automotive
cypress.com/clocks
cypress.com/interface
cypress.com/iot
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP | PSoC 6 MCU
Automotive
Cypress Developer Community
Clocks & Buffers
Interface
Community | Code Examples | Projects | Video | Blogs |
Training | Components
Internet of Things
Memory
Technical Support
cypress.com/memory
cypress.com/mcu
cypress.com/support
Microcontrollers
PSoC
cypress.com/psoc
Power Management ICs
Touch Sensing
USB Controllers
Wireless Connectivity
cypress.com/pmic
cypress.com/touch
cypress.com/usb
cypress.com/wireless
© Cypress Semiconductor Corporation, 2004–2020. This document is the property of Cypress Semiconductor Corporation and its subsidiaries (“Cypress”). This document, including any software or
firmware included or referenced in this document (“Software”), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries worldwide. Cypress
reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other intellectual property
rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress hereby grants
you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to modify and reproduce
the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users (either directly or
indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress’s patents that are infringed by the Software (as provided by
Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation of the
Software is prohibited.
TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. No computing
device can be absolutely secure. Therefore, despite security measures implemented in Cypress hardware or software products, Cypress shall have no liability arising out of any security breach, such
as unauthorized access to or use of a Cypress product. CYPRESS DOES NOT REPRESENT, WARRANT, OR GUARANTEE THAT CYPRESS PRODUCTS, OR SYSTEMS CREATED USING
CYPRESS PRODUCTS, WILL BE FREE FROM CORRUPTION, ATTACK, VIRUSES, INTERFERENCE, HACKING, DATA LOSS OR THEFT, OR OTHER SECURITYINTRUSION (collectively, “Security
Breach”). Cypress disclaims any liability relating to any Security Breach, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from any Security Breach. In
addition, the products described in these materials may contain design defects or errors known as errata which may cause the product to deviate from published specifications. To the extent permitted
by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any product or
circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is the
responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. “High-Risk Device”
means any device or system whose failure could cause personal injury, death, or property damage. Examples of High-Risk Devices are weapons, nuclear installations, surgical implants, and other
medical devices. “Critical Component” means any component of a High-Risk Device whose failure to perform can be reasonably expected to cause, directly or indirectly, the failure of the High-Risk
Device, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from any use of
a Cypress product as a Critical Component in a High-Risk Device. You shall indemnify and hold Cypress, its directors, officers, employees, agents, affiliates, distributors, and assigns harmless from
and against all claims, costs, damages, and expenses, arising out of any claim, including claims for product liability, personal injury or death, or property damage arising from any use of a Cypress
product as a Critical Component in a High-Risk Device. Cypress products are not intended or authorized for use as a Critical Component in any High-Risk Device except to the limited extent that (i)
Cypress’s published data sheet for the product explicitly states Cypress has qualified the product for use in a specific High-Risk Device, or (ii) Cypress has given you advance written authorization to
use the product as a Critical Component in the specific High-Risk Device and you have signed a separate indemnification agreement.
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in
the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Document Number: 38-05576 Rev. *X
Revised June 26, 2020
Page 20 of 20
MoBL is a registered trademark, and More Battery Life is a trademark, of Cypress Semiconductor Corporation.
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