CY62157EV30LL-45BVI [INFINEON]
Asynchronous SRAM;
| 型号： | CY62157EV30LL-45BVI |
| 厂家： | 
Infineon |
| 描述： | Asynchronous SRAM 静态存储器 内存集成电路 |
| 文件： | 总24页 (文件大小：735K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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The fact that Infineon offers the following product as part of the Infineon product
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ordering part numbers listed in the datasheet for ordering.
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CY62157EV30 MoBL
8-Mbit (512K × 16) Static RAM
8-Mbit (512K
× 16) Static RAM
Features
Functional Description
■ Thin small outline package (TSOP) I package configurable as
512K × 16 or 1M × 8 static RAM (SRAM)
The CY62157EV30 is a high performance CMOS static RAM
organized as 512K words by 16 bits. This device features
advanced circuit design to provide ultra low active current. This
is ideal for providing More Battery Life™ (MoBL®) in portable
applications such as cellular telephones. The device also has an
automatic power down feature that significantly reduces power
consumption when addresses are not toggling. Place the device
into standby mode when deselected (CE1 HIGH or CE2 LOW or
both BHE and BLE are HIGH). The input or output pins (I/O0
through I/O15) are placed in a high impedance state when the
device is deselected (CE1HIGH or CE2 LOW), the outputs are
disabled (OE HIGH), Byte High Enable and Byte Low Enable are
disabled (BHE, BLE HIGH), or a write operation is active (CE1
LOW, CE2 HIGH and WE LOW).
■ High speed: 45 ns
■ Temperature ranges
❐ Industrial: –40 °C to +85 °C
❐ Automotive-A: –40 °C to +85 °C
❐ Automotive-E: –40 °C to +125 °C
■ Wide voltage range: 2.20 V to 3.60 V
■ Pin compatible with CY62157DV30
■ Ultra low standby power
❐ Typical standby current: 2 A
❐ Maximum standby current: 8 A (Industrial)
To write to the device, take Chip Enable (CE1 LOW and CE2
HIGH) and Write Enable (WE) inputs LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O0 through I/O7) is
written into the location specified on the address pins (A0 through
■ Ultra low active power
❐ Typical active current: 6 mA at f = 1 MHz
A
18). If Byte High Enable (BHE) is LOW, then data from I/O pins
■ Easy memory expansion with CE1, CE2, and OE features
■ Automatic power down when deselected
(I/O8 through I/O15) is written into the location specified on the
address pins (A0 through A18).
To read from the device, take Chip Enable (CE1 LOW and CE2
HIGH) and Output Enable (OE) LOW while forcing the Write
Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data
from the memory location specified by the address pins appear
on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from
memory appears on I/O8 to I/O15. See Truth Table on page 13
for a complete description of read and write modes.
■ Complementary Metal Oxide Semiconductor (CMOS) for
optimum speed and power
■ Available in Pb-free and non Pb-free 48-ball very fine-pitch ball
grid array (VFBGA), Pb-free 44-pin thin small outline package
(TSOP) II and 48-pin TSOP I packages
For a complete list of related documentation, click here.
Logic Block Diagram
DATA IN DRIVERS
A10
A 9
A 8
A 7
A 6
A 5
512K × 16/1M × 8
RAM Array
I/O0–I/O7
A 4
A 3
I/O8–I/O15
A 2
A 1
A 0
COLUMN DECODER
BYTE
CE2
CE
BHE
WE
1
PowerDown
Circuit
CE2
CE
BHE
BLE
1
OE
BLE
Cypress Semiconductor Corporation
Document Number: 38-05445 Rev. *S
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised February 28, 2020
CY62157EV30 MoBL
Contents
Pin Configurations ...........................................................3
Product Portfolio ..............................................................3
Maximum Ratings .............................................................4
Operating Range ...............................................................4
Electrical Characteristics .................................................4
Capacitance ......................................................................5
Thermal Resistance ..........................................................5
AC Test Loads and Waveforms .......................................5
Data Retention Characteristics .......................................6
Data Retention Waveform ................................................6
Switching Characteristics ................................................7
Switching Waveforms ......................................................8
Truth Table ......................................................................13
Ordering Information ......................................................14
Ordering Code Definitions .........................................14
Package Diagrams ..........................................................15
Acronyms ........................................................................18
Document Conventions .................................................18
Units of Measure .......................................................18
Document History Page .................................................19
Sales, Solutions, and Legal Information ......................23
Worldwide Sales and Design Support .......................23
Products ....................................................................23
PSoC® Solutions ......................................................23
Cypress Developer Community .................................23
Technical Support .....................................................23
Document Number: 38-05445 Rev. *S
Page 2 of 23
CY62157EV30 MoBL
Pin Configurations
Figure 1. 48-ball VFBGA pinout (Top View) [1]
Figure 2. 44-pin TSOP II pinout (Top View) [2]
1
2
3
4
5
6
A
A
A
A
A
A
A
1
2
3
4
5
6
7
8
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
4
3
2
1
0
5
6
A
7
A2
CE2
A0
A3
A5
A1
A4
A6
BLE OE
A
B
C
OE
BHE
BLE
I/O
15
I/O
14
I/O
I/O8
I/O0
I/O2
CE1
I/O1
BHE
CE
I/O
I/O
I/O
I/O
0
I/O9
I/O10
1
2
3
9
13
V
CC
I/O
V
10
11
12
13
14
15
16
I/O11 A17
D
V
SS
A7
I/O3
I/O4
I/O5
12
V
CC
SS
V
SS
I/O
I/O
I/O
I/O
V
CC
I/O
I/O
V
SS
I/O12
NC
A16
A15
A13
A10
V
CC
E
F
4
11
10
5
I/O14 I/O13
I/O6
I/O7
NC
A14
A12
A9
I/O
6
7
9
I/O
A
8
WE 17
G
H
8
9
I/O15
A18
NC
A8
WE
A11
A
A
A
A
A
18
19
20
21
22
A
18
17
16
15
A
10
A
11
A
12
A
14
13
Figure 3. 48-pin TSOP I pinout (Top View) [1, 3]
A15
1
2
3
4
5
6
7
8
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
BYTE
Vss
A14
A13
A12
A11
A10
A9
A8
NC
NC
I/O15/A19
I/O7
I/O14
I/O6
I/O13
I/O5
I/O12
I/O4
Vcc
I/O11
I/O3
I/O10
I/O2
I/O9
I/O1
I/O8
I/O0
OE
9
10
11
12
13
WE
CE2
NC
BHE 14
BLE
A18
A17
A7
A6
A5
A4
A3
A2
A1
15
16
17
18
19
20
21
22
23
24
Vss
CE1
A0
Product Portfolio
Power Dissipation
Operating ICC, (mA)
f = 1 MHz f = fmax
Speed
(ns)
VCC Range (V)
Standby, ISB2
Product
Range
(A)
Min Typ [4] Max
Typ [4] Max Typ [4] Max Typ [4] Max
CY62157EV30LL
Industrial/Automotive-A
Automotive-E
2.2
2.2
3.0
3.0
3.6
3.6
45
55
6
7
4
18
18
25
35
2
2
8
1.8
30
Notes
1. NC pins are not connected on the die.
2. The 44-pin TSOP II package has only one chip enable (CE) pin.
3. The BYTE pin in the 48-pin TSOP I package must be tied HIGH to use the device as a 512K × 16 SRAM. The 48-pin TSOP I package can also be used as a 1M × 8
SRAM by tying the BYTE signal LOW. In the 1M x 8 configuration, Pin 45 is A19, while BHE, BLE and I/O to I/O pins are not used.
8
14
4. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V = V
, T = 25 °C.
CC
CC(typ)
A
Document Number: 38-05445 Rev. *S
Page 3 of 23
CY62157EV30 MoBL
Output Current into Outputs (LOW) ............................ 20 mA
Maximum Ratings
Static Discharge Voltage
(MIL-STD-883, Method 3015) .................................> 2001 V
Exceeding the maximum ratings may impair the useful life of the
device. User guidelines are not tested.
Latch-Up Current ...................................................> 200 mA
Storage Temperature .............................. –65 °C to + 150 °C
Operating Range
Ambient Temperature
with Power Applied ................................. –55 °C to + 125 °C
Ambient
[7]
Device
Range
VCC
Supply Voltage
Temperature
to Ground Potential ............–0.3 V to 3.9 V (VCCmax + 0.3 V)
CY62157EV30LL Industrial / –40 °C to +85 °C 2.2 V to
DC Voltage Applied to Outputs
Automotive-A
3.6 V
in High Z State [5, 6] ............–0.3 V to 3.9 V (VCCmax + 0.3 V)
Automotive-E –40 °C to +125 °C
DC Input Voltage [5, 6] .......–0.3 V to 3.9 V (VCC max + 0.3 V)
Electrical Characteristics
Over the Operating Range
45 ns (Industrial/
Automotive-A)
Min Typ [8]
Max
55 ns (Automotive-E)
Parameter
Description
Test Conditions
Unit
Min Typ [8]
Max
VOH
Output HIGH voltage IOH = –0.1 mA
IOH = –1.0 mA, VCC > 2.70 V
IOL = 0.1 mA
2.0
2.4
–
–
–
–
–
2.0
2.4
–
–
–
–
V
V
–
0.4
VOL
VIH
VIL
Output LOW voltage
Input HIGH voltage
Input LOW voltage
–
0.4
0.4
–
V
IOL = 2.1 mA, VCC > 2.70 V
VCC = 2.2 V to 2.7 V
VCC = 2.7 V to 3.6 V
VCC = 2.2 V to 2.7 V
VCC = 2.7 V to 3.6 V
–
–
–
–
0.4
V
1.8
2.2
–0.3
–0.3
–1
–1
–
–
VCC + 0.3 1.8
VCC + 0.3 2.2
–
VCC + 0.3
VCC + 0.3
0.6
V
–
–
V
–
0.6
0.8
+1
+1
25
7
–0.3
–0.3
–4
–4
–
–
V
–
–
0.8
V
IIX
Input leakage current GND < VI < VCC
–
–
+4
A
A
mA
IOZ
ICC
Output leakage current GND < VO < VCC, Output Disabled
–
–
+4
VCC operating supply
current
f = fmax = 1/tRC VCC = VCCmax
OUT = 0 mA
CMOS levels
18
6
18
1.8
35
I
f = 1 MHz
–
–
4
[9]
ISB1
Automatic CE power
down current – CMOS
inputs
–
2
2
8
–
2
2
30
30
A
CE1 > VCC 0.2 V or CE2 < 0.2 V
or (BHE and BLE) > VCC – 0.2 V,
VIN > VCC – 0.2 V, VIN < 0.2 V
f = fmax (Address and Data Only),
f = 0 (OE and WE), VCC = 3.60 V
CE1 > VCC – 0.2 V or CE2 < 0.2 V
[9]
ISB2
Automatic CE power
down current – CMOS
inputs
–
8
–
A
or (BHE and BLE) > VCC – 0.2 V,
VIN > VCC – 0.2 V or VIN < 0.2 V,
f = 0, VCC = 3.60 V
Notes
5.
6.
V
V
= –2.0 V for pulse durations less than 20 ns.
IL(min)
= V + 0.75 V for pulse durations less than 20 ns.
IH(max)
CC
7. Full device AC operation assumes a 100 s ramp time from 0 to V (min) and 200 s wait time after V stabilization.
cc
CC
8. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V = V
, T = 25 °C.
A
CC
CC(typ)
9. Chip enables (CE and CE ), byte enables (BHE and BLE) and BYTE (48-pin TSOP I only) need to be tied to CMOS levels to meet the I
/ I
/ I
spec. Other
1
2
SB1 SB2 CCDR
inputs can be left floating.
Document Number: 38-05445 Rev. *S
Page 4 of 23
CY62157EV30 MoBL
Capacitance
Parameter [10]
Description
Input capacitance
Output capacitance
Test Conditions
TA = 25 °C, f = 1 MHz, VCC = VCC(typ)
Max
10
Unit
pF
CIN
COUT
10
pF
Thermal Resistance
Parameter [10]
Description
Test Conditions
48-ball BGA 48-pin TSOP I 44-pin TSOP II Unit
JA
Thermal resistance
(junction to ambient)
Still air, soldered on a 3 × 4.5
inch, four-layer printed circuit
board
36.92
60.07
65.91
C/W
JC
Thermal resistance
(junction to case)
13.55
9.73
13.96
C/W
AC Test Loads and Waveforms
Figure 4. AC Test Loads and Waveforms
R1
ALL INPUT PULSES
VCC
VCC
OUTPUT
90%
10%
90%
10%
GND
Fall Time = 1 V/ns
Rise Time = 1 V/ns
R2
30 pF
INCLUDING
JIG AND
SCOPE
Equivalent to:
THÉVENIN EQUIVALENT
RTH
OUTPUT
VTH
Parameters
2.5 V
16667
15385
8000
3.0 V
1103
1554
645
Unit
R1
R2
RTH
VTH
1.20
1.75
V
Note
10. Tested initially and after any design or process changes that may affect these parameters.
Document Number: 38-05445 Rev. *S
Page 5 of 23
CY62157EV30 MoBL
Data Retention Characteristics
Over the Operating Range
Parameter
Description
Conditions
Min
1.5
–
Typ [11]
Max
–
Unit
V
VDR
VCC for data retention
Data retention current
–
[12]
VCC = 1.5 V,
Industrial /
Automotive-A
3.2
8
A
ICCDR
CE1 > VCC – 0.2 V, CE < 0.2 V
,
2
Automotive-E
–
–
30
(BHE and BLE) > VCC – 0.2 V,
VIN > VCC – 0.2 V or VIN < 0.2 V
[13]
tCDR
Chip deselect to data
retention time
0
–
ns
ns
[14]
tR
Operation recovery time
CY62157EV30LL-45
CY62157EV30LL-55
45
55
–
–
–
–
Data Retention Waveform
Figure 5. Data Retention Waveform [15]
DATA RETENTION MODE
VCC(min)
tR
VCC(min)
tCDR
> 1.5V
VDR
VCC
CE1 or
BHE.BLE
or
CE2
Notes
11. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V = V
, T = 25 °C.
A
CC
CC(typ)
12. Chip enables (CE and CE ), byte enables (BHE and BLE) and BYTE (48-pin TSOP I only) need to be tied to CMOS levels to meet the I
/ I
/ I
spec.
1
2
SB1 SB2 CCDR
Other inputs can be left floating.
13. Tested initially and after any design or process changes that may affect these parameters.
14. Full device operation requires linear V ramp from V to V
15. BHE.BLE is the AND of both BHE and BLE. Deselect the chip by either disabling chip enable signals or by disabling both BHE and BLE.
> 100 s or stable at V
> 100 s.
CC(min)
CC
DR
CC(min)
Document Number: 38-05445 Rev. *S
Page 6 of 23
CY62157EV30 MoBL
Switching Characteristics
Over the Operating Range
45 ns (Industrial/
Automotive-A)
55 ns (Automotive-E)
Unit
Parameter [16, 17]
Description
Min
Max
Min
Max
Read Cycle
tRC
Read cycle time
45
–
–
45
–
55
–
–
55
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAA
Address to data valid
tOHA
Data hold from address change
CE1 LOW and CE2 HIGH to data valid
OE LOW to data valid
OE LOW to Low Z[18]
OE HIGH to High Z[18, 19]
CE1 LOW and CE2 HIGH to Low Z[18]
CE1 HIGH and CE2 LOW to High Z[18, 19]
CE1 LOW and CE2 HIGH to power up
CE1 HIGH and CE2 LOW to power down
BLE/BHE LOW to data valid
10
–
10
–
tACE
45
22
–
55
25
–
–
–
tDOE
tLZOE
5
–
5
–
tHZOE
18
–
20
–
tLZCE
10
–
10
–
tHZCE
18
–
20
–
tPU
0
–
–
0
–
–
tPD
45
45
–
55
55
–
tDBE
tLZBE
BLE/BHE LOW to Low Z[18, 20]
BLE/BHE HIGH to High Z[18, 19]
5
–
10
–
tHZBE
18
20
Write Cycle [21, 22]
tWC
Write cycle time
45
–
–
–
–
–
–
–
–
–
55
–
–
–
–
–
–
–
–
–
ns
tSCE
tAW
tHA
tSA
CE1 LOW and CE2 HIGH to write end
Address setup to write end
35
35
40
40
ns
ns
Address hold from write end
Address setup to write start
0
0
0
0
ns
ns
tPWE
tBW
tSD
WE pulse width
35
35
25
0
40
40
25
0
ns
ns
ns
ns
BLE/BHE LOW to write end
Data setup to write end
Data hold from write end
tHD
WE LOW to High Z[18, 19]
WE HIGH to Low Z[18]
18
–
20
–
ns
ns
–
–
tHZWE
tLZWE
10
10
Notes
16. Test conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns or less, timing reference levels of V
/2, input pulse levels
CC(typ)
of 0 to V
, and output loading of the specified I /I as shown in the Figure 4 on page 5.
CC(typ)
OL OH
17. In an earlier revision of this device, under a specific application condition, READ and WRITE operations were limited to switching of the byte enable and/or chip enable
signals as described in the Application Notes AN13842 and AN66311. However, the issue has been fixed and in production now, and hence, these Application Notes
are no longer applicable. They are available for download on our website as they contain information on the date code of the parts, beyond which the fix has been in
production.
18. At any temperature and voltage condition, t
is less than t
, t
is less than t
, t
is less than t
, and t
is less than t
for any device.
HZCE
LZCE HZBE
LZBE HZOE
LZOE
HZWE
LZWE
19. t
, t
, t
, and t
transitions are measured when the outputs enter a high-impedance state.
HZOE HZCE HZBE
HZWE
20. If both byte enables are toggled together, this value is 10 ns.
21. The internal write time of the memory is defined by the overlap of WE, CE = V , BHE, BLE or both = V , and CE = V . All signals must be active to initiate a write
IL
IL
2
IH
and any of these signals can terminate a write by going inactive. The data input setup and hold timing must be referenced to the edge of the signal that terminates
the write.
22. The minimum write cycle time for Write Cycle No. 3 (WE Controlled, OE LOW) should be equal to the sum of tSD and tHZWE.
Document Number: 38-05445 Rev. *S
Page 7 of 23
CY62157EV30 MoBL
Switching Waveforms
Figure 6. Read Cycle No. 1 (Address Transition Controlled) [23, 24]
t
RC
ADDRESS
t
AA
t
OHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
Figure 7. Read Cycle No. 2 (OE Controlled) [24, 25]
ADDRESS
tRC
CE1
CE2
tPD
t
HZCE
tACE
BHE/BLE
OE
tDBE
tHZBE
tLZBE
tHZOE
tDOE
tLZOE
HIGH
IMPEDANCE
HIGH IMPEDANCE
DATA OUT
VCC
SUPPLY
CURRENT
DATA VALID
tLZCE
ICC
ISB
tPU
50%
50%
Notes
23. The device is continuously selected. OE, CE = V , BHE, BLE, or both = V , and CE = V .
IH
1
IL
IL
2
24. WE is HIGH for read cycle.
25. Address valid before or similar to CE , BHE, BLE transition LOW and CE transition HIGH.
1
2
Document Number: 38-05445 Rev. *S
Page 8 of 23
CY62157EV30 MoBL
Switching Waveforms (continued)
Figure 8. Write Cycle No. 1 (WE Controlled) [26, 27, 28]
tWC
ADDRESS
CE1
tSCE
CE2
tAW
tHA
tSA
tPWE
WE
tBW
BHE/BLE
OE
tHD
tSD
NOTE 29
DATA I/O
VALID DATA
tHZOE
Notes
26. The internal write time of the memory is defined by the overlap of WE, CE = V , BHE, BLE or both = V , and CE = V . All signals must be active to initiate
IL
IL
2
IH
a write and any of these signals can terminate a write by going inactive. The data input setup and hold timing must be referenced to the edge of the signal that
terminates the write.
27. Data I/O is high impedance if OE = V
.
IH
28. If CE goes HIGH and CE goes LOW simultaneously with WE = V , the output remains in a high impedance state.
1
2
IH
29. During this period, the I/Os are in output state. Do not apply input signals.
Document Number: 38-05445 Rev. *S
Page 9 of 23
CY62157EV30 MoBL
Switching Waveforms (continued)
Figure 9. Write Cycle No. 2 (CE1 or CE2 Controlled) [30, 31, 32]
tWC
ADDRESS
CE1
tSCE
CE2
tSA
tAW
tHA
tPWE
WE
tBW
BHE/BLE
OE
tHD
tSD
VALID DATA
DATA I/O
NOTE 33
tHZOE
Notes
30. The internal write time of the memory is defined by the overlap of WE, CE = V , BHE, BLE or both = V , and CE = V . All signals must be active to initiate
IL
IL
2
IH
a write and any of these signals can terminate a write by going inactive. The data input setup and hold timing must be referenced to the edge of the signal that
terminates the write.
31. Data I/O is high impedance if OE = V
.
IH
32. If CE goes HIGH and CE goes LOW simultaneously with WE = V , the output remains in a high impedance state.
1
2
IH
33. During this period, the I/Os are in output state. Do not apply input signals.
Document Number: 38-05445 Rev. *S
Page 10 of 23
CY62157EV30 MoBL
Switching Waveforms (continued)
Figure 10. Write Cycle No. 3 (WE Controlled, OE LOW) [34, 35]
tWC
ADDRESS
CE1
tSCE
CE2
tBW
BHE/BLE
tAW
tHA
tSA
tPWE
WE
tSD
tHD
NOTE 36
DATA I/O
VALID DATA
tLZWE
tHZWE
Notes
34. If CE goes HIGH and CE goes LOW simultaneously with WE = V , the output remains in a high impedance state.
1
2
IH
35. The minimum write cycle pulse width should be equal to the sum of tSD and tHZWE.
36. During this period, the I/Os are in output state. Do not apply input signals.
Document Number: 38-05445 Rev. *S
Page 11 of 23
CY62157EV30 MoBL
Switching Waveforms (continued)
Figure 11. Write Cycle No. 4 (BHE/BLE Controlled, OE LOW) [37]
tWC
ADDRESS
CE1
CE2
tSCE
tAW
tHA
tBW
BHE/BLE
WE
tSA
tPWE
tSD
tHD
NOTE 38
DATA I/O
VALID DATA
Notes
37. If CE goes HIGH and CE goes LOW simultaneously with WE = V , the output remains in a high impedance state.
1
2
IH
38. During this period, the I/Os are in output state. Do not apply input signals.
Document Number: 38-05445 Rev. *S
Page 12 of 23
CY62157EV30 MoBL
Truth Table
CE1
CE2
X[39]
L
WE
X
OE
X
BHE
X
BLE
X
Inputs/Outputs
High Z
Mode
Power
H
Deselect/power down
Deselect/power down
Deselect/power down
Read
Standby (ISB
Standby (ISB
Standby (ISB
)
)
)
X[39]
X[39]
L
X
X
X
X
High Z
X[39]
X
X
H
H
High Z
H
H
L
L
L
Data Out (I/O0–I/O15
)
Active (ICC
)
)
L
H
H
L
H
L
Data Out (I/O0–I/O7);
High Z (I/O8–I/O15
Read
Active (ICC
)
L
H
H
L
L
H
High Z (I/O0–I/O7);
Data Out (I/O8–I/O15
Read
Active (ICC
)
)
L
L
L
L
L
H
H
H
H
H
H
H
H
L
H
H
H
X
X
L
H
L
H
L
L
L
L
High Z
High Z
High Z
Output disabled
Output disabled
Output disabled
Write
Active (ICC
Active (ICC
Active (ICC
Active (ICC
Active (ICC
)
)
)
)
)
L
Data In (I/O0–I/O15)
L
H
Data In (I/O0–I/O7);
High Z (I/O8–I/O15)
Write
L
H
L
X
L
H
High Z (I/O0–I/O7);
Data In (I/O8–I/O15)
Write
Active (ICC
)
Note
39. The ‘X’ (Don’t care) state for the Chip enables in the truth table refer to the logic state (either HIGH or LOW). Intermediate voltage levels on these pins is not permitted.
Document Number: 38-05445 Rev. *S
Page 13 of 23
CY62157EV30 MoBL
Ordering Information
Speed
Package
Diagram
Operating
Range
Package Type
(ns)
Ordering Code
CY62157EV30LL-45BVI
CY62157EV30LL-45BVIT
CY62157EV30LL-45BVXI
CY62157EV30LL-45BVXIT
CY62157EV30LL-45ZSXI
CY62157EV30LL-45ZSXIT
CY62157EV30LL-45ZXI
CY62157EV30LL-45ZXIT
CY62157EV30LL-45BVXA
CY62157EV30LL-45BVXAT
CY62157EV30LL-45ZSXA
CY62157EV30LL-45ZSXAT
CY62157EV30LL-45ZXA
CY62157EV30LL-45ZXAT
CY62157EV30LL-55ZSXE
CY62157EV30LL-55ZSXET
CY62157EV30LL-55ZXE
CY62157EV30LL-55ZXET
45
51-85150 48-ball VFBGA
51-85150 48-ball VFBGA
Industrial
51-85150 48-ball VFBGA (Pb-free)
51-85150 48-ball VFBGA (Pb-free)
51-85087 44-pin TSOP Type II (Pb-free)
51-85087 44-pin TSOP Type II (Pb-free)
51-85183 48-pin TSOP Type I (Pb-free)
51-85183 48-pin TSOP Type I (Pb-free)
51-85150 48-ball VFBGA (Pb-free)
Automotive-A
Automotive-E
51-85150 48-ball VFBGA (Pb-free)
51-85087 44-pin TSOP Type II (Pb-free)
51-85087 44-pin TSOP Type II (Pb-free)
51-85183 48-pin TSOP Type I (Pb-free)
51-85183 48-pin TSOP Type I (Pb-free)
51-85087 44-pin TSOP Type II (Pb-free)
51-85087 44-pin TSOP Type II (Pb-free)
51-85183 48-pin TSOP Type I (Pb-free)
51-85183 48-pin TSOP Type I (Pb-free)
55
Contact your local Cypress sales representative for availability of these parts.
Ordering Code Definitions
-
XX XX
V30 LL
X
X
5
621
E
X
CY
7
Option: T- Tape & Reel; Blank - Std
Temperature Range: X = I or A or E
I = Industrial; A = Automotive-A; E = Automotive-E
Pb-free
Package Type: XX = BV or ZS or Z
BV = 48-ball VFBGA
ZS = 44-pin TSOP II
Z = 48-pin TSOP I
Speed Grade: XX = 45 ns or 55 ns
Low Power
Voltage
Process Technology: E = 90 nm
Bus Width: 7 = × 16
Density: 5 = 8-Mbit
Family Code: MoBL SRAM family
Company ID: CY = Cypress
Document Number: 38-05445 Rev. *S
Page 14 of 23
CY62157EV30 MoBL
Package Diagrams
Figure 12. 48-pin VFBGA (6 × 8 × 1.0 mm) Package Outline, 51-85150
51-85150 *I
Document Number: 38-05445 Rev. *S
Page 15 of 23
CY62157EV30 MoBL
Package Diagrams (continued)
Figure 13. 44-pin TSOP II Package Outline, 51-85087
51-85087 *E
Document Number: 38-05445 Rev. *S
Page 16 of 23
CY62157EV30 MoBL
Package Diagrams (continued)
Figure 14. 48-pin TSOP I (18.4 × 12 × 1.2 mm) Package Outline, 51-85183
STANDARD PIN OUT (TOP VIEW)
0.10
2X (N/2 TIPS)
0.10 C
8
2X
A2
2
0.10
2X
1
N
SEE DETAIL B
R
A
B
(c)
E
5
GAUGE PLANE
0.25 BASIC
e
9
N/2 +1
N/2
0°
5
A1
C
D1
D
4
PARALLEL TO
SEATING PLANE
L
C
0.20
2X (N/2 TIPS)
SEATING PLANE
DETAIL A
B
A
B
SEE DETAIL A
0.08MM M C A-B
b
6
7
WITH PLATING
e/2
REVERSE PIN OUT (TOP VIEW)
3
1
N
c
7
c1
X
X = A OR B
b1
BASE METAL
DETAIL B
N/2
N/2 +1
SECTION B-B
NOTES:
DIMENSIONS
SYMBOL
1. DIMENSIONS ARE IN MILLIMETERS (mm).
MIN. NOM. MAX.
A
1.20
2. PIN 1 IDENTIFIER FOR STANDARD PIN OUT (DIE UP).
0.15
0.05
A1
A2
b1
b
3. PIN 1 IDENTIFIER FOR REVERSE PIN OUT (DIE DOWN): INK OR LASER MARK.
0.95
0.17
0.17
1.00
0.20
1.05
0.23
0.27
4. TO BE DETERMINED AT THE SEATING PLANE -C- . THE SEATING PLANE IS
DEFINED AS THE PLANE OF CONTACT THAT IS MADE WHEN THE PACKAGE
LEADS ARE ALLOWED TO REST FREELY ON A FLAT HORIZONTAL SURFACE.
0.22
5. DIMENSIONS D1 AND E DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE
MOLD PROTRUSION ON E IS 0.15mm PER SIDE AND ON D1 IS 0.25mm PER SIDE.
c1
0.10
0.10
0.16
0.21
c
D
6. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08mm TOTAL IN EXCESS OF b DIMENSION AT MAX.
MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON LOWER RADIUS OR
THE FOOT. MINIMUM SPACE BETWEEN PROTRUSION AND AN ADJACENT LEAD
TO BE 0.07mm .
20.00 BASIC
18.40 BASIC
12.00 BASIC
0.50 BASIC
D1
E
e
L
0
0.50
0.60 0.70
7. THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN
0.10mm AND 0.25mm FROM THE LEAD TIP.
0°
8
0.20
R
N
0.08
8. LEAD COPLANARITY SHALL BE WITHIN 0.10mm AS MEASURED FROM THE
SEATING PLANE.
48
9. DIMENSION "e" IS MEASURED AT THE CENTERLINE OF THE LEADS.
10. JEDEC SPECIFICATION NO. REF: MO-142(D)DD.
51-85183 *F
Document Number: 38-05445 Rev. *S
Page 17 of 23
CY62157EV30 MoBL
Acronyms
Document Conventions
Units of Measure
Symbol
Acronym
Description
CE
Chip Enable
Unit of Measure
CMOS
I/O
Complementary Metal Oxide Semiconductor
Input/Output
°C
MHz
µA
µs
mA
mm
ns
degree Celsius
megahertz
microampere
microsecond
milliampere
millimeter
nanosecond
ohm
OE
Output Enable
RAM
SRAM
TSOP
VFBGA
WE
Random Access Memory
Static Random Access Memory
Thin Small Outline Package
Very Fine-Pitch Ball Grid Array
Write Enable
%
percent
pF
V
picofarad
volt
W
watt
Document Number: 38-05445 Rev. *S
Page 18 of 23
CY62157EV30 MoBL
Document History Page
Document Title: CY62157EV30 MoBL, 8-Mbit (512K × 16) Static RAM
Document Number: 38-05445
Submission
Revision
ECN
Description of Change
Date
**
202940
291272
01/29/2004 New data sheet.
*A
11/19/2004 Changed status from Advance Information to Preliminary.
Removed 48-pin TSOP I Package related information in all instances across the document.
Updated Pin Configurations:
Added Note 2 and referred the same note in Figure 2.
Updated Operating Range:
Updated Note 7 (Replaced 100 s with 200 s).
Updated Data Retention Characteristics:
Changed maximum value of ICCDR parameter from 4 µA to 4.5 µA.
Updated Switching Characteristics:
Changed minimum value of tOHA parameter from 6 ns to 10 ns corresponding to both 35 ns
and 45 ns speed bins.
Changed maximum value of tDOE parameter from 15 ns to 18 ns corresponding to 35 ns
speed bin.
Changed maximum value of tHZOE parameter from 12 ns to 15 ns corresponding to 35 ns
speed bin.
Changed maximum value of tHZOE parameter from 15 ns to 18 ns corresponding to 45 ns
speed bin.
Changed maximum value of tHZCE parameter from 12 ns to 18 ns corresponding to 35 ns
speed bin.
Changed maximum value of tHZCE parameter from 15 ns to 22 ns corresponding to 45 ns
speed bin.
Changed maximum value of tHZBE parameter from 12 ns to 15 ns corresponding to 35 ns
speed bin.
Changed maximum value of tHZBE parameter from 15 ns to 18 ns corresponding to 45 ns
speed bin.
Changed minimum value of tSCE parameter from 25 ns to 30 ns corresponding to 35 nsspeed
bin.
Changed minimum value of tSCE parameter from 40 ns to 35 ns corresponding to 45 ns speed
bin.
Changed minimum value of tAW parameter from 25 ns to 30 ns corresponding to 35 ns speed
bin.
Changed minimum value of tAW parameter from 40 ns to 35 ns corresponding to 45 ns speed bin.
Changed minimum value of tBW parameter from 25 ns to 30 ns corresponding to 35 ns speed
bin.
Changed minimum value of tBW parameterfrom 40ns to35 ns corresponding to 45nsspeedbin.
Changed minimum value of tSD parameter from 15 ns to 18 ns corresponding to 35 ns speed bin.
Changed minimum value of tSD parameter from 20 ns to 22 ns corresponding to 45 ns speed bin.
Changed maximum value of tHZWE parameter from 12 ns to 15 ns corresponding to 35 ns
speed bin.
Changed maximum value of tHZWE parameter from 15 ns to 18 ns corresponding to 45 ns
speed bin.
Updated Ordering Information:
Updated part numbers.
Document Number: 38-05445 Rev. *S
Page 19 of 23
CY62157EV30 MoBL
Document History Page (continued)
Document Title: CY62157EV30 MoBL, 8-Mbit (512K × 16) Static RAM
Document Number: 38-05445
Submission
Revision
ECN
Description of Change
Date
*B
444306
04/13/2006 Changed status from Preliminary to Final.
Removed 35 ns speed bin related information in all instances across the document.
Added 55 ns speed bin related information in all instances across the document.
Added 48-pin TSOP I Package related information in all instances across the document.
Added Automotive Temperature Range related information in all instances across the
document.
Updated Pin Configurations:
Updated Figure 1 (Replaced DNU with NC in ball E3).
Removed Note “DNU pins have to be left floating or tied to VSS to ensure proper application.”
and its reference.
Updated Product Portfolio:
Removed “L” and “LL” from the part numbers.
Updated Electrical Characteristics:
Changed typical value of ICC parameter from 16 mA to 18 mA corresponding to 45 ns speed
bin and Test Condition “f = fax = 1/tRC”.
Changed maximum value of ICC parameter from 28 mA to 25 mA corresponding to 45 ns
speed bin and Test Condition “f = fax = 1/tRC”.
Changed maximum value of ICC parameter from 2.3 mA to 3 mA corresponding to 45 ns
speed bin and Test Condition “f = 1 MHz”.
Updated details in “Test Condition” column corresponding to ISB1 parameter.
Changed typical value of ISB1 parameter from 0.9 A to 2 A corresponding to 45 ns speed
bin.
Changed maximum value of ISB1 parameter from 4.5 A to 8 A corresponding to 45 ns
speed bin.
Changed typical value of ISB2 parameter from 0.9 A to 2 A corresponding to 45 ns speed
bin.
Changed maximum value of ISB2 parameter from 4.5 A to 8 A corresponding to 45 ns
speed bin.
Updated Thermal Resistance:
Replaced TBD with values in TSOP II column and updated all remaining values.
Updated AC Test Loads and Waveforms:
Updated Figure 4 (Replaced 50 pF with 30 pF).
Updated Data Retention Characteristics:
Added value in “Typ” column for ICCDR parameter.
Changed maximum value of ICCDR parameter from 4.5 A to 5 A corresponding to Test
Condition “Industrial”.
Changed minimum value of tR parameter from 100 s to tRC ns.
Updated Switching Characteristics:
Changed minimum value of tLZOE parameter from 3 ns to 5 ns corresponding to 45 ns speed
bin.
Changed minimum value of tLZCE parameter from 6 ns to 10 ns corresponding to 45 ns
speed bin.
Changed maximum value of tHZCE parameter from 22 ns to 18 ns corresponding to 45 ns
speed bin.
Changed minimum value of tLZBE parameter from 6 ns to 5 ns corresponding to 45 ns speed
bin.
Changed minimum value of tPWE parameter from 30 ns to 35 ns corresponding to 45 ns
speed bin.
Changed minimum value of tSD parameter from 22 ns to 25 ns corresponding to 45 ns speed
bin.
Changed minimum value of tLZWE parameter from 6 ns to 10 ns corresponding to 45 ns
speed bin.
Added Note 20 and referred the same note in tLZBE parameter.
Document Number: 38-05445 Rev. *S
Page 20 of 23
CY62157EV30 MoBL
Document History Page (continued)
Document Title: CY62157EV30 MoBL, 8-Mbit (512K × 16) Static RAM
Document Number: 38-05445
Submission
Revision
ECN
Description of Change
Date
*B (cont.)
444306
04/13/2006 Updated Ordering Information:
Updated part numbers.
Removed “Package Name” column.
Added “Package Diagram” column.
*C
*D
467052
925501
06/06/2006 Added 1M × 8 configuration related information in all instances across the document.
Updated Ordering Information:
Updated part numbers.
04/09/2007 Removed Automotive-E temperature range related information in all instances across the
document.
Added Preliminary Automotive-A related information in all instances across the document.
Updated Electrical Characteristics:
Added Note 9 and referred the same note in ISB2 parameter.
Updated Switching Characteristics:
Added Note 17 and referred the same note in “Parameter” column.
*E
*F
1045801
2724889
05/08/2007 Changed Automotive-A temperature range related information from Preliminary to Final.
Updated Electrical Characteristics:
Updated Note 9.
06/26/2009 Added Automotive-E temperature range related information in all instances across the
document.
Updated Ordering Information:
Updated part numbers.
Updated to new template.
*G
2927528
05/04/2010 Updated Pin Configurations:
Updated Figure 3 (Renamed “DNU” pins as “NC”).
Updated Truth Table:
Added Note 39 and referred the same note in “X” in “CE1” and “CE2” columns.
Updated Package Diagrams:
spec 51-85150 – Changed revision from *D to *E.
spec 51-85087 – Changed revision from *A to *C.
spec 51-85183 – Changed revision from *A to *B.
Updated to new template.
*H
*I
3110053
3269771
12/14/2010 Changed Table Footnotes to Notes.
Updated Ordering Information:
No change in part numbers.
Added Ordering Code Definitions.
05/30/2011 Updated Functional Description:
Updated description.
Updated Electrical Characteristics:
Updated details in “Conditions” column corresponding to ISB1 and ISB2 parameters.
Updated Data Retention Characteristics:
Updated details in “Conditions” and “Min” columns corresponding to ICCDR and tR param-
eters.
Updated Package Diagrams:
spec 51-85150 – Changed revision from *E to *F.
Added Acronyms and Units of Measure.
Updated to new template.
Completing Sunset Review.
*J
3578601
04/11/2012 Updated Package Diagrams:
spec 51-85150 – Changed revision from *F to *G.
spec 51-85087 – Changed revision from *C to *D.
spec 51-85183 – Changed revision from *B to *C.
Completing Sunset Review.
Document Number: 38-05445 Rev. *S
Page 21 of 23
CY62157EV30 MoBL
Document History Page (continued)
Document Title: CY62157EV30 MoBL, 8-Mbit (512K × 16) Static RAM
Document Number: 38-05445
Submission
Revision
ECN
Description of Change
Date
*K
4102449
08/22/2013 Updated Switching Characteristics:
Updated Note 17.
Updated Package Diagrams:
spec 51-85150 – Changed revision from *G to *H.
spec 51-85087 – Changed revision from *D to *E.
Updated to new template.
*L
4126231
09/18/2013 Updated Switching Characteristics:
Updated Note 17 (Removed last sentence from Note 17 and added the same sentence as
a new note namely Note 18).
*M
*N
4214977
4578508
12/09/2013 Updated Pin Configurations:
Updated Note 3 (Removed ‘NC’ mentioned at the end of the note).
11/24/2014 Updated Functional Description:
Added “For a complete list of related documentation, click here.” at the end.
Updated Switching Characteristics:
Added Note 22 and referred the same note in “Write Cycle”.
Updated Switching Waveforms:
Added Note 35 and referred the same note in Figure 10.
*O
*P
4748627
5320972
04/30/2015 Updated Package Diagrams:
spec 51-85183 – Changed revision from *C to *D.
Updated to new template.
Completing Sunset Review.
06/23/2016 Updated Thermal Resistance:
Replaced “two-layer” with “four-layer” in “Test Conditions” column.
Updated values of JA, JC parameters corresponding to all packages.
Updated Ordering Information:
Updated part numbers.
Updated to new template.
*Q
5731504
05/10/2017 Updated Package Diagrams:
spec 51-85183 – Changed revision from *D to *F.
Updated to new template.
Completing Sunset Review.
*R
*S
6517814
6819854
03/21/2019 Updated Package Diagrams:
spec 51-85150 – Changed revision from *H to *I.
Updated to new template.
02/28/2020 Updated Features:
Updated description.
Updated Product Portfolio:
Updated all values of “Operating ICC” corresponding to “f = 1 MHz”.
Updated Electrical Characteristics:
Updated all values of ICC parameter corresponding to
“45 ns (Industrial/Automotive-A)” and “f = 1 MHz”.
Updated Thermal Resistance:
Updated all values of JA, JC parameters corresponding to all packages.
Updated Data Retention Characteristics:
Updated all values of
“Industrial/Automotive-A”.
Updated to new template.
parameter corresponding to Condition
ICCDR
Document Number: 38-05445 Rev. *S
Page 22 of 23
CY62157EV30 MoBL
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
®
Products
PSoC Solutions
Arm® Cortex® Microcontrollers
cypress.com/arm
cypress.com/automotive
cypress.com/clocks
cypress.com/interface
cypress.com/iot
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP | PSoC 6 MCU
Automotive
Cypress Developer Community
Clocks & Buffers
Interface
Community | Code Examples | Projects | Video | Blogs |
Training | Components
Internet of Things
Memory
Technical Support
cypress.com/memory
cypress.com/mcu
cypress.com/support
Microcontrollers
PSoC
cypress.com/psoc
Power Management ICs
Touch Sensing
USB Controllers
Wireless Connectivity
cypress.com/pmic
cypress.com/touch
cypress.com/usb
cypress.com/wireless
© Cypress Semiconductor Corporation, 2004–2020. This document is the property of Cypress Semiconductor Corporation and its subsidiaries (“Cypress”). This document, including any software or
firmware included or referenced in this document (“Software”), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries worldwide. Cypress
reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other intellectual property
rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress hereby grants
you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to modify and reproduce
the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users (either directly or
indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress’s patents that are infringed by the Software (as provided by
Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation of the
Software is prohibited.
TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. No computing
device can be absolutely secure. Therefore, despite security measures implemented in Cypress hardware or software products, Cypress shall have no liability arising out of any security breach, such
as unauthorized access to or use of a Cypress product. CYPRESS DOES NOT REPRESENT, WARRANT, OR GUARANTEE THAT CYPRESS PRODUCTS, OR SYSTEMS CREATED USING
CYPRESS PRODUCTS, WILL BE FREE FROM CORRUPTION, ATTACK, VIRUSES, INTERFERENCE, HACKING, DATA LOSS OR THEFT, OR OTHER SECURITYINTRUSION (collectively, “Security
Breach”). Cypress disclaims any liability relating to any Security Breach, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from any Security Breach. In
addition, the products described in these materials may contain design defects or errors known as errata which may cause the product to deviate from published specifications. To the extent permitted
by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any product or
circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is the
responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. “High-Risk Device”
means any device or system whose failure could cause personal injury, death, or property damage. Examples of High-Risk Devices are weapons, nuclear installations, surgical implants, and other
medical devices. “Critical Component” means any component of a High-Risk Device whose failure to perform can be reasonably expected to cause, directly or indirectly, the failure of the High-Risk
Device, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from any use of
a Cypress product as a Critical Component in a High-Risk Device. You shall indemnify and hold Cypress, its directors, officers, employees, agents, affiliates, distributors, and assigns harmless from
and against all claims, costs, damages, and expenses, arising out of any claim, including claims for product liability, personal injury or death, or property damage arising from any use of a Cypress
product as a Critical Component in a High-Risk Device. Cypress products are not intended or authorized for use as a Critical Component in any High-Risk Device except to the limited extent that (i)
Cypress’s published data sheet for the product explicitly states Cypress has qualified the product for use in a specific High-Risk Device, or (ii) Cypress has given you advance written authorization to
use the product as a Critical Component in the specific High-Risk Device and you have signed a separate indemnification agreement.
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in
the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Document Number: 38-05445 Rev. *S
Revised February 28, 2020
Page 23 of 23
MoBL is a registered trademark and More Battery Life is a trademark of Cypress Semiconductor Corporation.
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Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9130CG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9130LG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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VISHAY
SI9130_11
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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VISHAY
SI9137
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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VISHAY
SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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VISHAY
SI9137LG
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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VISHAY
SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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VISHAY
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