CY62162G30-45BGXI [INFINEON]
Asynchronous SRAM;
| 型号： | CY62162G30-45BGXI |
| 厂家： | 
Infineon |
| 描述： | Asynchronous SRAM 静态存储器 内存集成电路 |
| 文件： | 总21页 (文件大小：544K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Please note that Cypress is an Infineon Technologies Company.
The document following this cover page is marked as “Cypress” document as this is the
company that originally developed the product. Please note that Infineon will continue
to offer the product to new and existing customers as part of the Infineon product
portfolio.
Continuity of document content
The fact that Infineon offers the following product as part of the Infineon product
portfolio does not lead to any changes to this document. Future revisions will occur
when appropriate, and any changes will be set out on the document history page.
Continuity of ordering part numbers
Infineon continues to support existing part numbers. Please continue to use the
ordering part numbers listed in the datasheet for ordering.
www.infineon.com
CY62162G/CY62162GE MoBL
16-Mbit (512K × 32) Static RAM
with Error-Correcting Code (ECC)
16-Mbit (512K
× 32) Static RAM with Error-Correcting Code (ECC)
feature that reduces power consumption when addresses are
not toggling. Placing the device into standby mode reduces
power consumption by more than 99% when deselected (CE1
HIGH or CE2 LOW or BA-D HIGH). The input and output pins
(I/O0 through I/O31) are placed in a high impedance state when
deselected (CE1 HIGH or CE2 LOW) or outputs are disabled (OE
HIGH) or the byte selects are disabled (BA-D HIGH).
Features
■ Ultra-low standby power
❐ Typical standby current: 5.5 A
❐ Maximum standby current: 16 A
■ High speed: 45 ns/55 ns
To write to the device, take chip enables (CE1 LOW, CE2 HIGH)
and write enable (WE) input LOW. If byte enable A (BA) is LOW,
then data from I/O pins (I/O0 through I/O7) is written into the
location specified on the address pins (A0 through A18). If byte
enable B (BB) is LOW, then data from I/O pins (I/O8 through
I/O15) is written into the location specified on the address pins
(A0 through A18). Likewise, BC and BD correspond with the I/O
pins I/O16 to I/O23 and I/O24 to I/O31, respectively.
■ Embedded error-correcting code (ECC) for single-bit error
correction
■ Wide voltage range: 1.65 V to 2.2 V, 2.2 V to 3.6 V
■ 1.0-V data retention
■ Transistor-transistor logic (TTL) compatible inputs and outputs
■ ERR pin to indicate 1-bit error detection and correction
■ Easy memory expansion with CE1 and CE2 features
To read from the device, take chip enables (CE1 LOW, CE2
HIGH), and output enable (OE) LOW while forcing the write
enable (WE) HIGH. If the first byte enable (BA) is LOW, then data
from the memory location specified by the address pins appear
on I/O0 to I/O7. If byte enable (BB) is LOW, then data from
memory appears on I/O8 to I/O15. Likewise, BC and BD
correspond to the third and fourth bytes. During Read operation,
in case of a single bit error detection and correction, ERR is
■ Available in Pb-free 119-ball PBGA package, 512K × 32 bits
SRAM
Functional Description
The CY62162G and CY62162GE devices are high performance
CMOS MoBL SRAM organized as 512K words by 32-bits. Both
CY62162G and CY62162GE are available with dual chip
enables. CY62162GE includes an error indication pin that
signals the host processor in the case of a single bit
error-detection and correction event. It is ideal for providing More
Battery Life™ (MoBL®) in portable applications such as cellular
telephones. The device also has an automatic power down
asserted
HIGH[1]
.
See
the
Truth
Table
–
CY62162G/CY62162GE on page 14 for a complete description
of read and write modes.
CY62162G and CY62162GE devices are available in a 119-ball
PBGA package with center power and ground pinout.
Product Portfolio
Power Dissipation
Features and Options
(see the Pin
Operating ICC, (mA)
f = fmax
Speed
(ns)
Product
Range
VCC Range (V)
Standby, ISB2 (µA)
Configurations
Section)
Typ[2]
Max
32
Typ[2]
7
Max
26
CY62162G(E)18
CY62162G(E)30
Dual Chip Enable
Optional Error indication
on ERR pinout
Industrial
1.65 V–2.2 V
2.2 V–3.6 V
55
45
29
29
36
5.5
16
Notes
1. This device does not support automatic write-back on error detection.
2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V = 1.8 V (for V range of 1.65 V–2.2 V), V = 3 V
CC
CC
CC
(for V range of 2.2 V–3.6 V), T = 25 °C.
CC
A
Cypress Semiconductor Corporation
Document Number: 001-81598 Rev. *F
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised March 2, 2020
CY62162G/CY62162GE MoBL
Logic Block Diagram – CY62162G
ECC ENCODER
DATAIN DRIVERS
I/O0‐I/O7
I/O8‐I/O15
I/O16‐I/O23
I/O24‐I/O32
WE
BD
BC
BB
BA
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
512K x 32
RAM ARRAY
COLUMN DECODER
WE
OE
CE2
CE1
BD BC BB BA
Document Number: 001-81598 Rev. *F
Page 2 of 20
CY62162G/CY62162GE MoBL
Logic Block Diagram – CY62162GE
ECC ENCODER
DATAIN DRIVERS
I/O0‐I/O7
I/O8‐I/O15
I/O16‐I/O23
I/O24‐I/O32
WE
BD
BC
BB
BA
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
512K x 32
RAM ARRAY
ERR
COLUMN DECODER
WE
OE
CE2
CE1
BD BC BB BA
Document Number: 001-81598 Rev. *F
Page 3 of 20
CY62162G/CY62162GE MoBL
Contents
Pin Configurations ...........................................................5
Maximum Ratings .............................................................6
Operating Range ...............................................................6
Electrical Characteristics .................................................6
Capacitance ......................................................................7
Thermal Resistance ..........................................................7
AC Test Loads and Waveforms .......................................7
Data Retention Characteristics .......................................8
Data Retention Waveform ................................................8
Switching Characteristics ................................................9
Switching Waveforms ....................................................10
Truth Table – CY62162G/CY62162GE ...........................14
ERR Output – CY62162GE .............................................14
Ordering Information ......................................................15
Ordering Code Definitions .........................................15
Package Diagram ............................................................16
Acronyms ........................................................................17
Document Conventions .................................................17
Units of Measure .......................................................17
Document History Page .................................................18
Sales, Solutions, and Legal Information ......................20
Worldwide Sales and Design Support .......................20
Products ....................................................................20
PSoC® Solutions ......................................................20
Cypress Developer Community .................................20
Technical Support .....................................................20
Document Number: 001-81598 Rev. *F
Page 4 of 20
CY62162G/CY62162GE MoBL
Pin Configurations
Figure 1. 119-ball FBGA pinout [3]
CY62162G (512K × 32)
1
2
3
4
5
6
7
I/O
A
4
A
3
A
2
A
1
A
0
I/O
A
16
0
I/O
I/O
I/O
I/O
I/O
I/O
I/O
A
A
CE
A
A
I/O
I/O
I/O
I/O
I/O
I/O
I/O
B
C
D
E
F
G
H
J
17
18
19
20
21
22
23
18
17
CE
1
16
15
1
2
3
4
5
6
7
B
NC
NC
B
a
c
2
V
CC
GND
GND
GND
V
CC
GND
V
CC
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
V
CC
GND
V
CC
GND
GND
V
CC
GND
V
CC
V
CC
GND
V
CC
GND
GND
V
CC
GND
GND
NC
V
CC
V
CC
NC
I/O
I/O
I/O
I/O
I/O
I/O
V
CC
GND
GND
GND
V
CC
GND
K
L
24
25
26
27
28
8
V
CC
V
CC
I/O
I/O
9
V
GND
GND
V
CC
M
N
P
CC
10
11
12
13
14
15
GND
V
CC
V
CC
GND
I/O
I/O
I/O
I/O
I/O
V
CC
GND
GND
V
CC
I/O
I/O
I/O
A
14
B
d
NC
B
b
A
13
R
T
29
30
31
A
12
A
A
10
A
9
11
WE
OE
A
8
A
7
A
6
A
5
U
Figure 2. 119-ball FBGA pinout [3, 4]
CY62162GE (512K × 32)
1
2
3
4
5
6
7
I/O
A
A
A
A
A
I/O
A
16
4
3
2
1
0
0
I/O
I/O
I/O
I/O
I/O
I/O
I/O
A
A
CE
A
A
I/O
I/O
I/O
I/O
I/O
I/O
I/O
B
C
D
E
F
G
H
J
17
18
19
18
17
1
16
15
1
2
3
B
CE
NC
NC
B
c
2
a
V
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
V
CC
CC
GND
V
V
GND
20
21
22
23
CC
CC
4
5
6
7
V
GND
GND
V
CC
CC
GND
V
V
GND
CC
CC
V
GND
V
GND
CC
CC
ERR
GND
V
V
GND
NC
I/O
CC
CC
I/O
V
GND
GND
V
K
L
24
CC
CC
8
I/O
GND
V
CC
V
CC
GND
I/O
I/O
25
9
I/O
V
GND
GND
V
M
N
P
26
CC
CC
10
11
12
I/O
GND
V
V
GND
I/O
I/O
I/O
I/O
I/O
27
CC
CC
I/O
V
GND
GND
V
28
CC
CC
I/O
A
B
NC
B
A
R
T
29
14
d
b
13
13
14
15
I/O
A
A
A
A
30
12
11
10
9
WE
OE
I/O
A
A
A
A
U
31
8
7
6
5
Notes
3. NC pins are not connected internally to the die.
4. ERR is an Output pin. If not used, this pin should be left floating.
Document Number: 001-81598 Rev. *F
Page 5 of 20
CY62162G/CY62162GE MoBL
Output current into outputs (LOW) ............................. 20 mA
Maximum Ratings
Static discharge voltage
(per MIL-STD-883, method 3015) ......................... > 2001 V
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Latch-up current ....................................................> 140 mA
Storage temperature ................................ –65 °C to +150 °C
Operating Range
Ambient temperature
with power applied ................................... –55 °C to +125 °C
Ambient
Temperature
[7]
Device
Range
VCC
Supply voltage to ground potential .....–0.5 V to VCC + 0.5 V
DC voltage applied to outputs
CY62162G
Industrial –40°Cto+85°C 1.65 V to 2.2 V,
2.2 V to 3.6 V
in high Z State[6] .................................–0.5 V to VCC + 0.5 V
DC input voltage [6] ..............................–0.5 V to VCC+ 0.5 V
Electrical Characteristics
Over the Operating Range
Parameter
Description
Output HIGH
Test Conditions
Min
1.4
2.0
2.2
–
Typ [8]
Max
Unit
VOH
1.65 V to 2.2 V VCC = Min, IOH = –0.1 mA
–
–
–
V
voltage
2.2 V to 2.7 V
2.7 V to 3.6 V
V
CC = Min, IOH = –1.0 mA
CC = Min, IOH = –4.0 mA
–
–
V
–
VOL
VIH
VIL
Output LOW
voltage
1.65 V to 2.2 V VCC = Min, IOL = 0.1 mA
–
0.2
2.2 V to 2.7 V
2.7 V to 3.6 V
V
CC = Min, IOL = 2 mA
CC = Min, IOL = 8 mA
–
–
0.4
V
–
–
0.4
Input HIGH
voltage
1.65 V to 2.2 V –
1.4
2.0
2.0
–0.2
–0.3
–0.3
–1.0
–1.0
–
–
VCC + 0.2
2.2 V to 2.7 V
2.7 V to 3.6 V
–
–
–
V
CC + 0.3
CC + 0.3
0.4
–
V
Input LOW
voltage [6]
1.65 V to 2.2 V –
–
2.2 V to 2.7 V
2.7 V to 3.6 V
–
–
–
0.6
–
0.8
IIX
Input leakage current
GND < VIN < VCC
–
+1.0
+1.0
36.0
32.0
9.0
A
IOZ
ICC
Output leakage current
VCC operating supply current
GND < VOUT < VCC, Output disabled
–
f = 22.22 MHz (45 ns)
f = 18.18 MHz (55 ns)
f = 1 MHz
VCC = VCC(max)
OUT = 0 mA
CMOS levels
,
29.0
29.0
7.0
5.5
mA
I
–
–
[9]
ISB1
Automatic power down current – CE1 > VCC – 0.2 V or CE2 < 0.2 V
CMOS inputs; VCC = 2.2 to 3.6 V
–
16.0
A
or BA–D > VCC – 0.2 V,
VIN > VCC – 0.2 V, VIN < 0.2 V,
f = fmax (address and data only),
Automatic power down current –
CMOS inputs; VCC = 1.65 to 2.2 V
–
7.0
26.0
f = 0 (OE, and WE), VCC = VCC(max)
[9]
ISB2
Automatic power down current – CE1 > VCC – 0.2V or CE2 < 0.2 V
CMOS inputs; VCC = 2.2 to 3.6 V or BA–D > VCC – 0.2 V,
–
–
5.5
7.0
16.0
26.0
VIN > VCC – 0.2 V or VIN < 0.2 V,
Automatic power down current –
CMOS inputs; VCC = 1.65 to 2.2 V
f = 0, VCC = VCC(max)
Notes
5. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V = 1.8 V (for V range of 1.65 V–2.2 V), V = 3 V
CC
CC
CC
(for V range of 2.2 V–3.6 V), T = 25 °C.
CC
A
6.
V
= –2.0 V and V
= V + 2 V for pulse durations of less than 2 ns.
IL(min)
IH(max) CC
7. Full device AC operation assumes a 100-µs ramp time from 0 to V (min) and 200-µs wait time after V stabilizes to its operational value.
CC
CC
8. Indicates the value for the center of distribution at 3.0 V, 25 °C and not 100% tested.
9. Chip enables (CE and CE ) must be tied to CMOS levels to meet the I /I /I spec. Other inputs can be left floating.
1
2
SB1 SB2 CCDR
Document Number: 001-81598 Rev. *F
Page 6 of 20
CY62162G/CY62162GE MoBL
Capacitance
Parameter [10]
Description
Input capacitance
Output capacitance
Test Conditions
Max
Unit
CIN
TA = 25 °C, f = 1 MHz, VCC = VCC(typ)
10
pF
COUT
Thermal Resistance
Parameter [10]
Description
Test Conditions
119-ball BGA Unit
JA
Thermal resistance
(junction to ambient)
Still air, soldered on a 3 × 4.5 inch, 2-layer printed circuit
board
20.92
C/W
JC
Thermal resistance
(junction to case)
15.84
AC Test Loads and Waveforms
Figure 3. AC Test Loads and Waveforms
ALL INPUT PULSES
VCC
90%
90%
R1
VCC
OUTPUT
10%
10%
Fall Time = 1 V/ns
GND
R2
30 pF
Rise Time = 1 V/ns
INCLUDING
JIG AND
SCOPE
Equivalent to: THEVENIN EQUIVALENT
RTH
OUTPUT
VTH
Table 1. AC Test Loads
Parameter
R1
1.8 V
13500
10800
6000
0.8
2.5 V
16667
15385
8000
1.2
3.0 V
1103
1554
645
Unit
R2
RTH
VTH
1.75
V
Note
10. Tested initially and after any design or process changes that may affect these parameters.
Document Number: 001-81598 Rev. *F
Page 7 of 20
CY62162G/CY62162GE MoBL
Data Retention Characteristics
Over the Operating Range
Parameter
VDR
ICCDR
Description
VCC for data retention
Data retention current
Conditions
Min
1.0
–
Typ [11]
–
Max
–
Unit
V
[12, 13]
1.0 V < VCC < 2.2 V,
CE1 > VCC 0.2 V or CE2 < 0.2 V or
A–D > VCC – 0.2 V,
7.0
26.0
A
B
VIN > VCC 0.2 V or VIN < 0.2 V
2.2 V < VCC < 3.6 V,
–
5.5
16.0
CE1 > VCC 0.2 V or CE2 < 0.2 V or
BA–D > VCC – 0.2 V,
VIN > VCC 0.2 V or VIN < 0.2 V
[14]
tCDR
Chip deselect to data retention
time
–
0
–
–
–
–
ns
[14, 15]
tR
Operation recovery time
–
45 / 55
Data Retention Waveform
Figure 4. Data Retention Waveform
D A T A R E T E N T IO N M O D E
V C C
V D R = 1 .0 V
V C C (m in )
tC D R
V C C (m in )
t R
C E 1
(o r )
C E 2
Notes
11. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V = 1.8 V for the range 1.7 V to 2.2 V; 3 V for the
CC
range 2.2 V to 3.6 V, T = 25 °C.
A
12. Only chip enables (CE and CE ) and all byte enables (B ) need to be tied to CMOS levels to meet the I
/I
spec. Other inputs can be left floating.
1
2
A-D
SB2 CCDR
13. B
is the AND of B , B , B and B . Chip is deselected by either disabling the chip enable signals or by disabling all byte enables together.
A B C D
A-D
14. These parameters are guaranteed by design and are not tested.
15. Full device operation requires linear V ramp from V to V
> 100 s or stable at V > 100 s.
CC(min)
CC
DR
CC(min)
Document Number: 001-81598 Rev. *F
Page 8 of 20
CY62162G/CY62162GE MoBL
Switching Characteristics
Over the Operating Range
45 ns
55 ns
Parameter [16, 17]
Description
Unit
Min
Max
Min
Max
Read Cycle
tRC
Read cycle time
45.0
–
–
55.0
–
–
ns
tAA
Address to data/ERR valid
45.0
–
55.0
–
tOHA
tACE
tDOE
tLZOE
tHZOE
tLZCE
tHZCE
tPU
Data/ERR hold from address change
CE1 LOW and CE2 HIGH to data/ERR valid
OE LOW to data/ERR valid
OE LOW to low Z [17, 18]
OE HIGH to high Z [17, 18, 19]
CE1 LOW and CE2 HIGH to low Z [17, 18]
CE1 HIGH and CE2 LOW to high Z [17, 18, 19]
CE1 LOW and CE2 HIGH to power-up [20]
CE1 HIGH and CE2 LOW to power-down [20]
Byte enable LOW to data valid
10
–
10.0
–
45.0
22.0
–
55.0
25.0
–
–
–
5.0
–
5.0
–
18.0
–
18.0
–
10.0
–
10.0
–
18.0
–
18.0
–
0
0
tPD
–
45.0
45.0
–
–
55.0
55.0
–
tDBE
tLZBE
tHZBE
–
–
Byte enable LOW to low Z [17]
Byte enable HIGH to high Z [17, 19]
5.0
–
5.0
–
18.0
18.0
Write Cycle [21, 22]
tWC Write cycle time
tSCE
tAW
45.0
35.0
35.0
0
–
–
55.0
40.0
40.0
0
–
–
ns
CE1 LOW and CE2 HIGH to write end
Address setup to write end
Address hold from write end
Address setup to write start
WE pulse width
–
–
tHA
–
–
tSA
0
–
0
–
tPWE
tBW
35.0
35.0
25.0
0
–
40.0
40.0
25.0
0
–
Byte enable LOW to write end
Data setup to write end
–
–
tSD
–
–
tHD
Data hold from write end
WE LOW to high Z [17, 18, 19]
WE HIGH to low Z [17, 18]
–
–
tHZWE
tLZWE
–
18.0
–
–
20.0
–
10.0
10.0
Notes
16. Test conditions for all parameters other than tri-state parameters assume signal transition time of 1 V/ns, timing reference levels of V , input pulse levels of 0 to
TH
V
, and output loading of the specified I /I as shown in Table 1 on page 7.
CC(typ)
OL OH
17. At any temperature and voltage condition, t
is less than t
, t
is less than t
, t
is less than t
, and t
is less than t
for any given device.
LZWE
HZCE
LZCE HZBE
LZBE HZOE
LZOE
HZWE
18. Tested initially and after any design or process changes that may affect these parameters.
19. t , t , t , and t transitions are measured when the outputs enter a high impedence state.
HZOE HZCE HZBE
HZWE
20. These parameters are guaranteed by design and are not tested.
21. The internal write time of the memory is defined by the overlap of CE and WE LOW. Chip enable must be active and WE and byte enables must be LOW to initiate a
write, and the transition of any of these signals terminate the write. The input data setup and hold timing are referenced to the leading edge of the signal that terminates
the write.
22. The minimum write cycle pulse width for Write Cycle No. 2 (WE Controlled, OE LOW) should be equal to sum of t
and t
.
HZWE
SD
Document Number: 001-81598 Rev. *F
Page 9 of 20
CY62162G/CY62162GE MoBL
Switching Waveforms
Figure 5. Read Cycle No. 1 of CY62162G (Address Transition Controlled) [23, 24]
tRC
ADDRESS
DATA I/O
tAA
tOHA
PREVIOUS DATAOUT
VALID
DATAOUT VALID
Figure 6. Read Cycle No. 1 of CY62162GE (Address Transition Controlled) [23, 24]
tRC
ADDRESS
tAA
tOHA
DATA I/O
ERR
PREVIOUS DATAOUT VALID
DATAOUT VALID
ERR VALID
tAA
tOHA
PREVIOUS ERR VALID
Notes
23. Device is continuously selected. OE = V , CE = V .
IL
IL
24. WE is HIGH for read cycle.
Document Number: 001-81598 Rev. *F
Page 10 of 20
CY62162G/CY62162GE MoBL
Switching Waveforms (continued)
Figure 7. Read Cycle No. 2 (OE Controlled) [25, 26, 27]
ADDRESS
tRC
CE
tPD
tHZCE
tACE
OE
tHZOE
tDOE
tLZOE
BA-D
tDBE
tLZBE
tHZBE
HIGH
IMPEDANCE
HIGH IMPEDANCE
tLZCE
tPU
DATA I/O
DATAOUT VALID
VCC
SUPPLY
CURRENT
ISB
Notes
25. WE is HIGH for read cycle.
26. Address valid before or similar to CE transition LOW.
27. CE refers to a combination of CE and CE . CE is LOW when CE is LOW and CE is HIGH. CE is HIGH when CE is HIGH or CE is LOW.
1
2
1
2
1
2
Document Number: 001-81598 Rev. *F
Page 11 of 20
CY62162G/CY62162GE MoBL
Switching Waveforms (continued)
Figure 8. Write Cycle No. 1 (CE Controlled) [28, 29, 30, 31]
tWC
ADDRESS
tSA
tSCE
CE
tAW
tHA
tPWE
WE
tBW
BA-D
OE
tHZOE
tHD
tSD
NOTE 32
DATA I/O
DATAIN VALID
Notes
28. The internal write time of the memory is defined by the overlap of CE and WE LOW. Chip enable must be active and WE and byte enables must be LOW to initiate a
write, and the transition of any of these signals terminate the write. The input data setup and hold timing are referenced to the leading edge of the signal that terminates
the write.
29. Data I/O is high impedance if OE or B , B , B , B = V .
A
B
C
D
IH
30. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high impedance state.
31. CE refers to a combination of CE and CE . CE is LOW when CE is LOW and CE is HIGH. CE is HIGH when CE is HIGH or CE is LOW.
1
2
1
2
1
2
32. During this period the I/Os are in output state and input signals should not be applied.
Document Number: 001-81598 Rev. *F
Page 12 of 20
CY62162G/CY62162GE MoBL
Switching Waveforms (continued)
[33, 34, 35]
Figure 9. Write Cycle No. 2 (WE Controlled, OE LOW)
tWC
ADDRESS
tSCE
CE
tBW
BA-D
tAW
tHA
tSA
tPWE
WE
tLZWE
tSD
t
HZWE
tHD
NOTE 36
DATA I/O
DATAIN VALID
[33, 34]
Figure 10. Write Cycle No. 3 (BA, BB, BC, BD Controlled, OE LOW)
tWC
ADDRESS
tSCE
CE
tAW
tSA
tHA
tBW
BA-D
tPWE
WE
tHZWE
tHD
tSD
tLZWE
NOTE 36
DATA I/O
DATAIN VALID
Notes
33. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high impedance state.
34. CE refers to a combination of CE and CE . CE is LOW when CE is LOW and CE is HIGH. CE is HIGH when CE is HIGH or CE is LOW.
1
2
1
2
1
2
35. The minimum write cycle pulse width should be equal to the sum of t
and t
.
HZWE
SD
36. During this period the I/Os are in output state and input signals should not be applied.
Document Number: 001-81598 Rev. *F
Page 13 of 20
CY62162G/CY62162GE MoBL
Truth Table – CY62162G/CY62162GE
[37]
CE
OE WE BA BB BC BD I/O0–I/O7 I/O8–I/O15 I/O16–I/O23 I/O24–I/O31
Mode
Power
[38]
[38]
[38]
[38]
H
X
X
L
X
X
H
H
H
H
H
L
X
X
X
X
High Z
High Z
Data out
Data out
High Z
High Z
High Z
Data in
Data in
High Z
High Z
High Z
High Z
High Z
High Z
Data out
High Z
Data out
High Z
High Z
Data in
High Z
Data in
High Z
High Z
High Z
High Z
High Z
Data out
High Z
High Z
Data out
High Z
Data in
High Z
High Z
Data in
High Z
High Z
High Z
High Z
Standby
Standby
(I
(I
)
)
SB
SB
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
[38]
X
H
L
H
L
H
L
H
L
L
L
L
L
L
L
L
L
L
L
L
Data out Read all bits
(I
(I
(I
(I
(I
(I
(I
(I
(I
(I
)
)
)
)
)
)
)
)
)
)
)
L
L
H
L
H
H
L
H
H
H
L
High Z
High Z
High Z
Read byte A bits only
L
H
H
H
L
Read byte B bits only
Read byte C bits only
L
H
H
L
L
H
L
Data out Read byte D bits only
X
X
X
X
X
H
L
Data in
High Z
High Z
High Z
Data in
High Z
Write all bits
L
L
H
L
H
H
L
H
H
H
Write byte A bits only
Write byte B bits only
Write byte C bits only
Write byte D bits only
L
H
H
L
H
L
H
H
H
L
[38]
[38]
[38]
[38]
H
X
X
X
X
Selected, outputs disabled (I
ERR Output – CY62162GE
[39]
Output
Mode
0
1
Z
Read Operation, no single bit error in the stored data.
Read Operation, single bit error detected and corrected.
Device deselected / Outputs disabled / Write Operation.
Note
37. CE refers to a combination of CE and CE . CE is LOW when CE is LOW and CE is HIGH. CE is HIGH when CE is HIGH or CE is LOW.
1
2
1
2
1
2
38. ‘X’ refers to V or V . For CMOS voltage levels refer to I
test conditions in Electrical Characteristics on page 6. Chip enables (CE and CE ) and all Byte Enables
IL
IH
SB2
/I
1 2
(B ) must be in CMOS voltage levels to meet the I
spec.
A-D
SB2 CCDR
39. ERR is an Output pin. If not used, this pin should be left floating.
Document Number: 001-81598 Rev. *F
Page 14 of 20
CY62162G/CY62162GE MoBL
Ordering Information
Speed
(ns)
Voltage
Range
Package
Diagram
Package Type
(All Pb-free)
Operating
Range
Ordering Code
45
55
2.2 V–3.6 V CY62162G30-45BGXI
1.65 V–2.2 V CY62162G18-55BGXI
51-85115 119-ball PBGA (14 × 22 × 2.4 mm)
Industrial
Industrial
Ordering Code Definitions
G
E
CY 621 6
2
–
BG
X I
XX 45
Temperature Grade: I = Industrial
Pb-free
Package Type: BG = 119-ball PBGA
Speed grade XX: 45 = 45 ns, 55 = 55 ns
Voltage Range: 30 = 3.3 V typ, 18 = 1.8 V typ
E = ECC flag
Process Technology: G = 65 nm
Bus Width: 2 = × 32
Density: 6 = 16-Mbit
Family Code: 621 = MoBL SRAM family
Company ID: CY = Cypress
Document Number: 001-81598 Rev. *F
Page 15 of 20
CY62162G/CY62162GE MoBL
Package Diagram
Figure 11. 119-ball PBGA (14 × 22 × 2.4 mm) Package Outline, 51-85115
51-85115 *D
Document Number: 001-81598 Rev. *F
Page 16 of 20
CY62162G/CY62162GE MoBL
Acronyms
Document Conventions
Units of Measure
Symbol
Acronym
Description
CE
Chip Enable
Unit of Measure
CMOS
FBGA
I/O
Complementary Metal Oxide Semiconductor
Fine-Pitch Ball Grid Array
Input/Output
°C
mA
MHz
mm
µA
µs
ns
degree Celsius
milliampere
megahertz
millimeter
microampere
microsecond
nanosecond
ohm
OE
Output Enable
SRAM
WE
Static Random Access Memory
Write Enable
%
percent
pF
V
picofarad
volt
W
watt
Document Number: 001-81598 Rev. *F
Page 17 of 20
CY62162G/CY62162GE MoBL
Document History Page
Document Title: CY62162G/CY62162GE MoBL, 16-Mbit (512K × 32) Static RAM with Error-Correcting Code (ECC)
Document Number: 001-81598
Submission
Revision
ECN
Description of Change
Date
*C
4863821
07/31/2015 Changed status from Preliminary to Final.
*D
*E
6012120
6674948
01/03/2018 Updated Cypress Logo and Copyright.
09/27/2019 Updated Product Portfolio:
Added Note “This device is offered with improved I , I
and I
specifications compared
CC SB1
SB2
to the current revision with same marketing part number. The new device will be in
production from WW1952. For more information, please contact Cypress sales
representative.” and referred the same note in “CY62162G(E)30” under “Product” column.
Added Note “For next version of this device, kindly refer here. Further details about
improvement and comparison between current and new versions can be found in the
PCN193805.” and referred the same note in “CY62162G(E)30” under “Product” column.
Updated Pin Configurations:
Updated Figure 1.
Updated Figure 2.
Updated Electrical Characteristics:
Added Note “This device is offered with improved I , I
and I
specifications compared
CC SB1
SB2
to the current revision with same marketing part number. The new device will be in
production from WW1952. For more information, please contact Cypress sales
representative.” and referred the same note in I , I
, I
parameters.
CC SB1 SB2
Added Note “For next version of this device, kindly refer here. Further details about
improvement and comparison between current and new versions can be found in the
PCN193805.” and referred the same note in I , I
, I
parameters.
CC SB1 SB2
Updated Data Retention Characteristics:
Added Note “This device is offered with improved I , I
and I
specifications compared
CC SB1
SB2
to the current revision with same marketing part number. The new device will be in
production from WW1952. For more information, please contact Cypress sales
representative.” and referred the same note in I
parameter.
CCDR
Added Note “For next version of this device, kindly refer here. Further details about
improvement and comparison between current and new versions can be found in the
PCN193805.” and referred the same note in I
Updated to new template.
parameter.
CCDR
Completing Sunset Review.
*F
6822780
03/02/2020 Updated Product Portfolio:
Removed Note “This device is offered with improved I , I
and I
specifications
SB2
CC SB1
compared to the current revision with same marketing part number. The new device will be
in production from WW1952. For more information, please contact Cypress sales
representative.” and its reference in “CY62162G(E)30” under “Product” column.
Removed Note “For next version of this device, kindly refer here. Further details about
improvement and comparison between current and new versions can be found in the
PCN193805.” and its reference in “CY62162G(E)30” under “Product” column.
Updated Electrical Characteristics:
Removed Note “This device is offered with improved I , I
and I
specifications
CC SB1
SB2
compared to the current revision with same marketing part number. The new device will be
in production from WW1952. For more information, please contact Cypress sales
representative.” and its reference in I , I
, I
parameters.
CC SB1 SB2
Removed Note “For next version of this device, kindly refer here. Further details about
improvement and comparison between current and new versions can be found in the
PCN193805.” and its reference in I , I
, I
parameters.
CC SB1 SB2
Document Number: 001-81598 Rev. *F
Page 18 of 20
CY62162G/CY62162GE MoBL
Document History Page (continued)
Document Title: CY62162G/CY62162GE MoBL, 16-Mbit (512K × 32) Static RAM with Error-Correcting Code (ECC)
Document Number: 001-81598
Submission
Revision
ECN
Description of Change
Date
*F (cont.)
6822780
03/02/2020 Updated Data Retention Characteristics:
Removed Note “This device is offered with improved I , I
and I
specifications
SB2
CC SB1
compared to the current revision with same marketing part number. The new device will be
in production from WW1952. For more information, please contact Cypress sales
representative.” and its reference in I
parameter.
CCDR
Removed Note “For next version of this device, kindly refer here. Further details about
improvement and comparison between current and new versions can be found in the
PCN193805.” and its reference in I
Updated to new template.
parameter.
CCDR
Document Number: 001-81598 Rev. *F
Page 19 of 20
CY62162G/CY62162GE MoBL
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
®
Products
PSoC Solutions
®
®
Arm Cortex Microcontrollers
Automotive
cypress.com/arm
cypress.com/automotive
cypress.com/clocks
cypress.com/interface
cypress.com/iot
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP | PSoC 6 MCU
Cypress Developer Community
Clocks & Buffers
Interface
Community | Code Examples | Projects | Video | Blogs |
Training | Components
Internet of Things
Memory
Technical Support
cypress.com/memory
cypress.com/mcu
cypress.com/support
Microcontrollers
PSoC
cypress.com/psoc
Power Management ICs
Touch Sensing
USB Controllers
Wireless Connectivity
cypress.com/pmic
cypress.com/touch
cypress.com/usb
cypress.com/wireless
© Cypress Semiconductor Corporation, 2012–2020. This document is the property of Cypress Semiconductor Corporation and its subsidiaries (“Cypress”). This document, including any software or
firmware included or referenced in this document (“Software”), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries worldwide. Cypress
reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other intellectual property
rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress hereby grants
you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to modify and reproduce
the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users (either directly or
indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress’s patents that are infringed by the Software (as provided by
Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation of the
Software is prohibited.
TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. No computing
device can be absolutely secure. Therefore, despite security measures implemented in Cypress hardware or software products, Cypress shall have no liability arising out of any security breach, such
as unauthorized access to or use of a Cypress product. CYPRESS DOES NOT REPRESENT, WARRANT, OR GUARANTEE THAT CYPRESS PRODUCTS, OR SYSTEMS CREATED USING
CYPRESS PRODUCTS, WILL BE FREE FROM CORRUPTION, ATTACK, VIRUSES, INTERFERENCE, HACKING, DATA LOSS OR THEFT, OR OTHER SECURITY INTRUSION (collectively, “Security
Breach”). Cypress disclaims any liability relating to any Security Breach, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from any Security Breach. In
addition, the products described in these materials may contain design defects or errors known as errata which may cause the product to deviate from published specifications. To the extent permitted
by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any product or
circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is the
responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. “High-Risk Device”
means any device or system whose failure could cause personal injury, death, or property damage. Examples of High-Risk Devices are weapons, nuclear installations, surgical implants, and other
medical devices. “Critical Component” means any component of a High-Risk Device whose failure to perform can be reasonably expected to cause, directly or indirectly, the failure of the High-Risk
Device, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from any use of
a Cypress product as a Critical Component in a High-Risk Device. You shall indemnify and hold Cypress, its directors, officers, employees, agents, affiliates, distributors, and assigns harmless from
and against all claims, costs, damages, and expenses, arising out of any claim, including claims for product liability, personal injury or death, or property damage arising from any use of a Cypress
product as a Critical Component in a High-Risk Device. Cypress products are not intended or authorized for use as a Critical Component in any High-Risk Device except to the limited extent that (i)
Cypress’s published data sheet for the product explicitly states Cypress has qualified the product for use in a specific High-Risk Device, or (ii) Cypress has given you advance written authorization to
use the product as a Critical Component in the specific High-Risk Device and you have signed a separate indemnification agreement.
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in
the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Document Number: 001-81598 Rev. *F
Revised March 2, 2020
Page 20 of 20
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