CY62167G30-45BVXAT [INFINEON]
Asynchronous SRAM;
| 型号： | CY62167G30-45BVXAT |
| 厂家： | 
Infineon |
| 描述： | Asynchronous SRAM 静态存储器 |
| 文件： | 总19页 (文件大小：519K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY62167G Automotive
16-Mbit (1M Words × 16-Bit) Static RAM
with Error-Correcting Code (ECC)
16-Mbit (1M Words
× 16-Bit) Static RAM with Error-Correcting Code (ECC)
Data writes are performed by asserting the Write Enable input
(WE) LOW, and providing the data and address on device data
(I/O0 through I/O15) and address (A0 through A19) pins
respectively. The Byte High/Low Enable (BHE, BLE) inputs
control byte writes, and write data on the corresponding I/O lines
Features
■ AEC-Q100 qualified
■ Ultra-low standby power
❐ Typical standby current: 5.5 A
❐ Maximum standby current: 75 A
to the memory location specified. BHE controls I/O8 through
I/O15; BLE controls I/O0 through I/O7.
■ High speed: 45 ns / 55 ns
Data reads are performed by asserting the Output Enable (OE)
input and providing the required address on the address lines.
Read data is accessible on I/O lines (I/O0 through I/O15). Byte
accesses can be performed by asserting the required byte
enable signal (BHE, BLE) to read either the upper byte or the
lower byte of data from the specified address location.
■ Embedded error-correcting code (ECC) for single-bit error
correction
■ Temperature Ranges:
❐ Automotive-A: -40 C to +85 C
❐ Automotive-E: -40 C to +125 C
All I/Os (I/O0 through I/O15) are placed in a HI-Z state when the
device is deselected (CE1 HIGH / CE2 LOW for dual chip-enable
■ Operating voltage range: 2.2 V to 3.6 V
■ 1.0-V data retention
device), or control signals are de-asserted (OE, BLE, and BHE).
These devices also have a unique “Byte Power down” feature
■ TTL-compatible inputs and outputs
where if both the Byte Enables (BHE and BLE) are disabled, the
devices seamlessly switches to standby mode irrespective of the
state of the chip enable(s), thereby saving power.
■ Available in Pb-free 48-ball VFBGA and 48-pin TSOP I
packages
The CY62167G device is available in a Pb-free 48-ball VFBGA
and 48-pin TSOP I packages. The device in the 48-pin TSOP I
package can also be configured to function as a 2M words × 8
bit device.The logic block diagram is on page 2. Refer to Pin
Configurations on page 4 and the associated footnotes for
details.
Functional Description
CY62167G is high-performance CMOS low-power (MoBL)
SRAM devices with embedded ECC. This device is offered in
dual chip-enable.
Devices with dual chip-enable are accessed by asserting both
chip-enable inputs – CE1 as LOW and CE2 as HIGH.
Note
1. This device does not support automatic write-back on error detection.
Cypress Semiconductor Corporation
Document Number: 001-84902 Rev. *F
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised May 3, 2017
CY62167G Automotive
Logic Block Diagram – CY62167G
ECC ENCODE
DATAIN DRIVERS
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
1M x 16 /
2M x 8
RAM ARRAY
I/O0-I/O7
I/O8-I/O15
COLUMN DECODER
CE
BYTE
BHE
POWER DOWN
CIRCUIT
BHE
BLE
WE
CE2
CE1
OE
BLE
Document Number: 001-84902 Rev. *F
Page 2 of 19
CY62167G Automotive
Contents
Pin Configurations ...........................................................4
Product Portfolio ..............................................................4
Maximum Ratings .............................................................5
Operating Range ...............................................................5
DC Electrical Characteristics ..........................................5
Capacitance ......................................................................6
Thermal Resistance ..........................................................6
AC Test Loads and Waveforms .......................................6
Data Retention Characteristics .......................................7
Data Retention Waveform ................................................7
Switching Characteristics ................................................8
Switching Waveforms ......................................................9
Truth Table – CY62167G ................................................13
Ordering Information ......................................................14
Ordering Code Definitions .........................................14
Package Diagram ............................................................15
Acronyms ........................................................................17
Document Conventions .................................................17
Units of Measure .......................................................17
Document History Page .................................................18
Sales, Solutions, and Legal Information ......................19
Worldwide Sales and Design Support .......................19
Products ....................................................................19
PSoC® Solutions ......................................................19
Cypress Developer Community .................................19
Technical Support .....................................................19
Document Number: 001-84902 Rev. *F
Page 3 of 19
CY62167G Automotive
Pin Configurations
Figure 1. 48-ball VFBGA pinout [2]
CY62167G
1
2
4
3
A0
A3
5
6
A1
A2
CE2
OE
BLE
A
B
C
A
4
I/O BHE
8
CE1 I/O
0
A
5
A
6
I/O I/O
I/O
I/O
9
10
1
2
VCC
A
7
V
I/O
I/O
3
A17
NC
D
E
F
SS
11
Vss
A
V
CC
I/O
I/O
16
12
4
A
A
15
I/O
I/O
I/O
I/O
6
14
13
5
14
A
A
G
H
I/O
A19
WE I/O
7
13
12
15
A
A
9
A
11
A
NC
A18
10
8
Figure 2. 48-pin TSOP I pinout (Dual Chip Enable without ERR) – CY62167G [2, 3]
A15
A14
A13
A12
A11
A10
A9
A8
A19
NC
1
2
3
4
5
6
7
8
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
BYTE
Vss
I/O15/A20
I/O7
I/O14
I/O6
I/O13
I/O5
I/O12
I/O4
Vcc
I/O11
I/O3
I/O10
I/O2
I/O9
I/O1
I/O8
I/O0
OE
Vss
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
WE
CE
2
NC
BHE
BLE
A18
A17
A7
A6
A5
A4
A3
A2
A1
CE
1
A0
Product Portfolio
Power Dissipation
Operating ICC, (mA), f = fmax Standby, ISB2 (µA)
Speed
(ns)
Product
Range
VCC Range (V)
Typ [4]
Max
40.0
36.0
Typ [4]
Max
75.0
16.0
CY62167G30
Automotive-E
Automotive-A
2.2 V–3.6 V
55
45
29.0
5.5
29.0
5.5
Notes
2. NC pins are not connected internally to the die and are typically used for address expansion to a higher-density device. Refer to the respective datasheets for pin
configuration.
3. The BYTE pin in the 48-pin TSOP I package must be tied to V to use the device as a 1M × 16 SRAM. The 48-pin TSOP I package can also be used as a 2M × 8
CC
SRAM by tying the BYTE signal to V . In the 2 M × 8 configuration, pin 45 is A20, while BHE, BLE and I/O to I/O pins are not used.
SS
8
14
4. Indicates the value for the center of Distribution at 3.0 V, 25 °C and not 100% tested.
Document Number: 001-84902 Rev. *F
Page 4 of 19
CY62167G Automotive
Output current into outputs (LOW) ............................. 20 mA
Maximum Ratings
Static discharge voltage
(MIL-STD-883, Method 3015) ................................. >2001 V
Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested.
Latch-up current .....................................................>140 mA
Storage temperature ............................... –65 °C to + 150 °C
Ambient temperature
with power applied .................................. –55 °C to + 125 °C
Operating Range
Grade
Ambient Temperature
–40 C to +125 C
–40 C to +85 C
VCC
Supply voltage
to ground potential [5] .......................... –0.5 V to VCC + 0.5 V
Automotive-E
Automotive-A
2.2 V to 3.6 V
DC voltage applied to outputs
in HI-Z state [5] .................................... –0.5 V to VCC + 0.5 V
DC input voltage [5] ............................. –0.5 V to VCC + 0.5 V
DC Electrical Characteristics
Over the Operating Range
55 ns (Automotive-E) 45 ns (Automotive-A)
Parameter
Description
Test Conditions
Unit
Min Typ [6]
Max
–
Min Typ [6]
Max
–
VOH
Output HIGH 2.2 V to 2.7 V VCC = Min, IOH = –0.1 mA
2.0
2.4
–
–
–
–
–
–
–
–
–
–
–
2.0
2.4
–
–
–
–
–
–
–
–
–
–
–
V
voltage
2.7 V to 3.6 V VCC = Min, IOH = –1.0 mA
–
–
VOL
VIH
VIL
Output LOW 2.2 V to 2.7 V VCC = Min, IOL = 0.1 mA
0.4
0.4
0.4
V
V
V
voltage
2.7 V to 3.6 V VCC = Min, IOL = 2.1 mA
–
–
0.4
Input HIGH
voltage[5]
2.2 V to 2.7 V –
2.7 V to 3.6 V –
2.2 V to 2.7 V –
2.7 V to 3.6 V –
1.8
2.0
–0.3
–0.3
–4.0
–4.0
VCC + 0.3 1.8
CC + 0.3 2.0
VCC + 0.3
VCC + 0.3
0.6
V
Input LOW
voltage[5]
0.6
0.8
–0.3
–0.3
–1.0
–1.0
0.8
IIX
Input leakage current
Output leakage current
GND < VIN < VCC
+4.0
+4.0
+1.0
+1.0
A
A
GND < VOUT < VCC, Output
disabled
IOZ
ICC
VCC operating supply
current
VCC = Max,
OUT = 0 mA,
CMOS levels
f = fMAX
f =1 MHz
–
–
29.0
7.0
40.0
18.0
–
–
29.0
7.0
36.0
9.0
mA
mA
I
[7]
ISB1
Automatic power down
current – CMOS inputs;
VCC = 2.2 to 3.6 V
–
5.5
75.0
–
5.5
16.0
A
CE1 > VCC – 0.2 V or CE2 < 0.2 V
or (BHE and BLE) > VCC – 0.2 V,
VIN > VCC – 0.2 V, VIN < 0.2 V,
f = fmax (address and data only),
f = 0 (OE, and WE), VCC = VCC(max)
[7]
ISB2
Automatic power down
current – CMOS inputs;
VCC = 2.2 to 3.6 V
–
5.5
75.0
–
5.5
16.0
A
CE1 > VCC – 0.2V or CE2 < 0.2 V
or (BHE and BLE) > VCC – 0.2 V,
VIN > VCC – 0.2 V or VIN < 0.2 V,
f = 0, VCC = VCC(max)
Notes
5.
6. Indicates the value for the center of Distribution at 3.0 V, 25 °C and not 100% tested.
7. Chip enables (CE and CE ) and BHE, BLE and BYTE must be tied to CMOS levels to meet the I
V
= –2.0 V and V
= V + 2 V for pulse durations of less than 20 ns.
IL(min)
IH(max) CC
/ I
/ I
spec. Other inputs can be left floating.
1
2
SB1 SB2 CCDR
Document Number: 001-84902 Rev. *F
Page 5 of 19
CY62167G Automotive
Capacitance
Parameter [8]
Description
Input capacitance
Output capacitance
Test Conditions
Max
10
Unit
pF
CIN
TA = 25 °C, f = 1 MHz, VCC = VCC(typ)
COUT
10
pF
Thermal Resistance
Parameter [8]
Description
Test Conditions
48-ball VFBGA 48-pin TSOP I Unit
JA
Thermal resistance
(junction to ambient)
Still air, soldered on a 3 × 4.5 inch,
four-layer printed circuit board
31.50
57.99
°C/W
JC
Thermal resistance
(junction to case)
15.75
13.42
°C/W
AC Test Loads and Waveforms
Figure 3. AC Test Loads and Waveforms
ALL INPUT PULSES
90%
10%
R1
V
V
CC
OUTPUT
HIGH
90%
10%
GND
Fall Time = 1 V/ns
R2
30 pF
Rise Time = 1 V/ns
Equivalent to: THÉVENIN EQUIVALENT
INCLUDING
JIG AND
SCOPE
R
TH
OUTPUT
V
Parameters
3.0 V
Unit
R1
R2
317
351
3.0
VHIGH
V
Note
8. Tested initially and after any design or process changes that may affect these parameters.
Document Number: 001-84902 Rev. *F
Page 6 of 19
CY62167G Automotive
Data Retention Characteristics
Over the Operating Range
55 ns (Automotive-E) 45 ns (Automotive-A) Unit
Parameter
VDR
Description
Conditions
Min Typ [9] Max
Min Typ [9] Max Unit
VCC for data retention
Data-retention current
1
–
–
–
1
–
–
–
V
[10]
ICCDR
2.2 V < VCC < 3.6 V
5.5
75.0
5.5
16.0
A
CE1 > VCC 0.2 V or CE2 < 0.2 V
or (BHE and BLE) > VCC – 0.2 V,
VIN > VCC 0.2 V or VIN < 0.2 V
[11]
tCDR
Chip deselect to
data-retention time
0
–
–
–
–
0
–
–
–
–
–
[12]
tR
Operation-recovery time
55
45
ns
Data Retention Waveform
Figure 4. Data-Retention Waveform [13]
DATA RETENTION M ODE
VCC
VDR = 1.0 V
VCC(min)
tCDR
VCC(min)
tR
CE1 or
BHE. BLE
(or)
CE2
Notes
9. Indicates the value for the center of distribution at 3.0 V, 25°C and not 100% tested.
10. Chip enables (CE and CE ) and BYTE must be tied to CMOS levels to meet the I / I / I spec. Other inputs can be left floating.
SB1 SB2 CCDR
1
2
11. Tested initially and after any design or process changes that may affect these parameters.
12. Full device operation requires linear V ramp from V to V > 100 s or stable at V > 100 s.
CC(min)
CC
DR
CC(min)
13. BHE.BLE is the AND of both BHE and BLE. Deselect the chip by either disabling the chip enable signals or by disabling both BHE and BLE.
Document Number: 001-84902 Rev. *F
Page 7 of 19
CY62167G Automotive
Switching Characteristics
55 ns (Automotive-E) 45 ns (Automotive-A)
Unit
Parameter [14]
Description
Min
Max
Min
Max
Read Cycle
tRC
Read cycle time
55
–
–
55
–
45
–
–
45
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAA
Address to data valid
tOHA
tACE
tDOE
tLZOE
tHZOE
tLZCE
tHZCE
tPU
Data hold from address change
CE1 LOW and CE2 HIGH to data valid / CE LOW
OE LOW to data valid / OE LOW
OE LOW to Low Z [15]
10
–
10
–
55
25
–
45
22
–
–
–
5
5
OE HIGH to High Z [15, 16]
–
20
–
–
18
–
CE1 LOW and CE2 HIGH to Low Z [15]
CE1 HIGH and CE2 LOW to High Z [15, 16]
CE1 LOW and CE2 HIGH to power-up
CE1 HIGH and CE2 LOW to power-down
BLE / BHE LOW to data valid
10
–
10
–
20
–
18
–
0
0
tPD
–
55
55
–
–
45
45
–
tDBE
tLZBE
tHZBE
Write Cycle [17]
tWC
–
–
BLE / BHE LOW to Low Z [15]
BLE / BHE HIGH to High Z [15, 16]
5
5
–
20
–
18
Write cycle time
55
40
40
0
–
–
45
35
35
0
–
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tSCE
tAW
CE1 LOW and CE2 HIGH to write end
Address setup to write end
Address hold from write end
Address setup to write start
WE pulse width
–
–
tHA
–
–
tSA
0
–
0
–
tPWE
tBW
40
40
25
0
–
35
35
25
0
–
BLE / BHE LOW to write end
Data setup to write end
Data hold from write end
WE LOW to High Z [15, 16]
WE HIGH to Low Z [15]
–
–
tSD
–
–
tHD
–
–
tHZWE
tLZWE
–
20
–
–
18
–
10
10
Notes
14. Test conditions assume signal transition time (rise/fall) of 3 ns or less, timing reference levels of 1.5 V (for V > 3 V) and V /2 (for V < 3 V), and input pulse
CC
CC
CC
levels of 0 to 3 V (for V > 3 V) and 0 to V (for V < 3 V). Test conditions for the read cycle use output loading shown in AC Test Loads and Waveforms section, unless
CC
CC
CC
specified otherwise.
15. At any temperature and voltage condition, t
is less than t
, t
is less than t
, t
is less than t
, and t
is less than t
for any device.
HZCE
LZCE HZBE
LZBE HZOE
LZOE
HZWE
LZWE
16. t
, t
, t
, and t
transitions are measured when the outputs enter a high impedance state.
HZOE HZCE HZBE
HZWE
17. The internal write time of the memory is defined by the overlap of WE = V , CE = V , BHE or BLE or both = V , and CE = V . All signals must be ACTIVE to initiate
IL
1
IL
IL
2
IH
a write. Any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing must refer to the edge of the signal that terminates the write.
Document Number: 001-84902 Rev. *F
Page 8 of 19
CY62167G Automotive
Switching Waveforms
Figure 5. Read Cycle No. 1 of CY62167G (Address Transition Controlled) [18, 19]
tRC
ADDRESS
DATA I/O
tAA
tOHA
PREVIOUS DATAOUT
VALID
DATAOUT VALID
Figure 6. Read Cycle No. 2 (OE Controlled) [19, 20, 21]
ADDRESS
tRC
CE
tPD
tHZCE
tACE
OE
tHZOE
tDOE
tLZOE
BHE/
BLE
tDBE
tLZBE
tHZBE
HIGH
IMPEDANCE
HIGH IMPEDANCE
DATA I/O
DATAOUT VALID
tLZCE
tPU
VCC
SUPPLY
CURRENT
ISB
Notes
18. The device is continuously selected. OE = V , CE = V , BHE or BLE or both = V .
IL
IL
IL
19. WE is HIGH for read cycle.
20. For all dual chip enable devices, CE is the logical combination of CE and CE . When CE is LOW and CE is HIGH, CE is LOW; when CE is HIGH or CE is LOW,
1
2
1
2
1
2
CE is HIGH.
21. Address valid prior to or coincident with CE LOW transition.
Document Number: 001-84902 Rev. *F
Page 9 of 19
CY62167G Automotive
Switching Waveforms (continued)
Figure 7. Write Cycle No. 1 (WE Controlled) [22, 23, 24]
tWC
ADDRESS
tSCE
CE
tBW
BHE/
BLE
tAW
tHA
tSA
tPWE
WE
tLZWE
tSD
t
HZWE
tHD
DATA I/O
DATAIN VALID
Notes
22. For all dual chip enable devices, CE is the logical combination of CE and CE . When CE is LOW and CE is HIGH, CE is LOW; when CE is HIGH or CE is LOW,
1
2
1
2
1
2
CE is HIGH.
23. The internal write time of the memory is defined by the overlap of WE = V , CE = V , BHE or BLE or both = V , and CE = V . All signals must be ACTIVE to initiate
IL
1
IL
IL
2
IH
a write and any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing must refer to the edge of the signal that terminates
the write.
24. Data I/O is in HI-Z state if CE = V , or OE = V or BHE, and/or BLE = V .
IH
IH
IH
Document Number: 001-84902 Rev. *F
Page 10 of 19
CY62167G Automotive
Switching Waveforms (continued)
[25, 26, 27]
Figure 8. Write Cycle No. 2 (CE Controlled)
tWC
ADDRESS
tSA
tSCE
CE
tAW
tHA
tPWE
WE
tBW
BHE/
BLE
OE
tHZOE
tHD
tSD
DATA I/O
DATAIN VALID
Notes
25. For all dual chip enable devices, CE is the logical combination of CE and CE . When CE is LOW and CE is HIGH, CE is LOW; when CE is HIGH or CE is LOW,
1
2
1
2
1
2
CE is HIGH.
26. The internal write time of the memory is defined by the overlap of WE = V , CE = V , BHE or BLE or both = V , and CE = V . All signals must be ACTIVE to initiate
IL
1
IL
IL
2
IH
a write and any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing must refer to the edge of the signal that terminates
the write.
27. Data I/O is in high impedance state if CE = V , or OE = V or BHE, and/or BLE = V
.
IH
IH
IH
Document Number: 001-84902 Rev. *F
Page 11 of 19
CY62167G Automotive
Switching Waveforms (continued)
[28, 29, 30]
Figure 9. Write Cycle No. 3 (BHE/BLE Controlled, OE LOW)
tWC
ADDRESS
tSCE
CE
tAW
tSA
tHA
tBW
BHE/
BLE
tPWE
WE
tHZWE
tHD
tSD
tLZWE
DATA I/O
DATAIN VALID
Notes
28. For all dual chip enable devices, CE is the logical combination of CE and CE . When CE is LOW and CE is HIGH, CE is LOW; when CE is HIGH or CE is LOW,
1
2
1
2
1
2
CE is HIGH.
29. The internal write time of the memory is defined by the overlap of WE = V , CE = V , BHE or BLE or both = V , and CE = V . All signals must be ACTIVE to initiate
IL
1
IL
IL
2
IH
a write and any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing must refer to the edge of the signal that terminates
the write.
30. Data I/O is in high impedance state if CE = V , or OE = V or BHE, and/or BLE = V
.
IH
IH
IH
Document Number: 001-84902 Rev. *F
Page 12 of 19
CY62167G Automotive
Truth Table – CY62167G
CE1
CE2
WE
X
OE
X
BHE BLE
Inputs/Outputs
Mode
Power
[31]
H
X
X
X
H
L
X
X
H
L
HI-Z
HI-Z
HI-Z
Deselect/Power-down
Deselect/Power-down
Deselect/Power-down
Read
Standby (I
Standby (I
Standby (I
)
SB
[31]
X
L
X
X
)
SB
[31]
[31]
X
X
X
X
)
SB
L
L
H
H
H
L
Data Out (I/O –I/O
)
Active (I )
CC
0
15
H
L
H
L
Data Out (I/O –I/O );
Read
Active (I )
CC
0
7
HI-Z (I/O –I/O
)
8
15
L
H
H
L
L
H
HI-Z (I/O –I/O );
Read
Active (I
)
0
7
CC
Data Out (I/O –I/O
)
8
15
L
L
L
H
H
H
H
L
L
H
X
X
X
L
X
L
L
HI-Z
Output disabled
Write
Active (I
Active (I
Active (I
)
CC
Data In (I/O –I/O
)
)
CC
0
15
H
Data In (I/O –I/O );
HI-Z (I/O –I/O
Write
)
CC
0
7
)
8
15
L
H
L
X
L
H
HI-Z (I/O –I/O );
Write
Active (I
)
0
7
CC
Data In (I/O –I/O
)
8
15
Note
31. The ‘X’ (Don’t care) state for the chip enables refer to the logic state (either HIGH or LOW). Intermediate voltage levels on these pins is not permitted.
Document Number: 001-84902 Rev. *F
Page 13 of 19
CY62167G Automotive
Ordering Information
Speed
Package
Diagram
Operating
Range
Package Type
(ns)
Ordering Code
CY62167G30-55BVXE
CY62167G30-55BVXET
CY62167G30-55ZXE
CY62167G30-55ZXET
CY62167G30-45ZXA
CY62167G30-45ZXAT
CY62167G30-45BVXA
CY62167G30-45BVXAT
55
51-85150 48-ball VFBGA (6 × 8 × 1 mm) (Pb-free),
Package Code: BZ48
Automotive-E
51-85183 48-pin TSOP I (12 × 18.4 × 1 mm) (Pb-free),
Package Code: Z48A
45
51-85183 48-pin TSOP I (12 × 18.4 × 1 mm) (Pb-free),
Package Code: Z48A
Automotive-A
51-85150 48-ball VFBGA (6 × 8 × 1 mm) (Pb-free),
Package Code: BZ48
Ordering Code Definitions
X
G
XX XX
XX -
X
621
6
X
CY
7
X = blank or T
blank = Bulk; T = Tape and Reel
Temperature Range: X = E or A
E = Automotive-E; A = Automotive-A
Pb-free
Package Type: XX = BV or Z
BV = 48-ball VFBGA; Z = 48-pin TSOP I
Speed Grade: XX = 45 or 55
45 = 45 ns; 55 = 55 ns
Voltage Range: 30 = 3 V typ
Process Technology: G = 65 nm
Bus Width: 7 = × 16
Density: 6 = 16-Mbit
Family Code: 621 = MoBL SRAM family
Company ID: CY = Cypress
Document Number: 001-84902 Rev. *F
Page 14 of 19
CY62167G Automotive
Package Diagram
Figure 10. 48-ball VFBGA (6 × 8 × 1.0 mm) BV48/BZ48 Package Outline, 51-85150
51-85150 *H
Document Number: 001-84902 Rev. *F
Page 15 of 19
CY62167G Automotive
Package Diagram (continued)
Figure 11. 48-pin TSOP I (18.4 × 12 × 1.2 mm) Package Outline, 51-85183
STANDARD PIN OUT (TOP VIEW)
2X (N/2 TIPS)
0.10 C
8
0.10
2X
A2
2
0.10
2X
1
N
B
SEE DETAIL B
R
A
(c)
E
5
GAUGE PLANE
0.25 BASIC
e
9
N/2 +1
N/2
0°
5
A1
C
D1
D
4
PARALLEL TO
SEATING PLANE
L
C
0.20
2X (N/2 TIPS)
SEATING PLANE
DETAIL A
B
A
B
SEE DETAIL A
0.08MM M C A-B
b
6
7
WITH PLATING
e/2
REVERSE PIN OUT (TOP VIEW)
3
1
N
c
7
c1
X
X = A OR B
b1
BASE METAL
DETAIL B
N/2
N/2 +1
SECTION B-B
NOTES:
DIMENSIONS
SYMBOL
1. DIMENSIONS ARE IN MILLIMETERS (mm).
MIN. NOM. MAX.
A
1.20
2. PIN 1 IDENTIFIER FOR STANDARD PIN OUT (DIE UP).
0.15
0.05
A1
A2
b1
b
3. PIN 1 IDENTIFIER FOR REVERSE PIN OUT (DIE DOWN): INK OR LASER MARK.
0.95
0.17
0.17
1.00
0.20
1.05
0.23
0.27
4. TO BE DETERMINED AT THE SEATING PLANE -C- . THE SEATING PLANE IS
DEFINED AS THE PLANE OF CONTACT THAT IS MADE WHEN THE PACKAGE
LEADS ARE ALLOWED TO REST FREELY ON A FLAT HORIZONTAL SURFACE.
0.22
5. DIMENSIONS D1 AND E DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE
MOLD PROTRUSION ON E IS 0.15mm PER SIDE AND ON D1 IS 0.25mm PER SIDE.
c1
0.10
0.10
0.16
0.21
c
D
6. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08mm TOTAL IN EXCESS OF b DIMENSION AT MAX.
MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON LOWER RADIUS OR
THE FOOT. MINIMUM SPACE BETWEEN PROTRUSION AND AN ADJACENT LEAD
TO BE 0.07mm .
20.00 BASIC
18.40 BASIC
12.00 BASIC
0.50 BASIC
D1
E
e
L
0
0.50
0.60 0.70
7. THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN
0.10mm AND 0.25mm FROM THE LEAD TIP.
0°
8
0.20
R
N
0.08
8. LEAD COPLANARITY SHALL BE WITHIN 0.10mm AS MEASURED FROM THE
SEATING PLANE.
48
9. DIMENSION "e" IS MEASURED AT THE CENTERLINE OF THE LEADS.
10. JEDEC SPECIFICATION NO. REF: MO-142(D)DD.
51-85183 *F
Document Number: 001-84902 Rev. *F
Page 16 of 19
CY62167G Automotive
Acronyms
Document Conventions
Units of Measure
Symbol
Acronym
Description
BHE
BLE
byte high enable
Unit of Measure
byte low enable
chip enable
°C
MHz
A
s
mA
mm
ns
Degrees Celsius
megahertz
microamperes
microseconds
milliamperes
millimeters
nanoseconds
ohms
CE
CMOS
I/O
complementary metal oxide semiconductor
input/output
OE
output enable
SRAM
VFBGA
WE
static random access memory
very fine-pitch ball grid array
write enable
%
percent
pF
V
picofarads
volts
W
watts
Document Number: 001-84902 Rev. *F
Page 17 of 19
CY62167G Automotive
Document History Page
Document Title: CY62167G Automotive, 16-Mbit (1M Words × 16-Bit) Static RAM with Error-Correcting Code (ECC)
Document Number: 001-84902
Orig. of
Change
Submission
Date
Rev.
ECN No.
Description of Change
*C
5083752
NILE
01/13/2016 Changed status from Preliminary to Final.
*D
*E
5130998
5555173
NILE
02/12/2016 Updated Logic Block Diagram – CY62167G.
Updated Pin Configurations:
Added Note 3 and referred the same note in Figure 2.
Updated DC Electrical Characteristics:
Updated Note 7.
Updated Data Retention Characteristics:
Updated Note 10.
VINI
01/18/2017 Updated Features:
Added “AEC-Q100 qualified”.
Updated Maximum Ratings:
Updated Note 5 (Replaced “2 ns” with “20 ns”).
Updated DC Electrical Characteristics:
Replaced “55 ns (Automotive-E)” with “45 ns (Automotive-A)” in column
heading.
Replaced “55 ns (Automotive-A)” with “55 ns (Automotive-E)” in column
heading.
Changed minimum value of V parameter from 2.2 V to 2.4 V corresponding
OH
to Operating Range “2.7 V to 3.6 V”.
Changed minimum value of V parameter from 2.0 V to 1.8 V corresponding
IH
to Operating Range “2.2 V to 2.7 V”.
Updated Ordering Information:
Updated part numbers.
Updated Ordering Code Definitions.
Updated Package Diagram:
spec 51-85183 – Changed revision from *D to *E.
Updated to new template.
Completing Sunset Review.
*F
5725191
NILE
05/03/2017 Updated DC Electrical Characteristics:
Fixed typo in values of I and I parameters (both “Min” and “Max” columns).
IX
OZ
Fixed typo in values of I
and I
parameters (only “Max” column).
SB1
SB2
Updated Data Retention Characteristics:
Fixed typo in values of I parameter (only “Max” column).
CCDR
Updated to new template.
Document Number: 001-84902 Rev. *F
Page 18 of 19
CY62167G Automotive
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
®
Products
PSoC Solutions
®
®
ARM Cortex Microcontrollers
Automotive
cypress.com/arm
cypress.com/automotive
cypress.com/clocks
cypress.com/interface
cypress.com/iot
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP
Cypress Developer Community
Clocks & Buffers
Interface
Forums | WICED IOT Forums | Projects | Video | Blogs |
Training | Components
Internet of Things
Memory
Technical Support
cypress.com/memory
cypress.com/mcu
cypress.com/support
Microcontrollers
PSoC
cypress.com/psoc
Power Management ICs
Touch Sensing
USB Controllers
Wireless Connectivity
cypress.com/pmic
cypress.com/touch
cypress.com/usb
cypress.com/wireless
© Cypress Semiconductor Corporation, 2013–2017. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document,
including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other
intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress
hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to
modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users
(either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as
provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation
of the Software is prohibited.
TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. To the extent
permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any
product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is
the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products
are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or
systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the
device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any component of a device or system whose failure to perform can be reasonably
expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim,
damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other
liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products.
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in
the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Document Number: 001-84902 Rev. *F
Revised May 3, 2017
Page 19 of 19
MoBL is a registered trademark, and More Battery Life is a trademark, of Cypress Semiconductor Corporation.
相关型号：
SI9130DB
5- and 3.3-V Step-Down Synchronous ConvertersWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1-E3
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135_11
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9136_11
Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130CG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130LG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130_11
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137LG
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
©2020 ICPDF网 联系我们和版权申明