CY62168GN30-45BVXIT [INFINEON]
Asynchronous SRAM;
| 型号： | CY62168GN30-45BVXIT |
| 厂家： | 
Infineon |
| 描述： | Asynchronous SRAM 静态存储器 |
| 文件： | 总17页 (文件大小：900K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY62168GN30 MoBL
16-Mbit (2M words × 8 bits) Static RAM
16-Mbit (2M words
× 8 bits) Static RAM
devices are accessed by asserting both chip enable inputs – CE1
as LOW and CE2 as HIGH.
Features
■ Ultra-low standby power
❐ Typical standby current: 1.5 A
❐ Maximum standby current: 8 A
Write to the device by taking Chip Enable 1 (CE1) LOW and
Chip Enable 2 (CE2) HIGH and the Write Enable (WE) input
LOW. Data on the eight I/O pins (I/O0 through I/O7) is then written
into the location specified on the address pins (A0 through A20).
■ High speed: 45 ns
Read from the device by taking Chip Enable 1 (CE1) and
Output Enable (OE) LOW and Chip Enable 2 (CE2) HIGH while
forcing Write Enable (WE) HIGH. Under these conditions, the
contents of the memory location specified by the address pins
■ Wide voltage range: 2.2 V to 3.6 V
■ 1.0 V data retention
■ Transistor-transistor logic (TTL) compatible inputs and outputs
■ Available in Pb-free 48-ball VFBGA package
will appear on the I/O pins.
The eight input and output pins (I/O0 through I/O7) are placed in
a high impedance state when the device is deselected (CE1
HIGH or CE2 LOW), the outputs are disabled (OE HIGH), or a
write operation is in progress (CE1 LOW and CE2 HIGH and WE
LOW). See the Truth Table – CY62168GN30 on page 12 for a
complete description of read and write modes.
Functional Description
CY62168GN30 is high-performance CMOS low-power (MoBL)
SRAM devices. Both devices are offered in single and dual chip
enable options and in multiple pin configurations.
The CY62168GN30 device is available in a Pb-free 48-pin
VFBGA package. The logic block diagrams are on page 2.
Devices with a single chip enable input are accessed by
asserting the chip enable input (CE) LOW. Dual chip enable
Product Portfolio
Power Dissipation
Features and
Options
(see Pin
Configurations
section)
Operating ICC, (mA)
Speed
Product
Range
VCC Range (V)
Standby, ISB2 (µA)
(ns)
f = fmax
Typ[2]
Max
Typ[2]
Max
CY62168GN30[3, 4] Single or dual Chip
Enables
Industrial
2.2 V–3.6 V
45
29
35
1.5
8
Notes
1. This device does not support automatic write-back on error detection.
2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V = 3 V (for V range of 2.2 V–3.6 V), T = 25 °C.
CC
CC
A
3. This device offers improved I , I
and I
specifications compared to the previous revision with same marketing part number.
CC SB1
SB2
4. For previous version of this device, kindly referhere. Further details about improvement and comparison between old and new versions can be found in the PCN193805.
Cypress Semiconductor Corporation
Document Number: 002-28483 Rev. *A
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised March 20, 2020
CY62168GN30 MoBL
Logic Block Diagram
A
A
A
A
A
A
A
A
A
0
1
2
3
4
5
6
7
8
I/O
0
DATA IN DRIVERS
I/O
1
I/O
2
2M x 8
I/O
3
I/O
I/O
I/O
I/O
ARRAY
4
5
6
7
A
A
A
A
9
10
11
12
CE
1
POWER
DOWN
CE
2
COLUMN DECODER
WE
OE
Document Number: 002-28483 Rev. *A
Page 2 of 17
CY62168GN30 MoBL
Contents
Pin Configurations ...........................................................4
Maximum Ratings .............................................................5
Operating Range ...............................................................5
DC Electrical Characteristics ..........................................5
Capacitance ......................................................................6
Thermal Resistance ..........................................................6
AC Test Loads and Waveforms .......................................6
Data Retention Characteristics .......................................7
Data Retention Waveform ................................................7
Switching Characteristics ................................................8
Switching Waveforms ......................................................9
Truth Table – CY62168GN30 ..........................................12
Ordering Information ......................................................13
Ordering Code Definitions .........................................13
Package Diagrams ..........................................................14
Acronyms ........................................................................15
Document Conventions .................................................15
Units of Measure .......................................................15
Document History Page .................................................16
Sales, Solutions, and Legal Information ......................17
Worldwide Sales and Design Support .......................17
Products ....................................................................17
PSoC® Solutions ......................................................17
Cypress Developer Community .................................17
Technical Support .....................................................17
Document Number: 002-28483 Rev. *A
Page 3 of 17
CY62168GN30 MoBL
Pin Configurations
Figure 1. 48-ball VFBGA (6 × 8 × 1 mm) pinout [5]
CY62168GN30
1
2
3
4
5
6
A0
A2
A1
CE2
A
B
C
NC
NC
OE
NC
A3
A5
A4
A6
NC
I/O4
VCC
CE1
NC
I/O0 NC
I/O1
VSS
A7 I/O5
D
E
F
A17
A18
VCC
I/O3 NC
A16 I/O6 VSS
I/O2
A14
A15
NC
I/O7
NC
A12 A13
A9
NC
A8
NC
A19
WE
G
H
A10 A11
A20
Note
5. NC pins are not connected internally to the die and are typically used for address expansion to a higher-density device. Refer to the respective datasheets for pin
configuration.
Document Number: 002-28483 Rev. *A
Page 4 of 17
CY62168GN30 MoBL
DC input voltage[6] .............................. –0.5 V to VCC + 0.5 V
Output current into outputs (LOW) ............................. 20 mA
Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested.
Static discharge voltage
(MIL-STD-883, Method 3015) ................................. >2001 V
Storage temperature ............................... –65 °C to + 150 °C
Latch-up current .....................................................>140 mA
Ambient temperature
with power applied .................................. –55 °C to + 125 °C
Operating Range
Supply voltage to ground potential ...................–0.5 V to 6 V
[7]
Grade
Ambient Temperature
VCC
DC voltage applied to outputs
Industrial
–40 C to +85 C
2.2 V to 3.6 V
in High Z state[6] .................................. –0.5 V to VCC + 0.5 V
DC Electrical Characteristics
Over the operating range of –40 C to 85 C
45 ns
Typ[8]
Parameter
Description
Test Conditions
Unit
Min
2.0
2.4
–
Max
–
VOH
Output HIGH
voltage
2.2 V to 2.7 V VCC = Min, IOH = –0.1 mA
2.7 V to 3.6 V VCC = Min, IOH = –1.0 mA
2.2 V to 2.7 V VCC = Min, IOL = 0.1 mA
2.7 V to 3.6 V VCC = Min, IOL = 2.1 mA
–
–
V
V
–
VOL
VIH
VIL
Output LOW
voltage
–
0.4
V
–
–
0.4
V
Input HIGH
voltage
2.2 V to 2.7 V
2.7 V to 3.6 V
2.2 V to 2.7 V
2.7 V to 3.6 V
–
1.8
2.0
–0.3
–0.3
–1.0
–1.0
–
–
VCC + 0.3
VCC + 0.3
0.6
V
–
–
V
Input LOW
voltage[6]
–
–
V
–
–
0.8
V
IIX
Input leakage current
GND < VIN < VCC
–
+1.0
+1.0
35.0
A
A
mA
IOZ
Output leakage current
VCC operating supply current
GND < VOUT < VCC, Output disabled
–
[9, 10]
ICC
VCC = Max,
IOUT = 0 mA,
CMOS levels
f = 22.22 MHz
(45 ns)
29.0
f = 1 MHz
–
–
7.0
1.5
9.0
8.0
mA
[9, 10, 11]
ISB1
Automatic power down current – CE1 > VCC – 0.2 V or CE2 < 0.2 V,
CMOS inputs;
VCC = 2.2 to 3.6 V
A
VIN > VCC – 0.2 V, VIN < 0.2 V,
f = fmax (address and data only),
f = 0 (OE, and WE), VCC = VCC(max)
[9, 10, 12]
ISB2
Automatic power down current – CE1 > VCC – 0.2 V or 25 °C[13]
–
–
–
–
1.5
–
3.0[13]
3.5[13]
6.5[13]
8.0
A
A
A
A
CMOS inputs;
CE2 < 0.2 V,
40 °C[13]
70 °C[13]
85 °C
VCC = 2.2 to 3.6 V
VIN > VCC – 0.2 V or
VIN < 0.2 V,
–
–
f = 0, VCC = VCC(max)
Notes
6.
V
= –2.0 V and V
= V + 2 V for pulse durations of less than 20 ns.
IH(max) CC
IL(min)
7. Full Device AC operation assumes a 100 µs ramp time from 0 to V
and 200 µs wait time after V stabilization.
CC(min)
CC
8. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V = 3 V (for V range of 2.2 V–3.6 V), T = 25 °C.
CC
CC
A
9. This device offers improved I , I
and I
specifications compared to the previous revision with same marketing part number.
CC SB1
SB2
10. For previous version of this device, kindly refer here. Further details about improvement and comparison between old and new versions can be found in the PCN193805.
11. This parameter is guaranteed by design and is not tested.
12. Chip enables (CE and CE ) must be tied to CMOS levels to meet the I
/I
/I
spec. Other inputs can be left floating.
1
2
SB1 SB2 CCDR
13. The I
limits at 25 °C, 40 °C, 70 °C and typical limit at 85 °C are guaranteed by design and not 100% tested.
SB2
Document Number: 002-28483 Rev. *A
Page 5 of 17
CY62168GN30 MoBL
Capacitance
Parameter [14]
Description
Input capacitance
Output capacitance
Test Conditions
Max
10
Unit
pF
CIN
TA = 25 °C, f = 1 MHz, VCC = VCC(typ)
COUT
10
pF
Thermal Resistance
Parameter [14]
Description
Test Conditions
48-ball VFBGA Unit
JA
Thermal resistance
(junction to ambient)
Still air, soldered on a 3 × 4.5 inch, four-layer printed circuit
board
31.50
°C/W
JC
Thermal resistance
(junction to case)
15.75
°C/W
AC Test Loads and Waveforms
Figure 2. AC Test Loads and Waveforms
ALL INPUT PULSES
V
10%
R1
V
CC
OUTPUT
HIGH
90%
10%
90%
GND
Fall Time = 1 V/ns
R2
30 pF
Rise Time = 1 V/ns
INCLUDING
JIG AND
SCOPE
Equivalent to: THÉVENIN EQUIVALENT
R
TH
OUTPUT
V
TH
Parameters
1.8 V
13500
10800
6000
0.8
2.5 V
3.0 V
1103
1554
645
5.0 V
1800
990
Unit
R1
R2
16667
15385
8000
1.2
RTH
VTH
VHIGH
639
1.75
3.0
1.77
5.0
V
1.8
2.5
V
Note
14. Tested initially and after any design or process changes that may affect these parameters.
Document Number: 002-28483 Rev. *A
Page 6 of 17
CY62168GN30 MoBL
Data Retention Characteristics
Over the Operating Range
Parameter
VDR
Description
VCC for data retention
Data retention current
Conditions
Min
1.0
–
Typ[15]
Max
–
Unit
V
–
–
[16, 17, 18, 19]
ICCDR
1.2 V < VCC < 2.2 V,
16.0
A
CE1 > VCC 0.2 V or CE2 < 0.2 V,
VIN > VCC 0.2 V or VIN < 0.2 V
2.2 V < VCC < 3.6 V or
4.5 V < VCC < 5.5 V,
–
–
8.0
A
CE1 > VCC 0.2 V or CE2 < 0.2 V,
VIN > VCC 0.2 V or VIN < 0.2 V
[20]
tCDR
Chip deselect to data retention
time
0
–
–
–
–
–
[20, 21]
tR
Operation recovery time
45/55
ns
Data Retention Waveform
Figure 3. Data Retention Waveform
D A T A R E T E N T IO N M O D E
V C C
V D R = 1 .0 V
V C C (m in )
tC D R
V C C (m in )
t R
C E 1
(o r )
C E 2
Notes
15. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V = 3 V (for V range of 2.2 V–3.6 V), T = 25 °C.
CC
CC
A
16. Chip enables (CE and CE ) must be tied to CMOS levels to meet the I /I /I spec. Other inputs can be left floating.
1
2
SB1 SB2 CCDR
17. I
is guaranteed only after device is first powered up to V
and brought down to V
.
DR
CCDR
CC(min)
18. This device offers improved I , I
and I
specifications compared to the previous revision with same marketing part number.
CC SB1
SB2
19. For previous version of this device, kindly refer here. Further details about improvement and comparison between old and new versions can be found in the PCN193805.
20. These parameters are guaranteed by design.
21. Full device operation requires linear V ramp from V to V
> 100 s or stable at V
> 100 s.
CC
DR
CC(min)
CC(min)
Document Number: 002-28483 Rev. *A
Page 7 of 17
CY62168GN30 MoBL
Switching Characteristics
45 ns
Unit
Parameter [22, 23]
Description
Min
Max
Read Cycle
tRC
Read cycle time
45.0
–
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAA
Address to data valid
Data hold from address change
45.0
–
tOHA
tACE
tDOE
tLZOE
tHZOE
tLZCE
tHZCE
10.0
–
CE1 LOW and CE2 HIGH to data valid
OE LOW to data valid
OE LOW to Low Z [23, 24]
45.0
22.0
–
–
5.0
–
OE HIGH to High Z [23, 24, 25]
18.0
–
CE1 LOW and CE2 HIGH to Low Z [23, 24]
CE1 HIGH and CE2 LOW to High Z [23, 24, 25]
CE1 LOW and CE2 HIGH to power-up
CE1 HIGH and CE2 LOW to power-down
10.0
–
18.0
–
[26]
tPU
0
[26]
tPD
–
45.0
Write Cycle[27, 28]
tWC
tSCE
tAW
Write cycle time
45.0
35.0
35.0
0
–
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CE1 LOW and CE2 HIGH to write end
Address setup to write end
Address hold from write end
Address setup to write start
WE pulse width
–
tHA
–
tSA
0
–
tPWE
tSD
35.0
25.0
0
–
Data setup to write end
Data hold from write end
WE LOW to High Z [23, 24, 25]
WE HIGH to Low Z [23, 24]
–
tHD
–
tHZWE
tLZWE
–
18.0
–
10.0
Notes
22. Test conditions assume signal transition time (rise/fall) of 3 ns or less, timing reference levels of 1.5 V (for V > 3 V) and V /2 (for V < 3 V), and input pulse levels
CC
CC
CC
of 0 to 3 V (for V > 3 V) and 0 to V (for V < 3V). Test conditions for the read cycle use output loading shown in AC Test Loads and Waveforms section, unless specified
CC
CC
CC
otherwise.
23. At any temperature and voltage condition, t
is less than t
, t
is less than t
, and t
is less than t
for any device.
HZCE
LZCE HZOE
LZOE
HZWE
LZWE
24. Tested initially and after any design or process changes that may affect these parameters.
25. t , t , and t transitions are measured when the outputs enter a high impedance state.
HZOE HZCE
HZWE
26. These parameters are guaranteed by design and are not tested.
27. The internal write time of the memory is defined by the overlap of WE = V , CE = V , and CE = V . All signals must be ACTIVE to initiate a write and any of these
IL
1
IL
2
IH
signals can terminate a write by going INACTIVE. The data input setup and hold timing must refer to the edge of the signal that terminates the write.
28. The minimum write cycle pulse width for write cycle No. 2 (WE Controlled, OE Low) should be equal to he sum of t
and t
.
HZWE
SD
Document Number: 002-28483 Rev. *A
Page 8 of 17
CY62168GN30 MoBL
Switching Waveforms
Figure 4. Read Cycle No. 1 of CY62168GN (Address Transition Controlled) [29, 30]
tRC
ADDRESS
DATA I/O
tAA
tOHA
PREVIOUS DATAOUT
VALID
DATAOUT VALID
Figure 5. Read Cycle No. 2 (OE Controlled) [30, 31, 32]
ADDRESS
tRC
CE
tPD
tHZCE
tACE
OE
tHZOE
tDOE
tLZOE
HIGH
IMPEDANCE
HIGH IMPEDANCE
DATA I/O
DATAOUT VALID
tLZCE
tPU
VCC
SUPPLY
CURRENT
ISB
Notes
29. The device is continuously selected. OE = V , CE = V .
IL
IL
30. WE is HIGH for read cycle.
31. For all dual chip enable devices, CE is the logical combination of CE and CE . When CE is LOW and CE is HIGH, CE is LOW; when CE is HIGH or CE is LOW,
1
2
1
2
1
2
CE is HIGH.
32. Address valid prior to or coincident with CE LOW transition.
Document Number: 002-28483 Rev. *A
Page 9 of 17
CY62168GN30 MoBL
Switching Waveforms (continued)
Figure 6. Write Cycle No. 1 (WE Controlled) [33, 34, 35]
tW
C
A D D R E S S
tS C E
C E
tA W
tS A
tH A
tP W
E
W E
O E
tH Z O
tH D
E
tS D
Note 36
D A T A I/O
D A T A IN V A L ID
Notes
33. For all dual chip enable devices, CE is the logical combination of CE and CE . When CE is LOW and CE is HIGH, CE is LOW; when CE is HIGH or CE is LOW,
1
2
1
2
1
2
CE is HIGH.
34. The internal write time of the memory is defined by the overlap of WE = V , CE = V , and CE = V . All signals must be ACTIVE to initiate a write and any of these
IL
1
IL
2
IH
signals can terminate a write by going INACTIVE. The data input setup and hold timing must refer to the edge of the signal that terminates the write.
35. Data I/O is in the high-impedance state if CE = V , or OE = V
.
IH
IH
36. During this period, the I/Os are in output state. Do not apply input signals.
Document Number: 002-28483 Rev. *A
Page 10 of 17
CY62168GN30 MoBL
Switching Waveforms (continued)
Figure 7. Write Cycle No. 2 (WE Controlled, OE Low) [37, 38, 39, 40]
tWC
ADDRESS
tSCE
CE
tAW
tHA
tSA
tPWE
WE
tLZWE
tSD
t
HZWE
tHD
Note 41
DATA I/O
DATA VALID
IN
Figure 8. Write Cycle No. 3 (CE Controlled) [37, 38, 39]
tWC
ADDRESS
tSA
tSCE
CE
tAW
tHA
tPWE
WE
OE
tHZOE
tHD
tSD
Note 41
DATA I/O
DATA VALID
IN
Notes
37. For all dual chip enable devices, CE is the logical combination of CE and CE . When CE is LOW and CE is HIGH, CE is LOW; when CE is HIGH or CE is LOW,
1
2
1
2
1
2
CE is HIGH.
38. The internal write time of the memory is defined by the overlap of WE = V , CE = V , and CE = V . All signals must be ACTIVE to initiate a write and any of these
IL
1
IL
2
IH
signals can terminate a write by going INACTIVE. The data input setup and hold timing must refer to the edge of the signal that terminates the write.
39. Data I/O is in high impedance state if CE = V , or OE = V
.
IH
IH
40. The minimum write cycle pulse width should be equal to the sum of the t
41. During this period I/O are in the output state. Do not apply input signals.
and t
.
SD
HZWE
Document Number: 002-28483 Rev. *A
Page 11 of 17
CY62168GN30 MoBL
Truth Table – CY62168GN30
CE1
CE2
X[42]
L
WE
X[42]
X[42]
H
OE
I/Os
Mode
Deselect/Power down
Deselect/Power down
Read
Power
H
X[42] High Z
X[42] High Z
Standby (ISB2
Standby (ISB2
)
)
X[42]
L
H
L
H
X
Data Out (I/O0–I/O7)
High Z
Active (ICC
Active (ICC
Active (ICC
)
)
)
L
H
H
Output disabled
Write
L
H
L
Data In (I/O0–I/O7)
Note
42. The ‘X’ (Don’t care) state for the chip enables refer to the logic state (either HIGH or LOW). Intermediate voltage levels on these pins is not permitted.
Document Number: 002-28483 Rev. *A
Page 12 of 17
CY62168GN30 MoBL
Ordering Information
Speed
(ns)
Package
Diagram
Operating
Range
Package Type (all Pb-free)
Ordering Code
45
CY62168GN30-45BVXI
CY62168GN30-45BVXIT
51-85150 48-ball VFBGA
Industrial
48-ball VFBGA, Tape and Reel
Ordering Code Definitions
G
X
X
XX BV
XX -
X
I
6
621
CY
8
X = blank or T
blank = Bulk; T = Tape and Reel
Temperature Range:
I = Industrial
Pb-free
Package Type:
BV = 48-ball VFBGA
Speed Grade: XX = 45
45 = 45 ns
Voltage Range: XX = 30
30 = 3 V typ
X = blank or E
blank = without ERR output;
E = with ERR output, Single bit error correction indicator
Process Technology: G = 65 nm
Bus Width: 8 = × 8
Density: 6 = 16-Mbit
Family Code: MoBL SRAM family
Company ID: CY = Cypress
Document Number: 002-28483 Rev. *A
Page 13 of 17
CY62168GN30 MoBL
Package Diagrams
Figure 9. 48-ball VFBGA (6 × 8 × 1.0 mm) Package Outline, 51-85150
51-85150 *I
Document Number: 002-28483 Rev. *A
Page 14 of 17
CY62168GN30 MoBL
Acronyms
Document Conventions
Units of Measure
Symbol
Acronym
Description
CE
Chip Enable
Unit of Measure
CMOS
I/O
Complementary Metal Oxide Semiconductor
Input/Output
°C
MHz
A
s
mA
mm
ns
degree Celsius
megahertz
microampere
microsecond
milliampere
millimeter
nanosecond
ohm
OE
Output Enable
SRAM
VFBGA
WE
Static Random Access Memory
Very Fine-Pitch Ball Grid Array
Write Enable
%
percent
pF
V
picofarad
volt
W
watt
Document Number: 002-28483 Rev. *A
Page 15 of 17
CY62168GN30 MoBL
Document History Page
Document Title: CY62168GN30 MoBL, 16-Mbit (2M words × 8 bits) Static RAM
Document Number: 002-28483
Submission
Rev.
ECN No.
Description of Change
Date
**
6680216
6834957
10/06/2019 New data sheet.
*A
03/20/2020 Updated Product Portfolio:
Updated Note 3.
Updated DC Electrical Characteristics:
Updated Note 9.
Updated Data Retention Characteristics:
Updated Note 18.
Updated to new template.
Document Number: 002-28483 Rev. *A
Page 16 of 17
CY62168GN30 MoBL
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© Cypress Semiconductor Corporation, 2019–2020. This document is the property of Cypress Semiconductor Corporation and its subsidiaries (“Cypress”). This document, including any software or
firmware included or referenced in this document (“Software”), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries worldwide. Cypress
reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other intellectual property
rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress hereby grants
you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to modify and reproduce
the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users (either directly or
indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress’s patents that are infringed by the Software (as provided by
Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation of the
Software is prohibited.
TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. No computing
device can be absolutely secure. Therefore, despite security measures implemented in Cypress hardware or software products, Cypress shall have no liability arising out of any security breach, such
as unauthorized access to or use of a Cypress product. CYPRESS DOES NOT REPRESENT, WARRANT, OR GUARANTEE THAT CYPRESS PRODUCTS, OR SYSTEMS CREATED USING
CYPRESS PRODUCTS, WILL BE FREE FROM CORRUPTION, ATTACK, VIRUSES, INTERFERENCE, HACKING, DATA LOSS OR THEFT, OR OTHER SECURITYINTRUSION (collectively, “Security
Breach”). Cypress disclaims any liability relating to any Security Breach, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from any Security Breach. In
addition, the products described in these materials may contain design defects or errors known as errata which may cause the product to deviate from published specifications. To the extent permitted
by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any product or
circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is the
responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. “High-Risk Device”
means any device or system whose failure could cause personal injury, death, or property damage. Examples of High-Risk Devices are weapons, nuclear installations, surgical implants, and other
medical devices. “Critical Component” means any component of a High-Risk Device whose failure to perform can be reasonably expected to cause, directly or indirectly, the failure of the High-Risk
Device, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from any use of
a Cypress product as a Critical Component in a High-Risk Device. You shall indemnify and hold Cypress, its directors, officers, employees, agents, affiliates, distributors, and assigns harmless from
and against all claims, costs, damages, and expenses, arising out of any claim, including claims for product liability, personal injury or death, or property damage arising from any use of a Cypress
product as a Critical Component in a High-Risk Device. Cypress products are not intended or authorized for use as a Critical Component in any High-Risk Device except to the limited extent that (i)
Cypress’s published data sheet for the product explicitly states Cypress has qualified the product for use in a specific High-Risk Device, or (ii) Cypress has given you advance written authorization to
use the product as a Critical Component in the specific High-Risk Device and you have signed a separate indemnification agreement.
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in
the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Document Number: 002-28483 Rev. *A
Revised March 20, 2020
Page 17 of 17
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