CY7C1441KVE33-133AXC [INFINEON]
Synchronous SRAM with ECC;型号: | CY7C1441KVE33-133AXC |
厂家: | Infineon |
描述: | Synchronous SRAM with ECC 静态存储器 |
文件: | 总33页 (文件大小:1068K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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Infineon continues to support existing part numbers. Please continue to use the
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CY7C1441KV33
CY7C1443KV33
CY7C1441KVE33
36-Mbit (1M × 36/2M × 18)
Flow-Through SRAM (With ECC)
36-Mbit (1M
× 36/2M × 18) Flow-Through SRAM (With ECC)
Features
Functional Description
■ Supports 133-MHz bus operations
■ 1M × 36/2M × 18 common I/O
■ 3.3 V core power supply
The CY7C1441KV33/CY7C1443KV33/CY7C1441KVE33 are
3.3 V, 1M × 36/2M × 18/1M × 36 synchronous flow-through
SRAMs, respectively designed to interface with high-speed
microprocessors with minimum glue logic. Maximum access
delay from clock rise is 6.5 ns (133 MHz version). A 2-bit on-chip
counter captures the first address in a burst and increments the
address automatically for the rest of the burst access. All
synchronous inputs are gated by registers controlled by a
positive-edge-triggered Clock (CLK) input. The synchronous
inputs include all addresses, all data inputs, address-pipelining
Chip Enable (CE1), depth-expansion Chip Enables (CE2 and
CE3), Burst Control inputs (ADSC, ADSP, and ADV), Write
Enables (BWx, and BWE), and Global Write (GW).
Asynchronous inputs include the Output Enable (OE) and the ZZ
pin.
■ 2.5 V or 3.3 V I/O power supply
■ Fast clock-to-output times
❐ 6.5 ns (133 MHz version)
■ Provide high-performance 2-1-1-1 access rate
■ User-selectable burst counter supporting Intel Pentium
interleaved or linear burst sequences
■ Separate processor and controller address strobes
■ Synchronous self-timed write
■ Asynchronous output enable
CY7C1441KVE33
The CY7C1441KV33/CY7C1443KV33/
allow
either interleaved or linear burst sequences, selected by the
MODE input pin. A HIGH selects an interleaved burst sequence,
while a LOW selects a linear burst sequence. Burst accesses
can be initiated with the Processor Address Strobe (ADSP) or the
cache Controller Address Strobe (ADSC) inputs. Address
advancement is controlled by the Address Advancement (ADV)
input.
■ CY7C1441KV33, CY7C1443KV33, and CY7C1441KVE33 are
available in JEDEC-standard 100-pin TQFP and 165-ball
FBGA Pb-free packages.
■ IEEE 1149.1 JTAG-Compatible Boundary Scan
■ “ZZ” Sleep Mode option
■ On-chip error correction code (ECC) to reduce soft error rate
(SER)
Addresses and chip enables are registered at rising edge of
clock when either Address Strobe Processor (ADSP) or Address
Strobe Controller (ADSC) are active. Subsequent burst
addresses can be internally generated as controlled by the
Advance pin (ADV).
The
CY7C1441KV33/CY7C1443KV33/CY7C1441KVE33
operate from a +3.3 V core power supply while all outputs may
operate with either a +2.5 V or +3.3 V supply. All inputs and
outputs are JEDEC-standard JESD8-5-compatible.
Selection Guide
Description
Maximum access time
133 MHz
6.5
Unit
ns
Maximum operating current
× 18
× 36
150
mA
170
Cypress Semiconductor Corporation
Document Number: 001-66677 Rev. *J
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised December 5, 2019
CY7C1441KV33
CY7C1443KV33
CY7C1441KVE33
Logic Block Diagram – CY7C1441KV33
ADDRESS
REGISTER
A0, A1,
A
A
[1:0]
MODE
ADV
CLK
Q1
Q0
BURST
COUNTER
AND LOGIC
CLR
ADSC
ADSP
DQ
BYTE
WRITE REGISTER
D, DQP D
DQ
BYTE
WRITE REGISTER
D, DQP D
BW
D
DQ
BYTE
WRITE REGISTER
C, DQP C
DQ
BYTE
WRITE REGISTER
C, DQP C
BW
C
OUTPUT
BUFFERS
DQ s
MEMORY
ARRAY
SENSE
AMPS
DQP
DQP
DQP
DQP
A
DQ
BYTE
WRITE REGISTER
B, DQP B
B
C
D
DQ
BYTE
WRITE REGISTER
B, DQP B
BW
B
DQ
BYTE
WRITE REGISTER
A, DQP A
DQ
A, DQPA
BW
A
BYTE
BWE
WRITE REGISTER
INPUT
GW
REGISTERS
ENABLE
REGISTER
CE1
CE2
CE3
OE
SLEEP
CONTROL
ZZ
Logic Block Diagram – CY7C1443KV33
ADDRESS
REGISTER
A0,A1,A
A[1:0]
MODE
Q1
ADV
CLK
BURST
COUNTER AND
LOGIC
CLR
Q0
ADSC
ADSP
DQ
B,DQP B
DQ
B,DQP B
WRITE DRIVER
WRITE REGISTER
BW
B
MEMORY
ARRAY
OUTPUT
BUFFERS
DQs
DQP
DQP
SENSE
AMPS
A
B
DQ
A,DQP A
DQ A,DQP A
WRITE REGISTER
WRITE DRIVER
BW
A
BWE
GW
INPUT
REGISTERS
ENABLE
REGISTER
CE
CE
1
2
3
CE
OE
SLEEP
CONTROL
ZZ
Document Number: 001-66677 Rev. *J
Page 2 of 32
CY7C1441KV33
CY7C1443KV33
CY7C1441KVE33
Logic Block Diagram – CY7C1441KVE33
ADDRESS
REGISTER
A0, A1, A
A[1:0]
MODE
ADV
CLK
Q1
Q0
BURST
COUNTER
AND LOGIC
CLR
ADSC
ADSP
DQ
BYTE
WRITE REGISTER
D, DQPD
DQ
BYTE
WRITE REGISTER
D, DQPD
BWD
DQ
BYTE
WRITE REGISTER
C, DQPC
DQ
BYTE
WRITE REGISTER
C, DQPC
BW
C
ECC
DECODER
OUTPUT
BUFFERS
DQs
MEMORY
ARRAY
SENSE
AMPS
DQP
DQP
DQP
A
DQ
BYTE
WRITE REGISTER
B, DQPB
B
C
DQ
BYTE
WRITE REGISTER
B, DQPB
BW
B
DQP
D
DQ
BYTE
WRITE REGISTER
A, DQPA
DQ
BYTE
WRITE REGISTER
A, DQPA
BW
A
BWE
ECC
ENCODER
INPUT
REGISTERS
GW
ENABLE
REGISTER
CE1
CE2
CE3
OE
SLEEP
CONTROL
ZZ
Document Number: 001-66677 Rev. *J
Page 3 of 32
CY7C1441KV33
CY7C1443KV33
CY7C1441KVE33
Contents
Pin Configurations ...........................................................5
Pin Definitions ..................................................................7
Functional Overview ........................................................8
Single Read Accesses ................................................8
Single Write Accesses Initiated by ADSP ...................8
Single Write Accesses Initiated by ADSC ...................9
Burst Sequences .........................................................9
Sleep Mode .................................................................9
On-Chip ECC ..............................................................9
Interleaved Burst Address Table .................................9
Linear Burst Address Table .........................................9
ZZ Mode Electrical Characteristics ..............................9
Truth Table ......................................................................10
Partial Truth Table for Read/Write ................................11
Partial Truth Table for Read/Write ................................11
IEEE 1149.1 Serial Boundary Scan (JTAG) ..................12
Disabling the JTAG Feature ......................................12
Test Access Port (TAP) .............................................12
PERFORMING A TAP RESET ..................................12
TAP REGISTERS ......................................................12
TAP Instruction Set ...................................................13
TAP Controller State Diagram .......................................14
TAP Controller Block Diagram ......................................14
TAP Timing ......................................................................14
TAP AC Switching Characteristics ...............................15
3.3 V TAP AC Test Conditions .......................................15
3.3 V TAP AC Output Load Equivalent .........................15
2.5 V TAP AC Test Conditions .......................................15
2.5 V TAP AC Output Load Equivalent .........................15
TAP DC Electrical Characteristics
and Operating Conditions .............................................16
Identification Register Definitions ................................17
Scan Register Sizes .......................................................17
Identification Codes .......................................................17
Boundary Scan Order ....................................................18
Maximum Ratings ...........................................................19
Operating Range .............................................................19
Neutron Soft Error Immunity .........................................19
Electrical Characteristics ...............................................19
DC Characteristics ....................................................19
Capacitance ....................................................................21
Thermal Resistance ........................................................21
AC Test Loads and Waveforms .....................................21
Switching Characteristics ..............................................22
Timing Diagrams ............................................................23
Ordering Information ......................................................27
Ordering Code Definitions .........................................27
Package Diagrams ..........................................................28
Acronyms ........................................................................30
Document Conventions .................................................30
Units of Measure .......................................................30
Document History Page .................................................31
Sales, Solutions, and Legal Information ......................32
Worldwide Sales and Design Support .......................32
Products ....................................................................32
PSoC® Solutions ......................................................32
Cypress Developer Community .................................32
Technical Support .....................................................32
Document Number: 001-66677 Rev. *J
Page 4 of 32
CY7C1441KV33
CY7C1443KV33
CY7C1441KVE33
Pin Configurations
Figure 1. 100-pin TQFP Pinout
DQPC
1
DQPB
DQB
DQB
VDDQ
VSSQ
DQB
DQB
DQB
DQB
VSSQ
VDDQ
DQB
DQB
VSS
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC
NC
NC
VDDQ
VSSQ
NC
A
NC
NC
VDDQ
VSSQ
NC
DQPA
DQA
DQA
VSSQ
VDDQ
DQA
DQA
VSS
NC
1
2
3
4
5
6
7
8
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQC
2
DQC
VDDQ
VSSQ
DQC
3
4
5
6
DQC
7
NC
DQC
8
DQB
DQB
VSSQ
VDDQ
DQB
DQB
NC
VDD
NC
VSS
DQB
DQB
VDDQ
VSSQ
DQB
DQB
DQPB
NC
DQC
9
10
11
9
VSSQ
VDDQ
DQC
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
12
DQC
13
NC
14
VDD
NC
VSS
NC
VDD
ZZ
15
CY7C1443KV33
(2M × 18)
CY7C1441KV33/CY7C1441KVE33
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
VDD
ZZ
(1M × 36)
DQD
DQD
VDDQ
VSSQ
DQD
DQD
DQD
DQD
VSSQ
VDDQ
DQD
DQD
DQPD
DQA
DQA
VDDQ
VSSQ
DQA
DQA
DQA
DQA
VSSQ
VDDQ
DQA
DQA
DQPA
DQA
DQA
VDDQ
VSSQ
DQA
DQA
NC
NC
VSSQ
VDDQ
NC
NC
NC
VSSQ
VDDQ
NC
NC
NC
Document Number: 001-66677 Rev. *J
Page 5 of 32
CY7C1441KV33
CY7C1443KV33
CY7C1441KVE33
Pin Configurations (continued)
Figure 2. 165-ball FBGA Pinout
CY7C1441KV33 (1M × 36)
1
2
A
3
CE1
4
BWC
5
BWB
6
CE3
7
8
9
ADV
10
A
11
NC
NC/288M
NC/144M
DQPC
BWE
GW
VSS
VSS
ADSC
A
B
C
D
A
CE2
VDDQ
VDDQ
BWD
VSS
BWA
VSS
VSS
CLK
VSS
VSS
OE
VSS
VDD
ADSP
VDDQ
VDDQ
A
NC/576M
DQPB
DQB
NC
DQC
NC/1G
DQB
DQC
VDD
DQC
DQC
DQC
NC
DQC
DQC
DQC
NC
VDDQ
VDDQ
VDDQ
NC
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
NC
DQB
DQB
DQB
NC
DQB
DQB
DQB
ZZ
E
F
G
H
J
DQD
DQD
DQD
DQD
DQD
DQD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
DQA
DQA
DQA
DQA
DQA
DQA
K
L
DQD
DQPD
NC
DQD
NC
VDDQ
VDDQ
A
VDD
VSS
A
VSS
NC
VSS
A
VSS
NC
VDD
VSS
A
VDDQ
VDDQ
A
DQA
NC
A
DQA
DQPA
A
M
N
P
NC/72M
TDI
A1
TDO
A0
MODE
A
A
A
TMS
TCK
A
A
A
A
R
Document Number: 001-66677 Rev. *J
Page 6 of 32
CY7C1441KV33
CY7C1443KV33
CY7C1441KVE33
Pin Definitions
Name
I/O
Description
A0, A1, A
Input-Synchronous Address Inputs Used to Select One of the Address Locations. Sampled at the
rising edge of the CLK if ADSP or ADSC is active LOW, and CE1, CE2, and CE3 are
sampled active. A[1:0] feed the 2-bit counter.
BWA, BWB, BWC, BWD Input-Synchronous Byte Write Select Inputs, Active LOW. Qualified with BWE to conduct byte writes to
the SRAM. Sampled on the rising edge of CLK.
GW
Input-Synchronous Global Write Enable Input, Active LOW. When asserted LOW on the rising edge of
CLK, a global write is conducted (ALL bytes are written, regardless of the values on
BWX and BWE).
CLK
CE1
Input-Clock
Clock Input. Used to capture all synchronous inputs to the device. Also used to
increment the burst counter when ADV is asserted LOW, during a burst operation.
Input-Synchronous Chip Enable 1 Input, Active LOW. Sampled on the rising edge of CLK. Used in
conjunction with CE2 and CE3 to select/deselect the device. ADSP is ignored if CE1
is HIGH. CE1 is sampled only when a new external address is loaded.
CE2
CE3
Input-Synchronous Chip Enable 2 Input, Active HIGH. Sampled on the rising edge of CLK. Used in
conjunction with CE1 and CE3 to select/deselect the device. CE2 is sampled only when
a new external address is loaded.
Input-Synchronous Chip Enable 3 Input, Active LOW. Sampled on the rising edge of CLK. Used in
conjunction with CE1 and CE2 to select/deselect the device. CE3 is assumed active
throughout this document for BGA. CE3 is sampled only when a new external address
is loaded.
OE
Input-Asynchronous Output Enable, Asynchronous Input, Active LOW. Controls the direction of the I/O
pins. When LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins
are tristated, and act as input data pins. OE is masked during the first clock of a read
cycle when emerging from a deselected state.
ADV
Input-Synchronous Advance Input Signal, Sampled on the Rising Edge of CLK. When asserted, it
automatically increments the address in a burst cycle.
ADSP
Input-Synchronous Address Strobe from Processor, Sampled on the Rising Edge of CLK, Active
LOW. When asserted LOW, addresses presented to the device are captured in the
address registers. A[1:0] are also loaded into the burst counter. When ADSP and ADSC
are both asserted, only ADSP is recognized. ASDP is ignored when
CE1 is deasserted
HIGH.
ADSC
Input-Synchronous Address Strobe from Controller, Sampled on the Rising Edge of CLK, Active
LOW. When asserted LOW, addresses presented to the device are captured in the
address registers. A[1:0] are also loaded into the burst counter. When ADSP and ADSC
are both asserted, only ADSP is recognized.
BWE
ZZ
Input-Synchronous Byte Write Enable Input, ActiveLOW. Sampled on the rising edge of CLK. This signal
must be asserted LOW to conduct a byte write.
Input-Asynchronous ZZ “sleep” Input, Active HIGH. When asserted HIGH places the device in a
non-time-critical “sleep” condition with data integrity preserved. For normal operation,
this pin must be LOW or left floating. ZZ pin has an internal pull down.
I/O-Synchronous Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is
triggered by the rising edge of CLK. As outputs, they deliver the data contained in the
memory location specified by the addresses presented during the read cycle. The
direction of the pins is controlled by OE. When OE is asserted LOW, the pins behave
as outputs. When HIGH, DQs and DQPX are placed in a tristate condition.The outputs
are automatically tristated during the data portion of a write sequence, during the first
clock when emerging from a deselected state, and when the device is deselected,
regardless of the state of OE.
DQs
Document Number: 001-66677 Rev. *J
Page 7 of 32
CY7C1441KV33
CY7C1443KV33
CY7C1441KVE33
Pin Definitions (continued)
Name
I/O
Description
I/O-Synchronous Bidirectional Data Parity I/O Lines. Functionally, these signals are identical to DQs.
DQPX
During write sequences, DQPx is controlled by BW[A:H] correspondingly.
MODE
Input-Static
Selects Burst Order. When tied to GND selects linear burst sequence. When tied to
VDD or left floating selects interleaved burst sequence. This is a strap pin and should
remain static during device operation. Mode Pin has an internal pull up.
VDD
Power Supply
Power Supply Inputs to the Core of the Device.
VDDQ
VSS
I/O Power Supply Power Supply for the I/O Circuitry.
Ground
Ground for the Core of the Device.
Ground for the I/O Circuitry.
VSSQ
TDO
I/O Ground
JTAG serial output Serial Data-Out to the JTAG Circuit. Delivers data on the negative edge of TCK. If
Synchronous
the JTAG feature is not being utilized, this pin should be left unconnected. This pin is
not available on TQFP packages.
TDI
JTAG serial input Serial Data-In to the JTAG Circuit. Sampled on the rising edge of TCK. If the JTAG
Synchronous
feature is not being utilized, this pin can be left floating or connected to VDD through a
pull up resistor. This pin is not available on TQFP packages.
TMS
JTAG serial input Serial Data-In to the JTAG Circuit. Sampled on the rising edge of TCK. If the JTAG
Synchronous
feature is not being utilized, this pin can be disconnected or connected to VDD. This
pin is not available on TQFP packages.
TCK
NC
JTAG-Clock
Clock Input to the JTAG Circuitry. If the JTAG feature is not being utilized, this pin
must be connected to VSS. This pin is not available on TQFP packages.
–
–
No Connects. Not internally connected to the die. 72M, 144M and 288M are address
expansion pins are not internally connected to the die.
NC/72M, NC/144M,
NC/288M, NC/576M,
NC/1G
No Connects. Not internally connected to the die. NC/72M, NC/144M, NC/288M,
NC/576M and NC/1G are address expansion pins are not internally connected to the
die.
Single Read Accesses
Functional Overview
A single read access is initiated when the following conditions
All synchronous inputs pass through input registers controlled by
the rising edge of the clock. Maximum access delay from the
clock rise (tCDV) is 6.5 ns (133-MHz device).
are satisfied at clock rise: (1) CE1, CE2, and CE3 are all asserted
active, and (2) ADSP or ADSC is asserted LOW (if the access is
initiated by ADSC, the write inputs must be deasserted during
this first cycle). The address presented to the address inputs is
latched into the address register and the burst counter/control
logic and presented to the memory core. If the OE input is
asserted LOW, the requested data is available at the data
outputs a maximum to tCDV after clock rise. ADSP is ignored if
CE1 is HIGH.
The
CY7C1441KV33/CY7C1443KV33/CY7C1441KVE33
support secondary cache in systems utilizing either a linear or
interleaved burst sequence. The interleaved burst order
supports Pentium processors. The burst order is
user-selectable, and is determined by sampling the MODE input.
Accesses can be initiated with either the Processor Address
Strobe (ADSP) or the Controller Address Strobe (ADSC).
Address advancement through the burst sequence is controlled
by the ADV input. A two-bit on-chip wraparound burst counter
captures the first address in a burst sequence and automatically
increments the address for the rest of the burst access.
Single Write Accesses Initiated by ADSP
This access is initiated when the following conditions are
satisfied at clock rise: (1) CE1, CE2, CE3 are all asserted active,
and (2) ADSP is asserted LOW. The addresses presented are
loaded into the address register and the burst inputs (GW, BWE,
and BWX)are ignored during this first clock cycle. If the write
inputs are asserted active (see Write Cycle Descriptions table for
appropriate states that indicate a write) on the next clock rise, the
appropriate data is latched and written into the device. Byte
writes are allowed. All I/Os are tristated during a byte write.Since
this is a common I/O device, the asynchronous OE input signal
must be deasserted and the I/Os must be tristated prior to the
presentation of data to DQs. As a safety precaution, the data
Byte write operations are qualified with the Byte Write Enable
(BWE) and Byte Write Select (BWx) inputs. A Global Write
Enable (GW) overrides all byte write inputs and writes data to all
four bytes. All writes are simplified with on-chip synchronous
self-timed write circuitry.
Three synchronous Chip Selects (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) provide for easy bank
selection and output tristate control. ADSP is ignored if CE1 is
HIGH.
Document Number: 001-66677 Rev. *J
Page 8 of 32
CY7C1441KV33
CY7C1443KV33
CY7C1441KVE33
lines are tristated once a write cycle is detected, regardless of
the state of OE.
On-Chip ECC
CY7C1441KVE33 SRAMs include an on-chip ECC algorithm
that detects and corrects all single-bit memory errors, including
Soft Error Upset (SEU) events induced by cosmic rays, alpha
particles etc. The resulting Soft Error Rate (SER) of these
Single Write Accesses Initiated by ADSC
This write access is initiated when the following conditions are
satisfied at clock rise: (1) CE1, CE2, and CE3 are all asserted
active, (2) ADSC is asserted LOW, (3) ADSP is deasserted
HIGH, and (4) the write input signals (GW, BWE, and BWX)
indicate a write access. ADSC is ignored if ADSP is active LOW.
devices is anticipated to be
<0.01
FITs/Mb
a
4-order-of-magnitude improvement over comparable SRAMs
with no On-Chip ECC, which typically have an SER of 200
FITs/Mb or more. To protect the internal data, ECC parity bits
(invisible to the user) are used.
The addresses presented are loaded into the address register
and the burst counter/control logic and delivered to the memory
core. The information presented to DQS is written into the
specified address location. Byte writes are allowed. All I/Os are
tristated when a write is detected, even a byte write. Since this
is a common I/O device, the asynchronous OE input signal must
be deasserted and the I/Os must be tristated prior to the
presentation of data to DQs. As a safety precaution, the data
lines are tristated once a write cycle is detected, regardless of
the state of OE.
The ECC algorithm does not correct multi-bit errors. However,
Cypress SRAMs are designed in such a way that a single SER
event has a very low probability of causing a multi-bit error
across any data word. The extreme rarity of multi-bit errors
results in a SER of <0.01 FITs/Mb.
Interleaved Burst Address Table
(MODE = Floating or VDD
)
First
Address
A1: A0
Second
Address
A1: A0
Third
Address
A1: A0
Fourth
Address
A1: A0
Burst Sequences
The
CY7C1441KV33/CY7C1443KV33/CY7C1441KVE33
provide an on-chip two-bit wraparound burst counter inside the
SRAM. The burst counter is fed by A[1:0], and can follow either a
linear or interleaved burst order. The burst order is determined
by the state of the MODE input. A LOW on MODE selects a linear
burst sequence. A HIGH on MODE selects an interleaved burst
order. Leaving MODE unconnected causes the device to default
to a interleaved burst sequence.
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
Sleep Mode
Linear Burst Address Table
The ZZ input pin is an asynchronous input. Asserting ZZ places
the SRAM in a power conservation “sleep” mode. Two clock
cycles are required to enter into or exit from this “sleep” mode.
While in this mode, data integrity is guaranteed. Accesses
pending when entering the “sleep” mode are not considered valid
nor is the completion of the operation guaranteed. The device
must be deselected prior to entering the “sleep” mode. CE1,
CE2,CE3, ADSP, and ADSC must remain inactive for the
duration of tZZREC after the ZZ input returns LOW.
(MODE = GND)
First
Address
A1: A0
Second
Address
A1: A0
Third
Address
A1: A0
Fourth
Address
A1: A0
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
ZZ Mode Electrical Characteristics
Parameter
IDDZZ
Description
Sleep mode standby current
Device operation to ZZ
ZZ recovery time
Test Conditions
Min
Max
Unit
mA
ns
ZZ > VDD– 0.2 V
–
75
2tCYC
–
tZZS
ZZ > VDD – 0.2 V
ZZ < 0.2 V
–
2tCYC
–
tZZREC
tZZI
ns
2tCYC
ZZ active to sleep current
This parameter is sampled
ns
tRZZI
ZZ Inactive to exit sleep current This parameter is sampled
0
–
ns
Document Number: 001-66677 Rev. *J
Page 9 of 32
CY7C1441KV33
CY7C1443KV33
CY7C1441KVE33
Truth Table
The truth table for CY7C1441KV33/CY7C1443KV33/CY7C1441KVE33 is as follows. [1, 2, 3, 4, 5]
Cycle Description
Address Used CE1 CE2 CE3 ZZ ADSP ADSC ADV WRITE OE CLK
DQ
Deselected Cycle, Power down
Deselected Cycle, Power down
Deselected Cycle, Power down
Deselected Cycle, Power down
Deselected Cycle, Power down
Sleep Mode, Power down
Read Cycle, Begin Burst
None
None
H
L
X
L
X
X
H
X
H
X
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X
L
L
X
X
L
X
X
X
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
L
L–H Tristate
L–H Tristate
L–H Tristate
L–H Tristate
L–H Tristate
None
L
X
L
L
None
L
H
H
X
L
None
X
X
L
X
X
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
L
None
X
X
X
L
X
Tristate
Q
External
External
External
External
External
Next
L–H
L–H
L–H
L–H
L–H
L–H
L–H
L–H
Tristate
Read Cycle, Begin Burst
L
L
L
H
X
L
Write Cycle, Begin Burst
L
L
H
H
H
H
H
X
X
H
X
H
H
X
X
H
X
D
Q
Read Cycle, Begin Burst
L
L
L
H
H
H
H
H
H
L
Tristate
Read Cycle, Begin Burst
L
L
L
H
L
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Write Cycle, Continue Burst
Write Cycle, Continue Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Write Cycle, Suspend Burst
Write Cycle, Suspend Burst
X
X
H
H
X
H
X
X
H
H
X
H
X
X
X
X
X
X
X
X
X
X
X
X
H
H
H
H
H
H
H
H
H
H
H
H
Q
Tristate
Next
L
H
L
Next
L
Q
Next
L
H
X
X
L
L–H Tristate
Next
L
L–H
L–H
L–H
D
D
Q
Next
L
L
Current
Current
Current
Current
Current
Current
H
H
H
H
H
H
H
H
H
H
L
H
L
L–H Tristate
L–H
L–H Tristate
Q
H
X
X
L–H
L–H
D
D
L
Notes
1. X = “Don't Care.” H = Logic HIGH, L = Logic LOW.
2. WRITE = L when any one or more Byte Write enable signals and BWE = L or GW = L. WRITE = H when all Byte write enable signals, BWE, GW = H.
3. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
4. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BW . Writes may occur only on subsequent clocks after
X
the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to tristate. OE is a don't care
for the remainder of the write cycle.
5. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are tristate when OE is inactive
or when the device is deselected, and all data bits behave as output when OE is active (LOW).
Document Number: 001-66677 Rev. *J
Page 10 of 32
CY7C1441KV33
CY7C1443KV33
CY7C1441KVE33
Partial Truth Table for Read/Write
The partial truth table for read/write for CY7C1441KV33/CY7C1441KVE33 is as follows. [6, 7, 8]
Function (CY7C1441KV33/CY7C1441KVE33)
Read
GW
H
BWE
BWD
X
BWC
X
BWB
X
BWA
X
H
L
L
L
L
L
L
L
L
Read
H
H
H
H
H
Write Byte A (DQA, DQPA)
H
H
H
H
L
Write Byte B (DQB, DQPB)
H
H
H
L
H
Write Bytes A, B (DQA, DQB, DQPA, DQPB)
Write Byte C (DQC, DQPC)
H
H
H
L
L
H
H
L
H
H
Write Bytes C, A (DQC, DQA, DQPC, DQPA)
Write Bytes C, B (DQC, DQB, DQPC, DQPB)
H
H
L
H
L
H
H
L
L
H
Write Bytes C, B, A (DQC, DQB, DQA, DQPC, DQPB,
DQPA)
H
H
L
L
L
Write Byte D (DQD, DQPD)
H
H
H
H
L
L
L
L
L
L
L
L
H
H
H
H
H
H
L
H
L
Write Bytes D, A (DQD, DQA, DQPD, DQPA)
Write Bytes D, B (DQD, DQA, DQPD, DQPA)
H
L
Write Bytes D, B, A (DQD, DQB, DQA, DQPD, DQPB,
DQPA)
L
Write Bytes D, B (DQD, DQB, DQPD, DQPB)
H
H
L
L
L
L
L
L
H
H
H
L
Write Bytes D, B, A (DQD, DQC, DQA, DQPD, DQPC,
DQPA)
Write Bytes D, C, A (DQD, DQB, DQA, DQPD, DQPB,
DQPA)
H
L
L
L
L
H
Write All Bytes
Write All Bytes
H
L
L
L
L
L
L
X
X
X
X
X
Partial Truth Table for Read/Write
The partial truth table for read/write for CY7C1443KV33 is as follows. [6, 7, 8]
Function (CY7C1443KV33)
GW
H
BWE
BWB
X
BWA
X
Read
Read
H
L
L
L
L
X
H
H
H
Write Byte A – (DQA and DQPA)
Write Byte B – (DQB and DQPB)
Write All Bytes
H
H
L
H
L
H
H
L
L
Write All Bytes
L
X
X
Notes
6. X = “Don't Care.” H = Logic HIGH, L = Logic LOW.
7. Table only lists a partial listing of the byte write combinations. Any Combination of BW is valid Appropriate write is done based on which byte write is active.
X
8. BWx represents any byte write signal BW
.To enable any byte write BW a Logic LOW signal should be applied at clock rise.Any number of bye writes can be
[A..H]
x,
enabled at the same time for any given write.
Document Number: 001-66677 Rev. *J
Page 11 of 32
CY7C1441KV33
CY7C1443KV33
CY7C1441KVE33
TAP Registers
IEEE 1149.1 Serial Boundary Scan (JTAG)
Registers are connected between the TDI and TDO balls and
scan data into and out of the SRAM test circuitry. Only one
register can be selected at a time through the instruction register.
Data is serially loaded into the TDI ball on the rising edge of TCK.
Data is output on the TDO ball on the falling edge of TCK.
The CY7C1441KV33 incorporates a serial boundary scan test
access port (TAP). This part is fully compliant with 1149.1. The
TAP operates using JEDEC-standard 3.3 V or 2.5 V I/O logic
levels.
The CY7C1441KV33 contains a TAP controller, instruction
register, boundary scan register, bypass register, and ID register.
Instruction Register
Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the TDI
and TDO balls as shown in the TAP Controller Block Diagram on
page 14. Upon power up, the instruction register is loaded with
the IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state as described
in the previous section.
Disabling the JTAG Feature
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied LOW
(VSS) to prevent clocking of the device. TDI and TMS are
internally pulled up and may be unconnected. They may
alternately be connected to VDD through a pull up resistor. TDO
should be left unconnected. Upon power up, the device comes
up in a reset state which does not interfere with the operation of
the device.
When the TAP controller is in the Capture-IR state, the two least
significant bits are loaded with a binary “01” pattern to allow for
fault isolation of the board-level serial test data path.
Test Access Port (TAP)
Bypass Register
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain chips. The bypass
register is a single-bit register that can be placed between the
TDI and TDO balls. This shifts data through the SRAM with
minimal delay. The bypass register is set LOW (VSS) when the
BYPASS instruction is executed.
Test Clock (TCK)
The test clock is used only with the TAP controller. All inputs are
captured on the rising edge of TCK. All outputs are driven from
the falling edge of TCK.
Test MODE SELECT (TMS)
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. It is allowable to leave
this ball unconnected if the TAP is not used. The ball is pulled up
internally, resulting in a logic HIGH level.
Boundary Scan Register
The boundary scan register is connected to all the input and
bidirectional balls on the SRAM.
The boundary scan register is loaded with the contents of the
RAM I/O ring when the TAP controller is in the Capture-DR state
and is then placed between the TDI and TDO balls when the
controller is moved to the Shift-DR state. The EXTEST,
SAMPLE/PRELOAD and SAMPLE Z instructions can be used to
capture the contents of the I/O ring.
Test Data-In (TDI)
The TDI ball is used to serially input information into the registers
and can be connected to the input of any of the registers. The
register between TDI and TDO is chosen by the instruction that
is loaded into the TAP instruction register. TDI is internally pulled
up and can be unconnected if the TAP is unused in an
application. TDI is connected to the most significant bit (MSB) of
any register (see TAP Controller Block Diagram on page 14).
The Boundary Scan Order on page 18 show the order in which
the bits are connected. Each bit corresponds to one of the bumps
on the SRAM package. The MSB of the register is connected to
TDI, and the LSB is connected to TDO.
Test Data-Out (TDO)
Identification (ID) Register
The TDO output ball is used to serially clock data-out from the
registers. The output is active depending upon the current state
of the TAP state machine. The output changes on the falling edge
of TCK. TDO is connected to the least significant bit (LSB) of any
register (see TAP Controller State Diagram on page 14).
The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired into
the SRAM and can be shifted out when the TAP controller is in
the Shift-DR state. The ID register has a vendor code and other
information described in the Identification Register Definitions on
page 17.
Performing a TAP Reset
A RESET is performed by forcing TMS HIGH (VDD) for five rising
edges of TCK. This RESET does not affect the operation of the
SRAM and may be performed while the SRAM is operating.
At power up, the TAP is reset internally to ensure that TDO
comes up in a High Z state.
Document Number: 001-66677 Rev. *J
Page 12 of 32
CY7C1441KV33
CY7C1443KV33
CY7C1441KVE33
during a SAMPLE/PRELOAD instruction. If this is an issue, it is
still possible to capture all other signals and simply ignore the
value of the clock captured in the boundary scan register.
TAP Instruction Set
Overview
Eight different instructions are possible with the three bit
instruction register. All combinations are listed in the Instruction
Codes table. Three of these instructions are listed as
RESERVED and should not be used. The other five instructions
are described in this section in detail.
After the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the boundary
scan register between the TDI and TDO pins.
PRELOAD places an initial data pattern at the latched parallel
outputs of the boundary scan register cells prior to the selection
of another boundary scan test operation.
Instructions are loaded into the TAP controller during the Shift-IR
state when the instruction register is placed between TDI and
TDO. During this state, instructions are shifted through the
instruction register through the TDI and TDO balls. To execute
the instruction once it is shifted in, the TAP controller must be
moved into the Update-IR state.
The shifting of data for the SAMPLE and PRELOAD phases can
occur concurrently when required – that is, while data captured
is shifted out, the preloaded data can be shifted in.
BYPASS
When the BYPASS instruction is loaded in the instruction register
and the TAP is placed in a Shift-DR state, the bypass register is
placed between the TDI and TDO pins. The advantage of the
BYPASS instruction is that it shortens the boundary scan path
when multiple devices are connected together on a board.
IDCODE
The IDCODE instruction loads a vendor-specific, 32-bit code into
the instruction register. It also places the instruction register
between the TDI and TDO balls and shifts the IDCODE out of the
device when the TAP controller enters the Shift-DR state.
EXTEST
The IDCODE instruction is loaded into the instruction register
upon power up or whenever the TAP controller is given a test
logic reset state.
The EXTEST instruction drives the preloaded data out through
the system output pins. This instruction also connects the
boundary scan register for serial access between the TDI and
TDO in the shift-DR controller state.
SAMPLE Z
The SAMPLE Z instruction connects the boundary scan register
between the TDI and TDO pins when the TAP controller is in a
Shift-DR state. The SAMPLE Z command puts the output bus
into a High Z state until the next command is given during the
“Update IR” state.
EXTEST OUTPUT BUS TRISTATE
IEEE Standard 1149.1 mandates that the TAP controller be able
to put the output bus into a tristate mode.
The boundary scan register has a special bit located at bit #89
(for 165-FBGA package). When this scan cell, called the “extest
output bus tristate”, is latched into the preload register during the
“Update-DR” state in the TAP controller, it directly controls the
state of the output (Q-bus) pins, when the EXTEST is entered as
the current instruction. When HIGH, it enables the output buffers
to drive the output bus. When LOW, this bit places the output bus
into a High-Z condition.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When
the SAMPLE/PRELOAD instructions are loaded into the
instruction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the inputs and output pins is
captured in the boundary scan register.
The user must be aware that the TAP controller clock can only
operate at a frequency up to 20 MHz, while the SRAM clock
operates more than an order of magnitude faster. Because there
is a large difference in the clock frequencies, it is possible that
during the Capture-DR state, an input or output undergoes a
transition. The TAP may then try to capture a signal while in
transition (metastable state). This does not harm the device, but
there is no guarantee as to the value that is captured.
Repeatable results may not be possible.
This bit can be set by entering the SAMPLE/PRELOAD or
EXTEST command, and then shifting the desired bit into that cell,
during the “Shift-DR” state. During “Update-DR”, the value
loaded into that shift-register cell latches into the preload
register. When the EXTEST instruction is entered, this bit directly
controls the output Q-bus pins. Note that this bit is pre-set HIGH
to enable the output when the device is powered-up, and also
when the TAP controller is in the “Test-Logic-Reset” state.
Reserved
To guarantee that the boundary scan register captures the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller's capture setup plus hold
times (tCS and tCH). The SRAM clock input might not be captured
correctly if there is no way in a design to stop (or slow) the clock
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
Document Number: 001-66677 Rev. *J
Page 13 of 32
CY7C1441KV33
CY7C1443KV33
CY7C1441KVE33
The 0/1 next to each state represents the value of TMS at the
rising edge of TCK.
TAP Controller State Diagram
TAP Controller Block Diagram
TEST-LOGIC
1
RESET
0
0
1
1
1
RUN-TEST/
IDLE
SELECT
DR-SCAN
SELECT
IR-SCAN
0
Bypass Register
0
0
2
1
0
0
0
1
1
Selection
Circuitry
CAPTURE-DR
CAPTURE-IR
Instruction Register
31 30 29
Identification Register
Selection
TDI
TDO
Circuitr
y
0
0
.
.
. 2 1
SHIFT-DR
0
SHIFT-IR
0
x
.
.
.
.
. 2 1
1
1
Boundary Scan Register
1
1
EXIT1-DR
EXIT1-IR
0
0
TCK
TMS
PAUSE-DR
1
0
PAUSE-IR
1
0
TAP CONTROLLER
0
0
EXIT2-DR
1
EXIT2-IR
1
UPDATE-DR
UPDATE-IR
1
0
1
0
TAP Timing
1
2
3
4
5
6
Test Clock
(TCK)
t
t
t
CYC
TH
TL
t
t
t
t
TMSS
TDIS
TMSH
Test Mode Select
(TMS)
TDIH
Test Data-In
(TDI)
t
TDOV
t
TDOX
Test Data-Out
(TDO)
DON’T CARE
UNDEFINED
Document Number: 001-66677 Rev. *J
Page 14 of 32
CY7C1441KV33
CY7C1443KV33
CY7C1441KVE33
TAP AC Switching Characteristics
Over the Operating Range
Parameter [9, 10]
Clock
Description
Min
Max
Unit
tTCYC
TCK Clock Cycle Time
TCK Clock Frequency
TCK Clock HIGH time
TCK Clock LOW time
50
–
–
20
–
ns
MHz
ns
tTF
tTH
20
20
tTL
–
ns
Output Times
tTDOV
tTDOX
Setup Times
tTMSS
tTDIS
TCK Clock LOW to TDO Valid
TCK Clock LOW to TDO Invalid
–
0
10
–
ns
ns
TMS Setup to TCK Clock Rise
TDI Setup to TCK Clock Rise
Capture Setup to TCK Rise
5
5
5
–
–
–
ns
ns
ns
tCS
Hold Times
tTMSH
tTDIH
TMS Hold after TCK Clock Rise
TDI Hold after Clock Rise
5
5
5
–
–
–
ns
ns
ns
tCH
Capture Hold after Clock Rise
3.3 V TAP AC Test Conditions
2.5 V TAP AC Test Conditions
Input pulse levels ...............................................VSS to 3.3 V
Input rise and fall times (Slew Rate) ........................... 2 V/ns
Input timing reference levels ......................................... 1.5 V
Output reference levels ................................................ 1.5 V
Test load termination supply voltage ............................ 1.5 V
Input pulse levels ...............................................VSS to 2.5 V
Input rise and fall times (Slew Rate) ........................... 2 V/ns
Input timing reference levels ................. ......................1.25 V
Output reference levels ................ ..............................1.25 V
Test load termination supply voltage .................. ........1.25 V
3.3 V TAP AC Output Load Equivalent
2.5 V TAP AC Output Load Equivalent
1.5V
1.25V
50Ω
50Ω
TDO
TDO
ZO = 50Ω
ZO= 50Ω
20p F
20pF
Notes
9.
t
and t refer to the set-up and hold time requirements of latching data from the boundary scan register.
CS CH
10. Test conditions are specified using the load in TAP AC test Conditions. t /t = 2 V/ns (Slew Rate).
R
F
Document Number: 001-66677 Rev. *J
Page 15 of 32
CY7C1441KV33
CY7C1443KV33
CY7C1441KVE33
TAP DC Electrical Characteristics and Operating Conditions
(0 °C < TA < +70 °C; VDD = 3.135 V to 3.6 V unless otherwise noted)
Parameter [11]
Description
Description
IOH = –4.0 mA
Conditions
VDDQ = 3.3 V
Min
2.4
2.0
2.9
2.1
–
Max
Unit
V
VOH1
Output HIGH Voltage
–
IOH = –1.0 mA
IOH = –100 µA
VDDQ = 2.5 V
VDDQ = 3.3 V
VDDQ = 2.5 V
VDDQ = 3.3 V
VDDQ = 2.5 V
VDDQ = 3.3 V
VDDQ = 2.5 V
VDDQ = 3.3 V
VDDQ = 2.5 V
VDDQ = 3.3 V
VDDQ = 2.5 V
–
V
VOH2
VOL1
VOL2
VIH
Output HIGH Voltage
Output LOW Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Load Current
–
V
–
0.4
V
IOL = 8.0 mA
IOL = 1.0 mA
IOL = 100 µA
V
–
0.4
V
–
0.2
V
–
0.2
V
2.0
1.7
–0.3
–0.3
–5
VDD + 0.3
VDD + 0.3
0.8
V
V
VIL
V
0.7
V
IX
GND < VIN < VDDQ
5
µA
Note
11. All voltages referenced to V (GND).
SS
Document Number: 001-66677 Rev. *J
Page 16 of 32
CY7C1441KV33
CY7C1443KV33
CY7C1441KVE33
Identification Register Definitions
CY7C1441KV33
(1M × 36)
Instruction Field
Description
Revision Number (31:29)
000
01011
Describes the version number.
Device Depth (28:24)
Reserved for Internal Use
Architecture/Memory Type(23:18)[12]
000001
100111
00000110100
1
Defines memory type and architecture
Defines width and density
Bus Width/Density(17:12)
Cypress JEDEC ID Code (11:1)
ID Register Presence Indicator (0)
Allows unique identification of SRAM vendor.
Indicates the presence of an ID register.
Scan Register Sizes
Register Name
Bit Size (× 36)
Instruction Bypass
3
1
Bypass
ID
32
89
Boundary Scan Order (165-ball FBGA package)
Identification Codes
Instruction
EXTEST
Code
Description
000
Captures I/O ring contents.
Loads the ID register with the vendor ID code and places the register between TDI and TDO.
This operation does not affect SRAM operations.
IDCODE
001
Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Forces
all SRAM output drivers to a High Z state.
SAMPLE Z
010
011
100
RESERVED
Do Not Use: This instruction is reserved for future use.
Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Does
not affect SRAM operation.
SAMPLE/PRELOAD
RESERVED
RESERVED
101
110
Do Not Use: This instruction is reserved for future use.
Do Not Use: This instruction is reserved for future use.
Places the bypass register between TDI and TDO. This operation does not affect SRAM
operations.
BYPASS
111
Note
12. Bit #24 is “1” in the ID Register Definitions for both 2.5 V and 3.3 V versions of this device.
Document Number: 001-66677 Rev. *J
Page 17 of 32
CY7C1441KV33
CY7C1443KV33
CY7C1441KVE33
Boundary Scan Order
165-ball FBGA [13, 14]
CY7C1441KV33 (1M × 36)
Bit #
1
Ball ID
Bit #
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
Ball ID
E11
D11
G10
F10
E10
D10
C11
A11
B11
A10
B10
A9
Bit #
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
Ball ID
A3
A2
B2
C2
B1
A1
C1
D1
E1
F1
Bit #
76
77
78
79
80
81
82
83
84
85
86
87
88
89
Ball ID
N1
N6
N7
2
N2
3
N10
P11
P8
P1
4
R1
5
R2
6
R8
P3
7
R9
R3
8
P9
P2
9
P10
R10
R11
H11
N11
M11
L11
K11
J11
M10
L10
K10
J10
H9
R4
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
P4
G1
D2
E2
F2
N5
P6
B9
R6
C10
A8
Internal
G2
H1
H3
J1
B8
A7
B7
B6
K1
L1
A6
M1
J2
B5
A5
A4
B4
B3
H10
G11
F11
K2
L2
M2
Notes
13. Balls which are NC (No Connect) are preset LOW.
14. Bit# 89 is preset HIGH.
Document Number: 001-66677 Rev. *J
Page 18 of 32
CY7C1441KV33
CY7C1443KV33
CY7C1441KVE33
Maximum Ratings
Operating Range
Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested.
Ambient
Range
VDD
VDDQ
Temperature
0 °C to +70 °C
–40 °C to +85 °C
Commercial
Industrial
3.3 V– 5% / 2.5 V – 5% to
Storage Temperature ............................... –65 C to +150C
+ 10%
VDD
Ambient Temperature
with Power Applied .................................. –55C to +125 C
Supply Voltage on VDD Relative to GND .....–0.3 V to +4.6 V
Supply Voltage on VDDQ Relative to GND .... –0.3 V to +VDD
Neutron Soft Error Immunity
DC Voltage Applied to Outputs
in Tristate ..........................................–0.5 V to VDDQ + 0.5 V
Test
Parameter Description
Conditions
Typ Max* Unit
DC Input Voltage ................................–0.5 V to VDD + 0.5 V
Current into Outputs (LOW) ........................................ 20 mA
LSBU
Logical
Single-Bit
Upsets
25 °C
<5
5
FIT/
Mb
(Device
without
ECC)
Static Discharge Voltage
(per MIL-STD-883, Method 3015) ......................... > 2001 V
LSBU
(Device with
ECC)
0
0
0
0.01
0.01
0.1
FIT/
Mb
Latch-up Current ................................................... > 200 mA
DC Input Voltage ................................–0.5 V to VDD + 0.5 V
Current into Outputs (LOW) ........................................ 20 mA
LMBU (All
Devices)
Logical
Multi-Bit
Upsets
25 °C
85 °C
FIT/
Mb
Static Discharge Voltage
(per MIL-STD-883, Method 3015) ......................... > 2001 V
SEL (All
Devices)
Single Event
Latch up
FIT/
Dev
Latch-up Current ................................................... > 200 mA
* No LMBU or SEL events occurred during testing; this column represents a
2
statistical , 95% confidence limit calculation. For more details refer to Application
Note AN54908 “Accelerated Neutron SER Testing and Calculation of Terrestrial
Failure Rates”.
Electrical Characteristics
Over the Operating Range
DC Characteristics
Over the Operating Range
Parameter
VDD
Description
Power supply voltage
I/O supply voltage
Test Conditions
Min
3.135
3.135
2.375
2.4
Max
Units
V
–
3.6
VDDQ
VOH
VOL
VIH
for 3.3 V I/O
for 2.5 V I/O
VDD
V
2.625
V
Output HIGH voltage
Output LOW voltage
Input HIGH voltage[15]
Input LOW voltage[15]
for 3.3 V I/O, IOH = -4.0 mA
for 2.5 V I/O, IOH = -1.0 mA
for 3.3 V I/O, IOL = 8.0 mA
for 2.5 V I/O, IOL = 1.0 mA
for 3.3 V I/O
–
V
2.0
–
0.4
V
–
V
–
0.4
V
2.0
VDD + 0.3 V
VDD + 0.3 V
0.8
V
for 2.5 V I/O
1.7
V
VIL
for 3.3 V I/O
-0.3
-0.3
V
for 2.5 V I/O
0.7
V
Notes
15. Overshoot: V (AC) < V +1.5V (Pulse width less than t
/2), undershoot: V (AC) > –2V (Pulse width less than t
/2).
CYC
IH
DD
CYC
IL
16. T
: Assumes a linear ramp from 0V to V (min.) within 200 ms. During this time V < V and V
< V
Power-up
DD
IH
DD
DDQ DD.
Document Number: 001-66677 Rev. *J
Page 19 of 32
CY7C1441KV33
CY7C1443KV33
CY7C1441KVE33
Electrical Characteristics (continued)
Over the Operating Range
DC Characteristics (continued)
Over the Operating Range
Parameter
Description
Test Conditions
Min
Max
Units
IX
Input leakage current except ZZ GND VI VDDQ
and MODE
–5
5
A
Input current of MODE
Input = VSS
–30
–
–
5
A
A
A
A
Input = VDD
Input current of ZZ
Input = VSS
–5
–
–
Input = VDD
30
5
IOZ
IDD
Output leakage current
GND VI VDDQ, Output Disabled
VDD = Max., IOUT = 0 mA, 7.5-nscycle, × 18
f = fMAX = 1/tCYC
–5
–
VDD operating supply current
150
170
85
90
mA
mA
133 MHz
× 36
–
ISB1
ISB2
ISB3
ISB4
Automatic CE power down
current – TTL inputs
Max. VDD, Device
Deselected,
7.5-nscycle, × 18
133 MHz
–
× 36
–
VIN VIH or VIN VIL,
f = fMAX,
inputs switching
Automatic CE power down
current – CMOS inputs
Max. VDD
,
7.5-nscycle, × 18
–
–
75
80
mA
mA
mA
Device Deselected,
VIN VDD – 0.3 V or
VIN 0.3 V,
133 MHz
× 36
f = 0, inputs static
Automatic CE power down
current – CMOS inputs
Max. VDD
,
7.5-nscycle, × 18
–
–
85
90
Device Deselected,
VIN VDDQ – 0.3 V or
VIN 0.3 V,
133 MHz
× 36
f = fMAX, inputs switching
Automatic CE power down
current – TTL inputs
Max. VDD, Device
Deselected,
7.5-nscycle, × 18
–
–
75
80
133 MHz
× 36
VIN VDD – 0.3 V or
VIN 0.3 V,
f = 0, inputs static
Document Number: 001-66677 Rev. *J
Page 20 of 32
CY7C1441KV33
CY7C1443KV33
CY7C1441KVE33
Capacitance
100-pin TQFP 165-ballFBGA
Parameter [17]
Description
Input capacitance
Test Conditions
Unit
Max.
Max.
CIN
TA = 25C, f = 1 MHz,
VDD = 3.3V, VDDQ = 2.5 V
5
5
5
5
5
5
pF
pF
pF
CCLK
CIO
Clock input capacitance
Input/output capacitance
Thermal Resistance
100-pinTQFP 165-ball FBGA
Parameter [17]
Description
Test Conditions
Unit
Package
35.36
31.30
28.86
7.52
Package
14.24
12.47
11.40
JA
Thermal resistance Test conditions follow
(junction to ambient) standard test methods and
With Still Air (0 m/s)
With Air Flow (1 m/s)
With Air Flow (3 m/s)
–
°C/W
°C/W
°C/W
°C/W
procedures for measuring
thermal impedance, per
EIA/JESD51.
JC
JB
Thermal resistance
(junction to case)
3.92
Thermal resistance
(junction to board)
28.89
7.19
°C/W
AC Test Loads and Waveforms
Figure 3. AC Test Loads and Waveforms
3.3V I/O Test Load
R = 317
3.3V
OUTPUT
OUTPUT
ALL INPUT PULSES
90%
V
DDQ
90%
10%
Z = 50
0
R = 50
10%
L
GND
5 pF
R = 351
1 ns
2 V/ns
V = 1.5V
T
INCLUDING
JIG AND
SCOPE
(c)
(a)
(b)
2.5V I/O Test Load
R = 1667
2.5V
OUTPUT
OUTPUT
ALL INPUT PULSES
90%
V
DDQ
90%
Z = 50
0
10%
2 V/ns
R = 50
10%
L
GND
5 pF
R = 1538
1 ns
V = 1.25V
T
INCLUDING
JIG AND
SCOPE
(c)
(a)
(b)
Note
17. Tested initially and after any design or process change that may affect these parameters.
Document Number: 001-66677 Rev. *J
Page 21 of 32
CY7C1441KV33
CY7C1443KV33
CY7C1441KVE33
Switching Characteristics
Over the Operating Range
–133
Unit
Parameter [18, 19]
Description
VDD (Typical) to the first Access[20]
Min
Max
tPOWER
Clock
tCYC
1
–
ms
Clock cycle time
Clock HIGH
7.5
2.5
2.5
–
–
–
ns
ns
ns
tCH
tCL
Clock LOW
Output Times
tCDV
Data Output Valid after CLK Rise
Data Output Hold after CLK Rise
Clock to Low Z[21, 22, 23]
–
2.5
2.5
–
6.5
–
ns
ns
ns
ns
ns
ns
ns
tDOH
tCLZ
–
tCHZ
Clock to High Z[21, 22, 23]
3.8
3.0
–
tOEV
OE LOW to Output Valid
–
tOELZ
tOEHZ
Setup Times
tAS
OE LOW to Output Low Z[21, 22, 23]
OE HIGH to Output High Z[21, 22, 23]
0
–
3.0
Address setup before CLK Rise
ADSP, ADSC setup before CLK Rise
ADV setup before CLK Rise
1.5
1.5
1.5
1.5
1.5
1.5
–
–
–
–
–
–
ns
ns
ns
ns
ns
ns
tADS
tADVS
tWES
GW, BWE, BWX setup before CLK Rise
Data input setup before CLK Rise
Chip Enable setup
tDS
tCES
Hold Times
tAH
Address Hold after CLK Rise
ADSP, ADSC Hold after CLK Rise
GW, BWE, BWX Hold after CLK Rise
ADV Hold after CLK Rise
0.5
0.5
0.5
0.5
0.5
0.5
–
–
–
–
–
–
ns
ns
ns
ns
ns
ns
tADH
tWEH
tADVH
tDH
Data Input Hold after CLK Rise
Chip Enable Hold after CLK Rise
tCEH
Notes
18. Timing reference level is 1.5V when V
= 3.3V and is 1.25V when V
= 2.5V.
DDQ
DDQ
19. Test conditions shown in (a) of AC Test Loads unless otherwise noted.
20. This part has a voltage regulator internally; t
is the time that the power must be supplied above V (minimum) initially, before a read or write operation can be
POWER
DD
initiated.
21. t
, t
,t
, and t
are specified with AC test conditions shown in part (b) of Figure 3 on page 21. Transition is measured ± 200 mV from steady-state voltage.
CHZ CLZ OELZ
OEHZ
22. At any given voltage and temperature, t
is less than t
and t
is less than t
to eliminate bus contention between SRAMs when sharing the same data
CLZ
OEHZ
OELZ
CHZ
bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve
High Z prior to Low Z under the same system conditions.
23. This parameter is sampled and not 100% tested.
Document Number: 001-66677 Rev. *J
Page 22 of 32
CY7C1441KV33
CY7C1443KV33
CY7C1441KVE33
Timing Diagrams
Figure 4. Read Cycle Timing [24]
t
CYC
CLK
t
t
CL
CH
t
t
ADH
ADS
ADSP
ADSC
t
t
ADH
ADS
t
t
AH
AS
A1
A2
ADDRESS
t
t
WES
WEH
GW, BWE,BW
X
Deselect Cycle
t
t
CES
CEH
CE
t
t
ADVH
ADVS
ADV
OE
ADV suspends burst
t
t
t
CDV
OEV
OELZ
t
t
OEHZ
CHZ
t
DOH
t
CLZ
Q(A2)
Q(A2 + 1)
Q(A2 + 2)
Q(A2
+
3)
Q(A2)
Q(A2
+
1)
Q(A2
+
2)
Q(A1)
Data Out (Q)
High-Z
t
CDV
Burst wraps around
to its initial state
Single READ
BURST
READ
DON’T CARE
UNDEFINED
.
Note
24. On this diagram, when CE is LOW: CE is LOW, CE is HIGH and CE is LOW. When CE is HIGH: CE is HIGH or CE is LOW or CE is HIGH.
1
2
3
1
2
3
Document Number: 001-66677 Rev. *J
Page 23 of 32
CY7C1441KV33
CY7C1443KV33
CY7C1441KVE33
Timing Diagrams (continued)
Figure 5. Write Cycle Timing [25, 26]
t
CYC
CLK
t
t
CL
CH
t
t
ADH
ADS
ADSP
ADSC extends burst
t
t
ADH
ADS
t
t
ADH
ADS
ADSC
t
t
AH
AS
A1
A2
A3
ADDRESS
Byte write signals are ignored for first cycle when
ADSP initiates burst
t
t
WEH
WES
BWE,
BWX
t
t
WEH
WES
GW
t
t
CEH
CES
CE
t
t
ADVH
ADVS
ADV
ADV suspends burst
OE
t
t
DH
DS
Data in (D)
High-Z
D(A2)
D(A2
+
1)
D(A2
+
1)
D(A2
+
2)
D(A2
+
3)
D(A3)
D(A3
+
1)
D(A3 + 2)
D(A1)
t
OEHZ
Data Out (Q)
BURST READ
BURST WRITE
Extended BURST WRITE
Single WRITE
DON’T CARE
UNDEFINED
.
Notes
25. On this diagram, when CE is LOW: CE is LOW, CE is HIGH and CE is LOW. When CE is HIGH: CE is HIGH or CE is LOW or CE is HIGH.
1
2
3
1
2
3
26.
Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BW LOW.
X
Document Number: 001-66677 Rev. *J
Page 24 of 32
CY7C1441KV33
CY7C1443KV33
CY7C1441KVE33
Timing Diagrams (continued)
Figure 6. Read/Write Cycle Timing [27, 28, 29]
t
CYC
CLK
t
t
CL
CH
t
t
ADH
ADS
ADSP
ADSC
t
t
AH
AS
A1
A2
A3
A4
A5
A6
ADDRESS
t
t
WEH
WES
BWE, BW
X
t
t
CEH
CES
CE
ADV
OE
t
t
DH
DS
t
OELZ
t
High-Z
D(A3)
D(A5)
D(A6)
Data In (D)
t
OEHZ
CDV
Data Out (Q)
Q(A1)
Q(A2)
Q(A4)
Q(A4+1)
Q(A4+2)
Q(A4+3)
Back-to-Back
WRITEs
Back-to-Back READs
Single WRITE
BURST READ
DON’T CARE
UNDEFINED
.
Notes
27. On this diagram, when CE is LOW: CE is LOW, CE is HIGH and CE is LOW. When CE is HIGH: CE is HIGH or CE is LOW or CE is HIGH.
1
2
3
1
2
3
28. The data bus (Q) remains in high Z following a Write cycle, unless a new read access is initiated by ADSP or ADSC.
29. GW is HIGH.
Document Number: 001-66677 Rev. *J
Page 25 of 32
CY7C1441KV33
CY7C1443KV33
CY7C1441KVE33
Timing Diagrams (continued)
Figure 7. ZZ Mode Timing [30, 31]
CLK
ZZ
t
t
ZZ
ZZREC
t
ZZI
I
SUPPLY
I
DDZZ
t
RZZI
ALL INPUTS
(except ZZ)
DESELECT or READ Only
Outputs (Q)
High-Z
DON’T CARE
Notes
30. Device must be deselected when entering ZZ mode. See the Cycle Descriptions table for all possible signal conditions to deselect the device.
31. DQs are in high Z when exiting ZZ sleep mode.
Document Number: 001-66677 Rev. *J
Page 26 of 32
CY7C1441KV33
CY7C1443KV33
CY7C1441KVE33
Ordering Information
Table 1 lists the ordering codes. The table contains only the parts that are currently available. If you do not see what you are looking
for, contact your local sales representative. For more information, visit the Cypress website at www.cypress.com and refer to the
product summary page at http://www.cypress.com/products.
Table 1. Ordering Information
Speed (MHz)
Ordering Code
Package Diagram
Part and Package Type
Operating Range
133
CY7C1441KV33-133AXC
CY7C1441KVE33-133AXC
CY7C1441KV33-133AXI
CY7C1441KVE33-133AXI
CY7C1443KV33-133AXI
CY7C1441KV33-133BZXI
51-85050
100-pin TQFP (14 × 20 × 1.4 mm) Pb-free
Commercial
Industrial
51-85195
165-ball FBGA (15 × 17 × 1.4 mm) Pb-free
Ordering Code Definitions
-
XXX XX
X X
33
E
CY
7
C
14XX
KV
Temperature range: X = C or I
C = Commercial = 0 °C to +70 °C; I = Industrial = –40 °C to +85 °C
X = Pb-free; X Absent = Leaded
Package Type: XX = A or BZ
A = 100-pin TQFP
BZ = 165-ball FBGA
Speed Grade: XXX = 133 MHz
33 = 3.3 V VDD
E = Device with ECC; E Absent = Device without ECC
Process Technology: KV 65 nm
Part Identifier: 14XX = 1441 or 1443
1441 = FT, 1M × 36 (36-Mbit)
1443 = FT, 2M × 18 (36-Mbit)
Technology Code: C = CMOS
Marketing Code: 7 = SRAM
Company ID: CY = Cypress
Document Number: 001-66677 Rev. *J
Page 27 of 32
CY7C1441KV33
CY7C1443KV33
CY7C1441KVE33
Package Diagrams
Figure 8. 100-pin TQFP (14 × 20 × 1.4 mm) A100RA Package Outline, 51-85050
ș 2
ș
1
ș
DIMENSIONS
MIN. NOM. MAX.
1.60
NOTE:
SYMBOL
1. ALL DIMENSIONS ARE IN MILLIMETERS.
2. BODY LENGTH DIMENSION DOES NOT
INCLUDE MOLD PROTRUSION/END FLASH.
MOLD PROTRUSION/END FLASH SHALL
A
0.05
0.15
A1
A2
D
1.35 1.40 1.45
15.80 16.00 16.20
13.90 14.00 14.10
21.80 22.00 22.20
19.90 20.00 20.10
NOT EXCEED 0.0098 in (0.25 mm) PER SIDE.
BODY LENGTH DIMENSIONS ARE MAX PLASTIC
D1
E
E1
BODY SIZE INCLUDING MOLD MISMATCH.
3. JEDEC SPECIFICATION NO. REF: MS-026.
0.08
0.08
0°
R
R
ș
0.20
0.20
7°
1
2
ș 1
ș 2
c
0°
11° 12° 13°
0.20
0.22 0.30 0.38
0.45 0.60 0.75
1.00 REF
b
L
L1
L 2
L 3
e
0.25 BSC
0.20
0.65 TYP
51-85050 *G
Document Number: 001-66677 Rev. *J
Page 28 of 32
CY7C1441KV33
CY7C1443KV33
CY7C1441KVE33
Package Diagrams (continued)
Figure 9. 165-ball FBGA (15 × 17 × 1.4 mm (0.5 Ball Diameter)) Package Outline, 51-85195
51-85195 *D
Document Number: 001-66677 Rev. *J
Page 29 of 32
CY7C1441KV33
CY7C1443KV33
CY7C1441KVE33
Acronyms
Document Conventions
Table 2. Acronyms Used in this Document
Units of Measure
Acronym
CE
Description
Table 3. Units of Measure
Chip Enable
Symbol
°C
Unit of Measure
CMOS
FBGA
I/O
Complementary Metal Oxide Semiconductor
Fine-Pitch Ball Grid Array
Input/Output
degree Celsius
megahertz
microampere
milliampere
millisecond
millimeter
nanosecond
picofarad
volt
MHz
µA
mA
ms
mm
ns
JTAG
NoBL
OE
Joint Test Action Group
No Bus Latency
Output Enable
SRAM
TCK
TDI
Static Random Access Memory
Test Clock
pF
V
Test Data-In
W
watt
TDO
TMS
TQFP
WE
Test Data-Out
Test Mode Select
Thin Quad Flat Pack
Write Enable
ECC
Error Correcting Code
Document Number: 001-66677 Rev. *J
Page 30 of 32
CY7C1441KV33
CY7C1443KV33
CY7C1441KVE33
Document History Page
Document Title: CY7C1441KV33/CY7C1443KV33/CY7C1441KVE33, 36-Mbit (1M × 36/2M × 18) Flow-Through SRAM (With
ECC)
Document Number: 001-66677
Submission
Revision
ECN
Description of Change
Date
*E
4680535
04/10/2015 Changed status from Preliminary to Final.
*F
4757974
05/07/2015 Added Logic Block Diagram – CY7C1441KVE33.
Updated Functional Overview:
Updated ZZ Mode Electrical Characteristics:
Changed maximum value of IDDZZ parameter from 89 mA to 75 mA.
*G
*H
4965199
5338013
10/15/2015 Updated Selection Guide:
Updated value of “Maximum Operating Current”.
07/05/2016 Updated Truth Table:
Updated details in “CE3” column corresponding to fifth row of “Deselected Cycle, Power
Down”.
Updated Neutron Soft Error Immunity:
Updated values in “Typ” and “Max” columns corresponding to LSBU (Device without ECC)
parameter.
Updated to new template.
*I
6072311
6745577
02/15/2018 Updated Package Diagrams:
spec 51-85050 – Changed revision from *E to *G.
Updated to new template.
*J
12/05/2019 Updated Ordering Information:
Updated part numbers.
Updated to new template.
Document Number: 001-66677 Rev. *J
Page 31 of 32
CY7C1441KV33
CY7C1443KV33
CY7C1441KVE33
Sales, Solutions, and Legal Information
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© Cypress Semiconductor Corporation, 2011–2019. This document is the property of Cypress Semiconductor Corporation and its subsidiaries (“Cypress”). This document, including any software or
firmware included or referenced in this document (“Software”), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries worldwide. Cypress
reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other intellectual property
rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress hereby grants
you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to modify and reproduce
the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users (either directly or
indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress’s patents that are infringed by the Software (as provided by
Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation of the
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TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
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CYPRESS PRODUCTS, WILL BE FREE FROM CORRUPTION, ATTACK, VIRUSES, INTERFERENCE, HACKING, DATA LOSS OR THEFT, OR OTHER SECURITYINTRUSION (collectively, “Security
Breach”). Cypress disclaims any liability relating to any Security Breach, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from any Security Breach. In
addition, the products described in these materials may contain design defects or errors known as errata which may cause the product to deviate from published specifications. To the extent permitted
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responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. “High-Risk Device”
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medical devices. “Critical Component” means any component of a High-Risk Device whose failure to perform can be reasonably expected to cause, directly or indirectly, the failure of the High-Risk
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Cypress’s published data sheet for the product explicitly states Cypress has qualified the product for use in a specific High-Risk Device, or (ii) Cypress has given you advance written authorization to
use the product as a Critical Component in the specific High-Risk Device and you have signed a separate indemnification agreement.
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in
the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Document Number: 001-66677 Rev. *J
Revised December 5, 2019
Page 32 of 32
i486 is a trademark, and Intel and Pentium are registered trademarks of Intel Corporation. PowerPC is a trademark of IBM Corporation.
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