CY7C1618KV18-300BZXC

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CY7C1618KV18/CY7C1620KV18

144-Mbit DDR II SRAM Two-Word

Burst Architecture

CY7C1618KV18/CY7C1620KV18, 144-Mbit DDR II SRAM Two-Word Burst Architecture

Features

Configuration

■ 144-Mbit density (8M × 18, 4M × 36)

CY7C1618KV18 – 8M × 18

CY7C1620KV18 – 4M × 36

■ 333 MHz clock for high bandwidth

■ Two-word burst for reducing address bus frequency

Functional Description

■ Double data rate (DDR) interfaces (data transferred at

666 MHz) at 333 MHz

The CY7C1618KV18, and CY7C1620KV18 are 1.8-V

synchronous pipelined SRAM equipped with DDR II architecture.

The DDR II consists of an SRAM core with advanced

synchronous peripheral circuitry and a 1-bit burst counter.

Addresses for read and write are latched on alternate rising

edges of the input (K) clock. Write data is registered on the rising

edges of both K and K. Read data is driven on the rising edges

of C and C if provided, or on the rising edge of K and K if C/C are

not provided. On CY7C1618KV18 and CY7C1620KV18, the

burst counter takes in the least significant bit of the external

address and bursts two 18-bit words in the case of

CY7C1618KV18 and two 36-bit words in the case of

CY7C1620KV18 sequentially into or out of the device.

■ Two input clocks (K and K) for precise DDR timing

❐ SRAM uses rising edges only

■ Two input clocks for output data (C and C) to minimize clock

skew and flight time mismatches

■ Echo clocks (CQ and CQ) simplify data capture in high-speed

systems

■ Synchronous internally self-timed writes

■ DDR II operates with 1.5-cycle read latency when DOFF is

asserted high

Asynchronous inputs include an output impedance matching

input (ZQ). Synchronous data outputs (Q, sharing the same

physical pins as the data inputs D) are tightly matched to the two

output echo clocks CQ/CQ, eliminating the need for separately

capturing data from each individual DDR SRAM in the system

design. Output data clocks (C/C) enable maximum system

clocking and data synchronization flexibility.

■ Operates similar to DDR I device with one cycle read latency

when DOFF is asserted low

■ 1.8-V core power supply with high-speed transceiver logic

(HSTL) inputs and outputs

■ Variable drive HSTL output buffers

All synchronous inputs pass through input registers controlled by

the K or K input clocks. All data outputs pass through output

registers controlled by the C or C (or K or K in a single clock

domain) input clocks. Writes are conducted with on-chip

synchronous self-timed write circuitry.

■ Expanded HSTL output voltage (1.4 V–V_DD

❐ Supports both 1.5-V and 1.8-V I/O supply

)

■ Available in 165-ball fine-pitch ball grid array (FBGA) package

(15 ×17 × 1.4 mm)

For a complete list of related documentation, click here.

■ Offered in Pb-free packages

■ JTAG 1149.1 compatible test access port

■ Phase locked loop (PLL) for accurate data placement

Selection Guide

Description

Maximum operating frequency

333 MHz

333

300 MHz

300

250 MHz

250

Unit

MHz

mA

Maximum operating current

× 18

× 36

650

610

Not Offered

660

790

Not Offered

Cypress Semiconductor Corporation

Document Number: 001-44274 Rev. *O

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised April 30, 2020

CY7C1618KV18/CY7C1620KV18

Logic Block Diagram – CY7C1618KV18

Burst

Logic

A0

Write

Reg

Write

Reg

23 22

A

(22:0)

Address

Register

(22:1)

18

LD

K

Output

R/W

CLK

Logic

Gen.

Control

C

DOFF

Read Data Reg.

36

18

CQ

V

REF

18

Reg.

Control

Logic

R/W

18

BWS

DQ

[1:0]

[17:0]

Logic Block Diagram – CY7C1620KV18

Burst

Logic

A0

Write

Reg

Write

Reg

22 21

A

(21:0)

Address

Register

(21:1)

36

LD

K

Output

Logic

Control

CLK

R/W

Gen.

C

DOFF

Read Data Reg.

72

36

CQ

V

REF

36

Reg.

Control

Logic

R/W

36

BWS

DQ

[3:0]

[35:0]

Document Number: 001-44274 Rev. *O

Page 2 of 32

CY7C1618KV18/CY7C1620KV18

Contents

Pin Configurations ...........................................................4

Pin Definitions ..................................................................5

Functional Overview ........................................................6

Read Operations .........................................................6

Write Operations .........................................................6

Byte Write Operations .................................................6

Single Clock Mode ......................................................7

DDR Operation ............................................................7

Depth Expansion .........................................................7

Programmable Impedance ..........................................7

Echo Clocks ................................................................7

PLL ..............................................................................7

Application Example ........................................................8

Truth Table ........................................................................9

Burst Address Table ........................................................9

Write Cycle Descriptions ...............................................10

Write Cycle Descriptions ...............................................11

IEEE 1149.1 Serial Boundary Scan (JTAG) ..................12

Disabling the JTAG Feature ......................................12

Test Access Port .......................................................12

Performing a TAP Reset ...........................................12

TAP Registers ...........................................................12

TAP Instruction Set ...................................................12

TAP Controller State Diagram .......................................14

TAP Controller Block Diagram ......................................15

TAP Electrical Characteristics ......................................15

TAP AC Switching Characteristics ...............................16

TAP Timing and Test Conditions ..................................17

Identification Register Definitions ................................18

Scan Register Sizes .......................................................18

Instruction Codes ...........................................................18

Boundary Scan Order ....................................................19

Power Up Sequence in DDR II SRAM ...........................20

Power Up Sequence .................................................20

PLL Constraints .........................................................20

Maximum Ratings ...........................................................21

Operating Range .............................................................21

Neutron Soft Error Immunity .........................................21

Electrical Characteristics ...............................................21

DC Electrical Characteristics .....................................21

AC Electrical Characteristics ........................................23

Capacitance ....................................................................23

Thermal Resistance ........................................................23

AC Test Loads and Waveforms .....................................23

Switching Characteristics ..............................................24

Switching Waveforms ....................................................26

Read/Write/Deselect Sequence ................................26

Ordering Information ......................................................27

Ordering Code Definitions .........................................27

Package Diagram ............................................................28

Acronyms ........................................................................29

Document Conventions .................................................29

Units of Measure .......................................................29

Document History Page .................................................30

Sales, Solutions and Legal Information .......................32

Worldwide Sales and Design Support .......................32

Products ....................................................................32

PSoC® Solutions ......................................................32

Cypress Developer Community .................................32

Technical Support .....................................................32

Document Number: 001-44274 Rev. *O

Page 3 of 32

CY7C1618KV18/CY7C1620KV18

Pin Configurations

The pin configuration for CY7C1618KV18, and CY7C1620KV18 follow: ^[1]

Figure 1. 165-ball FBGA (15 × 17 × 1.4 mm) pinout

CY7C1618KV18 (8M × 18)

1

CQ

NC

DOFF

NC

TDO

2

A

3

4

5

BWS₁

NC/288M

A

6

7

A

8

9

A

10

A

11

CQ

A

B

C

D

E

F

A

R/W

A

K

LD

DQ9

NC

K

BWS₀

A

NC

V_DDQ

NC

A

NC

DQ8

NC

V_SS

V_DDQ

V_SS

A

A0

V_SS

A

V_SS

V_DDQ

V_SS

A

DQ7

NC

DQ10

DQ11

NC

V_SS

V_DD

V_SS

A

V_SS

V_DD

V_SS

A

NC

DQ6

DQ5

NC

DQ12

NC

G

H

J

DQ13

V_DDQ

NC

V_REF

NC

V_REF

DQ4

NC

ZQ

NC

K

L

NC

DQ14

NC

DQ3

DQ2

NC

DQ15

NC

M

N

P

R

NC

DQ1

NC

DQ16

DQ17

A

NC

A

C

A

NC

DQ0

TDI

TCK

A

C

A

TMS

CY7C1620KV18 (4M × 36)

1

CQ

NC

DOFF

NC

TDO

2

3

4

5

BWS₂

BWS₃

A

6

7

BWS₁

BWS₀

A

8

9

A

10

A

11

A

B

C

D

E

F

A

R/W

A

K

LD

CQ

DQ27

NC

DQ18

DQ28

DQ19

DQ20

DQ21

DQ22

V_DDQ

DQ32

DQ23

DQ24

DQ34

DQ25

DQ26

A

K

A

NC

V_DDQ

NC

A

NC

DQ8

DQ7

DQ16

DQ6

DQ5

DQ14

ZQ

V_SS

V_DDQ

V_SS

A

A0

V_SS

A

V_SS

V_DDQ

V_SS

A

DQ17

NC

DQ29

NC

V_SS

V_DD

V_SS

A

V_SS

V_DD

V_SS

A

DQ15

NC

DQ30

DQ31

V_REF

NC

G

H

J

NC

V_REF

DQ13

DQ12

NC

DQ4

DQ3

DQ2

DQ1

DQ10

DQ0

TDI

K

L

NC

DQ33

NC

M

N

P

R

DQ11

NC

DQ35

NC

A

C

A

DQ9

TMS

TCK

A

C

A

Note

1. NC/288M is not connected to the die and can be tied to any voltage level.

Document Number: 001-44274 Rev. *O

Page 4 of 32

CY7C1618KV18/CY7C1620KV18

Pin Definitions

Pin Name

I/O

Pin Description

DQ_[x:0]

Input Output- Data input output signals: Inputs are sampled on the rising edge of K and K clocks during valid write

Synchronous operations. These pins drive out the requested data when the read operation is active. Valid data is

driven out on the rising edge of both the C and C clocks during read operations or K and K when in single

clock mode. When read access is deselected, Q_[x:0]are automatically tristated.

CY7C1618KV18 − DQ_[17:0]

CY7C1620KV18 − DQ_[35:0]

LD

Input-

Synchronous load: This input is brought low when a bus cycle sequence is defined. This definition

Synchronous includes address and read and write direction. All transactions operate on a burst of 2 data.

BWS₀,

BWS₁,

BWS₂,

BWS₃

Input-

Byte write select (BWS) 0, 1, 2, and 3 − Active low: Sampled on the rising edge of the K and K clocks

Synchronous during write operations. Used to select which byte is written into the device during the current portion of

the write operations. Bytes not written remain unaltered.

CY7C1618KV18 − BWS₀controls D_[8:0]and BWS₁controls D_[17:9].

CY7C1620KV18 − BWS₀controls D_[8:0], BWS₁controls D_[17:9], BWS₂controls D_[26:18]and BWS₃

controls D_[35:27]

.

All the byte write selects are sampled on the same edge as the data. Deselecting a BWS ignores the

corresponding byte of data and it is not written into the device.

A, A₀

Input-

Address inputs: These address inputs are multiplexed for both read and write operations. Internally,

Synchronous the device is organized as 8M × 18 (2 arrays each of 4M × 18) for CY7C1618KV18, and 4M × 36 (2

arrays each of 2M × 36) for CY7C1620KV18.

CY7C1618KV18 – A₀is the input to the burst counter. These are incremented in a linear fashion

internally. 23 address inputs are needed to access the entire memory array.

CY7C1620KV18 – A₀is the input to the burst counter. These are incremented in a linear fashion

internally. 22 address inputs are needed to access the entire memory array. All the address inputs are

ignored when the appropriate port is deselected.

R/W

C

Input-

Synchronous read or write input: When LD is low, this input designates the access type (read when

Synchronous R/W is high, write when R/W is low) for loaded address. R/W must meet the setup and hold times around

edge of K.

Input Clock Positive input clock for output data: C is used in conjunction with C to clock out the read data from

the device. C and C can be used together to deskew the flight times of various devices on the board

back to the controller. See application example for further details.

C

Input Clock Negative input clock for output data: C is used in conjunction with C to clock out the read data from

the device. C and C can be used together to deskew the flight times of various devices on the board

back to the controller. See application example for further details.

K

Input Clock Positive input clock input: The rising edge of K is used to capture synchronous inputs to the device

and to drive out data through Q_[x:0]when in single clock mode. All accesses are initiated on the rising

edge of K.

Input Clock Negative input clock input: K is used to capture synchronous data being presented to the device and

K

to drive out data through Q_[x:0]when in single clock mode.

CQ

Output Clock CQ referenced with respect to C: This is a free running clock and is synchronized to the input clock

for output data (C) of the DDR II. In the single clock mode, CQ is generated with respect to K. The timing

for the echo clocks is shown in the AC Timing table.

Output Clock CQ referenced with respect to C: This is a free running clock and is synchronized to the input clock

for output data (C) of the DDR II. In the single clock mode, CQ is generated with respect to K. The timing

for the echo clocks is shown in the AC Timing table.

CQ

ZQ

Input

Output impedance matching input: This input is used to tune the device outputs to the system data

bus impedance. CQ, CQ, and Q_[x:0]output impedance are set to 0.2 × RQ, where RQ is a resistor

connected between ZQ and ground. Alternatively, this pin can be connected directly to V_DDQ, which

enables the minimum impedance mode. This pin cannot be connected directly to GND or left

unconnected.

Document Number: 001-44274 Rev. *O

Page 5 of 32

CY7C1618KV18/CY7C1620KV18

Pin Definitions (continued)

Pin Name

I/O

Pin Description

DOFF

Input

PLL turn Off − Active low. Connecting this pin to ground turns off the PLL inside the device. The timing

in the PLL turned off operation differs from those listed in this data sheet. For normal operation, this pin

can be connected to a pull-up through a 10 kΩ or less pull-up resistor. The device behaves in DDR I

mode when the PLL is turned off. In this mode, the device can be operated at a frequency of up to

167 MHz with DDR I timing.

TDO

TCK

Output

Input

N/A

Test data-out (TDO) pin for JTAG.

Test clock (TCK) pin for JTAG.

TDI

Test data-in (TDI) pin for JTAG.

TMS

NC

Test mode select (TMS) pin for JTAG.

Not connected to the die: Can be tied to any voltage level.

Reference voltage input: Static input used to set the reference level for HSTL inputs, outputs, and AC

NC/288M

V_REF

Input

Input-

Reference measurement points.

V_DD

V_SS

Power Supply Power supply inputs to the core of the device.

Ground

Ground for the device.

V_DDQ

Power Supply Power supply inputs for the outputs of the device.

from the address location generated by the burst counter is

driven onto the Q_[17:0]. The requested data is valid 0.45 ns from

the rising edge of the output clock (C or C, or K and K when in

single clock mode). To maintain the internal logic, each read

access must be enabled to complete. Read accesses can be

initiated on every rising edge of the positive input clock (K).

Functional Overview

The CY7C1618KV18, and CY7C1620KV18 are synchronous

pipelined burst SRAMs equipped with a DDR interface, which

operates with a read latency of one and a half cycles when DOFF

pin is tied high. When DOFF pin is set low or connected to V_SS,

the device behaves in DDR I mode with a read latency of one

clock cycle.

When read access is deselected, the CY7C1618KV18 first

completes the pending read transactions. Synchronous internal

circuitry automatically tristates the output, following the next

rising edge of the positive output clock (C). This enables a

transition between devices without the insertion of wait states in

a depth expanded memory.

Accesses are initiated on the rising edge of the positive input

clock (K). All synchronous input timing is referenced from the

rising edge of the input clocks (K and K) and all output timing is

referenced to the rising edge of the output clocks (C/C, or K/K

when in single clock mode).

Write Operations

All synchronous data inputs (D_[x:0]) pass through input registers

controlled by the rising edge of the input clocks (K and K). All

synchronous data outputs (Q_[x:0]) pass through output registers

controlled by the rising edge of the output clocks (C/C, or K/K

when in single clock mode).

Write operations are initiated by asserting R/W low and LD low

at the rising edge of the positive input clock (K). The address

presented to address inputs is stored in the write address

register and the least significant bit of the address is presented

to the burst counter. The burst counter increments the address

in a linear fashion. On the following K clock rise, the data

presented to D_[17:0]is latched and stored into the 18-bit write

data register, provided BWS_[1:0]are both asserted active. On the

subsequent rising edge of the Negative Input Clock (K) the

information presented to D_[17:0]is also stored into the write data

register, provided BWS_[1:0]are both asserted active. The 36 bits

of data are then written into the memory array at the specified

location. Write accesses can be initiated on every rising edge of

the positive input clock (K). This pipelines the data flow so that

18 bits of data can be transferred into the device on every rising

edge of the input clocks (K and K).

All synchronous control (R/W, LD, BWS_[0:X]) inputs pass through

input registers controlled by the rising edge of the input clock (K).

CY7C1618KV18 is described in the following sections. The

same basic descriptions apply to CY7C1620KV18.

Read Operations

The CY7C1618KV18 is organized internally as two arrays of

2M × 18. Accesses are completed in a burst of 2 sequential

18-bit data words. Read operations are initiated by asserting

R/W high and LD low at the rising edge of the positive input clock

(K). The address presented to address inputs is stored in the

read address register and the least significant bit of the address

is presented to the burst counter. The burst counter increments

the address in a linear fashion. Following the next K clock rise,

the corresponding 18-bit word of data from this address location

is driven onto the Q_[17:0]using C as the output timing reference.

On the subsequent rising edge of C, the next 18-bit data word

When the write access is deselected, the device ignores all

inputs after the pending write operations have been completed.

Byte Write Operations

Byte write operations are supported by the CY7C1618KV18. A

write operation is initiated as described in Write Operations on

Document Number: 001-44274 Rev. *O

Page 6 of 32

CY7C1618KV18/CY7C1620KV18

page 6. The bytes that are written are determined by BWS₀and

BWS₁, which are sampled with each set of 18-bit data words.

Asserting the appropriate Byte Write Select input during the data

portion of a write latches the data being presented, and writes it

into the device. Deasserting the Byte Write Select input during

the data portion of a write enables the data stored in the device

for that byte to remain unaltered. This feature can be used to

simplify read, modify, or write operations to a byte write

operation.

Depth Expansion

Depth expansion requires replicating the LD control signal for

each bank. All other control signals can be common between

banks as appropriate.

Programmable Impedance

An external resistor, RQ, must be connected between the ZQ pin

on the SRAM and V_SSto enable the SRAM to adjust its output

driver impedance. The value of RQ must be 5 × the value of the

intended line impedance driven by the SRAM. The allowable

range of RQ to guarantee impedance matching with a tolerance

of ±15 percent is between 175 Ω and 350 Ω, with V_DDQ= 1.5 V.

The output impedance is adjusted every 1024 cycles upon power

up to account for drifts in supply voltage and temperature.

Single Clock Mode

The CY7C1618KV18 can be used with a single clock that

controls both the input and output registers. In this mode, the

device recognizes only a single pair of input clocks (K and K) that

control both the input and output registers. This operation is

identical to the operation if the device had zero skew between

the K/K and C/C clocks. All timing parameters remain the same

in this mode. To use this mode of operation, the user must tie C

and C high at power on. This function is a strap option and not

alterable during device operation.

Echo Clocks

Echo clocks are provided on the DDR II to simplify data capture

on high-speed systems. Two echo clocks are generated by the

DDR II. CQ is referenced with respect to C and CQ is referenced

with respect to C. These are free-running clocks and are

synchronized to the output clock of the DDR II. In single clock

mode, CQ is generated with respect to K and CQ is generated

with respect to K. The timing for the echo clocks is shown in the

Switching Characteristics on page 24.

DDR Operation

The CY7C1618KV18 enables high performance operation

through high clock frequencies (achieved through pipelining) and

DDR mode of operation. The CY7C1618KV18 requires a single

No Operation (NOP) cycle during transition from a read to a write

cycle. At higher frequencies, some applications may require a

second NOP cycle to avoid contention.

PLL

These chips use a PLL that is designed to function between

120 MHz and the specified maximum clock frequency. During

power up, when the DOFF is tied high, the PLL is locked after

20 μs of stable clock. The PLL can also be reset by slowing or

stopping the input clock K and K for a minimum of 30 ns.

However, it is not necessary to reset the PLL to lock to the

desired frequency. The PLL automatically locks 20 μs after a

stable clock is presented. The PLL may be disabled by applying

ground to the DOFF pin. When the PLL is turned off, the device

behaves in DDR I mode (with one cycle latency and a longer

access time).

If a read occurs after a write cycle, address and data for the write

are stored in registers. The write information must be stored

because the SRAM cannot perform the last word write to the

array, without conflicting with the read. The data stays in this

register until the next write cycle occurs. On the first write cycle

after the read(s), the stored data from the earlier write is written

into the SRAM array. This is called a posted write.

If a read is performed on the same address on which a write is

performed in the previous cycle, the SRAM reads out the most

current data. The SRAM does this by bypassing the memory

array and reading the data from the registers.

Document Number: 001-44274 Rev. *O

Page 7 of 32

CY7C1618KV18/CY7C1620KV18

Application Example

Figure 2 shows two DDR II used in an application.

Figure 2. Application Example (Width Expansion)

ZQ

SRAM#1

DQ[x:0]

SRAM#2

CQ/CQ

RQ

DQ[x:0]

A

LD R/W BWS C C K K

A LD R/W BWS C C K K

DQ[2x:0]

ADDRESS

LD

R/W

BWS

CLKIN1/CLKIN1

CLKIN2/CLKIN2

SOURCE K

DELAYED K

FPGA / ASIC

Document Number: 001-44274 Rev. *O

Page 8 of 32

CY7C1618KV18/CY7C1620KV18

Truth Table

The truth table for the CY7C1618KV18, and CY7C1620KV18 follow: ^{[2, 3, 4, 5, 6, 7]}

Operation

K

LD

R/W

DQ

Write cycle:

Load address; wait one cycle;

L–H

L

D(A1) at K(t + 1) ↑ D(A2) at K(t + 1) ↑

input write data on consecutive K and K rising edges.

Read cycle:

L–H

L

H

Q(A1) at C(t + 1)↑ Q(A2) at C(t + 2) ↑

Load address; wait one and a half cycle;

read data on consecutive C and C rising edges.

NOP: No operation

L–H

H

X

High Z

Standby: Clock stopped

Stopped

Previous state

Burst Address Table

(CY7C1618KV18, CY7C1620KV18)

First Address (External)

Second Address (Internal)

X..X0

X..X1

X..X0

Notes

2. X = “Don’t Care,” H = Logic HIGH, L = Logic LOW, ↑ represents rising edge.

3. Device powers up deselected with the outputs in a tristate condition.

4. On CY7C1618KV18 and CY7C1620KV18, “A1” represents address location latched by the devices when transaction was initiated and “A2” represents the addresses

sequence in the burst.

5. “t” represents the cycle at which a read/write operation is started. t + 1 and t + 2 are the first and second clock cycles succeeding the “t” clock cycle.

6. Data inputs are registered at K and K rising edges. Data outputs are delivered on C and C rising edges, except when in single clock mode.

7. Ensure that when clock is stopped K = K and C = C = high. This is not essential, but permits most rapid restart by overcoming transmission line charging symmetrically.

Document Number: 001-44274 Rev. *O

Page 9 of 32

CY7C1618KV18/CY7C1620KV18

Write Cycle Descriptions

The write cycle description table for CY7C1618KV18 follows: ^{[8, 9]}

BWS₀BWS₁

K

Comments

K

L

L–H

–

During the data portion of a write sequence:

CY7C1618KV18 − both bytes (D_[17:0]) are written into the device.

L

–

L–H

–

L–H During the data portion of a write sequence:

CY7C1618KV18 − both bytes (D_[17:0]) are written into the device.

L

H

L

–

During the data portion of a write sequence:

CY7C1618KV18 − only the lower byte (D_[8:0]) is written into the device, D_[17:9]remains unaltered.

L

L–H During the data portion of a write sequence:

CY7C1618KV18 − only the lower byte (D_[8:0]) is written into the device, D_[17:9]remains unaltered.

H

L–H

–

During the data portion of a write sequence:

CY7C1618KV18 − only the upper byte (D_[17:9]) is written into the device, D_[8:0]remains unaltered.

L

L–H During the data portion of a write sequence:

CY7C1618KV18 − only the upper byte (D_[17:9]) is written into the device, D_[8:0]remains unaltered.

H

L–H

–

No data is written into the devices during this portion of a write operation.

L–H No data is written into the devices during this portion of a write operation.

Notes

8. X = “Don’t Care,” H = Logic HIGH, L = Logic LOW, ↑ represents rising edge.

9. Is based on a write cycle that was initiated in accordance with the Truth Table on page 9. BWS , BWS , BWS , and BWS can be altered on different portions of a

0

1

2

3

write cycle, as long as the setup and hold requirements are achieved.

Document Number: 001-44274 Rev. *O

Page 10 of 32

CY7C1618KV18/CY7C1620KV18

Write Cycle Descriptions

The write cycle description table for CY7C1620KV18 follows: ^{[10, 11]}

BWS₀BWS₁BWS₂BWS₃

K

Comments

L

L–H

–

During the data portion of a write sequence, all four bytes (D_[35:0]) are written into

the device.

L

–

L–H

–

L–H During the data portion of a write sequence, all four bytes (D_[35:0]) are written into

the device.

L

H

L

H

L

H

L

–

During the data portion of a write sequence, only the lower byte (D_[8:0]) is written

into the device. D_[35:9]remains unaltered.

L

L–H During the data portion of a write sequence, only the lower byte (D_[8:0]) is written

into the device. D_[35:9]remains unaltered.

H

L–H

–

During the data portion of a write sequence, only the byte (D_[17:9]) is written into the

device. D_[8:0]and D_[35:18]remains unaltered.

L

L–H During the data portion of a write sequence, only the byte (D_[17:9]) is written into the

device. D_[8:0]and D_[35:18]remains unaltered.

H

L–H

–

During the data portion of a write sequence, only the byte (D_[26:18]) is written into

the device. D_[17:0]and D_[35:27]remains unaltered.

L

L–H During the data portion of a write sequence, only the byte (D_[26:18]) is written into

the device. D_[17:0]and D_[35:27]remains unaltered.

H

L–H

–

During the data portion of a write sequence, only the byte (D_[35:27]) is written into

the device. D_[26:0]remains unaltered.

L

L–H During the data portion of a write sequence, only the byte (D_[35:27]) is written into

the device. D_[26:0]remains unaltered.

H

L–H

–

No data is written into the device during this portion of a write operation.

L–H No data is written into the device during this portion of a write operation.

Notes

10. X = “Don’t Care,” H = Logic HIGH, L = Logic LOW, ↑ represents rising edge.

11. Is based on a write cycle that was initiated in accordance with the Truth Table on page 9. BWS , BWS , BWS , and BWS can be altered on different portions of a

0

1

2

3

write cycle, as long as the setup and hold requirements are achieved.

Document Number: 001-44274 Rev. *O

Page 11 of 32

CY7C1618KV18/CY7C1620KV18

Instruction Register

IEEE 1149.1 Serial Boundary Scan (JTAG)

Three-bit instructions can be serially loaded into the instruction

register. This register is loaded when it is placed between the TDI

and TDO pins, as shown in TAP Controller Block Diagram on

page 15. Upon power up, the instruction register is loaded with

the IDCODE instruction. It is also loaded with the IDCODE

instruction if the controller is placed in a reset state, as described

in the previous section.

These SRAMs incorporate a serial boundary scan Test Access

Port (TAP) in the FBGA package. This part is fully compliant with

IEEE Standard 1149.1-2001. The TAP operates using JEDEC

standard 1.8 V I/O logic levels.

Disabling the JTAG Feature

It is possible to operate the SRAM without using the JTAG

feature. To disable the TAP controller, TCK must be tied low

(V_SS) to prevent clocking of the device. TDI and TMS are

internally pulled up and may be unconnected. They may

alternatively be connected to V_DDthrough a pull-up resistor. TDO

must be left unconnected. Upon power up, the device comes up

in a reset state, which does not interfere with the operation of the

device.

When the TAP controller is in the Capture-IR state, the two least

significant bits are loaded with a binary ‘01’ pattern to enable fault

isolation of the board level serial test path.

Bypass Register

To save time when serially shifting data through registers, you

can skip certain chips. The bypass register is a single-bit register

that is placed between TDI and TDO pins. This enables shifting

of data through the SRAM with minimal delay. The bypass

register is set low (V_SS) when the BYPASS instruction is

executed.

Test Access Port

Test Clock

The test clock is used only with the TAP controller. All inputs are

captured on the rising edge of TCK. All outputs are driven from

the falling edge of TCK.

Boundary Scan Register

The boundary scan register is connected to all of the input and

output pins on the SRAM. Several No Connect (NC) pins are also

included in the scan register to reserve pins for higher density

devices.

Test Mode Select (TMS)

The TMS input is used to give commands to the TAP controller

and is sampled on the rising edge of TCK. This pin may be left

unconnected if the TAP is not used. The pin is pulled up

internally, resulting in a Logic HIGH level.

The boundary scan register is loaded with the contents of the

RAM input and output ring when the TAP controller is in the

Capture-DR state and is then placed between the TDI and TDO

pins when the controller is moved to the Shift-DR state. The

EXTEST, SAMPLE/PRELOAD, and SAMPLE Z instructions can

be used to capture the contents of the input and output ring.

Test Data-In (TDI)

The TDI pin is used to serially input information into the registers

and can be connected to the input of any of the registers. The

instruction loaded into the TAP instruction register, chooses the

register between TDI and TDO. For information about loading

the instruction register, see the TAP Controller State Diagram on

page 14. TDI is internally pulled up and can be unconnected if

the TAP is unused in an application. TDI is connected to the most

significant bit (MSB) on any register.

The Boundary Scan Order on page 19 shows the order in which

the bits are connected. Each bit corresponds to one of the bumps

on the SRAM package. The MSB of the register is connected to

TDI, and the LSB is connected to TDO.

Identification (ID) Register

The ID register is loaded with a vendor-specific, 32-bit code

during the Capture-DR state when the IDCODE command is

loaded in the instruction register. The IDCODE is hardwired into

the SRAM and can be shifted out when the TAP controller is in

the Shift-DR state. The ID register has a vendor code and other

information described in Identification Register Definitions on

page 18.

Test Data-Out (TDO)

The TDO output pin is used to serially clock data out from the

registers. The output is active, depending upon the current state

of the TAP state machine (see Instruction Codes on page 18).

The output changes on the falling edge of TCK. TDO is

connected to the least significant bit (LSB) of any register.

TAP Instruction Set

Performing a TAP Reset

Eight different instructions are possible with the three-bit

instruction register. All combinations are listed in Instruction

Codes on page 18. Three of these instructions are listed as

RESERVED and cannot be used. The other five instructions are

described in this section in detail.

A Reset is performed by forcing TMS high (V_DD) for five rising

edges of TCK. This Reset does not affect the operation of the

SRAM and can be performed while the SRAM is operating. At

power up, the TAP is reset internally to ensure that TDO comes

up in a High Z state.

Instructions are loaded into the TAP controller during the Shift-IR

state when the instruction register is placed between TDI and

TDO. During this state, instructions are shifted through the

instruction register through the TDI and TDO pins. To execute

the instruction after it is shifted in, the TAP controller is moved

into the Update-IR state.

TAP Registers

Registers are connected between the TDI and TDO pins to scan

the data in and out of the SRAM test circuitry. Only one register

can be selected at a time through the instruction registers. Data

is serially loaded into the TDI pin on the rising edge of TCK. Data

is output on the TDO pin on the falling edge of TCK.

Document Number: 001-44274 Rev. *O

Page 12 of 32

CY7C1618KV18/CY7C1620KV18

IDCODE

PRELOAD places an initial data pattern at the latched parallel

outputs of the boundary scan register cells before the selection

of another boundary scan test operation.

The IDCODE instruction loads a vendor-specific, 32-bit code into

the instruction register. It also places the instruction register

between the TDI and TDO pins and shifts the IDCODE out of the

device when the TAP controller enters the Shift-DR state. The

IDCODE instruction is loaded into the instruction register at

power up or whenever the TAP controller is supplied a

Test-Logic-Reset state.

The shifting of data for the SAMPLE and PRELOAD phases

occurs concurrently when required, that is, while the data

captured is shifted out, the preloaded data can be shifted in.

BYPASS

When the BYPASS instruction is loaded in the instruction register

and the TAP is placed in a Shift-DR state, the bypass register is

placed between the TDI and TDO pins. The advantage of the

BYPASS instruction is that it shortens the boundary scan path

when multiple devices are connected together on a board.

SAMPLE Z

The SAMPLE Z instruction connects the boundary scan register

between the TDI and TDO pins when the TAP controller is in a

Shift-DR state. The SAMPLE Z command puts the output bus

into a High Z state until the next command is supplied during the

Update IR state.

EXTEST

The EXTEST instruction drives the preloaded data out through

the system output pins. This instruction also connects the

boundary scan register for serial access between the TDI and

TDO in the Shift-DR controller state.

SAMPLE/PRELOAD

SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When

the SAMPLE/PRELOAD instructions are loaded into the

instruction register and the TAP controller is in the Capture-DR

state, a snapshot of data on the input and output pins is captured

in the boundary scan register.

EXTEST OUTPUT BUS TRISTATE

IEEE Standard 1149.1 mandates that the TAP controller be able

to put the output bus into a tristate mode.

The TAP controller clock only operates at a frequency up to

20 MHz, while the SRAM clock operates more than an order of

magnitude faster. Since there is a large difference in the clock

frequencies, it is possible that during the Capture-DR state, an

input or output undergoes a transition. The TAP may then try to

capture a signal while in transition (metastable state). This does

not harm the device, but there is no guarantee to the value that

is captured. Repeatable results may not be possible.

The boundary scan register has a special bit located at bit 108.

When this scan cell, called the ‘extest output bus tristate’, is

latched into the preload register during the Update-DR state in

the TAP controller, it directly controls the state of the output

(Q-bus) pins, when the EXTEST is entered as the current

instruction. When high, it enables the output buffers to drive the

output bus. When low, this bit places the output bus into a High Z

condition.

To guarantee that the boundary scan register captures the

correct value of a signal, the SRAM signal must be stabilized

long enough to meet the TAP controller's capture setup plus hold

times (t_CSand t_CH). The SRAM clock input might not be captured

correctly if the design does not stop (or slow) the clock during a

SAMPLE/PRELOAD instruction. If this is an issue, it is still

possible to capture all other signals and simply ignore the value

of the CK and CK captured in the boundary scan register.

This bit can be set by entering the SAMPLE/PRELOAD or

EXTEST command, and then shifting the desired bit into that cell,

during the Shift-DR state. During Update-DR, the value loaded

into that shift-register cell latches into the preload register. When

the EXTEST instruction is entered, this bit directly controls the

output Q-bus pins. Note that this bit is preset high to enable the

output when the device is powered up, and also when the TAP

controller is in the Test-Logic-Reset state.

After the data is captured, it is possible to shift out the data by

putting the TAP into the Shift-DR state. This places the boundary

scan register between the TDI and TDO pins.

Reserved

These instructions are not implemented but are reserved for

future use. Do not use these instructions.

Document Number: 001-44274 Rev. *O

Page 13 of 32

CY7C1618KV18/CY7C1620KV18

TAP Controller State Diagram

The state diagram for the TAP controller follows. ^[12]

TEST-LOGIC

1

RESET

0

1

SELECT

TEST-LOGIC/

SELECT

0

IR-SCAN

IDLE

DR-SCAN

0

1

CAPTURE-DR

0

CAPTURE-IR

0

1

0

1

SHIFT-DR

1

SHIFT-IR

1

EXIT1-DR

0

EXIT1-IR

0

PAUSE-DR

1

PAUSE-IR

1

0

EXIT2-DR

1

EXIT2-IR

1

UPDATE-IR

0

UPDATE-DR

1

0

Note

12. The 0/1 next to each state represents the value at TMS at the rising edge of TCK.

Document Number: 001-44274 Rev. *O

Page 14 of 32

CY7C1618KV18/CY7C1620KV18

TAP Controller Block Diagram

0

Bypass Register

2

1

0

Selection

TDI

Selection

Circuitry

TDO

Instruction Register

Circuitry

31 30

29

.

2

Identification Register

.

108

.

2

Boundary Scan Register

TCK

TMS

TAP Controller

TAP Electrical Characteristics

Over the Operating Range

Parameter ^{[13, 14, 15]}

Description

Output high voltage

Output low voltage

Input high voltage

Input low voltage

Test Conditions

I_OH= −2.0 mA

Min

1.4

1.6

–

Max

–

Unit

V

V_OH1

V_OH2

V_OL1

V_OL2

V_IH

I_OH= −100 μA

I_OL= 2.0 mA

I_OL= 100 μA

–

V

0.4

0.2

V

–

V

0.65 × V_DDV_DD+ 0.3

V

V_IL

–

–0.3

–5

0.35 × V_DD

5

V

I_X

Input and output load current

GND ≤ V_I≤ V_DD

μA

Notes

13. These characteristics pertain to the TAP inputs (TMS, TCK, TDI and TDO). Parallel load levels are specified in the Electrical Characteristics on page 21.

14. Overshoot: V < V + 0.85 V (Pulse width less than t /2), Undershoot: V /2).

> -1.5 V (Pulse width less than t

CYC

IH(AC)

DDQ

CYC

IL(AC)

15. All voltage referenced to ground.

Document Number: 001-44274 Rev. *O

Page 15 of 32

CY7C1618KV18/CY7C1620KV18

TAP AC Switching Characteristics

Over the Operating Range

Parameter ^{[16, 17]}

Description

Min

50

–

Max

–

Unit

ns

t_TCYC

TCK clock cycle time

TCK clock frequency

TCK clock high

t_TF

20

–

MHz

ns

t_TH

20

t_TL

TCK clock low

–

ns

Setup Times

t_TMSS

t_TDIS

TMS setup to TCK clock rise

TDI setup to TCK clock rise

Capture setup to TCK rise

5

–

ns

t_CS

Hold Times

t_TMSH

t_TDIH

TMS hold after TCK clock rise

TDI hold after clock rise

5

–

ns

t_CH

Capture hold after clock rise

Output Times

t_TDOV

t_TDOX

TCK clock low to TDO valid

TCK clock low to TDO invalid

–

0

10

–

ns

Notes

16. t and t refer to the setup and hold time requirements of latching data from the boundary scan register.

CS

CH

17. Test conditions are specified using the load in TAP AC Test Conditions. t /t = 1 ns.

R

F

Document Number: 001-44274 Rev. *O

Page 16 of 32

CY7C1618KV18/CY7C1620KV18

TAP Timing and Test Conditions

Figure 3 shows the TAP timing and test conditions. ^[18]

Figure 3. TAP Timing and Test Conditions

0.9 V

50

ALL INPUT PULSES

1.8 V

0.9 V

Ω

TDO

0 V

Z = 50

Ω

0

C = 20 pF

L

t

TL

TH

GND

(a)

Test Clock

TCK

t

TCYC

t

TMSH

t

TMSS

Test Mode Select

TMS

t

TDIS

t

TDIH

Test Data In

TDI

Test Data Out

TDO

t

TDOV

t

TDOX

Note

18. Test conditions are specified using the load in TAP AC Test Conditions. t /t = 1 ns.

R

F

Document Number: 001-44274 Rev. *O

Page 17 of 32

CY7C1618KV18/CY7C1620KV18

Identification Register Definitions

Value

Instruction Field

Description

CY7C1618KV18

CY7C1620KV18

000

Revision number (31:29)

Cypress device ID (28:12)

Cypress JEDEC ID (11:1)

000

Version number.

11010100010010011

00000110100

11010100010100011

00000110100

Defines the type of SRAM.

Allows unique identification of

SRAM vendor.

ID register presence (0)

1

Indicates the presence of an ID

register.

Scan Register Sizes

Register Name

Bit Size

Instruction

Bypass

3

1

ID

32

109

Boundary Scan

Instruction Codes

Instruction

EXTEST

Code

000

Description

Captures the input and output ring contents.

IDCODE

001

Loads the ID register with the vendor ID code and places the register between TDI and TDO.

This operation does not affect SRAM operation.

SAMPLE Z

010

Captures the input and output contents. Places the boundary scan register between TDI and

TDO. Forces all SRAM output drivers to a High Z state.

RESERVED

011

100

Do Not Use: This instruction is reserved for future use.

SAMPLE/PRELOAD

Captures the input and output ring contents. Places the boundary scan register between TDI

and TDO. Does not affect the SRAM operation.

RESERVED

BYPASS

101

110

111

Do Not Use: This instruction is reserved for future use.

Places the bypass register between TDI and TDO. This operation does not affect SRAM

operation.

Document Number: 001-44274 Rev. *O

Page 18 of 32

CY7C1618KV18/CY7C1620KV18

Boundary Scan Order

Bit No.

0

Bump ID

6R

Bit No.

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

Bump ID

10G

9G

Bit No.

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

Bump ID

6A

Bit No.

84

Bump ID

1J

1

6P

5B

85

2J

2

6N

11F

11G

9F

5A

86

3K

3

7P

4A

87

3J

4

7N

5C

4B

88

2K

5

7R

10F

11E

10E

10D

9E

89

1K

6

8R

3A

90

2L

7

8P

2A

91

3L

8

9R

1A

92

1M

1L

9

11P

10P

10N

9P

2B

93

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

10C

11D

9C

3B

94

3N

1C

1B

95

3M

1N

96

10M

11N

9M

9D

3D

3C

1D

2C

3E

97

2M

3P

11B

11C

9B

98

99

2N

9N

100

101

102

103

104

105

106

107

108

2P

11L

11M

9L

10B

11A

10A

9A

1P

2D

2E

3R

4R

10L

11K

10K

9J

1E

4P

8B

2F

5P

7C

3F

5N

6C

1G

1F

5R

9K

8A

Internal

10J

11J

11H

7A

3G

2G

1H

7B

6B

Document Number: 001-44274 Rev. *O

Page 19 of 32

CY7C1618KV18/CY7C1620KV18

PLL Constraints

Power Up Sequence in DDR II SRAM

■ PLL uses K clock as its synchronizing input. The input must

have low phase jitter, which is specified as t_{KC Var}

DDR II SRAMs must be powered up and initialized in a

predefined manner to prevent undefined operations.

.

■ The PLL functions at frequencies down to 120 MHz.

Power Up Sequence

■ If the input clock is unstable and the PLL is enabled, then the

PLL may lock onto an incorrect frequency, causing unstable

SRAM behavior. To avoid this, provide 20 μs of stable clock to

relock to the desired clock frequency.

■ Apply power and drive DOFF either high or low (all other inputs

can be high or low).

❐ Apply V_DDbefore V_DDQ

.

❐ Apply V_DDQbefore V_REFor at the same time as V_REF

.

❐ Drive DOFF high.

■ Provide stable DOFF (high), power and clock (K, K) for 20 μs

to lock the PLL

Figure 4. Power Up Waveforms

K

Unstable Clock

> 20μs Stable clock

Stable)

DDQ

Start Normal

Operation

/

V

Clock Start (Clock Starts after V

DD

Stable (< +/- 0.1V DC per 50ns )

/

V

V_DDQ

V

V_DD

DD

DDQ

Fix HIGH (or tie to V

)

DDQ

DOFF

Document Number: 001-44274 Rev. *O

Page 20 of 32

CY7C1618KV18/CY7C1620KV18

Maximum Ratings

Operating Range

Exceeding maximum ratings may impair the useful life of the

device. These user guidelines are not tested.

Ambient

[20]

Range

Commercial

Industrial

Temperature (T_A)

V_DD

V_DDQ

Storage temperature ................................ –65 °C to +150 °C

0 °C to +70 °C

1.8 ± 0.1 V 1.4 V to

V_DD

Ambient temperature

with power applied ................................... –55 °C to +125 °C

–40 °C to +85 °C

Supply voltage on V_DDrelative to GND .......–0.5 V to +2.9 V

Supply voltage on V_DDQrelative to GND ...... –0.5 V to +V_DD

DC applied to outputs in High Z ........–0.5 V to V_DDQ+ 0.3 V

DC input voltage ^[19]...........................–0.5 V to V_DD+ 0.3 V

Current into outputs (Low) .......................................... 20 mA

Neutron Soft Error Immunity

Test

Parameter Description

Conditions

Typ Max* Unit

LSBU

LMBU

SEL

Logical

single-bit

upsets

25 °C

85 °C

197 216

FIT/

Mb

Static discharge voltage

(MIL-STD-883, M. 3015) .........................................> 2001 V

Latch up current .....................................................> 200 mA

Logical

multi-bit

upsets

0

0.01 FIT/

Mb

Single event

latch up

0.1

FIT/

Dev

* No LMBU or SEL events occurred during testing; this column represents a

2

statistical χ , 95% confidence limit calculation. For more details refer toApplication

Note Accelerated Neutron SER Testing and Calculation of Terrestrial Failure

Rates – AN54908.

Electrical Characteristics

Over the Operating Range

DC Electrical Characteristics

Over the Operating Range

Parameter ^[21]

V_DD

Description

Power supply voltage

I/O supply voltage

Output high voltage

Output low voltage

Output high voltage

Output low voltage

Input high voltage

Input low voltage

Test Conditions

Min

1.7

Typ

1.8

1.5

–

Max

Unit

V

1.9

V_DD

V_DDQ

V_OH

1.4

V

Note 22

Note 23

V_DDQ/2 – 0.12

V_DDQ– 0.2

V_SS

V_DDQ/2 + 0.12

V_DDQ

V

V_OL

–

V

V_OH(LOW)

V_OL(LOW)

V_IH

I_OH= −0.1 mA, Nominal impedance

–

V

I_OL= 0.1 mA, Nominal impedance

–

0.2

V

V_REF+ 0.1

–0.3

–

V_DDQ+ 0.3

V_REF– 0.1

5

V

V_IL

–

V

I_X

Input leakage current

GND ≤ V_I≤ V_DDQ

−5

–

μA

V

I_OZ

Output leakage current

Input reference voltage ^[24]Typical Value = 0.75 V

GND ≤ V_I≤ V_DDQ,Output disabled

−5

–

5

V_REF

0.68

0.75

0.95

Notes

19. Overshoot: V

20. Power up: assumes a linear ramp from 0 V to V

< V

+ 0.85 V (Pulse width less than t

/2), Undershoot: V

> −1.5 V (Pulse width less than t

/2).

CYC

IH(AC)

DDQ

CYC

IL(AC)

within 200 ms. During this time V < V and V

< V

.

DD(min)

IH

DD

DDQ

DD

21. All voltage referenced to ground.

22. Outputs are impedance controlled. I = –(V

/2)/(RQ/5) for values of 175 Ω < RQ < 350 Ω.

OH

DDQ

23. Outputs are impedance controlled. I = (V

OL

DDQ

24. V

= 0.68 V or 0.45 V

, whichever is larger, V

= 0.95 V or 0.54 V

, whichever is smaller.

DDQ

REF(min)

DDQ

REF(max)

Document Number: 001-44274 Rev. *O

Page 21 of 32

CY7C1618KV18/CY7C1620KV18

Electrical Characteristics (continued)

Over the Operating Range

DC Electrical Characteristics (continued)

Over the Operating Range

Parameter ^[21]

Description

Test Conditions

Min

–

Typ

–

Max

650

790

610

660

410

390

370

Unit

[25]

I_DD

V_DDoperating supply

V_DD= Max, I_OUT= 0 mA, 333 MHz (× 18)

f = f_MAX= 1/t_CYC

mA

(× 36)

–

300 MHz (× 18)

250 MHz (× 36)

–

mA

–

I_SB1

Automatic Power Down

Current

Max V_DD

,

333 MHz (× 18)

(× 36)

–

Both Ports Deselected,

–

V_IN≥ V_IHor V_IN≤ V_IL,

f = f_MAX= 1/t_CYC

Inputs Static

,

300 MHz (× 18)

250 MHz (× 36)

–

mA

–

Note

25. The operation current is calculated with 50% read cycle and 50% write cycle.

Document Number: 001-44274 Rev. *O

Page 22 of 32

CY7C1618KV18/CY7C1620KV18

AC Electrical Characteristics

Over the Operating Range

Parameter ^[26]

Description

Input high voltage

Input low voltage

Test Conditions

Min

V_REF+ 0.2

–

Typ

–

Max

–

Unit

V

V_IH

V_IL

–

V_REF– 0.2

V

Capacitance

Parameter ^[27]

Description

Input capacitance

Output capacitance

Test Conditions

Max

4

Unit

pF

C_IN

C_O

T_A= 25 °C, f = 1 MHz, V_DD= 1.8 V, V_DDQ= 1.5 V

4

pF

Thermal Resistance

165-ballFBGA

Package

Parameter ^[27]

Description

Test Conditions

Unit

Θ

_JA(0 m/s)

_JA(1 m/s)

_JA(3 m/s)

Thermal resistance

(junction to ambient)

Socketed on a 170 × 220 × 2.35 mm, eight-layer printed

circuit board

12.23

11.17

10.42

9.34

°C/W

Θ_JB

Thermal resistance

(junction to board)

Θ_JC

Thermal resistance

(junction to case)

2.10

°C/W

AC Test Loads and Waveforms

Figure 5. AC Test Loads and Waveforms

V_REF= 0.75 V

0.75 V

V_REF

0.75 V

R = 50Ω

OUTPUT

[28]

ALL INPUT PULSES

1.25 V

Z = 50Ω

0

OUTPUT

Device

R = 50Ω

L

0.75 V

Under

Device

Under

0.25 V

Test

5 pF

V_REF= 0.75 V

Slew Rate = 2 V/ns

ZQ

Test

ZQ

RQ =

250Ω

INCLUDING

JIG AND

(a)

(b)

SCOPE

Notes

26. Overshoot: V

< V

+ 0.85 V (Pulse width less than t

/2), Undershoot: V

> −1.5 V (Pulse width less than t

/2).

IH(AC)

DDQ

CYC

IL(AC)

CYC

27. Tested initially and after any design or process change that may affect these parameters.

28. Unless otherwise noted, test conditions assume signal transition time of 2 V/ns, timing reference levels of 0.75 V, V

= 0.75 V, RQ = 250 Ω, V

= 1.5 V, input

REF

DDQ

pulse levels of 0.25 V to 1.25 V, and output loading of the specified I /I and load capacitance shown in (a) of Figure 5.

OL OH

Document Number: 001-44274 Rev. *O

Page 23 of 32

CY7C1618KV18/CY7C1620KV18

Switching Characteristics

Over the Operating Range

Parameters ^{[29, 30]}

333 MHz

300 MHz

250 MHz

Description

Unit

Cypress Consortium

Parameter Parameter

Min

Max

Min

Max

Min

Max

t_POWER

t_CYC

t_KH

V_DD(typical)to the first access ^[31]

K clock and C clock cycle time

Input clock (K/K; C/C) high

Input clock (K/K; C/C) low

1

–

8.4

–

1

–

8.4

–

1

–

8.4

–

ms

ns

t_KHKH

t_KHKL

t_KLKH

t_KHKH

3.0

3.3

4.0

1.6

1.8

1.20

1.35

1.32

1.49

t_KL

–

t_KHKH

–

K clock rise to K clock rise and C

to C rise (rising edge to rising

edge)

t_KHCH

0.0

1.30

0.0

1.45

0.0

1.8

ns

K/K clock rise to C/C clock rise

(rising edge to rising edge)

Setup Times

t_SAt_AVKH

t_SCt_IVKH

Address setup to K clock rise

0.4

–

0.4

–

0.5

–

ns

ControlsetuptoKclockrise(RPS,

WPS)

t_SCDDR

t_IVKH

Double data rate control setup to

clock (K/K) rise (BWS₀, BWS₁,

BWS₂, BWS₃)

0.3

–

0.3

–

0.35

–

ns

t_SD

t_DVKH

D_[X:0]setup to clock (K/K) rise

Hold Times

t_HA

t_HC

t_KHAX

t_KHIX

0.4

–

0.4

–

0.5

–

ns

Address hold after K clock rise

Control hold after K clock rise

(RPS, WPS)

t_HCDDR

t_HD

t_KHIX

DDR control hold after clock (K/K)

rise (BWS₀, BWS₁, BWS₂, BWS₃)

0.3

–

0.3

–

0.35

–

ns

t_KHDX

D_[X:0]hold after Clock (K/K) rise

Notes

29. Unless otherwise noted, test conditions assume signal transition time of 2 V/ns, timing reference levels of 0.75 V, V

= 0.75 V, RQ = 250 Ω, V

= 1.5 V, input pulse

REF

DDQ

levels of 0.25 V to 1.25 V, and output loading of the specified I /I and load capacitance shown in (a) of Figure 5 on page 23.

OL OH

30. When a part with a maximum frequency above 167 MHz is operating at a lower clock frequency, it requires the input timings of the frequency range in which it is being

operated and outputs data with the output timings of that frequency range.

31. This part has an internal voltage regulator; t

is the time that the power is supplied above V min initially before a read or write operation can be initiated.

DD

POWER

Document Number: 001-44274 Rev. *O

Page 24 of 32

CY7C1618KV18/CY7C1620KV18

Switching Characteristics (continued)

Over the Operating Range

Parameters ^{[29, 30]}

333 MHz

300 MHz

250 MHz

Description

Unit

Cypress Consortium

Parameter Parameter

Min

Max

Min

Max

Min

Max

Output Times

t_CO

t_CHQV

t_CHQX

–

0.45

–

0.45

–

0.45

–

ns

C/C clock rise (or K/K in single

clock mode) to data valid

t_DOH

–0.45

Data output hold after output C/C

clock rise (active to active)

t_CCQO

t_CQOH

t_CHCQV

t_CHCQX

–

0.45

–

0.45

–

0.45

–

ns

C/C clock rise to echo clock valid

–0.45

Echo clock hold after C/C clock

rise

t_CQD

t_CQHQV

t_CQHQX

t_CQHCQL

t_CQHCQH

Echo clock high to data valid

Echo clock high to data invalid

Output clock (CQ/CQ) high ^[32]

–

0.25

–

0.27

–

0.30

ns

t_CQDOH

t_CQH

–0.25

1.25

–

–0.27

1.40

–

–0.30

1.75

–

t_CQHCQH

CQ clock rise to CQ clock rise

(rising edge to rising edge) ^[32]

t_CHZ

t_CHQZ

–

0.45

–

0.45

–

0.45

–

ns

Clock (C/C) rise to High Z (Active

to High Z) ^{[33, 34]}

Clock (C/C) rise to Low Z ^{[33, 34]}

t_CLZ

t_CHQX1

–0.45

PLL Timing

t_{KC Var}

Clock phase jitter

–

0.20

–

0.20

–

0.20

–

ns

μs

ns

t_{KC lock}

t_{KC Reset}

PLL lock time (K, C)

K static to PLL reset

20

30

20

30

20

30

t_{KC Reset}

–

Notes

32. These parameters are extrapolated from the input timing parameters (t

design and are not tested in production.

/2 – 250 ps, where 250 ps is the internal jitter). These parameters are only guaranteed by

CYC

33. t

, t

are specified with a load capacitance of 5 pF as in (b) of Figure 5 on page 23. Transition is measured 100 mV from steady-state voltage.

CHZ CLZ

34. At any voltage and temperature t

is less than t

and t

less than t

.

CHZ

CLZ

CHZ

CO

Document Number: 001-44274 Rev. *O

Page 25 of 32

CY7C1618KV18/CY7C1620KV18

Switching Waveforms

Read/Write/Deselect Sequence

Figure 6. Read/Write/Deselect Sequence ^{[35, 36, 37]}

Notes

35. Q00 refers to output from address A0. Q01 refers to output from the next internal burst address following A0, that is, A0 + 1.

36. Outputs are disabled (High Z) one clock cycle after a NOP.

37. In this example, if address A4 = A3, then data Q40 = D30 and Q41 = D31. Write data is forwarded immediately as read results. This note applies to the whole diagram.

Document Number: 001-44274 Rev. *O

Page 26 of 32

CY7C1618KV18/CY7C1620KV18

Ordering Information

The following table contains only the parts that are currently available. If you do not see what you are looking for, contact your local

sales representative. For more information, visit the Cypress website at www.cypress.com and refer to the product summary page at

http://www.cypress.com/products.

Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives and distributors. To find the office

closest to you, visit us at http://www.cypress.com/go/datasheet/offices.

Speed

(MHz)

Package

Diagram

Operating

Range

Ordering Code

Package Type

250 CY7C1620KV18-250BZXC

300 CY7C1618KV18-300BZXC

333 CY7C1618KV18-333BZXC

CY7C1620KV18-333BZXI

51-85195 165-ball FBGA (15 × 17 × 1.4 mm) Pb-free

Commercial

Industrial

Ordering Code Definitions

CY

7

C 16XX

K V18 -

XXX

X

BZ

Temperature Grade: X = C or I

C = Commercial; I = Industrial

Pb-free

Package Type: BZ = 165-ball FBGA

Frequency Range: XXX = 300 MHz or 333 MHz or 250MHz

V18 = 1.8 V

Die Revision

Part Identifier: 16XX = 1618 or 1620

Technology Code: C = CMOS

Marketing Code: 7 = SRAM

Company ID: CY = Cypress

Document Number: 001-44274 Rev. *O

Page 27 of 32

CY7C1618KV18/CY7C1620KV18

Package Diagram

Figure 7. 165-ball FBGA (15 × 17 × 1.40 mm (0.50 Ball Diameter)) Package Outline, 51-85195

51-85195 *E

Document Number: 001-44274 Rev. *O

Page 28 of 32

CY7C1618KV18/CY7C1620KV18

Acronyms

Document Conventions

Units of Measure

Symbol

Acronym

Description

BWS

DDR

DLL

Byte Write Select

Unit of Measure

Double Data Rate

Delay Lock Loop

°C

degree Celsius

failure in time per device

FIT/Dev

FIT/Mb

MHz

µA

failure in time per mega bit

megahertz

microampere

microsecond

milliampere

millimeter

millisecond

nanosecond

ohm

FBGA

HSTL

I/O

Fine-Pitch Ball Grid Array

High-Speed Transceiver Logic

Input/Output

µs

JTAG

LSB

Joint Test Action Group

Least Significant Bit

Logical Single-Bit Upsets

Logical Multi-Bit Upsets

Most Significant Bit

Phase Locked Loop

Quad Data Rate

mA

mm

ms

LSBU

LMBU

MSB

PLL

ns

Ω

%

percent

QDR

SEL

pF

picofarad

Single Event Latch-up

Static Random Access Memory

Test Access Port

V

volt

SRAM

TAP

W

watt

TCK

TDI

Test Clock

Test Data-In

TDO

TMS

Test Data-Out

Test Mode Select

Document Number: 001-44274 Rev. *O

Page 29 of 32

CY7C1618KV18/CY7C1620KV18

Document History Page

Document Title: CY7C1618KV18/CY7C1620KV18, 144-Mbit DDR II SRAM Two-Word Burst Architecture

Document Number: 001-44274

Submission

Rev.

ECN No.

Description of Change

Date

**

1961327

2555945

See ECN New data sheet.

*A

08/22/08

Updated Identification Register Definitions (Changed Revision Number (31:29) from 001 to

000).

Updated Power Up Sequence in DDR II SRAM (description and Figure 4).

Updated Maximum Ratings (Changed Ambient Temperature with Power Applied from “–10

°C to +85 °C” to “–55 °C to +125 °C”).

Updated Electrical Characteristics (Updated DC Electrical Characteristics (Updated the

maximum values of I_DDand I_SB1parameters)).

Updated Thermal Resistance (Included values for 165-ball FBGA package).

*B

2806011

11/12/09

Added Neutron Soft Error Immunity.

Updated Capacitance (Changed maximum value of Input capacitance (C_IN) from 2 pF to 4

pF, changed maximum value of Output capacitance (C_O) from 3 pF to 4 pF).

Updated Ordering Information (By including parts that are available) and added disclaimer

at the top of Ordering Information table.

Updated Package Diagram.

*C

*D

3022441

3243572

09/03/2010 Changed status from Preliminary to Final.

Updated Ordering Information (Updated part numbers) and added Ordering Code Defini-

tions.

Added Acronyms and Units of Measure.

Updated Sales, Solutions and Legal Information.

04/28/2011 Updated Ordering Information (Updated part numbers).

Updated to new template.

*E

*F

3275033

3430142

06/06/2011 No technical updates.

11/04/2011 Updated Ordering Information (Updated part numbers).

Updated Package Diagram.

*G

3565554

03/29/2012 Updated Features (Removed CY7C1616KV18, CY7C1627KV18 related information).

Updated Configuration (Removed CY7C1616KV18, CY7C1627KV18 related information).

Updated Functional Description (Removed CY7C1616KV18, CY7C1627KV18 related

information).

Updated Selection Guide (Removed 250 MHz, 200 MHz, and 167 MHz frequencies related

information).

Removed Logic Block Diagram – CY7C1616KV18.

Removed Logic Block Diagram – CY7C1627KV18.

Updated Pin Configurations (Removed CY7C1616KV18, CY7C1627KV18 related

information).

Updated Pin Definitions (Removed CY7C1616KV18, CY7C1627KV18 related information).

Updated Functional Overview (Removed CY7C1616KV18, CY7C1627KV18 related

information).

Updated Write Cycle Descriptions (Removed CY7C1616KV18 related information).

Removed Write Cycle Descriptions (corresponding to CY7C1627KV18).

Updated Identification Register Definitions (Removed CY7C1616KV18, CY7C1627KV18

related information).

Updated Electrical Characteristics (Updated DC Electrical Characteristics (Removed

CY7C1616KV18, CY7C1627KV18 related information, removed 250 MHz, 200 MHz, and

167 MHz frequencies related information, removed 300 MHz frequency related information

for only CY7C1620KV18)).

Updated Switching Characteristics (Removed 250 MHz, 200 MHz, and 167 MHz

frequencies related information).

Updated Ordering Information (Updated part numbers).

Document Number: 001-44274 Rev. *O

Page 30 of 32

CY7C1618KV18/CY7C1620KV18

Document History Page (continued)

Document Title: CY7C1618KV18/CY7C1620KV18, 144-Mbit DDR II SRAM Two-Word Burst Architecture

Document Number: 001-44274

Submission

Rev.

ECN No.

Description of Change

Date

*H

3702845

08/06/2012 Updated Selection Guide (Included 250 MHz frequency related information).

Updated Electrical Characteristics (Updated DC Electrical Characteristics (Included 250

MHz frequency related information)).

Updated Switching Characteristics (Included 250 MHz frequency related information).

Updated Ordering Information (Updated part numbers).

*I

3800880

4372963

11/02/2012 No technical updates.

Completing Sunset Review.

*J

05/07/2014 Updated Application Example:

Updated Figure 2.

Updated Thermal Resistance:

Updated values of Θ_JAparameter.

Included Θ_JBparameter and its details.

Updated to new template.

*K

*L

4575228

5072740

11/20/2014 Updated Functional Description:

Added “For a complete list of related documentation, click here.” at the end.

01/05/2016 Updated Package Diagram:

spec 51-85195 – Changed revision from *C to *D.

Updated to new template.

Completing Sunset Review.

*M

5131023

02/09/2016 Updated Switching Waveforms:

Updated Read/Write/Deselect Sequence:

Updated Figure 6.

*N

*O

5980689

6872794

11/30/2017 Updated logo and copyright.

04/30/2020 Updated Package Diagram:

spec 51-85195 – Changed revision from *D to *E.

Document Number: 001-44274 Rev. *O

Page 31 of 32

CY7C1618KV18/CY7C1620KV18

Sales, Solutions and Legal Information

Worldwide Sales and Design Support

Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office

closest to you, visit us at Cypress Locations.

®

Products

PSoC Solutions

ARM^®Cortex^®Microcontrollers

cypress.com/arm

cypress.com/automotive

cypress.com/clocks

cypress.com/interface

cypress.com/iot

PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP | PSoC 6 MCU

Automotive

Cypress Developer Community

Clocks & Buffers

Interface

Training | Components

Internet of Things

Memory

Technical Support

cypress.com/memory

cypress.com/mcu

cypress.com/support

Microcontrollers

PSoC

cypress.com/psoc

cypress.com/pmic

cypress.com/touch

cypress.com/usb

Power Management ICs

Touch Sensing

USB Controllers

Wireless Connectivity

cypress.com/wireless

firmware included or referenced in this document (“Software”), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries worldwide. Cypress reserves

all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other intellectual property rights. If

the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress hereby grants you a personal,

non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to modify and reproduce the Software

solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users (either directly or indirectly through

resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as provided by Cypress, unmodified)

to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation of the Software is prohibited.

TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE

OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. No computing

device can be absolutely secure. Therefore, despite security measures implemented in Cypress hardware or software products, Cypress shall have no liability arising out of any security breach, such

as unauthorized access to or use of a Cypress product. CYPRESS DOES NOT REPRESENT, WARRANT, OR GUARANTEE THAT CYPRESS PRODUCTS, OR SYSTEMS CREATED USING

CYPRESS PRODUCTS, WILLBE FREE FROM CORRUPTION,ATTACK, VIRUSES, INTERFERENCE, HACKING, DATALOSS OR THEFT, OR OTHER SECURITYINTRUSION (collectively, “Security

Breach”). Cypress disclaims any liability relating to any Security Breach, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from any Security Breach. In

addition, the products described in these materials may contain design defects or errors known as errata which may cause the product to deviate from published specifications. To the extent permitted

by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any product or

circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is the responsibility

of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. “High-Risk Device” means any

device or system whose failure could cause personal injury, death, or property damage. Examples of High-Risk Devices are weapons, nuclear installations, surgical implants, and other medical devices.

“Critical Component” means any component of a High-Risk Device whose failure to perform can be reasonably expected to cause, directly or indirectly, the failure of the High-Risk Device, or to affect

its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from any use of a Cypress product

as a Critical Component in a High-Risk Device. You shall indemnify and hold Cypress, its directors, officers, employees, agents, affiliates, distributors, and assigns harmless from and against all claims,

costs, damages, and expenses, arising out of any claim, including claims for product liability, personal injury or death, or property damage arising from any use of a Cypress product as a Critical

Component in a High-Risk Device. Cypress products are not intended or authorized for use as a Critical Component in any High-Risk Device except to the limited extent that (i) Cypress's published

data sheet for the product explicitly states Cypress has qualified the product for use in a specific High-Risk Device, or (ii) Cypress has given you advance written authorization to use the product as a

Critical Component in the specific High-Risk Device and you have signed a separate indemnification agreement.

Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in

the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.

Document Number: 001-44274 Rev. *O

Revised April 30, 2020

Page 32 of 32


型号：	CY7C1618KV18-300BZXC
厂家：	Infineon
描述：	DDR-II CIO 时钟双倍数据速率静态存储器内存集成电路
文件：	总33页 (文件大小：768K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

CY7C1618KV18-300BZXC [INFINEON]

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