CY7C65632-48AXC_技术文档

CY7C65632, CY7C65634

HX2VL - Very Low-Power USB 2.0 Hub

Controller

Features

• High performance, low-power USB 2.0 Hub, optimized for low cost designs with minimum bill-of-material

• USB 2.0 hub controller

- Compliant with USB 2.0 specification, TID# 30000060

- Up to four downstream ports support

- Downstream ports are backward compatible with FS, LS

- Single transaction translator (TT) for low cost

• Very low power consumption

- Supports bus-powered and self-powered modes

- Auto switching between bus-powered and self-powered

- Single MCU with 2K ROM and 64 byte RAM

- Lowest power consumption

• Highly integrated solution for reduced BOM cost

- Internal regulator – single power supply 5 V required

- Provision of connecting 3.3 V with external regulator

- Integrated upstream pull-up resistor

- Integrated pull-down resistors for all downstream ports

- Integrated upstream/downstream termination resistors

- Integrated port status indicator control

- 12 MHz +/– 500 ppm external crystal with drive level 600 µW (integrated PLL) clock input with

optional 27/48 MHz oscillator clock input

- Internal power failure detection for ESD recovery

• Downstream port management

- Support individual and ganged mode power management

- Overcurrent detection

- Two port status indicators per downstream port

• Maximum configurability

- VID and PID are configurable through external EEPROM

- Number of ports, removable/non-removable ports are configurable through EEPROM and I/O pin

configuration

- I/O pins can configure gang/individual mode power switching, reference clock source and polarity of power

switch enable pin

- Configuration options also available through mask ROM

• Available in space saving 48-pin (7 × 7 mm) TQFP and 28-pin (5 × 5 mm) QFN packages

• Supports 0°C to 70°C temperature range

Datasheet

www.infineon.com

Please read the Important Notice and Warnings at the end of this document

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HX2VL - Very Low-Power USB 2.0 Hub Controller

Block diagram – CY7C6563X

I2C /

SPI

MCU

D+

D-

RAM ROM

12/27/48

MHz

OSC-in

OR 12

MHz

USB 2.0 PHY

PLL

Serial

Interface

Engine

HS USB

Control Logic

USB Upstream Port

Crystal

5V i/p (for internal regulator)

NC (for external regulator)

Transaction Translator

1.8V

3.3V

Regulator

Hub Repeater

3.3V i/p (with ext. reg. & 28 QFN)

NC (with ext. reg. & 48 TQFP)

3.3V o/p (for int. reg.)

Routing Logic

USB Downstream Port 1

USB Downstream Port 2

USB Downstream Port 3

USB Downstream Port 4

For two port version, USB Downstream

ports 3 and 4 are to be No connect from

the Chip I/O perspective.

USB 2.0

PHY

Port

Control

USB 2.0

PHY

Port

Control

USB 2.0

PHY

Port

Control

USB 2.0

PHY

Port

Control

LED

D+ D-

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HX2VL - Very Low-Power USB 2.0 Hub Controller

Table of contents

Features ...........................................................................................................................................1

Block diagram – CY7C6563X................................................................................................................2

Table of contents...............................................................................................................................3

1 More information............................................................................................................................5

1.1 HX2VL Development Kit..........................................................................................................................................5

2 Introduction...................................................................................................................................6

3 HX2VL architecture .........................................................................................................................7

3.1 USB serial interface engine ....................................................................................................................................7

3.2 HS USB control logic...............................................................................................................................................7

3.3 Hub Repeater ..........................................................................................................................................................7

3.4 MCU..........................................................................................................................................................................7

3.5 Transaction translator............................................................................................................................................7

3.6 Port Control.............................................................................................................................................................7

4 Applications ...................................................................................................................................8

5 Functional overview .......................................................................................................................9

5.1 System initialization ...............................................................................................................................................9

5.2 Enumeration ...........................................................................................................................................................9

5.3 Upstream port.........................................................................................................................................................9

5.4 Downstream ports ..................................................................................................................................................9

5.5 Power switching....................................................................................................................................................10

5.6 Overcurrent detection ..........................................................................................................................................10

5.7 Port indicators ......................................................................................................................................................10

5.8 Power regulator ....................................................................................................................................................10

5.9 External regulation scheme .................................................................................................................................11

5.10 Internal regulation scheme ................................................................................................................................11

6 Pin configurations ........................................................................................................................12

7 Pin definitions ..............................................................................................................................15

8 Pin definitions ..............................................................................................................................18

9 EEPROM Configuration options ......................................................................................................20

10 Pin configuration options ............................................................................................................23

10.1 Power on reset ....................................................................................................................................................23

10.2 Gang/individual power switching mode............................................................................................................23

10.3 Power switch enable pin polarity.......................................................................................................................24

10.4 Port number configuration.................................................................................................................................24

10.5 Non removable ports configuration ..................................................................................................................24

10.6 Reference clock configuration ...........................................................................................................................24

11 Absolute maximum ratings ..........................................................................................................25

12 Operating conditions...................................................................................................................26

13 Electrical characteristics .............................................................................................................27

13.1 DC electrical characteristics...............................................................................................................................27

13.2 AC electrical characteristics ...............................................................................................................................29

14 Thermal resistance......................................................................................................................30

15 Ordering information ..................................................................................................................31

15.1 Ordering code definitions...................................................................................................................................31

16 ^{Package diagrams ...................................................................................................................................................................32}

17 Acronyms ...................................................................................................................................34

18 Document conventions................................................................................................................35

18.1 Units of measure .................................................................................................................................................35

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Table of contents

19 Silicon Errata for the HX2VL, CY7C65632 product family.................................................................36

19.1 Part numbers affected........................................................................................................................................36

19.2 HX2VL Qualification status .................................................................................................................................36

19.3 HX2VL Errata summary.......................................................................................................................................36

Revision history ..............................................................................................................................37

Datasheet

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HX2VL - Very Low-Power USB 2.0 Hub Controller

More information

1

More information

Infineon provides a wealth of data at www.infineon.com to help you to select the right HX2VL device for your

design, and to help you to quickly and effectively integrate the device into your design. For a comprehensive list

of resources, see the HX2VL product page.

• Overview: USB portfolio

• USB 2.0 Hub Controller selectors: HX2LP, HX2VL

• Application notes: Infineon offers a large number of USB application notes covering a broad range of topics,

from basic to advanced level. Recommended application notes for getting started with HX2VL are:

- AN72332 - Guidelines on System Design using Infineon’s USB 2.0 Hub (HX2VL)

- AN69235 - Migrating from HX2/HX2LP to HX2VL

• Reference designs:

- CY4608 HX2VL Very Low-Power USB 2.0 Compliant 4-Port Hub Development Kit

- CY4607 HX2VL Very Low-Power USB 2.0 Compliant 4-Port Hub Development Kit

• Models: HX2VL (CY7C65632/34/42) - IBIS

1.1

HX2VL Development Kit

HX2VL Development Kit board is a tool to demonstrate the features of HX2VL devices (CY7C65632, CY7C65634).

In the initial phase of the design, this board helps developers to understand the chip features and limitations

before proceeding with a complete design. The Development kit includes support documents related to board

hardware, PC application software, and EEPROM configuration data (.iic) files.

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HX2VL - Very Low-Power USB 2.0 Hub Controller

Introduction

2

Introduction

HX2VL™ is Infineon’s next generation family of high performance, very low power USB 2.0 hub controllers. HX2VL

has integrated upstream and downstream transceivers; a USB Serial Interface Engine (SIE); USB Hub Control and

Repeater logic; and Transaction Translator (TT) logic. Infineon has also integrated external components such as

voltage regulator and pull-up/pull-down resistors, reducing the overall bill of materials required to implement a

USB hub system.

The CY7C6563X is a part of the HX2VL portfolio. This device option is for ultra low power but high performance

applications that require up to four downstream ports. All downstream ports share a single transaction

translator. The CY7C6563X is available in 48-pin TQFP and 28-pin QFN package options.

All device options are supported by Infineon’s world class reference design kits, which include board schematics,

bill of materials, Gerber files, Orcad files, and thorough design documentation.

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HX2VL - Very Low-Power USB 2.0 Hub Controller

HX2VL architecture

3

HX2VL architecture

The “Block diagram – CY7C6563X” on page 2 shows the HX2VL single TT hub architecture.

3.1

USB serial interface engine

The serial interface engine (SIE) allows HX2VL to communicate with the USB host. The SIE handles the following

USB activities independently of the Hub Control Block.

• Bit stuffing and unstuffing

• Checksum generation and checking

• TOKEN type identification

• Address checking

3.2

HS USB control logic

‘Hub Control’ block co-ordinates enumeration, suspend and resume. It generates status and control signals for

host access to the hub. It also includes the frame timer that synchronizes the hub to the host. It has status/control

registers which function as the interface to the firmware in the MCU.

3.3

Hub Repeater

The Hub Repeater manages the connectivity between upstream and downstream facing ports that are operating

at the same speed. It supports full and high speed connectivity. According to the USB 2.0 specification, the Hub

Repeater provides the following functions:

• Sets up and tears down connectivity on packet boundaries

• Ensures orderly entry into and out of ‘Suspend’ state, including proper handling of remote wakeups.

3.4

MCU

HX2VL has MCU with 2K ROM and 64 byte RAM. The MCU operates with a 12 MHz clock to decode USB commands

from host and respond to the host. It can also handle GPIO settings to provide higher flexibility to the customers

and control the read interface to the EEPROM which has extended configuration options. The MCU is

programmable while manufacturing in the factory as per customer needs.

3.5

Transaction translator

The transaction translator translates data from one speed to another. A TT takes high speed split transactions

and translates them to full or low speed transactions when the hub is operating at high speed (the upstream port

is connected to a high speed host controller) and has full or low speed devices attached. The operating speed of

a device attached on a downstream port determines whether the routing logic connects a port to the TT or to hub

repeater. When the upstream host and downstream device are functioning at different speeds, the data is routed

through the TT. In all other cases, the data is routed through the repeater. For example, If a full or low speed

device is connected to the high speed host upstream through the hub, then the data transfer route includes TT.

If a high speed device is connected to the high speed host upstream through the hub, the transfer route includes

the repeater. When the hub is connected to a full speed host controller upstream, then high speed peripheral

does not operate at its full capability. These devices only work at full speed. Full and low speed devices connected

to this hub operate at their normal speed.

3.6

Port Control

The downstream ‘Port Control’ block handles the connect/disconnect and over current detection as well as the

power enable and LED control. It also generates the control signals for the downstream transceivers.

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HX2VL - Very Low-Power USB 2.0 Hub Controller

Applications

4

Applications

Typical applications for the HX2VL device family are:

• Docking stations

• Standalone hubs

• Monitor hubs

• Multi-function printers

• Digital televisions

• Advanced port replicators

• Keyboard hubs

• Gaming consoles

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HX2VL - Very Low-Power USB 2.0 Hub Controller

Functional overview

5

Functional overview

The Infineon CY7C6563X USB 2.0 Hubs are low power hub solutions for USB which provide maximum transfer

efficiency. The CY7C6563X USB 2.0 Hubs integrate 1.5 kohm upstream pull-up resistors for full speed operation

and all downstream 15 kohm pull-down resistors and series termination resistors on all upstream and

downstream D+ and D– pins. This results in optimization of system costs by providing built-in support for the

USB 2.0 specification.

5.1

System initialization

On power up, CY7C6563X has an option to enumerate from the default settings in the mask ROM or from reading

an external EEPROM for configuration information. At the most basic level, this EEPROM has the Vendor ID (VID)

and the Product ID (PID), for the customer’s application. For more specialized applications, other configuration

options can be specified. See “EEPROM Configuration options” on page 20 for more details. CY7C6563X verifies

the checksum before loading the EEPROM contents as the descriptors.

5.2

Enumeration

CY7C6563X enables the pull-up resistor on D+ to indicate its presence to the upstream hub, after which a USB Bus

Reset is expected. After a USB Bus Reset, CY7C6563X is in an unaddressed, unconfigured state (configuration

value set to ‘0’). During the enumeration process, the host sets the hub's address and configuration. After the hub

is configured, the full hub functionality is available.

5.3

Upstream port

The upstream port includes the transmitter and the receiver state machine. The transmitter and receiver operate

in high speed and full speed depending on the current hub configuration. The transmitter state machine

monitors the upstream facing port while the Hub Repeater has connectivity in the upstream direction. This

machine prevents babble and disconnect events on the downstream facing ports of this hub from propagating

and causing the hub to be disabled or disconnected by the hub to which it is attached.

5.4

Downstream ports

The CY7C6563X supports a maximum of four downstream ports, each of which may be marked as usable or

removable in the EEPROM configuration, see “EEPROM Configuration options” on page 20. Additionally it can

also be configured by pin strapping, see “Pin configuration options” on page 23^.

Downstream D+ and D– pull-down resistors are incorporated in CY7C6563X for each port. Before the hubs are

configured, the ports are driven SE0 (Single Ended Zero, where both D+ and D– are driven low) and are set to the

unpowered state. When the hub is configured, the ports are not driven and the host may power the ports by

sending a SetPortPower command for each port. After a port is powered, any connect or disconnect event is

detected by the hub. Any change in the port state is reported by the hubs back to the host through the Status

Change Endpoint (endpoint 1).

On receipt of SetPortReset request for a port with a device connected, the hub does as follows:

• Performs a USB Reset on the corresponding port

• Puts the port in an enabled state

• Enables babble detection after the port is enabled.

Babble consists of a non idle condition on the port after EOF2. If babble is detected on an enabled port, that port

is disabled. A ClearPortEnable request from the host also disables the specified port.

Downstream ports can be individually suspended by the host with the SetPortSuspend request. If the hub is not

suspended, a remote wakeup event on that port is reflected to the host through a port change indication in the

Hub Status Change Endpoint. If the hub is suspended, a remote wakeup event on this port is forwarded to the

host. The host may resume the port by sending a ClearPortSuspend command.

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HX2VL - Very Low-Power USB 2.0 Hub Controller

Functional overview

5.5

Power switching

The CY7C6563X includes interface signals for external port power switches. Both ganged and individual (per-port)

configurations are supported by pin strapping, see “Pin configuration options” on page 23.

After enumerating, the host may power each port by sending a SetPortPower request for that port. Power

switching and overcurrent detection are managed using respective control signals (PWR#[n] and OVR#[n]) which

are connected to an external power switch device. Both High/Low enabled power switches are supported and

the polarity is configured through GPIO setting, see “Pin configuration options” on page 23.

5.6

Overcurrent detection

The OVR#[n] pins of the CY7C6563X series are connected to the respective external power switch’s port

overcurrent indication (output) signals. After detecting an overcurrent condition, hub reports overcurrent

condition to the host and disables the PWR#[n] output to the external power device. OVR#[n] has a setup time of

20 ns. It takes 3 to 4 ms from overcurrent detection to de-assertion of PWR#[n]

5.7

Port indicators

The USB 2.0 port indicators are also supported directly by CY7C6563X. According to the specification, each

downstream port of the hub optionally supports a status indicator. The presence of indicators for downstream

facing ports is specified by bit 7 of the wHub Characteristics field of the hub class descriptor. The default

CY7C6563X descriptor specifies that the port indicators are supported. The CY7C6563X port indicators has two

modes of operation: automatic and manual.

On power up the CY7C6563X defaults to automatic mode, where the color of the Port Indicator (green, amber,

off) indicates the functional status of the CY7C6563X port. The LEDs are turned off when the device is suspended.

PORT STATUS

INDICATOR

LED

Figure 1

Port status indicator LED

5.8

Power regulator

CY7C6563X requires 3.3 V source power for normal operation of internal core logic and USB physical layer (PHY).

The integrated low-drop power regulator converts 5 V power input from USB cable (Vbus) to 3.3 V source power.

The 3.3 V power output is guaranteed by an internal voltage reference circuit when the input voltage is within the

4.75 V to 5.25 V range. The regulator’s maximum current loading is 150 mA, which provides tolerance margin over

CY7C6563X’s normal power consumption of below 100 mA. The on chip regulator has a quiescent current of 28 µA.

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HX2VL - Very Low-Power USB 2.0 Hub Controller

Functional overview

5.9

External regulation scheme

CY7C6563X supports both external regulation and internal regulation schemes. When an external regulation is

chosen, then for the 48 pin package, VCC and VREG are to be left open with no connection. The external regulator

output 3.3 V has to be connected to VCC_A and VCC_D pins. This connection has to be done externally, on board.

For the 28-pin package, the 3.3 V output from the external regulator has to be connected to VREG, VCC_A and

VCC_D. The VCC pin has to be left open with no connection. From the external input 3.3 V, 1.8 V is internally

generated for the chip’s internal usage.

5V to 3.3V

Regulator

5V to 3.3V

Regulator

NC

VCC

VREG

VCC

CY7C65632

48 Pin

CY7C65632

28 Pin

VCC_D

VCC_A

VCC_D

VCC_A

External Regulation Scheme

Figure 2

External regulation scheme

5.10

Internal regulation scheme

When the built-in internal regulator is chosen, then the VCC pin has to be connected to a 5 V, in both 48-pin and

28-pin packages. Internally, the built-in regulator generates a 3.3 V and 1.8 V for the chip’s internal usage. Also a

3.3 V output is available at VREG pin, that has to be connected externally to VCC_A and VCC_D.

5V

3.3V

5V

3.3V

VCC

VREG

VCC

CY7C65632

48 Pin

CY7C65632

28 Pin

VCC_D

VCC_A

VCC_D

VCC_A

Internal Regulation Scheme

Figure 3

Internal regulation scheme

Datasheet

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Pin configurations

6

Pin configurations

AMBER[2] / SPI_MOSI /

PWR_PIN_POL

36

35

34

33

32

31

30

29

28

27

26

25

1

2

VCC_A

GND

GREEN[2] /

SPI_MISO / FIXED_PORT2

3

VCC_D

D-

AMBER[3] /

SET_PORT_NUM2

4

D+

GREEN[3] /

FIXED_PORT3

5

DD-[1]

DD+[1]

VCC_A

GND

CY7C65632

48-pin TQFP

6

PWR#[3]

OVR#[3]

PWR#[4]

OVR#[4]

TEST / SCL

RESET#

SEL48

7

8

9

DD-[2]

DD+[2]

RREF

VCC_A

10

11

12

Figure 4

48-pin TQFP (7 × 7 × 1.4 mm) pinout

Datasheet

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HX2VL - Very Low-Power USB 2.0 Hub Controller

Pin configurations

Two Port

AMBER[2] / SPI_MOSI /

PWR_PIN_POL

36

35

34

33

32

31

30

29

28

27

26

25

1

2

VCC_A

GND

GREEN[2] /

SPI_MISO/ FIXED_PORT2

3

VCC_D

NC

D-

4

D+

5

NC

DD-[1]

DD+[1]

VCC_A

GND

CY7C65634

48-pin TQFP

6

NC

7

NC

8

NC

9

NC

DD-[2]

DD+[2]

RREF

VCC_A

10

11

12

TEST / SCL

RESET#

SEL48

Figure 5

48-pin TQFP (7 × 7 × 1.4 mm) pinout

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HX2VL - Very Low-Power USB 2.0 Hub Controller

Pin configurations

D -

D+

1

2

3

4

21

20

19

18

17

VCC_D

OVR # [3]

OVR # [4]

DD - [1]

CY7C65632

28-pin QFN

TEST/

I2C_SCL

DD + [1]

VCC_A

5

RESET#

6

7

DD + [4]

DD - [4]

D

D - [2]

16

15

DD + [2]

Figure 6

28-pin QFN (5 × 5 × 0.8 mm) pinout

Two Port

D -

D+

1

2

3

4

21

20

19

18

17

VCC_D

NC

CY7C65634

28-pin QFN

DD - [1]

NC

TEST/

I2C_SCL

DD + [1]

VCC_A

5

RESET#

DD - [2]

DD + [2]

6

7

NC

16

15

Figure 7

28-pin QFN (5 × 5 × 0.8 mm) pinout

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Pin definitions

7

Pin definitions

Table 1

Pin definitions

48-pin TQFP package

Name

Pin No. Type ^[1]

Description

Power and Clock

VCC_A

1

7

P

V

_{CC_A}. 3.3 V analog power to the chip.

_{CC_A}. 3.3 V analog power to the chip. NC in CY7C65634.

_{CC_D}. 3.3 V digital power to the chip.

_CC. 5 V input to the internal regulator; NC if using external

regulator.

VCC_A

VCC_D

12

16

19

34

38

VCC

47

48

P

V_REG. 5 V–3.3 V regulator o/p during internal regulation; NC if using

external regulator.

VREG

GND

XIN

2

8

13

20

14

15

P

I

GND. Connect to Ground with as short a path as possible.

12 MHz crystal clock input, or 12/27/48 MHz clock input.

12 MHz Crystal OUT.

XOUT

O

Clock source selection inputs.

00: Reserved

SEL48/SEL27

25 / 44

I

01: 48 MHz OSC-in

10: 27 MHz OSC-in

11: 12 MHz Crystal or OSC-in

Active LOW Reset. External reset input, default pull high 10 k;

RESET#

26

37

I

When RESET = low, whole chip is reset to the initial state.

Self Power. Input for selecting self/bus power. 0 is bus powered, 1

is self powered.

SELFPWR

GANG. Default is input mode after power-on-reset.

Gang Mode: Input:1 -> Output is 0 for Normal Operation and 1 for

Suspend.

GANG

39

11

I/O

Individual Mode: Input:0 -> Output is 1 for Normal Operation and 0

for Suspend.

Refer to Gang/Individual Power Switching Modes in Pin

Configuration Options section for details.

649 ohm resistor must be connected between RREF and Ground.

RREF

Notes

1. Pin Types: I = Input, O = Output, P = Power/Ground.;

Z = High Impedance, R_DN= Pad internal Pull Down Resistor, R_UP= Pad internal Pull Up Resistor.

2. The alternate function of these pins as LED indicator is not available if the pins are strapped to logic high,

unless a separate circuit is designed to support logic high disconnect after 60 ms of power-on reset (POR),

when these pins are reconfigured as outputs.

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Pin definitions

Table 1

Pin definitions ^(continued)

48-pin TQFP package

Name

Pin No. Type ^[1]

Description

System Interface

Test

I2C_SCL

I(R_DN

)

Test: 0: Normal Operation & 1: Chip will be put in test mode.

I2C_SCL: Can be used as I2C clock pin to access I2C EEPROM.

27

I/O(R_DN)

Upstream Port

D–

3

4

I/O/Z

Upstream D– Signal.

Upstream D+ Signal.

D+

Downstream Port 1

DD–[1]

5

6

I/O/Z

O(R_DN

Downstream D– Signal. Downstream D– signal of port 1.

Downstream D+ Signal. Downstream D+ signal of port 1.

LED. Driver output for Amber LED. Port Indicator Support. Default

is Active HIGH.

SPI_CS. Can be used as chip select to access external SPI EEPROM.

LED. Driver output for Green LED. Port Indicator Support. Default is

Active HIGH.

SPI_SK. Can be used as SPI Clock to access external SPI EEPROM.

FIXED_PORT1. At POR used to set Port1 as non removable port.

Refer pin configuration Section.

DD+[1]

AMBER[1]^{[1, 2]}

)

46

SPI_CS

GREEN^{[1, 2]}

O(R_DN

)

SPI_SK

FIXED_PORT1

45

O(R_DN

I(R_DN)

)

Active LOW Overcurrent Condition Detection Input. Overcurrent

OVR#[1]

42

43

I(R_UP)

condition detection input for Port 1.

PWR#[1]

I2C_SDA

O/Z

I/O

Power Switch Driver Output. Default is Active LOW.

I2C_SDA. Can be used as I2C Data pin, connected with I2C EEPROM.

Downstream Port 2

DD–[2]

9

10

I/O/Z

O(R_DN

Downstream D– Signal. Downstream D– signal of port 2.

Downstream D+ Signal. Downstream D+ signal of port 2.

LED. Driver output for Amber LED. Port Indicator Support. Default

is Active HIGH.

SPI_MOSI. Can be used as Data Out to access external SPI EEPROM.

PWR_PIN_POL. Used for power switch enable pin polarity setting.

Refer Configuration section.

LED. Driver output for Green LED. Port Indicator Support. Default is

Active HIGH.

DD+[2]

AMBER[2]^[2]

)

SPI_MOSI

PWR_PIN_POL

36

35

O(R_DN

I(R_DN)

GREEN[2]^[2]

O(R_DN

)

SPI_MISO

FIXED_PORT2

I(R_DN

)

SPI_MISO. Can be used as Data In to access external SPI EEPROM.

FIXED_PORT2. At POR used to set Port2 as non removable port.

Refer Configuration section.

Active LOW Overcurrent Condition Detection Input. Overcurrent

OVR#[2]

PWR#[2]

40

41

I(R_UP

O/Z

)

condition detection input for Port 2.

Power Switch Driver Output. Default is Active LOW.

Notes

1. Pin Types: I = Input, O = Output, P = Power/Ground.;

Z = High Impedance, R_DN= Pad internal Pull Down Resistor, R_UP= Pad internal Pull Up Resistor.

2. The alternate function of these pins as LED indicator is not available if the pins are strapped to logic high,

unless a separate circuit is designed to support logic high disconnect after 60 ms of power-on reset (POR),

when these pins are reconfigured as outputs.

Datasheet

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Pin definitions

Table 1

Pin definitions ^(continued)

48-pin TQFP package

Name

Pin No. Type ^[1]

Description

Downstream Port 3

DD–[3]

17

18

I/O/Z

O(R_DN

Downstream D– Signal. NC in CY7C65634.

Downstream D+ Signal. NC in CY7C65634.

LED. Driver output for Amber LED. Port Indicator Support. Default

is Active HIGH.

SET_PORT_NUM2. Used to set port numbering along with

SET_PORT_NUM1. Refer pin configuration section.

NC in CY7C65634.

DD+[3]

AMBER[3]^[2]

)

SET_PORT_NUM2

33

32

I(R_DN

)

GREEN[3]^[2]

O(R_DN

LED. Driver output for Green LED. Port Indicator Support. Default is

Active HIGH.

FIXED_PORT3

I(R_DN

)

FIXED_PORT3. At POR used to set Port3 as non removable port.

Refer pin configuration section.

NC in CY7C65634.

Active LOW Overcurrent Condition Detection Input. Overcurrent

condition detection input for Port 3.

OVR#[3]

PWR#[3]

30

31

I(R_UP

O/Z

)

NC in CY7C65634.

Power Switch Driver Output. Default is Active LOW.

NC in CY7C65634.

Downstream Port 4

DD–[4]

21

22

I/O/Z

O(R_DN

Downstream D– Signal. NC in CY7C65634.

Downstream D+ Signal. NC in CY7C65634.

LED. Driver output for Amber LED. Port Indicator Support. Default

is Active HIGH.

SET_PORT_NUM1. Used to set port numbering along with

SET_PORT_NUM2. Refer configuration section.

NC in CY7C65634.

DD+[4]

AMBER[4]^[2]

)

SET_PORT_NUM1

24

23

I(R_DN

)

GREEN[4]^[2]

O(R_DN

LED. Driver output for Green LED. Port Indicator Support. Default is

Active HIGH.

FIXED_PORT4

I(R_DN

)

FIXED_PORT4. At POR used to set Port4 as non removable port.

Refer configuration section.

NC in CY7C65634.

Active LOW Overcurrent Condition Detection Input. Overcurrent

condition detection input for Port 4.

OVR#[4]

PWR#[4]

28

29

I(R_UP

O/Z

)

NC in CY7C65634.

Power Switch Driver Output. Default is Active LOW.

NC in CY7C65634.

Notes

1. Pin Types: I = Input, O = Output, P = Power/Ground.;

Z = High Impedance, R_DN= Pad internal Pull Down Resistor, R_UP= Pad internal Pull Up Resistor.

2. The alternate function of these pins as LED indicator is not available if the pins are strapped to logic high,

unless a separate circuit is designed to support logic high disconnect after 60 ms of power-on reset (POR),

when these pins are reconfigured as outputs.

Datasheet

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Pin definitions

8

Pin definitions

Table 2

Pin definitions

28-pin QFN package

Name

Pin No. Type^[3]

Description

Power and Clock

VCC_A

5

9

14

21

27

P

V

_{CC_A}. 3.3 V analog power to the chip.

_{CC_D}. 3.3 V digital power to the chip.

VCC_A

VCC_D

VCC

_CC. 5 V input to the internal regulator; NC if using external regulator

V_CC. 5 V–3.3 V regulator o/p during internal regulation; 3.3 V I/P if

using external regulator.

VREG

28

P

XIN

XOUT

10

11

I

O

12 MHz crystal clock input, or 12 MHz clock input.

12 MHz Crystal OUT.

Active LOW Reset. External reset input, default pull high 10 k;

RESET#

17

22

I

When RESET = low, whole chip is reset to the initial state.

Self Power. Input for selecting self/bus power. 0 is bus powered, 1

is self powered.

SELFPWR

GANG. Default is input mode after power-on-reset.

Gang Mode: Input:1 -> Output is 0 for Normal Operation and 1 for

Suspend.

GANG^[4]

23

8

I/O

Individual Mode: Input:0 -> Output is 1 for Normal Operation and 0

for Suspend.

Refer to Gang/Individual Power Switching Modes in Pin

Configuration Options section for details.

649 ohm resistor must be connected between RREF and Ground.

RREF

I/O

System Interface

Test

I(R_DN

)

Test: 0: Normal Operation & 1: Chip will be put in test mode.

I2C_SCL: I2C Clock pin.

Power Switch Driver Output. Default is Active LOW.

I2C_SDA: I2C Data pin.

18

26

I2C_SCL

I/O(R_DN

)

PWR# ^[5]

I2C_SDA

I/O

Upstream Port

D–

D+

1

2

I/O/Z

Upstream D– Signal.

Upstream D+ Signal.

Notes

3. Pin Types: I = Input, O = Output, P = Power/Ground.;

Z = High Impedance, R_DN= Pad internal Pull Down Resistor, R_UP= Pad internal Pull Up Resistor.

4. In Gang mode, only OVR#1 (pin 25) is enabled.

5. PWR#/I2C_SDA can be used as either PWR# or I2C_SDA but not as both. If EEPROM is connected then the pin

will act as I2C_SDA, it will not switch to PWR# mode (as it does in 48-pin TQFP package).

Datasheet

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Pin definitions

Table 2

Pin definitions ^(continued)

28-pin QFN package

Name

Pin No. Type^[3]

Description

Downstream Port 1

DD–[1]

3

4

I/O/Z

Downstream D– Signal.

Downstream D+ Signal.

DD+[1]

Active LOW Overcurrent Condition Detection Input. Overcurrent

condition detection input for Port 1. Only OVR#[1](pin 25) is enabled

in Gang mode. OVR#[2](pin 24), OVR#[3](pin 20) and OVR#[4](pin 19)

are disabled in Gang mode.

OVR#[1]

25

I(R_UP)

Downstream Port 2

DD–[2]

6

7

I/O/Z

Downstream D– Signal.

Downstream D+ Signal.

DD+[2]

Active LOW Overcurrent Condition Detection Input. Overcurrent

condition detection input for Port 2. Only OVR#[1](pin 25) is enabled

in Gang mode.

OVR#[2]

24

I(R_UP)

This (OVR#[2]) pin is disabled in Gang mode.

Downstream Port 3

DD–[3]

12

13

I/O/Z

Downstream D– Signal. NC in CY7C65634.

Downstream D+ Signal. NC in CY7C65634.

DD+[3]

Overcurrent Condition Detection Input. Default is Active LOW.

NC in CY7C65634. Only OVR#[1](pin 25) is enabled in Gang mode.

This (OVR#[3]) pin is disabled in Gang mode.

OVR#[3]

20

I(R_UP)

Downstream Port 4

DD–[4]

15

16

I/O/Z

Downstream D– Signal. NC in CY7C65634.

Downstream D+ Signal. NC in CY7C65634.

DD+[4]

Overcurrent Condition Detection Input. Default is Active LOW.

NC in CY7C65634. Only OVR#[1](pin 25) is enabled in Gang mode.

This (OVR#[4]) pin is disabled in Gang mode.

Ground pin for the chip. It is the solderable exposed pad beneath

the chip. Refer Figure 12.

OVR#[4]

GND

19

I(R_UP

P

)

PAD

Notes

3. Pin Types: I = Input, O = Output, P = Power/Ground.;

Z = High Impedance, R_DN= Pad internal Pull Down Resistor, R_UP= Pad internal Pull Up Resistor.

4. In Gang mode, only OVR#1 (pin 25) is enabled.

5. PWR#/I2C_SDA can be used as either PWR# or I2C_SDA but not as both. If EEPROM is connected then the pin

will act as I2C_SDA, it will not switch to PWR# mode (as it does in 48-pin TQFP package).

Datasheet

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EEPROM Configuration options

9

EEPROM Configuration options

Systems using CY7C6563X have the option of using the default descriptors to configure the hub. Otherwise, it

must have an external EEPROM for the device to have a unique VID, and PID. The CY7C6563X can communicate

with an SPI (microwire) EEPROM like 93C46 or I2C EEPROM like 24C02. Example EEPROM connections are as

shown in the following figure.

SPI EEPROMConnection

VDD

AMBER#[1]

GREEN#[1]

AMBER#[2]

GREEN#[2]

CS

SK

DI

VCC

NC1

NC2

GND

DO

AT93C46

I2C EEPROM Connection

VDD

A0

VCC

WP

A1

TEST

PWR#[1]

A2

SCL

SDA

GND

AT24C02

Figure 8

EEPROM connections

Note The 28-pin QFN package includes only support for I2C EEPROM like ATMEL/24C02N_SU27 D,

MICROCHIP/4LC028 SN0509, SEIKO/S24CS02AVH9. The 48-pin TQFP package includes both I2C and SPI EEPROM

connectivity options. In this case, user can use either SPI or I2C connectivity at a time for communicating to

EEPROM. The 48-pin package supports ATMEL/AT93C46DN-SH-T, in addition to the above mentioned families.

HX2VL can only read from SPI EEPROM. So, field programming of EEPROM is supported only for I2C EEPROM.

CY7C6563X verifies the check sum after power on reset and if validated loads the configuration from the EEPROM.

To prevent this configuration from being overwritten, AMBER[1] is disabled when SPI EEPROM is present.

Datasheet

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HX2VL - Very Low-Power USB 2.0 Hub Controller

EEPROM Configuration options

Table 3

EEPROM configuration options

Byte Value

00h

VID_LSB

01h

VID_MSB

02h

PID_LSB

03h

PID_MSB

04h

ChkSum

05h

06h

07h

Reserved - FEh

Removable Ports

Port Number

08h

09h–0Fh

Maximum Power

Reserved - FFh

10h

11h–3Fh

40h

41h–6Fh

Vendor String Length

Vendor String (ASCII code)

Product String Length

Product String (ASCII Code)

Serial Number Length

Serial Number String

70h

71h to 80h onwards

Default VID is 0x4B4, PID is 0x6570.

Byte 0: VID (LSB)

Least Significant Byte of Vendor ID

Byte 1: VID (MSB)

Most Significant Byte of Vendor ID

Byte2: PID (LSB)

Least Significant Byte of Product ID

Byte 3: PID (MSB)

Most Significant Byte of Product ID

Byte 4: ChkSum

CY7C6563X will ignore the EEPROM settings if ChkSum is not equal to

VID_LSB + VID_MSB + PID_LSB + PID_MSB +1

Byte 5: Reserved

Set to FEh

Byte 6: RemovablePorts

RemovablePorts[4:1] are the bits that indicates whether the device attached to the corresponding

downstream port is removable (set to 0) or non-removable (set to 1). Bit 1 corresponds to Port 1, Bit 2 to Port 2

and so on. Default value is 0 (removable). These bit values are reported appropriately in the

HubDescriptor:DeviceRemovable field.

Bits 0, 5, 6, 7 are set to 0.

Datasheet

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EEPROM Configuration options

Byte 7: Port Number

Port Number indicates the number of downstream ports. The values must be 1 to 4. Default value is 4.

Byte 8: Maximum Power

This value is reported in the Configuration Descriptor: bMax-Power field and is the current in 2 mA increments

that is required from the upstream hubs. The allowed range is 00h (0 mA) to FAh(500 mA). Default value is 32h

(100mA).

Byte 9–15: Reserved

Set to FFh

Byte 16: Vendor String Length

Length of the Vendor String

Byte 17–63: Vendor String

Value of Vendor String.

Byte 64: Product String Length

Length of the Product String

Byte 65–111: Product String

Value of Product String.

Byte 112: Serial Number Length

Length of the Serial Number

Byte 113 onwards: Serial Number String

Serial Number String.

Datasheet

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Pin configuration options

10

Pin configuration options

10.1

Power on reset

The power on reset can be triggered by external reset or internal circuitry. The internal reset is initiated, when

there is an unstable power event for silicon’s internal core power (3.3 V ± 10%). The internal reset is released

2.7 µs± 1.2% after supply reaches power good voltage (2.5 V to 2.8 V). The external reset pin, continuously senses

the voltage level (5 V) on the upstream VBUS as shown in the figure. In the event of USB plug/unplug or drop in

voltage, the external reset is triggered. This reset trigger can be configured using the resistors R1 and R2. Infineon

recommends that the reset time applied in external reset circuit should be longer than that of the internal reset

time.

PCB

Silicon

VBUS

(External 5V)

Ext. VBUS power-good

detection circuit input

(Pin"RESET#")

R1

R2

EXT

Global

Reset#

INT

Int. 3.3V power-good

detection circuit input

(USB PHY reset)

Figure 9

Power on reset circuit

10.2

Gang/individual power switching mode

A single pin is used to set individual / gang mode as well as output the suspend flag. This is done to reduce the

pin count. The individual or gang mode is decided within 20 µs after power on reset. It has a setup time of 1 ns.

50 ms to 60 ms after reset, this pin is changed to output mode. CY7C6563X outputs the suspend flag, after it is

globally suspended. Pull-down resistor of greater than 100K is needed for Individual mode and a pull-up resistor

greater than 100K is needed for Gang mode. Figure below shows the suspend LED indicator schematics. The

polarity of LED must be followed, otherwise the suspend current will be over the spec limitation (2.5 mA).

VDD (3.3V)

100K

PCB

Silicon

GANG MODE

GANG/SUSPEND

SUSPEND OUT

SUSPEND

INDICATOR

100K

0 : INDIVIDUAL MODE

1: GANG MODE

INDIVIDUAL MODE

Figure 10

Power switching mode

Datasheet

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Pin configuration options

Table 4

Features supported in 48-pin and 28-pin packages

Supported features

48-pin

Yes

28-pin

No

Port number configuration

Non-Removable port configuration

Reference clock configuration

Power switch enable polarity

LED Indicator

Yes

No

10.3

Power switch enable pin polarity

The pin polarity is set Active-High by pin-strapping the PWR_PIN_POL pin to 1 and Active-Low by pin-strapping

the PWR_PIN_POL pin to 0. Thus, both kinds of power switches are supported. This feature is not supported in

28-pin QFN package.

10.4

Port number configuration

In addition to the EEPROM configuration, as described above, configuring the hub for 2/3/4 ports is also

supported using pin-strapping SET_PORT_NUM1 and SET_PORT_NUM2, as shown in following table. Pin

strapping option is not supported in the 28-pin QFN package.

Table 5

Port number configuration using pinstrap

SET_PORT_NUM2

SET_PORT_NUM1

# Ports

1 (Port 1)

2 (Port 1/2)

3 (Port 1/2/3)

4 (All ports)

1

0

1

0

1

0

10.5

Non removable ports configuration

In embedded systems, downstream ports that are always connected inside the system, can be set as

non-removable (always connected) ports, by pin-strapping the corresponding FIXED_PORT# pins 1~4 to High,

before power on reset. At POR, if the pin is pull high, the corresponding port is set to non-removable. This is not

supported in the 28-pin QFN package.

10.6

Reference clock configuration

This hub can support, optional 27/48 MHz clock source. When on-board 27/48 MHz clock is present, then using

this feature, system integrator can further reduce the BOM cost by eliminating the external crystal. This is

available through GPIO pin configuration shown as follows. This is not supported in the 28-pin QFN package.

Table 6

Reference clock options

SEL27 Clock source

48 MHz OSC-in

SEL48

0

1

0

1

27 MHz OSC-in

12 MHz X’tal/OSC-in

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Absolute maximum ratings

11

Absolute maximum ratings

Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested.

Table 7

Absolute maximum ratings

Parameter

Ratings

Storage temperature

Ambient temperature

–55°C to +100°C

0°C to +70°C

5 V supply voltage to ground potential

3.3 V supply voltage to ground potential

Voltage at open drain input pins

(OVR#1–4, SELFPWR, RESET#)

–0.5 V to +6.0 V

–0.5 V to +3.6 V

–0.5 V to +5.5 V

3.3 V input voltage for digital I/O

FOSC (oscillator or crystal frequency)

–0.5 V to +3.6 V

12 MHz ± 0.05%

Datasheet

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Operating conditions

12

Operating conditions

Table 8

Operating conditions

Parameter

Conditions

Ambient temperature

0°C to +70°C

0°C to +125°C

4.75 V to +5.25 V

3.15 V to +3.6 V

0.5 V to +3.6 V

–0.5 V to +5.0 V

78.7 °C/W

Ambient max junction temperature

5 V supply voltage to ground potential

3.3 V supply voltage to ground potential

Input voltage for USB signal pins

Voltage at open drain input pins

Thermal characteristics 48-pin TQFP

Thermal characteristics 28-pin QFN

33.3 °C/W

Datasheet

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Electrical characteristics

13

Electrical characteristics

13.1

DC electrical characteristics

Table 9

DC electrical characteristics

Max

Parameter

Description

Conditions

Min

Typ

Unit

External Internal

regulator regulator

P_D

Power dissipation

Excluding USB

signals

–

366.5

–

426.5

mW

V

V_IH

V_IL

I_l

Input high voltage

Input low voltage

Input leakage current Full speed / Low

speed (0 < V_IN< V_CC

2

–

–10

–

0.8

+10

A

)

High speed mode

–5

0

+5

(0 < V_IN< V_CC

I_OH= 8 mA

I_OL= 8 mA

)

V_OH

V_OL

R_DN

Output voltage high

Output low voltage

Padinternalpull-down –

resistor

2.4

–

29

–

59

–

0.4

135

V

K

R_UP

C_IN

Pad internal pull-up

resistor

Input pin capacitance Full speed / Low

speed mode

–

80

–

108

–

140

20

5

pF

High speed mode

–

4

–

4.5

0.786

I_SUSP

Suspend current

1.043

1.3

mA

Notes

6. Current measurement is with device attached and enumerated.

7. No devices attached.

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Electrical characteristics

Table 9

Parameter

I_CC

DC electrical characteristics ^(continued)

Max

Description

Conditions

Min

Typ

Unit

External Internal

regulator regulator

Supply current

4 Active ports^[6]

Full speed host, full

speed devices

–

88.7

81.9

88.2

79.1

72.9

75.9

68.1

61.9

64.9

57.1

51.9

54.7

103.9

88.2

101.2

91.6

78.5

88.7

78.4

67.6

75.4

66.3

57.6

61.1

105.4

89.3

102.3

93

mA

High speed host,

high speed devices

High speed host,

full speed devices

3 Active ports

2 Active ports

1 Active port

Full speed host, full

speed devices

High speed host,

high speed devices

High speed host,

full speed devices

Full speed host, full

speed devices

High speed host,

high speed devices

78.6

88.8

78.6

69.6

76.1

66.7

59.3

62.5

High speed host,

full speed devices

Full speed host, full

speed devices

High speed host,

high speed devices

High speed host,

full speed devices

Full speed host

High speed host

No Active Ports^[7]

–

42.8

44.2

48.9

49.1

50.3

50.6

Notes

6. Current measurement is with device attached and enumerated.

7. No devices attached.

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Electrical characteristics

13.2

AC electrical characteristics

USB Transceiver is USB 2.0 certified in low, full and high speed modes.

Both the upstream USB transceiver and all four downstream transceivers have passed the USB-IF USB 2.0

Electrical Certification Testing.

The 48-pin TQFP package can support communication to EEPROM using either I²C or SPI. The 28-pin QFN package

can support only I²C communication to EEPROM.

AC Characteristics of these two interfaces to EEPROM are summarized in tables below:

Table 10

Parameter

t_CSS

t_CSH

t_SKH

t_SKL

t_DIS

t_DIH

t_PD1

AC characteristics of SPI EEPROM interface

Parameter

CS setup time

CS hold time

SK high time

SK low time

DI setup time

DI hold time

Output delay to ‘1’

Output delay to ‘0’

Min

3.0

1.0

2.2

1.8

2.4

–

Typ

–

Max

–

1.8

Units

µs

t_PD0

–

Table 11

AC characteristics of I²C EEPROM interface

Parameter

1.8 V–5.5 V

2.5 V–5.5 V

Parameter

Units

Min

Max

100

–

Min

Max

400

–

f_SCL

t_LOW

SCL clock frequency

Clock LOW Period

0.0

4.7

4.0

4.7

4.0

200.0

0

0.0

1.2

0.6

100.0

0

kHz

µs

t_HIGH

t_SU:STA

t_SU:STO

t_HD:STA

t_HD:STO

t_SU:DAT

t_HD:DAT

t_DH

Clock HIGH Period

–

Start condition setup time

Stop condition setup time

Start condition hold time

Stop condition hold time

Data in setup time

Data in hold time

Data out hold time

Clock to output

–

ns

100

0.1

–

4.5

10

50

0.1

–

5

t_AA

t_WR

µs

ns

Write cycle time

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Thermal resistance

14

Thermal resistance

Table 12

Thermal resistance

48-pinTQFP 28-pin QFN

Parameter

Description

Unit

package

78.7

package

33.3

_JA

_JC

Thermal resistance (junction to ambient)

Thermal resistance (junction to case)

°C/W

35.3

18.4

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Ordering information

15

Ordering information

Table 13

Ordering information

Ordering code

Device

Package type

CY7C65632, CY7C65634-48AXC

CY7C65632, CY7C65634-28LTXC

CY7C65632, CY7C65634-48AXCT

CY7C65632, CY7C65634-28LTXCT

CY7C65634-48AXC

4 port Single-TT hub (configurable 48-pin TQFP Bulk

with GPIOs and EEPROM)

4 port Single-TT hub (configurable 28-pin QFN Bulk

with GPIOs and EEPROM)

4 port Single-TT hub (configurable 48-pin TQFP - Tape and reel

with GPIOs and EEPROM)

4 port Single-TT hub (configurable 28-pin QFN - Tape and reel

with GPIOs and EEPROM)

2 port Single-TT hub (configurable 48-pin TQFP Bulk

with GPIOs and EEPROM)

CY7C65634-28LTXC

2 port Single-TT hub (configurable 28-pin QFN Bulk

with GPIOs and EEPROM)

CY7C65634-48AXCT

2 port Single-TT hub (configurable 48-pin TQFP - Tape and reel

with GPIOs and EEPROM)

CY7C65634-28LTXCT

2 port Single-TT hub (configurable 28-pin QFN - Tape and reel

with GPIOs and EEPROM)

15.1

Ordering code definitions

CY

7

C 656 3X - XX XX

X

C

X

X = T or blank

T = Tape and reel; blank = Bulk

Temperature range:

C = Commercial

Pb-free

Package type: XX = A or LT

A = TQFP

LT = Q FN

Pin count: XX = 48 or 28

48 = 48 pins; 28 = 28 pins

Specific product identifier: 3X = 32 or 34

Part identifier

Technology code: C = CMOS

Marketing code

Company ID: CY = Cypress, An Infineon Technologies

company

Datasheet

31

001-67568 Rev. *N

2023-02-13

HX2VL - Very Low-Power USB 2.0 Hub Controller

Package diagrams

16

Package diagrams

The CY7C65632, CY7C65634 is available in following packages:

51-85135 *C

Figure 11

48-pin TQFP (7 × 7 × 1.4 mm) package outline, 51-85135

Datasheet

32

001-67568 Rev. *N

2023-02-13

HX2VL - Very Low-Power USB 2.0 Hub Controller

Package diagrams

001-64621 *A

28-pin QFN ((5 × 5 × 0.8 mm) 3.5 × 3.5 E-Pad (Sawn)) package outline, 001-64621

Figure 12

Datasheet

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001-67568 Rev. *N

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HX2VL - Very Low-Power USB 2.0 Hub Controller

Acronyms

17

Acronyms

Table 14

Acronyms

Acronym

Description

AC

alternating current

ASCII

EEPROM

EMI

ESD

GPIO

I/O

american standard code for information interchange

electrically erasable programmable read only memory

electromagnetic interference

electrostatic discharge

general purpose input/output

input/output

LED

light emitting diode

LSB

least significant bit

MSB

PCB

PLL

most significant bit

printed circuit board

phase-locked loop

POR

PSoC™

QFN

RAM

ROM

SIE

power on reset

Programmable System-on-Chip™

quad flat no leads

random access memory

read only memory

serial interface engine

TQFP

TT

thin quad flat pack

transaction translator

USB

universal serial bus

Datasheet

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HX2VL - Very Low-Power USB 2.0 Hub Controller

Document conventions

18

Document conventions

18.1

Units of measure

Table 15

Units of measure

Symbol

Unit of measure

°C

degree Celsius

kilohertz

kilohm

kHz

k

MHz

A

s

W

mA

mm

ms

mW

ns

megahertz

microampere

microsecond

microwatt

milliampere

millimeter

millisecond

milliwatt

nanosecond

ohm



%

percent

pF

ppm

V

picofarad

parts per million

volt

W

watt

Datasheet

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001-67568 Rev. *N

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HX2VL - Very Low-Power USB 2.0 Hub Controller

Silicon Errata for the HX2VL, CY7C65632

product family

19

Silicon Errata for the HX2VL, CY7C65632 product family

This section describes the errata for the HX2VL, CY7C65632. The details include errata trigger conditions, scope

of impact, available workarounds, and silicon revision applicability.

Contact your local Infineon Sales Representative, if you have any questions.

19.1

Part numbers affected

Part number

Device characteristics

CY7C65632

USB 2.0 Single TT Hub

19.2

HX2VL Qualification status

Product Status: In production

19.3

HX2VL Errata summary

This table defines the errata applicability to available HX2VL family devices.

Silicon

Items

Part numbers

Workaround

Fix status

Revision

1. USB device is not

CY7C65632

Rev. **

Issue a Port-Reset from host No fix

USB application or driver if planned.

the USB device commands

STALLed

recognized properly if a

disconnect followed by a

connect event happen

during hub suspend

1. USB device is not recognized properly if a disconnect followed by a connect event happen during hub suspend

•Problem definition

HX2VL sometimes does not recognize Downstream (DS) USB device after coming out of suspend if the

connected DS device is disconnected and connected back to the same DS port during hub suspend state.

•Parameters affected

N/A.

•Trigger condition(s)

Disconnect followed by a Connect event of DS device from the hub during suspend state.

•Scope of impact

The issue is not observed with standard Microsoft driver/class devices such as mouse, keyboard, mass

storage, etc. as the standard class drivers recover the device using Port-Reset command when there is a STALL

from the DS devices.

•Workaround

Issue a Port-Reset from host USB application or driver to recover the DS device when it STALLS.

•Fix status

No fix planned.

Datasheet

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HX2VL - Very Low-Power USB 2.0 Hub Controller

Revision history

Document

Date

Description of changes

revision

**

2011-03-02

New data sheet.

Updated Functional overview:

Updated Port indicators:

Added a Note “Pin-strapping GREEN#[1] and GREEN#[2] enables proprietary

function that may affect the normal functionality of HX2VL. Configuring Port

#1 and #2 as non-removable by pin-strapping should be avoided.”.

Updated Pin configurations:

Updated Figure 4 (Pin 37 of the 48-pin TQFP package was named

SELF_PWR. It is changed to SELFPWR.).

Updated Figure 5 (Pin 37 of the 48-pin TQFP package was named

SELF_PWR. It is changed to SELFPWR.).

Updated Pin definitions (for 48-pin TQFP package):

Changed value from 680  to 650  in description of RREF pin.

Updated Functional overview:

*A

2011-05-06

Updated Power regulator:

Changed regulator’s maximum current loading from 200 mA to 150 mA.

Updated Pin configuration options:

Updated Power switch enable pin polarity:

Replaced first two occurrences of the word “setting” with “pin-strapping”.

Updated Electrical characteristics:

Updated DC electrical characteristics:

Changed typical value of I_SUSPparameter from 693.3 µA to 786 µA.

Changed maximum value of I_SUSPparameter 693.7 µA to 903 µA.

Updated typical and maximum values of I_CCparameter.

Changed status from Preliminary to Final.

Updated Pin configurations:

Included CY7C65634 related information.

Updated Pin definitions (for 48-pin TQFP package):

Changed description of OVR# pins from “Default is Active LOW” to “Active

LOW Overcurrent Condition Detection Input” (since the polarity is not

configurable).

Updated Pin definitions (for 28-pin QFN package):

Changed description of OVR# pins from “Default is Active LOW” to “Active

LOW Overcurrent Condition Detection Input” (since the polarity is not

configurable).

Updated Electrical characteristics:

Updated DC electrical characteristics:

Updated minimum, typical, and maximum values of R_DNand R_UP

parameters to 81 k103 k and 181 k.

*B

*C

2011-07-25

2011-08-04

No technical updates.

Datasheet

37

001-67568 Rev. *N

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HX2VL - Very Low-Power USB 2.0 Hub Controller

Revision history

Document

Date

Description of changes

revision

Updated Pin configurations:

Updated Figure 4 (Renamed SPI_DI to SPI_MOSI, renamed SPI_DO to

SPI_MISO respectively for clarity).

Updated Figure 5 (Renamed SPI_DI to SPI_MOSI, renamed SPI_DO to

SPI_MISO respectively for clarity).

Updated Figure 6 (Updated pin 26 to describe the alternate function

I2C_SDA.).

Updated Figure 7 (Updated to reflect pin 20 as NC).

Updated Pin definitions (for 48-pin TQFP package):

Renamed SPI_DI to SPI_MOSI, renamed SPI_DO to SPI_MISO respectively

for clarity.

*D

2011-10-18

Updated Pin definitions (for 28-pin QFN package):

Added Note 5 and referred the same note in PWR#.

Minor text edits to add clarity.

Updated EEPROM Configuration options:

Removed text “Strings must comply with the USB specification. The first

byte (Byte 16) must be the length of the string in bytes, the second must be

0x03, and the string must be in ASCII code.” below “Vendor string”, “Product

string” and “Serial Number string”.

*E

2011-01-25

Updated Functional overview:

Updated Overcurrent detection:

Included text “OVR#[n] has a setup time of 20 ns. It takes 3 to 4 ms from

overcurrent detection to de-assertion of PWR#[n].”.

Completing Sunset Review.

Updated EEPROM Configuration options:

Changed the value of Byte 5 to FEh to match with the tabular column.

Updated Electrical characteristics:

Updated DC electrical characteristics:

*F

2012-07-02

2013-05-09

Splitted the Max column into two columns namely External regulator and

Internal regulator for I_SUSPand I_CCparameters and updated the

corresponding values.

Added Thermal resistance.

Updated to new template.

*G

Added Silicon Errata for the HX2VL, CY7C65632 product family.

Datasheet

38

001-67568 Rev. *N

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HX2VL - Very Low-Power USB 2.0 Hub Controller

Revision history

Document

Date

Description of changes

revision

Added More information.

Updated Functional overview:

Updated Port indicators:

Updated description.

Updated Pin definitions (for 48-pin TQFP package):

Replaced “Active LOW” with “Active HIGH” in “Description” column

corresponding to pin numbers 46, 45, 36, 35, 33, 32, 24, 23 (as LEDs are active

HIGH by default).

Added Note 2 and referred the same note in “Name” column corresponding

to pin numbers 46, 45, 36, 35, 33, 32, 24, 23.

Updated Pin definitions (for 28-pin QFN package):

Added Note 4 and referred the same note in “Name” column corresponding

to pin number 23.

*H

2015-02-17

Updated Electrical characteristics:

Updated DC electrical characteristics:

Updated all values corresponding to R_DNand R_DUPparameters.

Added Note 6 and 7 and referred the same notes in “Description” column

corresponding to I_CCparameter (for Active ports and No active ports).

Updated Package diagrams:

spec 51-85135 – Changed revision from *B to *C.

spec 001-64621 – Changed revision from ** to *A.

Updated Silicon Errata for the HX2VL, CY7C65632 product family:

Updated HX2VL Qualification status:

Changed Product Status from “Sampling” to “In production”.

Completing Sunset Review.

Updated Features:

Updated description.

Updated Pin definitions (for 28-pin QFN package):

Updated details in “Description” column corresponding to OVR#[1],

OVR#[2], OVR#[3], and OVR#[4] pins.

Updated to new template.

*I

2016-07-21

Updated More information:

Updated description.

*J

2016-12-07

2017-05-05

Updated to new template.

*K

Updated Cypress Logo and Copyright.

Updated Pin configurations:

Updated Figure 4 (Removed old Cypress Logo).

Updated Figure 5 (Removed old Cypress Logo).

Updated Figure 6 (Removed old Cypress Logo).

Updated Figure 7 (Removed old Cypress Logo).

Updated Silicon Errata for the HX2VL, CY7C65632 product family:

Updated HX2VL Errata summary:

*L

2018-04-13

Updated description.

Updated to new template.

Added watermark “Not Recommended for New Designs” across the

*M

*N

2021-05-20

2023-02-13

document.

Updated to new template.

Removed watermark “Not Recommended for New Designs” across the

document.

Updated hyperlinks across the document.

Migrated to Infineon template.

Completing Sunset Review.

Datasheet

39

001-67568 Rev. *N

2023-02-13

Please read the Important Notice and Warnings at the end of this document

Trademarks

All referenced product or service names and trademarks are the property of their respective owners.

IMPORTANT NOTICE

WARNINGS

The information given in this document shall in no Due to technical requirements products may contain

Edition 2023-02-13

Published by

event be regarded as a guarantee of conditions or dangerous substances. For information on the types

characteristics (“Beschaffenheitsgarantie”).

in question please contact your nearest Infineon

Technologies office.

With respect to any examples, hints or any typical

Infineon Technologies AG

81726 Munich, Germany

values stated herein and/or any information Except as otherwise explicitly approved by Infineon

regarding the application of the product, Infineon Technologies in a written document signed by

Technologies hereby disclaims any and all authorized

representatives

of

Infineon

warranties and liabilities of any kind, including Technologies, Infineon Technologies’ products may

without limitation warranties of non-infringement of not be used in any applications where a failure of the

intellectual property rights of any third party.

product or any consequences of the use thereof can

reasonably be expected to result in personal injury.

In addition, any information given in this document

is subject to customer’s compliance with its

obligations stated in this document and any

applicable legal requirements, norms and standards

concerning customer’s products and any use of the

product of Infineon Technologies in customer’s

applications.

Do you have a question about this

document?

Email:

erratum@infineon.com

The data contained in this document is exclusively

intended for technically trained staff. It is the

responsibility of customer’s technical departments

to evaluate the suitability of the product for the

intended application and the completeness of the

product information given in this document with

respect to such application.

Document reference

001-67568 Rev. *N


型号：	CY7C65632-48AXC
厂家：	Infineon
描述：	4 port Single-TT hub (configurable with GPIOs, LED indicator and EEPROM) with 48-pin TQFP Bulk, C-grade 可编程只读存储器电动程控只读存储器电可擦编程只读存储器时钟外围集成电路
文件：	总40页 (文件大小：595K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

CY7C65632-48AXC [INFINEON]

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