CY7C68013A-56PVXCT_技术文档

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Infineon continues to support existing part numbers. Please continue to use the

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CY7C68013A/CY7C68014A

CY7C68015A/CY7C68016A

EZ-USB FX2LP USB Microcontroller

High-Speed USB Peripheral Controller

EZ-USB FX2LP USB Microcontroller High-Speed USB Peripheral Controller

■ 3.3-V operation with 5-V tolerant inputs

Features

■ Vectored USB interrupts and GPIF/FIFO interrupts

■ Separate data buffers for the setup and data portions of a

■ USB 2.0 USB IF Hi-Speed certified (TID # 40460272)

■ Single-chip integrated USB 2.0 transceiver, smart SIE, and

enhanced 8051 microprocessor

CONTROL transfer

■ Integrated I²C controller; runs at 100 or 400 kHz^[1]

■ Fit-, form-, and function-compatible with the FX2

❐ Pin-compatible0

■ Four integrated FIFOs

❐ Object-code-compatible

❐ Functionally compatible (FX2LP is a superset)

❐ Integrated glue logic and FIFOs lower system cost

❐ Automatic conversion to and from 16-bit buses

❐ Master or slave operation

❐ Uses external clock or asynchronous strobes

❐ Easy interface to ASIC and DSP ICs

■ Ultra-low power: I_CCno more than 85 mA in any mode

❐ Ideal for bus- and battery-powered applications

■ Software: 8051 code runs from:

■ Available in commercial and industrial temperature grades (all

packages except VFBGA)

❐ Internal RAM, which is downloaded through USB

❐ Internal RAM, which is loaded from EEPROM

❐ External memory device (128-pin package)

Features (CY7C68013A/14A only)

■ 16 KB of on-chip code/data RAM

■ CY7C68014A: Ideal for battery-powered applications

❐ Suspend current: 100 A (typ)

■ Four programmable BULK, INTERRUPT, and

ISOCHRONOUS endpoints

❐ Buffering options: Double, triple, and quad

■ CY7C68013A: Ideal for nonbattery-powered applications

❐ Suspend current: 300 A (typ)

■ Additional programmable (BULK/INTERRUPT) 64-byte

endpoint

■ Available in five Pb-free packages with up to 40 GPIOs

❐ 128-pinTQFP(40GPIOs), 100-pinTQFP(40GPIOs), 56-pin

QFN (24 GPIOs), 56-pin SSOP (24 GPIOs), and 56-pin

VFBGA (24 GPIOs)

■ 8-bit or 16-bit external data interface

■ Smart media standard ECC generation

Features (CY7C68015A/16A only)

■ GPIF™ (general programmable interface)

■ CY7C68016A: Ideal for battery-powered applications

❐ Suspend current: 100 A (typ)

❐ Enables direct connection to most parallel interfaces

❐ Programmable waveform descriptors and configuration

registers to define waveforms

❐ Supports multiple ready (RDY) inputs and control (CTL)

outputs

■ CY7C68015A: Ideal for nonbattery-powered applications

❐ Suspend current: 300 A (typ)

■ Available in Pb-free 56-pin QFN package (26 GPIOs)

■ Integrated, industry-standard, enhanced 8051

❐ 48-MHz, 24-MHz, or 12-MHz CPU operation

❐ Four clocks per instruction cycle

❐ Two USARTs

■ Two more GPIOs than CY7C68013A/14A enabling additional

features in the same footprint

Functional Description

❐ Three counter/timers

❐ Expanded interrupt system

❐ Two data pointers

For a complete list of related resources, click here.

Notes

2

1. The actual I C clock frequency will be different. The measured I C clock frequency when set for 100 kHz and 400 kHz is around 85 kHz and 300 kHz respectively.

2. For information on silicon errata, see “Errata” on page 68. Details include trigger conditions, devices affected, and proposed workaround.

Cypress Semiconductor Corporation

Document Number: 38-08032 Rev. AD

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised April 30, 2021

CY7C68013A/CY7C68014A

CY7C68015A/CY7C68016A

More Information

Cypress provides a wealth of data at www.cypress.com to help you to select the right device for your design, and to help you to quickly

and effectively integrate the device into your design. For a comprehensive list of resources, see the application note AN65209 - Getting

Started with FX2LP.

■ Overview: USB Portfolio, USB Roadmap

EZ-USB FX2LP Development Kit

The CY3684 EZ-USB FX2LP Development Kit is a complete

development resource for FX2LP.

■ USB 2.0 Product Selectors: FX2LP, AT2LP, NX2LP-Flex, SX2

■ Application notes: Cypress offers a large number of USB appli-

cation notes covering a broad range of topics, from basic to

advanced level. Recommended application notes for getting

started with FX2LP are:

The CY3689 EZ-USB FX2LP Discovery Kit is a newly designed

kit that helps beginners and experienced users to implement

different applications using FX2LP

The development kit contains collateral materials for the

firmware, hardware, and software aspects of a design using

FX2LP.

❐ AN65209 - Getting Started with FX2LP

❐ AN15456 - Guide to Successful EZ-USB^®FX2LP™ and

EZ-USB FX1™ Hardware Design and Debug

❐ AN50963 - EZ-USB^®FX1™/FX2LP™ Boot Options

❐ AN66806 - EZ-USB^®FX2LP™ GPIF Design Guide

❐ AN61345 - Implementing an FX2LP™- FPGA Interface

❐ AN57322 - Interfacing SRAM with FX2LP over GPIF

GPIF™ Designer

FX2LP™ General Programmable Interface (GPIF) provides an

independent hardware unit, which creates the data and control

signals required by an external interface. FX2LP GPIF Designer

allows users to create and modify GPIF waveform descriptors for

EZ-USB FX2/ FX2LP family of chips using a graphical user

interface. Extensive discussion of general GPIF discussion and

programming using GPIF Designer is included in FX2LP

Technical Reference Manual and GPIF Designer User Guide,

distributed with GPIF Designer. AN66806 - Getting Started with

EZ-USB^®FX2LP™ GPIF can be a good starting point.

❐ AN4053 - Streaming Data through Isochronous/Bulk End-

points on EZ-USB^®FX2 and EZUSB FX2LP

❐ AN63787 - EZ-USB^®FX2LP™ GPIF and Slave FIFO Con-

figuration Examples using 8-bit Asynchronous Interface

For complete list of Application notes, click here.

■ Code Examples:

❐ USB Hi-Speed

■ Technical Reference Manual (TRM):

❐ EZ-USB FX2LP Technical Reference Manual

■ Reference Designs:

❐ CY4661 - External USB Hard Disk Drives (HDD) with

Fingerprint Authentication Security

❐ FX2LP DMB-T/H TV Dongle reference design

■ Models: IBIS

Document Number: 38-08032 Rev. AD

Page 2 of 74

CY7C68013A/CY7C68014A

CY7C68015A/CY7C68016A

Logic Block Diagram

High-performance micro

using standard tools

24 MHz

Ext. XTAL

with lower-power options

FX2LP

I²C

/0.5

/1.0

/2.0

8051 Core

x20

Master

VCC

12/24/48 MHz,

four clocks/cycle

PLL

Abundant I/O

including two USARTs

Additional I/Os (24)

1.5k

connected for

full speed

General

ADDR (9)

programmable I/F

to ASIC/DSP or bus

standards such as

D+

D–

GPIF

USB

2.0

XCVR

CY

Smart

USB

16 KB

RAM

RDY (6)

CTL (6)

ATAPI, EPP, etc.

ECC

1.1/2.0

Engine

Integrated

full speed and

high speed

XCVR

Up to 96 MBytes/s

burst rate

4 kB

FIFO

8/16

Enhanced USB core

Simplifies 8051 code

“Soft Configuration”

Easy firmware changes

FIFO and endpoint memory

(master or slave operation)

Cypress’s EZ-USB^®FX2LP™ (CY7C68013A/14A) is

a

With EZ-USB FX2LP, the Cypress Smart SIE handles most of

the USB 1.1 and 2.0 protocol in hardware, freeing the embedded

microcontroller for application-specific functions and decreasing

the development time to ensure USB compatibility.

low-power version of the EZ-USB FX2™(CY7C68013), which is

a highly integrated, low-power USB 2.0 microcontroller. By

integrating the USB 2.0 transceiver, serial interface engine (SIE),

enhanced 8051 microcontroller, and a programmable peripheral

interface in a single chip, Cypress has created a cost-effective

solution that provides superior time-to-market advantages with

low power to enable bus-powered applications.

The general programmable interface (GPIF) and Master/Slave

Endpoint FIFO (8-bit or 16-bit data bus) provide an easy and

glueless interface to popular interfaces such as ATA, UTOPIA,

EPP, PCMCIA, and most DSP/processors.

The ingenious architecture of FX2LP results in data transfer

rates of over 53 Mbytes per second (the maximum allowable

USB 2.0 bandwidth), while still using a low-cost 8051

microcontroller in a package as small as a 56 VFBGA (5 mm ×

5 mm). Because it incorporates the USB 2.0 transceiver, the

FX2LP is more economical, providing a smaller-footprint solution

than a USB 2.0 SIE or external transceiver implementations.

The FX2LP draws less current than the FX2 (CY7C68013), has

double the on-chip code/data RAM, and is fit, form, and function

compatible with the 56-, 100-, and 128-pin FX2.

Five packages are defined for the family: 56-ball VFBGA, 56-pin

SSOP, 56-pin QFN, 100-pin TQFP, and 128-pin TQFP.

Document Number: 38-08032 Rev. AD

Page 3 of 74

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CY7C68015A/CY7C68016A

Contents

Applications ......................................................................5

Functional Overview ........................................................5

USB Signaling Speed ..................................................5

8051 Microprocessor ...................................................5

I²C Bus ........................................................................5

Buses ..........................................................................5

USB Boot Methods ......................................................6

ReNumeration .............................................................6

Bus-Powered Applications ..........................................6

Interrupt System ..........................................................6

Reset and Wakeup ......................................................9

Program/Data RAM ...................................................10

Register Addresses ...................................................12

Endpoint RAM ...........................................................13

External FIFO Interface .............................................15

GPIF ..........................................................................15

ECC Generation ........................................................16

USB Uploads and Downloads ...................................16

Autopointer Access ...................................................16

I²C Controller .............................................................16

Compatible with Previous Generation

Data Memory Read ^{..................................................................44}

Data Memory Write

..................................................................45

PORTC Strobe Feature Timings ...............................46

GPIF Synchronous Signals .......................................47

Slave FIFO Synchronous Read .................................48

Slave FIFO Asynchronous Read ...............................49

Slave FIFO Synchronous Write .................................50

Slave FIFO Asynchronous Write ...............................51

Slave FIFO Synchronous Packet End Strobe ...........52

Slave FIFO Asynchronous Packet End Strobe .........54

Slave FIFO Output Enable ........................................54

Slave FIFO Address to Flags/Data ............................54

Slave FIFO Synchronous Address ............................55

Slave FIFO Asynchronous Address ..........................55

Sequence Diagram ....................................................56

Ordering Information ......................................................60

Ordering Code Definitions .........................................60

Package Diagrams ..........................................................61

PCB Layout Recommendations ....................................65

Quad Flat Package No Leads (QFN) Package

Design Notes ...................................................................66

Acronyms ........................................................................67

Document Conventions .................................................67

Units of Measure .......................................................67

Errata ...............................................................................68

Part Numbers Affected ..............................................68

CY7C68013A/14A/15A/16A Qualification Status ......68

CY7C68013A/14A/15A/16A Errata Summary ...........68

Document History Page .................................................69

Sales, Solutions, and Legal Information ......................74

Worldwide Sales and Design Support .......................74

Products ....................................................................74

PSoC® Solutions .......................................................74

Cypress Developer Community .................................74

Technical Support .....................................................74

EZ-USB FX2 ..............................................................17

CY7C68013A/14A and CY7C68015A/16A

Differences ................................................................17

Pin Assignments ............................................................18

CY7C68013A/15A Pin Descriptions ..........................25

Register Summary ..........................................................34

Absolute Maximum Ratings ..........................................41

Operating Conditions .....................................................41

Thermal Characteristics .................................................41

DC Electrical Characteristics ........................................42

USB Transceiver .......................................................42

AC Electrical Characteristics ........................................43

USB Transceiver .......................................................43

Program Memory Read .............................................43

Document Number: 38-08032 Rev. AD

Page 4 of 74

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Applications

Figure 1. Crystal Configuration

■ Portable video recorder

■ MPEG/TV conversion

■ DSL modems

24 MHz

C1

C2

12 pF

■ ATA interface

■ Memory card readers

■ Legacy conversion devices

■ Cameras

20 × PLL

12-pF capacitor values assume a trace capacitance

of 3 pF per side on a four-layer FR4 PCA

■ Scanners

The CLKOUT pin, which can be three-stated and inverted using

internal control bits, outputs the 50% duty cycle 8051 clock, at

the selected 8051 clock frequency: 48 MHz, 24 MHz, or 12 MHz.

■ Wireless LAN

■ MP3 players

■ Networking

USARTs

The “Reference Designs” section of the Cypress web site

provides additional tools for typical USB 2.0 applications. Each

reference design comes complete with firmware source and

object code, schematics, and documentation. Visit

www.cypress.com for more information.

FX2LP contains two standard 8051 USARTs, addressed through

Special Function Register (SFR) bits. The USART interface pins

are available on separate I/O pins, and are not multiplexed with

port pins.

UART0 and UART1 can operate using an internal clock at

230 KBaud with no more than 1% baud rate error. 230 KBaud

operation is achieved by an internally derived clock source that

generates overflow pulses at the appropriate time. The internal

clock adjusts for the 8051 clock rate (48 MHz, 24 MHz, and

12 MHz) such that it always presents the correct frequency for

Functional Overview

USB Signaling Speed

FX2LP operates at two of the three rates defined in the USB

Specification Revision 2.0, dated April 27, 2000:

the 230-KBaud operation^[3]

.

■ Full speed, with a signaling bit rate of 12 Mbps

■ High speed, with a signaling bit rate of 480 Mbps

Special Function Registers

Certain 8051 SFR addresses are populated to provide fast

access to critical FX2LP functions. These SFR additions are

shown in Table 1 on page 6. Bold type indicates nonstandard,

enhanced 8051 registers. The two SFR rows that end with “0”

and “8” contain bit-addressable registers. The four I/O ports A to

D use the SFR addresses used in the standard 8051 for ports 0

to 3, which are not implemented in FX2LP. Because of the faster

and more efficient SFR addressing, the FX2LP I/O ports are not

addressable in external RAM space (using the MOVX

instruction).

FX2LP does not support the Low Speed signaling mode of

1.5 Mbps.

8051 Microprocessor

The 8051 microprocessor embedded in the FX2LP family has

256 bytes of register RAM, an expanded interrupt system, three

timer/counters, and two USARTs.

8051 Clock Frequency

2

FX2LP has an on-chip oscillator circuit that uses an external

24-MHz (±100 ppm) crystal with the following characteristics:

I C Bus

FX2LP supports the I²C bus as a master only at 100/400 kHz^[4]

.

SCL and SDA pins have open-drain outputs and hysteresis

inputs. These signals must be pulled up to 3.3 V, even if no I²C

device is connected.

■ Parallel resonant

■ Fundamental mode

■ 500-W drive level

Buses

■ 12-pF (5% tolerance) load capacitors

All packages, 8-bit or 16-bit “FIFO” bidirectional data bus,

multiplexed on I/O ports B and D. 128-pin package: adds 16-bit

output-only 8051 address bus, 8-bit bidirectional data bus.

An on-chip PLL multiplies the 24-MHz oscillator up to 480 MHz,

as required by the transceiver/PHY; internal counters divide it

down for use as the 8051 clock. The default 8051 clock

frequency is 12 MHz. The clock frequency of the 8051 can be

changed by the 8051 through the CPUCS register, dynamically.

Notes

3. 115-KBaud operation is also possible by programming the 8051 SMOD0 or SMOD1 bits to a “1” for UART0, UART1, or both respectively.

2

4. The actual I C clock frequency will be different.The measured I C clock frequency when set for 100 kHz and 400 kHz is around 85 kHz and 300 kHz respectively.

Document Number: 38-08032 Rev. AD

Page 5 of 74

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Table 1. Special Function Registers

x

0

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

8x

IOA

9x

Ax

Bx

IOD

Cx

Dx

Ex

ACC

–

Fx

B

–

IOB

IOC

SCON1

PSW

SP

EXIF

INT2CLR

IOE

SBUF1

–

DPL0

DPH0

DPL1

DPH1

DPS

PCON

TCON

TMOD

TL0

MPAGE

INT4CLR

OEA

OEB

OEC

OED

OEE

–

T2CON

–

SCON0

SBUF0

AUTOPTRH1

AUTOPTRL1

reserved

AUTOPTRH2

AUTOPTRL2

reserved

IE

IP

EICON

EIE

–

EIP

–

EP2468STAT

EP24FIFOFLGS

EP68FIFOFLGS

–

EP01STAT

GPIFTRIG

RCAP2L

RCAP2H

TL2

–

TL1

–

TH0

–

TH1

GPIFSGLDATH

GPIFSGLDATLX

GPIFSGLDATLNOX

TH2

–

CKCON

–

AUTOPTRSET-UP

–

Two control bits in the USBCS (USB Control and Status) register

control the ReNumeration process: DISCON and RENUM. To

simulate a USB disconnect, the firmware sets DISCON to 1. To

reconnect, the firmware clears DISCON to 0.

USB Boot Methods

During the power-up sequence, internal logic checks the I²C port

for the connection of an EEPROM whose first byte is either 0xC0

or 0xC2. If found, it uses the VID/PID/DID values in the EEPROM

in place of the internally stored values (0xC0), or it boot-loads the

EEPROM contents into internal RAM (0xC2). If no EEPROM is

detected, FX2LP enumerates using internally stored descriptors.

The default ID values for FX2LP are VID/PID/DID (0x04B4,

Before reconnecting, the firmware sets or clears the RENUM bit

to indicate whether the firmware or the Default USB Device

handles device requests over endpoint zero: if RENUM = 0, the

Default USB Device handles device requests; if RENUM = 1, the

firmware services the requests.

0x8613, 0xAxxx where xxx = Chip revision)^[5]

.

Bus-Powered Applications

Table 2. Default ID Values for FX2LP

Default VID/PID/DID

The FX2LP fully supports bus-powered designs by enumerating

with less than 100 mA as required by the USB 2.0 specification.

Vendor ID

Product ID

0x04B4 Cypress Semiconductor

0x8613 EZ-USB FX2LP

Depends on chip revision

Interrupt System

INT2 Interrupt Request and Enable Registers

Device release 0xAnnn (nnn = chip revision where first

FX2LP implements an autovector feature for INT2 and INT4.

There are 27 INT2 (USB) vectors, and 14 INT4 (FIFO/GPIF)

vectors. See EZ-USB Technical Reference Manual (TRM) for

more details.

silicon = 001)

ReNumeration

Because the FX2LP’s configuration is soft, one chip can take on

the identities of multiple distinct USB devices.

USB Interrupt Autovectors

The main USB interrupt is shared by 27 interrupt sources. To

save the code and processing time that is required to identify the

individual USB interrupt source, the FX2LP provides a second

level of interrupt vectoring, called Autovectoring. When a USB

interrupt is asserted, the FX2LP pushes the program counter to

its stack, and then jumps to the address 0x0043 where it expects

to find a “jump” instruction to the USB interrupt service routine.

When first plugged into USB, the FX2LP enumerates

automatically and downloads firmware and USB descriptor

tables over the USB cable. Next, the FX2LP enumerates again,

this time as a device defined by the downloaded information.

This patented two step process called ReNumeration™ happens

instantly when the device is plugged in, without a hint that the

initial download step has occurred.

Note

2

5. The I C bus SCL and SDA pins must be pulled up, even if an EEPROM is not connected. Otherwise this detection method does not work properly.

Document Number: 38-08032 Rev. AD

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The FX2LP jump instruction is encoded as follows:

Table 3. INT2 USB Interrupts

USB INTERRUPT TABLE FOR INT2

Source

Priority

1

INT2VEC Value

Notes

00

04

08

0C

10

14

18

1C

20

24

28

2C

30

34

38

3C

40

44

48

4C

50

54

58

5C

60

64

68

6C

70

74

78

7C

SUDAV

Setup data available

2

SOF

Start of frame (or microframe)

Setup token received

3

SUTOK

4

SUSPEND

USB RESET

HISPEED

EP0ACK

USB suspend request

5

Bus reset

6

Entered high speed operation

FX2LP ACK’d the CONTROL Handshake

reserved

7

8

9

EP0-IN

EP0-OUT

EP1-IN

EP1-OUT

EP2

EP0-IN ready to be loaded with data

EP0-OUT has USB data

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

EP1-IN ready to be loaded with data

EP1-OUT has USB data

IN: buffer available. OUT: buffer has data

IN-Bulk-NAK (any IN endpoint)

reserved

EP4

EP6

EP8

IBN

EP0PING

EP1PING

EP2PING

EP4PING

EP6PING

EP8PING

ERRLIMIT

–

EP0 OUT was pinged and it NAK’d

EP1 OUT was pinged and it NAK’d

EP2 OUT was pinged and it NAK’d

EP4 OUT was pinged and it NAK’d

EP6 OUT was pinged and it NAK’d

EP8 OUT was pinged and it NAK’d

Bus errors exceeded the programmed limit

–

Reserved

–

Reserved

EP2ISOERR

EP4ISOERR

EP6ISOERR

EP8ISOERR

ISO EP2 OUT PID sequence error

ISO EP4 OUT PID sequence error

ISO EP6 OUT PID sequence error

ISO EP8 OUT PID sequence error

If Autovectoring is enabled (AV2EN = 1 in the INTSET-UP register), the FX2LP substitutes its INT2VEC byte. Therefore, if the high

byte (“page”) of a jump table address is preloaded at the location 0x0044, the automatically inserted INT2VEC byte at 0x0045 directs

the jump to the correct address out of the 27 addresses within the page.

Document Number: 38-08032 Rev. AD

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FIFO/GPIF Interrupt (INT4)

Just as the USB Interrupt is shared among 27 individual USB interrupt sources, the FIFO/GPIF interrupt is shared among 14 individual

FIFO/GPIF sources. The FIFO/GPIF Interrupt, similar to the USB Interrupt, can employ autovectoring.

Table 4 shows the priority and INT4VEC values for the 14 FIFO/GPIF interrupt sources.

Table 4. Individual FIFO/GPIF Interrupt Sources

Priority

INT4VEC Value

Source

EP2PF

EP4PF

EP6PF

EP8PF

EP2EF

EP4EF

EP6EF

EP8EF

EP2FF

EP4FF

EP6FF

EP8FF

GPIFDONE

GPIFWF

Notes

1

2

80

84

88

8C

90

94

98

9C

A0

A4

A8

AC

B0

B4

Endpoint 2 programmable flag

Endpoint 4 programmable flag

Endpoint 6 programmable flag

Endpoint 8 programmable flag

Endpoint 2 empty flag ^[6]

Endpoint 4 empty flag

Endpoint 6 empty flag

Endpoint 8 empty flag

Endpoint 2 full flag

3

4

5

6

7

8

9

10

11

12

13

14

Endpoint 4 full flag

Endpoint 6 full flag

Endpoint 8 full flag

GPIF operation complete

GPIF waveform

If Autovectoring is enabled (AV4EN = 1 in the INTSET-UP

register), the FX 2LP substitutes its INT4VEC byte. Therefore, if

the high byte (“page”) of a jump-table address is preloaded at

location 0x0054, the automatically inserted INT4VEC byte at

0x0055 directs the jump to the correct address out of the 14

addresses within the page. When the ISR occurs, the FX2LP

pushes the program counter to its stack then jumps to address

0x0053, where it expects to find a “jump” instruction to the

interrupt service routine (ISR).

Note

6. Errata: In Slave FIFO Asynchronous Word Wide mode, if a single word data is transferred from the USB host to EP2, configured as OUT Endpoint (EP) in the first

transaction, then the Empty flag behaves incorrectly. This does not happen if the data size is more than one word in the first transaction. For more information, see

the Errata on page 68.

Document Number: 38-08032 Rev. AD

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Figure 2 shows a power-on reset condition and a reset applied

during operation. A power-on reset is defined as the time reset

that is asserted while power is being applied to the circuit. A

powered reset is when the FX2LP is powered on and operating

and the RESET# pin is asserted.

Reset and Wakeup

Reset Pin

The input pin, RESET#, resets the FX2LP when asserted. This

pin has hysteresis and is active LOW. When a crystal is used with

the CY7C680xxA, the reset period must enable stabilization of

the crystal and the PLL. This reset period must be approximately

5 ms after VCC reaches 3.0 V. If the crystal input pin is driven by

a clock signal, the internal PLL stabilizes in 200 s after VCC has

Cypress provides an application note which describes and

recommends power-on reset implementation. For more

information about reset implementation for the FX2 family of

products, visit http://www.cypress.com.

reached 3.0 V^[7]

.

Figure 2. Reset Timing Plots

RESET#

V_IL

3.3V

3.0V

3.3V

VCC

0V

T_RESET

Power on Reset

Powered Reset

Wakeup Pins

Table 5. Reset Timing Values

The 8051 puts itself and the rest of the chip into a power-down

mode by setting PCON.0 = 1. This stops the oscillator and PLL.

When WAKEUP is asserted by external logic, the oscillator

restarts after the PLL stabilizes, and the 8051 receives a wakeup

interrupt. This applies irrespective of whether FX2LP is

connected to the USB.

Condition

T_RESET

Power-on reset with crystal

5 ms

Power-on reset with external

clock

200 s + clock stability time

200 s

The FX2LP exits the power-down (USB suspend) state by using

one of the following methods:

Powered reset

■ USB bus activity (if D+/D– lines are left floating, noise on these

lines may indicate activity to the FX2LP and initiate a wakeup)

■ External logic asserts the WAKEUP pin

■ External logic asserts the PA3/WU2 pin

The second wakeup pin, WU2, can also be configured as a

general-purpose I/O pin. This enables a simple external R-C

network to be used as a periodic wakeup source. WAKEUP is by

default active LOW.

Document Number: 38-08032 Rev. AD

Page 9 of 74

CY7C68013A/CY7C68014A

CY7C68015A/CY7C68016A

suppressed for memory spaces that exist inside the chip. This

enables the user to connect a 64 KB memory without requiring

address decodes to keep clear of internal memory spaces.

Program/Data RAM

Size

The FX2LP has 16 KB of internal program/data RAM, where

PSEN#/RD# signals are internally ORed to enable the 8051 to

access it as both program and data memory. No USB control

registers appears in this space.

Only the internal 16 KB and scratch pad 0.5 KB RAM spaces

have the following access:

■ USB download

■ USB upload

Two memory maps are shown in the following diagrams:

Figure 3 shows the Internal Code Memory, EA = 0.

■ Setup data pointer

■ I²C interface boot load

Figure 4 on page 11 shows the External Code Memory, EA = 1.

Internal Code Memory, EA = 0

External Code Memory, EA = 1

This mode implements the internal 16 KB block of RAM (starting

at 0) as combined code and data memory. When external RAM

or ROM is added, the external read and write strobes are

The bottom 16 KB of program memory is external and therefore

the bottom 16 KB of internal RAM is accessible only as a data

memory.

Figure 3. Internal Code Memory, EA = 0

Inside FX2LP

Outside FX2LP

FFFF

7.5 KB

USB regs and

4K FIFO buffers

(OK to populate

data memory

here—RD#/WR#

strobes are not

active)

(RD#,WR#)

E200

E1FF

0.5 KB RAM

Data (RD#,WR#)*

E000

48 KB

External

Code

Memory

(PSEN#)

40 KB

External

Data

Memory

(RD#,WR#)

3FFF

(Ok to populate

data memory

here—RD#/WR#

strobes are not

active)

(OK to populate

program

memory here—

PSEN# strobe

is not active)

16 KB RAM

Code and Data

(PSEN#,RD#,WR#)*

0000

Data

Code

*SUDPTR, USB upload/download, I²C interface boot access

Note

7. If the external clock is powered at the same time as the CY7C680xxA and has a stabilization wait period, it must be added to the 200 s.

Document Number: 38-08032 Rev. AD

Page 10 of 74

CY7C68013A/CY7C68014A

CY7C68015A/CY7C68016A

Figure 4. External Code Memory, EA = 1

Inside FX2LP Outside FX2LP

FFFF

7.5 KB

(OK to populate

USB regs and

4K FIFO buffers

(RD#,WR#)

data memory

here—RD#/WR#

strobes are not

active)

E200

E1FF

0.5 KB RAM

Data (RD#,WR#)*

E000

40 KB

External

Data

Memory

(RD#,WR#)

64 KB

External

Code

Memory

(PSEN#)

3FFF

(Ok to populate

data memory

here—RD#/WR#

strobes are not

active)

16 KB

RAM

Data

(RD#,WR#)*

0000

Data

Code

*SUDPTR, USB upload/download, I²C interface boot access

Document Number: 38-08032 Rev. AD

Page 11 of 74

CY7C68013A/CY7C68014A

CY7C68015A/CY7C68016A

Register Addresses

FFFF

4 KB EP2-EP8

buffers

(8 x 512)

F000

EFFF

2 KB RESERVED

E800

E7FF

E7C0

64 BEP1IN

E7BF

E780

E77F

E740

E73F

E700

E6FF

64 Bytes EP1OUT

64 Bytes EP0 IN/OUT

64 Bytes RESERVED

8051 Addressable Registers

(512)

E500

E4FF

E480

E47F

Reserved (128)

128 Bytes GPIF Waveforms

Reserved (512)

E400

E3FF

E200

E1FF

512 Bytes

8051 xdata RAM

E000

Document Number: 38-08032 Rev. AD

Page 12 of 74

CY7C68013A/CY7C68014A

CY7C68015A/CY7C68016A

Setup Data Buffer

Endpoint RAM

Aseparate 8-byte buffer at 0xE6B8-0xE6BF holds the setup data

from a CONTROL transfer.

Size

■ 3 × 64 bytes

(Endpoints 0 and 1)

Endpoint Configurations (Hi-Speed Mode)

■ 8 × 512 bytes (Endpoints 2, 4, 6, 8)

Endpoints 0 and 1 are the same for every configuration.

Endpoint 0 is the only CONTROL endpoint, and endpoint 1 can

be either BULK or INTERRUPT.

Organization

■ EP0

The endpoint buffers can be configured in any 1 of the 12

configurations shown in the vertical columns. When operating in

the Full-Speed BULK mode, only the first 64 bytes of each buffer

are used. For example, in Hi-Speed mode, the max packet size

is 512 bytes, but in Full-Speed mode, it is 64 bytes. Even though

a buffer is configured to a 512-byte buffer, in Full-Speed mode,

only the first 64 bytes are used. The unused endpoint buffer

space is not available for other operations. An example endpoint

configuration is the EP2–1024 double-buffered; EP6–512

quad-buffered (column 8).

■ Bidirectional endpoint zero, 64-byte buffer

■ EP1IN, EP1OUT

■ 64 byte buffers, bulk or interrupt

■ EP2, 4, 6, 8

■ Eight 512-byte buffers, bulk, interrupt, or isochronous. EP4 and

EP8 can be double buffered; EP2 and 6 can be either double,

triple, or quad buffered. For Hi-Speed endpoint configuration

options, see Figure 5.

Figure 5. Endpoint Configuration

64

EP0 IN&OUT

EP1 IN

EP1 OUT

EP2

512

EP2

EP2 EP2

EP2

512

EP2

512

EP2

512

1024

512

1024

EP4

512

EP4 EP4

512

EP6

1024

512

EP6

512

EP6

512

EP6

EP6 EP6

EP6

EP6 EP6

512

1024

1024 1024

512

1024

512

EP8

512

EP8

512

EP8

512

EP8

512

EP8

512

1024

512

1024

512

10

11

12

9

4

5

8

1

2

3

6

7

Document Number: 38-08032 Rev. AD

Page 13 of 74

CY7C68013A/CY7C68014A

CY7C68015A/CY7C68016A

Default Full-Speed Alternate Settings

Table 6. Default Full Speed Alternate Settings^{[8, 9]}

Alternate Setting

0

64

0

1

2

3

ep0

64

ep1out

ep1in

ep2

64 bulk

64 int

0

64 int

0

64 bulk out (2×)

64 bulk in (2×)

64 int out (2×)

64 bulk out (2×)

64 int in (2×)

64 iso out (2×)

64 bulk out (2×)

64 iso in (2×)

64 bulk in (2×)

ep4

0

ep6

0

ep8

0

64 bulk in (2×)

Default High Speed Alternate Settings

Table 7. Default Hi-Speed Alternate Settings^{[8, 9]}

Alternate Setting

0

1

2

3

ep0

64

0

64

ep1out

ep1in

ep2

512 bulk^[10]

64 int

0

64 int

0

512 bulk out (2×)

512 bulk in (2×)

512 int out (2×)

512 bulk out (2×)

512 int in (2×)

512 bulk in (2×)

512 iso out (2×)

512 bulk out (2×)

512 iso in (2×)

512 bulk in (2×)

ep4

0

ep6

0

ep8

0

Notes

8. “0” means “not implemented.”

9. “2×” means “double buffered.”

10. Even though these buffers are 64 bytes, they are reported as 512 for USB 2.0 compliance. The user must never transfer packets larger than 64 bytes to EP1.

Document Number: 38-08032 Rev. AD

Page 14 of 74

CY7C68013A/CY7C68014A

CY7C68015A/CY7C68016A

Alternatively, an externally supplied clock of 5 MHz–48 MHz

feeding the IFCLK pin can be used as the interface clock. IFCLK

can be configured to function as an output clock when the GPIF

and FIFOs are internally clocked. An output enable bit in the

IFCONFIG register turns this clock output off, if desired. Another

bit within the IFCONFIG register inverts the IFCLK signal

whether internally or externally sourced.

External FIFO Interface

Architecture

The FX2LP slave FIFO architecture has eight 512-byte blocks in

the endpoint RAM that directly serve as FIFO memories and are

controlled by FIFO control signals (such as IFCLK, SLCS#,

SLRD, SLWR, SLOE, PKTEND, and flags).

In operation, some of the eight RAM blocks fill or empty from the

SIE, while the others are connected to the I/O transfer logic. The

transfer logic takes two forms: the GPIF for internally generated

control signals and the slave FIFO interface for externally

controlled transfers.

GPIF

The GPIF is a flexible 8-bit or 16-bit parallel interface driven by

a user-programmable finite state machine. It enables the

CY7C68013A/15A to perform local bus mastering and can

implement a wide variety of protocols such as ATA interface,

printer parallel port, and Utopia.

Master/Slave Control Signals

The GPIF has six programmable control outputs (CTL), nine

address outputs (GPIFADRx), and six general-purpose ready

inputs (RDY). The data bus width can be 8 or 16 bits. Each GPIF

vector defines the state of the control outputs, and determines

what state a ready input (or multiple inputs) must be before

proceeding. The GPIF vector can be programmed to advance a

FIFO to the next data value, advance an address, etc. A

sequence of the GPIF vectors make up a single waveform that

is executed to perform the desired data move between the

FX2LP and the external device.

The FX2LP endpoint FIFOs are implemented as eight physically

^{distinct 256}16 RAM blocks. The 8051/SIE can switch any of the

RAM blocks between two domains, the USB (SIE) domain and

the 8051-I/O Unit domain. This switching is done virtually

instantaneously, giving essentially zero transfer time between

“USB FIFOs” and “Slave FIFOs.” Because they are physically

the same memory, no bytes are actually transferred between

buffers.

At any time, some RAM blocks are filling/emptying with the USB

data under SIE control, while other RAM blocks are available to

the 8051, the I/O control unit, or both. The RAM blocks operates

as single-port in the USB domain, and dual-port in the 8051-I/O

domain. The blocks can be configured as single-, double-, triple-,

or quad-buffered as previously shown.

Six Control OUT Signals

The 100-pin and 128-pin packages bring out all six Control

Output pins (CTL0-CTL5). The 8051 programs the GPIF unit to

define the CTL waveforms. The 56-pin package brings out three

of these signals, CTL0–CTL2. CTLx waveform edges can be

programmed to make transitions as fast as once per clock

(20.8 ns using a 48-MHz clock).

The I/O control unit implements either an internal master (M for

Master) or external master (S for Slave) interface.

In Master (M) mode, the GPIF internally controls FIFOADR[1..0]

to select a FIFO. The RDY pins (two in the 56-pin package, six

in the 100-pin and 128-pin packages) can be used as flag inputs

from an external FIFO or other logic if desired. The GPIF can be

run from either an internally derived clock or externally supplied

clock (IFCLK), at a rate that transfers data up to 96 MBytes/s

(48 Hz IFCLK with 16-bit interface).

Six Ready IN Signals

The 100-pin and 128-pin packages bring out all six Ready inputs

(RDY0–RDY5). The 8051 programs the GPIF unit to test the

RDY pins for GPIF branching. The 56-pin package brings out two

of these signals, RDY0–1.

In the Slave (S) mode, FX2LP accepts either an internally

derived clock or externally supplied clock (IFCLK, max frequency

48 MHz) and SLCS#, SLRD, SLWR, SLOE, PKTEND signals

from external logic. When using an external IFCLK, the external

clock must be present before switching to the external clock with

the IFCLKSRC bit. Each endpoint can individually be selected

for byte or word operation by an internal configuration bit and a

Slave FIFO Output Enable signal (SLOE) that enables data of

the selected width. External logic must ensure that the output

enable signal is inactive when writing data to a slave FIFO. The

slave interface can also operate asynchronously, where the

SLRD and SLWR signals act directly as strobes, rather than a

clock qualifier as in synchronous mode. The signals SLRD,

SLWR, SLOE, and PKTEND are gated by the signal SLCS#.

Nine GPIF Address OUT Signals

Nine GPIF address lines are available in the 100-pin and 128-pin

packages, GPIFADR[8..0]. The GPIF address lines enable

indexing through up to a 512-byte block of RAM. If more address

lines are needed, then I/O port pins are used.

Long Transfer Mode

In the master mode, the 8051 appropriately sets GPIF

transaction count registers (GPIFTCB3, GPIFTCB2, GPIFTCB1,

or GPIFTCB0) for unattended transfers of up to 2³²transactions.

The GPIF automatically throttles data flow to prevent under or

overflow until the full number of requested transactions

complete. The GPIF decrements the value in these registers to

represent the current status of the transaction.

GPIF and FIFO Clock Rates

An 8051 register bit selects one of two frequencies for the

internally supplied interface clock: 30 MHz and 48 MHz.

Document Number: 38-08032 Rev. AD

Page 15 of 74

CY7C68013A/CY7C68014A

CY7C68015A/CY7C68016A

under the control of a mode bit (AUTOPTRSET-UP.0). Using the

external FX2LP autopointer access (at 0xE67B–0xE67C)

enables the autopointer to access all internal and external RAM

to the part.

ECC Generation

The EZ-USB can calculate ECCs (Error Correcting Codes)^[11]on

data that passes across its GPIF or Slave FIFO interfaces. There

are two ECC configurations: Two ECCs, each calculated over

256 bytes (SmartMedia Standard); and one ECC calculated over

512 bytes.

Also, autopointers can point to any FX2LP register or endpoint

buffer space. When the autopointer access to external memory

is enabled, locations 0xE67B and 0xE67C in XDATA and code

space cannot be used.

The ECC can correct any one-bit error or detect any two-bit error.

ECC Implementation

2

I C Controller

The two ECC configurations are selected by the ECCM bit:

FX2LP has one I²C port that is driven by two internal controllers,

the one that automatically operates at boot time to load

VID/PID/DID and configuration information, and another that the

8051 uses when running to control external I²C devices. The I²C

port operates in master mode only.

ECCM = 0

Two 3-byte ECCs, each calculated over a 256-byte block of data.

This configuration conforms to the SmartMedia Standard.

Write any value to ECCRESET, then pass data across the GPIF

or Slave FIFO interface. The ECC for the first 256 bytes of data

is calculated and stored in ECC1. The ECC for the next 256 bytes

is stored in ECC2. After the second ECC is calculated, the values

in the ECCx registers do not change until ECCRESET is written

again, even if more data is subsequently passed across the

interface.

I²C Port Pins

The I²C pins SCL and SDA must have external 2.2-k pull-up

resistors even if no EEPROM is connected to the FX2LP.

External EEPROM device address pins must be configured

properly. See Table 8 for configuring the device address pins.

ECCM = 1

Table 8. Strap Boot EEPROM Address Lines to These Values

One 3-byte ECC calculated over a 512-byte block of data.

Bytes

16

Example EEPROM

24LC00^[13]

24LC01

A2

N/A

0

A1

N/A

0

A0

N/A

0

Write any value to ECCRESET then pass data across the GPIF

or Slave FIFO interface. The ECC for the first 512 bytes of data

is calculated and stored in ECC1; ECC2 is unused. After the

ECC is calculated, the values in ECC1 do not change even if

more data is subsequently passed across the interface, till

ECCRESET is written again.

128

256

4K

24LC02

0

24LC32

0

1

8K

24LC64

0

1

USB Uploads and Downloads

16K

24LC128

0

1

The core has the ability to directly edit the data contents of the

internal 16-KB RAM and of the internal 512-byte scratch pad

RAM via a vendor-specific command. This capability is normally

used when soft downloading the user code and is available only

to and from the internal RAM, only when the 8051 is held in reset.

The available RAM spaces are 16 KB from 0x0000–0x3FFF

(code/data) and 512 bytes from 0xE000–0xE1FF (scratch pad

I²C Interface Boot Load Access

At power-on reset, the I²C interface boot loader loads the

VID/PID/DID configuration bytes and up to 16 KB of

program/data. The available RAM spaces are 16 KB from

0x0000–0x3FFF and 512 bytes from 0xE000–0xE1FF. The 8051

is in reset. I²C interface boot loads only occur after power-on

reset.

data RAM)^[12]

.

Autopointer Access

I²C Interface General-Purpose Access

FX2LP provides two identical autopointers. They are similar to

the internal 8051 data pointers but with an additional feature:

they can optionally increment after every memory access. This

capability is available to and from both internal and external

RAM. Autopointers are available in external FX2LP registers

The 8051 can control peripherals connected to the I²C bus using

the I2CTL and I2DAT registers. FX2LP provides I²C master

control only; it is never an I²C slave.

Notes

11. To use the ECC logic, the GPIF or Slave FIFO interface must be configured for byte-wide operation.

12. After the data is downloaded from the host, a “loader” can execute from internal RAM to transfer downloaded data to external memory.

13. This EEPROM does not have address pins.

Document Number: 38-08032 Rev. AD

Page 16 of 74

CY7C68013A/CY7C68014A

CY7C68015A/CY7C68016A

Compatible with Previous Generation EZ-USB FX2

CY7C68013A/14A and CY7C68015A/16A Differences

The EZ-USB FX2LP is form-, fit-, and with minor exceptions,

functionally-compatible with its predecessor, the EZ-USB FX2.

This makes for an easy transition for designers wanting to

upgrade their systems from the FX2 to the FX2LP. The pinout

and package selection are identical and a vast majority of

firmware previously developed for the FX2 functions in the

FX2LP.

CY7C68013A is identical to CY7C68014A in form, fit, and

functionality. CY7C68015A is identical to CY7C68016A in form,

fit, and functionality. CY7C68014A and CY7C68016A have a

lower suspend current than CY7C68013A and CY7C68015A

respectively and are ideal for power-sensitive battery

applications.

CY7C68015A and CY7C68016A are available in 56-pin QFN

package only. Two additional GPIO signals are available on the

CY7C68015A and CY7C68016A to provide more flexibility when

neither IFCLK or CLKOUT are needed in the 56-pin package.

For designers migrating from the FX2 to the FX2LP, a change in

the bill of material and review of the memory allocation (due to

increased internal memory) is required. For more information

about migrating from EZ-USB FX2 to EZ-USB FX2LP, see the

application note titled Migrating from EZ-USB FX2 to EZ-USB

FX2LP available in the Cypress web site.

USB developers wanting to convert their FX2 56-pin application

to a bus-powered system directly benefit from these additional

signals. The two GPIOs give developers the signals they need

for the power-control circuitry of their bus-powered application

without pushing them to a high-pincount version of FX2LP.

Table 9. Part Number Conversion Table

EZ-USB FX2

Part Number

EZ-USB FX2LP

Part Number

Package

Description

The CY7C68015A is only available in the 56-pin QFN package

Table 10. CY7C68013A/14A and CY7C68015A/16A

Pin Differences

CY7C68013A-56PVXC or 56-pin

CY7C68013-56PVC

CY7C68014A-56PVXC

SSOP

CY7C68013A/CY7C68014A CY7C68015A/CY7C68016A

56-pin

CY7C68013A-56PVXCTor SSOP –

CY7C68014A-56PVXCT Tape and

Reel

IFCLK

PE0

PE1

CY7C68013-56PVCT

CLKOUT

CY7C68013A-56LFXC or

56-pin QFN

CY7C68013-56LFC

CY7C68013-100AC

CY7C68013-128AC

CY7C68014A-56LFXC

CY7C68013A-100AXC or 100-pin

CY7C68014A-100AXC

CY7C68013A-128AXC or 128-pin

CY7C68014A-128AXC TQFP

TQFP

Document Number: 38-08032 Rev. AD

Page 17 of 74

CY7C68013A/CY7C68014A

CY7C68015A/CY7C68016A

The 100-pin package adds functionality to the 56-pin package by

adding these pins:

Pin Assignments

Figure 6 on page 19 identifies all signals for the five package

types. The following pages illustrate the individual pin diagrams,

plus a combination diagram showing which of the full set of

signals are available in the 128-pin, 100-pin, and 56-pin

packages.

■ PORTC or alternate GPIFADR[7:0] address signals

■ PORTE or alternate GPIFADR[8] address signal and seven

additional 8051 signals

■ Three GPIF Control signals

■ Four GPIF Ready signals

The signals on the left edge of the 56-pin package in Figure 6

on page 19 are common to all versions in the FX2LP family with

the noted differences between the CY7C68013A/14A and the

CY7C68015A/16A.

■ Nine 8051 signals (two USARTs, three timer inputs, INT4, and

INT5#)

Three modes are available in all package versions: Port, GPIF

master, and Slave FIFO. These modes define the signals on the

right edge of the diagram. The 8051 selects the interface mode

using the IFCONFIG[1:0] register bits. Port mode is the power on

default configuration.

■ BKPT, RD#, WR#.

The 128-pin package adds the 8051 address and data buses

plus control signals. Note that two of the required signals, RD#

and WR#, are present in the 100-pin version.

In the 100-pin and 128-pin versions, an 8051 control bit can be

set to pulse the RD# and WR# pins when the 8051 reads

from/writes to PORTC. This feature is enabled by setting the

PORTCSTB bit in the CPUCS register.

PORTC Strobe Feature Timings on page 46 displays the timing

diagram of the read and write strobing function on accessing

PORTC.

Document Number: 38-08032 Rev. AD

Page 18 of 74

CY7C68013A/CY7C68014A

CY7C68015A/CY7C68016A

Figure 6. Signal

GPIF Master

Port

Slave FIFO

PD7

PD6

PD5

PD4

PD3

PD2

PD1

PD0

PB7

PB6

PB5

PB4

PB3

PB2

PB1

PB0

FD[15]

FD[14]

FD[13]

FD[12]

FD[11]

FD[10]

FD[9]

FD[8]

FD[7]

FD[6]

FD[5]

FD[4]

FD[3]

FD[2]

FD[1]

FD[0]

FD[15]

FD[14]

FD[13]

FD[12]

FD[11]

FD[10]

FD[9]

FD[8]

FD[7]

FD[6]

FD[5]

FD[4]

FD[3]

FD[2]

FD[1]

FD[0]

XTALIN

XTALOUT

RESET#

WAKEUP#

SCL

SDA

56

SLRD

SLWR

RDY0

RDY1

**PE0 replaces IFCLK

& PE1 replaces CLKOUT

on CY7C68015A/16A

**PE0

**PE1

FLAGA

FLAGB

FLAGC

CTL0

CTL1

CTL2

INT0#/PA0

INT1#/PA1

PA2

WU2/PA3

PA4

INT0#/ PA0

INT1#/ PA1

SLOE

INT0#/PA0

INT1#/PA1

PA2

WU2/PA3

PA4

PA5

PA6

IFCLK

CLKOUT

WU2/PA3

FIFOADR0

FIFOADR1

PKTEND

DPLUS

DMINUS

PA5

PA6

PA7

PA7/FLAGD/SLCS#

PA7

CTL3

CTL4

CTL5

RDY2

RDY3

RDY4

RDY5

100

BKPT

PORTC7/GPIFADR7

PORTC6/GPIFADR6

PORTC5/GPIFADR5

PORTC4/GPIFADR4

PORTC3/GPIFADR3

PORTC2/GPIFADR2

PORTC1/GPIFADR1

PORTC0/GPIFADR0

RxD0

TxD0

RxD1

TxD1

INT4

INT5#

T2

PE7/GPIFADR8

PE6/T2EX

PE5/INT6

PE4/RxD1OUT

PE3/RxD0OUT

PE2/T2OUT

PE1/T1OUT

PE0/T0OUT

T1

T0

RD#

WR#

CS#

OE#

PSEN#

D7

D6

D5

D4

D3

D2

D1

D0

A15

A14

A13

A12

A11

A10

A9

128

A8

A7

A6

A5

A4

A3

EA

A2

A1

A0

Document Number: 38-08032 Rev. AD

Page 19 of 74

CY7C68013A/CY7C68014A

CY7C68015A/CY7C68016A

Figure 7. CY7C68013A/CY7C68014A 128-Pin TQFP Pin Assignment

1

102

101

100

99

98

97

96

95

94

93

92

91

90

89

88

87

86

85

84

83

82

81

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

CLKOUT

VCC

GND

PD0/FD8

*WAKEUP

VCC

2

3

4

RDY0/*SLRD

RDY1/*SLWR

RDY2

RDY3

RDY4

RDY5

AVCC

XTALOUT

XTALIN

AGND

NC

RESET#

5

CTL5

6

A3

A2

A1

A0

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

GND

PA7/*FLAGD/SLCS#

PA6/*PKTEND

PA5/FIFOADR1

PA4/FIFOADR0

D7

NC

D6

D5

AVCC

DPLUS

DMINUS

AGND

A11

A12

A13

A14

A15

VCC

GND

INT4

T0

T1

T2

CY7C68013A/CY7C68014A

128-pin TQFP

PA3/*WU2

PA2/*SLOE

PA1/INT1#

PA0/INT0#

VCC

GND

PC7/GPIFADR7

PC6/GPIFADR6

PC5/GPIFADR5

PC4/GPIFADR4

PC3/GPIFADR3

PC2/GPIFADR2

PC1/GPIFADR1

PC0/GPIFADR0

CTL2/*FLAGC

CTL1/*FLAGB

CTL0/*FLAGA

VCC

*IFCLK

RESERVED

BKPT

EA

SCL

SDA

CTL4

CTL3

GND

OE#

* denotes programmable polarity

Document Number: 38-08032 Rev. AD

Page 20 of 74

CY7C68013A/CY7C68014A

CY7C68015A/CY7C68016A

Figure 8. CY7C68013A/CY7C68014A 100-Pin TQFP Pin Assignment

1

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

VCC

GND

PD0/FD8

*WAKEUP

VCC

RESET#

2

3

RDY0/*SLRD

RDY1/*SLWR

RDY2

RDY3

RDY4

RDY5

AVCC

XTALOUT

XTALIN

AGND

NC

4

5

CTL5

GND

6

7

PA7/*FLAGD/SLCS#

PA6/*PKTEND

PA5/FIFOADR1

PA4/FIFOADR0

PA3/*WU2

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

PA2/*SLOE

PA1/INT1#

PA0/INT0#

NC

CY7C68013A/CY7C68014A

100-pin TQFP

VCC

GND

AVCC

DPLUS

DMINUS

AGND

VCC

GND

INT4

T0

T1

PC7/GPIFADR7

PC6/GPIFADR6

PC5/GPIFADR5

PC4/GPIFADR4

PC3/GPIFADR3

PC2/GPIFADR2

PC1/GPIFADR1

PC0/GPIFADR0

CTL2/*FLAGC

CTL1/*FLAGB

CTL0/*FLAGA

VCC

T2

*IFCLK

RESERVED

BKPT

SCL

CTL4

CTL3

SDA

* denotes programmable polarity

Document Number: 38-08032 Rev. AD

Page 21 of 74

CY7C68013A/CY7C68014A

CY7C68015A/CY7C68016A

Figure 9. CY7C68013A/CY7C68014A 56-Pin SSOP Pin Assignment

CY7C68013A/CY7C68014A

56-pin SSOP

1

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

PD5/FD13

PD4/FD12

PD3/FD11

PD2/FD10

PD1/FD9

PD0/FD8

*WAKEUP

VCC

2

PD6/FD14

PD7/FD15

GND

CLKOUT

VCC

3

4

5

6

7

GND

8

RDY0/*SLRD

RDY1/*SLWR

AVCC

XTALOUT

XTALIN

AGND

RESET#

9

GND

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

PA7/*FLAGD/SLCS#

PA6/PKTEND

PA5/FIFOADR1

PA4/FIFOADR0

PA3/*WU2

PA2/*SLOE

PA1/INT1#

PA0/INT0#

VCC

AVCC

DPLUS

DMINUS

AGND

VCC

GND

*IFCLK

RESERVED

SCL

SDA

VCC

CTL2/*FLAGC

CTL1/*FLAGB

CTL0/*FLAGA

GND

VCC

GND

PB7/FD7

PB6/FD6

PB5/FD5

PB4/FD4

PB0/FD0

PB1/FD1

PB2/FD2

PB3/FD3

* denotes programmable polarity

Document Number: 38-08032 Rev. AD

Page 22 of 74

CY7C68013A/CY7C68014A

CY7C68015A/CY7C68016A

Figure 10. CY7C68013A/14A/15A/16A 56-Pin QFN Pin Assignment

RESET#

RDY0/*SLRD

RDY1/*SLWR

AVCC

1

2

42

41

40

39

38

37

36

35

34

33

32

31

30

GND

PA7/*FLAGD/SLCS#

PA6/*PKTEND

PA5/FIFOADR1

PA4/FIFOADR0

PA3/*WU2

3

XTALOUT

XTALIN

4

CY7C68013A/CY7C68014A

5

&

AGND

6

CY7C68015A/CY7C68016A

AVCC

7

56-pin QFN

PA2/*SLOE

PA1/INT1#

DPLUS

8

DMINUS

AGND

9

PA0/INT0#

10

11

12

13

14

VCC

CTL2/*FLAGC

CTL1/*FLAGB

GND

*IFCLK/**PE0

RESERVED

29 CTL0/*FLAGA

* denotes programmable polarity

** denotes CY7C68015A/CY7C68016A pinout

Document Number: 38-08032 Rev. AD

Page 23 of 74

CY7C68013A/CY7C68014A

CY7C68015A/CY7C68016A

Figure 11. CY7C68013A 56-pin VFBGA Pin Assignment – Top View

1

2

3

4

5

6

7

8

1A

1B

1C

2A

2B

2C

3A

3B

3C

4A

4B

4C

5A

5B

5C

6A

6B

6C

7A

7B

7C

8A

8B

8C

A

B

C

D

1D

2D

7D

8D

1E

1F

1G

1H

2E

2F

2G

2H

7E

7F

7G

7H

8E

8F

8G

8H

E

3F

4F

5F

6F

F

G

H

3G

3H

4G

4H

5G

5H

6G

6H

Document Number: 38-08032 Rev. AD

Page 24 of 74

CY7C68013A/CY7C68014A

CY7C68015A/CY7C68016A

CY7C68013A/15A Pin Descriptions

Table 11. FX2LP Pin Descriptions^[14]

128 100

56

Name

Type Default Reset^[15]

Description

TQFP TQFP SSOP QFN VFBGA

Analog VCC. Connect this pin to the 3.3 V power

source. This signal provides power to the analog

section of the chip.

10

17

9

10

14

3

7

2D

1D

AVCC

Power

N/A

Analog VCC. Connect this pin to the 3.3 V power

source. This signal provides power to the analog

section of the chip.

16

AVCC

Analog Ground. Connect to ground with as short

a path as possible.

13

20

12

19

13

17

6

2F

1F

AGND

Ground N/A

N/A

Analog Ground. Connect to ground with as short

a path as possible.

10

19

18

17

16

15

9

8

1E

2E

DMINUS

DPLUS

A0

I/O/Z

Z

L

Z

N/A

L

USB D– Signal. Connect to the USB D– signal.

USB D+ Signal. Connect to the USB D+ signal.

94

–

Output

I/O/Z

95

A1

L

96

A2

L

97

A3

L

117

118

119

120

126

127

128

21

A4

L

A5

L

A6

L

8051 Address Bus. This bus is driven at all times.

When the 8051 is addressing internal RAM it

reflects the internal address.

A7

L

A8

L

A9

L

A10

A11

A12

A13

A14

A15

D0

L

22

L

23

L

24

L

25

L

59

Z

60

D1

I/O/Z

8051 Data Bus. This bidirectional bus is

high impedance when inactive, input for bus reads,

and output for bus writes. The data bus is used for

external 8051 program and data memory. The data

bus is active only for external bus accesses, and is

driven LOW in suspend.

61

D2

I/O/Z

62

D3

I/O/Z

63

D4

I/O/Z

86

D5

I/O/Z

87

D6

I/O/Z

88

D7

I/O/Z

Program Store Enable. This active LOW signal

indicates an 8051 code fetch from external

memory. It is active for program memory fetches

from 0x4000–0xFFFF when the EA pin is LOW, or

from 0x0000–0xFFFF when the EA pin is HIGH.

39

–

PSEN#

Output

H

Notes

14. Unused inputs must not be left floating. Tie either HIGH or LOW as appropriate. Outputs should only be pulled up or down to ensure signals at power up and in

standby. Note also that no pins should be driven while the device is powered down.

15. The Reset column indicates the state of signals during reset (RESET# asserted) or during Power on Reset (POR).

Document Number: 38-08032 Rev. AD

Page 25 of 74

CY7C68013A/CY7C68014A

CY7C68015A/CY7C68016A

Table 11. FX2LP Pin Descriptions^[14](continued)

128 100 56 56 56

Name

Type Default Reset^[15]

Description

TQFP TQFP SSOP QFN VFBGA

Breakpoint. This pin goes active (HIGH) when the

8051 address bus matches the BPADDRH/L

registers and breakpoints are enabled in the

BREAKPTregister (BPEN = 1). If the BPPULSE bit

in the BREAKPT register is HIGH, this signal

pulses HIGH for eight 12-/24-/48-MHz clocks. If the

BPPULSE bit is LOW, the signal remains HIGH

until the 8051 clears the BREAK bit (by writing 1 to

it) in the BREAKPT register.

34

28

–

BKPT

Output

L

Active LOW Reset. Resets the entire chip. See

section ”Reset and Wakeup” on page 9 for more

details.

99

35

77

–

49

–

42

–

8B

–

RESET#

EA

Input

N/A

External Access. This pin determines where the

8051fetchescodebetweenaddresses0x0000and

0x3FFF. If EA = 0 the 8051 fetches this code from

its internal RAM. IF EA = 1 the 8051 fetches this

code from external memory.

Crystal Input. Connect this signal to a 24-MHz

parallel-resonant, fundamental mode crystal and

load capacitor to GND.

It is also correct to drive XTALIN with an external

24-MHz square wave derived from another clock

source. When driving from an external source, the

driving signal should be a 3.3-V square wave.

12

11

10

12

11

5

4

1C

2C

XTALIN

Input

N/A

Crystal Output. Connect this signal to a 24-MHz

parallel-resonant, fundamental mode crystal and

load capacitor to GND.

XTALOUT

Output

If an external clock is used to drive XTALIN, leave

this pin open.

CLKOUT on

CY7C68013A

and

CY7C68014A

------------------

PE1 on

Clock

Driven

O/Z 12 MHz

CLKOUT: 12-, 24- or 48-MHz clock, phase-locked

to the 24-MHz input clock. The 8051 defaults to

12-MHz operation. The 8051 may three-state this

output by setting CPUCS.1 = 1.

------------------------------------------------------------------

------PE1 is a bidirectional I/O port pin.

1

100

5

54

2B

----------

Z

---------- ----------

CY7C68015A

and

-

I

I/O/Z

CY7C68016A

Port A

Multiplexed pin whose function is selected by

PORTACFG.0

PA0 is a bidirectional I/O port pin.

INT0# is the active-LOW 8051 INT0 interrupt input

signal, which is either edge-triggered (IT0 = 1) or

level-triggered (IT0 = 0).

Z

PA0 or

INT0#

I

82

67

68

40

41

33

34

8G

6G

I/O/Z

(PA0)

Multiplexed pin whose function is selected by:

PORTACFG.1

PA1 is a bidirectional I/O port pin.

PA1 or

INT1#

I

Z

83

(PA1)

(PA1) INT1# is the active-LOW 8051 INT1 interrupt input

signal, which is either edge-triggered (IT1 = 1) or

level-triggered (IT1 = 0).

Document Number: 38-08032 Rev. AD

Page 26 of 74

CY7C68013A/CY7C68014A

CY7C68015A/CY7C68016A

Table 11. FX2LP Pin Descriptions^[14](continued)

128 100 56 56 56

Name

Type Default Reset^[15]

Description

TQFP TQFP SSOP QFN VFBGA

Multiplexed pin whose function is selected by two

bits:

IFCONFIG[1:0].

Z

PA2 or

SLOE

I

84

69

42

35

8F

I/O/Z

(PA2) PA2 is a bidirectional I/O port pin.

SLOE is an input-only output enable with program-

mable polarity (FIFOPINPOLAR.4) for the slave

FIFOs connected to FD[7..0] or FD[15..0].

(PA2)

Multiplexed pin whose function is selected by:

WAKEUP.7 and OEA.3

PA3 is a bidirectional I/O port pin.

WU2 is an alternate source for USB Wakeup,

enabled by WU2EN bit (WAKEUP.1) and polarity

PA3 or

WU2

I

Z

85

70

43

36

7F

I/O/Z

(PA3)

(PA3) set by WU2POL (WAKEUP.4). If the 8051 is in

suspend and WU2EN = 1, a transition on this pin

starts up the oscillator and interrupts the 8051 to

enable it to exit the suspend mode. Asserting this

pin inhibits the chip from suspending if WU2EN = 1.

Multiplexed pin whose function is selected by:

IFCONFIG[1..0].

PA4 or

FIFOADR0

I

Z

89

90

71

72

44

45

37

38

6F

8C

I/O/Z

PA4 is a bidirectional I/O port pin.

(PA4)

FIFOADR0 is an input-only address select for the

slave FIFOs connected to FD[7..0] or FD[15..0].

Multiplexed pin whose function is selected by:

IFCONFIG[1..0].

PA5 or

FIFOADR1

I

Z

PA5 is a bidirectional I/O port pin.

(PA5)

FIFOADR1 is an input-only address select for the

slave FIFOs connected to FD[7..0] or FD[15..0].

Multiplexed pin whose function is selected by the

IFCONFIG[1:0] bits.

PA6 is a bidirectional I/O port pin.

PA6 or

PKTEND

I

Z

91

92

73

74

46

47

39

40

7C

6C

I/O/Z

(PA6)

(PA6) PKTEND is an input used to commit the FIFO

packet data to the endpoint and whose polarity is

programmable via FIFOPINPOLAR.5.

Multiplexed pin whose function is selected by the

IFCONFIG[1:0] and PORTACFG.7 bits.

PA7 is a bidirectional I/O port pin.

PA7 or

FLAGD or

SLCS#

I

Z

(PA7)

(PA7) FLAGD is a programmable slave-FIFO output

status flag signal.

SLCS# gates all other slave FIFO enable/strobes

Port B

Multiplexed pin whose function is selected by the

Z

PB0 or

FD[0]

I

following bits: IFCONFIG[1..0].

(PB0)

44

34

35

36

25

26

27

18

19

20

3H

4F

4H

I/O/Z

(PB0)

PB0 is a bidirectional I/O port pin.

FD[0] is the bidirectional FIFO/GPIF data bus.

Multiplexed pin whose function is selected by the

following bits: IFCONFIG[1..0].

(PB1) PB1 is a bidirectional I/O port pin.

PB1 or

FD[1]

I

Z

45

46

(PB1)

FD[1] is the bidirectional FIFO/GPIF data bus.

Multiplexed pin whose function is selected by the

following bits: IFCONFIG[1..0].

(PB2) PB2 is a bidirectional I/O port pin.

PB2 or

FD[2]

I

Z

(PB2)

FD[2] is the bidirectional FIFO/GPIF data bus.

Document Number: 38-08032 Rev. AD

Page 27 of 74

CY7C68013A/CY7C68014A

CY7C68015A/CY7C68016A

Table 11. FX2LP Pin Descriptions^[14](continued)

128 100 56 56 56

Name

Type Default Reset^[15]

Description

TQFP TQFP SSOP QFN VFBGA

Multiplexed pin whose function is selected by the

following bits: IFCONFIG[1..0].

(PB3) PB3 is a bidirectional I/O port pin.

PB3 or

FD[3]

I

Z

47

54

55

56

57

37

44

45

46

47

28

29

30

31

32

21

22

23

24

25

4G

5H

5G

5F

6H

I/O/Z

(PB3)

FD[3] is the bidirectional FIFO/GPIF data bus.

Multiplexed pin whose function is selected by the

following bits: IFCONFIG[1..0].

(PB4) PB4 is a bidirectional I/O port pin.

PB4 or

FD[4]

I

Z

(PB4)

FD[4] is the bidirectional FIFO/GPIF data bus.

Multiplexed pin whose function is selected by the

following bits: IFCONFIG[1..0].

(PB5) PB5 is a bidirectional I/O port pin.

PB5 or

FD[5]

I

Z

(PB5)

FD[5] is the bidirectional FIFO/GPIF data bus.

Multiplexed pin whose function is selected by the

following bits: IFCONFIG[1..0].

(PB6) PB6 is a bidirectional I/O port pin.

PB6 or

FD[6]

I

Z

(PB6)

FD[6] is the bidirectional FIFO/GPIF data bus.

Multiplexed pin whose function is selected by the

following bits: IFCONFIG[1..0].

(PB7) PB7 is a bidirectional I/O port pin.

PB7 or

FD[7]

I

Z

(PB7)

FD[7] is the bidirectional FIFO/GPIF data bus.

PORT C

Multiplexed pin whose function is selected by

Z

PC0 or

GPIFADR0

I

PORTCCFG.0

(PC0)

72

73

74

75

76

77

78

79

57

–

I/O/Z

(PC0)

PC0 is a bidirectional I/O port pin.

GPIFADR0 is a GPIF address output pin.

Multiplexed pin whose function is selected by

PC1 or

GPIFADR1

Z

I

PORTCCFG.1

(PC1)

58

59

60

61

62

63

64

(PC1)

PC1 is a bidirectional I/O port pin.

GPIFADR1 is a GPIF address output pin.

Multiplexed pin whose function is selected by

PORTCCFG.2

(PC2) (PC2) PC2 is a bidirectional I/O port pin.

GPIFADR2 is a GPIF address output pin.

PC2 or

GPIFADR2

I

Z

Multiplexed pin whose function is selected by

PORTCCFG.3

(PC3) (PC3) PC3 is a bidirectional I/O port pin.

PC3 or

GPIFADR3

I

Z

GPIFADR3 is a GPIF address output pin.

Multiplexed pin whose function is selected by

PORTCCFG.4

(PC4) (PC4) PC4 is a bidirectional I/O port pin.

GPIFADR4 is a GPIF address output pin.

PC4 or

GPIFADR4

I

Z

Multiplexed pin whose function is selected by

PORTCCFG.5

(PC5) (PC5) PC5 is a bidirectional I/O port pin.

GPIFADR5 is a GPIF address output pin.

PC5 or

GPIFADR5

I

Z

Multiplexed pin whose function is selected by

PORTCCFG.6

(PC6) (PC6) PC6 is a bidirectional I/O port pin.

GPIFADR6 is a GPIF address output pin.

PC6 or

GPIFADR6

I

Z

Multiplexed pin whose function is selected by

PORTCCFG.7

(PC7) (PC7) PC7 is a bidirectional I/O port pin.

GPIFADR7 is a GPIF address output pin.

PC7 or

GPIFADR7

I

Z

Document Number: 38-08032 Rev. AD

Page 28 of 74

CY7C68013A/CY7C68014A

CY7C68015A/CY7C68016A

Table 11. FX2LP Pin Descriptions^[14](continued)

128 100 56 56 56

Name

Type Default Reset^[15]

Description

TQFP TQFP SSOP QFN VFBGA

PORT D

Multiplexed pin whose function is selected by the

IFCONFIG[1..0] and EPxFIFOCFG.0 (wordwide)

(PD0) (PD0) bits.

FD[8] is the bidirectional FIFO/GPIF data bus.

PD0 or

FD[8]

I

Z

102

103

104

105

121

122

123

80

81

82

83

95

96

97

98

52

53

54

55

56

1

45

46

47

48

49

50

51

52

8A

7A

6B

6A

3B

3A

3C

2A

I/O/Z

Multiplexed pin whose function is selected by the

IFCONFIG[1..0] and EPxFIFOCFG.0 (wordwide)

(PD1) (PD1) bits.

FD[9] is the bidirectional FIFO/GPIF data bus.

PD1 or

FD[9]

I

Z

Multiplexed pin whose function is selected by the

IFCONFIG[1..0] and EPxFIFOCFG.0 (wordwide)

(PD2) (PD2) bits.

PD2 or

FD[10]

I

Z

FD[10] is the bidirectional FIFO/GPIF data bus.

Multiplexed pin whose function is selected by the

IFCONFIG[1..0] and EPxFIFOCFG.0 (wordwide)

(PD3) (PD3) bits.

FD[11] is the bidirectional FIFO/GPIF data bus.

PD3 or

FD[11]

I

Z

Multiplexed pin whose function is selected by the

IFCONFIG[1..0] and EPxFIFOCFG.0 (wordwide)

(PD4) (PD4) bits.

FD[12] is the bidirectional FIFO/GPIF data bus.

PD4 or

FD[12]

I

Z

Multiplexed pin whose function is selected by the

IFCONFIG[1..0] and EPxFIFOCFG.0 (wordwide)

(PD5) (PD5) bits.

PD5 or

FD[13]

I

Z

FD[13] is the bidirectional FIFO/GPIF data bus.

Multiplexed pin whose function is selected by the

IFCONFIG[1..0] and EPxFIFOCFG.0 (wordwide)

(PD6) (PD6) bits.

FD[14] is the bidirectional FIFO/GPIF data bus.

PD6 or

FD[14]

I

Z

2

Multiplexed pin whose function is selected by the

IFCONFIG[1..0] and EPxFIFOCFG.0 (wordwide)

(PD7) (PD7) bits.

FD[15] is the bidirectional FIFO/GPIF data bus.

PD7 or

FD[15]

I

Z

124

3

Port E

Multiplexed pin whose function is selected by the

PORTECFG.0 bit.

PE0 is a bidirectional I/O port pin.

T0OUT is an active-HIGH signal from 8051

Timer-counter0. T0OUT outputs a high level for

one CLKOUT clock cycle when Timer0 overflows.

If Timer0 is operated in Mode 3 (two separate

timer/counters), T0OUTis active when the low byte

timer/counter overflows.

PE0 or

T0OUT

I

Z

108

86

–

I/O/Z

(PE0)

Multiplexed pin whose function is selected by the

PORTECFG.1 bit.

PE1 is a bidirectional I/O port pin.

T1OUT is an active HIGH signal from 8051

Timer-counter1. T1OUT outputs a high level for

one CLKOUT clock cycle when Timer1 overflows.

If Timer1 is operated in Mode 3 (two separate

timer/counters), T1OUTis active when the low byte

timer/counter overflows.

PE1 or

T1OUT

I

Z

109

87

–

I/O/Z

(PE1)

Document Number: 38-08032 Rev. AD

Page 29 of 74

CY7C68013A/CY7C68014A

CY7C68015A/CY7C68016A

Table 11. FX2LP Pin Descriptions^[14](continued)

128 100 56 56 56

Name

Type Default Reset^[15]

Description

TQFP TQFP SSOP QFN VFBGA

Multiplexed pin whose function is selected by the

PORTECFG.2 bit.

PE2 is a bidirectional I/O port pin.

PE2 or

T2OUT

I

Z

110

111

88

89

–

I/O/Z

(PE2)

(PE2) T2OUT is the active HIGH output signal from 8051

Timer2. T2OUTis active (HIGH) for one clock cycle

when Timer/Counter 2 overflows.

Multiplexed pin whose function is selected by the

PORTECFG.3 bit.

PE3 is a bidirectional I/O port pin.

PE3 or

RXD0OUT

I

Z

RXD0OUT is an active HIGH signal from 8051

(PE3)

(PE3) UART0. If RXD0OUT is selected and UART0 is in

Mode 0, this pin provides the output data for

UART0 only when it is in sync mode. Otherwise it

is a 1.

Multiplexed pin whose function is selected by the

PORTECFG.4 bit.

PE4 is a bidirectional I/O port pin.

RXD1OUT is an active-HIGH output from 8051

(PE4) UART1. When RXD1OUT is selected and UART1

is in Mode 0, this pin provides the output data for

UART1 only when it is in sync mode. In Modes 1,

2, and 3, this pin is HIGH.

PE4 or

RXD1OUT

I

Z

112

113

90

91

–

I/O/Z

(PE4)

Multiplexed pin whose function is selected by the

PORTECFG.5 bit.

PE5 is a bidirectional I/O port pin.

PE5 or

INT6

I

Z

(PE5)

(PE5) INT6 is the 8051 INT6 interrupt request input

signal. The INT6 pin is edge-sensitive, active

HIGH.

Multiplexed pin whose function is selected by the

PORTECFG.6 bit.

PE6 is a bidirectional I/O port pin.

T2EX is an active HIGH input signal to the 8051

Timer2. T2EX reloads timer 2 on its falling edge.

T2EX is active only if the EXEN2 bit is set in

T2CON.

PE6 or

T2EX

I

Z

114

115

92

93

–

I/O/Z

(PE6)

Multiplexed pin whose function is selected by the

PORTECFG.7 bit.

(PE7) PE7 is a bidirectional I/O port pin.

GPIFADR8 is a GPIF address output pin.

PE7 or

GPIFADR8

I

Z

(PE7)

Multiplexed pin whose function is selected by the

following bits:

IFCONFIG[1..0].

RDY0 is a GPIF input signal.

SLRD is the input-only read strobe with program-

mable polarity (FIFOPINPOLAR.3) for the slave

FIFOs connected to FD[7..0] or FD[15..0].

RDY0 or

SLRD

4

3

8

1

1A

Input

N/A

Multiplexed pin whose function is selected by the

following bits:

IFCONFIG[1..0].

RDY1 is a GPIF input signal.

SLWR is the input-only write strobe with program-

mable polarity (FIFOPINPOLAR.2) for the slave

FIFOs connected to FD[7..0] or FD[15..0].

RDY1 or

SLWR

5

6

4

5

9

–

2

–

1B

–

Input

N/A

RDY2

RDY2 is a GPIF input signal.

Document Number: 38-08032 Rev. AD

Page 30 of 74

CY7C68013A/CY7C68014A

CY7C68015A/CY7C68016A

Table 11. FX2LP Pin Descriptions^[14](continued)

128 100 56 56 56

Name

Type Default Reset^[15]

Description

TQFP TQFP SSOP QFN VFBGA

7

8

9

6

7

8

–

RDY3

Input

N/A

RDY3 is a GPIF input signal.

RDY4 is a GPIF input signal.

RDY5 is a GPIF input signal.

RDY4

RDY5

Multiplexed pin whose function is selected by the

following bits:

IFCONFIG[1..0].

CTL0 or

FLAGA

CTL0 is a GPIF control output.

FLAGA is a programmable slave-FIFO output

status flag signal.

Defaults to programmable for the FIFO selected by

the FIFOADR[1:0] pins.

69

70

71

54

55

56

36

37

38

29

30

31

7H

7G

8H

O/Z

H

L

Multiplexed pin whose function is selected by the

following bits:

IFCONFIG[1..0].

CTL1 is a GPIF control output.

FLAGB is a programmable slave-FIFO output

status flag signal.

Defaults to FULL for the FIFO selected by the

FIFOADR[1:0] pins.

CTL1 or

FLAGB

Multiplexed pin whose function is selected by the

following bits:

IFCONFIG[1..0].

CTL2 is a GPIF control output.

FLAGC is a programmable slave-FIFO output

status flag signal.

CTL2 or

FLAGC

Defaults to EMPTY for the FIFO selected by the

FIFOADR[1:0] pins.

66

67

98

51

52

76

–

CTL3

O/Z

H

L

CTL3 is a GPIF control output.

CTL4 is a GPIF control output.

CTL5 is a GPIF control output.

CTL4

Output

CTL5

IFCLK on

CY7C68013A I/O/Z

and

Interface Clock, used for synchronously clocking

data into or out of the slave FIFOs. IFCLK also

serves as a timing reference for all slave FIFO

control signals and GPIF. When internal clocking is

used (IFCONFIG.7 = 1) the IFCLK pin can be

configured to output 30/48 MHz by bits

Z

CY7C68014A

32

26

20

13

2G

IFCONFIG.5 and IFCONFIG.6. IFCLK may be

inverted, whether internally or externally sourced,

by setting the bit IFCONFIG.4 =1.

------------------

PE0 on

CY7C68015A

and

---------- ---------- ---------- ------------------------------------------------------------------

–

I

Z

-----

I/O/Z

PE0 is a bidirectional I/O port pin.

CY7C68016A

INT4 is the 8051 INT4 interrupt request input

signal. The INT4 pin is edge-sensitive, active

HIGH.

28

22

84

–

INT4

Input

N/A

INT5# is the 8051 INT5 interrupt request input

signal. The INT5 pin is edge-sensitive, active LOW.

106

INT5#

T2 is the active HIGH T2 input signal to 8051

Timer2, which provides the input to Timer2 when

C/T2 = 1. When C/T2 = 0, Timer2 does not use this

pin.

31

25

–

T2

Input

N/A

Document Number: 38-08032 Rev. AD

Page 31 of 74

CY7C68013A/CY7C68014A

CY7C68015A/CY7C68016A

Table 11. FX2LP Pin Descriptions^[14](continued)

128 100 56 56 56

Name

Type Default Reset^[15]

Description

TQFP TQFP SSOP QFN VFBGA

T1 is the active HIGH T1 signal for 8051 Timer1,

which provides the input to Timer1 when C/T1 is 1.

When C/T1 is 0, Timer1 does not use this bit.

30

29

53

52

51

50

24

23

43

42

41

40

–

T1

T0

Input

N/A

H

N/A

L

T0 is the active HIGH T0 signal for 8051 Timer0,

which provides the input to Timer0 when C/T0 is 1.

When C/T0 is 0, Timer0 does not use this bit.

RXD1is an active HIGH input signal for 8051

UART1, which provides data to the UART in all

modes.

RXD1

TXD1

RXD0

TXD0

Input

TXD1is an active HIGH output pin from 8051

UART1, which provides the output clock in sync

mode, and the output data in async mode.

Output

Input

RXD0 is the active HIGH RXD0 input to 8051

UART0, which provides data to the UART in all

modes.

N/A

H

N/A

L

TXD0 is the active HIGH TXD0 output from 8051

UART0, which provides the output clock in sync

mode, and the output data in async mode.

Output

CS# is the active LOW chip select for external

memory.

42

41

40

38

–

CS#

WR#

RD#

OE#

Output

H

WR# is the active LOW write strobe output for

external memory.

32

31

RD# is the active LOW read strobe output for

external memory.

OE# is the active LOW output enable for external

memory.

33

27

79

21

14

2H

Reserved

Input

N/A

Reserved. Connect to ground.

USB Wakeup. If the 8051 is in suspend, asserting

this pin starts up the oscillator and interrupts the

8051 to enable it to exit the suspend mode. Holding

WAKEUP asserted inhibits the EZ-USB chip from

suspending. This pin has programmable polarity

(WAKEUP.4).

101

51

44

7B

WAKEUP

Input

N/A

Z

(if

Clock for the I²C interface. Connect to VCC with a

2.2-k resistor, even if no I²C peripheral is

attached.

36

37

29

30

22

23

15

16

3F

SCL

SDA

OD

Z

booting

is done)

Z

(if

Data for I²C compatible interface. Connect to

VCC with a 2.2-k resistor, even if no I²C

compatible peripheral is attached.

3G

booting

is done)

2

1

6

18

24

–

55

11

17

–

5A

1G

7E

–

VCC

Power

N/A

VCC. Connect to the 3.3-V power source.

VCC. Connect to 3.3-V power source.

VCC. Connect to the 3.3-V power source.

26

43

48

64

68

81

20

33

38

49

53

66

34

–

27

–

8E

–

39

32

5C

Document Number: 38-08032 Rev. AD

Page 32 of 74

CY7C68013A/CY7C68014A

CY7C68015A/CY7C68016A

Table 11. FX2LP Pin Descriptions^[14](continued)

128 100 56 56 56

Name

Type Default Reset^[15]

Description

TQFP TQFP SSOP QFN VFBGA

100

107

78

85

50

–

43

–

5B

–

VCC

Power

N/A

VCC. Connect to the 3.3-V power source.

VCC

3

2

7

19

–

56

12

–

4B

1H

–

GND

Ground N/A

N/A

Ground

27

21

39

48

50

65

75

94

99

49

58

33

35

–

26

28

–

7D

8D

–

65

80

93

48

–

41

–

4C

–

116

125

4

53

4A

14

15

16

13

14

15

–

NC

N/A

No Connect. This pin must be left open.

Document Number: 38-08032 Rev. AD

Page 33 of 74

CY7C68013A/CY7C68014A

CY7C68015A/CY7C68016A

Register Summary

FX2LP register bit definitions are described in the FX2LP TRM in greater detail.

Table 12. FX2LP Register Summary

Hex Size

Name

Description

b7

b6

b5

b4

b3

b2

b1

b0

Default Access

GPIF Waveform Memories

E400 128 WAVEDATA

GPIF Waveform

Descriptor 0, 1, 2, 3 data

D7

D6

D5

D4

D3

D2

D1

D0

xxxxxxxx RW

E480 128 reserved

GENERAL CONFIGURATION

E50D

GPCR2

General Purpose Configu- reserved

ration Register 2

reserved

0

reserved

FULL_-

SPEED_ON-

LY

reserved

00000000 R

E600

E601

1

CPUCS

CPU Control & Status

0

PORTCSTB CLKSPD1

CLKSPD0 CLKINV

CLKOE

IFCFG1

8051RES

IFCFG0

00000010 rrbbbbbr

10000000 RW

IFCONFIG

Interface Configuration

(Ports, GPIF, slave FIFOs)

IFCLKSRC 3048MHZ

IFCLKOE

FLAGB1

FLAGD1

0

IFCLKPOL ASYNC GSTATE

[16]

E602

E603

E604

1

PINFLAGSAB

Slave FIFO FLAGA and

FLAGB Pin Configuration

FLAGB3

FLAGB2

FLAGD2

0

FLAGB0

FLAGD0

0

FLAGA3

FLAGC3

EP3

FLAGA2

FLAGC2

EP2

FLAGA1

FLAGC1

EP1

FLAGA0

FLAGC0

EP0

00000000 RW

PINFLAGSCD

Slave FIFO FLAGC and FLAGD3

FLAGD Pin Configuration

[16]

FIFORESET

Restore FIFOS to default NAKALL

state

xxxxxxxx W

E605

E606

E607

E608

1

BREAKPT

BPADDRH

BPADDRL

UART230

Breakpoint Control

0

BREAK

A11

A3

BPPULSE

BPEN

A9

0

00000000 rrrrbbbr

xxxxxxxx RW

Breakpoint Address H

Breakpoint Address L

A15

A7

0

A14

A6

0

A13

A5

0

A12

A4

0

A10

A2

0

A8

A0

A1

230 Kbaud internally

generated ref. clock

0

230UART1 230UART0 00000000 rrrrrrbb

[16]

E609

E60A

E60B

1

FIFOPINPOLAR

Slave FIFO Interface pins

polarity

0

PKTEND

SLOE

rv4

SLRD

rv3

SLWR

rv2

EF

FF

00000000 rrbbbbbb

REVID

Chip Revision

rv7

0

rv6

0

rv5

0

rv1

rv0

RevA

00000001

R

[16]

REVCTL

Chip Revision Control

0

dyn_out

enh_pkt

00000000 rrrrrrbb

UDMA

E60C 1

3

GPIFHOLDAMOUNT MSTB Hold Time

(for UDMA)

0

HOLDTIME1 HOLDTIME0 00000000 rrrrrrbb

reserved

ENDPOINT CONFIGURATION

E610

E611

1

EP1OUTCFG

Endpoint 1-OUT

Configuration

VALID

0

TYPE1

TYPE0

0

10100000 brbbrrrr

EP1INCFG

Endpoint 1-IN

Configuration

E612

E613

E614

E615

1

2

1

EP2CFG

EP4CFG

EP6CFG

EP8CFG

reserved

Endpoint 2 Configuration VALID

Endpoint 4 Configuration VALID

Endpoint 6 Configuration VALID

Endpoint 8 Configuration VALID

DIR

TYPE1

TYPE0

SIZE

0

BUF1

0

BUF0

0

10100010 bbbbbrbb

10100000 bbbbrrrr

11100010 bbbbbrbb

11100000 bbbbrrrr

SIZE

0

BUF1

0

BUF0

0

[16]

E618

E619

E61A

E61B

EP2FIFOCFG

Endpoint 2 / slave FIFO

configuration

0

INFM1

OEP1

AUTOOUT AUTOIN

ZEROLENIN 0

WORDWIDE 00000101 rbbbbbrb

1

EP4FIFOCFG

EP6FIFOCFG

EP8FIFOCFG

reserved

Endpoint 4 / slave FIFO

configuration

Endpoint 6 / slave FIFO

configuration

Endpoint 8 / slave FIFO

configuration

E61C 4

[16

E620

E621

E622

E623

E624

E625

E626

E627

1

EP2AUTOINLENH

Endpoint 2 AUTOIN

Packet Length H

0

PL10

PL2

0

PL9

PL8

PL0

PL8

PL0

PL8

PL0

PL8

PL0

00000010 rrrrrbbb

00000000 RW

[16]

EP2AUTOINLENL

Endpoint 2 AUTOIN

Packet Length L

PL7

0

PL6

0

PL5

0

PL4

0

PL3

0

PL1

PL9

PL1

PL9

PL1

PL9

PL1

EP4AUTOINLENH

Endpoint 4 AUTOIN

Packet Length H

00000010 rrrrrrbb

00000000 RW

[16]

EP4AUTOINLENL

EP6AUTOINLENH

Endpoint 4 AUTOIN

Packet Length L

PL7

0

PL6

0

PL5

0

PL4

0

PL3

0

PL2

PL10

PL2

0

[16]

Endpoint 6 AUTOIN

Packet Length H

00000010 rrrrrbbb

00000000 RW

[16]

EP6AUTOINLENL

Endpoint 6 AUTOIN

Packet Length L

PL7

0

PL6

0

PL5

0

PL4

0

PL3

0

EP8AUTOINLENH

Endpoint 8 AUTOIN

Packet Length H

00000010 rrrrrrbb

00000000 RW

[16]

EP8AUTOINLENL

Endpoint 8 AUTOIN

Packet Length L

PL7

PL6

PL5

PL4

PL3

PL2

E628

E629

E62A

1

ECCCFG

ECCRESET

ECC1B0

ECC Configuration

ECC Reset

0

ECCM

x

00000000 rrrrrrrb

00000000 W

00000000 R

x

ECC1 Byte 0 Address

LINE15

LINE14

LINE13

LINE12

LINE11

LINE10

LINE9

LINE8

Note

16. Read and writes to these registers may require synchronization delay; see Technical Reference Manual for “Synchronization Delay.”

Document Number: 38-08032 Rev. AD

Page 34 of 74

CY7C68013A/CY7C68014A

CY7C68015A/CY7C68016A

Table 12. FX2LP Register Summary (continued)

Hex Size

E62B

Name

ECC1B1

Description

ECC1 Byte 1 Address

ECC1 Byte 2 Address

ECC2 Byte 0 Address

ECC2 Byte 1 Address

ECC2 Byte 2 Address

b7

LINE7

b6

LINE6

b5

LINE5

b4

LINE4

b3

LINE3

b2

LINE2

b1

LINE1

b0

LINE0

Default Access

00000000 R

1

E62C 1

E62D 1

ECC1B2

COL5

COL4

COL3

LINE13

LINE5

COL3

COL2

LINE12

LINE4

COL2

COL1

LINE11

LINE3

COL1

COL0

LINE10

LINE2

COL0

0

LINE17

LINE9

LINE1

0

LINE16

LINE8

LINE0

0

00000000 R

ECC2B0

LINE15

LINE7

COL5

LINE14

LINE6

00000000 R

E62E

E62F

1

ECC2B1

00000000 R

ECC2B2

COL4

00000000 R

[17]

E630

H.S.

EP2FIFOPFH

Endpoint 2 / slave FIFO

Programmable Flag H

DECIS

PKTSTAT

IN:PKTS[2] IN:PKTS[1] IN:PKTS[0]

OUT:PFC12 OUT:PFC11 OUT:PFC10

PFC9

PFC8

10001000 bbbbbrbb

E630

F.S.

1

EP2FIFOPFH

Endpoint 2 / slave FIFO

Programmable Flag H

DECIS

PFC7

PKTSTAT

PFC6

OUT:PFC12 OUT:PFC11 OUT:PFC10 0

PFC9

PFC1

0

IN:PKTS[2] 10001000 bbbbbrbb

OUT:PFC8

[17]

E631

H.S.

EP2FIFOPFL

Endpoint 2 / slave FIFO

Programmable Flag L

PFC5

PFC4

PFC3

PFC2

PFC0

PFC8

PFC0

PFC8

00000000 RW

E631

F.S

Endpoint 2 / slave FIFO

Programmable Flag L

IN:PKTS[1] IN:PKTS[0] PFC5

OUT:PFC7

00000000 RW

OUT:PFC6

E632

H.S.

EP4FIFOPFH

Endpoint 4 / slave FIFO

Programmable Flag H

DECIS

PKTSTAT

0

IN: PKTS[1] IN: PKTS[0] 0

OUT:PFC10 OUT:PFC9

10001000 bbrbbrrb

00000000 RW

[17]

E632

F.S

Endpoint 4 / slave FIFO

Programmable Flag H

DECIS

PFC7

PKTSTAT

PFC6

0

OUT:PFC10 OUT:PFC9

0

[17]

E633

H.S.

EP4FIFOPFL

Endpoint 4 / slave FIFO

Programmable Flag L

PFC5

PFC4

PFC3

PFC2

0

PFC1

PFC9

PFC1

0

E633

F.S

Endpoint 4 / slave FIFO

Programmable Flag L

IN: PKTS[1] IN: PKTS[0] PFC5

OUT:PFC7

00000000 RW

OUT:PFC6

E634

H.S.

EP6FIFOPFH

Endpoint 6 / slave FIFO

Programmable Flag H

DECIS

PKTSTAT

IN:PKTS[2] IN:PKTS[1] IN:PKTS[0]

OUT:PFC12 OUT:PFC11 OUT:PFC10

00001000 bbbbbrbb

[17]

E634

F.S

Endpoint 6 / slave FIFO

Programmable Flag H

DECIS

PFC7

PKTSTAT

PFC6

OUT:PFC12 OUT:PFC11 OUT:PFC10 0

IN:PKTS[2] 00001000 bbbbbrbb

OUT:PFC8

[17]

E635

H.S.

EP6FIFOPFL

Endpoint 6 / slave FIFO

Programmable Flag L

PFC5

PFC4

PFC3

PFC2

PFC0

PFC8

PFC0

00000000 RW

E635

F.S

Endpoint 6 / slave FIFO

Programmable Flag L

IN:PKTS[1] IN:PKTS[0] PFC5

OUT:PFC7

00000000 RW

OUT:PFC6

E636

H.S.

EP8FIFOPFH

Endpoint 8 / slave FIFO

Programmable Flag H

DECIS

PKTSTAT

0

IN: PKTS[1] IN: PKTS[0] 0

OUT:PFC10 OUT:PFC9

00001000 bbrbbrrb

00000000 RW

[17]

E636

F.S

Endpoint 8 / slave FIFO

Programmable Flag H

DECIS

PFC7

PKTSTAT

PFC6

0

OUT:PFC10 OUT:PFC9

0

[17]

E637

H.S.

EP8FIFOPFL

reserved

Endpoint 8 / slave FIFO

Programmable Flag L

PFC5

PFC4

PFC3

PFC2

PFC1

E637

F.S

Endpoint 8 / slave FIFO

Programmable Flag L

IN: PKTS[1] IN: PKTS[0] PFC5

OUT:PFC7

00000000 RW

OUT:PFC6

8

1

E640

E641

E642

E643

EP2ISOINPKTS

EP4ISOINPKTS

EP6ISOINPKTS

EP8ISOINPKTS

reserved

EP2 (if ISO) IN Packets per AADJ

frame (1-3)

0

INPPF1

INPPF0

00000001 brrrrrbb

00000001 brrrrrrr

00000001 brrrrrbb

00000001 brrrrrrr

1

EP4 (if ISO) IN Packets per AADJ

frame (1-3)

EP6 (if ISO) IN Packets per AADJ

frame (1-3)

EP8 (if ISO) IN Packets per AADJ

frame (1-3)

E644

E648

E649

4

1

7

[17]

INPKTEND

Force IN Packet End

Skip

0

EP3

EP2

EP1

EP0

xxxxxxxx

W

[17]

OUTPKTEND

Force OUT Packet End

INTERRUPTS

[17]

E650

E651

E652

E653

E654

E655

E656

E657

E658

E659

E65A

E65B

1

EP2FIFOIE

Endpoint 2 slave FIFO Flag 0

Interrupt Enable

0

EDGEPF

0

PF

EF

EP1

0

FF

00000000 RW

[17,18]

EP2FIFOIRQ

Endpoint 2 slave FIFO Flag 0

Interrupt Request

0

PF

FF

00000000 rrrrrbbb

00000000 RW

[17]

EP4FIFOIE

Endpoint 4 slave FIFO Flag 0

Interrupt Enable

0

EDGEPF

0

PF

FF

[17,18]

EP4FIFOIRQ

Endpoint 4 slave FIFO Flag 0

Interrupt Request

0

PF

FF

00000000 rrrrrbbb

00000000 RW

[17]

EP6FIFOIE

Endpoint 6 slave FIFO Flag 0

Interrupt Enable

0

EDGEPF

0

PF

FF

EP6FIFOIRQ

Endpoint 6 slave FIFO Flag 0

Interrupt Request

0

PF

FF

00000000 rrrrrbbb

00000000 RW

[17]

EP8FIFOIE

EP8FIFOIRQ

IBNIE

Endpoint 8 slave FIFO Flag 0

Interrupt Enable

0

EDGEPF

0

PF

FF

Endpoint 8 slave FIFO Flag 0

Interrupt Request

0

PF

FF

00000000 rrrrrbbb

00000000 RW

IN-BULK-NAK Interrupt

Enable

0

EP8

EP4

EP6

EP2

EP4

EP2

EP0

SUTOK

EP0

IBN

SUDAV

[18]

IBNIRQ

IN-BULK-NAK interrupt

Request

0

EP4

00xxxxxx rrbbbbbb

00000000 RW

NAKIE

Endpoint Ping-NAK / IBN EP8

Interrupt Enable

EP6

EP0ACK

EP1

[18]

NAKIRQ

Endpoint Ping-NAK / IBN EP8

Interrupt Request

EP1

0

xxxxxx0x bbbbbbrb

00000000 RW

E65C 1

USBIE

USB Int Enables

0

HSGRANT URES

SUSP

SOF

Notes

17. Read and writes to these registers may require synchronization delay; see Technical Reference Manual for “Synchronization Delay”.

18. The register can only be reset; it cannot be set.

Document Number: 38-08032 Rev. AD

Page 35 of 74

CY7C68013A/CY7C68014A

CY7C68015A/CY7C68016A

Table 12. FX2LP Register Summary (continued)

Hex Size

Name

Description

b7

b6

EP0ACK

EP6

b5

b4

b3

SUSP

b2

SUTOK

EP1IN

b1

b0

SUDAV

Default Access

0xxxxxxx rbbbbbbb

00000000 RW

[19]

E65D 1

USBIRQ

USB Interrupt Requests

0

HSGRANT URES

SOF

E65E

1

EPIE

Endpoint Interrupt

Enables

EP8

EP4

EP2

EP1OUT

EP0OUT

EP0IN

[19]

[20]

E65F

1

EPIRQ

Endpoint Interrupt

Requests

EP8

EP6

EP1OUT

EP1IN

EP0OUT

EP0IN

0

RW

E660

E661

E662

1

GPIFIE

GPIF Interrupt Enable

GPIF Interrupt Request

0

GPIFWF

0

GPIFDONE 00000000 RW

GPIFDONE 000000xx RW

[20]

GPIFIRQ

0

USBERRIE

USB Error Interrupt

Enables

ISOEP8

ISOEP6

ISOEP4

ISOEP2

ERRLIMIT

00000000 RW

[19]

E663

1

USBERRIRQ

USB Error Interrupt

Requests

ISOEP8

ISOEP6

ISOEP4

ISOEP2

0

ERRLIMIT

0000000x bbbbrrrb

E664

E665

E666

1

ERRCNTLIM

USB Error counter and limit EC3

Clear Error Counter EC3:0 x

EC2

x

EC1

x

EC0

x

LIMIT3

x

LIMIT2

x

LIMIT1

LIMIT0

xxxx0100 rrrrbbbb

CLRERRCNT

INT2IVEC

x

xxxxxxxx W

Interrupt 2 (USB)

Autovector

0

1

0

I2V4

I2V3

I2V2

I2V1

I2V0

0

00000000 R

10000000 R

00000000 RW

E667

1

INT4IVEC

Interrupt 4 (slave FIFO &

GPIF) Autovector

0

I4V3

0

I4V2

0

I4V1

I4V0

0

E668

E669

1

7

INTSET-UP

reserved

Interrupt 2&4 setup

AV2EN

INT4SRC

AV4EN

INPUT / OUTPUT

PORTACFG

E670

E671

E672

1

I/O PORTAAlternate

Configuration

FLAGD

GPIFA7

GPIFA8

SLCS

GPIFA6

T2EX

0

INT1

INT0

00000000 RW

PORTCCFG

PORTECFG

I/O PORTC Alternate

Configuration

GPIFA5

INT6

GPIFA4

GPIFA3

GPIFA2

GPIFA1

T1OUT

GPIFA0

T0OUT

I/O PORTE Alternate

Configuration

RXD1OUT RXD0OUT T2OUT

E673

E677

E678

4

1

reserved

2

I CS

I²C Bus

START

STOP

d6

LASTRD

ID1

d4

0

ID0

d3

0

BERR

d2

ACK

d1

DONE

d0

000xx000 bbbrrrrr

xxxxxxxx RW

00000000 RW

xxxxxxxx RW

Control & Status

E679

E67A

E67B

1

I2DAT

I²C Bus

Data

d7

0

d5

0

2

I CTL

I²C Bus

Control

0

STOPIE

D1

400KHZ

D0

XAUTODAT1

XAUTODAT2

UDMA CRC

Autoptr1 MOVX access, D7

when APTREN=1

D6

D5

D4

D3

D2

E67C 1

Autoptr2 MOVX access, D7

when APTREN=1

D1

D0

[20]

E67D 1

UDMACRCH

UDMA CRC MSB

UDMA CRC LSB

UDMA CRC Qualifier

CRC15

CRC14

CRC6

0

CRC13

CRC5

0

CRC12

CRC4

0

CRC11

CRC3

CRC10

CRC2

CRC9

CRC1

CRC8

CRC0

01001010 RW

10111010 RW

[20]

E67E

E67F

1

UDMACRCL

CRC7

UDMACRC-

QUALIFIER

QENABLE

QSTATE

QSIGNAL2 QSIGNAL1 QSIGNAL0 00000000 brrrbbbb

USB CONTROL

USBCS

E680

E681

E682

E683

E684

E685

E686

E687

E688

1

2

USB Control & Status

Put chip into suspend

HSM

x

0

DISCON

NOSYNSOF RENUM

SIGRSUME x0000000 rrrrbbbb

SUSPEND

WAKEUPCS

TOGCTL

x

xxxxxxxx W

Wakeup Control & Status WU2

WU

S

WU2POL

WUPOL

I/O

0

DPEN

EP2

FC10

FC2

MF2

FA2

WU2EN

EP1

FC9

FC1

MF1

FA1

WUEN

EP0

FC8

FC0

MF0

FA0

xx000101 bbbbrbbb

x0000000 rrrbbbbb

00000xxx R

Toggle Control

Q

R

EP3

0

USBFRAMEH

USBFRAMEL

MICROFRAME

FNADDR

USB Frame count H

USB Frame count L

Microframe count, 0-7

USB Function address

0

FC7

0

FC6

0

FC5

0

FC4

0

FC3

0

xxxxxxxx

00000xxx R

0xxxxxxx R

R

0

FA6

FA5

FA4

FA3

reserved

ENDPOINTS

[20]

E68A

E68B

1

EP0BCH

Endpoint 0 Byte Count H (BC15)

Endpoint 0 Byte Count L (BC7)

(BC14)

BC6

(BC13)

BC5

(BC12)

BC4

(BC11)

BC3

(BC10)

BC2

(BC9)

BC1

(BC8)

BC0

xxxxxxxx RW

[20]

EP0BCL

E68C 1

E68D 1

reserved

EP1OUTBC

Endpoint 1 OUT Byte

Count

0

BC6

BC5

BC4

BC3

BC2

BC1

BC0

0xxxxxxx RW

E68E

E68F

E690

E691

E692

E694

E695

E696

E698

E699

1

2

1

2

1

reserved

EP1INBC

Endpoint 1 IN Byte Count

Endpoint 2 Byte Count H

0

BC6

0

BC5

0

BC4

0

BC3

0

BC2

BC10

BC2

BC1

BC9

BC1

BC0

BC8

BC0

0xxxxxxx RW

00000xxx RW

xxxxxxxx RW

[20]

EP2BCH

[20]

EP2BCL

Endpoint 2 Byte Count L BC7/SKIP

BC6

BC5

BC4

BC3

reserved

[20]

EP4BCH

Endpoint 4 Byte Count H

0

BC9

BC1

BC8

BC0

000000xx RW

xxxxxxxx RW

[20]

EP4BCL

Endpoint 4 Byte Count L BC7/SKIP

BC6

BC5

BC4

BC3

BC2

reserved

[20]

EP6BCH

Endpoint 6 Byte Count H

0

BC10

BC2

BC9

BC1

BC8

BC0

00000xxx RW

xxxxxxxx RW

[20]

EP6BCL

Endpoint 6 Byte Count L BC7/SKIP

BC6

BC5

BC4

BC3

Notes

19. The register can only be reset; it cannot be set.

20. Read and writes to these registers may require synchronization delay; see Technical Reference Manual for “Synchronization Delay”.

Document Number: 38-08032 Rev. AD

Page 36 of 74

CY7C68013A/CY7C68014A

CY7C68015A/CY7C68016A

Table 12. FX2LP Register Summary (continued)

Hex Size

E69A

Name

reserved

Description

b7

b6

b5

b4

b3

b2

b1

b0

Default Access

2

[21]

E69C 1

E69D 1

EP8BCH

Endpoint 8 Byte Count H

0

BC9

BC1

BC8

BC0

000000xx RW

xxxxxxxx RW

[21]

EP8BCL

reserved

EP0CS

Endpoint 8 Byte Count L BC7/SKIP

BC6

BC5

BC4

BC3

BC2

E69E

E6A0

2

1

Endpoint0ControlandSta-HSNAK

tus

0

BUSY

0

STALL

FF

10000000 bbbbbbrb

00000000 bbbbbbrb

00101000 rrrrrrrb

00000100 rrrrrrrb

00000010 R

E6A1

E6A2

E6A3

E6A4

E6A5

E6A6

E6A7

E6A8

E6A9

1

EP1OUTCS

EP1INCS

Endpoint 1 OUT Control

and Status

0

Endpoint 1 IN Control and 0

Status

EP2CS

Endpoint2ControlandSta-0

tus

NPAK2

NPAK1

NPAK0

0

FULL

0

EMPTY

PF

EP4CS

Endpoint4ControlandSta-0

tus

0

NPAK1

0

EP6CS

Endpoint6ControlandSta-0

tus

NPAK2

NPAK1

0

EP8CS

Endpoint8ControlandSta-0

tus

0

NPAK1

0

EP2FIFOFLGS

EP4FIFOFLGS

EP6FIFOFLGS

EP8FIFOFLGS

EP2FIFOBCH

EP2FIFOBCL

EP4FIFOBCH

EP4FIFOBCL

EP6FIFOBCH

EP6FIFOBCL

EP8FIFOBCH

EP8FIFOBCL

SUDPTRH

Endpoint 2 slave FIFO

Flags

0

EF

Endpoint 4 slave FIFO

Flags

0

PF

EF

FF

00000010 R

Endpoint 6 slave FIFO

Flags

0

PF

EF

FF

00000110 R

E6AA 1

E6AB 1

E6AC 1

E6AD 1

E6AE 1

E6AF 1

Endpoint 8 slave FIFO

Flags

0

PF

EF

FF

00000110 R

Endpoint 2 slave FIFO

total byte count H

0

BC12

BC4

0

BC11

BC3

0

BC10

BC2

BC10

BC2

BC10

BC2

BC10

BC2

A10

BC9

BC1

BC9

BC1

BC9

BC1

BC9

BC1

A9

BC8

00000000 R

Endpoint 2 slave FIFO

total byte count L

BC7

0

BC6

0

BC5

0

BC0

00000000 R

Endpoint 4 slave FIFO

total byte count H

BC8

00000000 R

Endpoint 4 slave FIFO

total byte count L

BC7

0

BC6

0

BC5

0

BC4

0

BC3

BC11

BC3

0

BC0

00000000 R

Endpoint 6 slave FIFO

total byte count H

BC8

00000000 R

E6B0

E6B1

E6B2

E6B3

E6B4

E6B5

1

Endpoint 6 slave FIFO

total byte count L

BC7

0

BC6

0

BC5

0

BC4

0

BC0

00000000 R

Endpoint 8 slave FIFO

total byte count H

BC8

00000000 R

Endpoint 8 slave FIFO

total byte count L

BC7

BC6

A14

A6

0

BC5

A13

A5

0

BC4

A12

A4

BC3

A11

A3

BC0

00000000 R

Setup Data Pointer high A15

address byte

A8

xxxxxxxx RW

xxxxxxx0 bbbbbbbr

00000001 RW

SUDPTRL

Setup Data Pointer low ad- A7

dress byte

A2

A1

0

SUDPTRCTL

Setup Data Pointer Auto

Mode

0

SDPAUTO

2

8

reserved

E6B8

SET-UPDAT

8 bytes of setup data

D7

D6

D5

D4

D3

D2

D1

D0

xxxxxxxx R

SET-UPDAT[0] =

bmRequestType

SET-UPDAT[1] =

bmRequest

SET-UPDAT[2:3] = wValue

SET-UPDAT[4:5] = wIndex

SET-UPDAT[6:7] =

wLength

GPIF

E6C0 1

E6C1 1

GPIFWFSELECT

GPIFIDLECS

Waveform Selector

SINGLEWR1 SINGLEWR0 SINGLERD1 SINGLERD0 FIFOWR1 FIFOWR0

FIFORD1

0

FIFORD0

IDLEDRV

11100100 RW

10000000 RW

GPIF Done, GPIF IDLE

drive mode

DONE

0

E6C2 1

E6C3 1

E6C4 1

E6C5 1

GPIFIDLECTL

GPIFCTLCFG

Inactive Bus, CTL states

CTL Drive Type

0

CTL5

0

CTL4

0

CTL3

0

CTL2

0

CTL1

0

CTL0

11111111 RW

00000000 RW

TRICTL

0

CTL0

[21]

GPIFADRH

GPIF Address H

0

GPIFA8

GPIFA0

[21]

GPIFADRL

GPIF Address L

GPIFA7

GPIFA6

GPIFA5

GPIFA4

GPIFA3

GPIFA2

GPIFA1

FLOWSTATE

E6C6 1

Flowstate Enable and

Selector

FSE

0

FS2

FS1

FS0

00000000 brrrrbbb

E6C7 1

E6C8 1

FLOWLOGIC

Flowstate Logic

LFUNC1

CTL0E3

LFUNC0

CTL0E2

TERMA2

TERMA1

TERMA0

CTL3

TERMB2

CTL2

TERMB1

CTL1

TERMB0

CTL0

00000000 RW

FLOWEQ0CTL

CTL-Pin States in

Flowstate

(when Logic = 0)

CTL0E1/

CTL5

CTL0E0/

CTL4

Note

21. Read and writes to these registers may require synchronization delay; see Technical Reference Manual for “Synchronization Delay”.

Document Number: 38-08032 Rev. AD

Page 37 of 74

CY7C68013A/CY7C68014A

CY7C68015A/CY7C68016A

Table 12. FX2LP Register Summary (continued)

Hex Size

Name

Description

b7

b6

b5

b4

b3

CTL3

b2

CTL2

b1

CTL1

b0

Default Access

E6C9 1

FLOWEQ1CTL

CTL-Pin States in Flow- CTL0E3

state (when Logic = 1)

CTL0E2

CTL0E1/

CTL5

CTL0E0/

CTL4

CTL0

00000000 RW

E6CA 1

E6CB 1

FLOWHOLDOFF

FLOWSTB

Holdoff Configuration

HOPERIOD3 HOPERIOD2 HOPERIOD1 HOPERIOD0 HOSTATE HOCTL2

HOCTL1

MSTB1

HOCTL0

MSTB0

00010010 RW

00100000 RW

Flowstate Strobe

Configuration

SLAVE

RDYASYNC CTLTOGL

SUSTAIN

0

MSTB2

E6CC 1

FLOWSTBEDGE

Flowstate Rising/Falling

Edge Configuration

0

FALLING

RISING

00000001 rrrrrrbb

E6CD 1

E6CE 1

FLOWSTBPERIOD Master-Strobe Half-Period D7

[22]

D6

D5

D4

D3

D2

D1

D0

00000010 RW

00000000 RW

GPIFTCB3

GPIFTCB2

GPIFTCB1

GPIFTCB0

GPIF Transaction Count TC31

Byte 3

TC30

TC29

TC28

TC27

TC26

TC25

TC24

[22]

E6CF 1

E6D0 1

E6D1 1

2

GPIF Transaction Count TC23

Byte 2

TC22

TC14

TC6

TC21

TC13

TC5

TC20

TC12

TC4

TC19

TC11

TC3

TC18

TC10

TC2

TC17

TC9

TC1

TC16

TC8

TC0

00000000 RW

00000001 RW

00000000 RW

GPIF Transaction Count TC15

Byte 1

GPIF Transaction Count TC7

Byte 0

reserved

[22]

E6D2 1

E6D3 1

EP2GPIFFLGSEL

Endpoint 2 GPIF Flag

select

0

x

0

x

0

x

0

x

0

x

0

x

FS1

0

FS0

00000000 RW

EP2GPIFPFSTOP

Endpoint 2 GPIF stop

transaction on prog. flag

FIFO2FLAG 00000000 RW

[22]

E6D4 1

3

EP2GPIFTRIG

Endpoint 2 GPIF Trigger

x

xxxxxxxx W

reserved

[22]

E6DA 1

E6DB 1

EP4GPIFFLGSEL

Endpoint 4 GPIF Flag

select

0

x

0

x

0

x

0

x

0

x

0

x

FS1

0

FS0

00000000 RW

EP4GPIFPFSTOP

Endpoint 4 GPIF stop

transaction on GPIF Flag

FIFO4FLAG 00000000 RW

[22]

E6DC 1

3

EP4GPIFTRIG

Endpoint 4 GPIF Trigger

x

xxxxxxxx W

reserved

[22]

E6E2

E6E3

E6E4

1

EP6GPIFFLGSEL

Endpoint 6 GPIF Flag

select

0

x

0

x

0

x

0

x

0

x

0

x

FS1

0

FS0

00000000 RW

EP6GPIFPFSTOP

Endpoint 6 GPIF stop

transaction on prog. flag

FIFO6FLAG 00000000 RW

[22]

1

3

EP6GPIFTRIG

Endpoint 6 GPIF Trigger

x

xxxxxxxx W

reserved

[22]

E6EA 1

E6EB 1

EP8GPIFFLGSEL

Endpoint 8 GPIF Flag

select

0

x

0

x

0

x

0

x

0

x

0

x

FS1

0

FS0

00000000 RW

EP8GPIFPFSTOP

Endpoint 8 GPIF stop

transaction on prog. flag

FIFO8FLAG 00000000 RW

[22]

E6EC 1

3

EP8GPIFTRIG

Endpoint 8 GPIF Trigger

x

xxxxxxxx W

reserved

E6F0

E6F1

E6F2

E6F3

1

XGPIFSGLDATH

GPIF Data H

D15

D14

D6

D13

D12

D4

0

D11

D3

0

D10

D2

0

D9

D1

0

D8

D0

0

xxxxxxxx RW

(16-bit mode only)

XGPIFSGLDATLX

Read/Write GPIF Data L & D7

trigger transaction

D5

XGPIFSGLDATLNOX Read GPIF Data L, no

transaction trigger

D7

D6

D5

xxxxxxxx

R

GPIFREADYCFG

Internal RDY, Sync/Async, INTRDY

RDY pin states

SAS

TCXRDY5

00000000 bbbrrrrr

E6F4

E6F5

E6F6

1

2

GPIFREADYSTAT

GPIFABORT

GPIF Ready Status

0

x

0

x

RDY5

x

RDY4

x

RDY3

x

RDY2

x

RDY1

x

RDY0

x

00xxxxxx

xxxxxxxx

R

Abort GPIF Waveforms

W

reserved

ENDPOINT BUFFERS

E740 64 EP0BUF

EP0-IN/-OUT buffer

EP1-OUT buffer

EP1-IN buffer

D7

D6

D5

D4

D3

D2

D1

D0

xxxxxxxx RW

RW

E780 64 EP10UTBUF

E7C0 64 EP1INBUF

E800 2048 reserved

F000 1024 EP2FIFOBUF

512/1024 byte EP 2 / slave D7

FIFO buffer (IN or OUT)

D6

D5

D4

D3

D2

D1

D0

xxxxxxxx RW

F400 512 EP4FIFOBUF

F600 512 reserved

512 byte EP 4 / slave FIFO D7

buffer (IN or OUT)

xxxxxxxx RW

Note

22. Read and writes to these registers may require synchronization delay; see Technical Reference Manual for “Synchronization Delay”.

Document Number: 38-08032 Rev. AD

Page 38 of 74

CY7C68013A/CY7C68014A

CY7C68015A/CY7C68016A

Table 12. FX2LP Register Summary (continued)

Hex Size

Name

Description

b7

b6

b5

b4

b3

b2

b1

b0

Default Access

F800 1024 EP6FIFOBUF

FC00 512 EP8FIFOBUF

FE00 512 reserved

512/1024 byte EP 6 / slave D7

FIFO buffer (IN or OUT)

D6

D5

D4

D3

D2

D1

D0

xxxxxxxx RW

512 byte EP 8 / slave FIFO D7

buffer (IN or OUT)

xxxxxxxx RW

xxxx

I²C Configuration Byte

0

DISCON

0

400KHZ

xxxxxxxx n/a

[23]

Special Function Registers (SFRs)

[24]

80

81

82

83

84

85

86

87

88

1

IOA

SP

Port A (bit addressable)

Stack Pointer

D7

A7

A15

A7

A15

0

D6

A6

A14

A6

A14

0

D5

A5

A13

A5

A13

0

D4

A4

A12

A4

A12

0

D3

A3

A11

A3

A11

0

D2

A2

A10

A2

A10

0

D1

A1

A9

A1

A9

0

D0

xxxxxxxx RW

00000111 RW

00000000 RW

00110000 RW

00000000 RW

D0

DPL0

DPH0

Data Pointer 0 L

Data Pointer 0 H

Data Pointer 1 L

Data Pointer 1 H

Data Pointer 0/1 select

Power Control

A0

A8

[24]

DPL1

DPH1

A0

[24]

A8

[24]

DPS

SEL

IDLE

IT0

PCON

TCON

SMOD0

TF1

x

1

x

Timer/Counter Control

(bit addressable)

TR1

TF0

TR0

IE1

IT1

IE0

89

1

TMOD

Timer/Counter Mode

Control

GATE

CT

M1

M0

GATE

CT

M1

M0

00000000 RW

8A

8B

8C

8D

8E

8F

90

91

92

1

TL0

Timer 0 reload L

Timer 1 reload L

Timer 0 reload H

Timer 1 reload H

Clock Control

D7

D15

x

D6

D14

x

D5

D4

D3

D2

D1

D0

00000000 RW

00000001 RW

TL1

D5

D4

D3

D2

D1

D0

TH0

D13

T2M

D12

T1M

D11

T0M

D10

MD2

D9

D8

TH1

D9

D8

[24]

CKCON

MD1

MD0

reserved

[24]

IOB

Port B (bit addressable)

D7

D6

D5

D4

D3

1

D2

0

D1

0

D0

0

xxxxxxxx RW

00001000 RW

00000000 RW

[24]

EXIF

External Interrupt Flag(s) IE5

IE4

A14

I²CINT

A13

USBNT

A12

[24]

MPAGE

Upper Addr Byte of MOVX A15

using @R0 / @R1

A11

A10

A9

A8

93

98

5

1

reserved

SCON0

Serial Port 0 Control

(bit addressable)

SM0_0

SM1_0

SM2_0

REN_0

TB8_0

RB8_0

TI_0

RI_0

00000000 RW

99

9A

9B

9C

9D

9E

9F

A0

A1

A2

A3

A8

1

5

1

SBUF0

Serial Port 0 Data Buffer D7

Autopointer 1 Address H A15

Autopointer 1 Address L A7

D6

D5

D4

D3

A11

A3

D2

D1

A9

A1

D0

A8

A0

00000000 RW

[24]

AUTOPTRH1

A14

A6

A13

A5

A12

A4

A10

A2

[24]

AUTOPTRL1

reserved

[24]

AUTOPTRH2

Autopointer 2 Address H A15

Autopointer 2 Address L A7

A14

A6

A13

A5

A12

A4

A11

A3

A10

A2

A9

A1

A8

A0

00000000 RW

[24]

AUTOPTRL2

reserved

[24]

IOC

Port C (bit addressable) D7

D6

x

D5

x

D4

x

D3

x

D2

x

D1

x

D0

x

xxxxxxxx RW

[24]

INT2CLR

Interrupt 2 clear

Interrupt 4 clear

x

xxxxxxxx

W

[24]

INT4CLR

x

reserved

IE

Interrupt Enable

(bit addressable)

EA

ES1

ET2

ES0

ET1

EX1

ET0

EX0

00000000 RW

A9

AA

1

reserved

[24]

EP2468STAT

Endpoint 2,4,6,8 status

flags

EP8F

EP8E

EP6F

EP6E

EP4F

EP4E

EP2F

EP2E

01011010 R

00100010 R

01100110 R

AB

AC

1

EP24FIFOFLGS

[24]

Endpoint 2,4 slave FIFO

status flags

0

EP4PF

EP8PF

EP4EF

EP8EF

EP4FF

EP8FF

0

EP2PF

EP6PF

EP2EF

EP6EF

EP2FF

EP6FF

EP68FIFOFLGS

[24]

Endpoint 6,8 slave FIFO

status flags

AD

AF

B0

B1

2

1

reserved

[24]

AUTOPTRSETUP

Autopointer 1&2 setup

0

APTR2INC APTR1INC APTREN

00000110 RW

xxxxxxxx RW

[24]

IOD

Port D (bit addressable) D7

D6

D5

D4

D3

D2

D1

D0

[24]

IOE

Port E

(NOT bit addressable)

D7

[24]

B2

B3

B4

B5

B6

B7

B8

1

OEA

Port A Output Enable

Port B Output Enable

Port C Output Enable

Port D Output Enable

Port E Output Enable

D7

D6

D5

D4

D3

D2

D1

D0

00000000 RW

[24]

OEB

[24]

OEC

[24]

OED

[24]

OEE

reserved

IP

Interrupt Priority (bit ad-

dressable)

1

PS1

PT2

PS0

PT1

PX1

PT0

PX0

10000000 RW

B9

1

reserved

Notes

23. If no EEPROM is detected by the SIE then the default is 00000000.

24. SFRs not part of the standard 8051 architecture.

Document Number: 38-08032 Rev. AD

Page 39 of 74

CY7C68013A/CY7C68014A

CY7C68015A/CY7C68016A

Table 12. FX2LP Register Summary (continued)

Hex Size

Name

Description

b7

b6

b5

b4

b3

b2

b1

b0

Default Access

00000000 R

[25]

BA

1

EP01STAT

Endpoint 0&1 Status

0

EP1INBSY EP1OUTBSY EP0BSY

[25, 26]

BB

GPIFTRIG

Endpoint 2,4,6,8 GPIF

slave FIFO Trigger

DONE

RW

EP1

D9

EP0

D8

10000xxx brrrrbbb

BC

BD

1

reserved

[25]

GPIFSGLDATH

GPIF Data H (16-bit mode D15

only)

D14

D13

D12

D11

D10

xxxxxxxx RW

[25]

BE

BF

1

GPIFSGLDATLX

GPIFSGLDATL-

GPIF Data L w/ Trigger

D7

D6

D5

D4

D3

D2

D1

D0

GPIF Data L w/ No Trigger D7

xxxxxxxx R

[25]

NOX

[25]

C0

1

SCON1

Serial Port 1 Control (bit SM0_1

addressable)

SM1_1

D6

SM2_1

D5

REN_1

D4

TB8_1

D3

RB8_1

D2

TI_1

D1

RI_1

D0

00000000 RW

[25]

C1

C2

C8

1

6

1

SBUF1

Serial Port 1 Data Buffer D7

reserved

T2CON

Timer/Counter 2 Control TF2

(bit addressable)

EXF2

RCLK

TCLK

EXEN2

TR2

CT2

CPRL2

00000000 RW

C9

CA

1

reserved

RCAP2L

Capture for Timer 2, au- D7

to-reload, up-counter

D6

D5

D4

D3

D2

D1

D0

00000000 RW

CB

1

RCAP2H

Capture for Timer 2, au- D7

to-reload, up-counter

CC

CD

CE

D0

1

2

1

TL2

Timer 2 reload L

Timer 2 reload H

D7

D6

D5

D4

D3

D2

D1

D9

D0

D8

00000000 RW

TH2

D15

D14

D13

D12

D11

D10

reserved

PSW

Program Status Word (bit CY

addressable)

AC

F0

RS1

RS0

OV

F1

P

00000000 RW

D1

D8

D9

E0

7

1

7

1

reserved

[25]

EICON

External Interrupt Control SMOD1

1

ERESI

D5

RESI

D4

INT6

D3

0

01000000 RW

00000000 RW

reserved

ACC

Accumulator (bit address- D7

able)

D6

D2

D1

D0

E1

E8

7

1

reserved

[25]

EIE

External Interrupt En-

able(s)

1

EX6

EX5

EX4

EI²C

EUSB

11100000 RW

E9

F0

F1

F8

7

1

7

1

reserved

B

B (bit addressable)

D7

1

D6

1

D5

1

D4

D3

D2

D1

D0

00000000 RW

11100000 RW

reserved

[25]

EIP

External Interrupt Priority

Control

PX6

PX5

PX4

PI²C

PUSB

F9

7

reserved

R = all bits read-only

W = all bits write-only

r = read-only bit

w = write-only bit

b = both read/write bit

Notes

25. SFRs not part of the standard 8051 architecture.

26. Read and writes to these registers may require synchronization delay; see Technical Reference Manual for “Synchronization Delay”.

Document Number: 38-08032 Rev. AD

Page 40 of 74

CY7C68013A/CY7C68014A

CY7C68015A/CY7C68016A

Absolute Maximum Ratings

Operating Conditions

Exceeding maximum ratings may shorten the useful life of the

device. User guidelines are not tested.

T_A(ambient temperature under bias)

Commercial ................................................... 0 °C to +70 °C

Storage temperature ................................ –65 °C to +150 °C

T_A(ambient temperature under bias)

Industrial .................................................. –40 °C to +105 °C

Ambient temperature with

power supplied (Commercial)......................... 0 °C to +70 °C

Supply voltage .........................................+3.00 V to +3.60 V

Ground voltage ................................................................ 0 V

Ambient temperature with

power supplied (Industrial) ...................... –40 °C to +105 °C

F_OSC(oscillator or crystal frequency) .... 24 MHz ± 100 ppm,

Supply voltage to ground potential ..............–0.5 V to +4.0 V

DC input voltage to any input pin^[27]........................... 5.25 V

parallel resonant

DC voltage applied to outputs

in high Z state .................................... –0.5 V to V_CC+ 0.5 V

Power dissipation .................................................... 300 mW

Static discharge voltage ..........................................>2000 V

Max output current, per I/O port ................................. 10 mA

Max output current, all five I/O ports

(128-pin and 100-pin packages) ................................. 50 mA

Thermal Characteristics

Maximum junction temperature ................................. 125 °C

The following table displays the thermal characteristics of various packages:

Table 13. Thermal Characteristics

Jc

Ja

Package

56 SSOP

Ambient Temperature (°C)

Junction to Case

Junction to Ambient Thermal

Resistance (°C/W)

Thermal Resistance (°C/W)

70

24.4

11.9

15.5

10.6

30.9

47.7

45.9

43.2

25.2

58.6

100 TQFP

128 TQFP

56 QFN

56 VFBGA

The junction temperature _j, can be calculated using the following equation: _j= P*_Ja+ _a

Where,

P = Power

_Ja= Junction to ambient temperature (_Jc+ _Ca

)

_a= Ambient temperature (70 °C)

The case temperature _c, can be calculated using the following equation: _c= P*_Ca+ _a

where,

P = Power

_Ca= Case to ambient temperature

_a= Ambient temperature (70 °C)

Note

27. Do not power I/O with the chip power OFF.

Document Number: 38-08032 Rev. AD

Page 41 of 74

CY7C68013A/CY7C68014A

CY7C68015A/CY7C68016A

DC Electrical Characteristics

Table 14. DC Characteristics

Parameter

VCC

VCC Ramp Up 0 to 3.3 V

Description

Conditions

Min

3.00

200

2

Typ

3.3

–

Max

3.60

–

Unit

V

Supply voltage

–

s

V

V_IH

V_IL

Input HIGH voltage

Input LOW voltage

–

5.25

0.8

5.25

0.8

±10

–

–0.5

2

–

V

V_{IH_X}

V_{IL_X}

I_I

Crystal input HIGH voltage

Crystal input LOW voltage

Input leakage current

Output voltage HIGH

Output LOW voltage

Output current HIGH

Output current LOW

–

V

–

–0.5

–

V

0< V_IN< V_CC

I_OUT= 4 mA

I_OUT= –4 mA

–

A

V

V_OH

V_OL

I_OH

I_OL

2.4

–

0.4

4

V

–

mA

pF

A

mA

ms

s

–

4

Except D+/D–

D+/D–

–

10

C_IN

Input pin capacitance

–

15

Suspend current

Connected

Disconnected

Connected

Disconnected

–

300

100

0.5

0.3

50

35

–

380^[28]

150^[28]

1.2^[28]

1.0^[28]

85

CY7C68014/CY7C68016

Suspend current

–

I_SUSP

–

CY7C68013/CY7C68015

–

8051 running, connected to USB HS

8051 running, connected to USB FS

–

I_CC

Supply current

–

65

Reset time after valid power

Pin reset after powered on

5.0

200

–

T_RESET

V_CCmin = 3.0 V

–

USB Transceiver

USB 2.0 compliant in Full Speed and Hi-Speed modes.

Note

28. Measured at Max V , 25 °C.

CC

Document Number: 38-08032 Rev. AD

Page 42 of 74

CY7C68013A/CY7C68014A

CY7C68015A/CY7C68016A

AC Electrical Characteristics

USB Transceiver

USB 2.0 compliant in Full-Speed and Hi-Speed modes.

Program Memory Read

Figure 12. Program Memory Read Timing Diagram

t

CL

CLKOUT^[29]

t

AV

A[15..0]

t

STBH

STBL

PSEN#

D[7..0]

[30]

ACC1

t

DH

t

data in

t

SOEL

OE#

CS#

t

SCSL

Table 15. Program Memory Read Parameters

Parameter Description

Min

–

Typ

Max

–

Unit

ns

Notes

20.83

48 MHz

t_CL

t_AV

1/CLKOUT frequency

–

41.66

–

24 MHz

–

83.2

–

12 MHz

Delay from clock to valid address

Clock to PSEN LOW

Clock to PSEN HIGH

Clock to OE LOW

0

10.7

8

–

t_STBL

t_STBH

t_SOEL

t_SCSL

t_DSU

t_DH

0

–

0

–

8

–

11.1

13

–

Clock to CS LOW

–

Data setup to clock

Data hold time

9.6

0

–

Notes

29. CLKOUT is shown with positive polarity.

30. t

is computed from these parameters as follows:

ACC1

t

(24 MHz) = 3*t – t – t

= 106 ns.

= 43 ns.

CL

AV

DSU

(48 MHz) = 3*t – t – t

CL

AV

Document Number: 38-08032 Rev. AD

Page 43 of 74

CY7C68013A/CY7C68014A

CY7C68015A/CY7C68016A

Data Memory Read^[31]

Figure 13. Data Memory Read Timing Diagram

t

CL

Stretch = 0

CLKOUT^[29]

t

AV

A[15..0]

t

STBH

STBL

RD#

t

SCSL

CS#

OE#

t

SOEL

t

DSU

[32]

t

DH

t

ACC2

D[7..0]

data in

Stretch = 1

t

CL

CLKOUT^[29]

t

AV

A[15..0]

RD#

CS#

t

DSU

t

DH

_ACC3[32]

t

D[7..0]

data in

Table 16. Data Memory Read Parameters

Parameter Description

1/CLKOUT frequency

Min

Typ

Max

–

Unit

ns

Notes

t_CL

–

20.83

48 MHz

41.66

–

24 MHz

–

83.2

–

12 MHz

t_AV

Delay from clock to valid address

Clock to RD LOW

–

10.7

11

13

11.1

–

t_STBL

t_STBH

t_SCSL

t_SOEL

t_DSU

t_DH

–

Clock to RD HIGH

Clock to CS LOW

–

Clock to OE LOW

–

Data setup to clock

Data hold time

9.6

0

–

When using the AUTPOPTR1 or AUTOPTR2 to address external memory, the address of AUTOPTR1 is only active while either RD#

or WR# is active. The address of AUTOPTR2 is active throughout the cycle and meets the address valid time for which is based on

the stretch value.

Notes

31. The stretch memory cycle feature enables EZ-USB firmware to adjust the speed of data memory accesses not the program memory accesses. Details including typical

strobe width timings can be found in the section 12.1.2 of the Technical Reference Manual. The address cycle width can be interpreted from these.

32. t

and t

are computed from these parameters as follows:

ACC3

ACC2

ACC3

t

(24 MHz) = 3*t – t –t

= 106 ns

(48 MHz) = 3*t – t – t = 43 ns

DSU

CL

AV DSU

CL

AV

(24 MHz) = 5*t – t –t = 190 ns

(48 MHz) = 5*t – t – t = 86 ns.

DSU

CL

AV DSU

CL

AV

Document Number: 38-08032 Rev. AD

Page 44 of 74

CY7C68013A/CY7C68014A

CY7C68015A/CY7C68016A

[33]

Data Memory Write

Figure 14. Data Memory Write Timing Diagram

t

CL

CLKOUT

A[15..0]

t

AV

t

STBL

STBH

AV

WR#

CS#

t

SCSL

t

ON1

t

OFF1

data out

D[7..0]

Stretch = 1

t

CL

CLKOUT

A[15..0]

t

AV

WR#

CS#

t

ON1

t

OFF1

data out

D[7..0]

Table 17. Data Memory Write Parameters

Parameter Description

Delay from clock to valid address

Min

Max

10.7

11.2

13.0

13.1

Unit

ns

Notes

t_AV

0

–

0

–

t_STBL

t_STBH

t_SCSL

t_ON1

Clock to WR pulse LOW

Clock to WR pulse HIGH

Clock to CS pulse LOW

Clock to data turn-on

ns

t_OFF1

Clock to data hold time

ns

When using the AUTPOPTR1 or AUTOPTR2 to address external memory, the address of AUTOPTR1 is only active while either RD#

or WR# are active. The address of AUTOPTR2 is active throughout the cycle and meets the address valid time for which is based on

the stretch value.

Note

33. The stretch memory cycle feature enables EZ-USB firmware to adjust the speed of data memory accesses not the program memory accesses. Details including

typical strobe width timings can be found in the section 12.1.2 of the Technical Reference Manual. The address cycle width can be interpreted from these.

Document Number: 38-08032 Rev. AD

Page 45 of 74

CY7C68013A/CY7C68014A

CY7C68015A/CY7C68016A

The RD# signal prompts the external logic to prepare the next

data byte. Nothing gets sampled internally on assertion of the

RD# signal itself; it is just a prefetch type signal to get the next

data byte prepared. So, using it with that in mind easily meets the

setup time to the next read.

PORTC Strobe Feature Timings

The RD# and WR# are present in the 100-pin version and the

128-pin package. In these 100-pin and 128-pin versions, an

8051 control bit can be set to pulse the RD# and WR# pins when

the 8051 reads from or writes to PORTC. This feature is enabled

by setting PORTCSTB bit in CPUCS register.

The purpose of this pulsing of RD# is to allow the external

peripheral to know that the 8051 is done reading PORTC and the

data was latched into PORTC three CLKOUT cycles before

asserting the RD# signal. After the RD# is pulsed, the external

logic can update the data on PORTC.

The RD# and WR# strobes are asserted for two CLKOUT cycles

when PORTC is accessed.

The WR# strobe is asserted two clock cycles after PORTC is

updated and is active for two clock cycles after that, as shown in

Figure 16.

Following is the timing diagram of the read and write strobing

function on accessing PORTC. Refer to Data Memory Read^[31]

on page 44 and Data Memory Write^[33]on page 45 for details on

propagation delay of RD# and WR# signals.

As for read, the value of PORTC three clock cycles before the

assertion of RD# is the value that the 8051 reads in. The RD# is

pulsed for two clock cycles after three clock cycles from the point

when the 8051 has performed a read function on PORTC.

Figure 16. WR# Strobe Function when PORTC is Accessed by 8051

t

CLKOUT

PORTC IS UPDATED

WR#

t

STBL

STBH

Figure 17. RD# Strobe Function when PORTC is Accessed by 8051

t

CLKOUT

8051 READS PORTC

RD#

DATA CAN BE UPDATED BY EXTERNAL LOGIC

DATA MUST BE HELD FOR 3 CLK CYLCES

t

STBL

STBH

Document Number: 38-08032 Rev. AD

Page 46 of 74

CY7C68013A/CY7C68014A

CY7C68015A/CY7C68016A

GPIF Synchronous Signals

Figure 18. GPIF Synchronous Signals Timing Diagram^[34]

t

IFCLK

t

SGA

GPIFADR[8:0]

RDY

X

t

SRY

t

RYH

DATA(input)

valid

t

SGD

t

DAH

CTL_X

t

XCTL

DATA(output)

N

N+1

t

XGD

Table 18. GPIF Synchronous Signals Parameters with Internally Sourced IFCLK^{[34, 35]}

Typ

Parameter

t_IFCLK

Description

Min

Max

Unit

Min

–

Max

–

IFCLK Period

20.83

–

ns

ps

%

t_SRY

RDY_Xto clock setup time

RDY_XHold Time

8.9

0

–

t_RYH

–

t_SGD

GPIF data to clock setup time

GPIF data hold time

9.2

0

–

t_DAH

–

t_SGA

Clock to GPIF address propagation delay

Clock to GPIF data output propagation delay

Clock to CTL_Xoutput propagation delay

IFCLK rise time

–

7.5

10

6.7

–

t_XGD

–

t_XCTL

t_IFCLKR

t_IFCLKF

t_IFCLKOD

t_IFCLKJ

–

900

51

300

IFCLK fall time

–

IFCLK output duty cycle

–

49

–

IFCLK jitter peak to peak

–

ps

Table 19. GPIF Synchronous Signals Parameters with Externally Sourced IFCLK^[35]

Parameter Description

t_IFCLK

Min

Max

200

–

Unit

ns

IFCLK period^[36]

20.83

2.9

3.7

3.2

4.5

–

t_SRY

t_RYH

t_SGD

t_DAH

t_SGA

t_XGD

t_XCTL

RDY_Xto clock setup time

RDY_XHold Time

–

GPIF data to clock setup time

–

GPIF data hold time

–

Clock to GPIF address propagation delay

Clock to GPIF data output propagation delay

Clock to CTL_Xoutput propagation delay

11.5

15

10.7

–

Notes

34. Dashed lines denote signals with programmable polarity.

35. GPIF asynchronous RDY signals have a minimum setup time of 50 ns when using the internal 48-MHz IFCLK.

x

36. IFCLK must not exceed 48 MHz.

Document Number: 38-08032 Rev. AD

Page 47 of 74

CY7C68013A/CY7C68014A

CY7C68015A/CY7C68016A

Slave FIFO Synchronous Read

Figure 19. Slave FIFO Synchronous Read Timing Diagram ^[37]

t

IFCLK

SLRD

t

RDH

t

SRD

t

XFLG

FLAGS

DATA

N+1

N

t

XFD

OEon

t

OEoff

SLOE

Table 20. Slave FIFO Synchronous Read Parameters with Internally Sourced IFCLK^[38]

Typ

Parameter

t_IFCLK

Description

Min

Max

Unit

Min

–

Max

–

IFCLK period

20.83

–

ns

ps

%

t_SRD

SLRD to clock setup time

18.7

0

–

t_RDH

Clock to SLRD hold time

–

t_OEon

SLOE turn on to FIFO data valid

SLOE turn off to FIFO data hold

Clock to FLAGS output propagation delay

Clock to FIFO data output propagation delay

IFCLK rise time

–

10.5

9.5

11

–

t_OEoff

–

t_XFLG

t_XFD

–

t_IFCLKR

t_IFCLKF

t_IFCLKOD

t_IFCLKJ

–

900

51

300

IFCLK fall time

–

IFCLK output duty cycle

–

49

–

IFCLK jitter peak to peak

–

ps

Table 21. Slave FIFO Synchronous Read Parameters with Externally Sourced IFCLK^[38]

Parameter

t_IFCLK

Description

Min

20.83

12.7

3.7

–

Max

200

–

Unit

ns

IFCLK period

t_SRD

t_RDH

t_OEon

t_OEoff

t_XFLG

t_XFD

SLRD to clock setup time

ns

Clock to SLRD hold time

–

ns

SLOE turn on to FIFO data valid

SLOE turn off to FIFO data hold

Clock to FLAGS output propagation delay

Clock to FIFO data output propagation delay

10.5

13.5

15

ns

–

ns

–

ns

–

ns

Notes

37. Dashed lines denote signals with programmable polarity.

38. GPIF asynchronous RDY signals have a minimum setup time of 50 ns when using the internal 48-MHz IFCLK.

x

Document Number: 38-08032 Rev. AD

Page 48 of 74

CY7C68013A/CY7C68014A

CY7C68015A/CY7C68016A

Slave FIFO Asynchronous Read

Figure 20. Slave FIFO Asynchronous Read Timing Diagram ^[39]

t

RDpwh

SLRD

t

RDpwl

t

XFLG

t

FLAGS

XFD

DATA

SLOE

N+1

N

t

OEoff

OEon

Table 22. Slave FIFO Asynchronous Read Parameters^[40]

Parameter Description

t_RDpwl

Min

50

–

Max

–

Unit

ns

SLRD pulse width LOW

SLRD pulse width HIGH

t_RDpwh

t_XFLG

t_XFD

–

ns

SLRD to FLAGS output propagation delay

SLRD to FIFO data output propagation delay

SLOE turn-on to FIFO data valid

70

ns

–

15

ns

t_OEon

t_OEoff

–

10.5

ns

SLOE turn-off to FIFO data hold

–

ns

Notes

39. Dashed lines denote signals with programmable polarity.

40. Slave FIFO asynchronous parameter values use internal IFCLK setting at 48 MHz.

Document Number: 38-08032 Rev. AD

Page 49 of 74

CY7C68013A/CY7C68014A

CY7C68015A/CY7C68016A

Slave FIFO Synchronous Write

Figure 21. Slave FIFO Synchronous Write Timing Diagram ^[41]

t

IFCLK

SLWR

t

WRH

t

SWR

DATA

N

Z

t

FDH

SFD

FLAGS

t

XFLG

Table 23. Slave FIFO Synchronous Write Parameters with Internally Sourced IFCLK^[42]

Parameter

t_IFCLK

Description

Min

20.83

10.4

0

Max

–

Unit

ns

IFCLK period

t_SWR

t_WRH

t_SFD

SLWR to clock setup time

–

ns

Clock to SLWR hold time

–

ns

FIFO data to clock setup time

Clock to FIFO data hold time

Clock to FLAGS output propagation time

9.2

0

–

ns

t_FDH

t_XFLG

–

ns

–

9.5

ns

Table 24. Slave FIFO Synchronous Write Parameters with Externally Sourced IFCLK^[42]

Parameter

t_IFCLK

Description

Min

20.83

12.1

3.6

Max

200

–

Unit

ns

IFCLK Period

t_SWR

t_WRH

t_SFD

SLWR to clock setup time

ns

Clock to SLWR hold time

–

ns

FIFO data to clock setup time

Clock to FIFO data hold time

Clock to FLAGS output propagation time

3.2

–

ns

t_FDH

t_XFLG

4.5

–

ns

–

13.5

ns

Notes

41. Dashed lines denote signals with programmable polarity.

42. GPIF asynchronous RDY signals have a minimum setup time of 50 ns when using the internal 48-MHz IFCLK.

x

Document Number: 38-08032 Rev. AD

Page 50 of 74

CY7C68013A/CY7C68014A

CY7C68015A/CY7C68016A

Slave FIFO Asynchronous Write

Figure 22. Slave FIFO Asynchronous Write Timing Diagram ^[43]

t

WRpwh

SLWR

SLWR/SLCS#

t

WRpwl

t

FDH

SFD

DATA

t

XFD

FLAGS

Table 25. Slave FIFO Asynchronous Write Parameters with Internally Sourced IFCLK^[44]

Parameter

t_WRpwl

t_WRpwh

t_SFD

Description

Min

50

70

10

–

Max

–

Unit

ns

SLWR pulse LOW

SLWR pulse HIGH

–

ns

SLWR to FIFO DATA setup time

FIFO DATA to SLWR hold time

–

ns

t_FDH

–

ns

t_XFD

SLWR to FLAGS output propagation delay

70

ns

Notes

43. Dashed lines denote signals with programmable polarity.

44. Slave FIFO asynchronous parameter values use internal IFCLK setting at 48 MHz.

Document Number: 38-08032 Rev. AD

Page 51 of 74

CY7C68013A/CY7C68014A

CY7C68015A/CY7C68016A

Slave FIFO Synchronous Packet End Strobe

Figure 23. Slave FIFO Synchronous Packet End Strobe Timing Diagram ^[45]

IFCLK

t

PEH

PKTEND

FLAGS

t

SPE

t

XFLG

Table 26. Slave FIFO Synchronous Packet End Strobe Parameters with Internally Sourced IFCLK^[46]

Parameter

t_IFCLK

Description

Min

20.83

14.6

0

Max

–

Unit

ns

IFCLK period

t_SPE

t_PEH

t_XFLG

PKTEND to clock setup time

–

ns

Clock to PKTEND hold time

–

ns

Clock to FLAGS output propagation delay

–

9.5

ns

Table 27. Slave FIFO Synchronous Packet End Strobe Parameters with Externally Sourced IFCLK^[46]

Parameter

t_IFCLK

Description

Min

20.83

8.6

Max

200

–

Unit

ns

IFCLK period

t_SPE

t_PEH

t_XFLG

PKTEND to clock setup time

ns

Clock to PKTEND hold time

2.5

–

ns

Clock to FLAGS output propagation delay

–

13.5

ns

Notes

45. Dashed lines denote signals with programmable polarity.

46. GPIF asynchronous RDY signals have a minimum setup time of 50 ns when using the internal 48-MHz IFCLK.

x

Document Number: 38-08032 Rev. AD

Page 52 of 74

CY7C68013A/CY7C68014A

CY7C68015A/CY7C68016A

There is no specific timing requirement that should be met for

asserting the PKTEND pin to asserting SLWR. PKTEND can be

asserted with the last data value clocked into the FIFOs or

thereafter. The setup time t_SPEand the hold time t_PEHmust be

met.

caused the last byte or word to be clocked into the previous auto

committed packet. Figure 24 shows this scenario. X is the value

the AUTOINLEN register is set to when the IN endpoint is

configured to be in auto mode.

Figure 24 shows a scenario where two packets are committed.

The first packet gets committed automatically when the number

of bytes in the FIFO reaches X (value set in AUTOINLEN

register) and the second one byte/word short packet being

committed manually using PKTEND.

Although there are no specific timing requirements for PKTEND

assertion, there is a specific corner-case condition that needs

attention while using the PKTEND pin to commit a one byte or

word packet. There is an additional timing requirement that

needs to be met when the FIFO is configured to operate in auto

mode and it is required to send two packets back to back: a full

packet (full defined as the number of bytes in the FIFO meeting

the level set in AUTOINLEN register) committed automatically

followed by a short one byte or word packet committed manually

using the PKTEND pin. In this scenario, the user must ensure to

assert PKTEND, at least one clock cycle after the rising edge that

Note that there is at least one IFCLK cycle timing between the

assertion of PKTEND and clocking of the last byte of the previous

packet (causing the packet to be committed automatically).

Failing to adhere to this timing results in the FX2 failing to send

the one byte or word short packet.

Figure 24. Slave FIFO Synchronous Write Sequence and Timing Diagram^[47]

t

IFCLK

t

SFA

FAH

FIFOADR

>= t

WRH

>= t

SWR

SLWR

DATA

t

FDH

t

FDH

t

SFD

t

SFD

FDH

t

SFD

t

SFD

FDH

SFD

FDH

X-4

X-2

X-1

1

X-3

X

At least one IFCLK cycle

t

SPE

t

PEH

PKTEND

Note

47. Dashed lines denote signals with programmable polarity.

Document Number: 38-08032 Rev. AD

Page 53 of 74

CY7C68013A/CY7C68014A

CY7C68015A/CY7C68016A

Slave FIFO Asynchronous Packet End Strobe

Figure 25. Slave FIFO Asynchronous Packet End Strobe Timing Diagram^[48]

t

PEpwh

PKTEND

FLAGS

t

PEpwl

t

XFLG

Table 28. Slave FIFO Asynchronous Packet End Strobe Parameters^[49]

Parameter Description

t_PEpwlPKTEND pulse width LOW

t_PWpwh

t_XFLG

Min

50

–

Max

–

Unit

ns

PKTEND pulse width HIGH

–

ns

PKTEND to FLAGS output propagation delay

115

ns

Slave FIFO Output Enable

Figure 26. Slave FIFO Output Enable Timing Diagram^[48]

SLOE

t

OEoff

t

OEon

DATA

Table 29. Slave FIFO Output Enable Parameters

Parameter Description

t_OEon

t_OEoff

Min

–

Max

10.5

Unit

ns

SLOE assert to FIFO DATA output

SLOE deassert to FIFO DATA hold

–

ns

Slave FIFO Address to Flags/Data

Figure 27. Slave FIFO Address to Flags/Data Timing Diagram^[48]

FIFOADR [1.0]

t

XFLG

FLAGS

DATA

t

XFD

N

N+1

Table 30. Slave FIFO Address to Flags/Data Parameters

Parameter

t_XFLG

Description

FIFOADR[1:0] to FLAGS output propagation delay

FIFOADR[1:0] to FIFODATA output propagation delay

Min

–

Max

10.7

14.3

Unit

ns

t_XFD

–

ns

Notes

48. Dashed lines denote signals with programmable polarity.

49. Slave FIFO asynchronous parameter values use internal IFCLK setting at 48 MHz.

Document Number: 38-08032 Rev. AD

Page 54 of 74

CY7C68013A/CY7C68014A

CY7C68015A/CY7C68016A

Slave FIFO Synchronous Address

Figure 28. Slave FIFO Synchronous Address Timing Diagram^[50]

IFCLK

SLCS/FIFOADR [1:0]

t

FAH

SFA

Table 31. Slave FIFO Synchronous Address Parameters^[51]

Parameter

t_IFCLK

t_SFA

t_FAH

Description

Min

20.83

25

Max

200

–

Unit

ns

Interface clock period

FIFOADR[1:0] to clock setup time

Clock to FIFOADR[1:0] hold time

ns

10

–

ns

Slave FIFO Asynchronous Address

Figure 29. Slave FIFO Asynchronous Address Timing Diagram ^[50]

SLCS/FIFOADR [1:0]

t

FAH

t

SFA

SLRD/SLWR/PKTEND

Table 32. Slave FIFO Asynchronous Address Parameters^[52]

Parameter

Description

Min

10

Max

–

Unit

ns

t_SFA

t_FAH

FIFOADR[1:0] to SLRD/SLWR/PKTEND setup time

RD/WR/PKTEND to FIFOADR[1:0] hold time

10

–

ns

Notes

50. Dashed lines denote signals with programmable polarity.

51. GPIF asynchronous RDY signals have a minimum setup time of 50 ns when using the internal 48-MHz IFCLK.

x

52. Slave FIFO asynchronous parameter values use internal IFCLK setting at 48 MHz.

Document Number: 38-08032 Rev. AD

Page 55 of 74

CY7C68013A/CY7C68014A

CY7C68015A/CY7C68016A

Sequence Diagram

Single and Burst Synchronous Read Example

Figure 30. Slave FIFO Synchronous Read Sequence and Timing Diagram^[53]

t

IFCLK

t

SFA

t

FAH

FIFOADR

t=0

T=0

t

>= t

SRD

>= t

RDH

SRD

SLRD

SLCS

t=3

t=2

T=3

T=2

t

XFLG

FLAGS

DATA

SLOE

t

XFD

t

XFD

N+4

Data Driven: N

N+2

N+3

N+1

t

OEon

t

OEoff

t

OEoff

OEon

t=4

T=4

T=1

t=1

Figure 31. Slave FIFO Synchronous Sequence of Events Diagram

IFCLK

N

IFCLK

N+1

IFCLK

N+1

IFCLK

N+1

IFCLK

N+2

IFCLK

N+3

IFCLK

N+4

IFCLK

N+4

IFCLK

N+4

N

FIFO POINTER

SLOE

SLRD

SLOE

SLRD

SLOE

SLRD

SLOE

FIFO DATA BUS Not Driven

Driven: N

N+1

Not Driven

N+1

N+2

N+3

N+4

Not Driven

Figure 30 shows the timing relationship of the SLAVE FIFO

signals during a synchronous FIFO read using IFCLK as the

synchronizing clock. The diagram illustrates a single read

followed by a burst read.

asserted (The SLCS and SLRD signals must both be asserted

to start a valid read condition).

■ The FIFO pointer is updated on the rising edge of the IFCLK,

while SLRD is asserted. This starts the propagation of data

from the newly addressed location to the data bus. After a

propagation delay of t_XFD(measured from the rising edge of

IFCLK) the new data value is present. N is the first data value

read from the FIFO. To have data on the FIFO data bus, SLOE

MUST also be asserted.

■ At t = 0, the FIFO address is stable and the signal SLCS is

asserted (SLCS may be tied LOW in some applications). Note

that t_SFAhas a minimum of 25 ns. This means that when IFCLK

is running at 48 MHz, the FIFO address setup time is more than

one IFCLK cycle.

The same sequence of events are shown for a burst read and

are marked with the time indicators of T = 0 through 5.

■ At t = 1, SLOE is asserted. SLOE is an output enable only,

whose sole function is to drive the data bus. The data that is

driven on the bus is the data that the internal FIFO pointer is

currently pointing to. In this example it is the first data value in

the FIFO. Note: the data is prefetched and is driven on the bus

when SLOE is asserted.

Note For the burst mode, the SLRD and SLOE are left asserted

during the entire duration of the read. In the burst read mode,

when SLOE is asserted, data indexed by the FIFO pointer is on

the data bus. During the first read cycle, on the rising edge of the

clock, the FIFO pointer is updated and incremented to point to

address N+1. For each subsequent rising edge of IFCLK, while

the SLRD is asserted, the FIFO pointer is incremented and the

next data value is placed on the data bus.

■ At t = 2, SLRD is asserted. SLRD must meet the setup time of

t_SRD(time from asserting the SLRD signal to the rising edge of

the IFCLK) and maintain a minimum hold time of t_RDH(time

from the IFCLK edge to the deassertion of the SLRD signal).

If the SLCS signal is used, it must be asserted before SLRD is

Note

53. Dashed lines denote signals with programmable polarity.

Document Number: 38-08032 Rev. AD

Page 56 of 74

CY7C68013A/CY7C68014A

CY7C68015A/CY7C68016A

Single and Burst Synchronous Write

Figure 32. Slave FIFO Synchronous Write Sequence and Timing Diagram^[54]

t

IFCLK

t

SFA

t

SFA

t

FAH

FIFOADR

>= t

t=0

WRH

t

>= t

T=0

SWR

WRH

SWR

SLWR

SLCS

T=2

T=5

t=2

t=3

t

XFLG

t

XFLG

FLAGS

DATA

t

FDH

t

SFD

FDH

SFD

FDH

N+1

N+3

N

N+2

T=4

T=3

t=1

T=1

t

SPE

t

PEH

PKTEND

Figure 32 shows the timing relationship of the SLAVE FIFO

signals during a synchronous write using IFCLK as the

synchronizing clock. The diagram illustrates a single write

followed by burst write of three bytes and committing all four

bytes as a short packet using the PKTEND pin.

FIFO data bus is written to the FIFO on every rising edge of

IFCLK. The FIFO pointer is updated on each rising edge of

IFCLK. In Figure 32, after the four bytes are written to the FIFO,

SLWR is deasserted. The short 4 byte packet can be committed

to the host by asserting the PKTEND signal.

There is no specific timing requirement that should be met for

asserting PKTEND signal with regards to asserting the SLWR

signal. PKTEND can be asserted with the last data value or

thereafter. The only requirement is that the setup time t_SPEand

the hold time t_PEHmust be met. In the scenario of Figure 32, the

number of data values committed includes the last value written

to the FIFO. In this example, both the data value and the

PKTEND signal are clocked on the same rising edge of IFCLK.

PKTEND can also be asserted in subsequent clock cycles. The

FIFOADDR lines should be held constant during the PKTEND

assertion.

■ At t = 0 the FIFO address is stable and the signal SLCS is

asserted. (SLCS may be tied LOW in some applications) Note

that t_SFAhas a minimum of 25 ns. This means when IFCLK is

running at 48 MHz, the FIFO address setup time is more than

one IFCLK cycle.

■ At t = 1, the external master/peripheral must outputs the data

value onto the data bus with a minimum set up time of t_SFD

before the rising edge of IFCLK.

■ At t = 2, SLWR is asserted. The SLWR must meet the setup

time of t_SWR(time from asserting the SLWR signal to the rising

edge of IFCLK) and maintain a minimumhold time of t_WRH(time

from the IFCLK edge to the deassertion of the SLWR signal).

If the SLCS signal is used, it must be asserted with SLWR or

before SLWR is asserted (The SLCS and SLWR signals must

both be asserted to start a valid write condition).

Although there are no specific timing requirement for the

PKTEND assertion, there is a specific corner-case condition that

needs attention while using the PKTEND to commit a one

byte/word packet. Additional timing requirements exist when the

FIFO is configured to operate in auto mode and it is desired to

send two packets: a full packet (‘full’ defined as the number of

bytes in the FIFO meeting the level set in the AUTOINLEN

register) committed automatically followed by a short one byte or

word packet committed manually using the PKTEND pin.

■ While the SLWR is asserted, data is written to the FIFO and on

the rising edge of the IFCLK, the FIFO pointer is incremented.

The FIFO flag is also updated after a delay of t_XFLGfrom the

rising edge of the clock.

In this case, the external master must ensure to assert the

PKTEND pin at least one clock cycle after the rising edge that

caused the last byte or word that needs to be clocked into the

previous auto committed packet (the packet with the number of

bytes equal to what is set in the AUTOINLEN register). Refer to

Figure 24 on page 53 for further details on this timing.

The same sequence of events are also shown for a burst write

and are marked with the time indicators of T = 0 through 5.

Note For the burst mode, SLWR and SLCS are left asserted for

the entire duration of writing all the required data values. In this

burst write mode, after the SLWR is asserted, the data on the

Note

54. Dashed lines denote signals with programmable polarity.

Document Number: 38-08032 Rev. AD

Page 57 of 74

CY7C68013A/CY7C68014A

CY7C68015A/CY7C68016A

Sequence Diagram of a Single and Burst Asynchronous Read

Figure 33. Slave FIFO Asynchronous Read Sequence and Timing Diagram^[55]

t

FAH

SFA

FAH

FIFOADR

t=0

t

RDpwh

t

RDpwl

t

T=0

RDpwl

RDpwh

SLRD

SLCS

t=3

t=2

T=2

T=3

T=5

T=4

T=6

t

XFLG

t

XFLG

FLAGS

DATA

SLOE

t

XFD

t

XFD

t

XFD

Data (X)

Driven

N+3

N

N+1

N+2

N

t

OEon

t

OEoff

OEon

t=4

T=1

T=7

t=1

Figure 34. Slave FIFO Asynchronous Read Sequence of Events Diagram

SLOE

SLRD

SLOE

SLRD

N+1

SLRD

N+1

SLRD

N+2

SLRD

N+2

SLOE

FIFO POINTER

N

N+1

N

N+1

N+3

N+2

N+3

FIFO DATA BUS Not Driven

Driven: X

Not Driven

N

N+1

N+2

Not Driven

Figure 33 shows the timing relationship of the SLAVE FIFO

signals during an asynchronous FIFO read. It shows a single

read followed by a burst read.

■ The data that is driven, after asserting SLRD, is the updated

data from the FIFO. This data is valid after a propagation delay

of t_XFDfrom the activating edge of SLRD. In Figure 33, data N

is the first valid data read from the FIFO. For data to appear on

the data bus during the read cycle (SLRD is asserted), SLOE

must be in an asserted state. SLRD and SLOE can also be tied

together.

■ At t = 0, the FIFO address is stable and the SLCS signal is

asserted.

■ At t = 1, SLOE is asserted. This results in the data bus being

driven. The data that is driven on to the bus is the previous

data, the data that was in the FIFO from an earlier read cycle.

The same sequence of events is also shown for a burst read

marked with T = 0 through 5.

■ At t = 2, SLRD is asserted. The SLRD must meet the minimum

active pulse of t_RDpwland minimum de-active pulse width of

Note In the burst read mode, during SLOE is asserted, the data

bus is in a driven state and outputs the previous data. After SLRD

is asserted, the data from the FIFO is driven on the data bus

(SLOE must also be asserted) and then the FIFO pointer is

incremented.

t

_RDpwh. If SLCS is used, then SLCS must be asserted before

SLRD is asserted (The SLCS and SLRD signals must both be

asserted to start a valid read condition.)

Note

55. Dashed lines denote signals with programmable polarity.

Document Number: 38-08032 Rev. AD

Page 58 of 74

CY7C68013A/CY7C68014A

CY7C68015A/CY7C68016A

Sequence Diagram of a Single and Burst Asynchronous Write

Figure 35. Slave FIFO Asynchronous Write Sequence and Timing Diagram^[56]

t

FAH

t

SFA

FAH

FIFOADR

t=0

T=0

t

WRpwh

WRpwl

WRpwh

WRpwl

WRpwh

WRpwl

SLWR

SLCS

t =1

t=3

T=1

T=4

T=3

T=7

T=6

T=9

t

XFLG

t

XFLG

FLAGS

DATA

t

SFD

t

SFD FDH

FDH

N

N+1

N+2

N+3

t=2

T=8

T=2

T=5

t

PEpwl

PEpwh

PKTEND

Figure 35 shows the timing relationship of the SLAVE FIFO write

in an asynchronous mode. The diagram shows a single write

followed by a burst write of 3 bytes and committing the 4byte

short packet using PKTEND.

The FIFO flag is also updated after t_XFLGfrom the deasserting

edge of SLWR.

The same sequence of events is shown for a burst write and is

indicated by the timing marks of T = 0 through 5.

■ At t = 0 the FIFO address is applied, ensuring that it meets the

setup time of t_SFA. If SLCS is used, it must also be asserted

(SLCS may be tied LOW in some applications).

Note In the burst write mode, after SLWR is deasserted, the data

is written to the FIFO and then the FIFO pointer is incremented

to the next byte in the FIFO. The FIFO pointer is post

incremented.

■ At t = 1 SLWR is asserted. SLWR must meet the minimum

active pulse of t_WRpwland minimum de-active pulse width of

t_WRpwh. If the SLCS is used, it must be asserted with SLWR or

before SLWR is asserted.

In Figure 35, after the four bytes are written to the FIFO and

SLWR is deasserted, the short 4-byte packet can be committed

to the host using PKTEND. The external device should be

designed to not assert SLWR and the PKTEND signal at the

same time. It should be designed to assert the PKTEND after

SLWR is deasserted and met the minimum deasserted pulse

width. The FIFOADDR lines have to held constant during the

PKTEND assertion.

■ At t = 2, data must be present on the bus t_SFDbefore the

deasserting edge of SLWR.

■ At t = 3, deasserting SLWR causes the data to be written from

the data bus to the FIFO and then increments the FIFO pointer.

Note

56. Dashed lines denote signals with programmable polarity.

Document Number: 38-08032 Rev. AD

Page 59 of 74

CY7C68013A/CY7C68014A

CY7C68015A/CY7C68016A

Ordering Information

Table 33. Ordering Information

8051 Address

/Data Bus

Ordering Code

Package Type

RAM Size # Prog I/Os

Serial Debug^[57]

Ideal for Battery Powered Applications

CY7C68014A-128AXC

CY7C68014A-100AXC

CY7C68014A-56PVXC

CY7C68014A-56LTXC

CY7C68016A-56LTXC

CY7C68016A-56LTXCT

128 TQFP – Pb-free

100 TQFP – Pb-free

56 SSOP – Pb-free

56 QFN - Pb-free

16K

40

24

26

16-/8-bit

Y

N

–

Ideal for Non Battery Powered Applications

128 TQFP – Pb-free

CY7C68013A-128AXC

CY7C68013A-128AXI

CY7C68013A-100AXC

CY7C68013A-100AXI

CY7C68013A-56PVXC

CY7C68013A-56PVXCT

CY7C68013A-56PVXI

CY7C68013A-56BAXC

CY7C68013A-56BAXCT

CY7C68013A-56LTXC

CY7C68013A-56LTXCT

CY7C68013A-56LTXI

CY7C68015A-56LTXC

Development Tool Kit

CY3684

16K

40

24

26

16-/8-bit

Y

N

128 TQFP – Pb-free (Industrial)

100 TQFP – Pb-free

16-/8-bit

–

100 TQFP – Pb-free (Industrial)

56 SSOP – Pb-free

56 SSOP – Pb-free (Industrial)

56 VFBGA – Pb-free

56 QFN – Pb-free

56 QFN – Pb-free (Industrial)

56 QFN – Pb-free

EZ-USB FX2LP development kit

EZ-USB FX2LP Discovery Kit

CY3689

Reference Design Kit

CY4611B

USB 2.0 to ATA/ATAPI reference design using EZ-USB FX2LP

Ordering Code Definitions

(C, I)

(T)

C

68 XXXX

XXXXX

CY

7

-

Tape and Reel

Thermal Rating:

C = Commercial

I = Industrial

Package Type:

LTX = QFN (Saw Type) Pb-free

LFX = QFN (Punch Type) Pb-free

Part Number

Family Code: 68 = USB

Technology Code: C = CMOS

Marketing Code: 7 = Cypress Products

Company ID: CY = Cypress

Note

57. As UART is not available in the 56-pin package of CY7C68013A, serial port debugging using Keil Monitor is not possible.

Document Number: 38-08032 Rev. AD

Page 60 of 74

CY7C68013A/CY7C68014A

CY7C68015A/CY7C68016A

Package Diagrams

The FX2LP is available in five packages:

■ 56-pin SSOP

■ 56-pin QFN

■ 100-pin TQFP

■ 128-pin TQFP

■ 56-ball VFBGA

Figure 36. 56-pin SSOP (300 Mils) Package Outline, 51-85062

51-85062 *F

Document Number: 38-08032 Rev. AD

Page 61 of 74

CY7C68013A/CY7C68014A

CY7C68015A/CY7C68016A

Figure 37. 56-pin QFN ((8 × 8 × 1 mm) 4.5 × 5.2 E-Pad (Sawn)) Package Outline, 001-53450

001-53450 *E

Figure 38. 100-pin TQFP (14 × 20 × 1.4 mm) Package Outline, 51-85050

ș 2

ș1

ș

DIMENSIONS

MIN. NOM. MAX.

1.60

NOTE:

SYMBOL

1. ALL DIMENSIONS ARE IN MILLIMETERS.

2. BODY LENGTH DIMENSION DOES NOT

INCLUDE MOLD PROTRUSION/END FLASH.

MOLD PROTRUSION/END FLASH SHALL

A

0.05

0.15

A1

A2

D

1.35 1.40 1.45

15.80 16.00 16.20

13.90 14.00 14.10

21.80 22.00 22.20

19.90 20.00 20.10

NOT EXCEED 0.0098 in (0.25 mm) PER SIDE.

BODY LENGTH DIMENSIONS ARE MAX PLASTIC

D1

E

E1

BODY SIZE INCLUDING MOLD MISMATCH.

3. JEDEC SPECIFICATION NO. REF: MS-026.

0.08

0°

R

0.20

7°

1

R2

ș

ș 1

ș 2

c

0°

11° 12° 13°

0.20

0.22 0.30 0.38

0.45 0.60 0.75

1.00 REF

b

L

L1

L 2

L 3

e

0.25 BSC

0.20

51-85050 *G

0.65 TYP

Document Number: 38-08032 Rev. AD

Page 62 of 74

CY7C68013A/CY7C68014A

CY7C68015A/CY7C68016A

Figure 39. 128-pin TQFP (14 × 20 × 1.4 mm) Package Outline, 51-85101

51-85101 *F

Document Number: 38-08032 Rev. AD

Page 63 of 74

CY7C68013A/CY7C68014A

CY7C68015A/CY7C68016A

Figure 40. 56-ball VFBGA (5 × 5 × 1.0 mm) 0.50 Pitch, 0.30 Ball Package Outline, 001-03901

001-03901 *F

Document Number: 38-08032 Rev. AD

Page 64 of 74

CY7C68013A/CY7C68014A

CY7C68015A/CY7C68016A

■ Bypass and flyback caps on VBUS, near connector, are

recommended.

PCB Layout Recommendations

Follow these recommendations to ensure reliable

high-performance operation:^[58]

■ DPLUS and DMINUS trace lengths should be kept to within

2 mm of each other in length, with preferred length of 20 to

30 mm.

■ Four-layer, impedance-controlled boards are required to

maintain signal quality.

■ Maintain a solid ground plane under the DPLUS and DMINUS

traces. Do not allow the plane to split under these traces.

■ Specify impedance targets (ask your board vendor what they

can achieve).

■ Do not place vias on the DPLUS or DMINUS trace routing.

■ To control impedance, maintain trace widths and trace spacing.

■ Minimize stubs to minimize reflected signals.

■ Isolate the DPLUS and DMINUS traces from all other signal

traces by no less than 10 mm.

■ Connections between the USB connector shell and signal

ground must be near the USB connector.

Note

58. Source for recommendations: EZ-USB FX2™PCB Design Recommendations, http://www.cypress.com and High Speed USB Platform Design Guidelines,

http://www.usb.org/developers/docs/hs_usb_pdg_r1_0.pdf.

Document Number: 38-08032 Rev. AD

Page 65 of 74

CY7C68013A/CY7C68014A

CY7C68015A/CY7C68016A

Quad Flat Package No Leads (QFN) Package Design Notes

Electrical contact of the part to the PCB is made by soldering the

leads on the bottom surface of the package to the PCB.

Therefore, special attention is required to the heat transfer area

below the package to provide a good thermal bond to the circuit

board. Design a copper (Cu) fill in the PCB as a thermal pad

under the package. Heat is transferred from the FX2LP through

the device’s metal paddle on the bottom side of the package.

Heat from here is conducted to the PCB at the thermal pad. It is

then conducted from the thermal pad to the PCB inner ground

plane by a 5 × 5 array of via. A via is a plated-through hole in the

PCB with a finished diameter of 13 mil. The QFN’s metal die

paddle must be soldered to the PCB’s thermal pad. Solder mask

is placed on the board top side over each via to resist solder flow

into the via. The mask on the top side also minimizes outgassing

during the solder reflow process.

For further information on this package design, refer to

application notes for Surface Mount Assembly of Amkor's

MicroLeadFrame (MLF) Packages. You can find this on Amkor's

website http://www.amkor.com.

This application note provides detailed information about board

mounting guidelines, soldering flow, rework process, etc.

Figure 41 shows

a cross-sectional area underneath the

package. The cross section is of only one via. The solder paste

template should be designed to allow at least 50% solder

coverage. The thickness of the solder paste template should be

5 mil. Use the No Clean type 3 solder paste for mounting the part.

Nitrogen purge is recommended during reflow.

Figure 42 is a plot of the solder mask pattern and Figure 43

displays an X-Ray image of the assembly (darker areas indicate

solder).

Figure 41. Cross-section of the Area Underneath the QFN Package

0.017” dia

Solder Mask

Cu Fill

0.013” dia

PCB Material

Via hole for thermally connecting the

This figure only shows the top three layers of the

circuit board: Top Solder, PCB Dielectric, and

the Ground Plane

QFN to the circuit board ground plane.

Figure 42. Plot of the Solder Mask (White Area)

Figure 43. X-ray Image of the Assembly

Document Number: 38-08032 Rev. AD

Page 66 of 74

CY7C68013A/CY7C68014A

CY7C68015A/CY7C68016A

Acronyms

Document Conventions

Table 34. Acronyms Used in this Document

Units of Measure

Table 35. Units of Measure

Symbol

Acronym

ASIC

ATA

Description

application-specific integrated circuit

advanced technology attachment

device identifier

Unit of Measure

kHz

mA

kilohertz

milliamperes

DID

Mbps

MBPs

MHz

uA

megabits per second

megabytes per second

megahertz

DSL

digital service line

DSP

digital signal processor

ECC

error correction code

microamperes

volts

EEPROM electrically erasable programmable read only

memory

V

EPP

enhanced parallel port

first in first out

FIFO

GPIF

GPIO

I/O

general programmable interface

general purpose input output

input output

LAN

local area network

MPEG

PCMCIA

moving picture experts group

personal computer memory card international

association

PID

product identifier

PLL

phase locked loop

QFN

quad flat no leads

RAM

SIE

random access memory

serial interface engine

start of frame

SOF

SSOP

TQFP

USART

USB

super small outline package

thin quad flat pack

universal serial asynchronous receiver/transmitter

universal serial bus

UTOPIA

universal test and operations physical-layer

interface

VFBGA

VID

very fine ball grid array

vendor identifier

Document Number: 38-08032 Rev. AD

Page 67 of 74

CY7C68013A/CY7C68014A

CY7C68015A/CY7C68016A

Errata

This section describes the errata for the EZ-USB^®FX2LP™ CY7C68013A/14A/15A/16A Rev. B silicon. Details include errata trigger

conditions, scope of impact, available workaround, and silicon revision applicability.

Contact your local Cypress Sales Representative if you have questions.

Part Numbers Affected

Part Number

CY7C68013A

CY7C68014A

CY7C68015A

CY7C68016A

Package Type

Operating Range

Commercial

All

Commercial

CY7C68013A/14A/15A/16A Qualification Status

In production

CY7C68013A/14A/15A/16A Errata Summary

This table defines the errata for available CY7C68013A/14A/15A/16A family devices. An “X” indicates that the errata pertain to the

selected device.

Items

CY7C68013A/14A/15A/16A Silicon Revision

Fix Status

[1.]. Empty Flag Assertion

X

B

No silicon fix planned currently. Use the workaround.

1. Empty Flag Assertion

■ Problem Definition

In Slave FIFO Asynchronous Word Wide mode, if a single word data is transferred from the USB host to EP2, configured as OUT

Endpoint (EP) in the first transaction, then the Empty flag behaves incorrectly. This does not happen if the data size is more than

one word in the first transaction.

■ Parameters Affected

NA

■ Trigger Condition(S)

In Slave FIFO Asynchronous Word Wide Mode, after firmware boot and initialization, EP2 OUT endpoint empty flag indicates the

status as ‘Empty’. When data is received in EP2, the status changes to ‘Not-Empty’. However, if data transferred to EP2 is a single

word, then asserting SLRD with FIFOADR pointing to any other endpoint changes ‘Not-Empty’ status to ‘Empty’ for EP2 even

though there is a word data (or it is untouched). This is noticed only when the single word is sent as the first transaction and not if

it follows a multi-word packet as the first transaction.

■ Scope of Impact

External interface does not see data available in EP2 OUT endpoint and can end up waiting for data to be read.

■ Workaround

One of the following workarounds can be used:

• Send a pulse signal to the SLWR pin, with FIFOADR pins pointing to an endpoint other than EP2, after firmware initialization

and before or after transferring the data to EP2 from the host

• Set the length of the first data to EP2 to be more than a word

• Prioritize EP2 read from the Master for multiple OUT EPs and single word write to EP2

• Write to an IN EP, if any, from the Master before reading from other OUT EPs (other than EP2) from the Master.

■ Fix Status

There is no silicon fix planned for this currently; use the workarounds provided.

Document Number: 38-08032 Rev. AD

Page 68 of 74

CY7C68013A/CY7C68014A

CY7C68015A/CY7C68016A

Document History Page

Document Title: CY7C68013A/CY7C68014A/CY7C68015A/CY7C68016A, EZ-USB FX2LP USB Microcontroller High-Speed

USB Peripheral Controller

Document Number: 38-08032

Submission

Rev.

ECN No.

Description of Change

New data sheet (Advance Information).

Date

**

124316

128461

03/17/2003

09/02/2003

*A

Updated Document Title to read as “CY7C68013A/CY7C68015A, EZ-USB FX2LP™ USB Microcon-

troller High-Speed USB Peripheral Controller”.

Changed status from Advance Information to Final.

Added CY7C68015A part related information in all instances across the document.

Replaced I²C-compatible with I²C in all instances across the document.

Updated Logic Block Diagram (Added ECC block and fixed errors).

Updated Functional Overview:

Updated 8051 Microprocessor:

Updated 8051 Clock Frequency:

Added Figure 1.

Updated Reset and Wakeup:

Updated Reset Pin:

Updated description; added Figure 2; and also added Table 5.

Updated Register Addresses:

Updated figure below the heading.

Updated Endpoint RAM:

Updated Endpoint Configurations (Hi-Speed Mode):

Updated Figure 5 (for clarity).

Added ECC Generation.

Updated I²C Controller:

Added “I²C Software Reset”.

Updated Compatible with Previous Generation EZ-USB FX2:

Updated description; and also updated Table 9.

Added CY7C68013A/14A and CY7C68015A/16A Differences.

Updated Register Summary:

Updated Table 12.

Updated Package Diagrams:

spec 51-85144 – Changed revision from *B to *D.

Minor grammatical edits across the document.

*B

*C

130335

131673

10/09/2003

02/12/2004

Changed status from Final to Preliminary.

Updated Functional Overview:

Updated Reset and Wakeup:

Updated Reset Pin:

Updated description; added Note 7 and referred the same note at the end of sentence “If the crystal

input pin is driven by a clock signal the internal PLLstabilizes in 200 μs after V_CChas reached 3.0 Volts”.

Updated Endpoint RAM:

Updated Endpoint Configurations (Hi-Speed Mode):

Updated description (Replaced column 9 with column 8 in last paragraph).

Updated ECC Generation:

Updated description.

Removed “ECC Features”.

Updated ECC Implementation:

Updated description.

Updated Register Summary:

Updated Table 12.

*C (cont.)

131673

02/12/2004

Updated DC Electrical Characteristics:

Updated Table 14:

Added V_{IH_X}, V_{IL_X}parameters and their corresponding details.

Updated USB Transceiver:

Replaced “certified” with “compliant”.

Updated AC Electrical Characteristics:

Updated USB Transceiver:

Replaced “certified” with “compliant”.

Updated Data Memory Write^[33]

Updated Figure 14.

:

Added Sequence Diagram.

Updated Ordering Information:

Updated Table 33:

Updated part numbers.

*D

230713

06/09/2004

Updated Ordering Information:

Updated Table 33:

Updated part numbers (Changed Lead free MPNs as per spec change in 28-00054).

Document Number: 38-08032 Rev. AD

Page 69 of 74

CY7C68013A/CY7C68014A

CY7C68015A/CY7C68016A

Document History Page (continued)

Document Title: CY7C68013A/CY7C68014A/CY7C68015A/CY7C68016A, EZ-USB FX2LP USB Microcontroller High-Speed

USB Peripheral Controller

Document Number: 38-08032

Submission

Rev.

ECN No.

Description of Change

Date

*E

242398

07/13/2004

Minor Change:

Post to external web,

*F

271169

10/07/2004

Updated Features:

Added “USB 2.0–USB-IF high speed certified (TID # 40440111)”.

Added Features (CY7C68013A/14A only).

Added Features (CY7C68015A/16A only).

Updated Logic Block Diagram (Added USB 2.0 logo).

Updated Absolute Maximum Ratings:

Replaced TBD with values for “Power Dissipation”.

Updated DC Electrical Characteristics:

Updated Table 14:

Updated minimum and maximum values of V_CCparameter.

Replaced TBD with values for V_{IH_X}, V_{IL_X}, I_SUSP, I_CCparameters.

Updated AC Electrical Characteristics:

Updated Slave FIFO Asynchronous Packet End Strobe:

Updated Table 28:

Changed maximum value of t_XFLGparameter from 70 ns to 115 ns.

Updated Ordering Information:

Updated Table 33:

Updated part numbers.

*G

316313

02/04/2005

Updated Document Title to read as “CY7C68013A/CY7C68014A/CY7C68015A/CY7C68016A,

EZ-USB FX2LP™ USB Microcontroller High-Speed USB Peripheral Controller”.

Changed status from Preliminary to Final.

Added CY7C68014A, CY7C68016A part related information in all instances across the document.

Updated DC Electrical Characteristics:

Updated Table 14:

Added V_CCRamp Up parameter and its corresponding details.

Updated AC Electrical Characteristics:

Updated Slave FIFO Synchronous Packet End Strobe:

Added description; and also added Figure 24.

Updated Ordering Information:

Updated Table 33:

Updated part numbers.

*H

338901

04/18/2005

Updated Register Summary:

Updated Table 12.

Updated AC Electrical Characteristics:

Updated Data Memory Read^[31]

Added description.

:

Updated Data Memory Write^[33]

Added description.

:

Updated Slave FIFO Synchronous Read:

Updated Table 20:

Replaced TBD with “–” under “Min” column corresponding to t_XFDparameter.

Updated Ordering Information:

Updated Table 33:

Updated part numbers.

*I

371097

397239

06/09/2005

09/19/2005

Updated AC Electrical Characteristics:

Added PORTC Strobe Feature Timings.

*J

Added 56-pin VFBGA Package related information in all instances across the document.

Updated Register Summary:

Updated Table 12.

Updated DC Electrical Characteristics:

Updated Table 14:

Updated minimum and maximum values of V_CCparameter.

Updated Ordering Information:

Updated Table 33:

Updated part numbers.

Updated Package Diagrams:

Added spec 001-03901 *B.

Document Number: 38-08032 Rev. AD

Page 70 of 74

CY7C68013A/CY7C68014A

CY7C68015A/CY7C68016A

Document History Page (continued)

Document Title: CY7C68013A/CY7C68014A/CY7C68015A/CY7C68016A, EZ-USB FX2LP USB Microcontroller High-Speed

USB Peripheral Controller

Document Number: 38-08032

Submission

Rev.

ECN No.

Description of Change

Date

*K

420505

02/09/2006

Updated Pin Assignments:

Updated description (Replaced “four package types” with “five package types”).

Updated Absolute Maximum Ratings:

Added “Ambient Temperature with Power Supplied (Industrial)” and its corresponding details.

Added Thermal Characteristics.

Updated AC Electrical Characteristics:

Updated Slave FIFO Asynchronous Write:

Updated Figure 22 (Remove SLCS).

Updated Sequence Diagram:

Updated Single and Burst Synchronous Write:

Updated description.

Updated Sequence Diagram of a Single and Burst Asynchronous Read:

Updated description.

Updated to new template.

*L

2064406

02/04/2008

Updated Features:

Replaced “TID # 40440111” with “TID # 40460272”.

Updated Functional Overview:

Updated CY7C68013A/14A and CY7C68015A/16A Differences:

Updated Table 10 (Removed T0OUT and T1OUT in “CY7C68015A/CY7C68016A” column).

Updated AC Electrical Characteristics:

Updated Slave FIFO Synchronous Write:

Updated Table 23 (Updated minimum value of t_SWRparameter).

Updated Package Diagrams:

spec 51-85144 – Changed revision from *D to *G.

*M

2710327

05/22/2009

Updated Operating Conditions:

Changed value of F_OSC(oscillator or crystal frequency) from

“24 MHz ± 100 ppm, Parallel Resonant” to “24 MHz ± 10 ppm, Parallel Resonant”.

Updated Ordering Information:

Updated Table 33:

Updated part numbers.

Updated Package Diagrams:

Added spec 51-85187 *C.

*N

*O

2727334

2756202

07/01/2009

08/26/2009

Updated Package Diagrams:

spec 51-85187 – Changed revision from *C to *D.

Fixed Typo in Document History Page (Removed sentence on E-Pad size change from *F revision).

Updated Ordering Information:

Updated Table 33:

No change in part numbers.

Added a column “Serial Debug” and added details under the column.

Added Note 57 and referred the same note in “Serial Debug”.

*P

2785207

2811890

10/12/2009

11/20/2009

Updated Ordering Information:

Updated Table 33:

No change in part numbers.

Updated details in “Package Type” column (Added information on Pb-free parts).

*Q

Updated Ordering Information:

Updated Table 33:

Updated part numbers.

Updated details under “# Program I/Os” column for CY7C68016A-56LTXC and

CY7C68016A-56LTXCT MPNs.

*R

2896281

03/19/2010

Updated Ordering Information:

Updated Table 33:

Updated part numbers.

Updated Package Diagrams:

spec 51-85062 – Changed revision from *C to *D.

spec 51-85144 – Changed revision from *G to *H.

spec 51-85187 – Changed revision from *D to *E.

spec 51-85050 – Changed revision from *B to *C.

spec 51-85101 – Changed revision from *C to *D.

Updated to new template.

Document Number: 38-08032 Rev. AD

Page 71 of 74

CY7C68013A/CY7C68014A

CY7C68015A/CY7C68016A

Document History Page (continued)

Document Title: CY7C68013A/CY7C68014A/CY7C68015A/CY7C68016A, EZ-USB FX2LP USB Microcontroller High-Speed

USB Peripheral Controller

Document Number: 38-08032

Submission

Rev.

ECN No.

Description of Change

Date

*S

3035980

09/22/2010

Updated Operating Conditions:

Changed value of F_OSC(oscillator or crystal frequency) from

“24 MHz + 10 ppm, Parallel Resonant” to “24 MHz + 100 ppm, Parallel Resonant”.

Updated Ordering Information:

Updated Table 33:

No change in part numbers.

Added Ordering Code Definitions.

Added Acronyms and Units of Measure.

Updated to new template.

*T

3161410

3195232

02/03/2011

03/14/2011

Updated Package Diagrams:

Removed spec 51-85144 *H.

Added spec 001-12921 *A.

Removed spec 51-85187 *E.

Added spec 001-53450 *B.

spec 51-85050 – Changed revision from *C to *D.

spec 51-85101 – Changed revision from *D to *E.

Completing Sunset Review.

*U

Updated table numbering.

Updated Thermal Characteristics:

Updated Table 13 (Removed column “Ca Case to Ambient Temperature (°C/W)”).

Updated AC Electrical Characteristics:

Updated GPIF Synchronous Signals:

Updated Table 18 (Added a column “Typ” and added values in that column).

Updated Slave FIFO Synchronous Read:

Updated Table 20 (Added a column “Typ” and added values in that column).

Updated Package Diagrams:

spec 001-12921 – Changed revision from *A to *B.

spec 001-03901 – Changed revision from *C to *D.

*V

3512313

3998554

02/01/2012

07/19/2013

Updated Ordering Information:

Updated Table 33:

Updated part numbers.

Updated Package Diagrams:

spec 51-85062 – Changed revision from *D to *E.

Removed spec 001-12921 *B.

spec 001-03901 – Changed revision from *D to *E.

Completing Sunset Review.

*W

Added Errata footnote (Note 6).

Updated Functional Overview:

Updated Interrupt System:

Updated FIFO/GPIF Interrupt (INT4):

Added Note 6 and referred the same note in “Endpoint 2 empty flag” in Table 4.

Updated Package Diagrams:

spec 51-85062 – Changed revision from *E to *F.

spec 001-53450 – Changed revision from *B to *C.

Added Errata.

Updated to new template.

*X

4617527

01/15/2015

Added More Information.

Updated Pin Assignments:

Updated CY7C68013A/15A Pin Descriptions:

Updated Table 11 (Added a column “Reset” and added details in that column).

Updated AC Electrical Characteristics:

Updated Data Memory Read^[31]

:

Added Note 31 and referred the same note in heading.

Updated Figure 13.

Updated Data Memory Write^[33]

:

Added Note 31 and referred the same note in heading.

Updated Package Diagrams:

spec 001-53450 – Changed revision from *C to *D.

spec 51-85050 – Changed revision from *D to *E.

spec 51-85101 – Changed revision from *E to *F.

Updated to new template.

Completing Sunset Review.

*Y

5317277

06/28/2016

Updated to new template.

Document Number: 38-08032 Rev. AD

Page 72 of 74

CY7C68013A/CY7C68014A

CY7C68015A/CY7C68016A

Document History Page (continued)

Document Title: CY7C68013A/CY7C68014A/CY7C68015A/CY7C68016A, EZ-USB FX2LP USB Microcontroller High-Speed

USB Peripheral Controller

Document Number: 38-08032

Submission

Rev.

ECN No.

Description of Change

Date

*Z

5713641

04/26/2017

Updated Package Diagrams:

spec 51-85050 – Changed revision from *E to *G.

Updated to new template.

AA

AB

5930426

6403695

11/09/2017

12/06/2018

Updated AC Electrical Characteristics:

Updated GPIF Synchronous Signals:

Updated Table 18.

Updated Table 19.

Updated Features:

Added Note 1 and referred the note at the end in “Integrated I²C controller; runs at 100 or 400 kHz”.

Updated Functional Overview:

Updated I²C Bus:

Added Note 4 and referred the note at the end in “FX2LP supports the I²C bus as a master only at

100/400 kHz”.

Updated Thermal Characteristics:

Added “Maximum junction temperature” and its corresponding details.

Updated Package Diagrams:

spec 001-53450 – Changed revision from *D to *E.

Updated to new template.

Completing Sunset Review.

AC

AD

6637530

7113265

07/26/2019

04/30/2021

Updated to new template.

Updated EZ-USB FX2LP Development Kit in More Information.

Added “CY3689” in Ordering Information.

Document Number: 38-08032 Rev. AD

Page 73 of 74

CY7C68013A/CY7C68014A

CY7C68015A/CY7C68016A

Sales, Solutions, and Legal Information

Worldwide Sales and Design Support

Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office

closest to you, visit us at Cypress Locations.

®

Products

PSoC Solutions

Arm^®Cortex^®Microcontrollers

cypress.com/arm

cypress.com/automotive

cypress.com/clocks

cypress.com/interface

cypress.com/iot

PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP | PSoC 6 MCU

Automotive

Cypress Developer Community

Clocks & Buffers

Interface

Training | Components

Internet of Things

Memory

Technical Support

cypress.com/memory

cypress.com/mcu

cypress.com/support

Microcontrollers

PSoC

cypress.com/psoc

cypress.com/pmic

cypress.com/touch

cypress.com/usb

Power Management ICs

Touch Sensing

USB Controllers

Wireless Connectivity

cypress.com/wireless

document, including any software or firmware included or referenced in this document (“Software”), is owned by Cypress under the intellectual property laws and treaties of the United States and other

countries worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks,

or other intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software,

then Cypress hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source

code form, to modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally

to end users (either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the

Software (as provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation,

or compilation of the Software is prohibited.

TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE

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addition, the products described in these materials may contain design defects or errors known as errata which may cause the product to deviate from published specifications. To the extent permitted

by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any product or

circuit described in this document.Any information provided inthis document, including any sample design information or programming code, is provided only for reference purposes. It is the responsibility

of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. “High-Risk Device” means any

device or system whose failure could cause personal injury, death, or property damage. Examples of High-Risk Devices are weapons, nuclear installations, surgical implants, and other medical devices.

“Critical Component” means any component of a High-Risk Device whose failure to perform can be reasonably expected to cause, directly or indirectly, the failure of the High-Risk Device, or to affect

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product as a Critical Component in the specific High-Risk Device and you have signed a separate indemnification agreement.

Cypress, the Cypress logo, and combinations thereof, PSoC, CapSense, EZ-USB, F-RAM, Traveo, WICED, and ModusToolbox are trademarks or registered trademarks of Cypress or a subsidiary of

Cypress in the United States or in other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.

Document Number: 38-08032 Rev. AD

Revised April 30, 2021

Page 74 of 74

FX2LP is a trademark and EZ-USB is a registered trademark of Cypress Semiconductor Corporation.


型号：	CY7C68013A-56PVXCT
厂家：	Infineon
描述：	USB 2.0 Peripheral controller with 16K RAM, 24 GPIOs, 56-pin SSOP for non-battery powered applications 可编程只读存储器电动程控只读存储器电可擦编程只读存储器时钟数据传输微控制器光电二极管外围集成电路
文件：	总75页 (文件大小：962K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

CY7C68013A-56PVXCT [INFINEON]

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SI9130DB

SI9135LG-T1

SI9135LG-T1-E3

SI9135_11

SI9136_11

SI9130CG-T1-E3

SI9130LG-T1-E3

SI9130_11

SI9137

SI9137DB

SI9137LG

SI9122E