CY8C4014SXS-421Z_技术文档

CY8C40xx

Automotive PSoC™ 4: PSoC™ 4000

Based on Arm® Cortex®-M0 CPU

General description

PSoC™ 4 is a scalable and reconfigurable platform architecture for a family of programmable embedded system

controllers with an Arm® Cortex®-M0 CPU, while being AEC-Q100 compliant. It combines programmable and

reconfigurable analog and digital blocks with flexible automatic routing. The PSoC™ 4000 product family is the

smallest member of the PSoC™ 4 platform architecture. It is a combination of a microcontroller with standard

communication and timing peripherals, a capacitive touch-sensing system (CAPSENSE™) with best-in-class

performance, and general-purpose analog. PSoC™ 4000 products will be fully upward compatible with members

of the PSoC™ 4 platform for new applications and design needs.

Features

• 32-bit MCU subsystem

- 16-MHz Arm® Cortex®-M0 CPU

- Up to 16 KB of flash with Read Accelerator

- Up to 2 KB of SRAM

• Programmable Analog

- Two current DACs (IDACs) for general-purpose or capacitive sensing applications

- One low-power comparator with internal reference

• Low power 1.71-V to 5.5-V operation

- Deep Sleep mode with wake-up on interrupt and I²C address detect

• Capacitive sensing

- Capacitive sigma-delta provides best-in-class signal-to-noise ratio (SNR) and water tolerance

- Infineon-supplied software component makes capacitive sensing design easy

- Automatic hardware tuning (SmartSense)

• Serial Communication

- Multi-master I²C block with the ability to do address matching during Deep Sleep and generate a wake-up on

match

• Timing and pulse-width modulation

- One 16-bit timer/counter/pulse-width modulator (TCPWM) block

- Center-aligned, Edge, and Pseudo-Random modes

- Comparator-based triggering of Kill signals for motor drive and other high-reliability digital logic applications

• Up to 20 programmable GPIO pins

- 24-pin QFN and 16-pin SOIC packages

- GPIO pins on Ports 0, 1, and 2 can be CAPSENSE™ or have other functions

- Drive modes, strengths, and slew rates are programmable

• Temperature ranges

- A Grade: –40 °C to +85 °C

- S-Grade: –40 °C to +105 °C

- E-Grade: –40 °C to +125 °C

- Automotive Electronics Council (AEC) Q100 qualified

• PSoC™ Creator Design Environment

- Integrated Development Environment (IDE) provides schematic design entry and build (with analog and dig-

ital automatic routing)

- Applications Programming Interface (API) component for all fixed-function and programmable peripherals

• Industry-Standard Tool Compatibility

- After schematic entry, development can be done with Arm-based industry-standard development tools

Datasheet

www.infineon.com

Please read the Important Notice and Warnings at the end of this document

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Automotive PSoC™ 4: PSoC™ 4000

Based on Arm® Cortex®-M0 CPU

Block diagram

CPU Subsystem

PSoC™ 4000

SWD/TC

Cortex

M0

16 MHz

MUL

SPCIF

Flash

16KB

SRAM

2KB

ROM

4KB

32-bit

AHB-Lite

Read Accelerator

SRAM Controller

ROM Controller

NVIC, IRQMX

System Resources

Lite

System Interconnect (

)

Single/Multi Layer AHB

Power

Sleep Control

WIC

Peripherals

POR

PWRSYS

REF

PCLK

Peripheral Interconnect (MMIO)

Clock

Clock Control

WDT

IMO

ILO

Reset

Reset Control

XRES

Test

DFT Logic

DFT Analog

Power Modes

Active/ Sleep

Deep Sleep

High Speed I/O Matrix

20 x GPIOs

I/O Subsystem

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Automotive PSoC™ 4: PSoC™ 4000

Based on Arm® Cortex®-M0 CPU

Table of contents

General description ...........................................................................................................................1

Features ...........................................................................................................................................1

Block diagram...................................................................................................................................2

Table of contents...............................................................................................................................3

1 Functional overview .......................................................................................................................4

1.1 CPU and memory subsystem .................................................................................................................................4

1.2 System resources....................................................................................................................................................4

1.3 Analog blocks ..........................................................................................................................................................6

1.4 Fixed function digital ..............................................................................................................................................6

1.5 GPIO.........................................................................................................................................................................6

1.6 Special Function Peripherals .................................................................................................................................7

2 Pinouts ..........................................................................................................................................8

3 Power ..........................................................................................................................................10

3.1 Unregulated external supply................................................................................................................................10

3.2 Regulated external supply....................................................................................................................................11

4 Development support ...................................................................................................................12

4.1 Documentation .....................................................................................................................................................12

4.2 Online ....................................................................................................................................................................12

4.3 Tools ......................................................................................................................................................................12

5 Electrical Specifications ................................................................................................................13

5.1 Absolute Maximum Ratings..................................................................................................................................13

5.2 Device Level Specifications ..................................................................................................................................13

5.3 Analog peripherals................................................................................................................................................18

5.4 Digital peripherals.................................................................................................................................................20

5.5 Memory..................................................................................................................................................................21

5.6 System resources..................................................................................................................................................21

6 Ordering information ....................................................................................................................24

6.1 Part numbering conventions................................................................................................................................24

7 Packaging ....................................................................................................................................26

7.1 Package outline drawings ....................................................................................................................................27

8 Acronyms.....................................................................................................................................29

9 Document conventions..................................................................................................................33

9.1 Units of measure ...................................................................................................................................................33

Revision history ..............................................................................................................................34

Datasheet

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Automotive PSoC™ 4: PSoC™ 4000

Based on Arm® Cortex®-M0 CPU

Functional description

1

Functional description

PSoC™ 4000 devices include extensive support for programming, testing, debugging, and tracing both hardware

and firmware.

The Arm® Serial-Wire Debug (SWD) interface supports all programming and debug features of the device.

Complete debug-on-chip functionality enables full-device debugging in the final system using the standard

production device. It does not require special interfaces, debugging pods, simulators, or emulators. Only the

standard programming connections are required to fully support debug.

The PSoC™ Creator IDE provides fully integrated programming and debug support for the PSoC™ 4000 devices.

The SWD interface is fully compatible with industry-standard third-party tools. The PSoC™ 4000 family provides

a level of security not possible with multi-chip application solutions or with microcontrollers.

It has the following advantages:

• Allows disabling of debug features

• Robust flash protection

• Allows customer-proprietary functionality to be implemented in on-chip programmable blocks

The debug circuits are enabled by default and can only be disabled in firmware. If they are not enabled, the only

way to re-enable them is to erase the entire device, clear flash protection, and reprogram the device with new

firmware that enables debugging.

Additionally, all device interfaces can be permanently disabled (device security) for applications concerned

about phishing attacks due to a maliciously reprogrammed device or attempts to defeat security by starting and

interrupting flash programming sequences. All programming, debug, and test interfaces are disabled when

maximum device security is enabled. Therefore, PSoC™ 4000, with device security enabled, will have only limited

capability for failure analysis. This is a trade-off the PSoC™ 4000 allows the customer to make.

2

Functional overview

CPU and memory subsystem

CPU

2.1

2.1.1

The Cortex®-M0 CPU in the PSoC™ 4000 is part of the 32-bit MCU subsystem, which is optimized for low-power

operation with extensive clock gating. Most instructions are 16 bits in length and the CPU executes a subset of

the Thumb-2 instruction set. This enables fully compatible, binary, upward migration of the code to higher

performance processors, such as the Cortex-M3 and M4. It includes a nested vectored interrupt controller (NVIC)

block with eight interrupt inputs and also includes a Wakeup Interrupt Controller (WIC). The WIC can wake the

processor from the Deep Sleep mode, allowing power to be switched off to the main processor when the chip is

in the Deep Sleep mode.

The CPU also includes a debug interface, the SWD interface, which is a 2-wire form of JTAG. The debug configu-

ration used for PSoC™ 4000 has four breakpoint (address) comparators and two watchpoint (data) comparators.

2.1.2

Flash

The PSoC™ 4000 device has a flash module with a flash accelerator, tightly coupled to the CPU to improve average

access times from the flash block. The low-power flash block is designed to deliver zero wait-state (WS) access

time at 16 MHz. The flash accelerator delivers 85% of the single-cycle SRAM access performance on average.

2.1.3

SRAM

Two KB of SRAM are provided with zero wait-state access at 16 MHz.

2.1.4

SROM

A supervisory ROM that contains boot and configuration routines is provided.

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Based on Arm® Cortex®-M0 CPU

Functional overview

2.2

System resources

Power system

2.2.1

The power system is described in detail in the section on Power on page 10. It provides an assurance that voltage

levels are as required for each respective mode and either delays mode entry (for example, on power-on reset

(POR)) until voltage levels are as required for proper functionality, or generates resets (for example, on brown-out

detection). The PSoC™ 4000 operates with a single external supply over the range of either 1.8 V ±5% (externally

regulated) or 1.8 to 5.5 V (internally regulated) and has three different power modes, transitions between which

are managed by the power system. The PSoC™ 4000 provides Active, Sleep, and Deep Sleep low-power modes.

All subsystems are operational in Active mode. The CPU subsystem (CPU, flash, and SRAM) is clock-gated off in

Sleep mode, while all peripherals and interrupts are active with instantaneous wake-up on a wake-up event. In

Deep Sleep mode, the high-speed clock and associated circuitry is switched off; wake-up from this mode takes

35 µs.

2.2.2

Clock system

The PSoC™ 4000 clock system is responsible for providing clocks to all subsystems that require clocks and for

switching between different clock sources without glitching. In addition, the clock system ensures that there are

no metastable conditions.

The clock system for the PSoC™ 4000 consists of the internal main oscillator (IMO) and the internal low-frequency

oscillator (ILO) and provision for an external clock.

IMO

F_CPU

Divide By

2,4,8

External Clock

(connects to GPIO pin P0.4)

Figure 1

PSoC™ 4000 MCU clocking architecture

The F_CPUsignal can be divided down to generate synchronous clocks for the analog and digital peripherals. There

are four clock dividers for the PSoC™ 4000, each with 16-bit divide capability The 16-bit capability allows flexible

generation of fine-grained frequency values and is fully supported in PSoC™ Creator.

2.2.3

IMO clock source

The IMO is the primary source of internal clocking in the PSoC™ 4000. It is trimmed during testing to achieve the

specified accuracy.The IMO default frequency is 24 MHz and it can be adjusted from 24 to 48 MHz in steps of

4 MHz. The IMO tolerance with Infineon-provided calibration settings is ±2% (24 and 32 MHz).

2.2.4

ILO clock source

The ILO is a very low power, 40-kHz oscillator, which is primarily used to generate clocks for the watchdog timer

(WDT) and peripheral operation in Deep Sleep mode. ILO-driven counters can be calibrated to the IMO to improve

accuracy. Infineon provides a software component, which does the calibration.

2.2.5

Watchdog timer

A watchdog timer is implemented in the clock block running from the ILO; this allows watchdog operation during

Deep Sleep and generates a watchdog reset if not serviced before the set timeout occurs. The watchdog reset is

recorded in a Reset Cause register, which is firmware readable.

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Based on Arm® Cortex®-M0 CPU

Functional overview

2.2.6

Reset

The PSoC™ 4000 can be reset from a variety of sources including a software reset. Reset events are asynchronous

and guarantee reversion to a known state. The reset cause is recorded in a register, which is sticky through reset

and allows software to determine the cause of the reset. An XRES pin is reserved for external reset on the 24-pin

package. An internal POR is provided on the 16-pin package. The XRES pin has an internal pull-up resistor that is

always enabled.

2.2.7

Voltage reference

The PSoC™ 4000 reference system generates all internally required references. A 1.2-V voltage reference is

provided for the comparator. The IDACs are based on a ±5% reference.

2.3

Analog blocks

2.3.1

Low-power comparators

The PSoC™ 4000 has a low-power comparator, which uses the built-in voltage reference. Any one of up to 16 pins

can be used as a comparator input and the output of the comparator can be brought out to a pin. The selected

comparator input is connected to the minus input of the comparator with the plus input always connected to the

1.2-V voltage reference

2.3.2

Current DACs

The PSoC™ 4000 has two IDACs, which can drive any of up to 16 pins on the chip. These IDACs have programmable

current ranges.

2.3.3

Analog multiplexed buses

The PSoC™ 4000 has two concentric independent buses that go around the periphery of the chip. These buses

(called amux buses) are connected to firmware-programmable analog switches that allow the chip's internal

resources (IDACs, comparator) to connect to any pin on Ports 0, 1, and 2.

2.4

Fixed function digital

2.4.1

Timer/Counter/PWM (TCPWM) block

The TCPWM block consists of a 16-bit counter with user-programmable period length. There is a capture register

to record the count value at the time of an event (which may be an I/O event), a period register that is used to

either stop or auto-reload the counter when its count is equal to the period register, and compare registers to

generate compare value signals that are used as PWM duty cycle outputs. The block also provides true and

complementary outputs with programmable offset between them to allow use as dead-band programmable

complementary PWM outputs. It also has a Kill input to force outputs to a predetermined state; for example, this

is used in motor drive systems when an over-current state is indicated and the PWM driving the FETs needs to be

shut off immediately with no time for software intervention.

2.4.2

Serial communication block (SCB)

The PSoC™ 4000 has a serial communication block, which implements a multi-master I²C interface.

I²C Mode: The hardware I²C block implements a full multi-master and slave interface (it is capable of

multi-master arbitration). This block is capable of operating at speeds of up to 400 kbps (Fast Mode) and has

flexible buffering options to reduce interrupt overhead and latency for the CPU. It also supports EZI2C that

creates a mailbox address range in the memory of the PSoC™ 4000 and effectively reduces I²C communication to

reading from and writing to an array in memory. In addition, the block supports an 8-deep FIFO for receive and

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Automotive PSoC™ 4: PSoC™ 4000

Based on Arm® Cortex®-M0 CPU

Functional overview

transmit which, by increasing the time given for the CPU to read data, greatly reduces the need for clock

stretching caused by the CPU not having read data on time.

The I²C peripheral is compatible with the I²C Standard-mode and Fast-mode devices as defined in the NXP

I²C-bus specification and user manual (UM10204). The I²C bus I/O is implemented with GPIO in open-drain

modes.

The PSoC™ 4000 is not completely compliant with the I²C spec in the following respect:

• GPIO cells are not overvoltage tolerant and, therefore, cannot be hot-swapped or powered up independently

of the rest of the I²C system.

2.5

GPIO

The PSoC™ 4000 has up to 20 GPIOs. The GPIO block implements the following:

• Eight drive modes:

- Analog input mode (input and output buffers disabled)

- Input only

- Weak pull-up with strong pull-down

- Strong pull-up with weak pull-down

- Open drain with strong pull-down

- Open drain with strong pull-up

- Strong pull-up with strong pull-down

- Weak pull-up with weak pull-down

• Input threshold select (CMOS or LVTTL).

• Individual control of input and output buffer enabling/disabling in addition to the drive strength modes

• Selectable slew rates for dV/dt related noise control to improve EMI

The pins are organized in logical entities called ports, which are 8-bit in width (less for Ports 2 and 3). During

power-on and reset, the blocks are forced to the disable state so as not to crowbar any inputs and/or cause excess

turn-on current. A multiplexing network known as a high-speed I/O matrix is used to multiplex between various

signals that may connect to an I/O pin.

Data output and pin state registers store, respectively, the values to be driven on the pins and the states of the

pins themselves.

Every I/O pin can generate an interrupt if so enabled and each I/O port has an interrupt request (IRQ) and interrupt

service routine (ISR) vector associated with it (4 for PSoC™ 4000).

2.6

Special function peripherals

CAPSENSE™

2.6.1

CAPSENSE™ is supported in the PSoC™ 4000 through a CSD block that can be connected to up to 16 pins through

an analog mux bus via an analog switch (pins on Port 3 are not available for CAPSENSE™ purposes). CAPSENSE™

function can thus be provided on any available pin or group of pins in a system under software control. A PSoC™

Creator component is provided for the CAPSENSE™ block to make it easy for the user.

Shield voltage can be driven on another mux bus to provide water-tolerance capability. Water tolerance is

provided by driving the shield electrode in phase with the sense electrode to keep the shield capacitance from

attenuating the sensed input. Proximity sensing can also be implemented.

The CAPSENSE™ block has two IDACs, which can be used for general purposes if CAPSENSE™ is not being used

(both IDACs are available in that case) or if CAPSENSE™ is used without water tolerance (one IDAC is available).

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Automotive PSoC™ 4: PSoC™ 4000

Based on Arm® Cortex®-M0 CPU

Pinouts

3

Pinouts

The following is the pin list for PSoC™ 4000. All Port pins support GPIO. Ports 0, 1, and 2 support CSD CAPSENSE™

and analog mux bus connections.

Table 1

PSoC™ 4000 pin descriptions

24-pin QFN 16-pin SOIC

Name Name

TCPWM signals

Alternate functions

1

P0.0/TRIN0

TRIN0: Trigger Input 0

P0.1/TRIN1/

CMPO_0

2

3

4

P0.1/TRIN1/CMPO_0 TRIN1: Trigger Input 1 CMPO_0: Sense Comp Out

3

4

P0.2/TRIN2

P0.3/TRIN3

P0.2/TRIN2

TRIN2: Trigger Input 2

TRIN3: Trigger Input 3

P0.4/TRIN4/

CMPO_0/EXT_CL

K

P0.4/TRIN4/CMPO_0/E

XT_CLK

CMPO_0: Sense Comp Out,

External Clock, CMOD Cap

5

TRIN4: Trigger Input 4

6

VCCD

VDD

6

7

VCCD

VDD

VSS

7

8

VSS

8

9

P0.5

9

P0.5

P0.6

10

11

12

13

14

15

16

17

P0.6

10

P0.7

P1.0

P1.1/OUT0

P1.2/SCL

P1.3/SDA

P1.4/UND0

P1.5/OVF0

11

12

13

P1.1/OUT0

P1.2/SCL

P1.3/SDA

OUT0: PWM OUT 0

I2C Clock

I2C Data

UND0: Underflow Out

OVF0: Overflow Out

CMPO_0: Sense Comp Out,

Internal Reset function

during POR (must not have

load to ground during POR).

P1.6/OVF0/UND0/

nOUT0/CMPO_0

P1.6/OVF0/UND0/

nOUT0/CMPO_0

nOUT0: Complement

of OUT0 (not OUT)

18

14

P1.7/MATCH/EXT

_CLK

19

20

21

15 P1.7/MATCH/EXT_CLK

MATCH: Match Out

External Clock

P2.0

16

1

P2.0

P3.0/SDA/

SWD_IO

P3.0/SDA/

SWD_IO

I2C Data, SWD IO

P3.1/SCL/

SWD_CLK

P3.1/SCL/

SWD_CLK

22

2

I2C Clock, SWD Clock

23

24

P3.2

OUT0:PWM OUT 0

XRES

XRES: External Reset

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Automotive PSoC™ 4: PSoC™ 4000

Based on Arm® Cortex®-M0 CPU

Pinouts

Descriptions of the pin functions are as follows:

VDD: Power supply for both analog and digital sections.

VSS: Ground pin.

VCCD: Regulated digital supply (1.8 V ±5%).

Pins belonging to Ports 0, 1, and 2 can all be used as CSD sense and shield pins can be connected to AMUXBUS A

or B or can all be used as GPIO pins that can be driven by the firmware.

Pins on Port 3 can be used as GPIO, in addition to their alternate functions listed above.

The following packages are provided: 24-pin QFN and 16-pin SOIC.

24

23

22

21 20

19

18

P0.0

P0.1

1

2

3

4

5

6

P1.6

P1.5

P1.4

P1.3

P1.2

P1.1

17

16

15

14

13

QFN

24

Top

View

P0.2

P0.3

P0.4

VCCD

7

8

9

10

11

12

Figure 2

24-pin QFN pinout

P3.0

1

2

3

4

5

6

16

15

14

13

12

11

P2.0

P1.7

P1.6

P1.3

P1.2

P3.1

P0.1

P0.2

P0.4

16-SOIC

Top View

P1.1

VCCD

VDD

7

8

P0.6

P0.5

10

9

VSS

Figure 3

16-pin SOIC pinout

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Automotive PSoC™ 4: PSoC™ 4000

Based on Arm® Cortex®-M0 CPU

Power

4

Power

The following power system diagrams (Figure 4 and Figure 5) show the set of power supply pins as implemented

for the PSoC™ 4000. The system has one regulator in Active mode for the digital circuitry. There is no analog

regulator; the analog circuits run directly from the V_DDinput. There is a separate regulator for the Deep Sleep

mode. The supply voltage range is either 1.8 V ±5% (externally regulated) or 1.8 V to 5.5 V (unregulated externally;

regulated internally) with all functions and circuits operating over that range.

The PSoC™ 4000 family allows two distinct modes of power supply operation: Unregulated external supply and

regulated external supply.

4.1

Unregulated external supply

In this mode, the PSoC™ 4000 is powered by an external power supply that can be anywhere in the range of 1.8

to 5.5 V. This range is also designed for battery-powered operation. For example, the chip can be powered from

a battery system that starts at 3.5 V and works down to 1.8 V. In this mode, the internal regulator of the PSoC™

4000 supplies the internal logic and the V_CCDoutput of the PSoC™ 4000 must be bypassed to ground via an

external capacitor (0.1 µF; X5R ceramic or better).

Bypass capacitors must be used from V_DDDto ground. The typical practice for systems in this frequency range is

to use a capacitor in the 1-µF range, in parallel with a smaller capacitor (0.1 µF, for example). Note that these are

simply rules of thumb and that, for critical applications, the PCB layout, lead inductance, and the bypass

capacitor parasitic should be simulated to design and obtain optimal bypassing.

An example of a bypass scheme follows (V_DDIOis available on the 16-QFN package).



5. 5V

Power supply connections when 1.8  V_DD

1.8 V to 5.5 V

PSoC4000

V_DD



1 F



0. 1 F

V_CCD



F

0. 1

V_SS

Figure 4

24-pin QFN bypass scheme example - Unregulated external supply

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Automotive PSoC™ 4: PSoC™ 4000

Based on Arm® Cortex®-M0 CPU

Power

4.2

Regulated external supply

In this mode, the PSoC™ 4000 is powered by an external power supply that must be within the range of 1.71^[1]to

1.89 V; note that this range needs to include the power supply ripple too. In this mode, the V_DDand V_CCDpins are

shorted together and bypassed. The internal regulator is disabled in the firmware.

An example of a bypass scheme follows.

Power supply connections when 1.71  V_DD 1.89 V

1.71 V to 1.89 V

PSoC 4000

V_DD

V_CCD

1 F

0.1 F

V_SS

Figure 5

24-pin QFN bypass scheme example - Regulated external supply

Note

1. 1.75 V for E-grade devices.

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Automotive PSoC™ 4: PSoC™ 4000

Based on Arm® Cortex®-M0 CPU

Development support

5

Development support

The PSoC™ 4000 family has a rich set of documentation, development tools, and online resources to assist you

during your development process. Visit www.infineon.com/psoc4 to find out more.

5.1

Documentation

A suite of documentation supports the PSoC™ 4000 family to ensure that you can find answers to your questions

quickly. This section contains a list of some of the key documents.

Software User Guide: A step-by-step guide for using PSoC™ Creator. The software user guide shows you how the

PSoC™ Creator build process works in detail, how to use source control with PSoC™ Creator, and much more.

Component Datasheets: The flexibility of PSoC™ allows the creation of new peripherals (components) long after

the device has gone into production. Component data sheets provide all of the information needed to select and

use a particular component, including a functional description, API documentation, example code, and AC/DC speci-

fications.

Application Notes: PSoC™ application notes discuss a particular application of PSoC™ in depth; examples include

brushless DC motor control and on-chip filtering. Application notes often include example projects in addition to

the application note document.

Technical Reference Manual: The Technical Reference Manual (TRM) contains all the technical detail you need to

use a PSoC™ device, including a complete description of all PSoC™ registers. The TRM is available in the Documen-

tation section at www.infineon.com/psoc4.

5.2

Online

In addition to print documentation, the PSoC™ forums connect you with fellow PSoC™ users and experts in PSoC™

from around the world, 24 hours a day, 7 days a week.

5.3

Tools

With industry standard cores, programming, and debugging interfaces, the PSoC™ 4000 family is part of a devel-

opment tool ecosystem. Visit us at www.infineon.com/psoccreator for the latest information on the revolutionary,

easy to use PSoC™ Creator IDE, supported third party compilers, programmers, debuggers, and development kits.

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Automotive PSoC™ 4: PSoC™ 4000

Based on Arm® Cortex®-M0 CPU

Electrical Specifications

6

Electrical Specifications

6.1

Table 2

Absolute Maximum Ratings

Absolute Maximum Ratings^[2]

Details/

Spec ID# Parameter

Description

Min

–0.5

Typ

–

Max

6

Unit

Conditions

SID1

SID2

V_{DDD_ABS}

V_{CCD_ABS}

Digital supply relative to V_SS

V

–

Direct digital core voltage input

relative to V_SS

–

1.95

V_DD

+

SID3

SID4

V_{GPIO_ABS}

I_{GPIO_ABS}

GPIO voltage

–0.5

–25

–

V

–

0.5

Maximum current per GPIO

GPIO injection current,

25

mA

Current injected

per pin

SID5

I_{GPIO_injection}Max for V_IH> V_DDD, and

Min for V_IL< V_SS

–0.5

–

0.5

mA

V

Electrostatic discharge human

body model

BID44

ESD_HBM

2000

–

Electrostatic discharge charged

device model

BID45

BID46

ESD_CDM

LU

500

–

V

–

Pin current for latch-up

–140

140

mA

6.2

Device Level Specifications

All specifications are valid for –40 °C T_A85 °C for A grade devices and –40 °C T_A105 °C for S grade devices and

–40 °C  T_A 125 °C for Grade-E devices, except where noted. Specifications are valid for 1.71 V to 5.5 V, except

where noted.

Table 3

DC Specifications

Typical values measured at V_DD= 3.3 V and 25 °C.

Spec ID# Parameter

SID53 V_DD

Description

Min

Typ

Max

Units Details/Conditions

With regulator

Power supply input voltage

1.8

–

5.5

V

enabled

Internally

1.71

–

1.89

V

Power supply input voltage

unregulated supply

SID255

SID54

V_DD

(V_CCD= V_DD

)

1.75

1.71

1.75

–

1.89

V_DD

V

-40 °C TA 125 °C

–

V_DDIO

V_DDIOdomain supply

-40 °C TA 125 °C

External regulator voltage

bypass

SID55

SID56

C_EFC

C_EXC

–

0.1

1

–

µF X5R ceramic or better

Power supply bypass capacitor

Active Mode, V_DD= 1.8 to 5.5 V

Execute from flash;

CPU at 6 MHz

SID9

I_DD5

–

2.0

2.85

mA

–

Note

2. Usage above the absolute maximum conditions listed in Table 1 may cause permanent damage to the device. Exposure to

Absolute Maximum conditions for extended periods of time may affect device reliability. The Maximum Storage Tempera-

ture is 150 °C in compliance with JEDEC Standard JESD22-A103, High Temperature Storage Life. When used below Absolute

Maximum conditions but above normal operating conditions, the device may not operate to specification.

Datasheet

13

001-92145 Rev. *L

2023-01-19

Automotive PSoC™ 4: PSoC™ 4000

Based on Arm® Cortex®-M0 CPU

Electrical Specifications

Table 3

DC Specifications (continued)

Typical values measured at V_DD= 3.3 V and 25 °C.

Spec ID# Parameter

Description

Min

Typ

Max

Units Details/Conditions

Execute from flash;

CPU at 12 MHz

SID12

SID16

I_DD8

–

3.2

3.75

mA

–

Execute from flash;

CPU at 16 MHz

I_DD11

–

4.0

4.5

Sleep Mode, V_DDD= 1.71 to 5.5 V

SID25

I_DD20

I²C wakeup, WDT on. 6 MHz

I²C wakeup, WDT on. 12 MHz

–

1.1

1.4

–

mA

–

SID25A

I_DD20A

Deep Sleep Mode, V_DD= 1.8 to 3.6 V (Regulator on)

SID31 I_DD26

I²C wakeup and WDT on

Deep Sleep Mode, V_DD= 3.6 to 5.5 V (Regulator on)

SID34 I_DD29

I²C wakeup and WDT on

–

2.5

8.2

12

µA

–

Deep Sleep Mode, V_DD= V_CCD= 1.71 to 1.89 V (Regulator bypassed)

SID37

I_DD32

I²C wakeup and WDT on

–

2.5

2

9.2

XRES Current

Supply current while XRES

asserted

SID307

I_{DD_XR}

–

5

mA

–

Table 4

AC Specifications

Details/

Spec ID# Parameter

Description

CPU frequency

Wakeup from Sleep mode

Min

Typ

Max Units

Conditions

SID48

SID49^[3]

SID50^[3]

F_CPU

DC

–

0

35

16

–

MHz 1.71 V_DD5.5

T_SLEEP

µs

–

T_DEEPSLEEPWakeup from Deep Sleep mode

–

Note

3. Guaranteed by characterization.

Datasheet

14

001-92145 Rev. *L

2023-01-19

Automotive PSoC™ 4: PSoC™ 4000

Based on Arm® Cortex®-M0 CPU

Electrical Specifications

6.2.1

GPIO

Table 5

GPIO DC Specifications

Details/

Spec ID# Parameter

Description

Min

Typ

Max

Units

Conditions

[4]

SID57

V_IH

V_IL

V_IH

V_IL

V_IH

V_IL

Input voltage high threshold 0.7 × V_DDD

–

V

CMOS Input

SID58

Input voltage low threshold

LVTTL input, V_DDD< 2.7 V

LVTTL input, V_DDD 2.7 V

–

0.3 × V_DDD

CMOS Input

[4]

SID241

SID242

SID243

SID244

0.7× V_DDD

–

2.0

–

0.3 × V_DDD

–

0.8

I_OH= 4 mA

at 3 V V_DDD

SID59

SID60

SID61

SID62

SID62A

V_OH

V_OL

Output voltage high level

Output voltage low level

V_DDD–0.6

–

V

I_OH= 1 mA

at 1.8 V V_DDD

V_DDD–0.5

–

I_OL= 4 mA

at 1.8 V V_DDD

–

0.6

0.4

I_OL= 10 mA

at 3 V V_DDD

I_OL= 3 mA

at 3 V V_DDD

V_OL

Output voltage low level

Pull-up resistor

SID63

SID64

R_PULLUP

3.5

5.6

8.5

kΩ

–

R_PULLDOWNPull-down resistor

Input leakage current

SID65

SID66

I_IL

–

2

nA 25 °C, V_DDD= 3.0 V

(absolute value)

C_IN

Input capacitance

–

3

7

–

pF

–

V

SID67^[5]V_HYSTTL

Input hysteresis LVTTL

15

40

mV

_DDD 2.7 V

0.05 ×

V_DDD

SID68^[5]V_HYSCMOS

Input hysteresis CMOS

–

mV V_DD< 4.5 V

mV V_DD> 4.5 V

SID68A^[5]V_HYSCMOS5V5Input hysteresis CMOS

200

Current through protection

SID69^[5]I_DIODE

–

100

µA

–

diode to V_DD/V_SS

Maximum total source or

SID69A^[5]I_{TOT_GPIO}

–

85

mA

sink chip current

Notes

4. V must not exceed V

+ 0.2 V.

DDD

IH

5. Guaranteed by characterization.

Datasheet

15

001-92145 Rev. *L

2023-01-19

Automotive PSoC™ 4: PSoC™ 4000

Based on Arm® Cortex®-M0 CPU

Electrical Specifications

Table 6

GPIO AC Specifications

(Guaranteed by Characterization)

Details/

Spec ID# Parameter

Description

Min

2

Typ

–

Max Units

Conditions

Rise time in fast strong

mode

3.3 V V_DDD

,

SID70

SID71

SID72

SID73

T_RISEF

T_FALLF

T_RISES

T_FALLS

12

60

ns

–

Cload = 25 pF

3.3 V V_DDD

,

Fall time in fast strong mode

2

–

Cload = 25 pF

Rise time in slow strong

mode

3.3 V V_DDD

,

10

–

Cload = 25 pF

Fall time in slow strong

mode

3.3 V V_DDD,

Cload = 25 pF

90/10%, 25 pF

–

GPIO F_OUT; 3.3 V  V_DDD

5.5 V.

Fast strong mode.

SID74

SID75

SID76

SID245

SID246

F_GPIOUT1

F_GPIOUT2

F_GPIOUT3

F_GPIOUT4

F_GPIOIN

–

16

7

MHz load, 60/40 duty

cycle

GPIO F_OUT; 1.71 VV_DDD

3.3 V.

Fast strong mode.

90/10%, 25 pF

MHz load, 60/40 duty

cycle

GPIO F_OUT; 3.3 V V_DDD

5.5 V.

Slow strong mode.

90/10%, 25 pF

MHz load, 60/40 duty

cycle

GPIO F_OUT; 1.71 V V_DDD

3.3 V.

Slow strong mode.

90/10%, 25 pF

MHz load, 60/40 duty

cycle

3.5

16

GPIO input operating

frequency;

1.71 V V_DDD5.5 V

MHz 90/10% V_IO

Datasheet

16

001-92145 Rev. *L

2023-01-19

Automotive PSoC™ 4: PSoC™ 4000

Based on Arm® Cortex®-M0 CPU

Electrical Specifications

6.2.2

XRES

Table 7

XRES DC Specifications

Details/

Spec ID# Parameter

Description

Min

Typ

Max

Units

Conditions

SID77

SID78

SID79

SID80

V_IH

Input voltage high threshold 0.7 × V_DDD

–

V

CMOS Input

V_IL

Input voltage low threshold

Pull-up resistor

–

3.5

–

0.3 × V_DDD

CMOS Input

R_PULLUP

C_IN

5.6

3

8.5

7

kΩ

pF

–

Input capacitance

–

Typical hysteresis

SID81^[6]

V_HYSXRES

Input voltage hysteresis

–

05 × V_DD

–

mV is 200 mV

for V_DD> 4.5V

Table 8

XRES AC Specifications

Details/

Spec ID# Parameter

Description

Min

5

Typ

–

Max

Units

µs

Conditions

SID83^[6]

T_RESETWIDTHReset pulse width

–

3

–

Wake-up time from reset

release

BID#194^[6]T_RESETWAKE

–

ms

Note

6. Guaranteed by characterization.

Datasheet

17

001-92145 Rev. *L

2023-01-19

Automotive PSoC™ 4: PSoC™ 4000

Based on Arm® Cortex®-M0 CPU

Electrical Specifications

6.3

Analog peripherals

6.3.1

Comparator

Table 9

Comparator DC specifications

Details/

Spec ID# Parameter

Description

Min Typ

Max

Units

Conditions

Block current, High Bandwidth

mode

SID330^[7]

SID331^[7]

SID332^[7]

–

I_CMP1

–

110

85

µA

I_CMP2

Block current, Low Power mode

Offset voltage, High Bandwidth

mode

V_OFFSET1

10

30

mV

Offset voltage, Low Power

mode

SID333^[7]

SID334^[7]

–

V_OFFSET2

Z_CMP

–

10

–

30

–

V

DC input impedance of

comparator

35

MΩ

Max input

voltage is lower

of 3.6 V or V_DD

SID338^[7]

VINP_COMP Comparator input range

0

–

3.6

V

Table 10

Comparator AC specifications (Guaranteed by characterization)

Details/

Spec ID# Parameter

Description

Min

–

Typ

–

Max

90

Units

ns

Conditions

Response Time High Bandwidth

mode, 50-mV overdrive

SID336^[7]

T_COMP1

–

Response Time Low Power

mode, 50-mV overdrive

SID337^[7]

T_COMP2

–

110

ns

Note

7. Guaranteed by characterization.

Datasheet

18

001-92145 Rev. *L

2023-01-19

Automotive PSoC™ 4: PSoC™ 4000

Based on Arm® Cortex®-M0 CPU

Electrical Specifications

6.3.2

CSD

Table 11

CSD and IDAC Block Specifications

Spec ID#

Parameter

Description

Min Typ

Max

Units Details/Conditions

CSD and IDAC Specifications

V_DD>2V(withripple),

mV 25 °C T_A,

Max allowed ripple on

SYS.PER#3

VDD_RIPPLE

–

±50

power supply, DC to 10 MHz

Sensitivity = 0.1 pF

V_DD> 1.75V (with

ripple), 25 C T_A,

Max allowed ripple on

SYS.PER#16 VDD_RIPPLE_1.8

SID.CSD#15 VREF

±25

1.3

mV Parasitic Capaci-

tance (C_P) < 20 pF,

Sensitivity ≥ 0.4 pF

power supply, DC to 10 MHz

Voltage reference for CSD

and Comparator

1.1 1.2

V

–

SID.CSD#16 IDAC1IDD

SID.CSD#17 IDAC2IDD

IDAC1 (8-bits) block current

IDAC2 (7-bits) block current

–

1125

µA

–

1.8 V ±5% or 1.8 V to

5.5 V

1.71

1.75

0.8

–

5.5

V

SID308

V_CSD

Voltage range of operation

-40 °C TA 125 °C

Voltage compliance range

of IDAC

SID308A

VCOMPIDAC

V_DD– 0.8

–

SID309

SID310

SID311

SID312

IDAC1_DNL

IDAC1_INL

IDAC2_DNL

IDAC2_INL

DNL for 8-bit resolution

INL for 8-bit resolution

DNL for 7-bit resolution

INL for 7-bit resolution

–1

–3

–1

–3

–

1

3

1

3

LSB

–

Ratio of counts of finger to

noise. Guaranteed by

characterization

Capacitance range of

SID313

SNR

5

–

Ratio 9 to 35 pF, 0.1 pF

sensitivity

Output current of IDAC1 (8

bits) in high range

SID314

SID314A

SID315

SID315A

IDAC1_CRT1

IDAC1_CRT2

IDAC2_CRT1

IDAC2_CRT2

–

612

306

–

µA

–

Output current of IDAC1(8

bits) in low range

Output current of IDAC2 (7

bits) in high range

304.8

152.4

Output current of IDAC2 (7

bits) in low range

SID320

SID321

SID322

IDAC_OFFSET

IDAC_GAIN

All zeroes input

–

±1

±10

7

LSB

%

–

Full-scale error less offset

Mismatch between IDACs

IDAC_MISMATCH

LSB

Settling time to 0.5 LSB for

8-bit IDAC

Full-scale transition.

No external load.

SID323

SID324

SID325

IDAC_SET8

IDAC_SET7

CMOD

–

10

–

µs

nF

Settling time to 0.5 LSB for

7-bit IDAC

Full-scale transition.

No external load.

External modulator

capacitor.

5-V rating,

2.2

X7R or NP0 cap.

Datasheet

19

001-92145 Rev. *L

2023-01-19

Automotive PSoC™ 4: PSoC™ 4000

Based on Arm® Cortex®-M0 CPU

Electrical Specifications

6.4

Digital peripherals

6.4.1

Timer counter pulse-width modulator (TCPWM)

Table 12

TCPWM specifications

Spec ID

Parameter

Description

Min

Typ

Max Units Details/Conditions

Block current

SID.TCPWM.1 ITCPWM1

SID.TCPWM.2 ITCPWM2

SID.TCPWM.2A ITCPWM3

–

45

145

160

Fc

µA All modes (TCPWM)

consumption at 3 MHz

Block current

consumption at 8 MHz

Block current

consumption at 16 MHz

–

Fc max = CLK_SYS.

MHz

TCPWM_FREQ

TPWM_ENEXT

SID.TCPWM.3

SID.TCPWM.4

Operating frequency

–

Maximum = 16 MHz

For all trigger

Input trigger pulse width

2/Fc

–

ns

events^[8]

Minimum

possible

width of Overflow,

Underflow, and CC

Output trigger pulse

widths

TPWM_EXT

SID.TCPWM.5

2/Fc

–

ns

(Counter

Compare

outputs

equals

value)

Minimum

time

TC_RES

PWM_RES

Q_RES

SID.TCPWM.5A

SID.TCPWM.5B

SID.TCPWM.5C

Resolution of counter

PWM resolution

1/Fc

–

ns between successive

counts

Minimum pulse width

of PWM Output

Minimum pulse width

ns between Quadrature

phase inputs.

ns

Quadrature inputs

resolution

6.4.2

Table 13

I²C

Fixed I²C DC specifications^[8]

Spec ID

Parameter

I_I2C1

Description

Min

Typ

Max Units Details/Conditions

SID149

Block current

consumption at 100 kHz

–

25

135

2.5

µA

–

SID150

SID152

I_I2C2

I_I2C4

Block current

consumption at 400 kHz

I²C enabled in Deep Sleep

mode

–

Table 14

Fixed I²C AC specifications^[8]

Spec ID

Parameter

Description

Min

Typ

Max Units Details/Conditions

SID153

F_I2C1

Bit rate

–

400 Kbps –

Note

8. Guaranteed by characterization.

Datasheet

20

001-92145 Rev. *L

2023-01-19

Automotive PSoC™ 4: PSoC™ 4000

Based on Arm® Cortex®-M0 CPU

Electrical Specifications

6.5

Memory

Table 15

Flash DC specifications

Spec ID

Parameter

V_PE

Flash AC specifications

Description

Min

1.71

1.75

Typ

–

Max

5.5

Units Details/Conditions

V

–

SID173

Erase and program voltage

–

5.5

-40 °C TA 125 °C

Table 16

Spec ID

Parameter

Description

Min

–

Typ

–

Max

20

13

7

Units Details/Conditions

Row (block) write time

(erase and program)

Row (block) =

ms

[9]

SID174

SID175

SID176

SID178

SID180^[10]T_DEVPROG

SID181^[10]F_END

T_ROWWRITE

128 bytes

[9]

T_ROWERASE

Row erase time

–

ms

–

Row program time after

erase

[9]

T_ROWPROGRAM

–

[9]

T_BULKERASE

Bulk erase time (16 KB)

Total device program time

Flash endurance

–

15

[9]

7.5 seconds –

100 K

–

cycles

–

Flash retention. T_A 55 °C,

SID182^[10]F_RET

20^[11]

–

years

–

100 K P/E cycles

Flash retention. T_A 85 °C,

10 K P/E cycles

SID182A^[10]

10^[12]

–

years

–

6.6

System resources

Power-on reset (POR)

6.6.1

Table 17

Power-on reset (PRES)

Spec ID

Parameter Description

Min

Typ

Max

Unit

Details/Conditions

SID.CLK#6 SR_POWER

Power supply slew rate

1

–

67

V/ms On power-up and

power-down

SID185^[10]V_RISEIPOR

SID186^[10]V_FALLIPOR

Rising trip voltage

Falling trip voltage

0.80

0.70

–

1.5

1.4

V

–

Table 18

Spec ID

Brown-out detect (BOD) for V_CCD

Parameter

Description

Min

Typ

–

Max

1.62

1.5

Unit

Details/Conditions

BOD trip voltage in active and

sleep modes

BOD trip voltage in Deep Sleep 1.11

SID190^[10]V_FALLPPOR

SID192^[10]V_FALLDPSLP

1.48

V

–

Notes

9. It can take as much as 20 milliseconds to write to Flash. During this time the device should not be Reset, or Flash operations

will be interrupted and cannot be relied on to have completed. Reset sources include the XRES pin, software resets, CPU

lockup states and privilege violations, improper power supply levels, and watchdogs. Make certain that these are not

inadvertently activated.

10.Guaranteed by characterization.

11.Infineon provides a retention calculator to calculate the retention lifetime based on customers' individual temperature

profiles for operation over the –40 °C to +125 °C ambient temperature range. Contact https://www.infineon.com/sup-

port.

12.Infineon provides a retention calculator to calculate the retention lifetime based on customers' individual temperature

profiles for operation over the –40 °C to +125 °C ambient temperature range. Contact https://www.infineon.com/sup-

port.

Datasheet

21

001-92145 Rev. *L

2023-01-19

Automotive PSoC™ 4: PSoC™ 4000

Based on Arm® Cortex®-M0 CPU

Electrical Specifications

6.6.2

SWD interface

Table 19

SWD interface specifications

Details/

Spec ID

SID213

Parameter

F_SWDCLK1

F_SWDCLK2

Description

Min

–

Typ

–

Max

14

Units

MHz

Conditions

SWDCLK ≤ 1/3 CPU

clock frequency

3.3 V  V_DD 5.5 V

SWDCLK ≤ 1/3 CPU

clock frequency

SID214

1.71 V  V_DD 3.3 V

–

7

SID215^[13]T_SWDI_SETUP T = 1/f SWDCLK

SID216^[13]T_SWDI_HOLD T = 1/f SWDCLK

SID217^[13]T_SWDO_VALID T = 1/f SWDCLK

SID217A^[13]T_SWDO_HOLD T = 1/f SWDCLK

0.25 × T

–

ns

–

0.25 × T

–

0.5 × T

–

1

6.6.3

Internal main oscillator

Table 20

IMO DC specifications

(Guaranteed by Design)

Spec ID

Parameter

I_IMO1

Description

Min

Typ

Max

Units Details/Conditions

SID218

IMO operating current at 48

MHz

–

250

µA

-40 °C TA 85 °C

SID219

I_IMO2

IMO operating current at 24

MHz

–

180

µA

-40 °C TA 85 °C

Table 21

Spec ID

IMO AC specifications

Parameter

F_IMOTOL1

Description

Min

Typ

Max

Units Details/Conditions

Frequency variation at 24

and 32 MHz (trimmed)

2 V  V_DD 5.5 V, and

%

SID223

–

±2

–25 °C  T_A 85 °C

Frequency variation

(trimmed)

SID223A F_IMOTOLVCCD

–

±4

%

All

SID226

SID228

T_STARTIMO

IMO startup time

–

7

–

µs

ps

–

T_JITRMSIMO2

RMS jitter at 24 MHz

145

Note

13.Guaranteed by characterization.

Datasheet

22

001-92145 Rev. *L

2023-01-19

Automotive PSoC™ 4: PSoC™ 4000

Based on Arm® Cortex®-M0 CPU

Electrical Specifications

6.6.4

Internal low-speed oscillator

Table 22

ILO DC specifications

(Guaranteed by Design)

Spec ID

Parameter

Description

ILO operating current

ILO leakage current

Min

–

Typ

0.3

2

Max

1.05

15

Units Details/Conditions

SID231^[14]I_ILO1

µA

nA

-40 °C TA 85 °C

SID233^[14]I_ILOLEAK

–

Table 23

Spec ID

SID234^[14]T_STARTILO1

SID236^[14]T_ILODUTY

ILO AC Specifications

Parameter

Description

ILO startup time

ILO duty cycle

Min

–

Typ

–

Max

2

Units Details/Conditions

ms

%

-40 °C TA 85 °C

40

20

50

40

60

80

SID237

F_ILOTRIM1

ILO frequency range

kHz -40 °C TA 85 °C

6.6.5

External clock

Table 24

External clock specifications

Spec ID

Parameter Description

Min

Typ

Max

Units Details/Conditions

SID305^[14]ExtClkFreq

SID306^[14]ExtClkDuty

External clock input

frequency

0

–

16

MHz

–

Duty cycle; measured at V_DD/2

45

–

55

%

–

6.6.6

Block

Table 25

Block specs

Spec ID

Parameter

Description

Min

Typ

Max

Units Details/Conditions

SID262^[14]T_CLKSWITCH

System clock source

switching time

3

–

4

Periods –

Note

14.Guaranteed by characterization.

Datasheet

23

001-92145 Rev. *L

2023-01-19

Automotive PSoC™ 4: PSoC™ 4000

Based on Arm® Cortex®-M0 CPU

Ordering information

7

Ordering information

The PSoC™ 4000 part numbers and features are listed in the following table.

Operating

Features

Package

temperature

MPN

CY8C4014SXA-421Z

CY8C4014LQA-422Z

CY8C4014SXS-421Z

CY8C4014LQS-422Z

CY8C4014SXE-421Z^[15]

CY8C4014LQE-422Z

16

2

✔

1

✔

–

✔

–

✔

–

✔

–

✔

–

✔

–

✔

–

7.1

Part numbering conventions

PSoC™ 4 devices follow the part numbering convention described in the following table. All fields are

single-character alphanumeric (0, 1, 2, …, 9, A,B, …, Z) unless stated otherwise.

The part numbers are of the form CY8C4ABCDEF-XYZ where the fields are defined as follows.

CY 8C

4

A B C D E F

- G H I

Z

Examples

Cypress (an Infineon

company) Prefix

4 :PSoC™4

0 : 4000 Family

1 : 16 MHz

Architecture

Family Group within Architecture

Speed Grade

4 : 16 KB

Flash Capacity

LQ: QFN

SX : SOIC

Package Code

A: AEC-Q100, -40 °C to +85 °C

S: AEC-Q100, -40 °C to +105 °C

E: AEC-Q100, -40 °C to +125 °C

Temperature Range

Peripheral Set

Fab Location Indicator

Z = New fab location

Blank = Initial fab location

Note

15.Contact Infineon for availability of this device.

Datasheet

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Automotive PSoC™ 4: PSoC™ 4000

Based on Arm® Cortex®-M0 CPU

Ordering information

The field values are listed in the following table:

Field

Description

Values

Meaning

CY8C

Cypress (an Infineon

company) prefix

4

A

B

Architecture

Family

CPU speed

4

0

1

PSoC™ 4

4000 Family

16 MHz

4

48 MHz

C

Flash capacity

Package code

3

4

5

6

7

8 KB

16 KB

32 KB

64 KB

128 KB

SOIC

DE

SX

LQ

QFN

F

GHI

Z

Temperature range

Attributes code

Fab location change

A/S

000-999

Automotive

Code of feature set in specific family

Datasheet

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Automotive PSoC™ 4: PSoC™ 4000

Based on Arm® Cortex®-M0 CPU

Packaging

8

Packaging

Table 26

Package list

Spec ID#

BID#26

BID#40

Package

24-pin QFN

16-pin SOIC

Description

24-pin 4  4  0.6 mm QFN with 0.5-mm pitch

16-pin SOIC (150 Mil)

Table 27

Parameter

T_A

Package characteristics

Description

Conditions

Min

Typ

Max

Units

Operating ambient

temperature

For A grade devices

–40

25.00

85

°C

T_A

T_J

Operating ambient

temperature

For S grade devices

For E grade devices

For A grade devices

For S grade devices

For E grade devices

–40

25.00

105

125

100

120

140

°C

Operating ambient

temperature

25.00

Operating junction

temperature

–

Operating junction

temperature

Operating junction

temperature

T_JA

Package _JA(24-pin QFN)

Package _JA(16-pin SOIC)

–

38.01

–

°C/W

142.14

Table 28

Solder reflow peak temperature

Package Maximum peak temperature

All 260 °C

Maximum time at peak temperature

30 seconds

Table 29

Package moisture sensitivity level (MSL), IPC/JEDEC J-STD-020

Package

MSL

All

MSL 3

Datasheet

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Automotive PSoC™ 4: PSoC™ 4000

Based on Arm® Cortex®-M0 CPU

Packaging

8.1

Package outline drawings

001-13937 *H

Figure 6

24-pin QFN ((4 × 4 × 0.55 mm) 2.65 × 2.65 E-Pad (Sawn)) package outline

The center pad on the QFN package should be connected to ground (VSS) for best mechanical, thermal, and

electrical performance. If not connected to ground, it should be electrically floating and not connected to any

other signal.

Datasheet

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Based on Arm® Cortex®-M0 CPU

Packaging

51-85068 *F

Figure 7

16-pin SOIC (150 Mils) package outline

Datasheet

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Automotive PSoC™ 4: PSoC™ 4000

Based on Arm® Cortex®-M0 CPU

Acronyms

9

Acronyms

Table 30

Acronyms used in this document

Acronym

Description

abus

ADC

AG

analog local bus

analog-to-digital converter

analog global

AHB

AMBA (advanced microcontroller bus architecture) high-performance bus, an Arm data

transfer bus

ALU

arithmetic logic unit

AMUXBUS

API

analog multiplexer bus

application programming interface

application program status register

advanced RISC machine, a CPU architecture

automatic thump mode

APSR

Arm^®

ATM

BW

bandwidth

CAN

CMRR

CPU

CRC

Controller Area Network, a communications protocol

common-mode rejection ratio

central processing unit

cyclic redundancy check, an error-checking protocol

digital-to-analog converter, see also IDAC, VDAC

digital filter block

DAC

DFB

DIO

digital input/output, GPIO with only digital capabilities, no analog. See GPIO.

Dhrystone million instructions per second

direct memory access, see also TD

differential nonlinearity, see also INL

do not use

DMIPS

DMA

DNL

DNU

DR

port write data registers

DSI

digital system interconnect

DWT

ECC

data watchpoint and trace

error correcting code

ECO

EEPROM

EMI

external crystal oscillator

electrically erasable programmable read-only memory

electromagnetic interference

external memory interface

EMIF

EOC

EOF

end of conversion

end of frame

EPSR

ESD

execution program status register

electrostatic discharge

ETM

FIR

embedded trace macrocell

finite impulse response, see also IIR

Datasheet

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Based on Arm® Cortex®-M0 CPU

Acronyms

Table 30

Acronyms used in this document ^(continued)

Acronym

Description

FPB

FS

flash patch and breakpoint

full-speed

GPIO

HVI

general-purpose input/output, applies to a PSoC™ pin

high-voltage interrupt, see also LVI, LVD

integrated circuit

IC

IDAC

IDE

current DAC, see also DAC, VDAC

integrated development environment

Inter-Integrated Circuit, a communications protocol

infinite impulse response, see also FIR

internal low-speed oscillator, see also IMO

internal main oscillator, see also ILO

integral nonlinearity, see also DNL

input/output, see also GPIO, DIO, SIO, USBIO

initial power-on reset

I²C, or IIC

IIR

ILO

IMO

INL

I/O

IPOR

IPSR

IRQ

interrupt program status register

interrupt request

ITM

instrumentation trace macrocell

liquid crystal display

LCD

LIN

Local Interconnect Network, a communications protocol.

link register

LR

LUT

LVD

lookup table

low-voltage detect, see also LVI

low-voltage interrupt, see also HVI

low-voltage transistor-transistor logic

multiply-accumulate

LVI

LVTTL

MAC

MCU

MISO

NC

microcontroller unit

master-in slave-out

no connect

NMI

NRZ

NVIC

NVL

opamp

PAL

nonmaskable interrupt

non-return-to-zero

nested vectored interrupt controller

nonvolatile latch, see also WOL

operational amplifier

programmable array logic, see also PLD

program counter

PC

PCB

PGA

PHUB

printed circuit board

programmable gain amplifier

peripheral hub

Datasheet

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Based on Arm® Cortex®-M0 CPU

Acronyms

Table 30

Acronyms used in this document ^(continued)

Acronym

Description

PHY

PICU

PLA

physical layer

port interrupt control unit

programmable logic array

PLD

PLL

programmable logic device, see also PAL

phase-locked loop

PMDD

POR

PRES

PRS

PS

package material declaration data sheet

power-on reset

precise power-on reset

pseudo random sequence

port read data register

PSoC™

PSRR

PWM

RAM

RISC

RMS

RTC

RTL

Programmable System-on-Chip

power supply rejection ratio

pulse-width modulator

random-access memory

reduced-instruction-set computing

root-mean-square

real-time clock

register transfer language

remote transmission request

receive

RTR

RX

SAR

SC/CT

SCL

successive approximation register

switched capacitor/continuous time

I²C serial clock

SDA

S/H

I²C serial data

sample and hold

SINAD

SIO

signal to noise and distortion ratio

special input/output, GPIO with advanced features. See GPIO.

start of conversion

SOC

SOF

SPI

start of frame

Serial Peripheral Interface, a communications protocol

slew rate

SR

SRAM

SRES

SWD

SWV

TD

static random access memory

software reset

serial wire debug, a test protocol

single-wire viewer

transaction descriptor, see also DMA

total harmonic distortion

transimpedance amplifier

THD

TIA

Datasheet

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Based on Arm® Cortex®-M0 CPU

Acronyms

Table 30

Acronyms used in this document ^(continued)

Acronym

Description

TRM

TTL

technical reference manual

transistor-transistor logic

transmit

TX

UART

UDB

USB

Universal Asynchronous Transmitter Receiver, a communications protocol

universal digital block

Universal Serial Bus

USBIO

VDAC

WDT

WOL

WRES

XRES

XTAL

USB input/output, PSoC™ pins used to connect to a USB port

voltage DAC, see also DAC, IDAC

watchdog timer

write once latch, see also NVL

watchdog timer reset

external reset I/O pin

crystal

Datasheet

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Based on Arm® Cortex®-M0 CPU

Document conventions

10

Document conventions

10.1

Units of measure

Table 31

Units of measure

Symbol

°C

dB

Unit of measure

degrees Celsius

decibel

fF

Hz

femto farad

hertz

KB

1024 bytes

kbps

Khr

kHz

k

ksps

LSB

Mbps

MHz

M

Msps

µA

kilobits per second

kilohour

kilohertz

kilo ohm

kilosamples per second

least significant bit

megabits per second

megahertz

mega-ohm

megasamples per second

microampere

microfarad

µF

µH

µs

µV

microhenry

microsecond

microvolt

µW

mA

ms

mV

nA

microwatt

milliampere

millisecond

millivolt

nanoampere

nanosecond

nanovolt

ns

nV



ohm

pF

picofarad

ppm

ps

parts per million

picosecond

s

second

sps

sqrtHz

V

samples per second

square root of hertz

volt

W

watt

Datasheet

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Based on Arm® Cortex®-M0 CPU

Revision history

Document

Date

revision

Description of changes

**

2014-05-23

New data sheet for new device family.

Changed status from Advance to Preliminary.

Updated Electrical Specifications:

Updated Device Level Specifications:

^{Updated description above}Table 3.

*A

2014-07-23

Updated Memory:

Updated Table 16:

Added Note 10 and referred the same note in minimum value of SID182 spec.

Added Note 13 and referred the same note in minimum value of SID182A spec.

Updated Electrical Specifications:

^UpdatedDevice Level Specifications:

^UpdatedTable 3:

Updated entire table.

^UpdatedAnalog peripherals:

^UpdatedComparator:

^UpdatedTable 9:

Added maximum value of I_CMP1parameter as 110 µA.

Added maximum value of I_CMP2parameter as 85 µA.

^UpdatedTable 10:

Changed maximum value of T_COMP1parameter from 50 ns to 90 ns.

Changed maximum value of T_COMP2parameter from 100 ns to 110 ns.

Updated Digital peripherals:

Removed Timer.

^AddedTimer counter pulse-width modulator (TCPWM).

Removed Counter.

Removed Pulse Width Modulation (PWM).

^UpdatedI²C:

^UpdatedTable 13:

Changed maximum value of I_I2C1parameter from 10.5 µA to 25 µA.

Added maximum value of I_I2C4parameter as 2.5 µA.

^UpdatedPower-on reset (POR):

Updated Table 17:

*B

2014-12-12

Updated entire table.

^UpdatedMemory:

Updated Table 16:

Added maximum value of T_BULKERASEparameter as 15 ms.

Added maximum value of T_DEVPROGparameter as 7.5 seconds.

Updated System resources:

^UpdatedPower-on reset (POR):

^UpdatedTable 18:

Added maximum value of V_FALLPPORparameter as 1.62 V.

Changed minimum value of V_FALLDPSLPparameter from 1.14 V to 1.11 V.

^UpdatedInternal main oscillator:

^UpdatedTable 20:

Changed maximum value of I_IMO1parameter from 1000 µA to 250 µA.

Changed maximum value of I_IMO2parameter from 325 µA to 180 µA.

^UpdatedTable 21:

Added maximum value of T_STARTIMOparameter as 7 µs.

^UpdatedPackaging:

^UpdatedTable 27:

Added values for T_Jparameter corresponding to Condition “For A grade devices”.

Changed maximum value of T_Jparameter corresponding to Condition “For S grade devices” from 100 °C to

120 °C.

Removed T_JCparameter and its details.

*C

*D

2015-01-06

2015-02-24

Changed status from Preliminary to Final.

Updated Ordering information:

No change in part numbers.

^UpdatedPart numbering conventions.

Updated Block diagram.

Added Low Power Comparator block.

^UpdatedPinouts.

Updated Table 1.

Updated details in “Name” column of pin 14 and pin 15 corresponding to 24-pin QFN and also updated details

in “Alternate Functions” column corresponding to same pins.

Updated details in “Name” column of pin 12 and pin 13 corresponding to 16-pin SOIC and also updated details

in “Alternate Functions” column corresponding to same pins.

^UpdatedPackaging.

*E

2016-02-17

2017-06-05

Updated Package outline drawings.

spec 001-13937 – Changed revision from *E to *F.

Updated to new template.

Updated Ordering information

Updated part numbers.

*F

Updated to new template.

Completing Sunset Review.

Datasheet

34

001-92145 Rev. *L

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Automotive PSoC™ 4: PSoC™ 4000

Based on Arm® Cortex®-M0 CPU

Revision history

Document

Date

revision

Description of changes

Updated Packaging.

^UpdatedPackage outline drawings.

spec 001-13937 – Changed revision from *F to *G.

spec 51-85068 – Changed revision from *E to *F.

Removed Note “Dimensions of the QFN package drawings are in millimeters.” and its reference.

Updated to new template.

*G

2019-06-05

Completing Sunset Review.

Added Automotive-E temperature range related information in all instances across the document.

Updated Ordering information.

*H

*I

2019-07-11

2020-02-12

Updated part numbers.

Updated to new template.

Updated Electrical Specifications.

Updated Absolute Maximum Ratings.

^UpdatedTable 2.

Changed maximum value of ESD_HBM parameter from 2200 V to 2000 V.

Updated to new template.

Removed note on Grade-E specifications.

^UpdatedTable 3: Updated SID 255, SID54.

^UpdatedTable 11: Updated SID 308.

^UpdatedTable 15: Updated SID 173.

*J

2020-07-28

^UpdatedTable 20, Table 22, and Table 23: Updated Details/Conditions.

^UpdatedOrdering information: Removed note for availability of Grade-E devices. Removed note on

same silicon ID.

^UpdatedFigure 6 (001-13937 *G to *H) in Package outline drawings.

Updated SID.CLK #6 parameter.

Updated conditions for Device-Level Specification.

*K

*L

2021-10-07

2023-01-19

Product Information Notice #7235128.

^UpdatedTable 21: Removed “for A grade devices and –25 °C” from Details and conditions for SID223.

Updated to Infineon template.

Datasheet

35

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Please read the Important Notice and Warnings at the end of this document

Trademarks

All referenced product or service names and trademarks are the property of their respective owners.

IMPORTANT NOTICE

WARNINGS

The information given in this document shall in no Due to technical requirements products may contain

Edition 2023-01-19

Published by

event be regarded as a guarantee of conditions or dangerous substances. For information on the types

characteristics (“Beschaffenheitsgarantie”).

in question please contact your nearest Infineon

Technologies office.

With respect to any examples, hints or any typical

Infineon Technologies AG

81726 Munich, Germany

values stated herein and/or any information Except as otherwise explicitly approved by Infineon

regarding the application of the product, Infineon Technologies in

a

written document signed by

Technologies hereby disclaims any and all authorized

representatives of Infineon

warranties and liabilities of any kind, including Technologies, Infineon Technologies’ products may

without limitation warranties of non-infringement of not be used in any applications where a failure of the

intellectual property rights of any third party.

product or any consequences of the use thereof can

reasonably be expected to result in personal injury.

In addition, any information given in this document

is subject to customer’s compliance with its

obligations stated in this document and any

applicable legal requirements, norms and standards

concerning customer’s products and any use of the

product of Infineon Technologies in customer’s

applications.

Do you have a question about this

document?

Email:

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The data contained in this document is exclusively

intended for technically trained staff. It is the

responsibility of customer’s technical departments

to evaluate the suitability of the product for the

intended application and the completeness of the

product information given in this document with

respect to such application.

Document reference

001-92145 Rev. *L


型号：	CY8C4014SXS-421Z
厂家：	Infineon
描述：	Automotive PSoC™ 4000
文件：	总36页 (文件大小：668K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

CY8C4014SXS-421Z [INFINEON]

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