CY8C4024PVA-S412 [INFINEON]
Automotive PSoC™ 4000S;
| 型号： | CY8C4024PVA-S412 |
| 厂家： | 
Infineon |
| 描述： | Automotive PSoC™ 4000S |
| 文件： | 总49页 (文件大小：508K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY8C40xx
Automotive PSoC™ 4: PSoC™ 4000S family
datasheet
Based on Arm® Cortex®-M0+ CPU
General description
PSoC™ 4 is a scalable and reconfigurable platform architecture for a family of programmable embedded system
controllers with an Arm® Cortex®-M0+ CPU while being AEC-Q100 compliant. It combines programmable and
reconfigurable analog and digital blocks with flexible automatic routing. The PSoC™ 4000S product family is a
member of the PSoC™ 4 platform architecture. It is a combination of a microcontroller with standard communi-
cation and timing peripherals, a capacitive touch-sensing system (CAPSENSE™) with best-in-class performance,
programmable general-purpose continuous-time and switched-capacitor analog blocks, and programmable
connectivity. PSoC™ 4000S products will be upward compatible with members of the PSoC™ 4 platform for new
applications and design needs.
Features
• Automotive Electronics Council (AEC) AEC-Q100 Qualified
• 32-bit MCU subsystem
- 48-MHz Arm® Cortex®-M0+ CPU
- Up to 32 KB of flash with read accelerator
- Up to 4 KB of SRAM
• Programmable analog
- Single-slope 10-bit ADC function provided by capacitance sensing block
- Two current DACs (IDACs) for general-purpose or capacitive sensing applications on any pin
- Two low-power comparators that operate in Deep Sleep low-power mode
• Programmable digital
- Programmable logic blocks allowing Boolean operations to be performed on port inputs and outputs
• Low-power 1.71-V to 5.5-V operation
- Deep Sleep mode with operational analog and 2.5 µA digital system current
• Capacitive sensing
- Capacitive sigma-delta (CSD) provides best-in-class signal-to-noise ratio (SNR) (>5:1) and water tolerance
- Infineon-supplied software component makes capacitive sensing design easy
- Automatic hardware tuning (SmartSense)
• Serial communication
- Two independent run-time reconfigurable serial communication blocks (SCBs) with re-configurable I2C, SPI,
or UART functionality
• LCD drive capability
- LCD segment drive capability on GPIOs
• Timing and pulse-width modulation
- Five 16-bit timer/counter/pulse-width modulator (TCPWM) blocks
- Center-aligned, Edge, and pseudo-random modes
- Comparator-based triggering of Kill signals for motor drive and other high-reliability digital logic applications
• Up to 24 programmable GPIO pins
- 24-pin QFN, 28-pin SSOP, 40-pin QFN, and 48-pin QFN packages
- Any GPIO pin can be CAPSENSE™, analog, or digital
- Drive modes, strengths, and slew rates are programmable
Datasheet
www.infineon.com
Please read the Important Notice and Warnings at the end of this document
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Automotive PSoC™ 4: PSoC™ 4000S family datasheet
Based on Arm® Cortex®-M0+ CPU
Features
• PSoC™ Creator design environment
- Integrateddevelopment environment (IDE)providesschematicdesign entry andbuild (with analogand digital
automatic routing)
- Applications programming interface (API) component for all fixed-function and programmable peripherals
• Industry-standard tool compatibility
- After schematic entry, development can be done with Arm®-based industry-standard development tools
• Temperature range
- A-Grade: –40°C to +85°C
- E-Grade: –40°C to +125°C
- S-Grade: –40°C to +105°C
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Automotive PSoC™ 4: PSoC™ 4000S family datasheet
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Table of contents
Table of contents
General description ...........................................................................................................................1
Features ...........................................................................................................................................1
Table of contents...............................................................................................................................3
Block diagram...................................................................................................................................5
1 Functional definition.......................................................................................................................7
1.1 CPU and memory subsystem .................................................................................................................................7
1.1.1 CPU .......................................................................................................................................................................7
1.1.2 Flash .....................................................................................................................................................................7
1.1.3 SRAM.....................................................................................................................................................................7
1.1.4 SROM ....................................................................................................................................................................7
1.2 System resources....................................................................................................................................................7
1.2.1 Power system.......................................................................................................................................................7
1.2.2 Clock system ........................................................................................................................................................8
1.2.3 IMO clock source ..................................................................................................................................................8
1.2.4 ILO clock source...................................................................................................................................................8
1.2.5 Watch Crystal Oscillator (WCO) ...........................................................................................................................8
1.2.6 Watchdog timer....................................................................................................................................................9
1.2.7 Reset .....................................................................................................................................................................9
1.2.8 Voltage reference.................................................................................................................................................9
1.3 Analog blocks ..........................................................................................................................................................9
1.3.1 Low-power comparators (LPC) ...........................................................................................................................9
1.3.2 Current DACs ........................................................................................................................................................9
1.3.3 Analog multiplexed buses ...................................................................................................................................9
1.4 Programmable digital blocks.................................................................................................................................9
1.5 Fixed function digital blocks ..................................................................................................................................9
1.5.1 Timer/Counter/PWM (TCPWM) Block..................................................................................................................9
1.5.2 Serial Communication Block (SCB)...................................................................................................................10
1.6 GPIO.......................................................................................................................................................................11
1.7 Special function peripherals ................................................................................................................................12
1.7.1 CAPSENSE™........................................................................................................................................................12
1.7.2 LCD segment drive.............................................................................................................................................12
2 Pinouts ........................................................................................................................................13
2.1 Alternate pin functions .........................................................................................................................................16
3 Power ..........................................................................................................................................18
3.1 Mode 1: 1.8 V to 5.5 V external supply..................................................................................................................18
3.2 Mode 2: 1.8 V ±5% external supply.......................................................................................................................19
4 Development support ...................................................................................................................20
4.1 Documentation .....................................................................................................................................................20
4.2 Online ....................................................................................................................................................................20
4.3 Tools ......................................................................................................................................................................20
5 Electrical specifications.................................................................................................................21
5.1 Absolute maximum ratings .................................................................................................................................21
5.2 Device level specifications....................................................................................................................................21
5.2.1 GPIO....................................................................................................................................................................23
5.2.2 XRES ...................................................................................................................................................................24
5.3 Analog peripherals................................................................................................................................................25
5.3.1 CSD .....................................................................................................................................................................26
5.4 Digital peripherals.................................................................................................................................................30
5.4.1 Timer Counter Pulse-Width Modulator (TCPWM).............................................................................................30
5.4.2 I2C .......................................................................................................................................................................30
5.5 Memory..................................................................................................................................................................32
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Table of contents
5.6 System resources..................................................................................................................................................33
5.6.1 Power-on reset (POR) ........................................................................................................................................33
5.6.2 SWD Interface ....................................................................................................................................................33
5.6.3 Internal Main Oscillator .....................................................................................................................................34
5.6.4 Internal Low-Speed Oscillator .........................................................................................................................35
6 Ordering Information....................................................................................................................36
7 Packaging ....................................................................................................................................38
7.1 Package diagrams.................................................................................................................................................39
8 Acronyms.....................................................................................................................................43
9 Document conventions..................................................................................................................47
9.1 Units of measure ...................................................................................................................................................47
Revision history ..............................................................................................................................48
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Block diagram
Block diagram
CPU Subsystem
PSoC™4000S
Architecture
SWD /TC
Cortex®
M0+
SPCIF
FLASH
32 KB
SRAM
4 KB
ROM
8 KB
32-bit
48 MHz
FAST MUL
NVIC, IRQMUX
AHB- Lite
Read Accelerator
SRAM Controller
ROM Controller
System Resources
Lite
System Interconnect (Single Layer AHB)
Peripheral Interconnect (MMIO)
Power
Sleep Control
WIC
Peripherals
PCLK
POR
REF
PWRSYS
Clock
Clock Control
WDT
ILO
IMO
Reset
Reset Control
XRES
Test
TestMode Entry
Digital DFT
Analog DFT
High Speed I/ O Matrix & 2x Programmable I/O
24x GPIOs, LCD
Power Modes
Active/ Sleep
DeepSleep
I/O Subsystem
PSoC™ 4000S devices include extensive support for programming, testing, debugging, and tracing both hardware
and firmware.
The Arm® Serial-Wire Debug (SWD) interface supports all programming and debug features of the device.
Complete debug-on-chip functionality enables full-device debugging in the final system using the standard
production device. It does not require special interfaces, debugging pods, simulators, or emulators. Only the
standard programming connections are required to fully support debug.
The PSoC™ Creator IDE provides fully integrated programming and debug support for the PSoC™ 4000S devices.
The SWD interface is fully compatible with industry-standard third-party tools. The PSoC™ 4000S family provides
a level of security not possible with multi-chip application solutions or with microcontrollers. It has the following
advantages:
• Allows disabling of debug features
• Robust flash protection
• Allows customer-proprietary functionality to be implemented in on-chip programmable blocks
The debug circuits are enabled by default and can be disabled in firmware. If they are not enabled, the only way
to re-enable them is to erase the entire device, clear flash protection, and reprogram the device with new
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Block diagram
firmware that enables debugging. Thus firmware control of debugging cannot be over-ridden without erasing the
firmware thus providing security.
Additionally, all device interfaces can be permanently disabled (device security) for applications concerned
about phishing attacks due to a maliciously reprogrammed device or attempts to defeat security by starting and
interrupting flash programming sequences. All programming, debug, and test interfaces are disabled when
maximum device security is enabled. Therefore, PSoC™ 4000S, with device security enabled, may not be returned
for failure analysis. This is a trade-off the PSoC™ 4000S allows the customer to make.
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Functional definition
1
Functional definition
CPU and memory subsystem
CPU
1.1
1.1.1
The Cortex®-M0+ CPU in the PSoC™ 4000S is part of the 32-bit MCU subsystem, which is optimized for low-power
operation with extensive clock gating. Most instructions are 16 bits in length and the CPU executes a subset of
the Thumb-2 instruction set. It includes a nested vectored interrupt controller (NVIC) block with eight interrupt
inputs and also includes a Wakeup Interrupt Controller (WIC). The WIC can wake the processor from Deep Sleep
mode, allowing power to be switched off to the main processor when the chip is in Deep Sleep mode.
The CPU also includes a debug interface, the serial wire debug (SWD) interface, which is a two-wire form of JTAG.
The debug configuration used for PSoC™ 4000S has four breakpoint (address) comparators and two watchpoint
(data) comparators.
1.1.2
Flash
The PSoC™ 4000S device has a flash module with a flash accelerator, tightly coupled to the CPU to improve
average access times from the flash block. The low-power flash block is designed to deliver two wait-state (WS)
access time at 48 MHz. The flash accelerator delivers 85% of single-cycle SRAM access performance on average.
1.1.3
SRAM
Four KB of SRAM are provided with zero wait-state access at 48 MHz.
1.1.4
SROM
A supervisory ROM that contains boot and configuration routines is provided.
1.2
System resources
Power system
1.2.1
The power system is described in detail in the Power section. It provides assurance that voltage levels are as
required for each respective mode and either delays mode entry (for example, on power-on reset (POR)) until
voltage levels are as required for proper functionality, or generates resets (for example, on brown-out detection).
The PSoC™ 4000S operates with a single external supply over the range of either 1.8 V ±5% (externally regulated)
or 1.8 to 5.5 V (internally regulated) and has three different power modes, transitions between which are
managed by the power system. The PSoC™ 4000S provides Active, Sleep, and Deep Sleep low-power modes.
All subsystems are operational in Active mode. The CPU subsystem (CPU, flash, and SRAM) is clock-gated off in
Sleep mode, while all peripherals and interrupts are active with instantaneous wake-up on a wake-up event. In
Deep Sleep mode, the high-speed clock and associated circuitry is switched off; wake-up from this mode takes
35 µs. The opamps can remain operational in Deep Sleep mode.
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Functional definition
1.2.2
Clock system
The PSoC™ 4000S clock system is responsible for providing clocks to all subsystems that require clocks and for
switching between different clock sources without glitching. In addition, the clock system ensures that there are
no metastable conditions.
The clock system for the PSoC™ 4000S consists of the internal main oscillator (IMO), internal low-frequency oscil-
lator (ILO), a 32 kHz Watch Crystal Oscillator (WCO) and provision for an external clock. Clock dividers are
provided to generate clocks for peripherals on a fine-grained basis. Fractional dividers are also provided to
enable clocking of higher data rates for UARTs.
The HFCLK signal can be divided down to generate synchronous clocks for the analog and digital peripherals.
There are eight clock dividers for the PSoC™ 4000S, two of those are fractional dividers. The 16-bit capability
allows flexible generation of fine-grained frequency values, and is fully supported in PSoC™ Creator.
IMO
HFCLK
Divide By
2,4,8
External Clock
ILO
LFCLK
HFCLK
Prescaler
SYSCLK
Integer
Dividers
6X 16-bit
Fractional
Dividers
2X 16.5-bit
Figure 1
PSoC™ 4000S MCU Clocking architecture
1.2.3
IMO clock source
The IMO is the primary source of internal clocking in the PSoC™ 4000S. It is trimmed during testing to achieve the
specified accuracy.The IMO default frequency is 24 MHz and it can be adjusted from 24 to 48 MHz in steps of 4
MHz. The IMO tolerance with Infineon-provided calibration settings is ±2%.
1.2.4
ILO clock source
The ILO is a very low power, nominally 40-kHz oscillator, which is primarily used to generate clocks for the
watchdog timer (WDT) and peripheral operation in Deep Sleep mode. ILO-driven counters can be calibrated to
the IMO to improve accuracy. Infineon provides a software component, which does the calibration.
1.2.5
Watch Crystal Oscillator (WCO)
The PSoC™ 4000S clock subsystem also implements a low-frequency (32-kHz watch crystal) oscillator that can
be used for precision timing applications.
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Functional definition
1.2.6
Watchdog timer
A watchdog timer is implemented in the clock block running from the ILO; this allows watchdog operation during
Deep Sleep and generates a watchdog reset if not serviced before the set timeout occurs. The watchdog reset is
recorded in a Reset Cause register, which is firmware readable.
1.2.7
Reset
The PSoC™ 4000S can be reset from a variety of sources including a software reset. Reset events are asynchronous
and guarantee reversion to a known state. The reset cause is recorded in a register, which is sticky through reset
and allows software to determine the cause of the reset. An XRES pin is reserved for external reset by asserting it
active low. The XRES pin has an internal pull-up resistor that is always enabled.
1.2.8
Voltage reference
The PSoC™ 4000S reference system generates all internally required references. A 1.2-V voltage reference is
provided for the comparator. The IDACs are based on a ±5% reference.
1.3
Analog blocks
1.3.1
Low-power comparators (LPC)
The PSoC™ 4000S has a pair of low-power comparators, which can also operate in Deep Sleep modes. This allows
the analog system blocks to be disabled while retaining the ability to monitor external voltage levels during
low-power modes. The comparator outputs are normally synchronized to avoid metastability unless operating
in an asynchronous power mode where the system wake-up circuit is activated by a comparator switch event.
The LPC outputs can be routed to pins.
1.3.2
Current DACs
The PSoC™ 4000S has two IDACs, which can drive any of the pins on the chip. These IDACs have programmable
current ranges.
1.3.3
Analog multiplexed buses
The PSoC™ 4000S has two concentric independent buses that go around the periphery of the chip. These buses
(called amux buses) are connected to firmware-programmable analog switches that allow the chip's internal
resources (IDACs, comparator) to connect to any pin on the I/O Ports.
1.4
Programmable digital blocks
The programmable I/O (Smart I/O) block is a fabric of switches and LUTs that allows Boolean functions to be
performed in signals being routed to the pins of a GPIO port. The Smart I/O can perform logical operations on
input pins to the chip and on signals going out as outputs.
1.5
Fixed function digital blocks
1.5.1
Timer/Counter/PWM (TCPWM) Block
The TCPWM block consists of a 16-bit counter with user-programmable period length. There is a capture register
to record the count value at the time of an event (which may be an I/O event), a period register that is used to
either stop or auto-reload the counter when its count is equal to the period register, and compare registers to
generate compare value signals that are used as PWM duty cycle outputs. The block also provides true and
complementary outputs with programmable offset between them to allow use as dead-band programmable
complementary PWM outputs. It also has a Kill input to force outputs to a predetermined state; for example, this
is used in motor drive systems when an over-current state is indicated and the PWM driving the FETs needs to be
shut off immediately with no time for software intervention. There are five TCPWM blocks in the PSoC™ 4000S.
Datasheet
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Functional definition
1.5.2
Serial Communication Block (SCB)
The PSoC™ 4000S has two serial communication blocks, which can be programmed to have SPI, I2C, or UART
functionality.
I2C Mode: The hardware I2C block implements a full multi-master and slave interface (it is capable of
multi-master arbitration). This block is capable of operating at speeds of up to 1 Mbps (Fast Mode Plus) and has
flexible buffering options to reduce interrupt overhead and latency for the CPU. It also supports EZI2C that
creates a mailbox address range in the memory of the PSoC™ 4000S and effectively reduces I2C communication
to reading from and writing to an array in memory. In addition, the block supports an 8-deep FIFO for receive and
transmit which, by increasing the time given for the CPU to read data, greatly reduces the need for clock
stretching caused by the CPU not having read data on time.
The I2C peripheral is compatible with the I2C Standard-mode and Fast Mode Plus devices as defined in the NXP
I2C-bus specification and user manual (UM10204). The I2C bus I/O is implemented with GPIO in open-drain
modes.
The PSoC™ 4000S is not completely compliant with the I2C spec in the following respect:
• GPIO cells are not overvoltage tolerant and, therefore, cannot be hot-swapped or powered up independently
of the rest of the I2C system.
UART Mode: This is a full-feature UART operating at up to 1 Mbps. It supports automotive single-wire interface
(LIN), infrared interface (IrDA), and SmartCard (ISO7816) protocols, all of which are minor variants of the basic
UART protocol. In addition, it supports the 9-bit multiprocessor mode that allows addressing of peripherals
connected over common RX and TX lines. Common UART functions such as parity error, break detect, and frame
error are supported. An 8-deep FIFO allows much greater CPU service latencies to be tolerated.
SPI Mode: The SPI mode supports full Motorola SPI, TI SSP (adds a start pulse used to synchronize SPI Codecs),
and National Microwire (half-duplex form of SPI). The SPI block can use the FIFO.
LIN slave mode: The LIN slave mode uses the SCB hardware block and implements a full LIN slave interface. This
LIN Slave is compliant with LIN v1.3, v2.1/2.2, ISO 17987-6, and SAE J2602-2 specification standards. It is certified
by C&S GmbH based on the standard protocol and data link layer conformance tests. LIN slave can be operated
at baud rates of up to ~20 Kbps with a maximum of 40-meter cable length. PSoC™ Creator software supports up
to two LIN slave interfaces in the PSoC™ 4 device, providing built-in application programming interfaces (APIs)
based on the LIN specification standard.
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Functional definition
1.6
GPIO
The PSoC™ 4000S has up to 24 GPIOs. The GPIO block implements the following:
• Eight drive modes:
- Analog input mode (input and output buffers disabled)
- Input only
- Weak pull-up with strong pull-down
- Strong pull-up with weak pull-down
- Open drain with strong pull-down
- Open drain with strong pull-up
- Strong pull-up with strong pull-down
- Weak pull-up with weak pull-down
• Input threshold select (CMOS or LVTTL).
• Individual control of input and output buffer enabling/disabling in addition to the drive strength modes
• Selectable slew rates for dV/dt related noise control to improve EMI
The pins are organized in logical entities called ports, which are 8-bit in width (less for Ports 2 and 3). During
power-on and reset, the blocks are forced to the disabled state so as not to crowbar any inputs and/or cause
excess turn-on current. A multiplexing network known as a high-speed I/O matrix is used to multiplex between
various signals that may connect to an I/O pin.
Data output and pin state registers store, respectively, the values to be driven on the pins and the states of the
pins themselves.
Every I/O pin can generate an interrupt if so enabled and each I/O port has an interrupt request (IRQ) and interrupt
service routine (ISR) vector associated with it (5 for PSoC™ 4000S).
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Functional definition
1.7
1.7.1
Special function peripherals
CAPSENSE™
CAPSENSE™ is supported in the PSoC™ 4000S through a capacitive sigma-delta (CSD) block that can be
connected to any pins through an analog multiplex bus via analog switches. CAPSENSE™ function can thus be
provided on any available pin or group of pins in a system under software control. A PSoC™ Creator component
is provided for the CAPSENSE™ block to make it easy for the user.
Shield voltage can be driven on another analog multiplex bus to provide water-tolerance capability. Water
tolerance is provided by driving the shield electrode in phase with the sense electrode to keep the shield capac-
itance from attenuating the sensed input. Proximity sensing can also be implemented.
The CAPSENSE™ block has two IDACs, which can be used for general purposes if CAPSENSE™ is not being used
(both IDACs are available in that case) or if CAPSENSE™ is used without water tolerance (one IDAC is available).
The CAPSENSE™ block also provides a 10-bit Slope ADC function, which can be used in conjunction with the
CAPSENSE™ function.
The CAPSENSE™ block is an advanced, low-noise, programmable block with programmable voltage references
and current source ranges for improved sensitivity and flexibility. It can also use an external reference voltage. It
has a full-wave CSD mode that alternates sensing to VDDA and Ground to null out power-supply related noise.
1.7.2
LCD segment drive
The PSoC™ 4000S has an LCD controller, which can drive up to 4 commons and 20 segments. It uses full digital
methods to drive the LCD segments requiring no generation of internal LCD voltages. The two methods used are
referred to as Digital Correlation and PWM. Digital Correlation pertains to modulating the frequency and drive
levels of the common and segment signals to generate the highest RMS voltage across a segment to light it up or
to keep the RMS signal to zero. This method is good for STN displays but may result in reduced contrast with TN
(cheaper) displays. PWM pertains to driving the panel with PWM signals to effectively use the capacitance of the
panel to provide the integration of the modulated pulse-width to generate the desired LCD voltage. This method
results in higher power consumption but can result in better results when driving TN displays. LCD operation is
supported during Deep Sleep refreshing a small display buffer (4 bits; 1 32-bit register per port).
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Pinouts
2
Pinouts
Table 1 provides the pin list for PSoC™ 4000S for the 24-pin QFN and 28-pin SSOP packages. All port pins support
GPIO.
Table 1
Automotive PSoC™ 4000S 24-pin QFN and 28-pin SSOP pin list
24-QFN
28-SSOP
Pin
13
Name
P0.0
Pin
19
20
21
22
Name
P0.0
P0.1
P0.2
P0.3
14
P0.1
15
16
17
P0.4
P0.5
P0.6
23
24
25
26
27
28
P0.6
P0.7
XRES
VCCD
VSS
18
19
20
21
22
XRES
VCCD
VSSD
VDD
VDD
VSSA
1
2
3
4
5
6
P1.0
P1.1
P1.2
P1.3
P1.4
P1.7
23
24
P1.2
P1.3
1
2
3
P1.7
P2.0
P2.1
7
8
9
P2.4
P2.5
P2.6
P2.7
4
5
P2.6
P2.7
10
6
P3.0
11
12
13
14
15
16
17
18
P3.0
P3.1
P3.2
P3.3
P4.0
P4.1
P4.2
P4.3
7
8
9
10
11
12
P3.2
P3.3
P4.0
P4.1
P4.2
P4.3
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Pinouts
Table 2
Automotive PSoC™ 4000S 40-pin QFN and 48-pin QFN pin list
40-QFN
48-QFN
Pin
22
23
24
25
26
27
28
29
30
31
Name
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
XRES
VCCD
Pin
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
1
2
3
4
5
6
7
8
9
11
12
13
14
15
16
17
18
Name
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
XRES
VCCD
VSSD
VDDD
VDDA
VSSA
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7/VREF
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
NC
32
33
34
35
36
37
38
39
VDDD
VDDA
VSSA
P1.0
P1.1
P1.2
P1.3
P1.4
40
1
2
3
4
5
6
7
8
P1.7/VREF
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
9
VSSD
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
VSSD
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
10
11
12
13
14
15
Datasheet
14
002-18381 Rev. *H
2023-03-20
Automotive PSoC™ 4: PSoC™ 4000S family datasheet
Based on Arm® Cortex®-M0+ CPU
Pinouts
Table 2
Automotive PSoC™ 4000S 40-pin QFN and 48-pin QFN pin list (continued)
40-QFN 48-QFN
Pin
16
17
Name
P3.6
P3.7
Pin
19
20
21
22
23
24
25
26
27
Name
P3.6
P3.7
VDDD
P4.0
P4.1
P4.2
P4.3
NC
18
19
20
21
P4.0
P4.1
P4.2
P4.3
NC
Descriptions of the pin functions are as follows:
VDDD: Power supply for the digital section.
VDDA: Power supply for the analog section.
VSSD, VSSA: Ground pins for the digital and analog sections respectively.
VCCD: Regulated digital supply (1.8 V ±5%)
VDD: On some packages, VDDA and VDDD are shorted inside and brought out as a single power supply
VSS: On some packages, VSSA and VSSD are shorted inside and brought out as a single ground
Datasheet
15
002-18381 Rev. *H
2023-03-20
2.1
Alternate pin functions
Each port pin can be assigned to one of multiple functions; it can, for instance, be an analog I/O, a digital peripheral function, an LCD pin, or a CAPSENSE™
pin. The pin assignments are shown in the following table.
Port/
Analog
Smart I/O
Alternate function 1
Alternate function 2
Alternate function 3
Deep Sleep 1
Deep Sleep 2
pin
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
lpcomp.in_p[0]
lpcomp.in_n[0]
lpcomp.in_p[1]
lpcomp.in_n[1]
wco.wco_in
tcpwm.tr_in[0]
tcpwm.tr_in[1]
scb[0].spi_select1:0
scb[0].spi_select2:0
scb[0].spi_select3:0
scb[1].uart_rx:0
scb[1].uart_tx:0
scb[1].uart_cts:0
scb[1].uart_rts:0
scb[1].i2c_scl:0
scb[1].i2c_sda:0
scb[1].spi_mosi:1
scb[1].spi_miso:1
scb[1].spi_clk:1
wco.wco_out
srss.ext_clk
scb[1].spi_select0:1
P1.0
P1.1
tcpwm.line[2]:1
scb[0].uart_rx:1
scb[0].uart_tx:1
scb[0].i2c_scl:0
scb[0].i2c_sda:0
scb[0].spi_mosi:1
scb[0].spi_miso:1
tcpwm.line_compl[2]:1
P1.2
P1.3
tcpwm.line[3]:1
scb[0].uart_cts:1
scb[0].uart_rts:1
tcpwm.tr_in[2]
tcpwm.tr_in[3]
scb[0].spi_clk:1
tcpwm.line_compl[3]:1
scb[0].spi_select0:1
P1.4
scb[0].spi_select1:1
P1.7
P2.0
prgio[0].io[0]
tcpwm.line[4]:0
csd.comp
tcpwm.tr_in[4]
tcpwm.tr_in[5]
scb[1].i2c_scl:1
scb[1].i2c_sda:1
scb[1].spi_mosi:2
P2.1
P2.4
P2.5
P2.6
P2.7
P3.0
prgio[0].io[1]
prgio[0].io[4]
prgio[0].io[5]
prgio[0].io[6]
prgio[0].io[7]
prgio[1].io[0]
tcpwm.line_compl[4]:0
tcpwm.line[0]:1
scb[1].spi_miso:2
scb[1].spi_select1:1
scb[1].spi_select2:1
scb[1].spi_select3:1
tcpwm.line_compl[0]:1
tcpwm.line[1]:1
tcpwm.line_compl[1]:1
tcpwm.line[0]:0
lpcomp.comp[0]:1
scb[1].i2c_scl:2
scb[1].uart_rx:1
scb[1].uart_tx:1
scb[1].spi_mosi:0
scb[1].spi_miso:0
P3.1
prgio[1].io[1]
tcpwm.line_compl[0]:0
scb[1].i2c_sda:2
Port/
pin
Analog
Smart I/O
Alternate function 1
Alternate function 2
Alternate function 3
Deep Sleep 1
Deep Sleep 2
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
P4.0
P4.1
prgio[1].io[2]
prgio[1].io[3]
prgio[1].io[4]
tcpwm.line[1]:0
tcpwm.line_compl[1]:0
tcpwm.line[2]:0
scb[1].uart_cts:1
scb[1].uart_rts:1
cpuss.swd_data
cpuss.swd_clk
scb[1].spi_clk:0
scb[1].spi_select0:0
scb[1].spi_select1:0
scb[1].spi_select2:0
scb[1].spi_select3:0
tcpwm.tr_in[6]
tcpwm.tr_in[7]
tcpwm.tr_in[8]
tcpwm.tr_in[9]
tcpwm.tr_in[10]
tcpwm.tr_in[11]
tcpwm.line_compl[2]:0
tcpwm.line[3]:0
tcpwm.line_compl[3]:0
lpcomp.comp[1]
scb[0].i2c_scl:1
scb[0].i2c_sda:1
csd.vref_ext
scb[0].uart_rx:0
scb[0].uart_tx:0
scb[0].spi_mosi:0
scb[0].spi_miso:0
csd.cshieldpads
P4.2
P4.3
csd.cmodpad
csd.csh_tank
scb[0].uart_cts:0
scb[0].uart_rts:0
lpcomp.comp[0]:0
lpcomp.comp[1]:0
scb[0].spi_clk:0
scb[0].spi_select0:0
Automotive PSoC™ 4: PSoC™ 4000S family datasheet
Based on Arm® Cortex®-M0+ CPU
Power
3
Power
The following power system diagram shows the set of power supply pins as implemented for the PSoC™ 4000S.
The system has one regulator in Active mode for the digital circuitry. There is no analog regulator; the analog
circuits run directly from the VDDA input.
VDD
VDDA
VDDD
Analog
Digital
Domain
Domain
VSSA
VSSD
VCCD
1.8 Volt
Regulator
Figure 2
Power supply connections
There are two distinct modes of operation. In Mode 1, the supply voltage range is 1.8 V to 5.5 V (unregulated
externally; internal regulator operational). In Mode 2, the supply range is1.8 V ±5% (externally regulated; 1.71 to
1.89, internal regulator bypassed).
3.1
Mode 1: 1.8 V to 5.5 V external supply
In this mode, the PSoC™ 4000S is powered by an external power supply that can be anywhere in the range of 1.8
to 5.5 V. This range is also designed for battery-powered operation. For example, the chip can be powered from
a battery system that starts at 3.5 V and works down to 1.8 V. In this mode, the internal regulator of the PSoC™
4000S supplies the internal logic and its output is connected to the VCCD pin. The VCCD pin must be bypassed to
ground via an external capacitor (0.1 µF; X5R ceramic or better) and must not be connected to anything else.
Datasheet
18
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2023-03-20
Automotive PSoC™ 4: PSoC™ 4000S family datasheet
Based on Arm® Cortex®-M0+ CPU
Power
3.2
Mode 2: 1.8 V ±5% external supply
In this mode, the PSoC™ 4000S is powered by an external power supply that must be within the range of 1.71 to
1.89 V; note that this range needs to include the power supply ripple too. In this mode, the VDD and VCCD pins
are shorted together and bypassed.
Bypass capacitors must be used from VDD to ground. The typical practice for systems in this frequency range is
to use a capacitor in the 1-µF range, in parallel with a smaller capacitor (0.1 µF, for example). Note that these are
simply rules of thumb and that, for critical applications, the PCB layout, lead inductance, and the bypass
capacitor parasitic should be simulated to design and obtain optimal bypassing.
An example of a bypass scheme is shown in Figure 3.
Power supply bypass connections example
1.8 V to 5.5 V
PSoC™ 4000S
VDD
µF
0.1 µF
VCCD
0.1 µF
VSS
Figure 3
External supply range from 1.8 V to 5.5 V with internal regulator active
Datasheet
19
002-18381 Rev. *H
2023-03-20
Automotive PSoC™ 4: PSoC™ 4000S family datasheet
Based on Arm® Cortex®-M0+ CPU
Development support
4
Development support
The PSoC™ 4000S family has a rich set of documentation, development tools, and online resources to assist you
during your development process. Visit PSoC™ 4 MCU webpage to find out more.
4.1
Documentation
A suite of documentation supports the PSoC™ 4000S family to ensure that you can find answers to your questions
quickly. This section contains a list of some of the key documents.
Software user guide: A step-by-step guide for using PSoC™ Creator. The software user guide shows you how the
PSoC™ Creator build process works in detail, how to use source control with PSoC™ Creator, and much more.
Component datasheets: The flexibility of PSoC™ allows the creation of new peripherals (components) long after
the device has gone into production. Component data sheets provide all of the information needed to select and
use a particular component, including a functional description, API documentation, example code, and AC/DC
specifications.
Application notes: PSoC™ application notes discuss a particular application of PSoC™ in depth; examples
include brushless DC motor control and on-chip filtering. Application notes often include example projects in
addition to the application note document.
Technical reference manual: The Technical Reference Manual (TRM) contains all the technical detail you need
to use a PSoC™ device, including a complete description of all PSoC™ registers. The TRM is available in the
Documentation section at PSoC™ 4 MCU webpage.
4.2
Online
In addition to print documentation, the PSoC™ forums connect you with fellow PSoC™ users and experts in
PSoC™ from around the world, 24 hours a day, 7 days a week.
4.3
Tools
With industry standard cores, programming, and debugging interfaces, the PSoC™ 4000S family is part of a devel-
opment tool ecosystem. Visit us at PSoC™ Creator webpage for the latest information on the revolutionary, easy
to use PSoC™ Creator IDE, supported third party compilers, programmers, debuggers, and development kits.
Datasheet
20
002-18381 Rev. *H
2023-03-20
Automotive PSoC™ 4: PSoC™ 4000S family datasheet
Based on Arm® Cortex®-M0+ CPU
Electrical specifications
5
Electrical specifications
5.1
Table 3
Absolute maximum ratings
Absolute maximum ratings[1]
Details/
Spec ID#
SID1
Parameter Description
Min
–0.5
–0.5
Typ
–
Max
6
Unit
conditions
VDDD_ABS
VCCD_ABS
Digital supply relative to VSS
Direct digital core voltage input
relative to VSS
–
SID2
–
1.95
–
V
VDD+0.
5
25
SID3
SID4
VGPIO_ABS
IGPIO_ABS
GPIO voltage
–0.5
–25
–
–
–
–
Maximum current per GPIO
Current
injected per
pin
mA
GPIOinjectioncurrent, MaxforVIH
> VDDD, and Min for VIL < VSS
SID5
IGPIO_injection
ESD_HBM
–0.5
–
–
0.5
Electrostatic discharge human
body model
Electrostatic discharge charged
device model
BID44
2200
–
–
V
BID45
BID46
ESD_CDM
LU
500
–
–
–
–
–
Pin current for latch-up
–140
140
mA
5.2
Device level specifications
All specifications are valid for –40°C TA 85°C for A grade devices and –40°C TA 105°C for S grade devices,
except where noted. Specifications are valid for 1.71 V to 5.5 V, except where noted.
Table 4
DC specifications
Typical values measured at VDD = 3.3 V and 25°C.
Details/
Spec ID#
Parameter Description
VDD Power supply input voltage
Min
Typ
Max
Unit
conditions
Internally
regulated
supply
SID53
1.8
–
5.5
V
Internally
unregulated
supply
Power supply input voltage (VCCD
= VDD= VDDA
SID255
VDD
1.71
–
1.89
)
SID54
SID55
VCCD
CEFC
Output voltage (for core logic)
External regulator voltage
bypass
–
–
1.8
0.1
–
–
–
X5R ceramic or
better
X5R ceramic or
better
µF
SID56
CEXC
Power supply bypass capacitor
–
1
–
Active Mode, VDD = 1.8 V to 5.5 V. Typical values measured at VDD = 3.3 V and 25°C.
Note
1. Usage above the absolute maximum conditions listed in Table 3 may cause permanent damage to the device.
Exposure to Absolute Maximum conditions for extended periods of time may affect device reliability. The
Maximum Storage Temperature is 150 °C in compliance with JEDEC Standard JESD22-A103, High Tempera-
ture Storage Life. When used below Absolute Maximum conditions but above normal operating conditions,
the device may not operate to specification.
Datasheet
21
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2023-03-20
Automotive PSoC™ 4: PSoC™ 4000S family datasheet
Based on Arm® Cortex®-M0+ CPU
Electrical specifications
Table 4
DC specifications (continued)
Typical values measured at VDD = 3.3 V and 25°C.
Details/
Spec ID#
SID10
Parameter Description
Min
–
Typ
1.2
2.4
4.6
Max
2.0
Unit
conditions
Max is at 105°C
and 5.5 V
Max is at 105°C
and 5.5 V
Max is at 105°C
and 5.5 V
IDD5
IDD8
IDD11
Execute from flash; CPU at 6 MHz
Execute from flash; CPU at 24
MHz
Execute from flash; CPU at 48
MHz
SID16
–
4.0
mA
SID19
–
5.9
Sleep Mode, VDDD = 1.8 V to 5.5 V (Regulator on)
I2C wakeup WDT, and Compar-
6 MHz, Max is at
105°C and 5.5 V
12 MHz, Max is
at 105°C and 5.5
V
SID22
IDD17
–
–
1.1
1.4
1.6
1.9
ators on
mA
mA
I2C wakeup, WDT, and Compar-
ators on
SID25
IDD20
Sleep Mode, VDDD = 1.71 V to 1.89 V (Regulator bypassed)
I2C wakeup, WDT, and Compar-
6 MHz, Max is at
105°C
12 MHz, Max is
SID28
IDD23
–
–
0.7
0.9
0.9
1.1
ators on
I2C wakeup, WDT, and Compar-
ators on
SID28A
IDD23A
mA at 105°C and 5.5
V
Deep Sleep Mode, VDD = 1.8 V to 3.6 V (Regulator on)
SID31 IDD26
I2C wakeup and WDT on
Deep Sleep Mode, VDD = 3.6 V to 5.5 V (Regulator on)
SID34 IDD29
I2C wakeup and WDT on
Max is at 105°C
–
–
2.5
2.5
60
µA
and 3.6 V
60
60
µA Max is at 105°C
µA Max is at 105°C
Deep Sleep Mode, VDD = VCCD = 1.71 V to 1.89 V (Regulator bypassed)
SID37
IDD32
I2C wakeup and WDT on
–
2.5
2
XRES Current
Supply current while XRES
asserted
SID307
IDD_XR
–
5
mA Max is at 105 °C
Table 5
AC specifications
Details/
Unit
Spec ID# Parameter
Description
Min Typ
Max
conditions
SID48
FCPU
TSLEEP
TDEEPSLEEP
CPU frequency
Wakeup from Sleep mode
Wakeup from Deep Sleep mode
DC
–
–
–
0
35
48
–
–
MHz 1.71 VDD 5.5
SID49[3]
SID50[3]
–
µs
–
Note
2. Guaranteed by characterization.
Datasheet
22
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Automotive PSoC™ 4: PSoC™ 4000S family datasheet
Based on Arm® Cortex®-M0+ CPU
Electrical specifications
5.2.1
GPIO
Table 6
GPIO DC specifications
Spec ID# Parameter Description
Min
Typ
Max Unit Details/conditions
0.7
[3]
SID57
VIH
VIL
VIH
VIL
Input voltage high threshold
Input voltage low threshold
LVTTL input, VDDD < 2.7 V
LVTTL input, VDDD < 2.7 V
–
–
CMOS Input
VDDD
0.3
VDDD
SID58
–
–
–
–
CMOS Input
0.7
VDDD
[3]
[3]
SID241
SID242
–
–
–
0.3
VDDD
–
0.8
–
–
SID243
SID244
SID59
VIH
VIL
LVTTL input, VDDD 2.7 V
LVTTL input, VDDD 2.7 V
Output voltage high level
Output voltage high level
2.0
–
VDDD –0.6
VDDD –0.5
–
–
–
–
–
–
V
VOH
VOH
IOH = 4 mA at 3 V VDDD
IOH = 1 mA at 3 V VDDD
SID60
–
IOL = 4 mA at 1.8 V
VDDD
SID61
SID62
VOL
VOL
Output voltage low level
Output voltage low level
–
–
–
–
0.6
0.6
IOL = 10 mA at 3 V
VDDD
SID62A
SID63
SID64
VOL
RPULLUP
Output voltage low level
Pull-up resistor
–
3.5
3.5
–
5.6
5.6
0.4
8.5
8.5
IOL = 3 mA at 3 V VDDD
–
–
kΩ
RPULLDOWN Pull-down resistor
Input leakage current
(absolute value)
SID65
IIL
–
–
2
nA 25 °C, VDDD = 3.0 V
SID66
SID67[4]
CIN
VHYSTTL
Input capacitance
Input hysteresis LVTTL
–
25
–
40
7
–
pF
–
V
DDD 2.7 V
0.05 ×
VDDD
SID68[4]
SID68A[4]
SID69[4]
VHYSCMOS
Input hysteresis CMOS
Input hysteresis CMOS
–
–
–
–
–
VDD < 4.5 V
mV
VHYSC-
MOS5V5
200
–
–
VDD > 4.5 V
Current through protection
diode to VDD/VSS
Maximum total source or
sink chip current
IDIODE
100
200
µA
–
–
SID69A[4] ITOT_GPIO
–
mA
Notes
3. VIH must not exceed VDDD + 0.2 V.
4. Guaranteed by characterization.
Datasheet
23
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2023-03-20
Automotive PSoC™ 4: PSoC™ 4000S family datasheet
Based on Arm® Cortex®-M0+ CPU
Electrical specifications
Table 7
GPIO AC specifications
(Guaranteed by Characterization)
Spec ID# Parameter Description
Min
Typ
Max
Unit Details/conditions
3.3 V VDDD
Cload = 25 pF
3.3 V VDDD
Cload = 25 pF
3.3 V VDDD
Cload = 25 pF
Rise time in fast strong
mode
,
SID70
SID71
SID72
SID73
TRISEF
TFALLF
TRISES
TFALLS
2
–
12
ns
,
Fall time in fast strong mode
2
–
–
–
12
60
60
Rise time in slow strong
mode
,
10
10
–
–
Fall time in slow strong
mode
3.3 V VDDD,
Cload = 25 pF
GPIO FOUT; 3.3 V VDDD
5.5 V
90/10%, 25 pF load,
60/40 duty cycle
SID74
SID75
SID76
SID245
SID246
FGPIOUT1
FGPIOUT2
FGPIOUT3
FGPIOUT4
–
–
–
–
–
–
–
–
–
–
33
16.7
7
Fast strong mode
GPIO FOUT; 1.71 VVDDD
3.3 V
Fast strong mode
GPIO FOUT; 3.3 V VDDD
5.5 V
Slow strong mode
GPIO FOUT; 1.71 V VDDD
3.3 V
Slow strong mode.
GPIO input operating
frequency;
1.71 V VDDD 5.5 V
90/10%, 25 pF load,
60/40 duty cycle
90/10%, 25 pF load,
60/40 duty cycle
MHz
90/10%, 25 pF load,
60/40 duty cycle
3.5
48
FGPIOIN
90/10% VIO
5.2.2
XRES
Table 8
XRES DC specifications
Spec ID#
Parameter Description
Min
Typ
Max
Unit Details/conditions
Input voltage high
0.7 ×
VDDD
SID77
SID78
VIH
VIL
–
–
threshold
V
CMOS Input
Input voltage low
threshold
0.3
VDDD
–
–
SID79
SID80
RPULLUP
CIN
Pull-up resistor
Input capacitance
–
–
60
–
–
7
kΩ
pF
–
–
Typical hysteresis is
200 mV for VDD > 4.5 V
SID81[5]
VHYSXRES
Input voltage hysteresis
–
100
–
mV
Current through
protection diode to
VDD/VSS
SID82
IDIODE
–
–
100
µA
–
Note
5. Guaranteed by characterization.
Datasheet
24
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2023-03-20
Automotive PSoC™ 4: PSoC™ 4000S family datasheet
Based on Arm® Cortex®-M0+ CPU
Electrical specifications
Table 9
Spec ID# Parameter
SID83[5]
TRESETWIDTH
BID194[5] TRESETWAKE
XRES AC specifications
Description
Reset pulse width
Wake-up time from reset
release
Min
1
Typ
–
Max
–
Unit Details/conditions
µs
–
–
–
2.7
ms
–
5.3
Analog peripherals
Table 10
Comparator DC specifications
Spec ID# Parameter Description
Details/conditions
Unit
Min Typ
Max
SID84
SID85
SID86
VOFFSET1
VOFFSET2
VHYST
Input offset voltage, Factory trim
Input offset voltage, Custom trim
Hysteresis when enabled
–
–
–
–
–
10
±10
±4
35
–
–
–
mV
Input common mode voltage in
normal mode
Input common mode voltage in
low power mode
Input common mode voltage in
ultra low power mode
SID87
VICM1
VICM2
0
0
0
–
–
–
VDDD-0.1
VDDD
Modes 1 and 2
–
SID247
V
VDDD ≥ 2.2 V at
–40 °C
SID247A VICM3
VDDD-1.15
SID88
SID88A
SID89
CMRR
CMRR
ICMP1
ICMP2
Common mode rejection ratio
Common mode rejection ratio
Block current, normal mode
Block current, low power mode
Block current in ultra low-power
mode
50
42
–
–
–
–
–
–
–
400
100
VDDD ≥ 2.7V
VDDD ≤ 2.7V
–
–
VDDD ≥ 2.2 V at
–40°C
dB
SID248
–
µA
SID259
SID90
ICMP3
ZCMP
–
6
–
28
–
DC Input impedance of
comparator
35
MΩ
–
Table 11
Comparator AC specifications
Spec ID# Parameter Description
Details/conditions
Min Typ Max
Unit
Response time, normal mode, 50
mV overdrive
Response time, low power mode,
50 mV overdrive
Response time, ultra-low power
mode, 200 mV overdrive
–
SID91
TRESP1
–
–
–
38
70
110
200
15
ns
µs
–
SID258 TRESP2
VDDD ≥ 2.2 V at
–40°C
SID92
TRESP3
2.3
Datasheet
25
002-18381 Rev. *H
2023-03-20
Automotive PSoC™ 4: PSoC™ 4000S family datasheet
Based on Arm® Cortex®-M0+ CPU
Electrical specifications
5.3.1
CSD
Table 12
CSD and IDAC specifications
Spec ID#
SYS.PER#3 VDD_RIPPLE
Parameter
Description
Min Typ
Max
Unit Details /conditions
DD > 2 V (with ripple),
mV 25 °C TA, Sensitivity =
0.1 pF
Max allowed ripple
on power supply, DC
to 10 MHz
V
–
–
±50
SYS.PER#1 VDD_RIP-
Max allowed ripple
on power supply, DC
to 10 MHz
VDD > 1.75V (with ripple),
6
PLE_1.8
25 °C TA, Parasitic Capaci-
tance (CP) < 20 pF, Sensi-
tivity ≥ 0.4 pF
–
–
±25
mV
µA
SID.CSD.BL ICSD
K
Maximum block
current
Maximum block current
for both IDACs in dynamic
(switching) mode
including comparators,
buffer, and reference
generator.
–
–
4000
SID.CSD#15 VREF
Voltage reference for
CSD and Comparator
VDDA
0.6
-
VDDA - 0.06 or 4.4,
whichever is lower
0.6
0.6
1.2
V
V
SID.CSD#15 VREF_EXT
A
External voltage
reference for CSD
and Comparator
VDDA
0.6
-
VDDA - 0.06 or 4.4,
whichever is lower
SID.CSD#16 IDAC1IDD
SID.CSD#17 IDAC2IDD
IDAC1 (7-bits) block
current
IDAC2 (7-bits) block
current
Voltage range of
operation
–
–
–
–
–
1750
1750
5.5
µA
µA
V
–
–
SID308
VCSD
1.71
1.8 V ±5% or 1.8 V to 5.5 V
SID308A
VCOMPIDAC
Voltage compliance
range of IDAC
VDDA
0.6
–
VDDA - 0.06 or 4.4,
whichever is lower
–
INL is ±5.5 LSB for VDDA
2 V
0.6
–1
–2
–1
–2
–
–
–
–
–
V
SID309
SID310
IDAC1DNL
IDAC1INL
DNL
INL
1
2
1
2
LSB
LSB
LSB
LSB
<
<
SID311
SID312
IDAC2DNL
IDAC2INL
DNL
INL
INL is ±5.5 LSB for VDDA
2 V
SID313
SNR
Ratio of counts of
finger to noise.
Guaranteed by
characterization
Capacitance range of 5 to
Ratio 35 pF, 0.1-pF sensitivity.
All use cases. VDDA > 2 V.
5
–
–
SID314
IDAC1CRT1
IDAC1CRT2
IDAC1CRT3
Output current of
IDAC1 (7 bits) in low
range
Output current of
IDAC1(7 bits) in
medium range
Output current of
IDAC1(7 bits) in high 275
range
4.2
34
–
–
–
5.4
41
µA LSB = 37.5-nA typ.
µA LSB = 300-nA typ.
µA LSB = 2.4-µA typ.
SID314A
SID314B
330
Datasheet
26
002-18381 Rev. *H
2023-03-20
Automotive PSoC™ 4: PSoC™ 4000S family datasheet
Based on Arm® Cortex®-M0+ CPU
Electrical specifications
Table 12
Spec ID#
SID314C
CSD and IDAC specifications (continued)
Parameter
Description
Min Typ
Max
Unit Details /conditions
IDAC1CRT12
Output current of
IDAC1 (7 bits) in low
range, 2X mode
8
–
10.5
µA LSB = 75-nA typ.
SID314D
IDAC1CRT22
Output current of
IDAC1(7 bits) in
medium range, 2X
mode
69
–
82
µA LSB = 600-nA typ.
SID314E
SID315
IDAC1CRT32
IDAC2CRT1
IDAC2CRT2
IDAC2CRT3
IDAC2CRT12
IDAC2CRT22
Output current of
IDAC1(7 bits) in high 540
range, 2X mode
–
–
–
–
–
660
5.4
µA LSB = 4.8-µA typ.
µA LSB = 37.5-nA typ.
µA LSB = 300-nA typ.
µA LSB = 2.4-µA typ.
µA LSB = 75-nA typ.
Output current of
IDAC2 (7 bits) in low
range
Output current of
IDAC2 (7 bits) in
medium range
Output current of
IDAC2 (7 bits) in high 275
range
Output current of
IDAC2 (7 bits) in low
range, 2X mode
4.2
34
SID315A
SID315B
SID315C
SID315D
41
330
10.5
8
Output current of
IDAC2(7 bits) in
medium range, 2X
mode
69
–
82
µA LSB = 600-nA typ.
SID315E
SID315F
SID315G
SID315H
SID320
IDAC2CRT32
IDAC3CRT13
IDAC3CRT23
IDAC3CRT33
IDACOFFSET
Output current of
IDAC2(7 bits) in high 540
range, 2X mode
–
–
–
–
660
10.5
82
µA LSB = 4.8-µA typ.
µA LSB = 37.5-nA typ.
µA LSB = 300-nA typ.
µA LSB = 2.4-µA typ.
Output current of
IDAC in 8-bit mode in
low range
Output current of
IDAC in 8-bit mode in 69
medium range
Output current of
IDAC in 8-bit mode in 540
high range
All zeroes input
–
8
660
Polarity set by Source or
LSB Sink. Offset is 2 LSBs for
37.5 nA/LSB mode
–
–
–
1
SID321
SID322
IDACGAIN
Full-scale error less
offset
Mismatch between
IDAC1 and IDAC2 in
Low mode
–
±10
9.2
%
–
IDACMIS-
MATCH1
–
LSB LSB = 37.5-nA typ.
Datasheet
27
002-18381 Rev. *H
2023-03-20
Automotive PSoC™ 4: PSoC™ 4000S family datasheet
Based on Arm® Cortex®-M0+ CPU
Electrical specifications
Table 12
Spec ID#
SID322A
CSD and IDAC specifications (continued)
Parameter
Description
Min Typ
Max
Unit Details /conditions
IDACMIS-
MATCH2
Mismatch between
IDAC1 and IDAC2 in
Medium mode
–
–
–
–
5.6
LSB LSB = 300-nA typ.
SID322B
IDACMIS-
MATCH3
Mismatch between
IDAC1 and IDAC2 in
High mode
6.8
LSB LSB = 2.4-µA typ.
SID323
SID324
SID325
IDACSET8
IDACSET7
CMOD
Settling time to 0.5
LSB for 8-bit IDAC
Full-scale transition. No
–
–
–
–
–
10
10
–
µs
external load.
Settling time to 0.5
LSB for 7-bit IDAC
Full-scale transition. No
external load.
µs
External modulator
capacitor.
2.2
nF 5-V rating, X7R or NP0 cap.
Datasheet
28
002-18381 Rev. *H
2023-03-20
Automotive PSoC™ 4: PSoC™ 4000S family datasheet
Based on Arm® Cortex®-M0+ CPU
Electrical specifications
Table 13
Spec ID#
10-bit CAPSENSE™ ADC specifications
Parameter
Description
Details/conditions
Unit
Min Typ
Max
Auto-zeroing is
bits required every milli-
second
SIDA94
A_RES
Resolution
–
–
10
Number of channels -
single ended
Monotonicity
Defined by AMUX
Bus.
–
In VREF (2.4 V) mode
with VDDA bypass
capacitance of 10 µF
SIDA95
SIDA97
A_CHNLS_S
A-MONO
–
–
–
–
16
–
Yes
%
SIDA98
SIDA99
A_GAINERR
A_OFFSET
Gain error
–
–
–
–
±2
3
In VREF (2.4 V) mode
Input offset voltage
mV with VDDA bypass
capacitance of 10 µF
SIDA100
SIDA101
A_ISAR
A_VINS
Current consumption
Input voltage range - single
ended
–
–
–
0.25
mA
–
VSSA
VDDA
V
–
SIDA103
SIDA104
A_INRES
A_INCAP
Input resistance
Input capacitance
–
–
2.2
20
–
–
KΩ
pF
–
–
In VREF (2.4 V) mode
Power supply rejection
ratio
SIDA106
SIDA107
A_PSRR
A_TACQ
–
–
60
1
–
–
dB with VDDA bypass
capacitance of 10 µF
µs
Sample acquisition time
–
Does not include
acquisition time.
Conversion time for 8-bit
resolution at conversion
rate = Fhclk/(2^(N+2)).
Clock frequency = 48 MHz.
SIDA108
A_CONV8
–
–
21.3
µs Equivalent to
44.8 ksps including
acquisition time.
Does not include
acquisition time.
µs Equivalent to
11.6 ksps including
acquisition time.
Conversion time for 10-bit
resolution at conversion
rate = Fhclk/(2^(N+2)).
SIDA108A A_CONV10
–
–
–
85.3
–
Clock frequency = 48 MHz.
With 10-Hz input
Signal-to-noise and
Distortion ratio (SINAD)
sine wave, external
SIDA109
A_SND
61
dB
2.4-V reference, VREF
(2.4 V) mode
Input bandwidth without
aliasing
Integral non linearity. 1
ksps.
Differential non linearity. 1
ksps.
SIDA110
SIDA111
SIDA112
A_BW
A_INL
A_DNL
–
–
–
–
–
–
22.4
2
kHz 8-bit resolution
VREF = 2.4 V or
greater
LSB
1
LSB –
Datasheet
29
002-18381 Rev. *H
2023-03-20
Automotive PSoC™ 4: PSoC™ 4000S family datasheet
Based on Arm® Cortex®-M0+ CPU
Electrical specifications
5.4
Digital peripherals
5.4.1
Timer Counter Pulse-Width Modulator (TCPWM)
Table 14
TCPWM specifications
Spec ID
Parameter Description
Details/conditions
Min Typ Max Unit
Block current consumption at
All modes (TCPWM)
SID.TCPWM.1 ITCPWM1
SID.TCPWM.2 ITCPWM2
SID.TCPWM.2A ITCPWM3
–
–
–
–
–
–
45
3 MHz
Block current consumption at
12 MHz
Block current consumption at
48 MHz
All modes (TCPWM)
All modes (TCPWM)
155 µA
650
Fc max = CLK_SYS
Maximum = 48 MHz
For all trigger events[6]
TCPWMFREQ
TPWMENEXT
SID.TCPWM.3
SID.TCPWM.4
Operating frequency
–
–
–
Fc MHz
–
Input trigger pulse width
2/Fc
Minimum possible
width of Overflow,
Underflow, and CC
(Counter equals
Compare value)
outputs
Minimumtimebetween
successive counts
Minimum pulse width
of PWM Output
TPWMEXT
SID.TCPWM.5
Output trigger pulse widths
2/Fc
–
–
ns
–
TCRES
SID.TCPWM.5A
SID.TCPWM.5B
Resolution of counter
PWM resolution
1/Fc
1/Fc
–
–
PWMRES
–
–
Minimum pulse width
between Quadrature
phase inputs
QRES
SID.TCPWM.5C
Quadrature inputs resolution 1/Fc
–
5.4.2
Table 15
I2C
Fixed I2C DC specifications[6]
Spec ID
Parameter Description
Min Typ Max Unit Details/conditions
SID149
II2C1
II2C2
II2C3
II2C4
Block current consumption at
–
–
–
–
–
–
–
–
50
135
310
1.4
–
–
100 kHz
SID150
SID151
SID152
Block current consumption at
400 kHz
Block current consumption at 1
Mbps
I2C enabled in Deep Sleep mode
µA
–
–
Table 16
Spec ID
SID153
Fixed I2C AC specifications[6]
Parameter Description
FI2C1 Bit rate
Min Typ Max Unit Details/conditions
Msps –
–
–
1
Table 17
SPI DC specifications[6]
Spec ID Parameter Description
Min Typ Max Unit Details/conditions
SID163 ISPI1
SID164 ISPI2
SID165 ISPI3
Block current consumption at 1 Mbps
Block current consumption at 4 Mbps
Block current consumption at 8 Mbps
–
–
–
–
–
–
360
560 µA
600
–
–
–
Datasheet
30
002-18381 Rev. *H
2023-03-20
Automotive PSoC™ 4: PSoC™ 4000S family datasheet
Based on Arm® Cortex®-M0+ CPU
Electrical specifications
Table 18
Spec ID Parameter Description
SPI AC specifications[6]
Min
Typ
Max Unit Details/conditions
SPI operating frequency (Master;
6X Oversampling)
SID166
FSPI
–
–
8
MHz –
Fixed SPI Master Mode AC specifications
MOSI valid after SClock driving
edge
SID167
SID168
SID169
TDMO
TDSI
–
20
0
–
–
–
15
–
–
MISO valid before SClock
capturing edge
Full clock, late MISO
sampling
Referred to Slave
capturing edge
ns
THMO
Previous MOSI data hold time
–
Fixed SPI Slave Mode AC specifications
MOSI valid before Sclock
Capturing edge
SID170
TDMI
40
–
–
–
–
–
42 +
3*Tcp
u
MISO valid after Sclock driving
edge
SID171
TDSO
TCPU = 1/FCPU
ns
ns
MISO valid after Sclock driving
edge in Ext. Clk mode
Previous MISO data hold time
SID171A TDSO_EXT
–
0
–
–
–
–
48
–
–
–
–
SID172
THSO
TSSELSSC
K
SID172A
SSEL valid to first SCK Valid edge
100
Table 19
UART DC specifications[6]
Spec ID Parameter Description
Min
Typ
Max Unit Details/conditions
Block current consumption at 100
SID160 IUART1
SID161 IUART2
–
–
–
55
µA
µA
–
–
Kbps
Block current consumption at
1000 Kbps
–
312
Table 20
Spec ID Parameter Description
UART AC specifications[6]
Min
Typ
Max Unit Details/conditions
SID162 FUART
Bit rate
–
–
1
Mbps –
Table 21
LCD Direct Drive DC specifications[6]
Spec ID Parameter Description
Min
Typ
Max Unit Details/conditions
16 4 small
Operating current in low power
SID154 ILCDLOW
5
–
µA segment disp. at 50
Hz
mode
–
–
LCD capacitance per
segment/common driver
SID155 CLCDCAP
500
5000
pF
–
Note
6. Guaranteed by characterization.
Datasheet
31
002-18381 Rev. *H
2023-03-20
Automotive PSoC™ 4: PSoC™ 4000S family datasheet
Based on Arm® Cortex®-M0+ CPU
Electrical specifications
Table 21
LCD Direct Drive DC specifications[6] (continued)
Spec ID Parameter Description
Min
Typ
Max Unit Details/conditions
SID156 LCDOFFSET Long-term segment offset
–
20
–
mV
–
LCD system operating current Vbias
32 4 segments. 50
SID157 ILCDOP1
SID158 ILCDOP2
2
2
–
= 5 V
–
–
Hz. 25°C.
mA
LCD system operating current Vbias
= 3.3 V
32 4 segments. 50
Hz. 25°C.
–
Table 22
Spec ID Parameter Description
LCD Direct Drive AC specifications[7]
Min
10
Typ
50
Max Unit Details/conditions
150 Hz
SID159 FLCD
LCD frame rate
–
5.5
Memory
Table 23
Flash DC specifications
Spec ID
SID173
Parameter
VPE
Description
Erase and program voltage 1.71
Min
Typ
–
Max
5.5
Unit Details/conditions
V
–
Table 24
Spec ID
SID174
Flash AC specifications
Parameter
TROWWRITE
Description
Row (block) write time
(erase and program)
Min Typ Max
Unit Details/conditions
[8]
Row (block) =
128 bytes
–
–
–
–
–
–
20
16
4
[8]
SID175
SID176
TROWERASE
Row erase time
–
ms
[8]
TROWPROGRAM Row program time after
–
erase
[8]
SID178
TBULKERASE
Bulk erase time (32 KB)
Total device program time
Flash endurance
–
–
–
–
–
35
7
–
–
[8]
SID180[9] TDEVPROG
SID181[9] FEND
SID182[9] FRET
Seconds –
100 K
Cycles
–
Flash retention. TA 55 °C,
100 K P/E cycles
Flash retention. TA 85 °C,
10 K P/E cycles
20
10
–
–
–
–
–
SID182A[9]
–
Years
SID182B FRETQ
Flash retention. TA 105 °C,
Guaranteed by
design
10 K P/E cycles with no more 10
–
–
than 3 years at TA 85 °C
Number of Wait states at 48
CPU execution from
Flash
CPU execution from
Flash
SID256
SID257
TWS48
TWS24
2
–
–
–
–
MHz
Number of Wait states at 24
MHz
1
Notes
7. Guaranteed by characterization.
8. It can take as much as 20 milliseconds to write to Flash. During this time the device should not be Reset, or
Flash operations will be interrupted and cannot be relied on to have completed. Reset sources include the
XRES pin, software resets, CPU lockup states and privilege violations, improper power supply levels, and
watchdogs. Make certain that these are not inadvertently activated.
9. Guaranteed by characterization.
Datasheet
32
002-18381 Rev. *H
2023-03-20
Automotive PSoC™ 4: PSoC™ 4000S family datasheet
Based on Arm® Cortex®-M0+ CPU
Electrical specifications
5.6
System resources
5.6.1
Power-on reset (POR)
Table 25
Power-on reset (PRES)
Spec ID
Parameter
Description
Min
Typ
Max
Unit Details/conditions
On power-up and
power-down
SID.CLK#6 SR_POWER
Power supply slew rate
1
–
67
V/ms
SID185[10] VRISEIPOR
SID186[10] VFALLIPOR
Rising trip voltage
Falling trip voltage
0.80
0.70
–
–
1.5
1.4
–
V
–
Table 26
Spec ID
Brown-out detect (BOD) for VCCD
Parameter
Description
Min
Typ
Max
Unit Details/conditions
BOD trip voltage in active
and sleep modes
BOD trip voltage in Deep
Sleep
SID190[10] VFALLPPOR
1.48
–
–
1.62
1.5
–
V
SID192[10] VFALLDPSLP
1.11
–
5.6.2
SWD Interface
Table 27
SWD Interface specifications
Spec ID
Parameter Description
Min
Typ
Max
Unit Details/conditions
SWDCLK ≤ 1/3 CPU
SID213
F_SWDCLK1 3.3 V VDD 5.5 V
F_SWDCLK2 1.71 V VDD 3.3 V
–
–
14
clock frequency
MHz
SWDCLK ≤ 1/3 CPU
clock frequency
SID214
–
0.25*T
0.25*T
–
–
–
–
–
–
7
T_SWDI_-
T = 1/f SWDCLK
SETUP
T_SWDI_HOL
T = 1/f SWDCLK
D
T_SWDO_VALI
T = 1/f SWDCLK
D
T_SWDO_HOL
T = 1/f SWDCLK
D
SID215[10]
SID216[10]
SID217[10]
SID217A[10]
–
–
–
–
ns
–
0.5*T
–
1
–
Note
10.Guaranteed by characterization.
Datasheet
33
002-18381 Rev. *H
2023-03-20
Automotive PSoC™ 4: PSoC™ 4000S family datasheet
Based on Arm® Cortex®-M0+ CPU
Electrical specifications
5.6.3
Internal Main Oscillator
Table 28
IMO DC specifications
(Guaranteed by Design)
Spec ID Parameter
SID218 IIMO1
Description
IMO operating current at 48
MHz
Min
–
Typ
–
Max
250
Units Details/conditions
µA
–
SID219 IIMO2
IMO operating current at 24
MHz
–
–
180
µA
–
Table 29
IMO AC specifications
Spec ID Parameter
Description
Min
Typ
Max
Unit Details/conditions
Frequency variation at 24, 32,
and 48 MHz (trimmed)
SID223 FIMOTOL1
–
–
±2
%
–
SID226 TSTARTIMO
SID228 TJITRMSIMO2
IMO startup time
RMS jitter at 24 MHz
–
–
–
145
7
–
µs
ps
–
–
Datasheet
34
002-18381 Rev. *H
2023-03-20
Automotive PSoC™ 4: PSoC™ 4000S family datasheet
Based on Arm® Cortex®-M0+ CPU
Electrical specifications
5.6.4
Internal Low-Speed Oscillator
Table 30
ILO DC specifications
(Guaranteed by Design)
Spec ID
Parameter
Description
ILO operating current
Min
–
Typ
0.3
Max
1.05
Unit Details/conditions
µA
SID231[11] IILO1
–
Table 31
ILO AC specifications
Spec ID Parameter
SID234[11] TSTARTILO1
SID236[11] TILODUTY
Description
Min
–
40
20
Typ
–
50
40
Max
Unit Details/conditions
ILO startup time
ILO duty cycle
ILO frequency range
2
60
80
ms
%
–
–
–
SID237
FILOTRIM1
kHz
Table 32
Watch Crystal Oscillator (WCO) specifications
Spec ID Parameter Description
Min Typ Max Unit Details/conditions
SID398
FWCO
Crystal frequency
–
32.76
8
–
kHz
–
SID399
SID400
SID401
SID402
SID403
SID404
SID405
FTOL
ESR
PD
TSTART
CL
C0
Frequency tolerance
Equivalent series resistance
Drive level
Startup time
Crystal load capacitance
Crystal shunt capacitance
Operating current (high power
mode)
Operating current (low power
mode)
–
–
–
–
6
–
–
50
50
–
–
–
250 ppm With 20-ppm crystal
–
1
500
12.5
–
kΩ
µW
ms
pF
–
–
–
–
–
1.35
–
pF
IWCO1
8
µA
–
–
SID406
IWCO2
–
–
1
µA
Table 33
External clock pecifications
Parameter Description
External clock input frequency
SID306[11] ExtClkDuty Duty cycle; measured at VDD/2
Spec ID
Min Typ Max
Unit Details/conditions
SID305[11] ExtClkFreq
0
–
–
48
55
MHz
%
–
–
45
Table 34 Block specs
Spec ID Parameter
Description
Min Typ Max
Unit Details/conditions
System clock source switching
time
SID262[11] TCLKSWITCH
3
–
4
Periods –
Table 35
Smart I/O Pass-through time (Delay in Bypass Mode)
Spec ID Parameter Description
Min
Typ
Max
Unit Details /conditions
PRG_BYPAS Max delay added by Smart I/O in
bypass mode
SID252
–
–
1.6
ns
–
S
Note
11.Guaranteed by characterization.
Datasheet
35
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2023-03-20
6
Ordering information
Table 36 lists the Automotive PSoC™ 4000S part numbers and features.
Table 36
Automotive PSoC™ 4000S ordering information
Features
Packages
Operating temperature
MPN
CY8C4024LQA-S411
24
24
24
24
24
24
24
24
48
48
48
48
16
16
16
16
32
32
32
32
32
32
32
32
2
2
2
2
4
4
4
4
4
4
4
4
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
2
2
2
2
2
2
2
2
2
2
2
2
5
5
5
5
5
5
5
5
5
5
5
5
2
2
2
2
2
2
2
2
2
2
2
2
19
19
24
24
19
19
24
24
19
19
24
24
X
–
–
X
X
–
–
X
X
–
–
X
X
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
X
–
X
–
X
–
X
–
X
–
X
–
–
X
–
X
–
X
–
X
–
X
–
X
–
–
–
–
–
–
–
–
–
–
–
–
[12]
CY8C4024LQS-S411
X
–
–
X
X
–
–
X
X
–
–
4024
4025
[12]
CY8C4024PVA-S412
CY8C4024PVS-S412
CY8C4025LQA-S411
CY8C4025LQS-S411
CY8C4025PVA-S412
CY8C4025PVS-S412
CY8C4045LQA-S411
CY8C4045LQS-S411
CY8C4045PVA-S412
CY8C4045PVS-S412
[12]
[12]
4045
Note
12. Alternate fab available.
Automotive PSoC™ 4: PSoC™ 4000S family datasheet
Based on Arm® Cortex®-M0+ CPU
Ordering information
The nomenclature used in the preceding table is based on the following part numbering convention:
Field
Description
Values
Meaning
Cypress (an Infineon
company) prefix
CY8C
–
4
A
Architecture
Family
4
0
2
4
4
5
6
7
PSoC™ 4
4000 Family
24 MHz
48 MHz
16 KB
32 KB
64 KB
128 KB
QFN
SSOP
B
CPU speed
Flash capacity
Package code
C
LQ/LD
PV
DE
F
I
A
S
E
S
Industrial
Automotive (AEC-Q100: –40°C to +85°C)
Automotive (AEC-Q100: –40°C to +105°C)
Automotive (AEC-Q100: –40°C to +125°C)
PSoC™ 4A-S1, PSoC™ 4A-S2
PSoC™ 4A-M
Temperature range
M
L
S
Silicon family
PSoC™ 4A-L
BL
PSoC™ 4A-BLE
XYZ
XX
Attributes code
000-999
Non KA
Blank
Code of feature set in the specific family
Fab/Assembly location
Initial Assembly location
The following is an example of a part number:
CY8C 4
DE
– S XYZ
XX
F
A B C
T
Example
CYPRESS(an Infineon company) prefix
Architecture
4
0
:PSoC
™ 4
Family within architecture
: 4000 Family
CPU speed
Flash capacity
Package code
4
:48 MHz
5
:
:
KB
32
PV
SSOP
Temperature range
Silicon family
A, S : Automotive
Attributes code
Blank/Non-KA = Initial assembly location
T = Tape and rseel
Datasheet
37
002-18381 Rev. *H
2023-03-20
Automotive PSoC™ 4: PSoC™ 4000S family datasheet
Based on Arm® Cortex®-M0+ CPU
Packaging
7
Packaging
The Automotive PSoC™ 4000S will be offered in 24-QFN and 28-SSOP packages.
Table 37 provides the package dimensions and Infineon drawing numbers.
Table 37
Spec ID
Package list
Package
Description
Package drawing
BID34
24-pin QFN
4 × 4 × 0.6 mm height, 2.75 × 2.75 mm EPAD 002-18982
(Sawn)
BID28
28-pin SSOP 210 Mils O28.21
51-85079
Table 38
Package thermal characteristics
Parameter Description
Package
Conditions
Min
Typ
Max
Unit
TA
Operating ambient
temperature
For A-grade
devices
–40
25
85
°C
For S-grade
devices
For A-grade
devices
For S-grade
devices
–40
–40
–40
25
–
105
100
120
TJ
Operating junction
temperature
°C
–
TJA
TJC
TJA
Package θJA
Package θJC
Package θJA
24-pin QFN
24-pin QFN
28-pin
SSOP
28-pin
SSOP
–
–
21.7
5.6
–
–
°C/Watt
°C/Watt
–
–
66.58
46.28
–
–
°C/Watt
°C/Watt
TJC
Package θJC
Table 39
Solder reflow peak temperature
Package Maximum peak temperature
All 260°C
Maximum time at peak temperature
30 seconds
Table 40
Package moisture sensitivity level (MSL), IPC/JEDEC J-STD-020
Package
MSL
MSL 3
All
Datasheet
38
002-18381 Rev. *H
2023-03-20
Automotive PSoC™ 4: PSoC™ 4000S family datasheet
Based on Arm® Cortex®-M0+ CPU
Packaging
7.1
Package diagrams
002-18982 *A
Figure 4
24-pin QFN package outline
Datasheet
39
002-18381 Rev. *H
2023-03-20
Automotive PSoC™ 4: PSoC™ 4000S family datasheet
Based on Arm® Cortex®-M0+ CPU
Packaging
The center pad on the QFN package should be connected to ground (VSS) for best mechanical, thermal, and
electrical performance. If not connected to ground, it should be electrically floating and not connected to any
other signal.
51-85079 *G
Figure 5
28-pin SSOP package outline
Datasheet
40
002-18381 Rev. *H
2023-03-20
Automotive PSoC™ 4: PSoC™ 4000S family datasheet
Based on Arm® Cortex®-M0+ CPU
Packaging
NOTES:
DIMENSIONS
SYMBOL
e
N
ND
1. ALL DIMENSIONS ARE IN MILLIMETERS.
2. N IS THE TOTAL NUMBER OF TERMINALS.
MIN.
0.35
NOM.
0.50 BSC
40
10
0.40
MAX.
0.45
3
DIMENSION "b" APPLIES TO METALLIZED TERMINAL AND IS MEASURED
BETWEEN 0.15 AND 0.30mm FROM TERMINAL TIP. IF THE TERMINAL HAS
THE OPTIONAL RADIUS ON THE OTHER END OF THE TERMINAL, THE
DIMENSION "b" SHOULD NOT BE MEASURED IN THAT RADIUS AREA.
ND REFERS TO THE NUMBER OF TERMINALS ON D SIDE.
L
b
D2
E2
D
0.20
4.50
4.50
0.25
4.60
4.60
0.30
4.70
4.70
4
5
6
PIN #1 ID ON TOP WILL BE LOCATED WITHIN THE INDICATED ZONE.
COPLANARITY ZONE APPLIES TO THE EXPOSED HEAT SINK
SLUG AS WELL AS THE TERMINALS.
6.00 BSC
E
A
A1
A3
R
6.00 BSC
7. JEDEC SPECIFICATION NO. REF. : N/A.
-
-
-
0.60
0.05
0.00
0.152 REF
0.20 TYP
0.20 MIN
K
002-27464 *B
Figure 6
40-pin QFN package outline
Datasheet
41
002-18381 Rev. *H
2023-03-20
Automotive PSoC™ 4: PSoC™ 4000S family datasheet
Based on Arm® Cortex®-M0+ CPU
Packaging
002-29721 **
Figure 7
48-pin package outline
Datasheet
42
002-18381 Rev. *H
2023-03-20
Automotive PSoC™ 4: PSoC™ 4000S family datasheet
Based on Arm® Cortex®-M0+ CPU
Acronyms
8
Acronyms
Table 41
Acronyms used in this document
Acronym
Description
abus
ADC
AG
analog local bus
analog-to-digital converter
analog global
AMBA (advanced microcontroller bus architecture) high-performance bus, an Arm
data transfer bus
AHB
ALU
arithmetic logic unit
AMUXBUS
API
APSR
Arm®
ATM
BW
analog multiplexer bus
application programming interface
application program status register
advanced RISC machine, a CPU architecture
automatic thump mode
bandwidth
CAN
CMRR
CPU
CRC
DAC
DFB
Controller Area Network, a communications protocol
common-mode rejection ratio
central processing unit
cyclic redundancy check, an error-checking protocol
digital-to-analog converter, see also IDAC, VDAC
digital filter block
DIO
digital input/output, GPIO with only digital capabilities, no analog. See GPIO.
Dhrystone million instructions per second
direct memory access, see also TD
differential nonlinearity, see also INL
do not use
DMIPS
DMA
DNL
DNU
DR
port write data registers
DSI
digital system interconnect
DWT
ECC
data watchpoint and trace
error correcting code
ECO
EEPROM
EMI
EMIF
EOC
EOF
external crystal oscillator
electrically erasable programmable read-only memory
electromagnetic interference
external memory interface
end of conversion
end of frame
EPSR
ESD
execution program status register
electrostatic discharge
ETM
FIR
FPB
embedded trace macrocell
finite impulse response, see also IIR
flash patch and breakpoint
Datasheet
43
002-18381 Rev. *H
2023-03-20
Automotive PSoC™ 4: PSoC™ 4000S family datasheet
Based on Arm® Cortex®-M0+ CPU
Acronyms
Table 41
Acronyms used in this document (continued)
Acronym
Description
FS
full-speed
GPIO
HVI
IC
general-purpose input/output, applies to a PSoC™ pin
high-voltage interrupt, see also LVI, LVD
integrated circuit
IDAC
IDE
I2C, or IIC
IIR
ILO
IMO
INL
current DAC, see also DAC, VDAC
integrated development environment
Inter-Integrated Circuit, a communications protocol
infinite impulse response, see also FIR
internal low-speed oscillator, see also IMO
internal main oscillator, see also ILO
integral nonlinearity, see also DNL
input/output, see also GPIO, DIO, SIO, USBIO
initial power-on reset
I/O
IPOR
IPSR
IRQ
interrupt program status register
interrupt request
ITM
LCD
LIN
instrumentation trace macrocell
liquid crystal display
Local Interconnect Network, a communications protocol.
link register
LR
LUT
LVD
LVI
LVTTL
MAC
MCU
MISO
NC
lookup table
low-voltage detect, see also LVI
low-voltage interrupt, see also HVI
low-voltage transistor-transistor logic
multiply-accumulate
microcontroller unit
master-in slave-out
no connect
NMI
NRZ
NVIC
NVL
opamp
PAL
nonmaskable interrupt
non-return-to-zero
nested vectored interrupt controller
nonvolatile latch, see also WOL
operational amplifier
programmable array logic, see also PLD
program counter
PC
PCB
PGA
PHUB
PHY
PICU
PLA
printed circuit board
programmable gain amplifier
peripheral hub
physical layer
port interrupt control unit
programmable logic array
Datasheet
44
002-18381 Rev. *H
2023-03-20
Automotive PSoC™ 4: PSoC™ 4000S family datasheet
Based on Arm® Cortex®-M0+ CPU
Acronyms
Table 41
Acronyms used in this document (continued)
Acronym
Description
PLD
PLL
programmable logic device, see also PAL
phase-locked loop
PMDD
POR
PRES
PRS
PS
package material declaration data sheet
power-on reset
precise power-on reset
pseudo random sequence
port read data register
PSoC™
PSRR
PWM
RAM
RISC
RMS
RTC
RTL
Programmable System-on-Chip™
power supply rejection ratio
pulse-width modulator
random-access memory
reduced-instruction-set computing
root-mean-square
real-time clock
register transfer language
remote transmission request
receive
RTR
RX
SAR
SC/CT
SCL
SDA
S/H
successive approximation register
switched capacitor/continuous time
I2C serial clock
I2C serial data
sample and hold
SINAD
SIO
SOC
SOF
SPI
signal to noise and distortion ratio
special input/output, GPIO with advanced features. See GPIO.
start of conversion
start of frame
Serial Peripheral Interface, a communications protocol
slew rate
SR
SRAM
SRES
SWD
SWV
TD
THD
TIA
TRM
TTL
static random access memory
software reset
serial wire debug, a test protocol
single-wire viewer
transaction descriptor, see also DMA
total harmonic distortion
transimpedance amplifier
technical reference manual
transistor-transistor logic
transmit
TX
UART
UDB
Universal Asynchronous Transmitter Receiver, a communications protocol
universal digital block
Datasheet
45
002-18381 Rev. *H
2023-03-20
Automotive PSoC™ 4: PSoC™ 4000S family datasheet
Based on Arm® Cortex®-M0+ CPU
Acronyms
Table 41
Acronyms used in this document (continued)
Acronym
Description
USB
Universal Serial Bus
USBIO
VDAC
WDT
USB input/output, PSoC™ pins used to connect to a USB port
voltage DAC, see also DAC, IDAC
watchdog timer
WOL
write once latch, see also NVL
watchdog timer reset
external reset I/O pin
WRES
XRES
XTAL
crystal
Datasheet
46
002-18381 Rev. *H
2023-03-20
Automotive PSoC™ 4: PSoC™ 4000S family datasheet
Based on Arm® Cortex®-M0+ CPU
Document conventions
9
Document conventions
9.1
Table 42
Units of measure
Units of measure
Unit of measure
degrees Celsius
decibel
Symbol
°C
dB
fF
femto farad
Hz
hertz
KB
1024 bytes
kbps
Khr
kHz
k
ksps
LSB
Mbps
MHz
M
Msps
µA
kilobits per second
kilohour
kilohertz
kilo ohm
kilosamples per second
least significant bit
megabits per second
megahertz
mega-ohm
megasamples per second
microampere
microfarad
µF
µH
µs
µV
microhenry
microsecond
microvolt
µW
mA
ms
mV
nA
microwatt
milliampere
millisecond
millivolt
nanoampere
nanosecond
nanovolt
ns
nV
ohm
pF
picofarad
ppm
ps
parts per million
picosecond
s
second
sps
sqrtHz
V
samples per second
square root of hertz
volt
Datasheet
47
002-18381 Rev. *H
2023-03-20
Automotive PSoC™ 4: PSoC™ 4000S family datasheet
Based on Arm® Cortex®-M0+ CPU
Revision history
Revision history
Document
Date
Description of changes
revision
**
2017-01-13
2017-03-06
2017-10-05
New datasheet
*A
*B
Corrected 28-pin SSOP pin details in Table 1.
Updated Automotive PSoC™ 4: PSoC™ 4000S family datasheet, Features,
Timer/Counter/PWM (TCPWM) Block, Ordering information, and
Packaging.
Updated Table 1.
*C
*D
2018-02-22
2018-06-21
Replaced Spec 002-18982 in Figure 4. 24-pin QFN package outline.
Updated Details/Conditions in DC specifications.
Removed SID182B.
Updated 24-pin QFN package diagram.
*E
2020-11-13
Updated I2C mode speed to 1 Mbps (Fast Mode Plus).
Updated VDD and VSS pin notes in Pinouts.
Updated Power.
Updated SID.CLK#6 parameter.
Added SID182B
Added tape and reel to ordering code definition.
Refer to Product Information Notice #6965423.
*F
2021-06-25
Updated Features, Alternate pin functions, and Ordering information.
Added Table 2.
Added package diagrams Figure and Figure .
Updated Copyright information.
*G
*H
2023-01-27
2023-03-20
Updated Ordering information.
Converted to Infineon template
Updated Ordering information.
Datasheet
48
002-18381 Rev. *H
2023-03-20
Please read the Important Notice and Warnings at the end of this document
Trademarks
All referenced product or service names and trademarks are the property of their respective owners.
IMPORTANT NOTICE
WARNINGS
The information given in this document shall in no Due to technical requirements products may contain
Edition 2023-03-20
Published by
event be regarded as a guarantee of conditions or dangerous substances. For information on the types
characteristics (“Beschaffenheitsgarantie”).
in question please contact your nearest Infineon
Technologies office.
With respect to any examples, hints or any typical
Infineon Technologies AG
81726 Munich, Germany
values stated herein and/or any information Except as otherwise explicitly approved by Infineon
regarding the application of the product, Infineon Technologies in
a
written document signed by
Technologies hereby disclaims any and all authorized
representatives of Infineon
warranties and liabilities of any kind, including Technologies, Infineon Technologies’ products may
without limitation warranties of non-infringement of not be used in any applications where a failure of the
intellectual property rights of any third party.
product or any consequences of the use thereof can
reasonably be expected to result in personal injury.
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All Rights Reserved.
In addition, any information given in this document
is subject to customer’s compliance with its
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applicable legal requirements, norms and standards
concerning customer’s products and any use of the
product of Infineon Technologies in customer’s
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Do you have a question about this
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to evaluate the suitability of the product for the
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respect to such application.
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