CY8C4045LQI-S413 [INFINEON]
32位PSoC™ 4 Arm® Cortex®-M0/M0+;
| 型号： | CY8C4045LQI-S413 |
| 厂家： | 
Infineon |
| 描述： | 32位PSoC™ 4 Arm® Cortex®-M0/M0+ |
| 文件： | 总58页 (文件大小：858K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY8C40xx
PSoC™ 4 MCU: PSoC™ 4000S
Based on Arm® Cortex®-M0+ CPU
General description
PSoC™ 4 is a scalable and reconfigurable platform architecture for a family of programmable embedded system
controllers with an Arm® Cortex®-M0+ CPU. It combines programmable and reconfigurable analog and digital
blocks with flexible automatic routing. The PSoC™ 4000S product family is a member of the PSoC™ 4 platform
architecture. It is a combination of a microcontroller with standard communication and timing peripherals, a
capacitive touch-sensing system (CAPSENSE™) with best-in-class performance, programmable general-purpose
continuous-time and switched-capacitor analog blocks, and programmable connectivity. PSoC™ 4000S products
are upward compatible with members of the PSoC™ 4 platform for new applications and design needs.
Features
• 32-bit MCU subsystem
- 48-MHz Arm® Cortex®-M0+ CPU with single-cycle multiply
- Up to 32 KB of flash with read accelerator
- Up to 4 KB of SRAM
• Programmable analog
- Single-slope 10-bit ADC function provided by Capacitance sensing block
- Two current DACs (IDACs) for general-purpose or capacitive sensing applications on any pin
- Two low-power comparators that operate in Deep Sleep low-power mode
• Programmable digital
- Programmable logic blocks allowing boolean operations to be performed on port inputs and outputs
• Low-power 1.71-V to 5.5-V operation
- Deep Sleep mode with operational analog and 2.5 µA digital system current
• Capacitive sensing
- Capacitive sigma-delta provides best-in-class signal-to-noise ratio (SNR) (>5:1) and water tolerance
- Infineon-supplied software component makes capacitive sensing design easy
- Automatic hardware tuning (SmartSense)
• LCD drive capability
- LCD segment drive capability on GPIOs
• Serial communication
- Two independent run-time reconfigurable serial communication blocks (SCBs) with re-configurable I2C, SPI,
or UART functionality
• Timing and pulse-width modulation
- Five 16-bit timer/counter/pulse-width modulator (TCPWM) blocks
- Center-aligned, edge, and pseudo-random modes
- Comparator-based triggering of kill signals for motor drive and other high-reliability digital logic applications
• Up to 36 programmable GPIO pins
- 48-pin TQFP, 40-pin QFN, 32-pin QFN, 24-pin QFN, 32-pin TQFP, and 25-ball WLCSP packages
- Any GPIO pin can be CAPSENSE™, analog, or digital
- Drive modes, strengths, and slew rates are programmable
Datasheet
www.infineon.com
Please read the Important Notice and Warnings at the end of this document
page 1
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PSoC™ 4 MCU: PSoC™ 4000S
Based on Arm® Cortex®-M0+ CPU
Features
• Clock sources
- 32-kHz watch crystal oscillator (WCO)
- ±2% internal main oscillator (IMO)
- 32-kHz internal low-power oscillator (ILO)
• ModusToolbox™ software
- Comprehensive collection of multi-platform tools and software libraries
- Includes board support packages (BSPs), peripheral driver library (PDL), and middleware such as CAPSENSE™
• PSoC™ Creator design environment
- Integrated development environment (IDE) provides schematic design entry and build, with analog and digital
automatic routing
- Application programming interface (API) components for all fixed-function and programmable peripherals
• Industry-standard tool compatibility
- After schematic entry, development can be done with Arm®-based industry-standard development tools
Datasheet
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PSoC™ 4 MCU: PSoC™ 4000S
Based on Arm® Cortex®-M0+ CPU
Table of contents
Table of contents
General description ...........................................................................................................................1
Features ...........................................................................................................................................1
Table of contents...............................................................................................................................3
1 Development ecosystem .................................................................................................................4
1.1 PSoC™ 4 MCU resources .........................................................................................................................................4
1.2 ModusToolbox™ software ......................................................................................................................................5
1.3 PSoC™ Creator ........................................................................................................................................................6
Block diagram...................................................................................................................................7
2 Functional description ....................................................................................................................9
3 Functional definition.....................................................................................................................10
3.1 CPU and memory subsystem ...............................................................................................................................10
3.2 System resources..................................................................................................................................................10
3.3 Analog blocks ........................................................................................................................................................12
3.4 Programmable digital blocks...............................................................................................................................12
3.5 Fixed function digital ............................................................................................................................................13
3.6 GPIO.......................................................................................................................................................................14
3.7 Special function peripherals ................................................................................................................................14
4 Pinouts ........................................................................................................................................15
4.1 Alternate pin functions .........................................................................................................................................17
5 Power ..........................................................................................................................................19
5.1 Mode 1: 1.8 V to 5.5 V external supply..................................................................................................................19
5.2 Mode 2: 1.8 V ± 5% external supply ......................................................................................................................20
6 Electrical specifications.................................................................................................................21
6.1 Absolute maximum ratings ..................................................................................................................................21
6.2 Device level specifications....................................................................................................................................22
6.3 Analog peripherals................................................................................................................................................27
6.4 Digital peripherals.................................................................................................................................................32
6.5 Memory..................................................................................................................................................................36
6.6 System resources..................................................................................................................................................37
7 Ordering information ....................................................................................................................41
8 Packaging ....................................................................................................................................43
8.1 Package diagrams.................................................................................................................................................44
9 Acronyms.....................................................................................................................................49
10 Document conventions................................................................................................................53
10.1 Units of measure .................................................................................................................................................53
Revision history ..............................................................................................................................54
Datasheet
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PSoC™ 4 MCU: PSoC™ 4000S
Based on Arm® Cortex®-M0+ CPU
Development ecosystem
1
Development ecosystem
1.1
PSoC™ 4 MCU resources
Infineon provides a wealth of data at www.cypress.com to help you select the right PSoC™ device and quickly
and effectively integrate it into your design. The following is an abbreviated, hyperlinked list of resources for
PSoC™ 4 MCU:
• Overview: PSoC™ Portfolio, PSoC™ Roadmap
• Product selectors: PSoC™ 4 MCU
• Application notes cover a broad range of topics, from basic to advanced level, and include the following:
- AN79953: Getting Started With PSoC™ 4. This application note has a convenient flow chart to help decide
which IDE to use: ModusToolbox™ software or PSoC™ Creator.
- AN91184: PSoC™ 4 BLE - Designing BLE Applications
- AN88619: PSoC™ 4 hardware design considerations
- AN73854: Introduction To bootloaders
- AN89610: Arm® Cortex® code optimization
- AN86233: PSoC™ 4 MCU power reduction techniques
- AN57821: Mixed signal circuit board layout
- AN85951: PSoC™ 4, PSoC™ 6 CAPSENSE™ design guide
• Code examples demonstrate product features and usage, and are also available on Infineon GitHub
repositories.
• Technical Reference Manuals (TRMs) provide detailed descriptions of PSoC™ 4 MCU architecture and registers.
• PSoC™ 4 MCU programming specification provides the information necessary to program PSoC™ 4 MCU
non-volatile memory.
• Development tools
- ModusToolbox™ software enables cross platform code development with a robust suite of tools and software
libraries.
- PSoC™ Creator is a free Windows-based IDE. It enables concurrent hardware and firmware design of PSoC™
3, PSoC™ 4, PSoC™ 5LP, and PSoC™ 6 MCU based systems. Applications are created using schematic capture
and over 150 pre-verified, production-ready peripheral components.
- CY8CKIT-145-40XX PSoC™ 4000S CAPSENSE™ prototyping kit, is a low-cost and easy-to-use evaluation
platform. This kit provides easy access to all the device I/Os in a breadboard-compatible format.
- MiniProg4 and MiniProg3 all-in-one development programmers and debuggers.
- PSoC™ 4 MCU CAD libraries provide footprint and schematic support for common tools. IBIS models are also
available.
• Training Videos are available on a wide range of topics including the PSoC™ 4 MCU 101 series.
• Infineon developer community enables connection with fellow PSoC™ developers around the world, 24 hours
a day, 7 days a week, and hosts a dedicated PSoC™ 4 MCU community.
Datasheet
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PSoC™ 4 MCU: PSoC™ 4000S
Based on Arm® Cortex®-M0+ CPU
Development ecosystem
1.2
ModusToolbox™ software
ModusToolbox™ software is Infineon’ comprehensive collection of multi-platform tools and software libraries
that enable an immersive development experience for creating converged MCU and wireless systems. It is:
• Comprehensive - it has the resources you need
• Flexible - you can use the resources in your own workflow
• Atomic - you can get just the resources you want
Infineon provides a large collection of code repositories on GitHub, including:
• Board support packages (BSPs) aligned with Infineon kits
• Low-level resources, including a peripheral driver library (PDL)
• Middleware enabling industry-leading features such as CAPSENSE™
• An extensive set of thoroughly tested code example applications
ModusToolbox™ software is IDE-neutral and easily adaptable to your workflow and preferred development
environment. It includes a project creator, peripheral and library configurators, a library manager, as well as the
optional Eclipse IDE for ModusToolbox™, as Figure 1 shows. For information on using Infineon tools, refer to the
documentation delivered with ModusToolbox™ software, and AN79953: Getting Started with PSoC™ 4.
Figure 1
ModusToolbox™ software tools
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PSoC™ 4 MCU: PSoC™ 4000S
Based on Arm® Cortex®-M0+ CPU
Development ecosystem
1.3
PSoC™ Creator
PSoC™ Creator is a free Windows-based IDE. It enables you to design hardware and firmware systems
concurrently, based on PSoC™ 4 MCU. As Figure 2 shows, with PSoC™ Creator you can:
1. Drag and drop component icons to build your hardware system design in the main design workspace
2. Co-design your application firmware with the PSoC™ hardware, using the PSoC™ Creator IDE C compiler
3. Configure components using the configuration tools
4. Explore the library of 100+ components
5. Review component datasheets
6. Prototype your solution with the PSoC™ 4 Pioneer kits. If a design change is needed, PSoC™ Creator and
components enable you to make changes on-the-fly without the need for hardware revisions.
1
2
3
4
5
Figure 2
Multiple-sensor example project in PSoC™ Creator
Datasheet
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PSoC™ 4 MCU: PSoC™ 4000S
Based on Arm® Cortex®-M0+ CPU
Block diagram
Block diagram
CPU Subsystem
SWD/TC
PSoC™ 4000S
Architecture
SPCIF
Cortex® M0+
48 MHz
FLASH
32 KB
SRAM
4 KB
ROM
8 KB
32-bit
FAST MUL
NVIC, IRQMUX
AHB-Lite
SRAM Controller
Read Accelerator
ROM Controller
System Resources
Lite
System Interconnect (Single Layer AHB)
Peripheral Interconnect (MMIO)
Power
Sleep Control
WIC
Peripherals
PCLK
POR
REF
PWRSYS
Clock
Clock Control
WDT
ILO
IMO
Reset
Reset Control
XRES
Test
TestMode Entry
Digital DFT
Analog DFT
High Speed I/O Matrix & 2 x Programmable I/O
36x GPIOs, LCD
Power Modes
Active/Sleep
DeepSleep
I/O Subsystem
PSoC™ 4000S devices include extensive support for programming, testing, debugging, and tracing both hardware
and firmware.
The Arm® serial-wire debug (SWD) interface supports all programming and debug features of the device.
Complete debug-on-chip functionality enables full-device debugging in the final system using the standard
production device. It does not require special interfaces, debugging pods, simulators, or emulators. Only the
standard programming connections are required to fully support debug.
The PSoC™ Creator IDE provides fully integrated programming and debug support for the PSoC™ 4000S devices.
The SWD interface is fully compatible with industry-standard third-party tools. The PSoC™ 4000S provides a level
of security not possible with multi-chip application solutions or with microcontrollers.
It has the following advantages:
• Allows disabling of debug features
• Robust flash protection
• Allows customer-proprietary functionality to be implemented in on-chip programmable blocks
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PSoC™ 4 MCU: PSoC™ 4000S
Based on Arm® Cortex®-M0+ CPU
Block diagram
The debug circuits are enabled by default and can be disabled in firmware. If they are not enabled, the only way
to re-enable them is to erase the entire device, clear flash protection, and reprogram the device with new
firmware that enables debugging. Thus firmware control of debugging cannot be over-ridden without erasing the
firmware thus providing security.
Additionally, all device interfaces can be permanently disabled (device security) for applications concerned
about phishing attacks due to a maliciously reprogrammed device or attempts to defeat security by starting and
interrupting flash programming sequences. All programming, debug, and test interfaces are disabled when
maximum device security is enabled. Therefore, PSoC™ 4000S, with device security enabled, may not be returned
for failure analysis. This is a trade-off the PSoC™ 4000S allows the customer to make.
Datasheet
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PSoC™ 4 MCU: PSoC™ 4000S
Based on Arm® Cortex®-M0+ CPU
Functional description
2
Functional description
PSoC™ 4000S devices include extensive support for programming, testing, debugging, and tracing both hardware
and firmware.
The Arm® serial-wire debug (SWD) interface supports all programming and debug features of the device.
Complete debug-on-chip functionality enables full-device debugging in the final system using the standard
production device. It does not require special interfaces, debugging pods, simulators, or emulators. Only the
standard programming connections are required to fully support debug.
The PSoC™ Creator IDE provides fully integrated programming and debug support for the PSoC™ 4000S devices.
The SWD interface is fully compatible with industry-standard third-party tools. The PSoC™ 4000S family provides
a level of security not possible with multi-chip application solutions or with microcontrollers. It has the following
advantages:
• Allows disabling of debug features
• Robust flash protection
• Allows customer-proprietary functionality to be implemented in on-chip programmable blocks
The debug circuits are enabled by default and can be disabled in firmware. If they are not enabled, the only way
to re-enable them is to erase the entire device, clear flash protection, and reprogram the device with new
firmware that enables debugging. Thus firmware control of debugging cannot be over-ridden without erasing the
firmware thus providing security.
Additionally, all device interfaces can be permanently disabled (device security) for applications concerned
about phishing attacks due to a maliciously reprogrammed device or attempts to defeat security by starting and
interrupting flash programming sequences. All programming, debug, and test interfaces are disabled when
maximum device security is enabled. Therefore, PSoC™ 4000S, with device security enabled, may not be returned
for failure analysis. This is a trade-off the PSoC™ 4000S allows the customer to make.
Datasheet
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PSoC™ 4 MCU: PSoC™ 4000S
Based on Arm® Cortex®-M0+ CPU
Functional definition
3
Functional definition
3.1
CPU and memory subsystem
3.1.1
CPU
The Cortex®-M0+ CPU in the PSoC™ 4000S is part of the 32-bit MCU subsystem, which is optimized for low-power
operation with extensive clock gating. Most instructions are 16 bits in length and the CPU executes a subset of
the thumb-2 instruction set. It includes a nested vectored interrupt controller (NVIC) block with eight interrupt
inputs and also includes a wakeup interrupt controller (WIC). The WIC can wake the processor from Deep Sleep
mode, allowing power to be switched off to the main processor when the chip is in Deep Sleep mode.
The CPU also includes a debug interface, the serial wire debug (SWD) interface, which is a two-wire form of JTAG.
The debug configuration used for PSoC™ 4000S has four breakpoint (address) comparators and two watchpoint
(data) comparators.
3.1.2
Flash
The PSoC™ 4000S device has a flash module with a flash accelerator, tightly coupled to the CPU to improve
average access times from the flash block. The low-power flash block is designed to deliver two wait-state (WS)
access time at 48 MHz. The flash accelerator delivers 85% of single-cycle SRAM access performance on average.
3.1.3
SRAM
Four KB of SRAM are provided with zero wait-state access at 48 MHz.
3.1.4
SROM
A supervisory ROM that contains boot and configuration routines is provided.
3.2
System resources
Power system
3.2.1
The power system is described in detail in the section “Power” on page 19. It provides assurance that voltage
levels are as required for each respective mode and either delays mode entry (for example, on power-on reset
(POR)) until voltage levels are as required for proper functionality, or generates resets (for example, on brown-out
detection). The PSoC™ 4000S operates with a single external supply over the range of either 1.8 V ±5% (externally
regulated) or 1.8 to 5.5 V (internally regulated) and has three different power modes, transitions between which
are managed by the power system. The PSoC™ 4000S provides Active, Sleep, and Deep Sleep low-power modes.
All subsystems are operational in Active mode. The CPU subsystem (CPU, flash, and SRAM) is clock-gated off in
Sleep mode, while all peripherals and interrupts are active with instantaneous wake-up on a wake-up event. In
Deep Sleep mode, the high-speed clock and associated circuitry is switched off; wake-up from this mode takes
35 µs.
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PSoC™ 4 MCU: PSoC™ 4000S
Based on Arm® Cortex®-M0+ CPU
Functional definition
3.2.2
Clock system
The PSoC™ 4000S clock system is responsible for providing clocks to all subsystems that require clocks and for
switching between different clock sources without glitching. In addition, the clock system ensures that there are
no metastable conditions.
The clock system for the PSoC™ 4000S consists of the internal main oscillator (IMO), internal low-frequency
oscillator (ILO), a 32 kHz watch crystal oscillator (WCO) and provision for an external clock. Clock dividers are
provided to generate clocks for peripherals on a fine-grained basis. Fractional dividers are also provided to
enable clocking of higher data rates for UARTs.
The HFCLK signal can be divided down to generate synchronous clocks for the analog and digital peripherals.
There are eight clock dividers for the PSoC™ 4000S, two of those are fractional dividers. The 16-bit capability
allows flexible generation of fine-grained frequency values, and is fully supported in PSoC™ Creator.
HFCLK
IMO
Divide By
2,4,8
External Clock
LFCLK
ILO
Prescaler
SYSCLK
HFCLK
Integer
Dividers
6X 16-bit
Fractional
Dividers
2X 16.5-bit
Figure 3
PSoC™ 4000S MCU clocking architecture
3.2.3
IMO clock source
The IMO is the primary source of internal clocking in the PSoC™ 4000S. It is trimmed during testing to achieve the
specified accuracy. The IMO default frequency is 24 MHz and it can be adjusted from 24 to 48 MHz in steps of
4 MHz. The IMO tolerance with Infineon-provided calibration settings is ±2%.
3.2.4
ILO clock source
The ILO is a very low power, nominally 40-kHz oscillator, which is primarily used to generate clocks for the
watchdog timer (WDT) and peripheral operation in Deep Sleep mode. ILO-driven counters can be calibrated to
the IMO to improve accuracy. Infineon provides a software component, which does the calibration.
3.2.5
Watch crystal oscillator (WCO)
The PSoC™ 4000S clock subsystem also implements a low-frequency (32-kHz watch crystal) oscillator that can
be used for precision timing applications. The WCO block allows locking the IMO to the 32-kHz oscillator. The
WCO on PSoC™ 4000S series devices does not connect to the LFCLK or WDT. Due to this, RTC functionality is not
supported.
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PSoC™ 4 MCU: PSoC™ 4000S
Based on Arm® Cortex®-M0+ CPU
Functional definition
3.2.6
Watchdog timer
A watchdog timer is implemented in the clock block running from the ILO; this allows watchdog operation during
Deep Sleep and generates a watchdog reset if not serviced before the set timeout occurs. The watchdog reset is
recorded in a Reset Cause Register, which is firmware readable.
3.2.7
Reset
The PSoC™ 4000S can be reset from a variety of sources including a software reset. Reset events are asynchronous
and guarantee reversion to a known state. The reset cause is recorded in a register, which is sticky through reset
and allows software to determine the cause of the reset. An XRES pin is reserved for external reset by asserting it
active low. The XRES pin has an internal pull-up resistor that is always enabled.
3.2.8
Voltage reference
The PSoC™ 4000S reference system generates all internally required references. A 1.2-V voltage reference is
provided for the comparator. The IDACs are based on a ±5% reference.
3.3
Analog blocks
3.3.1
Low-power comparators (LPC)
The PSoC™ 4000S has a pair of low-power comparators, which can also operate in Deep Sleep modes. This allows
the analog system blocks to be disabled while retaining the ability to monitor external voltage levels during
low-power modes. The comparator outputs are normally synchronized to avoid metastability unless operating
in an asynchronous power mode where the system wake-up circuit is activated by a comparator switch event.
The LPC outputs can be routed to pins.
3.3.2
Current DACs
The PSoC™ 4000S has two IDACs, which can drive any of the pins on the chip. These IDACs have programmable
current ranges.
3.3.3
Analog multiplexed buses
The PSoC™ 4000S has two concentric independent buses that go around the periphery of the chip. These buses
(called amux buses) are connected to firmware-programmable analog switches that allow the chip’s internal
resources (IDACs, comparator) to connect to any pin on the I/O Ports.
3.4
Programmable digital blocks
The programmable I/O (Smart I/O) block is a fabric of switches and LUTs that allows boolean functions to be
performed in signals being routed to the pins of a GPIO port. The Smart I/O can perform logical operations on
input pins to the chip and on signals going out as outputs.
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Based on Arm® Cortex®-M0+ CPU
Functional definition
3.5
Fixed function digital
3.5.1
Timer/Counter/PWM (TCPWM) block
The TCPWM block consists of a 16-bit counter with user-programmable period length. There is a capture register
to record the count value at the time of an event (which may be an I/O event), a period register that is used to
either stop or auto-reload the counter when its count is equal to the period register, and compare registers to
generate compare value signals that are used as PWM duty cycle outputs. The block also provides true and
complementary outputs with programmable offset between them to allow use as dead-band programmable
complementary PWM outputs. It also has a kill input to force outputs to a predetermined state; for example, this
is used in motor drive systems when an over-current state is indicated and the PWM driving the FETs needs to be
shut off immediately with no time for software intervention. There are five TCPWM blocks in the PSoC™ 4000S.
3.5.2
Serial communication block (SCB)
The PSoC™ 4000S has two serial communication blocks, which can be programmed to have SPI, I2C, or UART
functionality.
I2C Mode: The hardware I2C block implements a full multi-master and slave interface (it is capable of
multi-master arbitration). This block is capable of operating at speeds of up to 1 Mbps (Fast Mode Plus) and has
flexible buffering options to reduce interrupt overhead and latency for the CPU. It also supports EZI2C that
creates a mailbox address range in the memory of the PSoC™ 4000S and effectively reduces I2C communication
to reading from and writing to an array in memory. In addition, the block supports an 8-deep FIFO for receive and
transmit which, by increasing the time given for the CPU to read data, greatly reduces the need for clock
stretching caused by the CPU not having read data on time.
The I2C peripheral is compatible with the I2C Standard-mode and Fast-mode devices as defined in the NXP
I2C-bus specification and user manual (UM10204). The I2C bus I/O is implemented with GPIO in open-drain
modes.
The PSoC™ 4000S is not completely compliant with the I2C spec in the following respect:
• GPIO cells are not over-voltage tolerant and, therefore, cannot be hot-swapped or powered up independently
of the rest of the I2C system.
UART Mode: This is a full-feature UART operating at up to 1 Mbps. It supports automotive single-wire interface
(LIN), infrared interface (IrDA), and SmartCard (ISO7816) protocols, all of which are minor variants of the basic
UART protocol. In addition, it supports the 9-bit multiprocessor mode that allows addressing of peripherals
connected over common RX and TX lines. Common UART functions such as parity error, break detect, and frame
error are supported. An 8-deep FIFO allows much greater CPU service latencies to be tolerated.
SPI Mode: The SPI mode supports full Motorola SPI, TI SSP (adds a start pulse used to synchronize SPI Codecs),
and National Microwire (half-duplex form of SPI). The SPI block can use the FIFO.
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Based on Arm® Cortex®-M0+ CPU
Functional definition
3.6
GPIO
The PSoC™ 4000S has up to 36 GPIOs. The GPIO block implements the following:
• Eight drive modes:
- Analog input mode (input and output buffers disabled)
- Input only
- Weak pull-up with strong pull-down
- Strong pull-up with weak pull-down
- Open drain with strong pull-down
- Open drain with strong pull-up
- Strong pull-up with strong pull-down
- Weak pull-up with weak pull-down
• Input threshold select (CMOS or LVTTL).
• Individual control of input and output buffer enabling/disabling in addition to the drive strength modes
• Selectable slew rates for dV/dt related noise control to improve EMI
The pins are organized in logical entities called ports, which are 8-bit in width (less for ports 2 and 3). During
power-on and reset, the blocks are forced to the disable state so as not to crowbar any inputs and/or cause excess
turn-on current. A multiplexing network known as a high-speed I/O matrix is used to multiplex between various
signals that may connect to an I/O pin.
Data output and pin state registers store, respectively, the values to be driven on the pins and the states of the
pins themselves.
Every I/O pin can generate an interrupt if so enabled and each I/O port has an interrupt request (IRQ) and interrupt
service routine (ISR) vector associated with it (5 for PSoC™ 4000S).
3.7
3.7.1
Special function peripherals
CAPSENSE™
CAPSENSE™ is supported in the PSoC™ 4000S through a CAPSENSE™ Sigma-Delta (CSD) block that can be
connected to any pins through an analog multiplex bus via analog switches. CAPSENSE™ function can thus be
provided on any available pin or group of pins in a system under software control. A PSoC™ Creator component
is provided for the CAPSENSE™ block to make it easy for the user.
Shield voltage can be driven on another analog multiplex bus to provide water-tolerance capability. Water
tolerance is provided by driving the shield electrode in phase with the sense electrode to keep the shield
capacitance from attenuating the sensed input. Proximity sensing can also be implemented.
The CAPSENSE™ block has two IDACs, which can be used for general purposes if CAPSENSE™ is not being used
(both IDACs are available in that case) or if CAPSENSE™ is used without water tolerance (one IDAC is available).
The CAPSENSE™ block also provides a 10-bit slope ADC function, which can be used in conjunction with the
CAPSENSE™ function.
The CAPSENSE™ block is an advanced, low-noise, programmable block with programmable voltage references
and current source ranges for improved sensitivity and flexibility. It can also use an external reference voltage. It
has a full-wave CSD mode that alternates sensing to VDDA and Ground to null out power-supply related noise.
3.7.2
LCD segment drive
The PSoC™ 4000S has an LCD controller, which can drive up to 8 commons and up to 28 segments. It uses full
digital methods to drive the LCD segments requiring no generation of internal LCD voltages. The two methods
used are referred to as digital correlation and PWM. Digital correlation pertains to modulating the frequency and
drive levels of the common and segment signals to generate the highest RMS voltage across a segment to light it
up or to keep the RMS signal to zero. This method is good for STN displays but may result in reduced contrast
with TN (cheaper) displays. PWM pertains to driving the panel with PWM signals to effectively use the capacitance
of the panel to provide the integration of the modulated pulse-width to generate the desired LCD voltage. This
method results in higher power consumption but can result in better results when driving TN displays.
Datasheet
14
002-00123 Rev. *P
2023-01-23
PSoC™ 4 MCU: PSoC™ 4000S
Based on Arm® Cortex®-M0+ CPU
Pinouts
4
Pinouts
The following table provides the pin list for PSoC™ 4000S for the 48-pin TQFP, 40-pin QFN, 32-pin QFN,
24-pin QFN, 32-pin TQFP, and 25-ball CSP packages. All port pins support GPIO. Pin 11 is a No-Connect in the
48-TQFP.
Table 1
48-pin TQFP
PSoC™ 4000S pin list
32-pin QFN
24-pin QFN
25-ball CSP
40-pin QFN
32-pin TQFP
Pin
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
1
Name
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
XRES
VCCD
VSSD
VDDD
VDDA
VSSA
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
VSSD
P3.0
P3.1
Pin
17
18
19
20
21
22
23
Name
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
Pin
13
14
Name
P0.0
P0.1
Pin
D1
C3
Name
P0.0
P0.1
Pin
Name
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
XRES
VCCD
Pin
17
18
19
20
21
22
23
Name
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
22
23
24
25
26
27
28
29
30
31
15
16
17
P0.4
P0.5
P0.6
C2
C1
B1
B2
B3
A1
A2
A3
A3
A2
P0.4
P0.5
P0.6
P0.7
XRES
VCCD
VSS
VDD
VDD
VSS
24
25
26
27
27
28
29
30
31
32
XRES
VCCD
VSSD
VDD
18
19
20
21
21
22
XRES
VCCD
VSSD
VDD
VDD
VSSA
24
25
26
27
27
28
29
30
31
32
XRES
VCCD
VSSD
VDD
32
33
34
35
36
37
38
39
VDDD
VDDA
VSSA
P1.0
P1.1
P1.2
P1.3
P1.4
VDD
VDD
VSSA
P1.0
P1.1
P1.2
P1.3
VSSA
P1.0
P1.1
P1.2
P1.3
23
24
P1.2
P1.3
A4
B4
P1.2
P1.3
1
2
3
4
5
P1.7
P2.0
P2.1
P2.2
P2.3
1
2
3
P1.7
P2.0
P2.1
A5
B5
C5
P1.7
P2.0
P2.1
40
1
2
3
4
5
6
7
8
P1.7
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
VSSD
P3.0
P3.1
1
2
3
4
5
P1.7
P2.0
P2.1
P2.2
P2.3
2
3
4
5
6
7
8
9
6
7
8
P2.5
P2.6
P2.7
6
7
8
P2.5
P2.6
P2.7
4
5
P2.6
P2.7
D5
C4
A2
E5
D4
P2.6
P2.7
VSS
P3.0
P3.1
10
12
13
9
10
11
9
10
P3.0
P3.1
6
P3.0
9
10
P3.0
P3.1
Datasheet
15
002-00123 Rev. *P
2023-01-23
PSoC™ 4 MCU: PSoC™ 4000S
Based on Arm® Cortex®-M0+ CPU
Pinouts
Table 1
48-pin TQFP
PSoC™ 4000S pin list (continued)
32-pin QFN 24-pin QFN
25-ball CSP
40-pin QFN
32-pin TQFP
Pin
14
16
17
18
19
20
21
22
23
24
25
Name
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
VDDD
P4.0
P4.1
P4.2
P4.3
Pin
11
12
Name
P3.2
P3.3
Pin
7
8
Name
P3.2
P3.3
Pin
E4
D3
Name
P3.2
P3.3
Pin
Name
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
Pin
11
12
Name
P3.2
P3.3
12
13
14
15
16
17
13
14
15
16
P4.0
P4.1
P4.2
P4.3
9
P4.0
P4.1
P4.2
P4.3
E3
D2
E2
E1
P4.0
P4.1
P4.2
P4.3
18
19
20
21
P4.0
P4.1
P4.2
P4.3
13
14
15
16
P4.0
P4.1
P4.2
P4.3
10
11
12
Note: Pins 11, 15, 26, and 27 are No connects (NC) on the 48-pin TQFP.
Descriptions of the pin functions are as follows:
VDDD: Power supply for the digital section.
VDDA: Power supply for the analog section.
VSSD, VSSA: Ground pins for the digital and analog sections respectively.
VCCD: Regulated digital supply (1.8 V ± 5%)
VDD: Power supply to all sections of the chip
VSS: Ground for all sections of the chip
Datasheet
16
002-00123 Rev. *P
2023-01-23
4.1
Alternate pin functions
Each port pin can be assigned to one of multiple functions; it can, for instance, be an analog I/O, a digital peripheral function, an LCD pin, or a CAPSENSE™
pin. The pin assignments are shown in the following table.
Table 2
Port/Pin
P0.0
Pin assignments
Analog
Smart I/O
Alternate Function 1 Alternate Function 2 Alternate Function 3
Deep Sleep 1
Deep Sleep 2
lpcomp.in_p[0]
lpcomp.in_n[0]
lpcomp.in_p[1]
lpcomp.in_n[1]
wco.wco_in
tcpwm.tr_in[0]
tcpwm.tr_in[1]
scb[0].spi_select1:0
scb[0].spi_select2:0
scb[0].spi_select3:0
P0.1
P0.2
P0.3
P0.4
scb[1].uart_rx:0
scb[1].uart_tx:0
scb[1].i2c_scl:0
scb[1].i2c_sda:0
scb[1].spi_mosi:1
scb[1].spi_miso:1
scb[1].spi_clk:1
P0.5
wco.wco_out
P0.6
srss.ext_clk
scb[1].uart_cts:0
scb[1].uart_rts:0
P0.7
scb[1].spi_select0:1
P1.0
P1.1
tcpwm.line[2]:1
scb[0].uart_rx:1
scb[0].uart_tx:1
scb[0].i2c_scl:0
scb[0].i2c_sda:0
scb[0].spi_mosi:1
scb[0].spi_miso:1
tcpwm.line_compl[2]:1
P1.2
P1.3
tcpwm.line[3]:1
scb[0].uart_cts:1
scb[0].uart_rts:1
tcpwm.tr_in[2]
tcpwm.tr_in[3]
scb[0].spi_clk:1
tcpwm.line_compl[3]:1
scb[0].spi_select0:1
P1.4
P1.5
P1.6
scb[0].spi_select1:1
scb[0].spi_select2:1
scb[0].spi_select3:1
P1.7
P2.0
prgio[0].io[0]
tcpwm.line[4]:0
csd.comp
tcpwm.tr_in[4]
tcpwm.tr_in[5]
scb[1].i2c_scl:1
scb[1].i2c_sda:1
scb[1].spi_mosi:2
P2.1
P2.2
P2.3
prgio[0].io[1]
prgio[0].io[2]
prgio[0].io[3]
tcpwm.line_compl[4]:0
scb[1].spi_miso:2
scb[1].spi_clk:2
scb[1].spi_select0:2
Table 2
Port/Pin
P2.4
Pin assignments (continued)
Analog
Smart I/O
Alternate Function 1 Alternate Function 2 Alternate Function 3
Deep Sleep 1
Deep Sleep 2
prgio[0].io[4]
prgio[0].io[5]
prgio[0].io[6]
prgio[0].io[7]
prgio[1].io[0]
tcpwm.line[0]:1
tcpwm.line_compl[0]:1
tcpwm.line[1]:1
scb[1].spi_select1:1
scb[1].spi_select2:1
scb[1].spi_select3:1
P2.5
P2.6
P2.7
tcpwm.line_compl[1]:1
lpcomp.comp[0]:1
scb[1].i2c_scl:2
P3.0
tcpwm.line[0]:0
scb[1].uart_rx:1
scb[1].uart_tx:1
scb[1].spi_mosi:0
scb[1].spi_miso:0
P3.1
prgio[1].io[1]
tcpwm.line_compl[0]:0
scb[1].i2c_sda:2
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
P4.0
P4.1
prgio[1].io[2]
prgio[1].io[3]
prgio[1].io[4]
prgio[1].io[5]
prgio[1].io[6]
prgio[1].io[7]
tcpwm.line[1]:0
tcpwm.line_compl[1]:0
tcpwm.line[2]:0
scb[1].uart_cts:1
scb[1].uart_rts:1
cpuss.swd_data
cpuss.swd_clk
scb[1].spi_clk:0
scb[1].spi_select0:0
scb[1].spi_select1:0
scb[1].spi_select2:0
scb[1].spi_select3:0
tcpwm.tr_in[6]
tcpwm.tr_in[7]
tcpwm.tr_in[8]
tcpwm.tr_in[9]
tcpwm.tr_in[10]
tcpwm.tr_in[11]
tcpwm.line_compl[2]:0
tcpwm.line[3]:0
tcpwm.line_compl[3]:0
lpcomp.comp[1]:1
scb[0].i2c_scl:1
scb[0].i2c_sda:1
csd.vref_ext
scb[0].uart_rx:0
scb[0].uart_tx:0
scb[0].spi_mosi:0
scb[0].spi_miso:0
csd.cshieldpads
P4.2
P4.3
csd.cmodpad
csd.csh_tank
scb[0].uart_cts:0
scb[0].uart_rts:0
lpcomp.comp[0]:0
lpcomp.comp[1]:0
scb[0].spi_clk:0
scb[0].spi_select0:0
PSoC™ 4 MCU: PSoC™ 4000S
Based on Arm® Cortex®-M0+ CPU
Power
5
Power
The following power system diagram shows the set of power supply pins as implemented for the PSoC™ 4000S.
The system has one regulator in Active mode for the digital circuitry. There is no analog regulator; the analog
circuits run directly from the VDD input.
VDDA
VDDD
VDDA
VSSA
VDDD
VSSD
Analog
Domain
Digital
Domain
VCCD
1.8 Volt
Regulator
Figure 4
Power supply connections
There are two distinct modes of operation. In Mode 1, the supply voltage range is 1.8 V to 5.5 V (unregulated
externally; internal regulator operational). In Mode 2, the supply range is1.8 V ± 5% (externally regulated; 1.71 V
to 1.89 V, internal regulator bypassed).
5.1
Mode 1: 1.8 V to 5.5 V external supply
In this mode, the PSoC™ 4000S is powered by an external power supply that can be anywhere in the range of
1.8 V to 5.5 V. This range is also designed for battery-powered operation. For example, the chip can be powered
from a battery system that starts at 3.5 V and works down to 1.8 V. In this mode, the internal regulator of the
PSoC™ 4000S supplies the internal logic and its output is connected to the VCCD pin. The VCCD pin must be
bypassed to ground via an external capacitor (0.1 µF; X5R ceramic or better) and must not be connected to
anything else.
Datasheet
19
002-00123 Rev. *P
2023-01-23
PSoC™ 4 MCU: PSoC™ 4000S
Based on Arm® Cortex®-M0+ CPU
Power
5.2
Mode 2: 1.8 V ± 5% external supply
In this mode, the PSoC™ 4000S is powered by an external power supply that must be within the range of 1.71 V to
1.89 V; note that this range needs to include the power supply ripple too. In this mode, the VDD and VCCD pins
are shorted together and bypassed. The internal regulator can be disabled in the firmware.
Bypass capacitors must be used from VDDD to ground. The typical practice for systems in this frequency range is
to use a capacitor in the 1-µF range, in parallel with a smaller capacitor (0.1 µF, for example). Note that these are
simply rules of thumb and that, for critical applications, the PCB layout, lead inductance, and the bypass
capacitor parasitic should be simulated to design and obtain optimal bypassing.
An example of a bypass scheme is shown in the following diagram.
Power supply bypass connections example
1.8V to 5.5V
0.1mF
1.8V to 5.5V
0.1mF
PSoCTM 4000S
VDDA
VDD
1 mF
VCCD
0.1mF
VSS
Figure 5
External supply range from 1.8 V to 5.5 V with internal regulator active
Datasheet
20
002-00123 Rev. *P
2023-01-23
PSoC™ 4 MCU: PSoC™ 4000S
Based on Arm® Cortex®-M0+ CPU
Electrical specifications
6
Electrical specifications
6.1
Absolute maximum ratings
Table 3
Absolute maximum ratings[1]
Spec ID# Parameter
Description
Min
Typ
Max Units Details/conditions
SID1
VDDD_ABS
VCCD_ABS
VGPIO_ABS
IGPIO_ABS
Digital supply relative to VSS
Direct digital core voltage
input relative to VSS
GPIO voltage
Maximum current per GPIO
GPIO injection current,
–0.5
–
6
–
SID2
–0.5
–
1.95
V
–
SID3
SID4
–0.5
–25
–
–
VDD + 0.5
25
–
–
mA
Current injected
per pin
SID5
IGPIO_injection Max for VIH > VDDD, and
Min for VIL < VSS
–0.5
–
–
0.5
–
Electrostatic discharge
human body model
Electrostatic discharge
charged device model
BID44
ESD_HBM
2200
–
V
BID45
BID46
ESD_CDM
500
–
–
–
–
–
LU
Pin current for latch-up
–140
140
mA
Note
1. Usage above the absolute maximum conditions listed in Table 3 may cause permanent damage to the device. Exposure to absolute
maximum conditions for extended periods of time may affect device reliability. The maximum storage temperature is 150°C in com-
pliance with JEDEC Standard JESD22-A103, High Temperature Storage Life. When used below absolute maximum conditions but
above normal operating conditions, the device may not operate to specification.
Datasheet
21
002-00123 Rev. *P
2023-01-23
PSoC™ 4 MCU: PSoC™ 4000S
Based on Arm® Cortex®-M0+ CPU
Electrical specifications
6.2
Device level specifications
All specifications are valid for –40°C TA 105°C and TJ 125°C, except where noted. Specifications are valid for
1.71 V to 5.5 V, except where noted.
Table 4
DC specifications
Typical values measured at VDD = 3.3 V and 25°C.
Spec ID Parameter
SID53 VDD
Description
Min
Typ
Max Units Details/conditions
Internally regulated
supply
Power supply input voltage
Power supply input voltage
1.8
–
5.5
Internally unregulated
supply
SID255 VDD
1.71
–
1.89
V
(VCCD = VDD = VDDA
)
Output voltage
(for core logic)
External regulator voltage
bypass
Power supply bypass
capacitor
SID54
SID55
SID56
VCCD
CEFC
CEXC
–
–
–
1.8
0.1
1
–
–
–
–
X5R ceramic or better
X5R ceramic or better
µF
Active Mode, VDD = 1.8 V to 5.5 V. Typical values measured at VDD = 3.3 V and 25°C.
Execute from flash;
SID10
SID16
SID19
IDD5
IDD8
IDD11
–
–
–
1.2
2.4
4.6
2.0
4.0
5.9
–
–
–
CPU at 6 MHz
Execute from flash;
CPU at 24 MHz
Execute from flash;
CPU at 48 MHz
mA
mA
Sleep Mode, VDDD = 1.8 V to 5.5 V (Regulator on)
I2C wakeup WDT, and
SID22
SID25
IDD17
IDD20
–
–
1.1
1.4
1.6
1.9
6 MHz
comparators on
I2C wakeup, WDT, and
comparators on
12 MHz
Sleep Mode, VDDD = 1.71 V to 1.89 V (Regulator bypassed)
I2C wakeup, WDT, and
SID28
IDD23
–
–
0.7
0.9
0.9
1.1
mA 6 MHz
Comparators on
I2C wakeup, WDT, and
Comparators on
SID28A IDD23A
mA 12 MHz
Deep Sleep Mode, VDD = 1.8 V to 3.6 V (Regulator on)
SID31 IDD26
I2C wakeup and WDT on
Deep Sleep Mode, VDD = 3.6 V to 5.5 V (Regulator on)
SID34 IDD29
I2C wakeup and WDT on
–
–
2.5
2.5
60
60
60
µA
µA
µA
–
–
–
Deep Sleep Mode, VDD = VCCD = 1.71 V to 1.89 V (Regulator bypassed)
SID37
IDD32
I2C wakeup and WDT on
–
2.5
XRES Current
Supply current while XRES
asserted
SID307 IDD_XR
–
2
5
mA
–
Datasheet
22
002-00123 Rev. *P
2023-01-23
PSoC™ 4 MCU: PSoC™ 4000S
Based on Arm® Cortex®-M0+ CPU
Electrical specifications
Table 5
AC specifications
Description
CPU frequency
Spec ID Parameter
SID48
SID49[2] TSLEEP
Min
DC
–
Typ
–
0
Max Units Details/conditions
FCPU
48
–
MHz 1.71 V VDD 5.5 V
Wakeup from Sleep mode
–
µs
Wakeup from Deep Sleep
mode
SID50[2] TDEEPSLEEP
–
35
–
–
Note
2. Guaranteed by characterization.
Datasheet
23
002-00123 Rev. *P
2023-01-23
PSoC™ 4 MCU: PSoC™ 4000S
Based on Arm® Cortex®-M0+ CPU
Electrical specifications
6.2.1
GPIO
Table 6
GPIO DC specifications
Spec ID
Parameter
Description
Min
Typ
Max
Units Details/conditions
Input voltage high
threshold
Input voltage low
threshold
LVTTL input,
VDDD < 2.7 V
LVTTL input,
VDDD < 2.7 V
[3]
SID57
SID58
SID241
SID242
SID243
SID244
SID59
SID60
SID61
SID62
SID62A
VIH
0.7 VDDD
–
–
CMOS input
VIL
VIH
VIL
VIH
VIL
–
–
–
–
–
–
–
–
–
–
–
0.3 VDDD
CMOS input
[3]
[3]
0.7 VDDD
–
–
–
–
–
0.3 VDDD
LVTTL input,
2.0
–
VDDD 2.7 V
LVTTL input,
DDD 2.7 V
–
0.8
–
V
–
V
Output voltage high
level
Output voltage high
level
Output voltage low
level
Output voltage low
level
IOH = 4 mA
at 3 V VDDD
IOH = 1 mA
at 3 V VDDD
IOL = 4 mA
at 1.8 V VDDD
IOL = 10 mA
at 3 V VDDD
IOL = 3 mA
at 3 V VDDD
VOH
VOH
VOL
VOL
VDDD – 0.6
VDDD – 0.5
–
–
–
–
0.6
0.6
0.4
Output voltage low
level
VOL
SID63
SID64
RPULLUP
Pull-up resistor
3.5
3.5
5.6
5.6
8.5
8.5
–
–
kΩ
RPULLDOWN Pull-down resistor
Input leakage current
(absolute value)
SID65
IIL
–
–
2
nA 25°C, VDDD = 3.0 V
SID66
CIN
VHYSTTL
VHYSCMOS
Input capacitance
Input hysteresis LVTTL
Input hysteresis CMOS 0.05 × VDDD
–
25
–
40
–
7
–
–
–
pF
–
V
SID67[4]
SID68[4]
DDD 2.7 V
mV VDD < 4.5 V
VDD > 4.5 V
SID68A[4] VHYSCMOS5V5 Input hysteresis CMOS
Current through
200
–
SID69[4]
IDIODE
protection diode to
VDD/VSS
Maximum total source
or sink chip current
–
–
–
100
200
µA
–
–
SID69A[4] ITOT_GPIO
–
mA
Notes
3. VIH must not exceed VDDD + 0.2 V.
4. Guaranteed by characterization.
Datasheet
24
002-00123 Rev. *P
2023-01-23
PSoC™ 4 MCU: PSoC™ 4000S
Based on Arm® Cortex®-M0+ CPU
Electrical specifications
Table 7
GPIO AC Specifications
(Guaranteed by characterization)
Spec ID Parameter
Description
Min
Typ
Max Units Details/conditions
Rise time in fast strong
mode
3.3 V VDDD
,
SID70
SID71
SID72
SID73
TRISEF
TFALLF
TRISES
TFALLS
2
–
12
12
60
60
Cload = 25 pF
ns
3.3 V VDDD
,
Fall time in fast strong mode
2
–
–
–
Cload = 25 pF
Rise time in slow strong
mode
Fall time in slow strong
mode
3.3 V VDDD
,
10
10
–
–
Cload = 25 pF
3.3 V VDDD,
Cload = 25 pF
GPIO FOUT
;
90/10%, 25 pF load,
60/40 duty cycle
SID74
SID75
SID76
FGPIOUT1
FGPIOUT2
FGPIOUT3
3.3 V VDDD 5.5 V;
–
–
–
–
–
–
–
–
–
–
33
16.7
7
fast strong mode
GPIO FOUT
;
90/10%, 25 pF load,
60/40 duty cycle
1.71 VVDDD3.3 V;
fast strong mode
GPIO FOUT
;
90/10%, 25 pF load,
60/40 duty cycle
3.3 V VDDD 5.5 V;
MHz
slow strong mode
GPIO FOUT
;
90/10%, 25 pF load,
60/40 duty cycle
SID245 FGPIOUT4
SID246 FGPIOIN
1.71 V VDDD 3.3 V;
3.5
48
slow strong mode
GPIO input operating
frequency;
1.71 V VDDD 5.5 V
90/10% VIO
Datasheet
25
002-00123 Rev. *P
2023-01-23
PSoC™ 4 MCU: PSoC™ 4000S
Based on Arm® Cortex®-M0+ CPU
Electrical specifications
6.2.2
XRES
Table 8
XRES DC specifications
Spec ID Parameter
Description
Input voltage high threshold 0.7 × VDDD
Input voltage low threshold
Pull-up resistor
Input capacitance
Min
Typ
–
–
60
–
Max
–
0.3 × VDDD
Units Details/conditions
SID77
SID78
SID79
SID80
VIH
VIL
RPULLUP
CIN
V
CMOS Input
–
–
–
–
7
kΩ
–
pF
–
Typical hysteresis
SID81[5] VHYSXRES
Input voltage hysteresis
–
–
100
–
–
mV is 200 mV for
VDD > 4.5 V
Current through protection
diode to VDD/VSS
SID82
IDIODE
100
µA
–
Table 9
XRES AC specifications
Parameter Description
TRESETWIDTH Reset pulse width
Spec ID
SID83[5]
Min
1
–
Typ
–
–
Max Units Details/conditions
–
µs
–
–
BID194[5] TRESETWAKE Wake-up time from reset
release
2.7
ms
Note
5. Guaranteed by characterization.
Datasheet
26
002-00123 Rev. *P
2023-01-23
PSoC™ 4 MCU: PSoC™ 4000S
Based on Arm® Cortex®-M0+ CPU
Electrical specifications
6.3
Analog peripherals
Comparator
6.3.1
Table 10
Comparator DC specifications
Spec ID Parameter
Description
Min
Typ
Max
Units Details/conditions
Input offset voltage, factory
trim
SID84
VOFFSET1
–
–
±10
–
Input offset voltage, custom
trim
Hysteresis when enabled
Input common mode
voltage in normal mode
mV
–
SID85
SID86
SID87
VOFFSET2
VHYST
–
–
0
–
10
–
±4
35
–
VICM1
VDDD – 0.1
Modes 1 and 2
Input common mode
SID247 VICM2
SID247A VICM3
0
0
–
–
–
VDDD
VDDD – 1.15
–
–
V
voltage in low power mode
Input common mode
voltage in ultra low power
mode
Common mode rejection
ratio
Common mode rejection
ratio
Block current, normal mode
Block current, low power
mode
Block current in ultra
low-power mode
DC Input impedance of
comparator
VDDD ≥ 2.2 V at
–40°C
SID88
CMRR
50
VDDD ≥ 2.7V
dB
SID88A CMRR
SID89 ICMP1
42
–
–
–
–
–
VDDD ≤ 2.7V
400
100
–
SID248 ICMP2
SID259 ICMP3
–
–
µA
VDDD ≥ 2.2 V at
–40°C
–
6
–
28
–
SID90
ZCMP
35
MΩ
–
Table 11
Comparator AC specifications
Spec ID Parameter
Description
Min
Typ
Max Units Details/conditions
Response time, normal
mode, 50 mV overdrive
Response time, low power
mode, 50 mV overdrive
Response time, ultra-low
power mode, 200 mV
overdrive
SID91
TRESP1
–
38
70
110
200
–
–
ns
µs
SID258 TRESP2
–
–
VDDD ≥ 2.2 V at
–40°C
SID92
TRESP3
2.3
15
Datasheet
27
002-00123 Rev. *P
2023-01-23
PSoC™ 4 MCU: PSoC™ 4000S
Based on Arm® Cortex®-M0+ CPU
Electrical specifications
6.3.2
CSD and IDAC
Table 12
CSD and IDAC specifications
Spec ID
Parameter
Description
Min Typ
Max
Units
Details/conditions
Max allowed ripple
on power supply,
DC to 10 MHz
V
DD > 2 V (with ripple),
SYS.PER#3
VDD_RIPPLE
–
–
±50
mV 25°C TA,
Sensitivity = 0.1 pF
VDD > 1.75 V (with
ripple), 25°C TA,
Max allowed ripple
SYS.PER#16 VDD_RIPPLE_1.8 on power supply,
DC to 10 MHz
–
–
±25
mV Parasitic Capacitance
(CP) < 20 pF,
Sensitivity ≥ 0.4 pF
Maximum block current
for both IDACs in
dynamic (switching)
µA mode including
comparators, buffer,
and reference
Maximum block
SID.CSD.BLK ICSD
current
–
–
4000
generator.
Voltage reference
VDDA – 0.6 or 4.4 V,
SID.CSD#15 VREF
for CSD and
comparator
0.6 1.2 VDDA – 0.6
V
whichever is lower
External Voltage
reference for CSD
and comparator
V
DDA – 0.6 or 4.4 V,
SID.CSD#15A VREF_EXT
0.6
–
VDDA – 0.6
V
whichever is lower
IDAC1 (7-bits) block
current
IDAC2 (7-bits) block
current
Voltage range of
operation
SID.CSD#16 IDAC1IDD
SID.CSD#17 IDAC2IDD
–
–
–
–
–
1750
1750
5.5
µA
µA
V
–
–
1.8 V ± 5% or 1.8 V to
5.5 V
SID308
VCSD
1.71
Voltage
VDDA – 0.6 or 4.4 V,
whichever is lower
SID308A
VCOMPIDAC
compliance range
of IDAC
0.6
–
VDDA – 0.6
V
SID309
SID310
SID311
SID312
IDAC1DNL
IDAC1INL
IDAC2DNL
IDAC2INL
DNL
–1
–2
–1
–2
–
–
–
–
1
2
1
2
LSB
LSB
LSB
LSB
–
INL is ±5.5 LSB for
VDDA < 2 V
–
INL
DNL
INL
INL is ±5.5 LSB for
V
DDA < 2 V
Ratio of counts of
finger to noise.
Guaranteed by
characterization
Capacitance range of
5 pF to 35 pF, 0.1-pF
sensitivity.Allusecases.
VDDA > 2 V.
SID313
SNR
5
–
–
Ratio
Output current of
SID314
IDAC1CRT1
IDAC1CRT2
IDAC1 (7 bits) in low 4.2
range
–
–
5.4
41
µA LSB = 37.5-nA typ.
µA LSB = 300-nA typ.
Output current of
SID314A
IDAC1 (7 bits) in
medium range
34
Datasheet
28
002-00123 Rev. *P
2023-01-23
PSoC™ 4 MCU: PSoC™ 4000S
Based on Arm® Cortex®-M0+ CPU
Electrical specifications
Table 12
Spec ID
CSD and IDAC specifications (continued)
Parameter
Description
Min Typ
Max
Units
Details/conditions
Output current of
IDAC1 (7 bits) in
high range
Output current of
IDAC1 (7 bits) in low
range, 2X mode
Output current of
IDAC1 (7 bits) in
medium range, 2X
mode
Output current of
IDAC1 (7 bits) in
high range, 2X
mode
SID314B
SID314C
IDAC1CRT3
275
8
–
–
330
µA LSB = 2.4-µA typ.
IDAC1CRT12
IDAC1CRT22
10.5
82
µA LSB = 75-nA typ.
µA LSB = 600-nA typ.
SID314D
SID314E
69
–
–
IDAC1CRT32
540
660
µA LSB = 4.8-µA typ.
Output current of
SID315
IDAC2CRT1
IDAC2CRT2
IDAC2CRT3
IDAC2CRT12
IDAC2 (7 bits) in low 4.2
range
–
–
–
–
5.4
41
µA LSB = 37.5-nA typ.
µA LSB = 300-nA typ.
µA LSB = 2.4-µA typ.
µA LSB = 75-nA typ.
Output current of
SID315A
SID315B
SID315C
IDAC2 (7 bits) in
medium range
34
275
8
Output current of
IDAC2 (7 bits) in
high range
Output current of
IDAC2 (7 bits) in low
range, 2X mode
330
10.5
Output current of
IDAC2 (7 bits) in
medium range, 2X
mode
Output current of
IDAC2 (7 bits) in
high range, 2X
mode
SID315D
SID315E
IDAC2CRT22
IDAC2CRT32
69
–
–
82
µA LSB = 600-nA typ.
µA LSB = 4.8-µA typ.
540
660
Output current of
IDAC in 8-bit mode
in low range
Output current of
IDAC in 8-bit mode
in medium range
SID315F
SID315G
SID315H
IDAC3CRT13
IDAC3CRT23
IDAC3CRT33
8
–
–
–
10.5
82
µA LSB = 37.5-nA typ.
µA LSB = 300-nA typ.
µA LSB = 2.4-µA typ.
69
Output current of
IDAC in 8-bit mode 540
in high range
660
Polarity set by Source or
LSB Sink. Offset is 2 LSBs for
37.5 nA/LSB mode
SID320
SID321
SID322
IDACOFFSET
IDACGAIN
All zeroes input
–
–
–
–
–
–
1
Full-scale error less
offset
±10
9.2
%
–
Mismatch between
IDACMISMATCH1 IDAC1 and IDAC2 in
Low mode
LSB LSB = 37.5-nA typ.
Datasheet
29
002-00123 Rev. *P
2023-01-23
PSoC™ 4 MCU: PSoC™ 4000S
Based on Arm® Cortex®-M0+ CPU
Electrical specifications
Table 12
Spec ID
CSD and IDAC specifications (continued)
Parameter
Description
Min Typ
Max
Units
Details/conditions
Mismatch between
SID322A
SID322B
SID323
IDACMISMATCH2 IDAC1 and IDAC2 in
Medium mode
–
–
–
–
–
–
5.6
LSB LSB = 300-nA typ.
LSB LSB = 2.4-µA typ.
Mismatch between
IDACMISMATCH3 IDAC1 and IDAC2 in
High mode
6.8
10
Settling time to
Full-scale transition. No
IDACSET8
0.5 LSB for
8-bit IDAC
µs
external load.
Settling time to
0.5 LSB for
Full-scale transition. No
external load.
SID324
SID325
IDACSET7
CMOD
–
–
–
10
–
µs
nF
7-bit IDAC
External modulator
capacitor.
5-V rating, X7R or NP0
cap.
2.2
Datasheet
30
002-00123 Rev. *P
2023-01-23
PSoC™ 4 MCU: PSoC™ 4000S
Based on Arm® Cortex®-M0+ CPU
Electrical specifications
6.3.3
10-bit CAPSENSE™ ADC
Table 13
10-bit CAPSENSE™ ADC specifications
Description
Spec ID Parameter
Min
Typ
Max Units Details/conditions
Auto-zeroing is
bits required every
millisecond
SIDA94
A_RES
Resolution
–
–
10
Number of channels - single
ended
Monotonicity
Defined by AMUX
Bus.
–
In VREF (2.4 V) mode
with VDDA bypass
capacitance of
10 µF
In VREF (2.4 V) mode
with VDDA bypass
capacitance of
10 µF
SIDA95
SIDA97
A_CHNLS_S
A-MONO
–
–
–
–
16
–
Yes
%
SIDA98
SIDA99
A_GAINERR Gain error
–
–
–
–
±2
3
A_OFFSET
Input offset voltage
mV
SIDA100
SIDA101
A_ISAR
A_VINS
Current consumption
Input voltage range - single
ended
–
–
–
0.25
mA
V
–
VSSA
VDDA
–
SIDA103
SIDA104
A_INRES
A_INCAP
Input resistance
Input capacitance
–
–
2.2
20
–
–
KΩ
pF
–
–
In VREF (2.4 V) mode
with VDDA bypass
capacitance of
10 µF
SIDA106
SIDA107
A_PSRR
A_TACQ
Power supply rejection ratio
Sample acquisition time
–
–
60
1
–
–
dB
µs
–
Does not include
acquisition time.
Conversion time for 8-bit
resolution at conversion
rate = Fhclk/(2^(N+2)). Clock
frequency = 48 MHz.
SIDA108
A_CONV8
–
–
21.3
µs Equivalent to
44.8 ksps including
acquisition time.
Does not include
acquisition time.
µs Equivalent to
11.6 ksps including
acquisition time.
Conversion time for 10-bit
resolution at conversion
rate = Fhclk/(2^(N+2)). Clock
frequency = 48 MHz.
SIDA108A A_CONV10
–
–
–
85.3
–
With 10-Hz input
Signal-to-noise and
Distortion ratio (SINAD)
sine wave, external
SIDA109
A_SND
61
dB
2.4-V reference,
VREF (2.4 V) mode
Input bandwidth without
aliasing
Integral Non Linearity.
1 ksps
Differential Non Linearity.
1 ksps
SIDA110
SIDA111
SIDA112
A_BW
A_INL
A_DNL
–
–
–
–
–
–
22.4
2
kHz 8-bit resolution
VREF = 2.4 V or
greater
LSB
1
LSB –
Datasheet
31
002-00123 Rev. *P
2023-01-23
PSoC™ 4 MCU: PSoC™ 4000S
Based on Arm® Cortex®-M0+ CPU
Electrical specifications
6.4
Digital peripherals
6.4.1
Timer counter pulse-width modulator (TCPWM)
Table 14
TCPWM specifications
Spec ID
Parameter
Description
Min
Typ
Max Units Details/conditions
Block current
SID.TCPWM.1 ITCPWM1
SID.TCPWM.2 ITCPWM2
SID.TCPWM.2A ITCPWM3
–
–
45
155
650
Fc
All modes (TCPWM)
All modes (TCPWM)
All modes (TCPWM)
consumption at 3 MHz
Block current
consumption at 12 MHz
Block current
consumption at 48 MHz
–
–
–
–
–
–
µA
Fc max = CLK_SYS
Maximum = 48 MHz
TCPWMFREQ
TPWMENEXT
SID.TCPWM.3
SID.TCPWM.4
Operating frequency
MHz
Input trigger pulse
width
For all trigger
2/Fc
–
–
events[6]
Minimum possible
width of Overflow,
Underflow, and CC
(Counter equals
Compare value)
outputs
Output trigger pulse
widths
TPWMEXT
SID.TCPWM.5
2/Fc
–
–
Minimum time
between
ns
TCRES
SID.TCPWM.5A
SID.TCPWM.5B
Resolution of counter
PWM resolution
1/Fc
1/Fc
–
–
–
–
successive counts
Minimum pulse
width of PWM
Output
PWMRES
Minimum pulse
width between
Quadrature phase
inputs
Quadrature inputs
resolution
QRES
SID.TCPWM.5C
1/Fc
–
–
Note
6. Trigger events can be Stop, Start, Reload, Count, Capture, or Kill depending on which mode of operation is selected.
Datasheet
32
002-00123 Rev. *P
2023-01-23
PSoC™ 4 MCU: PSoC™ 4000S
Based on Arm® Cortex®-M0+ CPU
Electrical specifications
6.4.2
I2C
Table 15
Fixed I2C DC specifications[7]
Spec ID Parameter
Description
Min
Typ
Max Units Details/conditions
Block current consumption
at 100 kHz
Block current consumption
at 400 kHz
Block current consumption
at 1 Mbps
I2C enabled in Deep Sleep
mode
SID149 II2C1
–
–
50
–
–
–
–
SID150 II2C2
SID151 II2C3
SID152 II2C4
–
–
–
–
–
–
135
310
1.4
µA
Table 16
Fixed I2C AC specifications[7]
Spec ID Parameter
SID153 FI2C1
Description
Min
–
Typ
–
Max Units Details/conditions
Msps –
Bit rate
1
Note
7. Guaranteed by characterization.
Datasheet
33
002-00123 Rev. *P
2023-01-23
PSoC™ 4 MCU: PSoC™ 4000S
Based on Arm® Cortex®-M0+ CPU
Electrical specifications
6.4.3
SPI
Table 17
SPI DC specifications[7]
Spec ID Parameter
Description
Min
Typ
Max Units Details/conditions
Block current consumption
at 1 Mbps
Block current consumption
at 4 Mbps
Block current consumption
at 8 Mbps
SID163 ISPI1
–
–
360
560
600
–
–
–
SID164 ISPI2
SID165 ISPI3
–
–
–
–
µA
Table 18
Spec ID
SPI AC specifications[7]
Parameter
Description
Min Typ
Max
Units Details/conditions
SPI operating frequency
(Master; 6X Oversampling)
SID166
FSPI
–
–
8
MHz
–
Fixed SPI Master Mode AC specifications
MOSI valid after SClock
driving edge
MISO valid before SClock
capturing edge
Previous MOSI data hold
time
SID167
SID168
SID169
TDMO
TDSI
–
20
0
–
–
–
15
–
–
Full clock, late
MISO sampling
Referred to Slave
capturing edge
ns
THMO
–
Fixed SPI Slave Mode AC specifications
MOSI valid before Sclock
capturing edge
MISO valid after Sclock
driving edge
MISO valid after Sclock
driving edge in External
Clock mode
Previous MISO data hold
time
SID170
SID171
TDMI
TDSO
40
–
–
–
–
–
42 + (3 × Tcpu)
48
TCPU = 1/FCPU
ns
ns
SID171A
TDSO_EXT
–
–
–
SID172
THSO
0
–
–
–
–
–
–
SSEL valid to first SCK valid
edge
SID172A
TSSELSSCK
100
Datasheet
34
002-00123 Rev. *P
2023-01-23
PSoC™ 4 MCU: PSoC™ 4000S
Based on Arm® Cortex®-M0+ CPU
Electrical specifications
6.4.4
UART
Table 19
UART DC specifications[8]
Spec ID Parameter
Description
Min
Typ
Max Units Details/conditions
Block current consumption
at 100 Kbps
Block current consumption
at 1000 Kbps
SID160 IUART1
–
–
55
µA
µA
–
–
SID161 IUART2
–
–
312
Table 20
UART AC specifications[8]
Spec ID Parameter
SID162 FUART
Description
Min
–
Typ
–
Max Units Details/conditions
Mbps –
Bit rate
1
6.4.5
LCD direct drive
Table 21
LCD direct drive DC specifications[8]
Spec ID Parameter
Description
Min
Typ
Max Units Details/conditions
SID154 ILCDLOW
Operating current in low
power mode
–
5
–
µA 16 × 4 small
segment disp.
at 50 Hz
SID155 CLCDCAP
LCD capacitance per
segment/common driver
–
500
5000
pF
–
SID156 LCDOFFSET
SID157 ILCDOP1
Long-term segment offset
LCD system operating
current Vbias = 5 V
–
–
20
2
–
–
mV
–
mA 32 × 4 segments.
50 Hz. 25°C
SID158 ILCDOP2
LCD system operating
current Vbias = 3.3 V
–
2
–
32 × 4 segments.
50 Hz. 25°C
Table 22
LCD direct drive AC specifications[8]
Spec ID Parameter
SID159 FLCD
Description
LCD frame rate
Min
10
Typ
50
Max Units Details/conditions
150 Hz
–
Note
8. Guaranteed by characterization.
Datasheet
35
002-00123 Rev. *P
2023-01-23
PSoC™ 4 MCU: PSoC™ 4000S
Based on Arm® Cortex®-M0+ CPU
Electrical specifications
6.5
Memory
Flash
6.5.1
Table 23
Flash DC specifications
Spec ID Parameter
SID173 VPE
Description
Erase and program voltage
Min
1.71
Typ
–
Max Units Details/conditions
5.5
V
–
Table 24
Spec ID
Flash AC specifications
Parameter
Description
Min
Typ
Max
Units Details/conditions
Row (block) write
time (erase and
program)
Row erase time
Row program time
after erase
Row (block) =
128 bytes
[9]
[9]
SID174
TROWWRITE
TROWERASE
–
–
20
SID175
SID176
–
–
–
–
16
4
–
ms
[9]
TROWPROGRAM
–
–
Bulk erase time
(32 KB)
[9]
SID178
TBULKERASE
–
–
35
Total device
[9]
SID180[10]
SID181[10]
TDEVPROG
–
–
–
7
–
Seconds –
program time
FEND
FRET
Flash endurance
100 K
Cycles
–
–
Flash retention.
TA 55°C,
100 K P/E cycles.
Flash retention.
TA 85°C,
10 K P/E cycles.
SID182[10]
20
10
–
–
–
–
SID182A[10]
–
–
Years
Flash retention.
TA ≤ 105°C,
10 K P/E cycles,
≤ three years
at TA ≥ 85 °C.
Guaranteed by
Characterization
SID182B[10] FRETQ
10
–
20
Number of Wait
states at 48 MHz
Number of Wait
states at 24 MHz
CPU execution
from Flash
CPU execution
from Flash
SID256
SID257
TWS48
TWS24
2
1
–
–
–
–
Notes
9. It can take as much as 20 milliseconds to write to flash. During this time the device should not be Reset, or Flash operations may be
interrupted and cannot be relied on to have completed. Reset sources include the XRES pin, software resets, CPU lockup states and
privilege violations, improper power supply levels, and watchdogs. Make certain that these are not inadvertently activated.
10.Guaranteed by characterization.
Datasheet
36
002-00123 Rev. *P
2023-01-23
PSoC™ 4 MCU: PSoC™ 4000S
Based on Arm® Cortex®-M0+ CPU
Electrical specifications
6.6
System resources
6.6.1
Power-on reset (POR)
Table 25
Spec ID
Power-on reset (PRES)
Parameter
Description
Min
Typ
Max Units Details/conditions
At power-up and
SID.CLK#6 SR_POWER_UP Power supply slew rate
1
–
67
V/ms
V
power-down
SID185[10] VRISEIPOR
SID186[10] VFALLIPOR
Rising trip voltage
Falling trip voltage
0.80
0.70
–
–
1.5
1.4
–
–
Table 26
Spec ID
Brown-out detect (BOD) for VCCD
Parameter
Description
Min
Typ
Max Units Details/conditions
BOD trip voltage in active
and sleep modes
BOD trip voltage in Deep
Sleep
SID190[10] VFALLPPOR
1.48
–
1.62
1.5
–
–
V
SID192[10] VFALLDPSLP
1.11
–
6.6.2
SWD interface
Table 27
SWD interface specifications
Spec ID
Parameter
Description
Min
Typ Max Units Details/conditions
SWDCLK ≤ 1/3 CPU
SID213
F_SWDCLK1
3.3 V VDD 5.5 V
–
–
–
–
14
7
clock frequency
MHz
SWDCLK ≤ 1/3 CPU
clock frequency
SID214
F_SWDCLK2
1.71 V VDD 3.3 V
SID215[13]
SID216[13]
SID217[13]
T_SWDI_SETUP T = 1/f SWDCLK
T_SWDI_HOLD T = 1/f SWDCLK
0.25 × T
0.25 × T
–
–
–
–
–
–
–
–
–
–
0.5 × T
–
ns
T_SWDO_VALID T = 1/f SWDCLK
–
1
SID217A[13] T_SWDO_HOLD T = 1/f SWDCLK
Datasheet
37
002-00123 Rev. *P
2023-01-23
PSoC™ 4 MCU: PSoC™ 4000S
Based on Arm® Cortex®-M0+ CPU
Electrical specifications
6.6.3
Internal main oscillator (IMO)
Table 28
IMO DC specifications
(Guaranteed by design)
Spec ID Parameter
Description
Min
Typ
Max Units Details/conditions
IMO operating current
at 48 MHz
SID218 IIMO1
SID219 IIMO2
–
–
250
180
µA
µA
–
–
IMO operating current
at 24 MHz
–
–
Table 29
Spec ID
IMO AC specifications
Parameter
Description
Min
Typ
Max Units Details/conditions
At –40°C to 85°C, for
industrial
temperature range
SID223[12]
–
–
±2.0
%
and original
extended industrial
range parts
At –40°C to 105°C,
for all extended
industrial
SID223A[11, 12]
SID223B[11, 12]
SID223C[11, 12]
SID223D[11, 12]
–
–
–
–
–
–
–
–
±2.5
±2.0
%
%
%
%
temperature range
parts
At –30°C to 105°C,
for enhanced IMO
extended industrial
temperature range
parts
At –20°C to 105°C,
for enhanced IMO
extended industrial
temperature range
parts
At 0°C to 85°C, for
enhanced IMO
extended industrial
temperature range
parts
Frequency variation at
24, 32, and 48 MHz
(trimmed)
FIMOTOL1
±1.5
±1.25
SID226
SID228
TSTARTIMO
TJITRMSIMO2 RMS jitter at 24 MHz
IMO startup time
–
–
–
145
7
–
µs
ps
–
–
Notes
11.The enhanced IMO extended temperature range parts replace the original extended industrial temperature range parts. For details
on how to identify enhanced IMO extended temperature range parts, please refer to KBA235887.
12.Evaluated by characterization. Does not take into account soldering or board-level effects.
Datasheet
38
002-00123 Rev. *P
2023-01-23
PSoC™ 4 MCU: PSoC™ 4000S
Based on Arm® Cortex®-M0+ CPU
Electrical specifications
6.6.4
Internal low-speed oscillator (ILO)
Table 30
ILO DC specifications
(Guaranteed by design)
Spec ID
SID231[13]
Parameter
IILO1
Description
ILO operating current
Min
–
Typ
0.3
Max Units Details/conditions
1.05 µA
–
Table 31
Spec ID
SID234[13]
SID236[13]
SID237
ILO AC specifications
Parameter
TSTARTILO1
TILODUTY
Description
ILO startup time
ILO duty cycle
Min
–
40
20
Typ
–
50
40
Max Units Details/conditions
2
ms
%
–
–
–
60
80
FILOTRIM1
ILO frequency range
kHz
6.6.5
Watch crystal oscillator (WCO)
Table 32
Watch crystal oscillator (WCO) specifications
Spec ID Parameter
Description
Min
Typ
Max Units Details/conditions
SID398 FWCO
Crystal frequency
–
32.768
–
kHz
–
With 20-ppm
crystal
SID399 FTOL
Frequency tolerance
–
50
250
ppm
SID400 ESR
SID401 PD
SID402 TSTART
SID403 CL
Equivalent series resistance
Drive level
Startup time
Crystal load capacitance
Crystal shunt capacitance
–
–
–
6
–
50
–
–
–
1.35
–
1
500
12.5
–
kΩ
µW
ms
pF
–
–
–
–
–
SID404 C0
pF
Operating current (high
power mode)
Operating current (low
power mode)
SID405 IWCO1
SID406 IWCO2
–
–
–
–
8
1
µA
µA
–
–
6.6.6
External clock
Table 33
Spec ID
External clock specifications
Parameter
Description
Min
Typ
Max Units Details/conditions
External clock input
frequency
Duty cycle; measured at
VDD/2
SID305[15] ExtClkFreq
0
–
48
55
MHz
%
–
–
SID306[15] ExtClkDuty
45
–
Notes
13.Guaranteed by characterization.
14.For industrial temperature range parts, the maximum temperature is 85°C.
Datasheet
39
002-00123 Rev. *P
2023-01-23
PSoC™ 4 MCU: PSoC™ 4000S
Based on Arm® Cortex®-M0+ CPU
Electrical specifications
6.6.7
Clock
Table 34
Spec ID
Clock specs
Parameter
Description
Min
Typ
Max
Units Details/conditions
System clock source
switching time
SID262[15] TCLKSWITCH
3
–
4
Periods –
6.6.8
Smart I/O Pass-through Time
Table 35
Spec ID
Smart I/O pass-through time (Delay in Bypass Mode)
Parameter
Description
Min
Typ
Max Units Details/conditions
1.6 ns
Max delay added by Smart
I/O in Bypass Mode
SID252 PRG_BYPASS
–
–
–
Note
15.Guaranteed by characterization.
Datasheet
40
002-00123 Rev. *P
2023-01-23
PSoC™ 4 MCU: PSoC™ 4000S
Based on Arm® Cortex®-M0+ CPU
Ordering information
7
Ordering information
The PSoC™ 4000S part numbers and features are listed in the following table.
Table 36
PSoC™ 4000S ordering information
Features
Package
Category
MPN
CY8C4024FNI-S402
CY8C4024LQI-S401
CY8C4024LQI-S402
CY8C4024AXI-S402
CY8C4024LQI-S403
CY8C4024AZI-S403
CY8C4024FNI-S412
CY8C4024LQI-S411
CY8C4024LQI-S412
CY8C4024AXI-S412
CY8C4024LQI-S413
CY8C4024AZI-S413
CY8C4024AZQ-S413
CY8C4025FNI-S402
CY8C4025LQI-S401
CY8C4025LQI-S402
CY8C4025AXI-S402
CY8C4025LQI-S403
CY8C4025AZI-S403
CY8C4025AZQ-S403
CY8C4025FNI-S412
CY8C4025LQI-S411
CY8C4025LQI-S412
CY8C4025AXI-S412
CY8C4025LQI-S413
CY8C4025AZI-S413
CY8C4025AZQ-S413
CY8C4045FNI-S412
CY8C4045LQI-S411
CY8C4045LQI-S412
CY8C4045AXI-S412
CY8C4045LQI-S413
CY8C4045AZI-S413
CY8C4045AZQ-S413
24 16
24 16
24 16
24 16
24 16
24 16
24 16
24 16
24 16
24 16
24 16
24 16
24 16
24 32
24 32
24 32
24 32
24 32
24 32
24 32
24 32
24 32
24 32
24 32
24 32
24 32
24 32
48 32
48 32
48 32
48 32
48 32
48 32
48 32
2
2
2
2
2
2
2
2
2
2
2
2
2
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
8
8
21
19
✔
–
–
✔
–
–
–
–
–
–
–
–
–
–
–
16 27
16 27
16 34
16 36
–
✔
–
–
–
–
–
✔
–
–
–
–
–
✔
–
–
–
–
–
✔
–
–40°C to 85°C
4024
8
8
21
19
✔
–
–
–
–
–
✔
–
–
–
–
–
16 27
16 27
16 34
16 36
16 36
–
✔
–
–
–
–
–
–
✔
–
–
–
–
–
–
✔
–
–
–
–
–
–
✔
✔
–
–
–
–
–
–
–40°C to 105°C
–40°C to 85°C
–40°C to 105°C
8
8
21
19
✔
–
–
–
–
–
✔
–
–
–
–
–
16 27
16 27
16 34
16 36
16 36
–
✔
–
–
–
–
–
–
✔
–
–
–
–
–
–
✔
–
–
–
–
–
–
✔
✔
–
–
–
–
–
–
4025
8
8
21
19
✔
–
–
–
–
–
✔
–
–
–
–
–
16 27
16 27
16 34
16 36
16 36
–
✔
–
–
–
–
–40°C to 85°C
–
–
✔
–
–
–
–
–
–
✔
–
–
–
–
–
–
✔
✔
–
–
–
–
–
–
–40°C to 105°C
–40°C to 85°C
–40°C to 105°C
8
8
21
19
✔
–
–
–
–
–
✔
–
–
–
–
–
16 27
16 27
16 34
16 36
16 36
–
✔
–
–
–
–
–
–
✔
–
–
–
4045
–
–
–
✔
–
–
–
–
–
–
✔
✔
–
–
–
–
–
Datasheet
41
002-00123 Rev. *P
2023-01-23
PSoC™ 4 MCU: PSoC™ 4000S
Based on Arm® Cortex®-M0+ CPU
Ordering information
The nomenclature used in the preceding table is based on the following part numbering convention:
Field
CY8C
4
Description
Values
Meaning
Prefix
Architecture
Family
4
0
2
PSoC™ 4
4000 Family
24 MHz
48 MHz
16 KB
A
B
C
CPU Speed
4
4
5
6
32 KB
64 KB
Flash Capacity
7
128 KB
AX
AZ
LQ
PV
FN
I
Q
S
M
L
TQFP (0.8-mm pitch)
TQFP (0.5-mm pitch)
QFN
SSOP
CSP
DE
F
Package Code
Industrial
Temperature Range
Extended Industrial
PSoC™ 4 S-Series
PSoC™ 4 M-Series
PSoC™ 4 L-Series
PSoC™ 4 BLE-Series
S
Series Designator
Attributes Code
BL
XYZ
000-999 Code of feature set in the specific family
The following is an example of a part number:
Example
CY8C 4 A B C DE F – S XYZ
Cypress Prefix
Architecture
Family within Architecture
CPU Speed
4: PSoC 4
1
2
0: 4000 Family
4: 48 MHz
5: 32 KB
Flash Capacity
Package Code
A
AZ: TQFP
I: Industrial
Temperature Range
Silicon Family
Attributes Code
Datasheet
42
002-00123 Rev. *P
2023-01-23
PSoC™ 4 MCU: PSoC™ 4000S
Based on Arm® Cortex®-M0+ CPU
Packaging
8
Packaging
The PSoC™ 4000S is offered in 48-pin TQFP, 40-pin QFN, 32-pin QFN, 24-pin QFN, 32-pin TQFP, and 25-ball WLCSP
packages.
Package dimensions and Infineon drawing numbers are in the following table.
Table 37
Spec ID
BID20
BID27
BID34A
BID34
Package list
Package
Description
Package drawing
51-85135
48-pin TQFP
40-pin QFN
32-pin QFN
24-pin QFN
32-pin TQFP
25-ball WLCSP
7 × 7 × 1.4 mm height with 0.5-mm pitch
6 × 6 × 0.6 mm height with 0.5-mm pitch
5 × 5 × 0.6 mm height with 0.5-mm pitch
4 × 4 × 0.6 mm height with 0.5-mm pitch
7 × 7 × 1.4 mm height with 0.8-mm pitch
2.02 × 1.93 × 0.48 mm height with 0.35-mm pitch
001-80659
001-42168
001-13937
51-85088
BID34G
BID34F
002-09957
Table 38
Parameter
TA
TJ
TJA
TJC
TJA
TJC
Package thermal characteristics
Description
Operating ambient temperature
Operating junction temperature
Package θJA
Package θJC
Package θJA
Package θJC
Package
Min
–40
–40
–
–
–
Typ
25
–
73.5
33.5
17.8
2.8
Max
105
125
–
–
–
Units
°C
°C
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
–
–
48-pin TQFP
48-pin TQFP
40-pin QFN
40-pin QFN
32-pin QFN
32-pin QFN
–
–
TJA
TJC
Package θJA
Package θJC
–
–
20.8
5.9
–
–
TJA
TJC
TJA
TJC
TJA
TJC
Package θJA
Package θJC
Package θJA
Package θJC
Package θJA
Package θJC
24-pin QFN
–
–
–
–
–
–
21.7
5.6
–
–
–
–
–
–
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
24-pin QFN
32-pin TQFP
32-pin TQFP
25-ball WLCSP
25-ball WLCSP
29.4
3.5
40
0.5
Table 39
Solder reflow peak temperature
Package
All
Maximum peak temperature
260 °C
Maximum time at peak temperature
30 seconds
Datasheet
43
002-00123 Rev. *P
2023-01-23
PSoC™ 4 MCU: PSoC™ 4000S
Based on Arm® Cortex®-M0+ CPU
Packaging
Table 40
Package moisture sensitivity level (MSL), IPC/JEDEC J-STD-020
Package
All except WLCSP
25-ball WLCSP
MSL
MSL 3
MSL 1
8.1
Package diagrams
51-85135 *C
Figure 6
48-pin TQFP (7 × 7 × 1.4 mm) package outline, 51-85135
Datasheet
44
002-00123 Rev. *P
2023-01-23
PSoC™ 4 MCU: PSoC™ 4000S
Based on Arm® Cortex®-M0+ CPU
Packaging
001-80659 *A
40-pin QFN ((6 × 6 × 0.6 mm) 4.6 × 4.6 E-Pad (Sawn)) package outline, 001-80659
Figure 7
Datasheet
45
002-00123 Rev. *P
2023-01-23
PSoC™ 4 MCU: PSoC™ 4000S
Based on Arm® Cortex®-M0+ CPU
Packaging
SEE NOTE 1
TOP VIEW
BOTTOM VIEW
SIDE VIEW
NOTES:
1.
DIMENSIONS
MIN. NOM. MAX.
HATCH AREA IS SOLDERABLE EXPOSED PAD
SYMBOL
2. BASED ON REF JEDEC # MO-248
3. PACKAGE WEIGHT: 0.0388g
A
A1
A2
D
0.50
-
0.55
0.60
4. DIMENSIONS ARE IN MILLIMETERS
0.020 0.045
0.15 BSC
4.90
3.40
4.90
3.40
0.30
0.18
5.00
3.50
5.10
3.60
5.10
3.60
0.50
0.30
D2
E
5.00
E2
L
3.50
0.40
0.25
b
e
0.50 TYP
001-42168 *F
32-pin QFN ((5.0 × 5.0 × 0.55 mm) 3.5 × 3.5 mm E-Pad (Sawn)) package outline, 001-42168
Figure 8
Datasheet
46
002-00123 Rev. *P
2023-01-23
PSoC™ 4 MCU: PSoC™ 4000S
Based on Arm® Cortex®-M0+ CPU
Packaging
001-13937 *H
24-pin QFN ((4 × 4 × 0.60 mm) 2.65 × 2.65 E-Pad (Sawn)) package outline, 001-13937
Figure 9
The center pad on the QFN package should be connected to ground (VSS) for best mechanical, thermal, and
electrical performance. If not connected to ground, it should be electrically floating and not connected to any
other signal.
Datasheet
47
002-00123 Rev. *P
2023-01-23
PSoC™ 4 MCU: PSoC™ 4000S
Based on Arm® Cortex®-M0+ CPU
Packaging
51-85088 *E
Figure 10
32-pin TQFP (7 × 7 × 1.4 mm) package outline, 51-85088
002-09957 **
Figure 11
25-ball WLCSP (2.02 × 1.93 × 0.48 mm) package outline, 002-09957
Datasheet
48
002-00123 Rev. *P
2023-01-23
PSoC™ 4 MCU: PSoC™ 4000S
Based on Arm® Cortex®-M0+ CPU
Acronyms
9
Acronyms
Table 41
Acronyms used in this document
Acronym
Description
abus
ADC
AG
analog local bus
analog-to-digital converter
analog global
AHB
AMBA (advanced microcontroller bus architecture) high-performance bus, an ARM data
transfer bus
ALU
arithmetic logic unit
AMUXBUS
API
APSR
ARM®
ATM
BW
analog multiplexer bus
application programming interface
application program status register
advanced RISC machine, a CPU architecture
automatic thump mode
bandwidth
CAN
CMRR
CPU
CRC
DAC
DFB
Controller Area Network, a communications protocol
common-mode rejection ratio
central processing unit
cyclic redundancy check, an error-checking protocol
digital-to-analog converter, see also IDAC, VDAC
digital filter block
DIO
digital input/output, GPIO with only digital capabilities, no analog. See GPIO.
Dhrystone million instructions per second
direct memory access, see also TD
differential nonlinearity, see also INL
do not use
DMIPS
DMA
DNL
DNU
DR
port write data registers
DSI
digital system interconnect
DWT
ECC
data watchpoint and trace
error correcting code
ECO
external crystal oscillator
EEPROM
EMI
EMIF
EOC
EOF
electrically erasable programmable read-only memory
electromagnetic interference
external memory interface
end of conversion
end of frame
EPSR
ESD
execution program status register
electrostatic discharge
ETM
FIR
embedded trace macrocell
finite impulse response, see also IIR
Datasheet
49
002-00123 Rev. *P
2023-01-23
PSoC™ 4 MCU: PSoC™ 4000S
Based on Arm® Cortex®-M0+ CPU
Acronyms
Table 41
Acronyms used in this document (continued)
Description
Acronym
FPB
FS
flash patch and breakpoint
full-speed
GPIO
HVI
IC
general-purpose input/output, applies to a PSoC pin
high-voltage interrupt, see also LVI, LVD
integrated circuit
IDAC
IDE
I2C, or IIC
IIR
ILO
IMO
INL
current DAC, see also DAC, VDAC
integrated development environment
Inter-Integrated Circuit, a communications protocol
infinite impulse response, see also FIR
internal low-speed oscillator, see also IMO
internal main oscillator, see also ILO
integral nonlinearity, see also DNL
input/output, see also GPIO, DIO, SIO, USBIO
initial power-on reset
I/O
IPOR
IPSR
IRQ
interrupt program status register
interrupt request
ITM
LCD
LIN
instrumentation trace macrocell
liquid crystal display
Local Interconnect Network, a communications protocol.
link register
LR
LUT
LVD
LVI
LVTTL
MAC
MCU
MISO
NC
lookup table
low-voltage detect, see also LVI
low-voltage interrupt, see also HVI
low-voltage transistor-transistor logic
multiply-accumulate
microcontroller unit
master-in slave-out
no connect
NMI
NRZ
NVIC
NVL
opamp
PAL
nonmaskable interrupt
non-return-to-zero
nested vectored interrupt controller
nonvolatile latch, see also WOL
operational amplifier
programmable array logic, see also PLD
program counter
PC
PCB
PGA
PHUB
PHY
PICU
printed circuit board
programmable gain amplifier
peripheral hub
physical layer
port interrupt control unit
Datasheet
50
002-00123 Rev. *P
2023-01-23
PSoC™ 4 MCU: PSoC™ 4000S
Based on Arm® Cortex®-M0+ CPU
Acronyms
Table 41
Acronyms used in this document (continued)
Description
Acronym
PLA
programmable logic array
PLD
PLL
programmable logic device, see also PAL
phase-locked loop
PMDD
POR
PRES
PRS
PS
package material declaration datasheet
power-on reset
precise power-on reset
pseudo random sequence
port read data register
PSoC™
PSRR
PWM
RAM
RISC
RMS
RTC
RTL
Programmable System-on-Chip™
power supply rejection ratio
pulse-width modulator
random-access memory
reduced-instruction-set computing
root-mean-square
real-time clock
register transfer language
remote transmission request
receive
RTR
RX
SAR
SC/CT
SCL
SDA
S/H
successive approximation register
switched capacitor/continuous time
I2C serial clock
I2C serial data
sample and hold
SINAD
SIO
SOC
SOF
SPI
signal to noise and distortion ratio
special input/output, GPIO with advanced features. See GPIO.
start of conversion
start of frame
Serial Peripheral Interface, a communications protocol
slew rate
SR
SRAM
SRES
SWD
SWV
TD
THD
TIA
TRM
TTL
static random access memory
software reset
serial wire debug, a test protocol
single-wire viewer
transaction descriptor, see also DMA
total harmonic distortion
transimpedance amplifier
technical reference manual
transistor-transistor logic
transmit
TX
UART
Universal Asynchronous Transmitter Receiver, a communications protocol
Datasheet
51
002-00123 Rev. *P
2023-01-23
PSoC™ 4 MCU: PSoC™ 4000S
Based on Arm® Cortex®-M0+ CPU
Acronyms
Table 41
Acronyms used in this document (continued)
Description
Acronym
UDB
USB
universal digital block
Universal Serial Bus
USBIO
VDAC
WDT
USB input/output, PSoC pins used to connect to a USB port
voltage DAC, see also DAC, IDAC
watchdog timer
WOL
WRES
XRES
XTAL
write once latch, see also NVL
watchdog timer reset
external reset I/O pin
crystal
Datasheet
52
002-00123 Rev. *P
2023-01-23
PSoC™ 4 MCU: PSoC™ 4000S
Based on Arm® Cortex®-M0+ CPU
Document conventions
10
Document conventions
10.1
Units of measure
Table 42
Units of measure
Symbol
Unit of measure
°C
dB
degrees Celsius
decibel
fF
Hz
femto farad
hertz
KB
1024 bytes
kbps
Khr
kHz
k
ksps
LSB
Mbps
MHz
M
Msps
µA
kilobits per second
kilohour
kilohertz
kilo ohm
kilosamples per second
least significant bit
megabits per second
megahertz
mega-ohm
megasamples per second
microampere
microfarad
µF
µH
µs
µV
microhenry
microsecond
microvolt
µW
mA
ms
mV
nA
microwatt
milliampere
millisecond
millivolt
nanoampere
nanosecond
nanovolt
ns
nV
ohm
pF
picofarad
ppm
ps
s
parts per million
picosecond
second
sps
sqrtHz
V
samples per second
square root of hertz
volt
Datasheet
53
002-00123 Rev. *P
2023-01-23
PSoC™ 4 MCU: PSoC™ 4000S
Based on Arm® Cortex®-M0+ CPU
Revision history
Revision history
Document
Date of release Description of changes
version
**
2015-08-28
New datasheet.
Removed 20-ball WLCSP package related information in all instances across
the document.
Added 25-ball WLCSP package related information in all instances across
the document.
Updated Pinouts:
Updated Table 1.
Updated Electrical specifications:
Updated Analog peripherals:
Updated Comparator:
*A
2015-10-30
Updated Table 10 (Updated details in “Details/Conditions” column corre-
sponding to VICM3, ICMP3 parameters (Added VDDD ≥ 2.2V at –40 °C)).
Updated Table 11 (Updated details in “Details/Conditions” column
corresponding to TRESP3 parameter (Added VDDD ≥ 2.2V at –40 °C)).
Updated CSD and IDAC:
Updated Table 13.
Updated Ordering information:
Updated part numbers.
*B
*C
*D
2015-12-08
2016-01-27
2016-02-16
Changed status from Advance to Preliminary.
Updated Packaging:
Updated Table 38 (Replaced TBD with values for Theta JA and Theta JC
parameters).
Updated Package diagrams:
Replaced TBD with spec 002-09957 **.
Added Errata.
Updated to new template.
Updated Pinouts:
Updated Table 1.
Updated Electrical specifications:
Updated Device level specifications:
Updated XRES:
Updated Table 8 (Updated all values corresponding to RPULLUP parameter).
Updated Table 9 (Updated all values corresponding to TRESETWAKE
parameter).
*E
2016-03-15
Updated Analog peripherals:
Updated CSD and IDAC:
Updated Table 12.
Updated 10-bit CAPSENSE™ ADC:
Updated Table 13.
Updated Memory:
Updated Flash:
Updated Table 24 (Updated all values corresponding to TROWERASE
,
TROWPROGRAM parameters).
Datasheet
54
002-00123 Rev. *P
2023-01-23
PSoC™ 4 MCU: PSoC™ 4000S
Based on Arm® Cortex®-M0+ CPU
Revision history
Document
Date of release Description of changes
version
Updated Pinouts:
Updated Alternate pin functions:
Updated Table 2.
Updated Electrical specifications:
Updated Analog peripherals:
Updated CSD and IDAC:
Updated Table 12 (Updated all values corresponding to IDAC1INL,
IDAC2INL, SNR, IDAC1CRT1, IDAC1CRT12, IDAC1CRT22, IDAC1CRT32,
IDAC2CRT1, IDAC2CRT12, IDAC2CRT22, IDAC2CRT32, IDACMISMATCH2,
IDACMISMATCH3 parameters).
*F
2016-05-12
Updated 10-bit CAPSENSE™ ADC:
Updated Table 13 (Updated all values corresponding to A_SND parameter).
Removed Errata.
Updated to new template.
Changed status from Preliminary to Final.
Updated Functional definition:
Updated Special function peripherals:
Updated LCD segment drive:
Updated description.
Updated Electrical specifications:
Updated Device level specifications:
Updated Table 4 (Updated details corresponding to IDD5, IDD8, IDD11, IDD17
IDD20, IDD23, IDD23A, IDD26, IDD29, IDD32, IDD_XR parameters).
Updated GPIO:
,
*G
2016-07-27
Updated Table 6 (Updated details in “Details/Conditions” column corre-
sponding to VOH parameter and spec ID SID60).
Updated Packaging:
Updated Table 37 (Updated details in “Description” column corresponding
to 25-Ball WLCSP package (Updated package dimensions)).
Updated Table 40 (Added 25-ball WLCSP package and its corresponding
details).
Completing Sunset Review.
Added 40-pin QFN package related information in all instances across the
document.
Updated Electrical specifications:
Updated Device level specifications:
*H
2016-09-14
Updated Table 4 (Updated details corresponding to IDD5, IDD8, IDD11, IDD17
IDD20, IDD23, IDD23A, IDD26, IDD29, IDD32, IDD_XR parameters).
Updated Packaging:
,
Updated Package diagrams:
Added spec 001-80659 *A.
Updated Electrical specifications:
*I
2017-01-09
2017-04-26
Replaced PRGIO with Smart I/O in all instances.
*J
Updated Cypress Logo and Copyright.
Datasheet
55
002-00123 Rev. *P
2023-01-23
PSoC™ 4 MCU: PSoC™ 4000S
Based on Arm® Cortex®-M0+ CPU
Revision history
Document
Date of release Description of changes
version
Updated Document Title to read as “PSoC® 4: PSoC 4000S Datasheet
Programmable System-on-Chip (PSoC®)”.
Added 32-pin TQFP Package related information in all instance across the
document.
Updated Ordering information:
*K
2017-11-17
Updated part numbers.
Updated Packaging:
Updated Package diagrams:
spec 001-42168 – Changed revision from *E to *F.
Added spec 51-85088 *E.
Updated Features:
Updated 32-bit MCU subsystem:
Updated description.
Added Development ecosystem.
Added PSoC™ Creator.
Updated Functional definition:
Updated System resources:
Updated Power system:
Updated description.
Updated Watch crystal oscillator (WCO):
Updated description.
Updated Fixed function digital:
Updated Serial communication block (SCB):
Updated description.
Updated Special function peripherals:
Updated LCD segment drive:
Updated description.
*L
2019-07-31
Updated Pinouts:
Added Note below Table 1.
Updated Electrical specifications:
Updated Analog peripherals:
Updated CSD and IDAC:
Updated Table 12 (Updated details in “Details/Conditions” column
corresponding to VREF, VREF_EXT and VCOMPIDAC parameters).
Updated Digital peripherals:
Updated SPI:
Updated Table 18 (Updated all values corresponding to TSSELSSCK
parameter).
Updated Ordering information:
Updated part numbers.
Updated Packaging:
Updated Package diagrams:
spec 001-13937 – Changed revision from *F to *G.
Updated to new template.
Completing Sunset Review.
Datasheet
56
002-00123 Rev. *P
2023-01-23
PSoC™ 4 MCU: PSoC™ 4000S
Based on Arm® Cortex®-M0+ CPU
Revision history
Document
Date of release Description of changes
version
Updated Features:
Added “Clock sources”.
Added “ModusToolbox™ software”.
Updated Development ecosystem:
Replaced “More Information” with “Development ecosystem” in heading.
Updated description.
Added ModusToolbox™ software.
Updated Electrical specifications:
Updated Device level specifications:
Updated temperature range in description below heading.
Updated System resources:
*M
2020-11-20
Updated Power-on reset (POR):
Updated Table 25.
Updated Ordering information:
Updated Table 36:
Added Q-temp MPNs for the 48-pin TQFP package.
Updated Packaging:
Updated Table 38.
Updated to new template.
Updated Ordering information:
*N
2020-12-23
Updated Nomenclature:
Updated details under Temperature Range to show “Extended Industrial”.
Updated Table 29: Updated spec SID223 and SID223A. Added specs
SID223B through SID223D.
*O
*P
2022-07-28
2023-01-23
Migrated to Infineon template.
Updated the footnotes in IMO AC specifications.
Datasheet
57
002-00123 Rev. *P
2023-01-23
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IMPORTANT NOTICE
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Edition 2023-01-23
Published by
event be regarded as a guarantee of conditions or dangerous substances. For information on the types
characteristics (“Beschaffenheitsgarantie”).
in question please contact your nearest Infineon
Technologies office.
With respect to any examples, hints or any typical
Infineon Technologies AG
81726 Munich, Germany
values stated herein and/or any information Except as otherwise explicitly approved by Infineon
regarding the application of the product, Infineon Technologies in
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Technologies hereby disclaims any and all authorized
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Document reference
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