CY8C4124LQS-S433T [INFINEON]

Automotive PSoC™ 4100S;


型号：	CY8C4124LQS-S433T
厂家：	Infineon
描述：	Automotive PSoC™ 4100S
文件：	总59页 (文件大小：616K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

r e s t r i c t e d

CY8C41xx

Automotive PSoC™ 4: PSoC™ 4100S family

Based on Arm® Cortex®-M0+ CPU

Functional description

PSoC™ 4 is a scalable and reconfigurable platform architecture for a family of programmable embedded system

controllers with an Arm® Cortex®-M0+ CPU, while being AEC-Q100 compliant. It combines programmable and

reconfigurable analog and digital blocks with flexible automatic routing. The PSoC™ 4100S product family is a

member of the PSoC™ 4 platform architecture. It is a combination of a microcontroller with standard

communication and timing peripherals, a capacitive touch-sensing system (CAPSENSE™) with best-in-class

performance, programmable general-purpose continuous-time and switched-capacitor analog blocks, and

programmable connectivity. PSoC™ 4100S products will be upward compatible with members of the PSoC™ 4

platform for new applications and design needs.

Features

• Automotive Electronics Council (AEC) AEC-Q100 Qualified

• 32-bit MCU subsystem

- 48-MHz Arm® Cortex®-M0+ CPU

- Up to 64 KB of flash with read accelerator

- Up to 8 KB of SRAM

• Programmable analog

- Two opamps with reconfigurable high-drive external and high-bandwidth internal drive and Comparator

modes and ADC input buffering capability. Opamps can operate in Deep Sleep low-power mode.

- 12-bit 1-Msps SAR ADC with differential and single-ended modes, and channel sequencer with signal averaging

- Single-slope 10-bit ADC function provided by a capacitance sensing block

- Two current DACs (IDACs) for general-purpose or capacitive sensing applications on any pin

- Two low-power comparators that operate in Deep Sleep low-power mode

• Programmable digital

- Programmable logic blocks allowing Boolean operations to be performed on port inputs and outputs

• Low-power 1.71-V to 5.5-V operation

- Deep Sleep mode with operational analog and 2.5-µA digital system current

• Capacitive sensing

- Capacitive sigma-delta (CSD) provides best-in-class signal-to-noise ratio (SNR) (>5:1) and water tolerance

- Infineon-supplied software component makes capacitive sensing design easy

- Automatic hardware tuning (SmartSense)

• LCD drive capability

- LCD segment drive capability on GPIOs

• Serial communication

- Three independent run-time reconfigurable serial communication blocks (SCBs) with re-configurable I²C, SPI,

UART, or LIN slave functionality

• Timing and pulse-width modulation

- Five 16-bit timer/counter/pulse-width modulator (TCPWM) blocks

- Center-aligned, edge, and pseudo-random modes

- Comparator-based triggering of Kill signals for motor drive and other high-reliability digital logic applications

• Up to 38 programmable GPIO pins

- 24-pin QFN, 28-pin SSOP, 40-pin QFN, and 48-pin QFN packages

- Any GPIO pin can be CapSense, analog, or digital

- Drive modes, strengths, and slew rates are programmable

Datasheet

www.infineon.com

Please read the Important Notice and Warnings at the end of this document

page 1

002-15106 Rev. *J

2023-02-21

r e s t r i c t e d

Automotive PSoC™ 4: PSoC™ 4100S family

Based on Arm® Cortex®-M0+ CPU

Features

• PSoC™ Creator design environment

- Integrated development environment (IDE) provides

schematic design entry and build (with analog and digital automatic routing)

- Applications programming interface (API) component for all fixed-function and programmable peripherals

• Industry-standard tool compatibility

- After schematic entry, development can be done with Arm®-based industry-standard development tools

• Temperature ranges

- A-grade: –40°C to +85°C

- S-grade: –40°C to +105°C

- E-grade: –40°C to +125°C^[1]

Note

1. This device can also operate at temperatures exceeding 125°C (the high temperature of the AEC-Q100 Grade 1 operating range) for a

limited amount of time depending on the mission profile of the application. Infineon provides a retention calculator to help estimate

the retention lifetime based on the customers' individual temperature profiles for operation throughout the –40°C to +150°C ambient

temperature range. Go to the Infineon community page for more details.

Datasheet

002-15106 Rev. *J

2023-02-21

r e s t r i c t e d

Automotive PSoC™ 4: PSoC™ 4100S family

Based on Arm® Cortex®-M0+ CPU

Table of contents

Functional description.......................................................................................................................1

Features ...........................................................................................................................................1

Table of contents...............................................................................................................................3

Logic block diagram ..........................................................................................................................4

1 Functional overview .......................................................................................................................5

1.1 CPU and memory subsystem .................................................................................................................................5

1.2 System resources....................................................................................................................................................6

1.3 Analog blocks ..........................................................................................................................................................7

1.4 Fixed function digital ..............................................................................................................................................9

1.5 LIN slave mode........................................................................................................................................................9

1.6 GPIO.......................................................................................................................................................................10

1.7 Special function peripherals ................................................................................................................................10

2 Pinouts ........................................................................................................................................12

2.1 Alternate pin functions .........................................................................................................................................14

3 Power ..........................................................................................................................................16

3.1 Mode 1: 1.8 V to 5.5 V external supply..................................................................................................................16

3.2 Mode 2: 1.8 V ±5% external supply.......................................................................................................................16

4 Development support ...................................................................................................................18

4.1 Documentation .....................................................................................................................................................18

4.2 Online ....................................................................................................................................................................18

4.3 Tools ......................................................................................................................................................................18

5 Electrical specifications.................................................................................................................19

5.1 Absolute maximum ratings ..................................................................................................................................19

5.2 Device-level specifications ...................................................................................................................................20

5.3 Analog peripherals................................................................................................................................................25

5.4 Digital peripherals.................................................................................................................................................37

5.5 Memory..................................................................................................................................................................41

5.6 System resources..................................................................................................................................................42

6 Ordering information ....................................................................................................................45

7 Packaging information..................................................................................................................49

7.1 Package diagrams.................................................................................................................................................50

8 Acronyms.....................................................................................................................................55

9 Document conventions..................................................................................................................59

9.1 Units of measure ...................................................................................................................................................59

Revision history ..............................................................................................................................60

Datasheet

002-15106 Rev. *J

2023-02-21

r e s t r i c t e d

Automotive PSoC™ 4: PSoC™ 4100S family

Based on Arm® Cortex®-M0+ CPU

Logic block diagram

CPU Subsystem

PSoC™4100S

Architecture

SWD / TC

Cortex^®

M0+

SPCIF

FLASH

64 KB

SRAM

4 KB

ROM

8 KB

32-bit

48 MHz

FAST MUL

NVIC, IRQMUX

AHB- Lite

Read Accelerator

SRAM Controller

ROM Controller

System Resources

Lite

System Interconnect (Single Layer AHB)

Peripheral Interconnect (MMIO)

Power

Sleep Control

WIC

Peripherals

PCLK

POR

REF

PWRSYS

Clock

Clock Control

WDT

Programmable

Analog

ILO

IMO

Reset

Reset Control

XRES

SAR ADC

)

12-

bit

(

Test

TestMode Entry

Digital DFT

Analog DFT

CTBm

2 x Opamp

SARMUX

High Speed I/O Matrix& 2 x Programmable I/O

34x GPIOs, LCD

Power Modes

Active/ Sleep

DeepSleep

I/O Subsystem

Figure 1

Logic block diagram

Datasheet

002-15106 Rev. *J

2023-02-21

r e s t r i c t e d

Automotive PSoC™ 4: PSoC™ 4100S family

Based on Arm® Cortex®-M0+ CPU

Functional overview

PSoC™ 4100S devices include extensive support for programming, testing, debugging, and tracing both hardware

and firmware.

The Arm® SWD interface supports all programming and debug features of the device.

Complete debug-on-chip functionality enables full-device debugging in the final system using the standard

production device. It does not require special interfaces, debugging pods, simulators, or emulators. Only the

standard programming connections are required to fully support debug.

The PSoC™ Creator IDE provides fully integrated programming and debug support for the PSoC™ 4100S devices.

The SWD interface is fully compatible with industry-standard third-party tools. The PSoC™ 4100S family provides

a level of security not possible with multi-chip application solutions or with microcontrollers.

It has the following advantages:

• Allows disabling of debug features

• Robust flash protection

• Allows customer-proprietary functionality to be implemented in on-chip programmable blocks

The debug circuits are enabled by default and can be disabled in firmware. If they are not enabled, the only way

to re-enable them is to erase the entire device, clear flash protection, and reprogram the device with new

firmware that enables debugging. Thus firmware control of debugging cannot be over-ridden without erasing the

firmware thus providing security.

Additionally, all device interfaces can be permanently disabled (device security) for applications concerned

about phishing attacks due to a maliciously reprogrammed device or attempts to defeat security by starting and

interrupting flash programming sequences. All programming, debug, and test interfaces are disabled when

maximum device security is enabled. Therefore, PSoC™ 4100S, with device security enabled, may not be returned

for failure analysis. This is a trade-off the PSoC™ 4100S allows the customer to make.

1.1

CPU and memory subsystem

CPU

1.1.1

The Cortex®-M0+ CPU in the PSoC™ 4100S is part of the 32-bit MCU subsystem, which is optimized for low-power

operation with extensive clock gating. Most instructions are 16 bits in length and the CPU executes a subset of

the Thumb-2 instruction set. It includes a nested vectored interrupt controller (NVIC) block with eight interrupt

inputs and also includes a wakeup interrupt controller (WIC). The WIC can wake the processor from Deep Sleep

mode, allowing power to be switched off to the main processor when the chip is in Deep Sleep mode.

The CPU also includes a debug interface, the SWD interface, which is a two-wire form of JTAG. The debug config-

uration used for PSoC™ 4100S has four breakpoint (address) comparators and two watchpoint (data) compar-

ators.

1.1.2

Flash

The PSoC™ 4100S device has a flash module with a flash accelerator, tightly coupled to the CPU to improve

average access times from the flash block. The low-power flash block is designed to deliver two wait state (WS)

access time at 48 MHz. The flash accelerator delivers 85% of single-cycle SRAM access performance on average.

1.1.3

SRAM

8 KB of SRAM are provided with zero wait state access at 48 MHz.

1.1.4

SROM

An 8 KB supervisory ROM that contains boot and configuration routines is provided.

Datasheet

002-15106 Rev. *J

2023-02-21

r e s t r i c t e d

Automotive PSoC™ 4: PSoC™ 4100S family

Based on Arm® Cortex®-M0+ CPU

Functional overview

1.2

1.2.1

System resources

Power system

The power system is described in detail in the section “Power” on page 16. It provides assurance that voltage

levels are as required for each respective mode and either delays mode entry (for example, on power-on reset

(POR)) until voltage levels are as required for proper functionality, or generates resets (for example, on brown-out

detection). The PSoC™ 4100S operates with a single external supply over the range of either 1.8 V ±5% (externally

regulated) or 1.8 to 5.5 V (internally regulated) and has three different power modes, transitions between which

are managed by the power system. The PSoC™ 4100S provides Active, Sleep, and Deep Sleep low-power modes.

All subsystems are operational in Active mode. The CPU subsystem (CPU, flash, and SRAM) is clock-gated off in

Sleep mode, while all peripherals and interrupts are active with instantaneous wake-up on a wake-up event. In

Deep Sleep mode, the high-speed clock and associated circuitry is switched off; wake-up from this mode takes

35 µs. The opamps can remain operational in Deep Sleep mode.

1.2.2

Clock system

The PSoC™ 4100S clock system is responsible for providing clocks to all subsystems that require clocks and for

switching between different clock sources without glitching. In addition, the clock system ensures that there are

no metastable conditions.

The clock system for the PSoC™ 4100S consists of the internal main oscillator (IMO), internal low-speed oscillator

(ILO), a 32 kHz watch crystal oscillator (WCO) and provision for an external clock. Clock dividers are provided to

generate clocks for peripherals on a fine-grained basis. Fractional dividers are also provided to enable clocking

of higher data rates for UARTs.

IMO

HFCLK

Divide By

2,4,8

External Clock

ILO

LFCLK

HFCLK

Prescaler

SYSCLK

Integer

Dividers

6X 16-bit

Fractional

Dividers

2X 16.5-bit

Figure 2

Clocking architecture

The HFCLK signal can be divided down to generate synchronous clocks for the analog and digital peripherals.

There are eight clock dividers for the PSoC™ 4100S; two of those are fractional dividers. The 16-bit capability

allows flexible generation of fine-grained frequency values and is fully supported in PSoC™ Creator

1.2.3

IMO clock source

The IMO is the primary source of internal clocking in the PSoC™ 4100S. It is trimmed during testing to achieve the

specified accuracy.The IMO default frequency is 24 MHz and it can be adjusted from 24 to 48 MHz in steps of 4 MHz.

The IMO tolerance with Infineon-provided calibration settings is ±2%.

1.2.4

ILO clock source

The ILO is a very low power, nominally 40-kHz oscillator, which is primarily used to generate clocks for the

watchdog timer (WDT) and peripheral operation in Deep Sleep mode. ILO-driven counters can be calibrated to

the IMO to improve accuracy. Infineon provides a software component, which does the calibration.

Datasheet

002-15106 Rev. *J

2023-02-21

r e s t r i c t e d

Automotive PSoC™ 4: PSoC™ 4100S family

Based on Arm® Cortex®-M0+ CPU

Functional overview

1.2.5

Watch crystal oscillator (WCO)

The PSoC™ 4100S clock subsystem also implements a low-frequency (32-kHz watch crystal) oscillator that can

be used for precision timing applications.

1.2.6

Watchdog timer

A watchdog timer is implemented in the clock block running from the ILO; this allows watchdog operation during

Deep Sleep and generates a watchdog reset if not serviced before the set timeout occurs. The watchdog reset is

recorded in a Reset Cause register, which is firmware readable.

1.2.7

Reset

The PSoC™ 4100S can be reset from a variety of sources including a software reset. Reset events are asynchronous

and guarantee reversion to a known state. The reset cause is recorded in a register, which is sticky through reset

and allows software to determine the cause of the reset. An XRES pin is reserved for external reset by asserting it

active low. The XRES pin has an internal pull-up resistor that is always enabled.

1.3

Analog blocks

1.3.1

12-bit successive approximation register (SAR) ADC

The 12-bit, 1-Msps SAR ADC can operate at a maximum clock rate of 18 MHz and requires a minimum of 18 clocks

at that frequency to do a 12-bit conversion.

The Sample-and-Hold (S/H) aperture is programmable allowing the gain bandwidth requirements of the

amplifier driving the SAR inputs, which determine its settling time, to be relaxed if required. It is possible to

provide an external bypass (through a fixed pin location) for the internal reference amplifier.

The SAR is connected to a fixed set of pins through an 8-input sequencer. The sequencer cycles through selected

channels autonomously (sequencer scan) with zero switching overhead (that is, aggregate sampling bandwidth

is equal to 1 Msps whether it is for a single channel or distributed over several channels). The sequencer switching

is effected through a state machine or through firmware driven switching. A feature provided by the sequencer

is buffering of each channel to reduce CPU interrupt service requirements. To accommodate signals with varying

source impedance and frequency, it is possible to have different sample times programmable for each channel.

Also, signal range specification through a pair of range registers (low and high range values) is implemented with

a corresponding out-of-range interrupt if the digitized value exceeds the programmed range; this allows fast

detection of out-of-range values without the necessity of having to wait for a sequencer scan to be completed

and the CPU to read the values and check for out-of-range values in software.

The SAR is not available in Deep Sleep mode as it requires a high-speed clock (up to 18 MHz). The SAR operating

range is 1.71 V to 5.5 V.

Datasheet

002-15106 Rev. *J

2023-02-21

r e s t r i c t e d

Automotive PSoC™ 4: PSoC™ 4100S family

Based on Arm® Cortex®-M0+ CPU

Functional overview

AHB System Bus and Programmable Logic

Interconnect

SAR Sequencer

Sequencing

and Control

Data and

Status Flags

POS

NEG

SARADC

External

Reference

and

Bypass

(optional )

Reference

Selection

VDDD

VREF

VDD/2

Inputs from other Ports

Figure 3

SAR ADC

1.3.2

Two opamps (Continuous-time block; CTB)

The PSoC™ 4100S has two opamps with Comparator modes which allow most common analog functions to be

performed on-chip eliminating external components; PGAs, Voltage Buffers, Filters, Trans-Impedance Amplifiers,

and other functions can be realized, in some cases with external passives. saving power, cost, and space. The

on-chip opamps are designed with enough bandwidth to drive the Sample-and-Hold circuit of the ADC without

requiring external buffering.

1.3.3

Low-power comparators (LPC)

The PSoC™ 4100S has a pair of low-power comparators, which can also operate in Deep Sleep modes. This allows

the analog system blocks to be disabled while retaining the ability to monitor external voltage levels during

low-power modes. The comparator outputs are normally synchronized to avoid metastability unless operating

in an asynchronous power mode where the system wake-up circuit is activated by a comparator switch event.

The LPC outputs can be routed to pins.

1.3.4

Current DACs

The PSoC™ 4100S has two IDACs, which can drive any of the pins on the chip. These IDACs have programmable

current ranges.

1.3.5

Analog multiplexed buses

The PSoC™ 4100S has two concentric independent buses that go around the periphery of the chip. These buses

(called amux buses) are connected to firmware-programmable analog switches that allow the chip's internal

resources (IDACs, comparator) to connect to any pin on the I/O Ports.

1.3.6

Programmable digital blocks

The Programmable I/O (Smart I/O) block is a fabric of switches and LUTs that allows Boolean functions to be

performed in signals being routed to the pins of a GPIO port. The Smart I/O can perform logical operations on

input pins to the chip and on signals going out as outputs.

Datasheet

002-15106 Rev. *J

2023-02-21

r e s t r i c t e d

Automotive PSoC™ 4: PSoC™ 4100S family

Based on Arm® Cortex®-M0+ CPU

Functional overview

1.4

Fixed function digital

1.4.1

Timer/counter/PWM (TCPWM) block

The TCPWM block consists of a 16-bit counter with user-programmable period length. There is a capture register

to record the count value at the time of an event (which may be an I/O event), a period register that is used to

either stop or auto-reload the counter when its count is equal to the period register, and compare registers to

generate compare value signals that are used as PWM duty cycle outputs. The block also provides true and

complementary outputs with programmable offset between them to allow use as dead-band programmable

complementary PWM outputs. It also has a Kill input to force outputs to a predetermined state; for example, this

is used in motor drive systems when an over-current state is indicated and the PWM driving the FETs needs to be

shut off immediately with no time for software intervention. There are five TCPWM blocks in the PSoC™ 4100S.

1.4.2

Serial communication block (SCB)

The PSoC™ 4100S has three serial communication blocks, which can be programmed to have SPI, I2C, UART or

LIN Slave functionality.

I²C Mode: The hardware I²C block implements a full multi-master and slave interface (it is capable of

multi-master arbitration). This block is capable of operating at speeds of up to 1 Mbps (Fast Mode Plus) and has

flexible buffering options to reduce interrupt overhead and latency for the CPU. It also supports EZI2C that

creates a mailbox address range in the memory of the PSoC™ 4100S and effectively reduces I²C communication

to reading from and writing to an array in memory. In addition, the block supports an 8-deep FIFO for receive and

transmit which, by increasing the time given for the CPU to read data, greatly reduces the need for clock

stretching caused by the CPU not having read data on time.

The I²C peripheral is compatible with the I²C Standard-mode and Fast-mode devices as defined in the NXP

I²C-bus specification and user manual (UM10204). The I²C bus I/O is implemented with GPIO in open-drain

modes.

The PSoC™ 4100S is not completely compliant with the I²C spec in the following respect:

• GPIO cells are not overvoltage tolerant and, therefore, cannot be hot-swapped or powered up independently

of the rest of the I²C system.

UART Mode: This is a full-feature UART operating at up to 1 Mbps. It supports automotive single-wire interface

(LIN), infrared interface (IrDA), and SmartCard (ISO7816) protocols, all of which are minor variants of the basic

UART protocol. In addition, it supports the 9-bit multiprocessor mode that allows addressing of peripherals

connected over common RX and TX lines. Common UART functions such as parity error, break detect, and frame

error are supported. An 8-deep FIFO allows much greater CPU service latencies to be tolerated.

SPI Mode: The SPI mode supports full Motorola SPI, TI SSP (adds a start pulse used to synchronize SPI Codecs),

and National Microwire (half-duplex form of SPI). The SPI block can use the FIFO.

1.5

LIN slave mode

The LIN Slave mode uses the SCB hardware block and implements a full LIN slave interface. This LIN Slave is

compliant with LIN v1.3, v2.1/2.2, ISO 17987-6, and SAE J2602-2 specification standards. It is certified by C&S

GmbH based on the standard protocol and data link layer conformance tests. LIN slave can be operated at baud

rates of up to ~20 Kbps with a maximum of 40-meter cable length. PSoC™ Creator software supports up to two

LIN slave interfaces in the PSoC™ 4 device, providing built-in application programming interfaces (APIs) based on

the LIN specification standard.

Datasheet

002-15106 Rev. *J

2023-02-21

r e s t r i c t e d

Automotive PSoC™ 4: PSoC™ 4100S family

Based on Arm® Cortex®-M0+ CPU

Functional overview

1.6

GPIO

The PSoC™ 4100S has up to 38 GPIOs.

The GPIO block implements the following:

• Eight drive modes:

- Analog input mode (input and output buffers disabled)

- Input only

- Weak pull-up with strong pull-down

- Strong pull-up with weak pull-down

- Open drain with strong pull-down

- Open drain with strong pull-up

- Strong pull-up with strong pull-down

- Weak pull-up with weak pull-down

• Input threshold select (CMOS or LVTTL).

• Individual control of input and output buffer enabling/disabling in addition to the drive strength modes

• Selectable slew rates for dV/dt related noise control to improve EMI

The pins are organized in logical entities called ports, which are 8-bit in width. During power-on and reset, the

blocks are forced to the disabled state so as not to crowbar any inputs and/or cause excess turn-on current. A

multiplexing network known as a high-speed I/O matrix is used to multiplex between various signals that may

connect to an I/O pin.

Data output and pin state registers store, respectively, the values to be driven on the pins and the states of the

pins themselves.

Every I/O pin can generate an interrupt if so enabled and each I/O port has an interrupt request (IRQ) and interrupt

service routine (ISR) vector associated with it (5 for PSoC™ 4100S).

Datasheet

002-15106 Rev. *J

2023-02-21

r e s t r i c t e d

Automotive PSoC™ 4: PSoC™ 4100S family

Based on Arm® Cortex®-M0+ CPU

Functional overview

1.7

1.7.1

Special function peripherals

CAPSENSE™

CAPSENSE™ is supported in the PSoC™ 4100S through a CSD block that can be connected to any pins through an

analog multiplex bus via analog switches. CAPSENSE™ function can thus be provided on any available pin or

group of pins in a system under software control. A PSoC™ Creator component is provided for the CAPSENSE™

block to make it easy for the user.

Shield voltage can be driven on another analog multiplex bus to provide water-tolerance capability. Water

tolerance is provided by driving the shield electrode in phase with the sense electrode to keep the shield capac-

itance from attenuating the sensed input. Proximity sensing can also be implemented.

The CAPSENSE™ block has two IDACs, which can be used for general purposes if CAPSENSE™ is not being used

(both IDACs are available in that case) or if CAPSENSE™ is used without water tolerance (one IDAC is available).

The CAPSENSE™ block also provides a 10-bit Slope ADC function which can be used in conjunction with the

CAPSENSE™ function.

The CAPSENSE™ block is an advanced, low-noise, programmable block with programmable voltage references

and current source ranges for improved sensitivity and flexibility. It can also use an external reference voltage. It

has a full-wave CSD mode that alternates sensing to VDDA and ground to null out power-supply related noise.

1.7.2

LCD segment drive

The PSoC™ 4100S has an LCD controller, which can drive up to 4 commons and up to 32 segments. It uses full

digital methods to drive the LCD segments requiring no generation of internal LCD voltages. The two methods

used are referred to as Digital Correlation and PWM. Digital Correlation pertains to modulating the frequency and

drive levels of the common and segment signals to generate the highest RMS voltage across a segment to light it

up or to keep the RMS signal to zero. This method is good for STN displays but may result in reduced contrast

with TN (cheaper) displays. PWM pertains to driving the panel with PWM signals to effectively use the capacitance

of the panel to provide the integration of the modulated pulse-width to generate the desired LCD voltage. This

method results in higher power consumption but can result in better results when driving TN displays. LCD

operation is supported during Deep Sleep refreshing a small display buffer (4 bits; 1 32-bit register per port).

Datasheet

002-15106 Rev. *J

2023-02-21

r e s t r i c t e d

Automotive PSoC™ 4: PSoC™ 4100S family

Based on Arm® Cortex®-M0+ CPU

Pinouts

Table 1 provides the pin list for PSoC™ 4100S for the for the 8-pin QFN, 40-pin QFN, 28-pin SSOP, and 24-pin QFN

packages. All port pins support GPIO.

Table 1

Pin list

48-QFN-Auto

40-QFN-Auto

28-SSOP-Auto

24-QFN-Auto-2

Name

P0.0

Name

P0.0

P0.1

P0.2

P0.3

P0.4

P0.5

P0.6

P0.7

XRES

VCCD

VSSD

VDD

VSSA

P1.0

P1.1

P1.2

P1.3

P1.4

Name

P0.0

P0.1

P0.2

P0.3

Name

P0.0

P0.1

P0.2

P0.3

P0.4

P0.5

P0.6

P0.7

XRES

VCCD

VSSD

VDDD

VDDA

VSSA

P1.0

P1.1

P1.2

P1.3

P1.4

P0.4

P0.5

P0.6

P0.7

XRES

VCCD

VSS

XRES

VCCD

VSSD

VDD

VSSA

P1.0

P1.1

P1.2

P1.3

P1.4

P1.2

P1.3

P1.5

P1.6

P1.7/VREF

P2.0

P1.7/VREF

P2.0

P1.7/VREF

P2.0

P2.1

P2.2

P2.3

P2.4

P2.5

P2.6

P2.7

P2.4

P2.5

P2.6

P2.7

P2.4

P2.5

P2.6

P2.7

P2.6

P2.7

VSSD

P3.0

P3.1

P3.2

P3.3

VSSD

P3.0

P3.1

P3.2

P3.3

P3.0

P3.1

P3.2

P3.3

P3.0

P3.2

P3.3

Datasheet

002-15106 Rev. *J

2023-02-21

r e s t r i c t e d

Automotive PSoC™ 4: PSoC™ 4100S family

Based on Arm® Cortex®-M0+ CPU

Pinouts

Table 1

48-QFN-Auto

Pin list (continued)

40-QFN-Auto

28-SSOP-Auto

24-QFN-Auto-2

Name

P3.4

P3.5

P3.6

P3.7

VDDD

P4.0

P4.1

P4.2

P4.3

Name

P3.4

P3.5

P3.6

P3.7

Name

P4.0

P4.1

P4.2

P4.3

P4.0

P4.1

P4.2

P4.3

P4.0

P4.1

P4.2

P4.3

The power pins description is as follows:

VDDD: Power supply for the digital section.

VDDA: Power supply for the analog section.

VSSD, VSSA: Ground pins for the digital and analog sections respectively.

VCCD: Regulated digital supply (1.8 V ± 5%)

VDD: On some packages, VDDA and VDDD are shorted inside and brought out as a single power supply

NC: No connection

Datasheet

002-15106 Rev. *J

2023-02-21

2.1

Alternate pin functions

Each port pin has can be assigned to one of multiple functions. For example, it can be an analog I/O, a digital peripheral function, an LCD pin, or a

CAPSENSE™ pin.

Table 2 provides the pin assignments.

Table 2

Alternate pin functions

Alternate

Name

Analog

Smart I/O

Deep Sleep 1 Deep Sleep 2

Deep Sleep 3

Deelp Sleep 4

Function 1

Function 2

Function 3

P0.0

P0.1

P0.2

P0.3

P0.4

P0.5

P0.6

P0.7

P1.0

lpcomp.in_p[0]

lpcomp.in_n[0]

lpcomp.in_p[1]

lpcomp.in_n[1]

wco.wco_in

scb[2].uart_cts:0

scb[2].uart_rts:0

tcpwm.tr_in[0]

tcpwm.tr_in[1]

lcd.com[0]

lcd.com[1]

lcd.com[2]

lcd.com[3]

lcd.com[4]

lcd.com[5]

lcd.com[6]

lcd.com[7]

lcd.com[8]

lcd.seg[0]

lcd.seg[1]

lcd.seg[2]

lcd.seg[3]

lcd.seg[4]

lcd.seg[5]

lcd.seg[6]

lcd.seg[7]

lcd.seg[8]

scb[2].i2c_scl:0 scb[0].spi_select1:0

scb[2].i2c_sda:0 scb[0].spi_select2:0

scb[0].spi_select3:0

scb[2].spi_select0

scb[1].uart_rx:0

scb[1].uart_tx:0

scb[1].uart_cts:0

scb[1].uart_rts:0

scb[0].uart_rx:1

scb[2].uart_rx:0

scb[2].uart_tx:0

scb[2].uart_tx:1

scb[1].i2c_scl:0

scb[1].i2c_sda:0

scb[1].spi_mosi:1

scb[1].spi_miso:1

scb[1].spi_clk:1

wco.wco_out

srss.adft_por_pad_hv

srss.ext_clk

tcpwm.line[0]:2

tcpwm.line[2]:1

scb[1].spi_select0:1

scb[0].spi_mosi:1

pass.ctb0_pads[0]

pass.ctb0_pads[1]

scb[0].i2c_scl:0

scb[0].i2c_sda:0

scb[2].i2c_scl:1

P1.1

P1.2

P1.3

tcpwm.line_-

compl[2]:1

scb[0].uart_tx:1

scb[0].uart_cts:1

scb[0].uart_rts:1

lcd.com[9]

lcd.com[10]

lcd.com[11]

lcd.seg[9]

lcd.seg[10]

lcd.seg[11]

scb[0].spi_miso:1

scb[0].spi_clk:1

pass.ctb0_pads[2]

tcpwm.line[3]:1

tcpwm.tr_in[2]

tcpwm.tr_in[3]

pass.ctb0_oa0_out_10x

pass.ctb0_pads[3]

tcpwm.line_-

compl[3]:1

scb[2].i2c_sda:1 scb[0].spi_select0:1

pass.ctb0_oa1_out_10x

P1.4

P1.5

P1.6

P1.7

pass.ctb0_pads[4]

pass.ctb0_pads[5]

pass.ctb0_pads[6]

lcd.com[12]

lcd.com[13]

lcd.com[14]

lcd.com[15]

lcd.seg[12]

lcd.seg[13]

lcd.seg[14]

lcd.seg[15]

scb[0].spi_select1:1

scb[0].spi_select2:1

scb[0].spi_select3:1

scb[2].spi_clk

pass.ctb0_pads[7]

pass.sar_ext_vref0

pass.sar_ext_vref1

P2.0

P2.1

pass.sarmux_pads[0] prgio[0].io[0] tcpwm.line[4]:0

csd.comp

tcpwm.tr_in[4]

tcpwm.tr_in[5]

lcd.com[16]

lcd.com[17]

lcd.seg[16]

lcd.seg[17]

scb[1].i2c_scl:1

scb[1].i2c_sda:1

scb[1].spi_mosi:2

scb[1].spi_miso:2

pass.sarmux_pads[1] prgio[0].io[1] tcpwm.line_-

compl[4]:0

P2.2

pass.sarmux_pads[2] prgio[0].io[2]

lcd.com[18]

lcd.seg[18]

scb[1].spi_clk:2

Table 2

Alternate pin functions (continued)

Alternate

Name

Analog

Smart I/O

Deep Sleep 1 Deep Sleep 2

Deep Sleep 3

Deelp Sleep 4

Function 1

Function 2

Function 3

P2.3

P2.4

P2.5

pass.sarmux_pads[3] prgio[0].io[3]

lcd.com[19]

lcd.com[20]

lcd.com[21]

lcd.seg[19]

lcd.seg[20]

lcd.seg[21]

scb[1].spi_select0:2

scb[1].spi_select1:1

scb[1].spi_select2:1

pass.sarmux_pads[4] prgio[0].io[4] tcpwm.line[0]:1

pass.sarmux_pads[5] prgio[0].io[5] tcpwm.line_-

compl[0]:1

P2.6

P2.7

pass.sarmux_pads[6] prgio[0].io[6] tcpwm.line[1]:1

lcd.com[22]

lcd.com[23]

lcd.seg[22]

lcd.seg[23]

scb[1].spi_select3:1

scb[2].spi_mosi

pass.sarmux_pads[7] prgio[0].io[7] tcpwm.line_-

compl[1]:1

lpcomp.comp[0]:1

P3.0

P3.1

prgio[1].io[0] tcpwm.line[0]:0

scb[1].uart_rx:1

scb[1].uart_tx:1

lcd.com[24]

lcd.com[25]

lcd.seg[24]

lcd.seg[25]

scb[1].i2c_scl:2

scb[1].i2c_sda:2

scb[1].spi_mosi:0

scb[1].spi_miso:0

prgio[1].io[1] tcpwm.line_-

compl[0]:0

P3.2

P3.3

prgio[1].io[2] tcpwm.line[1]:0

scb[1].uart_cts:1

scb[1].uart_rts:1

lcd.com[26]

lcd.com[27]

lcd.seg[26]

lcd.seg[27]

cpuss.swd_data

cpuss.swd_clk

scb[1].spi_clk:0

prgio[1].io[3] tcpwm.line_-

compl[1]:0

scb[1].spi_select0:0

P3.4

P3.5

prgio[1].io[4] tcpwm.line[2]:0

tcpwm.tr_in[6]

lcd.com[28]

lcd.com[29]

lcd.seg[28]

lcd.seg[29]

scb[1].spi_select1:0

scb[1].spi_select2:0

prgio[1].io[5] tcpwm.line_-

compl[2]:0

P3.6

P3.7

prgio[1].io[6] tcpwm.line[3]:0

lcd.com[30]

lcd.com[31]

lcd.seg[30]

lcd.seg[31]

scb[1].spi_select3:0

scb[2].spi_miso

prgio[1].io[7] tcpwm.line_-

compl[3]:0

lpcomp.comp[1]:1

P4.0

P4.1

P4.2

csd.vref_ext

scb[0].uart_rx:0

scb[0].uart_tx:0

scb[0].uart_cts:0

lcd.com[32]

lcd.com[33]

lcd.com[34]

lcd.seg[32]

lcd.seg[33]

lcd.seg[34]

scb[0].i2c_scl:1

scb[0].i2c_sda:1

lpcomp.comp[0]:0

scb[0].spi_mosi:0

scb[0].spi_miso:0

scb[0].spi_clk:0

csd.cshieldpads

csd.cmodpads

csd.cmodpadd

P4.3

csd.csh_tankpads

csd.csh_tankpadd

scb[0].uart_rts:0

lcd.com[35]

lcd.seg[35]

lpcomp.comp[1]:0 scb[0].spi_select0:0

r e s t r i c t e d

Automotive PSoC™ 4: PSoC™ 4100S family

Based on Arm® Cortex®-M0+ CPU

Power

Figure 4 illustrates the set of power supply pins as implemented for the PSoC™ 4100S. The system has one

regulator in Active mode for the digital circuitry. There is no analog regulator; the analog circuits run directly from

the V_DDAinput.

VDDA

VDDD

VDDA

VSSA

VDDD

VSSD

Analog

Domain

Digital

Domain

VCCD

1.8 Volt

Regulator

Figure 4

Power supply connections

There are two distinct modes of operation. In Mode 1, the supply voltage range is 1.8 V to 5.5 V (unregulated

externally; internal regulator operational). In Mode 2, the supply range is1.8 V ±5% (externally regulated; 1.71 to

1.89, internal regulator bypassed).

3.1

Mode 1: 1.8 V to 5.5 V external supply

In this mode, the PSoC™ 4100S is powered by an external power supply that can be anywhere in the range of 1.8

to 5.5 V. This range is also designed for battery-powered operation. For example, the chip can be powered from

a battery system that starts at 3.5 V and works down to 1.8 V. In this mode, the internal regulator of the

PSoC™ 4100S supplies the internal logic and its output is connected to the VCCD pin. The VCCD pin must be

bypassed to ground via an external capacitor (0.1 µF; X5R ceramic or better) and must not be connected to

anything else.

Datasheet

002-15106 Rev. *J

2023-02-21

r e s t r i c t e d

Automotive PSoC™ 4: PSoC™ 4100S family

Based on Arm® Cortex®-M0+ CPU

Power

3.2

Mode 2: 1.8 V ±5% external supply

In this mode, the PSoC™ 4100S is powered by an external power supply that must be within the range of 1.71 to

1.89 V; note that this range needs to include the power supply ripple too. In this mode, the VDD and VCCD pins

are shorted together and bypassed.

Bypass capacitors must be used from VDDD to ground. The typical practice for systems in this frequency range is

to use a capacitor in the 1-µF range, in parallel with a smaller capacitor (0.1 µF, for example). Note that these are

simply rules of thumb and that, for critical applications, the PCB layout, lead inductance, and the bypass

capacitor parasitic should be simulated to design and obtain optimal bypassing.

On some packages, V_DDDand V_DDApins are shorted inside the package and brought out as a generic V_DDpin. In

that case, only 0.1 µF and 1 µF decoupling capacitors are required on the V_DDpin. Figure 5 illustrates an example

of a bypass scheme.

Power supply bypass connections example

1.8 V to 5.5 V

V_DDA

V_DD

1F

F

0.1F

V_CCD

0.1F

PSoC 4100S

V_SS

Figure 5

External supply range from 1.8 V to 5.5 V with internal regulator active

Datasheet

002-15106 Rev. *J

2023-02-21

r e s t r i c t e d

Automotive PSoC™ 4: PSoC™ 4100S family

Based on Arm® Cortex®-M0+ CPU

Development support

The PSoC™ 4100S family has a rich set of documentation, development tools, and online resources to assist you

during your development process. Visit www.infineon.com/psoc4 to find out more.

4.1

Documentation

A suite of documentation supports the PSoC™ 4100S family to ensure that you can find answers to your questions

quickly. This section contains a list of some of the key documents.

Software User Guide: A step-by-step guide for using PSoC™ Creator. The software user guide shows you how the

PSoC™ Creator build process works in detail, how to use source control with PSoC™ Creator, and much more.

Component Datasheets: The flexibility of PSoC™ allows the creation of new peripherals (components) long after

the device has gone into production. Component data sheets provide all of the information needed to select and

use a particular component, including a functional description, API documentation, example code, and AC/DC

specifications.

Application Notes: PSoC™ application notes discuss a particular application of PSoC™ in depth; examples

include brushless DC motor control and on-chip filtering. Application notes often include example projects in

addition to the application note document.

Technical Reference Manual: The Technical Reference Manual (TRM) contains all the technical detail you need

to use a PSoC™ device, including a complete description of all PSoC™ registers. The TRM is available in the

Documentation section at www.infineon.com/psoc4.

4.2

Online

In addition to print documentation, the PSoC™ forums connect you with fellow PSoC™ users and experts in

PSoC™ from around the world, 24 hours a day, 7 days a week.

4.3

Tools

With industry standard cores, programming, and debugging interfaces, the PSoC™ 4100S family is part of a devel-

opment tool ecosystem. Visit us at www.infineon.com/psoccreator for the latest information on the revolu-

tionary, easy to use PSoC™ Creator IDE, supported third party compilers, programmers, debuggers, and devel-

opment kits.

Datasheet

002-15106 Rev. *J

2023-02-21

r e s t r i c t e d

Automotive PSoC™ 4: PSoC™ 4100S family

Based on Arm® Cortex®-M0+ CPU

Electrical specifications

5.1

Table 3

Absolute maximum ratings

Absolute maximum ratings^[2]

Details/

Spec ID

SID1

Parameter Description

Min

–0.5

Typ

–

Max

Units

conditions

V_{DDD_ABS}

V_{CCD_ABS}

V_{GPIO_ABS}

I_{GPIO_ABS}

Digital supply relative to V_SS

–

Direct digital core voltage input

relative to V_SS

SID2

–

1.95

SID3

SID4

GPIO voltage

–0.5

–25

–

V_DD+0.5

–

Maximum current per GPIO

Current

injected per

GPIO injection current, Max for

V_IH> V_DDD, and Min for V_IL< V_SS

SID5

I_{GPIO_injection}

ESD_HBM

–0.5

–

0.5

–

Electrostatic discharge human

body model

–

BID44

2200

Electrostatic discharge charged

device model

BID45

BID46

ESD_CDM

500

–

Pin current for latch-up

–140

140

Note

2. Usage above the absolute maximum conditions listed in Table 3 may cause permanent damage to the device.

Exposure to Absolute Maximum conditions for extended periods of time may affect device reliability. The

Maximum Storage Temperature is 150°C in compliance with JEDEC Standard JESD22-A103, High

Temperature Storage Life. When used below Absolute Maximum conditions but above normal operating

conditions, the device may not operate to specification.

Datasheet

002-15106 Rev. *J

2023-02-21

r e s t r i c t e d

Automotive PSoC™ 4: PSoC™ 4100S family

Based on Arm® Cortex®-M0+ CPU

Electrical specifications

5.2

Device-level specifications

All specifications are valid for –40°C ≤ TA ≤ 85°C for Grade-A devices, –40°C ≤ T_A≤ 105°C for Grade-S devices, and

–40°C ≤ T_A≤ 125°C for Grade-E devices. Specifications are valid for 1.71 V to 5.5 V, except where noted.^[3]

5.2.1

Table 4

DC specifications

Typical values measured at V_DD= 3.3 V and 25°C.

Details/

Spec ID

Parameter

Description

Min

Typ

Max

Unit

conditions

Internally

regulated

supply

SID53

V_DD

Power supply input voltage

1.8

–

5.5

Internally

unregulated

supply

Power supply input voltage

SID255

V_DD

1.71

–

1.89

(V_CCD= V_DDD= V_DDA

)

SID54

SID55

V_CCD

C_EFC

Output voltage (for core logic)

–

1.8

0.1

–

X5R ceramic or

better

External regulator voltage bypass

µF

X5R ceramic or

better

SID56

C_EXC

Power supply bypass capacitor

–

Active Mode, V_DD= 1.8 V to 5.5 V. Typical values measured at VDD = 3.3 V and 25 °C.

Max is at 125°C

and 5.5 V

SID10

SID16

SID19

I_DD5

I_DD8

I_DD11

Execute from flash; CPU at 6 MHz

Execute from flash; CPU at 24 MHz

Execute from flash; CPU at 48 MHz

–

1.8

3.0

5.4

2.7

Max is at 125°C

and 5.5 V

4.75

6.85

Max is at 125°C

and 5.5 V

Sleep Mode, V_DDD= 1.8 V to 5.5 V (Regulator on)

I²C wakeup WDT, and Compar-

6 MHZ. Max is at

125°C and 5.5 V.

SID22

I_DD17

–

1.7

2.2

2.5

ators on

12 MHZ. Max is

at 125°C and

5.5 V.

I²C wakeup, WDT, and Compar-

ators on.

SID25

I_DD20

Sleep Mode, V_DDD= 1.71 V to 1.89 V (Regulator bypassed)

I²C wakeup, WDT, and

Comparators on

6 MHZ. Max is at

125°C and 5.5 V.

SID28

I_DD23

–

0.7

1.0

0.9

1.2

12 MHZ. Max is

mA at 125°C and

5.5 V.

I²C wakeup, WDT, and

Comparators on

SID28A

I_DD23A

Deep Sleep Mode, V_DD= 1.8 V to 3.6 V (Regulator on)

Max is at 3.6 V

µA

SID31

I_DD26

I²C wakeup and WDT on

–

2.5

150

and 125°C.

Note

3. This device is not AEC-Q100 Grade 0 qualified, so Infineon does not guarantee performance at +150°C. The

specifications for 125°C < T_A150°C are best estimates of the performance.

Datasheet

002-15106 Rev. *J

2023-02-21

r e s t r i c t e d

Automotive PSoC™ 4: PSoC™ 4100S family

Based on Arm® Cortex®-M0+ CPU

Electrical specifications

Table 4

DC specifications ^(continued)

Typical values measured at V_DD= 3.3 V and 25°C.

Details/

Spec ID

Deep Sleep Mode, V_DD= 3.6 V to 5.5 V (Regulator on)

SID34 I_DD29

I²C wakeup and WDT on

Parameter

Description

Min

Typ

2.5

Max

150

160

Unit

µA

conditions

Max is at 5.5 V

and 125°C.

–

Deep Sleep Mode, V_DD= V_CCD= 1.71 V to 1.89 V (Regulator bypassed)

Max is at 1.89 V

and 125°C.

SID37

I_DD32

I²C wakeup and WDT on

–

µA

XRES Current

Supply current while XRES

asserted

SID307

I_{DD_XR}

–

5.2.2

AC specifications

Table 5

AC specifications

Details/

Spec ID Parameter

Min

Typ

Max

Units

Description

conditions

SID48

F_CPU

CPU frequency

Wakeup from Sleep mode

Wakeup from Deep Sleep mode

–

MHz 1.71 V_DD5.5

SID49^[4]T_SLEEP

–

µs

–

SID50^[4]T_DEEPSLEEP

Note

4. Guaranteed by characterization.

Datasheet

002-15106 Rev. *J

2023-02-21

r e s t r i c t e d

Automotive PSoC™ 4: PSoC™ 4100S family

Based on Arm® Cortex®-M0+ CPU

Electrical specifications

5.2.3

Table 6

GPIO

GPIO DC specifications

Spec ID Parameter Description

Min

Typ

Max Unit Details/conditions

0.7 

[5]

SID57

V_IH

V_IL

V_IH

V_IL

Input voltage high threshold

Input voltage low threshold

LVTTL input, V_DDD< 2.7 V

–

CMOS Input

V_DDD

0.3 

SID58

–

CMOS Input

–

V_DDD

0.7 

[5]

SID241

SID242

–

V_DDD

0.3 

–

V_DDD

SID243

SID244

SID59

V_IH

V_IL

LVTTL input, V_DDD 2.7 V

Output voltage high level

2.0

–

0.8

–

V_OH

V_DDD–0.6

I_OH= 4 mA at 3 V V_DDD

I_OH= 1 mA at 1.8 V

V_DDD

SID60

SID61

SID62

V_OH

Output voltage high level

Output voltage low level

V_DDD–0.5

–

I_OL= 4 mA at 1.8 V

V_DDD

V_OL

–

0.6

I_OL= 10 mA at 3 V

V_DDD

SID62A

SID63

V_OL

Output voltage low level

Pull-up resistor

–

3.5

–

5.6

–

0.4

8.5

–

I_OL= 3 mA at 3 V V_DDD

R_PULLUP

–40°C  T_A 125°C

SID63A

SID64

Pull-up resistor

kΩ 125°C  T_A 150°C

–40°C  T_A 125°C

125°C  T_A 150°C

R_PULLDOWNPull-down resistor

3.5

5.6

–

8.5

–

SID64A

Input leakage current

SID65

I_IL

–

nA 25°C, V_DDD= 3.0 V

(absolute value)

SID66

C_IN

Input capacitance

–

_DDD 2.7 V, –40°C 

SID67^[6]V_HYSTTL

SID67A^[6]V_HYSTTL

SID68^[6]V_HYSCMOS

Input hysteresis LVTTL

Input hysteresis CMOS

–

T_A 125°C

7.5

–

125°C  T_A 150°C

0.05 ×

V_DDD

–

V_DD< 4.5 V

SID68A^[6]V_HYSCMOS5V5Input hysteresis CMOS

200

–

V_DD> 4.5 V

–

Current through protection

SID69^[6]I_DIODE

–

100

µA

diode to V_DD/V_SS

Maximum total source or sink

SID69A^[6]I_{TOT_GPIO}

–

200

chip current

Notes

5. V_IHmust not exceed V_DDD+ 0.2 V.

6. Guaranteed by characterization.

Datasheet

002-15106 Rev. *J

2023-02-21

r e s t r i c t e d

Automotive PSoC™ 4: PSoC™ 4100S family

Based on Arm® Cortex®-M0+ CPU

Electrical specifications

Table 7

GPIO AC Specifications

(Guaranteed by Characterization)

Spec ID Parameter Description

Min Typ Max Unit Details/conditions

Rise time in fast strong

mode

Rise time in fast strong

mode

Fall time in fast strong

mode

Fall time in fast strong

mode

Rise time in slow strong

mode

Rise time in slow strong

mode

Fall time in slow strong

mode

Fall time in slow strong

mode

3.3 V V_DDD, Cload = 25 pF, –40°C 

T_A 125°C

3.3 V V_DDD, Cload = 25 pF, 125°C 

T_A150°C

3.3 V V_DDD, Cload = 25 pF, –40°C 

T_A 125°C

3.3 V V_DDD, Cload = 25 pF, 125°C 

T_A150°C

3.3 V V_DDD, Cload = 25 pF, –4°C  T_A

 125°C

3.3 V V_DDD, Cload = 25 pF, 125°C 

T_A150°C

3.3 V V_DDD, Cload = 25 pF, –40°C 

T_A 125°C

3.3 V V_DDD, Cload = 25 pF, 125°C 

T_A150°C

SID70

SID70A T_RISEF

SID71 T_FALLF

SID71A T_FALLF

SID72 T_RISES

SID72A T_RISES

SID73 T_FALLS

SID73A T_FALLS

T_RISEF

–

130

–

130

GPIO F_OUT; 3.3 V  V_DDD

5.5 V

90/10%, 25-pF load, 60/40 duty

cycle

SID74

SID75

SID76

F_GPIOUT1

–

16.7

Fast strong mode

GPIO F_OUT; 1.71 VV_DDD

3.3 V

Fast strong mode

GPIO F_OUT; 3.3 V V_DDD

5.5 V

Slow strong mode

GPIO F_OUT; 1.71 V V_DDD

3.3 V

Slow strong mode.

GPIO input operating

frequency;

1.71 V V_DDD5.5 V

90/10%, 25-pF load, 60/40 duty

cycle

F_GPIOUT2

90/10%, 25-pF load, 60/40 duty

cycle

F_GPIOUT3

MHz

90/10%, 25-pF load, 60/40 duty

cycle

SID245 F_GPIOUT4

SID246 F_GPIOIN

3.5

90/10% V_IO

Datasheet

002-15106 Rev. *J

2023-02-21

r e s t r i c t e d

Automotive PSoC™ 4: PSoC™ 4100S family

Based on Arm® Cortex®-M0+ CPU

Electrical specifications

5.2.4

XRES

Table 8

XRES DC specifications

Spec ID Parameter Description

Min

Typ Max Unit Details/conditions

0.7 ×

V_DDD

SID77

SID78

V_IH

V_IL

Input voltage high threshold

Input voltage low threshold

–

CMOS Input

0.3 

V_DDD

–

SID79

SID80

R_PULLUP

C_IN

Pull-up resistor

Input capacitance

–

kΩ

–

Typical hysteresis is 200 mV

for V_DD> 4.5 V

–

SID81^[7]V_HYSXRES

Input voltage hysteresis

–

100

–

µA

Current through protection

diode to V_DD/V_SS

SID82

I_DIODE

100

Table 9

XRES AC specifications

Spec ID Parameter Description

Min

Typ

Max Unit Details/conditions

SID83^[7]T_RESETWIDTHReset pulse width

–

µs

–

Wake-up time from reset

BID194^[7]T_RESETWAKE

–

2.7

release

Note

7. Guaranteed by characterization.

Datasheet

002-15106 Rev. *J

2023-02-21

r e s t r i c t e d

Automotive PSoC™ 4: PSoC™ 4100S family

Based on Arm® Cortex®-M0+ CPU

Electrical specifications

5.3

Analog peripherals

5.3.1

CTBm opamp

Table 10

CTBm opamp specifications

Spec ID

Parameter

Description

Min Typ

Max

Unit Details/conditions

Opamp block current,

External load

I_DD

SID269

SID270

SID270A

SID271

SID271A

I_{DD_HI}

power = hi

–

1100

550

–

1850

950

–

I_{DD_MED}

I_{DD_LOW}

power = med

power = lo

–40°C  T_A 125°C

1075

350

µA

125°C  T_A150°C

–40°C  T_A 125°C

125°C  T_A15 °C

150

–

500

Load = 20 pF, 0.1 mA

V_DDA= 2.7 V

G_BW

Input and output are

0.2 V to V_DDA-0.2 V, –

40°C  T_A 125°C

SID272

SID272A

SID273

G_{BW_HI}

G_{BW_MED}

power = hi

power = med

4.5

–

125°C  T_A 150°C

Input and output are

0.2 V to V_DDA-0.2 V, –

40°C  T_A 125°C

MHz

SID273A

SID274

G_{BW_MED}

G_{BW_LO}

power = med

power = lo

–

125°C  T_A150°C

Input and output are

0.2 V to V_DDA-0.2 V

V_DDA= 2.7 V, 500 mV

from rail

I_{OUT_MAX}

Output is 0.5 V,

V_DDA-0.5 V

SID275

SID276

SID277

I_{OUT_MAX_HI}

power = hi

–

Output is 0.5 V,

V_DDA-0.5 V

I_{OUT_MAX_MID}power = mid

Output is 0.5 V,

V_DDA-0.5 V

I_{OUT_MAX_LO}

I_OUT

I_{OUT_MAX_HI}

I_{OUT_MAX_MID}

I_{OUT_MAX_LO}

I_{DD_Int}

power = lo

V_DDA= 1.71 V, 500 mV

from rail

Output is 0.5 V,

V_DDA-0.5 V

SID278

SID279

SID280

power = hi

–

Output is 0.5 V,

V_DDA-0.5 V

power = mid

Output is 0.5 V,

V_DDA-0.5 V

–

power = lo

Opamp block current

Internal Load

Datasheet

002-15106 Rev. *J

2023-02-21

r e s t r i c t e d

Automotive PSoC™ 4: PSoC™ 4100S family

Based on Arm® Cortex®-M0+ CPU

Electrical specifications

Table 10

Spec ID

SID269_I

CTBm opamp specifications ^(continued)

Parameter

I_{DD_HI_Int}

I_{DD_MED_Int}

I_{DD_LOW_Int}

G_BW

Description

power = hi

Min Typ

Max

1700

900

–

Unit Details/conditions

–

1500

–

SID270_I

SID271_I

power = med

power = lo

700

µA

–

V_DDA= 2.7 V

Output is 0.25 V to

V_DDA-0.25 V

–

G_{BW_HI_Int}

SID272_I

power = hi

MHz

General opamp specs

for both internal and

external modes

–

Charge-pump on, V_DDA

= 2.7 V

–

V_IN

V_DDA-0.2

SID281

SID282

–0.05

–

Charge-pump on, V_DDA

= 2.7 V

V_CM

V_OUT

V_{OUT_1}

V_DDA= 2.7 V

–

power = hi,

Iload = 10 mA

–

_DDA-0.5

SID283

SID284

SID285

SID286

0.5

0.2

power = hi,

Iload = 1 mA

V_{OUT_2}

V_{OUT_3}

V_{OUT_4}

V_DDA-0.2

–

power = med,

Iload = 1 mA

–

power = lo,

Iload = 0.1 mA

_DDA-0.2

1.0

High mode, input 0 V

to V_DDA-0.2 V,

Offset voltage,

trimmed

V_{OS_TR}

SID288

–1.0 0.5

–40°C  T_A 125°C

High mode, input 0 V

to V_DDA-0.2 V, 125°C 

Offset voltage,

trimmed

–1.3

–

1.3

V_{OS_TR}

SID288C

T_A 150°C

Medium mode, input

0 V to V_DDA-0.2 V

Offset voltage,

trimmed

–

V_{OS_TR}

SID288A

SID288B

1

Low mode, input 0 V

to V_DDA-0.2 V

Offset voltage,

trimmed

–

2

Datasheet

002-15106 Rev. *J

2023-02-21

r e s t r i c t e d

Automotive PSoC™ 4: PSoC™ 4100S family

Based on Arm® Cortex®-M0+ CPU

Electrical specifications

Table 10

Spec ID

CTBm opamp specifications ^(continued)

Parameter

Description

Min Typ

Max

Unit Details/conditions

High mode, –40°C  T_A

 125°C

Offset voltage drift,

trimmed

V_{OS_DR_TR}

SID290

–10

–15

–

3

–

High mode, 125°C  T_A

 150°C

Offset voltage drift,

trimmed

–

V_{OS_DR_TR}

SID290C

SID290A

SID290D

SID290B

SID290E

Medium mode, –40°C

 T_A 125°C

Offset voltage drift,

trimmed

10

15

10

15

µV/°C

Medium mode, 125°C

 T_A 150°C

Offset voltage drift,

trimmed

–

Low mode, –40°C  T_A

 125°C

Offset voltage drift,

trimmed

–

Low mode, 125°C  T_A

 150°C

Offset voltage drift,

trimmed

–

Input is 0 V to

V_DDA-0.2 V, Output is

–

SID291

SID292

CMRR

PSRR

0.2 V to V_DDA-0.2 V

V_DDD= 3.6 V,

high-power mode,

input is 0.2 V to

At 1 kHz, 10-mV ripple

V_DDA-0.2 V

Datasheet

002-15106 Rev. *J

2023-02-21

r e s t r i c t e d

Automotive PSoC™ 4: PSoC™ 4100S family

Based on Arm® Cortex®-M0+ CPU

Electrical specifications

Table 10

Spec ID

CTBm opamp specifications (continued)

Parameter

Description

Min Typ

Max

Unit Details/conditions

Noise

Input and output are

at 0.2 V to V_DDA-0.2 V

Input-referred, 1 kHz,

power = Hi

–

SID294

SID295

VN2

VN3

Input and output are

nV/rtHz at 0.2 V to V_DDA-0.2 V

Input-referred,10 kHz,

power = Hi

Input-referred,

100 kHz,

power = Hi

Input and output are

at 0.2 V to V_DDA-0.2 V

–

SID296

VN4

–

Stable up to max.

load. Performance

specs at 50 pF.

–

C_LOAD

SID297

SID298

125

–

Cload = 50 pF, Power =

High, V_DDA= 2.7 V

SLEW_RATE

V/µs

–

From disable to

T_OP_WAKE enable, no external RC

dominating

–

SID299

–

µs

–

SID299A

OL_GAIN

Open Loop Gain

Comparator mode;

50 mV drive, T_rise= T_fall

COMP_MODE

(approx.)

Input is 0.2 V to

Response time; power

= hi

–

SID300

SID301

TPD1

TPD2

150

500

V_DDA-0.2 V

Input is 0.2 V to

V_DDA-0.2 V

Response time; power

= med

Input is 0.2 V to

Response time; power

= lo

–

SID302

SID303

SID304

TPD3

2500

–

_DDA-0.2 V

VHYST_OP

WUP_CTB

Hysteresis

–

µs

Wake-up time from

Enabled to Usable

Mode 2 is lowest

current range. Mode 1

has higher GBW.

Deep Sleep

Mode

Datasheet

002-15106 Rev. *J

2023-02-21

r e s t r i c t e d

Automotive PSoC™ 4: PSoC™ 4100S family

Based on Arm® Cortex®-M0+ CPU

Electrical specifications

Table 10

Spec ID

CTBm opamp specifications ^(continued)

Parameter

Description

Min Typ

Max

Unit Details/conditions

–

I_{DD_HI_M1}

SID_DS_1

Mode 1, High current

1400

25°C

Mode 1, Medium

current

–

I_{DD_MED_M1}

SID_DS_2

700

25°C

–

I_{DD_LOW_M1}

I_{DD_HI_M2}

SID_DS_3

SID_DS_4

Mode 1, Low current

Mode 2, High current

200

25°C

µA

–

120

25°C

Mode 2, Medium

current

–

I_{DD_MED_M2}

I_{DD_LOW_M2}

SID_DS_5

SID_DS_6

25°C

–

Mode 2, Low current

20-pF load,

no DC load 0.2 V to

–

G_{BW_HI_M1}

SID_DS_7

SID_DS_8

SID_DS_9

SID_DS_10

SID_DS_11

SID_DS_12

Mode 1, High current

V_DDA-0.2 V

20-pF load,

no DC load 0.2 V to

Mode 1, Medium

current

–

G_{BW_MED_M1}

G_{BW_LOW_M1}

G_{BW_HI_M2}

V_DDA-0.2 V

20-pF load,

no DC load 0.2 V to

–

Mode 1, Low current

Mode 2, High current

0.5

V_DDA-0.2 V

MHz

20-pF load,

no DC load 0.2 V to

–

0.5

V_DDA-0.2 V

20-pF load,

no DC load 0.2 V to

Mode 2, Medium

current

–

G_{BW_MED_M2}

0.2

V_DDA-0.2 V

20-pF load,

no DC load 0.2 V to

–

G_{BW_Low_M2}

Mode 2, Low current

Mode 1, High current

0.1

V_DDA-0.2 V

With trim 25°C,

0.2 V to V_DDA-0.2 V

–

V_{OS_HI_M1}

SID_DS_13

SID_DS_14

SID_DS_15

SID_DS_16

SID_DS_17

SID_DS_18

With trim 25°C,

0.2 V to V_DDA-0.2 V

Mode 1, Medium

current

–

V_{OS_MED_M1}

V_{OS_LOW_M2}

V_{OS_HI_M2}

With trim 25°C,

0.2 V to V_DDA-0.2 V

–

Mode 1, Low current

Mode 2, High current

With trim 25°C,

0.2V to V_DDA-0.2 V

–

With trim 25°C,

0.2 V to V_DDA-0.2 V

Mode 2, Medium

current

–

V_{OS_MED_M2}

V_{OS_LOW_M2}

With trim 25°C,

0.2 V to V_DDA-0.2 V

–

Mode 2, Low current

Datasheet

002-15106 Rev. *J

2023-02-21

r e s t r i c t e d

Automotive PSoC™ 4: PSoC™ 4100S family

Based on Arm® Cortex®-M0+ CPU

Electrical specifications

Table 10

Spec ID

CTBm opamp specifications ^(continued)

Parameter

Description

Min Typ

Max

Unit Details/conditions

Output is 0.5 V to

–

I_{OUT_HI_M1}

SID_DS_19

SID_DS_20

Mode 1, High current

V_DDA-0.5 V

Output is 0.5 V to

Mode 1, Medium

current

–

I_{OUT_MED_M1}

V_DDA-0.5 V

Output is 0.5 V to

–

I_{OUT_LOW_M1}

I_{OUT_HI_M2}

I_{OU_MED_M2}

I_{OU_LOW_M2}

SID_DS_21

SID_DS_22

SID_DS_23

SID_DS_24

Mode 1, Low current

V_DDA-0.5 V

–

Mode 2, High current

–

Mode 2, Medium

current

–

Mode 2, Low current

0.5

Datasheet

002-15106 Rev. *J

2023-02-21

r e s t r i c t e d

Automotive PSoC™ 4: PSoC™ 4100S family

Based on Arm® Cortex®-M0+ CPU

Electrical specifications

5.3.2

Table 11

Comparator

Comparator DC specifications

Spec ID

Parameter Description

Details/conditions

Min Typ

Max

Unit

Input offset voltage, Factory

Normal mode, –40°C

SID84

V_OFFSET1

–

±15

–

±10

trim

 T_A 125°C

Input offset voltage, Factory

trim

Input offset voltage, Custom

trim

Input offset voltage, Custom

trim

125 °C  T_A150°C,

normal mode

SID84A

SID85

V_OFFSET1

–

±4

–

mV Low power mode, –

V_OFFSET2

40°C  T_A 125°C

125°C  T_A150°C,

low power mode

SID85A

V_OFFSET2

±4

SID86

SID86A

V_HYST

Hysteresis when enabled

–

–40°C  T_A 125°C

125°C  T_A150°C

Input common mode voltage

in normal mode

Input common mode voltage

in low power mode

Input common mode voltage

in ultra low power mode

Common mode rejection

ratio

Common mode rejection

ratio

Common mode rejection

ratio

SID87

V_ICM1

V_ICM2

V_ICM3

CMRR

–

V_DDD-0.1

Modes 1 and 2

SID247

SID247A

SID88

V_DDD

–

V_DDD≥ 2.2 V

at –40°C

V_DDD≥ 2.7 V, –40°C 

T_A 125°C

V_DDD≥ 2.7 V; 125°C 

T_A150°C

–

V_DDD-1.15

–

SID88B

SID88A

–

V_DDD≤ 2.7 V, –40°C 

T_A 125°C

Common mode rejection

ratio

Block current, normal mode

Block current, low power

mode

V_DDD≤ 2.7 V; 125°C 

T_A150°C

–

SID88C

SID89

CMRR

I_CMP1

I_CMP2

–

400

100

SID248

–

µA

Block current in ultra

low-power mode

DC Input impedance of

comparator

V_DDD≥ 2.2 V

SID259

SID90

I_CMP3

Z_CMP

–

at –40°C

–

MΩ

Table 12

Spec ID

Comparator AC specifications

Parameter Description

Response time, normal mode,

Min Typ

Max

110

200

Unit

Details/conditions

–

SID91

T_RESP1

50 mV overdrive

–

Response time, low power

mode, 50 mV overdrive

–

SID258

T_RESP2

µs

Response time, ultra-low

power mode, 200 mV

overdrive

SID92

T_RESP3

–

2.3

V_DDD≥ 2.2 V at –40°C

Datasheet

002-15106 Rev. *J

2023-02-21

r e s t r i c t e d

Automotive PSoC™ 4: PSoC™ 4100S family

Based on Arm® Cortex®-M0+ CPU

Electrical specifications

5.3.3

Temperature sensor

Table 13

Temperature sensor specifications

Spec ID Parameter

SID93 T_SENSACC

SID93A T_SENSACC

Description

Temperature sensor accuracy

Temperature sensor accuracy –15

Min

–5

Typ

±1

–

Max

+15

Unit Details/conditions

°C

–40°C to +85°C

–85°C to +150°C

5.3.4

Table 14

SAR ADC

SAR ADC DC specifications

Spec ID Parameter

Description

Min Typ

Max

Unit Details/conditions

SID94 A_RES

Resolution

–

bits

–

Number of channels - single

ended

SID95 A_CHNLS_S

–

8 full speed.

Number of channels - differ-

ential

Monotonicity

Diff inputs use neigh-

boring I/O

Yes.

With external

reference.

SID96 A-CHNKS_D

SID97 A-MONO

–

SID98 A_GAINERR Gain error

±0.1

Measured with 1-V

mV reference, –40°C  T_A

 125°C

SID99 A_OFFSET

Input offset voltage

–

SID99A A_OFFSET

SID100 A_ISAR

Input offset voltage

Current consumption

Input voltage range - single

ended

Input voltage range - differ-

ential

–

2.7

mV 125°C  T_A 150°C

–

SID101 A_VINS

SID102 A_VIND

V_SS

–

V_DDA

–

SID103 A_INRES

SID104 A_INCAP

Input resistance

Input capacitance

Trimmed internal reference to

SAR

–

2.2

KΩ

–

SID260 VREFSAR

–

TBD

Table 15

SAR ADC AC Specifications

Spec ID Parameter Description

Min Typ

Max

Unit Details/conditions

SID106 A_PSRR

SID107 A_CMRR

Power supply rejection ratio

–

Measured at 1 V, –40°C

 T_A 125°C

Common mode rejection ratio

–

SID107A A_CMRR

SID108 A_SAMP

SID108A A_SAMP

Common mode rejection ratio

Sample rate

–

dB 125°C  T_A 150°C

Msps –40°C  T_A 125°C

Msps 125°C  T_A 150°C

0.375

Signal-to-noise and distortion

ratio (SINAD)

Signal-to-noise and distortion

ratio (SINAD)

Input bandwidth without

aliasing

F_IN= 10 kHz, –40°C  T_A

SID109 A_SNR

SID109A A_SNR

SID110 A_BW

SID111 A_INL

–

 125°C

dB 125°C  T_A 150°C

A_samp/

–

kHz

Integral non linearity.

V_DD= 1.71 to 5.5, 1 Msps

V_REF= 1 to V_DD,–40°C 

T_A 125°C

–1.7

–

LSB

Datasheet

002-15106 Rev. *J

2023-02-21

r e s t r i c t e d

Automotive PSoC™ 4: PSoC™ 4100S family

Based on Arm® Cortex®-M0+ CPU

Electrical specifications

Table 15

SAR ADC AC Specifications ^(continued)

Spec ID Parameter Description

Min Typ

Max

Unit Details/conditions

Integral non linearity.

V_REF= 1.71 to V_DD,–

SID111A A_INL

SID111B A_INL

SID111C A_INL

SID111D A_INL

SID111E A_INL

SID112 A_DNL

SID112A A_DNL

SID112B A_DNL

SID112C A_DNL

SID112D A_DNL

–1.5

–4.5

–1

–

1.7

LSB

V_DDD= 1.71 to 3.6, 1 Msps

40°C  T_A 125°C

Integral non linearity.

V_DD= 1.71 to 5.5, 500 ksps

Integral non linearity. V_DD= 4.5

to 5.5 V, 375 ksps

Integral non linearity.

V_DD= 3 to 4.5 V, 300 ksps

Integral non linearity.

V_DD= 1.71 to 3 V, 150 ksps

Differential non linearity.

V_DD= 1.71 to 5.5, 1 Msps

Differential non linearity.

V_DD= 1.71 to 3.6, 1 Msps

Differential non linearity.

V_DD= 1.71 to 5.5, 500 ksps

Differential non linearity. V_DD

4.5 to 5.5V, 375 ksps

Differential non linearity. V_DD= 3

to 4.5 V, 300 ksps

Differential non linearity. V_DD

1.71 to 3 V, 150 ksps

V_REF= 1 to V_DD,–40°C 

T_A 125°C

V_REF= 1 to V_DD, 125°C 

T_A 150°C

V_REF= 1 to V_DD, 125°C 

T_A 150°C

V_REF= 1 to V_DD, 125°C 

T_A 150°C

V_REF= 1 to V_DD,–40°C 

T_A 125°C

V_REF= 1.71 to V_DD,–40

°C  T_A 125°C

V_REF= 1 to V_DD,–40°C 

T_A 125°C

V_REF= 1 to V_DD,125°C 

T_A 150°C

V_REF= 1 to V_DD,125°C 

T_A 150°C

V_REF= 1 to V_DD,125°C 

T_A 150°C

1.7

3.3

3.4

2.2

–1

2.2

3.2

–1

–

SID112E A_DNL

SID113 A_THD

SID113A A_THD

–1

–

3.3

–65

–

Total harmonic distortion

dB Fin = 10 kHz

Fin = 10 kHz, 125°C  T_A

 150°C

–

–65

Total harmonic distortion

SAR operating speed without

external reference bypass

–

SID261 FSAR_INTREF

100

ksps 12-bit resolution

5.3.5

Table 16

CSD and IDAC

CSD and IDAC specifications

Spec ID

Parameter

Description

Min Typ

Max

Unit Details/conditions

SYS.PER#3 V_{DD_RIPPLE}

V_DD> 2 V (with ripple),

mV 25°C T_A,

Max allowed ripple on

power supply, DC to 10 MHz

–

±50

Sensitivity = 0.1 pF

SYS.PER#16 V_{DD_RIPPLE_1.8}

V_DD> 1.75 V (with

ripple), 25°C T_A,

Max allowed ripple on

power supply, DC to 10 MHz

–

±25

mV Parasitic Capacitance

(C_P) < 20 pF,

Sensitivity ≥ 0.4 pF

SID.CSD.BLK I_CSD

Maximum block

current for both IDACs

in dynamic

Maximum block current

–

4000

µA (switching) mode

including compar-

ators, buffer, and

reference generator.

Datasheet

002-15106 Rev. *J

2023-02-21

r e s t r i c t e d

Automotive PSoC™ 4: PSoC™ 4100S family

Based on Arm® Cortex®-M0+ CPU

Electrical specifications

Table 16

Spec ID

CSD and IDAC specifications ^(continued)

Parameter

Description

Min Typ

Max

Unit Details/conditions

SID.CSD#15 V_REF

Voltage reference for CSD

and Comparator

External Voltage reference

for CSD and Comparator

V_DDA- 0.06 or 4.4,

0.6

1.2 V_DDA- 0.6

V_DDA- 0.6

whichever is lower

SID.CSD#15A V_{REF_EXT}

V_DDA- 0.06 or 4.4,

whichever is lower

SID.CSD#16 IDAC1_IDD

SID.CSD#17 IDAC2_IDD

IDAC1 (7 bits) block current

IDAC2 (7 bits) block current

–

1750

–

µA

SID308

V_CSD

1.8 V ±5% or 1.8 V to

Voltage range of operation 1.71

–

5.5

5.5 V

SID308A

V_COMPIDAC

Voltage compliance range

of IDAC

V_DDA- 0.06 or 4.4,

whichever is lower

0.6

–

V_DDA–0.6

SID309

SID310

IDAC1_DNL

IDAC1_INL

DNL

–1

–3

–1

INL is ±5 LSB for

V_DDA< 2 V

INL

SID311

SID312

IDAC2_DNL

IDAC2_INL

DNL

LSB

INL is ±5 LSB for

INL

–3

–

V_DDA< 2 V, –40°C T_A

125 °C

SID312A

SID313

IDAC2_INL

SNR

125°C  T_A150°C

Capacitance range of

Ratio of counts of finger to

noise. Guaranteed by

characterization

5 to 35 pF, 0.1-pF

–

sensitivity. All use

cases. V_DDA> 2 V

SID314

IDAC1_CRT1

IDAC1_CRT2

IDAC1_CRT3

IDAC1_CRT12

IDAC1_CRT22

Output current of IDAC1 (7

bits) in low range

Output current of IDAC1(7

bits) in medium range

Output current of IDAC1(7

bits) in high range

Output current of IDAC1 (7

bits) in low range, 2X mode

4.2

275

–

5.2

LSB = 37.5-nA typ

SID314A

SID314B

SID314C

SID314D

LSB = 300-nA typ

LSB = 2.4-µA typ

330

10.5

LSB = 37.5-nA typ. 2X

µA output stage

Output current of IDAC1(7

bits) in medium range, 2X

mode

LSB = 300-nA typ. 2X

output stage

–

SID314E

SID315

IDAC1_CRT32

IDAC2_CRT1

Output current of IDAC1(7

bits) in high range, 2X mode

Output current of IDAC2 (7

bits) in low range

LSB = 2.4-µA typ.2X

output stage

540

4.2

–

660

5.2

LSB = 37.5-nA typ.

Datasheet

002-15106 Rev. *J

2023-02-21

r e s t r i c t e d

Automotive PSoC™ 4: PSoC™ 4100S family

Based on Arm® Cortex®-M0+ CPU

Electrical specifications

Table 16

CSD and IDAC specifications ^(continued)

Spec ID

Parameter

Description

Min Typ

Max

Unit Details/conditions

SID315A

IDAC2_CRT2

Output current of IDAC2 (7

bits) in medium range

Output current of IDAC2 (7

bits) in high range

Output current of IDAC2 (7

bits) in low range, 2X mode

Output current of IDAC2(7

bits) in medium range, 2X

mode

Output current of IDAC2(7

bits) in high range, 2X mode

Output current of IDAC in

8-bit mode in low range

Output current of IDAC in

8-bit mode in medium

range

Output current of IDAC in

8-bit mode in high range

275

–

LSB = 300-nA typ.

SID315B

SID315C

SID315D

IDAC2_CRT3

IDAC2_CRT12

IDAC2_CRT22

330

LSB = 2.4-µA typ.

LSB = 37.5-nA typ. 2X

output stage

10.5

LSB = 300-nA typ. 2X

output stage

–

µA

SID315E

SID315F

SID315G

IDAC2_CRT32

IDAC3_CRT13

IDAC3_CRT23

LSB = 2.4-µA typ. 2X

output stage

540

–

660

10.5

LSB = 37.5-nA typ

–

LSB = 300-nA typ

SID315H

SID320

IDAC3_CRT33

IDAC_OFFSET

540

660

LSB = 2.4-µA typ

Polarity set by Source

or Sink. Offset is 2

All zeros input

–

LSB

LSBs for 37.5 nA/LSB

mode

SID321

SID321A

SID322

IDAC_GAIN

IDAC_MIS-

MATCH1

IDAC_MIS-

MATCH2

IDAC_MIS-

MATCH3

IDAC_MIS-

Full-scale error less offset

Mismatch between IDAC1

and IDAC2 in Low mode

Mismatch between IDAC1

and IDAC2 in Medium mode

Mismatch between IDAC1

and IDAC2 in High mode

Mismatch between IDAC1

and IDAC2 in High mode

Settling time to 0.5 LSB for

8-bit IDAC

Settling time to 0.5 LSB for

7-bit IDAC

External modulator

capacitor

–

±10

±11

–40°C  T_A 125°C

125°C  T_A150°C

–

9.2

4.6

2.3

6.3

–

LSB = 37.5-nA typ.

LSB = 300-nA typ.

SID322A

SID322B

SID322C

SID323

SID324

SID325

LSB

LSB = 2.4 µA typ, –40°C

 T_A 125°C

–

125°C  T_A150°C

MATCH4

IDAC_SET8

Full-scale transition.

–

No external load.

µs

IDAC_SET7

CMOD

Full-scale transition.

–

No external load.

5-V rating, X7R or NP0

cap

2.2

Datasheet

002-15106 Rev. *J

2023-02-21

r e s t r i c t e d

Automotive PSoC™ 4: PSoC™ 4100S family

Based on Arm® Cortex®-M0+ CPU

Electrical specifications

5.3.6

10-bit CAPSENSE™ ADC

Table 17

10-bit CAPSENSE™ ADC specifications

Spec ID

Parameter

Description

Details/conditions

Min Typ Max Unit

Auto-zeroing is

bits required every milli-

second

SIDA94

A_RES

Resolution

–

Number of channels - single

ended

Monotonicity

SIDA95

SIDA97

A_CHNLS_S

A-MONO

–

Defined by AMUX Bus.

Yes

–

In V_REF(2.4 V) mode

with V_DDAbypass

capacitance of 10 µF

SIDA98

SIDA99

A_GAINERR

A_OFFSET

Gain error

–

±2

In V_REF(2.4 V) mode

Input offset voltage

mV with V_DDAbypass

capacitance of 10 µF

SIDA100

SIDA101

A_ISAR

A_VINS

Current consumption

Input voltage range - single

ended

–

0.25

–

V_SSA

V_DDA

SIDA103

SIDA104

A_INRES

A_INCAP

Input resistance

Input capacitance

–

2.2

–

KΩ

–

In V_REF(2.4 V) mode

Power supply rejection

ratio

SIDA106

SIDA107

A_PSRR

A_TACQ

–

dB with V_DDAbypass

capacitance of 10 µF

µs

Sample acquisition time

–

Does not include

acquisition time.

Conversion time for 8-bit

resolution at conversion

rate = Fhclk/(2^(N+2)).

Clock frequency = 48 MHz.

SIDA108

A_CONV8

–

21.3

µs Equivalent to

44.8 ksps including

acquisition time.

Does not include

acquisition time.

µs Equivalent to

11.6 ksps including

acquisition time.

Conversion time for 10-bit

resolution at conversion

rate = Fhclk/(2^(N+2)).

SIDA108A A_CONV10

–

85.3

–

Clock frequency = 48 MHz.

With 10-Hz input sine

Signal-to-noise and

Distortion ratio (SINAD)

wave, external 2.4-V

SIDA109

A_SND

reference, V_REF(2.4 V)

mode

Input bandwidth without

aliasing

Integral Non Linearity. 1

ksps

Differential Non Linearity. 1

ksps

SIDA110

SIDA111

SIDA112

A_BW

A_INL

A_DNL

–

22.4

kHz 8-bit resolution

LSB V_REF= 2.4 V or greater

–

LSB

Datasheet

002-15106 Rev. *J

2023-02-21

r e s t r i c t e d

Automotive PSoC™ 4: PSoC™ 4100S family

Based on Arm® Cortex®-M0+ CPU

Electrical specifications

5.4

Digital peripherals

5.4.1

Timer counter pulse-width modulator (TCPWM)

Table 18

TCPWM specifications

Spec ID

Parameter Description

Details/conditions

Min Typ Max Unit

Block current consumption at

All modes (TCPWM)

I_TCPWM1

SID.TCPWM.1

SID.TCPWM.2

SID.TCPWM.2A

SID.TCPWM.3

–

155

650

3 MHz

Block current consumption at

12 MHz

Block current consumption at

48 MHz

All modes (TCPWM)

I_TCPWM2

µA

I_TCPWM3

Fc max = CLK_SYS

Maximum = 48 MHz

TCPWM_FREQ

Operating frequency

MHz

For all trigger

events^[8]

TPWM_ENEXT

SID.TCPWM.4

Input trigger pulse width

2/Fc

–

Minimum possible

width of Overflow,

Underflow, and CC

(Counter equals

Compare value)

outputs

TPWM_EXT

SID.TCPWM.5

Output trigger pulse widths

2/Fc

–

Minimum time

between successive

counts

TC_RES

SID.TCPWM.5A

SID.TCPWM.5B

Resolution of counter

PWM resolution

1/Fc

–

Minimum pulse

width of PWM

Output

PWM_RES

Minimum pulse

width between

Quadrature phase

inputs

Q_RES

SID.TCPWM.5C

Quadrature inputs resolution 1/Fc

–

Note

8. Trigger events can be Stop, Start, Reload, Count, Capture, or Kill depending on which mode of operation is

selected.

Datasheet

002-15106 Rev. *J

2023-02-21

r e s t r i c t e d

Automotive PSoC™ 4: PSoC™ 4100S family

Based on Arm® Cortex®-M0+ CPU

Electrical specifications

5.4.2

Table 19

I²C

Fixed I²C DC specifications^[9]

Parameter Description

Spec ID

Min Typ Max Unit Details/conditions

SID149

I_I2C1

I_I2C2

I_I2C3

I_I2C4

Block current consumption at

–

100 kHz

SID150

SID151

Block current consumption at

400 kHz

135

310

1.4

µA

Block current consumption at 1

Mbps

I²C enabled in Deep Sleep mode

SID152

Table 20

Fixed I²C AC Specifications^[9]

Parameter Description

Spec ID

Min Typ Max Unit Details/conditions

Msps –

SID153

F_I2C1

Bit rate

–

5.4.3

Table 21

SPI

SPI DC Specifications^[10]

Spec ID

Parameter Description

Min Typ Max Unit Details/conditions

Block current consumption at

–

SID163

ISPI1

ISPI2

ISPI3

–

360

560

600

1 Mbps

Block current consumption at

4 Mbps

–

SID164

SID165

µA

Block current consumption at

8 Mbps

Table 22

SPI AC Specifications^[10]

Spec ID Parameter Description

Min

Typ

Max Unit Details/conditions

SPI Operating frequency

(Master; 6X Oversampling)

SID166

FSPI

–

MHz

Fixed SPI Master Mode AC Specifications

MOSI Valid after SClock driving

edge

MISO Valid before SClock

capturing edge

–

SID167

SID168

SID169

TDMO

TDSI

–

Full clock, late MISO

sampling

Referred to Slave

capturing edge

THMO

Previous MOSI data hold time

–

Note

9. Guaranteed by characterization.

Datasheet

002-15106 Rev. *J

2023-02-21

r e s t r i c t e d

Automotive PSoC™ 4: PSoC™ 4100S family

Based on Arm® Cortex®-M0+ CPU

Electrical specifications

Table 22

SPI AC Specifications^[10](continued)

Spec ID Parameter Description

Min

Typ

Max Unit Details/conditions

Fixed SPI Slave Mode AC Specifications

MOSI Valid before Sclock

Capturing edge

MISO Valid after Sclock driving

edge

MISO Valid after Sclock driving

edge in Ext. Clk mode

Previous MISO data hold time

SID170

SID171

TDMI

TDSO

–

42 +

3*Tcpu

T_CPU= 1/F_CPU

SID171A TDSO_EXT

SID172 THSO

SID172A TSSELSSCK

–

SSEL Valid to first SCK valid

edge

100

5.4.4

Table 23

UART

UART DC specifications^[11]

Spec ID Parameter Description

Min

Typ

Max Unit Details/conditions

Block current consumption at

100 Kbps

SID160

SID161

I_UART1

I_UART2

–

µA

–

Block current consumption at

1000 Kbps

–

312

Table 24

UART AC specifications^[11]

Spec ID Parameter Description

Min

–

Typ

–

Max Unit Details/conditions

Mbps –

SID162 F_UART

Bit rate

Note

10.Guaranteed by characterization.

Datasheet

002-15106 Rev. *J

2023-02-21

r e s t r i c t e d

Automotive PSoC™ 4: PSoC™ 4100S family

Based on Arm® Cortex®-M0+ CPU

Electrical specifications

5.4.5

Table 25

LCD

LCD Direct Drive DC specifications^[11]

Spec ID Parameter Description

Min

Typ

Max Unit Details/conditions

Operating current in low power

16  4 small segment

SID154 I_LCDLOW

SID155 C_LCDCAP

–

µA

mode

–

disp. at 50 Hz

LCD capacitance per

segment/common driver

500

5000

–

SID156 LCD_OFFSETLong-term segment offset

–

LCD system operating current

32 4 segments. 50 Hz.

25°C

SID157 I_LCDOP1

Vbias = 5 V

–

LCD system operating current

32 4 segments. 50 Hz.

25°C

SID158 I_LCDOP2

Vbias = 3.3 V

–

Table 26

Spec ID Parameter Description

LCD Direct Drive AC specifications^[11]

Min

Typ

Max Unit Details/conditions

150 Hz

SID159 F_LCD

LCD frame rate

–

Note

11.Guaranteed by characterization.

Datasheet

002-15106 Rev. *J

2023-02-21

r e s t r i c t e d

Automotive PSoC™ 4: PSoC™ 4100S family

Based on Arm® Cortex®-M0+ CPU

Electrical specifications

5.5

Memory

5.5.1

Table 27

Flash

Flash DC specifications

Spec ID

Parameter Description

Min

Typ

Max

Unit Details/conditions

SID173

V_PE

Erase and program voltage 1.71

–

5.5

–

Table 28

Spec ID

Flash AC Specifications

Parameter Description

Min

Typ

–

Max

Unit Details/conditions

Row (block) write time

(erase and program)

Row erase time

Row program time after

erase

Bulk erase time (64 KB)

Row (block) =

128 bytes

–

[12]

SID174

T_ROWWRITE

–

[12]

SID175

T_ROWERASE

T_ROWPROGRAM

–

[12]

SID176

–

[12]

SID178

T_BULKERASE

–

Total device program

time

–

[12]

SID180^[13]

SID181^[13]

T_DEVPROG

–

Seconds

F_END

Flash endurance

100 K

–

Cycles

–

Flash retention. T_A 55

°C, 100 K P/E cycles

Flash retention. T_A 85

°C, 10 K P/E cycles

SID182^{[13, 14]}F_RET

–

Years

–

SID182A^{[13, 14]}F_RET

–

Number of Wait states

at 48 MHz

Number of Wait states

at 24 MHz

CPU execution from

Flash

CPU execution from

Flash

SID256

SID257

TWS48

TWS24

–

Notes

12.It can take as much as 20 milliseconds to write to Flash. During this time the device should not be Reset, or

Flash operations will be interrupted and cannot be relied on to have completed. Reset sources include the

XRES pin, software resets, CPU lockup states and privilege violations, improper power supply levels, and

watchdogs. Make certain that these are not inadvertently activated.

13.Guaranteed by characterization.

14.Infineon provides a retention calculator to calculate the retention lifetime based on the customers' individual

temperature profiles for operation over the –40 °C to +150 °C ambient temperature range. For more

information, visit the Infineon community page.

Datasheet

002-15106 Rev. *J

2023-02-21

r e s t r i c t e d

Automotive PSoC™ 4: PSoC™ 4100S family

Based on Arm® Cortex®-M0+ CPU

Electrical specifications

5.6

System resources

5.6.1

Table 29

Power-on reset (POR)

Power-on reset (PRES)

Details/

Min

Typ

Max

Unit

Spec ID

Parameter

Description

conditions

On power-up &

power-down

SID.CLK#6 SR_POWER

Power supply slew rate

1^[15]

–

V/ms

SID185^[16]V_RISEIPOR

SID186^[16]V_FALLIPOR

Rising trip voltage

Falling trip voltage

0.80

0.70

–

1.5

1.4

–

Table 30

Spec ID

Brown-out detect (BOD) for V_CCD

Parameter Description

Min

Typ

Max

Unit Details/conditions

SID190^[16]V_FALLPPOR

BOD trip voltage in active and 1.48

sleep modes

–

1.62

–

SID192^[16]V_FALLDPSLPBOD trip voltage in Deep

Sleep

1.11

–

1.5

5.6.2

SWD interface

Table 31

SWD interface specifications

Spec ID

Parameter

Description

Min

Typ

Max

Unit Details/conditions

SWDCLK ≤ 1/3 CPU

SID213

SID214

F_SWDCLK1

3.3 V  V_DD 5.5 V

–

clock frequency

MHz

SWDCLK ≤ 1/3 CPU

clock frequency

–

F_SWDCLK2

1.71 V  V_DD 3.3 V

–

SID215^[17]T_SWDI_SETUP T = 1/f SWDCLK

SID216^[17]T_SWDI_HOLD T = 1/f SWDCLK

SID217^[17]T_SWDO_VALID T = 1/f SWDCLK

SID217A^[17]T_SWDO_HOLD T = 1/f SWDCLK

0.25*T

–

0.25*T

–

0.5*T

–

Notes

15.If minimum ramp rate cannot be met, XRES should be asserted during voltage ramp (1.5 V > V_DDD> 1.0 V for

ramp-down or until voltage is stable for ramp-up). Note that a glitch on the I2C bus could occur during

voltage ramp in this case.

16.Guaranteed by characterization.

Datasheet

002-15106 Rev. *J

2023-02-21

r e s t r i c t e d

Automotive PSoC™ 4: PSoC™ 4100S family

Based on Arm® Cortex®-M0+ CPU

Electrical specifications

5.6.3

Internal main oscillator

Table 32

IMO DC specifications

(Guaranteed by design)

Spec ID

Parameter

I_IMO1

Description

Min

Typ

Max

Unit Details/conditions

SID218

IMO operating current at

48 MHz

–

250

µA

–

SID219

I_IMO2

IMO operating current at

24 MHz

–

180

µA

–

Table 33

IMO AC specifications

Spec ID Parameter

SID223 F_IMOTOL1

Description

Min

Typ

Max

Unit Details/conditions

Frequency variation at 24,

32, and 48 MHz (trimmed)

–

±2

–40°C  T_A 125°C

125°C  T_A150°C

Frequency variation at 24,

32, and 48 MHz (trimmed)

SID223A F_IMOTOL1

–

±4

SID226

SID228

T_STARTIMO

IMO startup time

–

µs

–

T_JITRMSIMO2

RMS jitter at 24 MHz

145

5.6.4

Internal low-speed oscillator

Table 34

ILO DC specifications

(Guaranteed by Design)

Spec ID

Parameter

Description

Min

Typ

Max

Unit Details/conditions

µA

SID231^[17]I_ILO1

ILO operating current

–

0.3

1.05

–

Table 35

Spec ID

SID234^[17]T_STARTILO1

SID236^[17]T_ILODUTY

ILO AC specifications

Parameter

Description

Min

–

Typ

–

Max

Unit Details/conditions

ILO startup time

ILO duty cycle

–

SID237

F_ILOTRIM1

ILO frequency range

kHz

5.6.5

Watch crystal oscillator

Table 36

Watch crystal oscillator specifications

Spec ID Parameter Description

Min Typ

Max Unit Details/conditions

kHz

250 ppm With 20-ppm crystal

SID398

SID399

SID400

SID401

F_WCO

F_TOL

ESR

Crystal frequency

Frequency tolerance

Equivalent series resistance

Drive Level

–

32.768

–

kΩ

–

µW

Note

17.Guaranteed by characterization.

Datasheet

002-15106 Rev. *J

2023-02-21

r e s t r i c t e d

Automotive PSoC™ 4: PSoC™ 4100S family

Based on Arm® Cortex®-M0+ CPU

Electrical specifications

Table 36

Watch crystal oscillator specifications

Spec ID Parameter Description

Min Typ

Max Unit Details/conditions

SID402

SID403

SID404

SID405

T_START

C_L

Startup time

–

500

12.5

–

µA

–

Crystal load capacitance

Crystal shunt capacitance

C₀

1.35

–

I_WCO1

Operating current (high power

mode)

SID406

I_WCO2

Operating current (low power

mode)

–

µA

–

5.6.6

External clock

Table 37

External clock specifications

Spec ID Parameter Description

Min Typ Max Unit Details/conditions

SID305^[18]ExtClk_Freq

SID306^[18]ExtClk_Duty

External clock input frequency

Duty cycle; measured at V_DD/2

–

MHz

–

5.6.7

Block

Table 38

Block specs

Spec ID Parameter Description

Min Typ

Max

Unit Details/conditions

SID262^[18]T_CLKSWITCHSystem clock source switching

time

–

Periods –

5.6.8

PRGIO pass-through time

Table 39

PRGIO pass-through time (Delay in bypass mode)

Spec ID Parameter Description

Min Typ Max

1.6

Unit Details/conditions

Max. delay added by PRGIO in

SID252 PRG_BYPASS

–

bypass mode

Note

18.Guaranteed by characterization.

Datasheet

002-15106 Rev. *J

2023-02-21

Ordering information

Table 40 lists the marketing part numbers for the PSoC™ 4100S family.

Table 40 Ordering information

MPN

Features

Packages

Operating temperature

CY8C4124PVA-S412

CY8C4124LQA-S413

CY8C4124PVA-S422

CY8C4124LQA-S423

CY8C4124PVA-S432

CY8C4124LQA-S433

CY8C4125PVA-S412

CY8C4125LQA-S413

CY8C4125PVA-S422

CY8C4125LQA-S423

CY8C4125PVA-S432

CY8C4125LQA-S433

CY8C4146PVA-S422

CY8C4146LQA-S423

CY8C4146PVA-S432

CY8C4146LQA-S433

CY8C4124PVS-S412

CY8C4124LQS-S413

806 Ksps

1000 Ksps

Note

19. Alternate fab available.

Table 40

Ordering information (continued)

MPN

Features

Packages

Operating temperature

806 Ksps

CY8C4124PVS-S422

CY8C4124LQS-S423

CY8C4124PVS-S432

CY8C4124LQS-S433

CY8C4125PVS-S412

CY8C4125LQS-S413

CY8C4125PVS-S422

CY8C4125LQS-S423

CY8C4125PVS-S432

CY8C4125LQS-S433

CY8C4146PVS-S422

CY8C4146LQS-S423

CY8C4146PVS-S432

CY8C4146LQS-S433

CY8C4124PVE-S412

CY8C4124LQE-S413

806 Ksps

1000 Ksps

[19]

806 Ksps

CY8C4124PVE-S422

CY8C4124LQE-S423

CY8C4124PVE-S432

CY8C4124LQE-S433

CY8C4125PVE-S412

CY8C4125LQE-S413

Note

19. Alternate fab available.

Table 40

Ordering information (continued)

MPN

Features

Packages

Operating temperature

[19]

806 Ksps

1000 Ksps

CY8C4125PVE-S422

CY8C4125LQE-S423

CY8C4125PVE-S432

CY8C4125LQE-S433

CY8C4146PVE-S422

CY8C4146LQE-S423

CY8C4146PVE-S432

[19]

CY8C4146LQE-S433

Note

19. Alternate fab available.

r e s t r i c t e d

Automotive PSoC™ 4: PSoC™ 4100S family

Based on Arm® Cortex®-M0+ CPU

Ordering information

The nomenclature used in the preceding table is based on the following part numbering convention:

Field

Description

Values

Meaning

Cypress (an Infineon

company) Prefix

CY8C

Architecture

Family

PSoC™ 4

4000 family

24 MHz

48 MHz

16 KB

32 KB

64 KB

CPU speed

Flash capacity

Package code

QFN

SSOP

Automotive (AEC-Q100: –40°C to +85°C)

Automotive (AEC-Q100: –40 °C to +105 °C)

Automotive (AEC-Q100: –40°C to +125°C)

PSoC™ 4A-S1, PSoC™ 4A-S2

PSoC™ 4A-M

Temperature range

Silicon family

XYZ

Attributes code

000-999

Code of feature set in the specific family

The following is an example of a part number:

CY8C

XYZ

T = Tape and Reel

Attributes Code

Silicon Family

Temperature Range

Package Code

Flash Capacity

CPU Speed

Family within Architecture

Architecture

CYPRESS (an Infineon company)

Prefix

Example

4: PSoC 4

2: 4200 Family

4: 48 MHz

5: 32 KB

PV: SSOP

A, S, E: Automotive

Datasheet

002-15106 Rev. *J

2023-02-21

r e s t r i c t e d

Automotive PSoC™ 4: PSoC™ 4100S family

Based on Arm® Cortex®-M0+ CPU

Packaging information

The PSoC™ 4100S will be offered in 24-pin QFN, 28-pin SSOP, 40 pin QFN, and 48-pin QFN packages.

Table 41 provides the package dimensions and Infineon drawing numbers.

Table 41

Spec ID

Package list

Package

Description

Package drawing

002-16818

BID27

BID28

BID29

40-pin QFN

28-pin SSOP

24-pin QFN

6  6  0.6 mm height with 0.5-mm pitch

28LD SSOP 210 MILS O28.21

4.0  4.0  0.6 mm (Wettable flank)

51-85079

002-18982

Table 42

Package thermal characteristics

Parameter Description

Package

Conditions

For A-grade devices

For S-grade devices

For E-grade devices

For A-grade devices

For S-grade devices

For E-grade devices

Min

–40

–

Typ Max

Unit

°C

°C/Watt

–

105

125

100

120

140

–

Operating Ambient

temperature

Operating Junction

temperature

–

TJA

TJC

TJA

TJC

Package θ_JA

Package θ_JC

Package θ_JA

Package θ_JC

40-pin QFN

28-pin SSOP

–

66.58

46.28

–

Table 43

Solder reflow peak temperature

Package

All

Maximum peak temperature

Maximum time at peak temperature

260 °C

30 seconds

Table 44

Package moisture sensitivity level (MSL), IPC/JEDEC J-STD-020

Package

MSL

All

MSL 3

Datasheet

002-15106 Rev. *J

2023-02-21

r e s t r i c t e d

Automotive PSoC™ 4: PSoC™ 4100S family

Based on Arm® Cortex®-M0+ CPU

Packaging information

7.1

Package diagrams

002-16818 *B

40-pin QFN (6.0 × 6.0 × 0.6 mm) LD40A 4.6 × 4.6 mm E-Pad (Sawn) package outline

Figure 6

Datasheet

002-15106 Rev. *J

2023-02-21

r e s t r i c t e d

Automotive PSoC™ 4: PSoC™ 4100S family

Based on Arm® Cortex®-M0+ CPU

Packaging information

51-85079 *G

Figure 7

28-pin SSOP (210 Mils) package outline

Datasheet

002-15106 Rev. *J

2023-02-21

r e s t r i c t e d

Automotive PSoC™ 4: PSoC™ 4100S family

Based on Arm® Cortex®-M0+ CPU

Packaging information

002-18982 *A

Figure 8

24-pin QFN 4.0 x 4.0 x 0.6 mm package outline (wettable flank)

Datasheet

002-15106 Rev. *J

2023-02-21

r e s t r i c t e d

Automotive PSoC™ 4: PSoC™ 4100S family

Based on Arm® Cortex®-M0+ CPU

Acronyms

Table 45

Acronyms Used in this Document

Acronym

abus

ADC

Description

analog local bus

analog-to-digital converter

analog global

AMBA (advanced microcontroller bus architecture) high-performance bus, an Arm data

transfer bus

AHB

ALU

arithmetic logic unit

AMUXBUS

API

analog multiplexer bus

application programming interface

application program status register

advanced RISC machine, a CPU architecture

automatic thump mode

APSR

Arm®

ATM

bandwidth

CMRR

CPU

CRC

common-mode rejection ratio

central processing unit

cyclic redundancy check, an error-checking protocol

digital-to-analog converter, see also IDAC, VDAC

digital input/output, GPIO with only digital capabilities, no analog. See GPIO.

Dhrystone million instructions per second

direct memory access, see also TD

differential nonlinearity, see also INL

do not use

DAC

DIO

DMIPS

DMA

DNL

DNU

port write data registers

DSI

digital system interconnect

DWT

ECC

data watchpoint and trace

error correcting code

ECO

external crystal oscillator

EEPROM

EMI

electrically erasable programmable read-only memory

electromagnetic interference

external memory interface

EMIF

EOC

EOF

end of conversion

end of frame

EPSR

ESD

execution program status register

electrostatic discharge

ETM

FPB

embedded trace macrocell

flash patch and breakpoint

GPIO

HVI

general-purpose input/output, applies to a PSoC™ pin

high-voltage interrupt, see also LVI, LVD

Datasheet

002-15106 Rev. *J

2023-02-21

r e s t r i c t e d

Automotive PSoC™ 4: PSoC™ 4100S family

Based on Arm® Cortex®-M0+ CPU

Acronyms

Table 45

Acronyms Used in this Document ^(continued)

Acronym

Description

integrated circuit

IDAC

current DAC, see also DAC, VDAC

integrated development environment

Inter-Integrated Circuit, a communications protocol

internal low-speed oscillator, see also IMO

internal main oscillator, see also ILO

integral nonlinearity, see also DNL

input/output, see also GPIO, DIO, SIO, USBIO

initial power-on reset

IDE

I²C, or IIC

ILO

IMO

INL

I/O

IPOR

IPSR

IRQ

interrupt program status register

interrupt request

ITM

instrumentation trace macrocell

liquid crystal display

LCD

LIN

Local Interconnect Network, a communications protocol.

link register

LUT

lookup table

LVD

low-voltage detect, see also LVI

low-voltage interrupt, see also HVI

low-voltage transistor-transistor logic

multiply-accumulate

LVI

LVTTL

MAC

MCU

MISO

microcontroller unit

master-in slave-out

no connect

NMI

nonmaskable interrupt

NRZ

NVIC

NVL

non-return-to-zero

nested vectored interrupt controller

nonvolatile latch, see also WOL

operational amplifier

opamp

program counter

PCB

PGA

PHUB

PHY

PICU

PLL

printed circuit board

programmable gain amplifier

peripheral hub

physical layer

port interrupt control unit

phase-locked loop

PMDD

POR

PRES

package material declaration data sheet

power-on reset

precise power-on reset

Datasheet

002-15106 Rev. *J

2023-02-21

r e s t r i c t e d

Automotive PSoC™ 4: PSoC™ 4100S family

Based on Arm® Cortex®-M0+ CPU

Acronyms

Table 45

Acronyms Used in this Document ^(continued)

Acronym

PRS

Description

pseudo random sequence

port read data register

PSoC™

PSRR

PWM

RAM

RISC

RMS

RTC

Programmable System-on-Chip

power supply rejection ratio

pulse-width modulator

random-access memory

reduced-instruction-set computing

root-mean-square

real-time clock

RTL

remote transmission request

receive

RTR

SAR

successive approximation register

switched capacitor/continuous time

I²C serial clock

SC/CT

SCL

SDA

S/H

I²C serial data

sample and hold

SINAD

SIO

signal to noise and distortion ratio

special input/output, GPIO with advanced features. See GPIO.

start of conversion

SOC

SOF

SPI

start of frame

Serial Peripheral Interface, a communications protocol

slew rate

SRAM

SRES

SWD

SWV

static random access memory

software reset

serial wire debug, a test protocol

single-wire viewer

transaction descriptor, see also DMA

total harmonic distortion

transimpedance amplifier

technical reference manual

transistor-transistor logic

transmit

THD

TIA

TRM

TTL

UART

UDB

USB

USBIO

VDAC

Universal Asynchronous Receiver-Transmitter, a communications protocol

universal digital block

Universal Serial Bus

USB input/output, PSoC™ pins used to connect to a USB port

voltage DAC, see also DAC, IDAC

Datasheet

002-15106 Rev. *J

2023-02-21

r e s t r i c t e d

Automotive PSoC™ 4: PSoC™ 4100S family

Based on Arm® Cortex®-M0+ CPU

Acronyms

Table 45

Acronyms Used in this Document ^(continued)

Acronym

WDT

Description

watchdog timer

WOL

write once latch, see also NVL

watchdog timer reset

external reset I/O pin

crystal

WRES

XRES

XTAL

Datasheet

002-15106 Rev. *J

2023-02-21

r e s t r i c t e d

Automotive PSoC™ 4: PSoC™ 4100S family

Based on Arm® Cortex®-M0+ CPU

Document conventions

9.1

Units of measure

Table 46

Units of measure

Symbol

°C

Unit of measure

degrees Celsius

decibel

femto farad

hertz

1024 bytes

kbps

Khr

kHz

k

ksps

LSB

Mbps

MHz

M

Msps

µA

kilobits per second

kilohour

kilohertz

kilo ohm

kilosamples per second

least significant bit

megabits per second

megahertz

mega-ohm

megasamples per second

microampere

microfarad

µF

µH

microhenry

microsecond

microvolt

µs

µV

µW

microwatt

milliampere

millisecond

millivolt

nanoampere

nanosecond

nanovolt



ohm

picofarad

ppm

parts per million

picosecond

second

sps

sqrtHz

samples per second

square root of hertz

volt

Datasheet

002-15106 Rev. *J

2023-02-21

r e s t r i c t e d

Automotive PSoC™ 4: PSoC™ 4100S family

Based on Arm® Cortex®-M0+ CPU

Revision history

Document

Date

Description of changes

revision

2016-07-18

New data sheet.

Updated Logic block diagram.

Updated Figure 1.

Updated Packaging information:

Updated Package diagrams:

Removed spec 001-80659 *A.

Added spec 002-16818 **.

2016-11-18

2017-02-06

Changed status from Advance to Preliminary.

Updated to new template.

Changed datasheet status to Final.

Added Note 1 for E-grade temperature range. Added new specs for the

device usage at 150C temperature range.

Added SID67A, SID277A, SID107A, SID108A, SID111C, SID111D, SID111E,

SID112C, SID112D, SID112E, SID113A

2017-05-30

2018-04-09

Removed SID93A

Updated max value for SID321A

Updated Note 1.

Updated DC specifications - Updated typ and max values for SID10, SID16,

SID19, SID22, SID25, SID28, SID28A, SID31, SID34, SID37, and SID307.

Added Note 3 under Device-level specifications.

Updated Ordering information.

Added Errata.

2018- 05-23

2019-04-24

2020-05-04

Updated SID64A, SID113, and SID113A specs.

Removed Errata.

Updated Ordering information.

Updated and Copyright year.

Updated SID.CLK#6 parameter.

2020-09-29

2021-12-01

2023-02-21

Updated conditions for Device-level specifications.

Refer to Product Information Notice #6965423.

Updated GPIO count.

Updated Pinouts.

Updated max values for SID31, SID34, and SID37.

Added footnote for SID.CLK#6.

Updated Ordering information and Packaging information.

Converted to Infineon template.

Updated Ordering information

Changed Cypress references to Infineon.

Removed package diagram 002-23807.

Datasheet

002-15106 Rev. *J

2023-02-21

Please read the Important Notice and Warnings at the end of this document

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IMPORTANT NOTICE

WARNINGS

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Edition 2023-02-21

Published by

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characteristics (“Beschaffenheitsgarantie”).

in question please contact your nearest Infineon

Technologies office.

With respect to any examples, hints or any typical

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Technologies hereby disclaims any and all authorized

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product information given in this document with

respect to such application.

Document reference

002-15106 Rev. *J

CY8C4124LQS-S433T [INFINEON]

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