CY8C4125AZI-S413T_技术文档

CY8C41xx

PSoC™ 4 MCU: PSoC™ 4100S

Based on Arm® Cortex®-M0+ CPU

General description

PSoC™ 4 is a scalable and reconfigurable platform architecture for a family of programmable embedded system

controllers with an Arm® Cortex®-M0+ CPU. It combines programmable and reconfigurable analog and digital

blocks with flexible automatic routing. The PSoC™ 4100S product family is a member of the PSoC™ 4 platform

architecture. It is a combination of a microcontroller with standard communication and timing peripherals, a

capacitive touch-sensing system (CAPSENSE™) with best-in-class performance, programmable general-purpose

continuous-time and switched-capacitor analog blocks, and programmable connectivity. PSoC™ 4100S products

are upward compatible with members of the PSoC™ 4 platform for new applications and design needs.

Features

• 32-bit MCU subsystem

- 48-MHz Arm® Cortex®-M0+ CPU with single-cycle multiply

- Up to 64 KB of flash with read accelerator

- Up to 8 KB of SRAM

• Programmable analog

- Two opamps with reconfigurable high-drive external and high-bandwidth internal drive and Comparator

modes and ADC input buffering capability. Opamps can operate in deep sleep low-power mode.

- 12-bit 1-Msps SAR ADC with differential and single-ended modes, and channel sequencer with signal averaging

- Single-slope 10-bit ADC function provided by a capacitance sensing block

- Two current DACs (IDACs) for general-purpose or capacitive sensing applications on any pin

- Two low-power comparators that operate in Deep Sleep low-power mode

• Programmable digital

- Programmable logic blocks allowing boolean operations to be performed on port inputs and outputs

• Low-power 1.71-V to 5.5-V operation

- Deep Sleep mode with operational analog and 2.5-µA digital system current

• Capacitive sensing

- Capacitive sigma-delta provides best-in-class signal-to-noise ratio (SNR) (>5:1) and water tolerance

- Infineon-supplied software component makes capacitive sensing design easy

- Automatic hardware tuning (SmartSense)

• LCD drive capability

- LCD segment drive capability on GPIOs

• Serial communication

- Three independent run-time reconfigurable Serial Communication Blocks (SCBs) with re-configurable I²C,

SPI, or UART functionality

• Timing and pulse-width modulation

- Five 16-bit Timer/Counter/Pulse-width Modulator (TCPWM) blocks

- Center-aligned, edge, and pseudo-random modes

- Comparator-based triggering of kill signals for motor drive and other high-reliability digital logic applications

- Quadrature decoder

Datasheet

www.infineon.com

Please read the Important Notice and Warnings at the end of this document

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PSoC™ 4 MCU: PSoC™ 4100S

Based on Arm® Cortex®-M0+ CPU

Features

• Up to 36 programmable GPIO pins

- 48-pin TQFP, 44-pin TQFP, 40-pin QFN, 32-pin QFN, and 35-ball WLCSP packages

- Any GPIO pin can be CAPSENSE™, analog, or digital

- Drive modes, strengths, and slew rates are programmable

• Clock sources

- 32-kHz watch crystal oscillator (WCO)

- ±2% internal main oscillator (IMO)

- 32-kHz internal low-power oscillator (ILO)

• ModusToolbox™ software

- Comprehensive collection of multi-platform tools and software libraries

- Includes board support packages (BSPs), peripheral driver library (PDL), and middleware such as CAPSENSE™

• PSoC™ Creator design environment

- Integrated development environment (IDE) provides schematic design entry and build, with analog and digital

automatic routing

- Application programming interface (API) components for all fixed-function and programmable peripherals

• Industry-standard tool compatibility

- After schematic entry, development can be done with Arm®-based industry-standard development tools

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PSoC™ 4 MCU: PSoC™ 4100S

Based on Arm® Cortex®-M0+ CPU

Table of contents

General description ...........................................................................................................................1

Features ...........................................................................................................................................1

Table of contents...............................................................................................................................3

1 Development ecosystem .................................................................................................................4

1.1 PSoC™ 4 MCU resources .........................................................................................................................................4

1.2 ModusToolbox™ software ......................................................................................................................................5

1.3 PSoC™ Creator ........................................................................................................................................................6

Block diagram...................................................................................................................................7

2 Functional definition.......................................................................................................................9

2.1 CPU and memory subsystem .................................................................................................................................9

2.2 System resources....................................................................................................................................................9

2.3 Analog blocks ........................................................................................................................................................11

2.4 Programmable digital blocks...............................................................................................................................12

2.5 Fixed function digital ............................................................................................................................................12

2.6 GPIO.......................................................................................................................................................................13

2.7 Special function peripherals ................................................................................................................................14

3 Pinouts ........................................................................................................................................15

3.1 Alternate pin functions .........................................................................................................................................17

4 Power ..........................................................................................................................................19

4.1 Mode 1: 1.8 V to 5.5 V external supply..................................................................................................................19

4.2 Mode 2: 1.8 V ± 5% external supply ......................................................................................................................20

5 Electrical specifications.................................................................................................................21

5.1 Absolute maximum ratings ..................................................................................................................................21

5.2 Device level specifications....................................................................................................................................22

5.3 Analog peripherals................................................................................................................................................27

5.4 Digital peripherals.................................................................................................................................................37

5.5 Memory..................................................................................................................................................................41

5.6 System resources..................................................................................................................................................42

6 Ordering information ....................................................................................................................46

7 Packaging ....................................................................................................................................49

7.1 Package diagrams.................................................................................................................................................50

8 Acronyms.....................................................................................................................................54

9 Document conventions..................................................................................................................58

9.1 Units of measure ...................................................................................................................................................58

Revision history ..............................................................................................................................59

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PSoC™ 4 MCU: PSoC™ 4100S

Based on Arm® Cortex®-M0+ CPU

Development ecosystem

1

Development ecosystem

1.1

PSoC™ 4 MCU resources

Infineon provides a wealth of data at www.cypress.com to help you select the right PSoC™ device and quickly

and effectively integrate it into your design. The following is an abbreviated, hyperlinked list of resources for

PSoC™ 4 MCU:

• Overview: PSoC™ Portfolio, PSoC™ Roadmap

• Product selectors: PSoC™ 4 MCU

• Application notes cover a broad range of topics, from basic to advanced level, and include the following:

- AN79953: Getting Started With PSoC™ 4. This application note has a convenient flow chart to help decide

which IDE to use: ModusToolbox™ software or PSoC™ Creator.

- AN91184: PSoC™ 4 BLE - Designing BLE applications

- AN88619: PSoC™ 4 hardware design considerations

- AN73854: Introduction to bootloaders

- AN89610: Arm® Cortex® code optimization

- AN86233: PSoC™ 4 MCU power reduction techniques

- AN57821: Mixed signal circuit board layout

- AN85951: PSoC™ 4, PSoC™ 6 CAPSENSE™ design guide

• Code examples demonstrate product features and usage, and are also available on Infineon GitHub

repositories.

• Technical Reference Manuals (TRMs) provide detailed descriptions of PSoC™ 4 MCU architecture and registers.

• PSoC 4 MCU programming specification provides the information necessary to program PSoC™ 4 MCU

non-volatile memory.

• Development tools

- ModusToolbox™ software enables cross platform code development with a robust suite of tools and software

libraries.

- PSoC™ Creator is a free Windows-based IDE. It enables concurrent hardware and firmware design of PSoC™

3, PSoC™ 4, PSoC™ 5LP, and PSoC™ 6 MCU based systems. Applications are created using schematic capture

and over 150 pre-verified, production-ready peripheral components.

- CY8CKIT-041-41XX PSoC™ 4100S CAPSENSE™ pioneer kit, is an easy-to-use and inexpensive development

platform. This kit includes connectors for Arduino™ compatible shields.

- MiniProg4 and MiniProg3 all-in-one development programmers and debuggers.

- PSoC™ 4 MCU CAD libraries provide footprint and schematic support for common tools. IBIS models are also

available.

• Training Videos are available on a wide range of topics including the PSoC™ 4 MCU 101 series.

• Infineon developer community enables connection with fellow PSoC™ developers around the world, 24 hours

a day, 7 days a week, and hosts a dedicated PSoC™ 4 MCU community.

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PSoC™ 4 MCU: PSoC™ 4100S

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Development ecosystem

1.2

ModusToolbox™ software

ModusToolbox™ software is Infineon’ comprehensive collection of multi-platform tools and software libraries

that enable an immersive development experience for creating converged MCU and wireless systems. It is:

• Comprehensive - it has the resources you need

• Flexible - you can use the resources in your own workflow

• Atomic - you can get just the resources you want

Infineon provides a large collection of code repositories on GitHub, including:

• Board support packages (BSPs) aligned with Infineon kits

• Low-level resources, including a peripheral driver library (PDL)

• Middleware enabling industry-leading features such as CAPSENSE™

• An extensive set of thoroughly tested code example applications

ModusToolbox™ software is IDE-neutral and easily adaptable to your workflow and preferred development

environment. It includes a project creator, peripheral and library configurators, a library manager, as well as the

optional Eclipse IDE for ModusToolbox™, as Figure 1 shows. For information on using Infineon tools, refer to the

documentation delivered with ModusToolbox™ software, and AN79953: Getting Started with PSoC™ 4.

Figure 1

ModusToolbox™ software tools

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PSoC™ 4 MCU: PSoC™ 4100S

Based on Arm® Cortex®-M0+ CPU

Development ecosystem

1.3

PSoC™ Creator

PSoC™ Creator is a free Windows-based IDE. It enables you to design hardware and firmware systems

concurrently, based on PSoC™ 4 MCU. As Figure 2 shows, with PSoC™ Creator you can:

1. Explore the library of 200+ components

2. Drag and drop component icons to complete your hardware system design in the main design workspace

3. Configure components using the component configuration tools and the component datasheets

4. Co-design your application firmware and hardware in the PSoC™ Creator IDE or build a project for a third-party

IDE

5. Prototype your solution with the PSoC™ 4 pioneer kits. If a design change is needed, PSoC™ Creator and

components enable you to make changes on-the-fly without the need for hardware revisions.

Figure 2

PSoC™ Creator schematic entry and components

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PSoC™ 4 MCU: PSoC™ 4100S

Based on Arm® Cortex®-M0+ CPU

Block diagram

CPU Subsystem

PSoC™ 4100S

Architecture

SWD/TC

SPCIF

Cortex® M0+

48 MHz

FLASH

64 KB

SRAM

16 KB

ROM

8 KB

32-bit

FAST MUL

NVIC, IRQMUX

AHB-Lite

SRAM Controller

Read Accelerator

ROM Controller

System Resources

Lite

System Interconnect (Single Layer AHB)

Peripheral Interconnect (MMIO)

Power

Sleep Control

WIC

Peripherals

PCLK

POR

REF

PWRSYS

Clock

Clock Control

WDT

Programmable

Analog

ILO

IMO

SAR ADC

( 12-bit)

Reset

Reset Control

XRES

Test

TestMode Entry

Digital DFT

Analog DFT

x1

SARMUX

CTBm

2 x Opamp

High Speed I/O Matrix, 2X Smart I/O Ports

36x GPIOs, LCD

Power Modes

Active/Sleep

DeepSleep

I/O Subsystem

PSoC™ 4100S devices include extensive support for programming, testing, debugging, and tracing both hardware

and firmware.

The Arm® serial-wire debug (SWD) interface supports all programming and debug features of the device.

Complete debug-on-chip functionality enables full-device debugging in the final system using the standard

production device. It does not require special interfaces, debugging pods, simulators, or emulators. Only the

standard programming connections are required to fully support debug.

The PSoC™ Creator IDE provides fully integrated programming and debug support for the PSoC™ 4100S devices.

The SWD interface is fully compatible with industry-standard third-party tools. The PSoC™ 4100S provides a level

of security not possible with multi-chip application solutions or with microcontrollers.

It has the following advantages:

• Allows disabling of debug features

• Robust flash protection

• Allows customer-proprietary functionality to be implemented in on-chip programmable blocks

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PSoC™ 4 MCU: PSoC™ 4100S

Based on Arm® Cortex®-M0+ CPU

Block diagram

The debug circuits are enabled by default and can be disabled in firmware. If they are not enabled, the only way

to re-enable them is to erase the entire device, clear flash protection, and reprogram the device with new

firmware that enables debugging. Thus firmware control of debugging cannot be over-ridden without erasing the

firmware thus providing security.

Additionally, all device interfaces can be permanently disabled (device security) for applications concerned

about phishing attacks due to a maliciously reprogrammed device or attempts to defeat security by starting and

interrupting flash programming sequences. All programming, debug, and test interfaces are disabled when

maximum device security is enabled. Therefore, PSoC™ 4100S, with device security enabled, may not be returned

for failure analysis. This is a trade-off the PSoC™ 4100S allows the customer to make.

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PSoC™ 4 MCU: PSoC™ 4100S

Based on Arm® Cortex®-M0+ CPU

Functional definition

2

Functional definition

2.1

CPU and memory subsystem

2.1.1

CPU

The Cortex®-M0+ CPU in the PSoC™ 4100S is part of the 32-bit MCU subsystem, which is optimized for low-power

operation with extensive clock gating. Most instructions are 16 bits in length and the CPU executes a subset of

the thumb-2 instruction set. It includes a nested vectored interrupt controller (NVIC) block with eight interrupt

inputs and also includes a wakeup interrupt controller (WIC). The WIC can wake the processor from Deep Sleep

mode, allowing power to be switched off to the main processor when the chip is in Deep Sleep mode.

The CPU also includes a debug interface, the serial wire debug (SWD) interface, which is a two-wire form of JTAG.

The debug configuration used for PSoC™ 4100S has four breakpoint (address) comparators and two watchpoint

(data) comparators.

2.1.2

Flash

The PSoC™ 4100S device has a flash module with a flash accelerator, tightly coupled to the CPU to improve

average access times from the flash block. The low-power flash block is designed to deliver two wait-state (WS)

access time at 48 MHz. The flash accelerator delivers 85% of single-cycle SRAM access performance on average.

2.1.3

SRAM

Eight KB of SRAM are provided with zero wait-state access at 48 MHz.

2.1.4

SROM

An 8 KB supervisory ROM that contains boot and configuration routines is provided.

2.2

2.2.1

System resources

Power system

The power system is described in detail in the section “Power” on page 19. It provides assurance that voltage

levels are as required for each respective mode and either delays mode entry (for example, on power-on reset

(POR)) until voltage levels are as required for proper functionality, or generates resets (for example, on brown-out

detection). The PSoC™ 4100S operates with a single external supply over the range of either 1.8 V ± 5% (externally

regulated) or 1.8 to 5.5 V (internally regulated) and has three different power modes, transitions between which

are managed by the power system. The PSoC™ 4100S provides Active, Sleep, and Deep Sleep low-power modes.

All subsystems are operational in Active mode. The CPU subsystem (CPU, flash, and SRAM) is clock-gated off in

Sleep mode, while all peripherals and interrupts are active with instantaneous wake-up on a wake-up event. In

Deep Sleep mode, the high-speed clock and associated circuitry is switched off; wake-up from this mode takes

35 µs. The opamps can remain operational in Deep Sleep mode.

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Functional definition

2.2.2

Clock system

The PSoC™ 4100S clock system is responsible for providing clocks to all subsystems that require clocks and for

switching between different clock sources without glitching. In addition, the clock system ensures that there are

no metastable conditions.

The clock system for the PSoC™ 4100S consists of the internal main oscillator (IMO), internal low-frequency

oscillator (ILO), a 32 kHz watch crystal oscillator (WCO) and provision for an external clock. Clock dividers are

provided to generate clocks for peripherals on a fine-grained basis. Fractional dividers are also provided to

enable clocking of higher data rates for UARTs.

External Clock

HFCLK

IMO

Divide By

2,4,8

WDC0

16-bits

WCO

ILO

LFCLK

WDC1

16-bits

WDC2

32-bits

Watchdog Counters (WDC)

WDT

Watchdog Timer (WDT)

Prescaler

SYSCLK

HFCLK

Integer

Dividers

6X 16-bit

Fractional

Dividers

3X 16.5-bit

Figure 3

PSoC™ 4100S MCU clocking architecture

The HFCLK signal can be divided down to generate synchronous clocks for the analog and digital peripherals.

There are eight clock dividers for the PSoC™ 4100S; two of those are fractional dividers. The 16-bit capability

allows flexible generation of fine-grained frequency values and is fully supported in PSoC™ Creator.

2.2.3

IMO clock source

The IMO is the primary source of internal clocking in the PSoC™ 4100S. It is trimmed during testing to achieve the

specified accuracy.The IMO default frequency is 24 MHz and it can be adjusted from 24 to 48 MHz in steps of

4 MHz. The IMO tolerance with Infineon provided calibration settings is ±2%.

2.2.4

ILO clock source

The ILO is a very low power, nominally 40-kHz oscillator, which is primarily used to generate clocks for the

watchdog timer (WDT) and peripheral operation in Deep Sleep mode. ILO-driven counters can be calibrated to

the IMO to improve accuracy. Infineon provides a software component, which does the calibration.

2.2.5

Watch Crystal Oscillator (WCO)

The PSoC™ 4100S clock subsystem also implements a low-frequency (32-kHz watch crystal) oscillator that can

be used for precision timing applications. The WCO block allows locking the IMO to the 32-kHz oscillator.

2.2.6

Watchdog timer and counters

A watchdog timer is implemented in the clock block running from the ILO; this allows watchdog operation during

Deep Sleep and generates a watchdog reset if not serviced before the set timeout occurs. The watchdog reset is

recorded in a Reset Cause Register, which is firmware readable. The watchdog counters can be used to

implement a real-time clock using the 32-kHz WCO.

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Based on Arm® Cortex®-M0+ CPU

Functional definition

2.2.7

Reset

The PSoC™ 4100S can be reset from a variety of sources including a software reset. Reset events are asynchronous

and guarantee reversion to a known state. The reset cause is recorded in a register, which is sticky through reset

and allows software to determine the cause of the reset. An XRES pin is reserved for external reset by asserting it

active low. The XRES pin has an internal pull-up resistor that is always enabled.

2.3

Analog blocks

12-bit SAR ADC

2.3.1

The 12-bit, 1-Msps SAR ADC can operate at a maximum clock rate of 18 MHz and requires a minimum of 18 clocks

at that frequency to do a 12-bit conversion.

The sample-and-hold (S/H) aperture is programmable allowing the gain bandwidth requirements of the amplifier

driving the SAR inputs, which determine its settling time, to be relaxed if required. It is possible to provide an

external bypass (through a fixed pin location) for the internal reference amplifier.

The SAR is connected to a fixed set of pins through an 8-input sequencer. The sequencer cycles through selected

channels autonomously (sequencer scan) with zero switching overhead (that is, aggregate sampling bandwidth

is equal to 1 Msps whether it is for a single channel or distributed over several channels). The sequencer switching

is effected through a state machine or through firmware driven switching. A feature provided by the sequencer

is buffering of each channel to reduce CPU interrupt service requirements. To accommodate signals with varying

source impedance and frequency, it is possible to have different sample times programmable for each channel.

Also, signal range specification through a pair of range registers (low and high range values) is implemented with

a corresponding out-of-range interrupt if the digitized value exceeds the programmed range; this allows fast

detection of out-of-range values without the necessity of having to wait for a sequencer scan to be completed

and the CPU to read the values and check for out-of-range values in software.

The SAR is not available in Deep Sleep mode as it requires a high-speed clock (up to 18 MHz). The SAR operating

range is 1.71 V to 5.5 V.

AHB System Bus and Programmable Logic

Interconnect

SAR Sequencer

Sequencing

and Control

Data and

Status Flags

POS

SARADC

NEG

External

Reference and

Bypass

(optional )

Reference

Selection

VDDA

VREF

VDDA /2

Inputs from other Ports

Figure 4

SAR ADC

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Based on Arm® Cortex®-M0+ CPU

Functional definition

2.3.2

Two opamps (continuous-time block; CTB)

The PSoC™ 4100S has two opamps with Comparator modes which allow most common analog functions to be

performed on-chip eliminating external components; PGAs, Voltage Buffers, Filters, Trans-Impedance Amplifiers,

and other functions can be realized, in some cases with external passives. saving power, cost, and space. The

on-chip opamps are designed with enough bandwidth to drive the Sample-and-Hold circuit of the ADC without

requiring external buffering.

2.3.3

Low-power comparators (LPC)

The PSoC™ 4100S has a pair of low-power comparators, which can also operate in Deep Sleep modes. This allows

the analog system blocks to be disabled while retaining the ability to monitor external voltage levels during

low-power modes. The comparator outputs are normally synchronized to avoid metastability unless operating

in an asynchronous power mode where the system wake-up circuit is activated by a comparator switch event.

The LPC outputs can be routed to pins.

2.3.4

Current DACs

The PSoC™ 4100S has two IDACs, which can drive any of the pins on the chip. These IDACs have programmable

current ranges.

2.3.5

Analog multiplexed buses

The PSoC™ 4100S has two concentric independent buses that go around the periphery of the chip. These buses

(called amux buses) are connected to firmware-programmable analog switches that allow the chip’s internal

resources (IDACs, comparator) to connect to any pin on the I/O ports.

2.4

Programmable digital blocks

The smart I/O block is a fabric of switches and LUTs that allows boolean functions to be performed in signals

being routed to the pins of a GPIO port. The Smart I/O can perform logical operations on input pins to the chip

and on signals going out as outputs.

2.5

Fixed function digital

2.5.1

Timer/Counter/PWM (TCPWM) block

The TCPWM block consists of a 16-bit counter with user-programmable period length. There is a capture register

to record the count value at the time of an event (which may be an I/O event), a period register that is used to

either stop or auto-reload the counter when its count is equal to the period register, and compare registers to

generate compare value signals that are used as PWM duty cycle outputs. The block also provides true and

complementary outputs with programmable offset between them to allow use as dead-band programmable

complementary PWM outputs. It also has a kill input to force outputs to a predetermined state; for example, this

is used in motor drive systems when an over-current state is indicated and the PWM driving the FETs needs to be

shut off immediately with no time for software intervention. There are five TCPWM blocks in the PSoC™ 4100S.

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Functional definition

2.5.2

Serial Communication Block (SCB)

The PSoC™ 4100S has three serial communication blocks, which can be programmed to have SPI, I2C, or UART

functionality.

I²C Mode: The hardware I²C block implements a full multi-master and slave interface (it is capable of

multi-master arbitration). This block is capable of operating at speeds of up to 400 kbps (Fast Mode) and has

flexible buffering options to reduce interrupt overhead and latency for the CPU. It also supports EZI2C that

creates a mailbox address range in the memory of the PSoC™ 4100S and effectively reduces I²C communication

to reading from and writing to an array in memory. In addition, the block supports an 8-deep FIFO for receive and

transmit which, by increasing the time given for the CPU to read data, greatly reduces the need for clock

stretching caused by the CPU not having read data on time.

The I²C peripheral is compatible with the I²C Standard-mode and Fast-mode devices as defined in the NXP

I²C-bus specification and user manual (UM10204). The I²C bus I/O is implemented with GPIO in open-drain

modes.

The PSoC™ 4100S is not completely compliant with the I²C spec in the following respect:

• GPIO cells are not over-voltage tolerant and, therefore, cannot be hot-swapped or powered up independently

of the rest of the I²C system.

UART Mode: This is a full-feature UART operating at up to 1 Mbps. It supports automotive single-wire interface

(LIN), infrared interface (IrDA), and SmartCard (ISO7816) protocols, all of which are minor variants of the basic

UART protocol. In addition, it supports the 9-bit multiprocessor mode that allows addressing of peripherals

connected over common RX and TX lines. Common UART functions such as parity error, break detect, and frame

error are supported. An 8-deep FIFO allows much greater CPU service latencies to be tolerated.

SPI Mode: The SPI mode supports full Motorola SPI, TI SSP (adds a start pulse used to synchronize SPI Codecs),

and National Microwire (half-duplex form of SPI). The SPI block can use the FIFO.

2.6

GPIO

The PSoC™ 4100S has up to 36 GPIOs. The GPIO block implements the following:

• Eight drive modes:

- Analog input mode (input and output buffers disabled)

- Input only

- Weak pull-up with strong pull-down

- Strong pull-up with weak pull-down

- Open drain with strong pull-down

- Open drain with strong pull-up

- Strong pull-up with strong pull-down

- Weak pull-up with weak pull-down

• Input threshold select (CMOS or LVTTL).

• Individual control of input and output buffer enabling/disabling in addition to the drive strength modes

• Selectable slew rates for dV/dt related noise control to improve EMI

The pins are organized in logical entities called ports, which are 8-bit in width (less for ports 2 and 3). During

power-on and reset, the blocks are forced to the disable state so as not to crowbar any inputs and/or cause excess

turn-on current. A multiplexing network known as a high-speed I/O matrix is used to multiplex between various

signals that may connect to an I/O pin.

Data output and pin state registers store, respectively, the values to be driven on the pins and the states of the

pins themselves.

Every I/O pin can generate an interrupt if so enabled and each I/O port has an interrupt request (IRQ) and interrupt

service routine (ISR) vector associated with it (5 for PSoC™ 4100S).

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PSoC™ 4 MCU: PSoC™ 4100S

Based on Arm® Cortex®-M0+ CPU

Functional definition

2.7

2.7.1

Special function peripherals

CAPSENSE™

CAPSENSE™ is supported in the PSoC™ 4100S through a CAPSENSE™ Sigma-Delta (CSD) block that can be

connected to any pins through an analog multiplex bus via analog switches. CAPSENSE™ function can thus be

provided on any available pin or group of pins in a system under software control. A PSoC™ Creator component

is provided for the CAPSENSE™ block to make it easy for the user.

Shield voltage can be driven on another analog multiplex bus to provide water-tolerance capability. Water

tolerance is provided by driving the shield electrode in phase with the sense electrode to keep the shield

capacitance from attenuating the sensed input. Proximity sensing can also be implemented.

The CAPSENSE™ block has two IDACs, which can be used for general purposes if CAPSENSE™ is not being used

(both IDACs are available in that case) or if CAPSENSE™ is used without water tolerance (one IDAC is available).

The CAPSENSE™ block also provides a 10-bit slope ADC function which can be used in conjunction with the

CAPSENSE™ function.

The CAPSENSE™ block is an advanced, low-noise, programmable block with programmable voltage references

and current source ranges for improved sensitivity and flexibility. It can also use an external reference voltage. It

has a full-wave CSD mode that alternates sensing to VDDA and ground to null out power-supply related noise.

2.7.2

LCD segment drive

The PSoC™ 4100S has an LCD controller, which can drive up to 4 commons and up to 32 segments. It uses full

digital methods to drive the LCD segments requiring no generation of internal LCD voltages. The two methods

used are referred to as digital correlation and PWM. Digital correlation pertains to modulating the frequency and

drive levels of the common and segment signals to generate the highest RMS voltage across a segment to light it

up or to keep the RMS signal to zero. This method is good for STN displays but may result in reduced contrast

with TN (cheaper) displays. PWM pertains to driving the panel with PWM signals to effectively use the capacitance

of the panel to provide the integration of the modulated pulse-width to generate the desired LCD voltage. This

method results in higher power consumption but can result in better results when driving TN displays. LCD

operation is supported during Deep Sleep refreshing a small display buffer (4 bits; 1 32-bit register per port).

Datasheet

14

002-00122 Rev. *P

2023-01-23

PSoC™ 4 MCU: PSoC™ 4100S

Based on Arm® Cortex®-M0+ CPU

Pinouts

3

Pinouts

Table 1 provides the pin list for PSoC™ 4100S for the 48-pin TQFP, 44-pin TQFP, 40-pin QFN, 32-pin QFN, and

35-ball CSP packages. All port pins support GPIO.

Table 1

48-pin TQFP

Name

Pin list

44-pin TQFP

Pin Name

40-pin QFN

32-pin QFN

35-ball CSP

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

1

Name

P0.0

P0.1

P0.2

P0.3

P0.4

P0.5

P0.6

P0.7

XRES

VCCD

VSSD

VDDD

VDDA

VSSA

P1.0

P1.1

P1.2

P1.3

P1.4

Name

P0.0

P0.1

P0.2

P0.3

P0.4

P0.5

P0.6

Name

P0.0

P0.1

P0.2

P0.3

P0.4

P0.5

P0.6

P0.7

XRES

VCCD

VSSD

VDDD

VDDA

VSSA

P1.0

P1.1

P1.2

P1.3

P1.4

24

25

26

27

28

29

30

31

32

33

P0.0

P0.1

P0.2

P0.3

P0.4

P0.5

P0.6

P0.7

XRES

VCCD

22

23

24

25

26

27

28

29

30

31

DN

32

33

34

35

36

37

38

39

17

18

19

20

21

22

23

C3

A5

A4

A3

B3

A6

B4

B5

B6

A7

B7

C7

B7

C4

C5

C6

D7

D4

D5

D6

E7

P0.1

P0.2

P0.3

P0.4

P0.5

P0.6

P0.7

XRES

VCCD

VSS

VDD

VSS

P1.0

P1.1

P1.2

24

25

26

XRES

VCCD

VSSD

34

35

36

37

38

39

40

41

42

43

44

1

VDDD

VDDA

VSSA

P1.0

P1.1

P1.2

P1.3

P1.4

P1.5

P1.6

27

28

29

30

31

32

VDD

VSSA

P1.0

P1.1

P1.2

P1.3

P1.4

P1.5

P1.6

P1.5

P1.6

P1.7/VREF

VSSD

P2.0

40

P1.7/VREF

1

P1.7/VREF

2

3

4

5

6

7

8

9

P2.0

P2.1

P2.2

P2.3

P2.4

P2.5

P2.6

P2.7

VSSD

P3.0

P3.1

2

1

2

3

4

5

6

7

8

9

P2.0

P2.1

P2.2

P2.3

P2.4

P2.5

P2.6

P2.7

VSSD

P3.0

P3.1

2

3

4

5

P2.0

P2.1

P2.2

P2.3

3

P2.1

4

P2.2

D3

E4

E5

E6

E3

E2

P2.2

P2.3

P2.4

P2.5

P2.6

P2.7

5

P2.3

6

P2.4

7

P2.5

6

7

8

P2.5

P2.6

P2.7

8

P2.6

9

P2.7

10

12

13

10

11

12

VSSD

P3.0

P3.1

10

11

9

10

P3.0

P3.1

E1

D2

P3.0

P3.1

Datasheet

15

002-00122 Rev. *P

2023-01-23

PSoC™ 4 MCU: PSoC™ 4100S

Based on Arm® Cortex®-M0+ CPU

Pinouts

Table 1

Pin list ^(continued)

44-pin TQFP

48-pin TQFP

40-pin QFN

32-pin QFN

35-ball CSP

14

16

17

18

19

20

21

22

23

24

25

Name

P3.2

P3.3

P3.4

P3.5

P3.6

P3.7

VDDD

P4.0

P4.1

P4.2

P4.3

13

14

15

16

17

18

19

20

21

22

23

Name

P3.2

P3.3

P3.4

P3.5

P3.6

P3.7

VDDD

P4.0

P4.1

P4.2

P4.3

Name

P3.2

P3.3

P3.4

P3.5

P3.6

P3.7

11

12

Name

P3.2

P3.3

Name

P3.2

P3.3

12

13

14

15

16

17

D1

C1

C2

P3.4

18

19

20

21

P4.0

P4.1

P4.2

P4.3

13

14

15

16

P4.0

P4.1

P4.2

P4.3

B1

B2

A2

A1

P4.0

P4.1

P4.2

P4.3

Note Pins 11, 15, 26, and 27 are No Connects (NC) on the 48-pin TQFP.

Descriptions of the power pins are as follows:

VDDD: Power supply for the digital section.

VDDA: Power supply for the analog section.

VSSD, VSSA: Ground pins for the digital and analog sections respectively.

VCCD: Regulated digital supply (1.8 V ± 5%)

VDD: Power supply to all sections of the chip

VSS: Ground for all sections of the chip

Datasheet

16

002-00122 Rev. *P

2023-01-23

PSoC™ 4 MCU: PSoC™ 4100S

Based on Arm® Cortex®-M0+ CPU

Power

4

Power

The following power system diagram shows the set of power supply pins as implemented for the PSoC™ 4100S.

The system has one regulator in Active mode for the digital circuitry. There is no analog regulator; the analog

circuits run directly from the V_DDinput.

VDDA

VDDD

VDDA

VSSA

VDDD

VSSD

Analog

Domain

Digital

Domain

VCCD

1.8 Volt

Regulator

Figure 5

Power supply connections

There are two distinct modes of operation. In Mode 1, the supply voltage range is 1.8 V to 5.5 V (unregulated

externally; internal regulator operational). In Mode 2, the supply range is 1.8 V ± 5% (externally regulated; 1.71 V

to 1.89 V, internal regulator bypassed).

4.1

Mode 1: 1.8 V to 5.5 V external supply

In this mode, the PSoC™ 4100S is powered by an external power supply that can be anywhere in the range of

1.8 V to 5.5 V. This range is also designed for battery-powered operation. For example, the chip can be powered

from a battery system that starts at 3.5 V and works down to 1.8 V. In this mode, the internal regulator of the

PSoC™ 4100S supplies the internal logic and its output is connected to the V_CCDpin. The V_CCDpin must be

bypassed to ground via an external capacitor (0.1 µF; X5R ceramic or better) and must not be connected to

anything else.

Datasheet

19

002-00122 Rev. *P

2023-01-23

PSoC™ 4 MCU: PSoC™ 4100S

Based on Arm® Cortex®-M0+ CPU

Power

4.2

Mode 2: 1.8 V ± 5% external supply

In this mode, the PSoC™ 4100S is powered by an external power supply that must be within the range of 1.71 V to

1.89 V; note that this range needs to include the power supply ripple too. In this mode, the VDD and VCCD pins

are shorted together and bypassed. The internal regulator can be disabled in the firmware.

Bypass capacitors must be used from VDDD to ground. The typical practice for systems in this frequency range is

to use a capacitor in the 1-µF range, in parallel with a smaller capacitor (0.1 µF, for example). Note that these are

simply rules of thumb and that, for critical applications, the PCB layout, lead inductance, and the bypass

capacitor parasitic should be simulated to design and obtain optimal bypassing.

Figure 6 shows an example of a bypass scheme.

Power supply bypass connections example

1.8 V to 5.5 V

0.1 mF

1.8 V to 5.5 V

0.1 mF

PSoC^TM4100S

V_DDA

V_DD

1 mF

V_CCD

0.1 mF

V_SS

Figure 6

External supply range from 1.8 V to 5.5 V with internal regulator active

Datasheet

20

002-00122 Rev. *P

2023-01-23

PSoC™ 4 MCU: PSoC™ 4100S

Based on Arm® Cortex®-M0+ CPU

Electrical specifications

5

Electrical specifications

5.1

Absolute maximum ratings

Table 3

Absolute maximum ratings^[1]

Spec ID Parameter

Description

Min

Typ

Max Unit

Details/conditions

SID1

V_{DDD_ABS}

V_{CCD_ABS}

V_{GPIO_ABS}

I_{GPIO_ABS}

Digital supply relative to V_SS

Direct digital core voltage

input relative to V_SS

GPIO voltage

Maximum current per GPIO

GPIO injection current,

–0.5

–

6

–

SID2

–0.5

–

1.95

V

SID3

SID4

–0.5

–25

–

V_DD+ 0.5

25

–

mA

SID5

I_{GPIO_injection}Max for V_IH> V_DDD, and

Min for V_IL< V_SS

–0.5

–

0.5

–

Current injected per pin

–

Electrostatic discharge

human body model

Electrostatic discharge

charged device model

BID44

ESD_HBM

2200

V

BID45

BID46

ESD_CDM

500

–

LU

Pin current for latch-up

–140

140

mA

Note

1. Usage above the absolute maximum conditions listed in Table 3 may cause permanent damage to the device. Exposure to absolute

maximum conditions for extended periods of time may affect device reliability. The maximum storage temperature is 150°C in

compliance with JEDEC Standard JESD22-A103, High Temperature Storage Life. When used below absolute maximum conditions but

above normal operating conditions, the device may not operate to specification.

Datasheet

21

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2023-01-23

PSoC™ 4 MCU: PSoC™ 4100S

Based on Arm® Cortex®-M0+ CPU

Electrical specifications

5.2

Device level specifications

All specifications are valid for –40°C  T_A 105°C and T_J 125°C, except where noted. Specifications are valid for

1.71 V to 5.5 V, except where noted.

Table 4

DC specifications

Typical values measured at V_DD= 3.3 V and 25 °C.

Spec ID Parameter

SID53 V_DD

Description

Min

Typ

Max Unit

Details/conditions

Internally regulated

supply

Internally unregulated

supply

Power supply input voltage

1.8

–

5.5

SID255 V_DD

1.71

–

1.89

V

(V_CCD= V_DDD= V_DDA

)

Output voltage (for core

logic)

External regulator voltage

bypass

Power supply bypass

capacitor

SID54

SID55

SID56

V_CCD

C_EFC

C_EXC

–

1.8

0.1

1

–

µF X5R ceramic or better

Active Mode, V_DD= 1.8 V to 5.5 V. Typical values measured at V_DD= 3.3 V and 25°C.

Execute from flash;

SID10

SID16

SID19

I_DD5

I_DD8

I_DD11

–

1.8

3.0

5.4

2.7

CPU at 6 MHz

Execute from flash;

CPU at 24 MHz

Execute from flash;

CPU at 48 MHz

4.75

6.85

mA Max is at 85°C and 5.5 V

Sleep Mode, VDDD = 1.8 V to 5.5 V (Regulator on)

I²C wakeup WDT, and

6 MHz. Max is at 85°C

SID22

SID25

IDD17

IDD20

–

1.7

2.2

2.5

comparators on

and 5.5 V.

mA

I²C wakeup, WDT, and

comparators on.

12 MHz. Max is at 85°C

and 5.5 V.

Sleep Mode, V_DDD= 1.71 V to 1.89 V (Regulator bypassed)

I²C wakeup, WDT, and

6 MHz. Max is at 85°C

SID28

IDD23

–

0.7

1

0.9

1.2

comparators on

and 5.5 V.

mA

I²C wakeup, WDT, and

comparators on

12 MHz. Max is at 85°C

and 5.5 V.

SID28A IDD23A

Deep Sleep Mode, V_DD= 1.8 V to 3.6 V (Regulator on)

SID31 I_DD26

I²C wakeup and WDT on

Deep Sleep Mode, V_DD= 3.6 V to 5.5 V (Regulator on)

SID34 I_DD29

I²C wakeup and WDT on

–

2.5

60

µA Max is at 3.6 V and 85°C.

µA Max is at 5.5 V and 85°C.

Deep Sleep Mode, V_DD= V_CCD= 1.71 V to 1.89 V (Regulator bypassed)

Max is at 1.89 V and

SID37

I_DD32

I²C wakeup and WDT on

–

2.5

2

65

5

µA

85°C.

XRES Current

Supply current while XRES

asserted

SID307 I_{DD_XR}

mA –

Datasheet

22

002-00122 Rev. *P

2023-01-23

PSoC™ 4 MCU: PSoC™ 4100S

Based on Arm® Cortex®-M0+ CPU

Electrical specifications

Table 5

AC specifications

Description

CPU frequency

Spec ID Parameter

SID48

SID49^[2]T_SLEEP

Min

DC

–

Typ

–

0

Max Unit

Details/conditions

F_CPU

48

–

MHz 1.71 V_DD5.5

Wakeup from Sleep mode

–

µs

Wakeup from Deep Sleep

mode

SID50^[2]T_DEEPSLEEP

–

35

–

Note

2. Guaranteed by characterization.

Datasheet

23

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PSoC™ 4 MCU: PSoC™ 4100S

Based on Arm® Cortex®-M0+ CPU

Electrical specifications

5.2.1

GPIO

Table 6

GPIO DC specifications

Spec ID Parameter

Description

Min

Typ

Max

Unit Details/conditions

Input voltage high

threshold

Input voltage low

threshold

LVTTL input,

V_DDD< 2.7 V

LVTTL input,

V_DDD< 2.7 V

[3]

SID57

SID58

SID241

SID242

SID243

SID244

SID59

SID60

SID61

SID62

SID62A

V_IH

V_IL

V_IH

V_IL

V_IH

V_IL

0.7 V_DDD

–

CMOS Input

–

0.3 V_DDD

[3]

0.7 V_DDD

–

0.3 V_DDD

LVTTL input,

2.0

–

V_DDD 2.7 V

LVTTL input,

_DDD 2.7 V

–

0.8

–

V

–

V

Output voltage high

level

Output voltage high

level

Output voltage low

level

Output voltage low

level

V_OH

V_OL

V_DDD– 0.6

I_OH= 4 mA, V_DDD 3 V

I_OH= 1 mA at 1.8 V V_DDD

I_OL= 4 mA at 1.8 V V_DDD

I_OL= 10 mA, V_DDD 3 V

I_OL= 3 mA, V_DDD 3 V

V_DDD– 0.5

–

0.6

0.4

Output voltage low

level

V_OL

SID63

SID64

R_PULLUP

Pull-up resistor

3.5

5.6

8.5

–

k

R_PULLDOWNPull-down resistor

Input leakage current

SID65

SID66

I_IL

–

2

nA 25°C, V_DDD= 3.0 V

(absolute value)

C_IN

Input capacitance

Input hysteresis LVTTL

–

25

–

40

7

–

pF

–

V

SID67^[4]V_HYSTTL

_DDD 2.7 V

0.05 ×

V_DDD

200

SID68^[4]V_HYSCMOS

Input hysteresis CMOS

–

mV

V_DD< 4.5 V

SID68A^[4]V_HYSCMOS5V5Input hysteresis CMOS

Current through

SID69^[4]I_DIODE

protection diode to

V_DD/V_SS

Maximum total source

or sink chip current

–

100

200

µA

–

SID69A^[4]I_{TOT_GPIO}

–

mA

Notes

3. V_IHmust not exceed V_DDD+ 0.2 V.

4. Guaranteed by characterization.

Datasheet

24

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PSoC™ 4 MCU: PSoC™ 4100S

Based on Arm® Cortex®-M0+ CPU

Electrical specifications

Table 7

GPIO AC specifications

(Guaranteed by characterization)

Spec ID Parameter

Description

Rise time in fast strong

mode

Fall time in fast strong mode

Rise time in slow strong

mode

Min

2

Typ

–

Max Unit

Details/conditions

SID70

SID71

SID72

T_RISEF

T_FALLF

T_RISES

12

ns

12

2

–

3.3 V V_DDD

,

Cload = 25 pF

10

–

60

–

Fall time in slow strong

mode

SID73

SID74

T_FALLS

10

–

GPIO F_OUT

;

F_GPIOUT1

3.3 V  V_DDD5.5 V

33

16.7

7

Fast strong mode

GPIO F_OUT

;

SID75

SID76

F_GPIOUT2

1.71 VV_DDD3.3 V

–

Fast strong mode

90/10%, 25 pF load,

60/40 duty cycle

GPIO F_OUT

;

F_GPIOUT3

3.3 V V_DDD5.5 V

MHz

Slow strong mode

GPIO F_OUT

;

SID245 F_GPIOUT4

SID246 F_GPIOIN

1.71 V V_DDD3.3 V

3.5

48

Slow strong mode.

GPIO input operating

frequency;

1.71 V V_DDD5.5 V

90/10% V_IO

Datasheet

25

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PSoC™ 4 MCU: PSoC™ 4100S

Based on Arm® Cortex®-M0+ CPU

Electrical specifications

5.2.2

XRES

Table 8

XRES DC specifications

Spec ID Parameter

Description

Input voltage high threshold 0.7 × V_DDD

Input voltage low threshold

Pull-up resistor

Input capacitance

Min

Typ

–

60

–

Max

–

0.3 × V_DDD

Unit Details/conditions

SID77

SID78

SID79

SID80

V_IH

V_IL

R_PULLUP

C_IN

V

CMOS Input

–

7

kΩ

–

pF

–

Typical hysteresis

SID81^[5]V_HYSXRES

Input voltage hysteresis

–

100

–

mV is 200 mV for

V_DD> 4.5 V

Current through protection

diode to V_DD/V_SS

SID82

I_DIODE

100

µA –

Table 9

XRES AC specifications

Description

SID83^[5]T_RESETWIDTHReset pulse width

Spec ID Parameter

Min

1

Typ

–

Max Unit Details/conditions

–

µs

–

Wake-up time from reset

release

BID194^[5]T_RESETWAKE

–

2.7

ms

–

Note

5. Guaranteed by characterization.

Datasheet

26

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PSoC™ 4 MCU: PSoC™ 4100S

Based on Arm® Cortex®-M0+ CPU

Electrical specifications

5.3

Analog peripherals

CTBm Opamp

5.3.1

Table 10

CTBm Opamp specifications

Spec ID

Parameter

Description

Min Typ

Max

Unit Details/conditions

Opamp block current,

external load

I_DD

SID269

SID270

SID271

I_{DD_HI}

I_{DD_MED}

I_{DD_LOW}

Power = High

Power = Medium

Power = Low

–

1100

550

150

1850

950

350

–

µA

Load = 20 pF, 0.1 mA

V_DDA= 2.7 V

G_BW

SID272

SID273

SID274

G_{BW_HI}

G_{BW_MED}

G_{BW_LO}

Power = High

Power = Medium

Power = Low

6

3

–

1

–

Input and output

MHz are 0.2 V to

V

_DDA– 0.2 V

V_DDA= 2.7 V,

500 mV from rail

I_{OUT_MAX}

SID275

SID276

SID277

I_{OUT_MAX_HI}

I_{OUT_MAX_MID}

I_{OUT_MAX_LO}

Power = High

Power = Medium

Power = Low

V_DDA= 1.71 V,

500 mV from rail

10

–

5

–

Output is 0.5 V to

V_DDA– 0.5 V

mA

I_OUT

SID278

SID279

SID280

I_{OUT_MAX_HI}

I_{OUT_MAX_MID}

I_{OUT_MAX_LO}

Power = High

4

–

Output is 0.5 V to

V_DDA– 0.5 V

Power = Medium

Power = Low

2

Opamp block current,

internal load

I_{DD_Int}

SID269_I

SID270_I

I_{DD_HI_Int}

I_{DD_MED_Int}

I_{DD_LOW_Int}

G_BW

–

Power = High

Power = Medium

Power = Low

V_DDA= 2.7 V

1500

700

–

1700

900

–

µA

SID271_I

SID272_I

–

Output is 0.25 V to

V

G_{BW_HI_Int}

–

Power = High

8

MHz

_DDA– 0.25 V

General opamp specs

for both internal and

external modes

Charge-pump on,

SID281

SID282

V_IN

–

V_DDA– 0.2

–0.05

V

_DDA= 2.7 V

Charge-pump on,

_DDA= 2.7 V

V

V_CM

V

Datasheet

27

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PSoC™ 4 MCU: PSoC™ 4100S

Based on Arm® Cortex®-M0+ CPU

Electrical specifications

Table 10

Spec ID

CTBm Opamp specifications (continued)

Parameter Description

V_OUT

Min Typ

Max

Unit Details/conditions

V_DDA= 2.7 V

Power = High,

Iload = 10 mA

SID283

SID284

SID285

SID286

SID288

V_{OUT_1}

V_{OUT_2}

V_{OUT_3}

V_{OUT_4}

V_{OS_TR}

–

V_DDA– 0.5

0.5

Power = High,

Iload = 1 mA

–

V_DDA– 0.2

0.2

V

Power = Medium,

Iload = 1 mA

–

V_DDA– 0.2

0.2

Power = Low,

Iload = 0.1 mA

–

0.2

High mode, input

0 V to V_DDA– 0.2 V

Offset voltage,

trimmed

–1.0 0.5

1.0

–

Medium mode,

Offset voltage,

trimmed

SID288A

V_{OS_TR}

–

input 0 V to

_DDA– 0.2 V

1

mV

V

Low mode, input

0 V to V_DDA– 0.2 V

Offset voltage,

trimmed

SID288B

SID290

V_{OS_TR}

–

2

3

Offset voltage drift,

trimmed

V_{OS_DR_TR}

–10

–

10

–

High mode

Offset voltage drift,

trimmed

SID290A

SID290B

10

µV/°C Medium mode

Offset voltage drift,

trimmed

–

Low mode

Input is 0 V to

V

_DDA– 0.2 V,

SID291

SID292

CMRR

PSRR

–

DC

70

80

85

Output is 0.2 V to

V

_DDA– 0.2 V

_DDD= 3.6 V,

dB

high-power mode,

input is 0.2 V to

At 1 kHz, 10-mV ripple

V

_DDA– 0.2 V

Noise

VN2

Input-referred, 1 kHz,

Power = High

SID294

SID295

–

72

28

Input and output

are at 0.2 V to

Input-referred, 10 kHz,

Power = High

VN3

VN4

nV/rtHz

V

_DDA– 0.2 V

Input-referred,

100 kHz,

SID296

–

15

Power = High

Datasheet

28

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2023-01-23

PSoC™ 4 MCU: PSoC™ 4100S

Based on Arm® Cortex®-M0+ CPU

Electrical specifications

Table 10

Spec ID

CTBm Opamp specifications ^(continued)

Parameter

Description

Min Typ

Max

Unit Details/conditions

Stable up to max.

load. Performance

specs at 50 pF.

SID297

SID298

C_LOAD

–

6

–

125

pF

Cload = 50 pF,

Power = High,

SLEW_RATE

–

V/µs

V_DDA= 2.7 V

From disable to

enable, no external RC

dominating

SID299

T_OP_WAKE

OL_GAIN

–

25

–

µs

SID299A

Open Loop Gain

90

dB

Comparator mode;

50 mV drive,

COMP_MODE

T_rise= T_fall(approx.)

Response time;

Power = High

SID300

SID301

TPD1

TPD2

–

150

500

Input is 0.2 V to

Response time;

Power = Medium

ns

V

_DDA– 0.2 V

Response time;

Power = Low

SID302

SID303

SID304

TPD3

–

2500

10

VHYST_OP

WUP_CTB

–

Hysteresis

mV

µs

Wake-up time from

Enabled to Usable

–

25

Mode 2 is lowest

current range.

Mode 1 has higher

GBW.

Deep Sleep

Mode

SID_DS_1

SID_DS_2

I_{DD_HI_M1}

–

Mode 1, high current

1400

700

Mode 1,

medium current

I_{DD_MED_M1}

SID_DS_3

SID_DS_4

I_{DD_LOW_M1}

I_{DD_HI_M2}

–

Mode 1, low current

Mode 2, high current

200

120

µA

25°C

Mode 2,

medium current

SID_DS_5

SID_DS_6

I_{DD_MED_M2}

I_{DD_LOW_M2}

–

60

15

Mode 2, low current

Datasheet

29

002-00122 Rev. *P

2023-01-23

PSoC™ 4 MCU: PSoC™ 4100S

Based on Arm® Cortex®-M0+ CPU

Electrical specifications

Table 10

Spec ID

CTBm Opamp specifications ^(continued)

Parameter

Description

Min Typ

Max

Unit Details/conditions

SID_DS_7

SID_DS_8

SID_DS_9

G_{BW_HI_M1}

–

Mode 1, high current

4

Mode 1,

medium current

G_{BW_MED_M1}

–

2

20-pF load, no DC

load 0.2 V to

G_{BW_LOW_M1}

–

Mode 1, low current

Mode 2, high current

0.5

MHz

SID_DS_10 G_{BW_HI_M2}

V

_DDA– 0.2 V

Mode 2,

medium current

SID_DS_11 G_{BW_MED_M2}

–

0.2

SID_DS_12 G_{BW_Low_M2}

SID_DS_13 V_{OS_HI_M1}

–

Mode 2, low current

Mode 1, high current

0.1

5

Mode 1,

medium current

SID_DS_14 V_{OS_MED_M1}

–

5

SID_DS_15 V_{OS_LOW_M1}

SID_DS_16 V_{OS_HI_M2}

–

Mode 1, low current

Mode 2, high current

5

With trim 25°C,

0.2 V to V_DDA– 0.2 V

mV

Mode 2,

medium current

SID_DS_17 V_{OS_MED_M2}

–

5

SID_DS_18 V_{OS_LOW_M2}

SID_DS_19 I_{OUT_HI_M1}

–

Mode 2, low current

Mode 1, high current

5

10

Output is 0.5 V to

Mode 1,

medium current

SID_DS_20 I_{OUT_MED_M1}

–

10

V

_DDA– 0.5 V

SID_DS_21 I_{OUT_LOW_M1}

SID_DS_22 I_{OUT_HI_M2}

–

Mode 1, low current

Mode 2, high current

4

1

mA

–

Mode 2,

medium current

SID_DS_23 I_{OUT_MED_M2}

SID_DS_24 I_{OUT_LOW_M2}

–

1

Mode 2, low current

0.5

Datasheet

30

002-00122 Rev. *P

2023-01-23

PSoC™ 4 MCU: PSoC™ 4100S

Based on Arm® Cortex®-M0+ CPU

Electrical specifications

5.3.2

Comparator

Table 11

Spec ID

Comparator DC specifications

Parameter

Description

Min Typ

Max

Unit Details/conditions

Input offset voltage,

factory trim

SID84

V_OFFSET1

–

±10

–

Input offset voltage,

custom trim

mV

–

SID85

SID86

SID87

V_OFFSET2

V_HYST

–

0

–

10

–

±4

35

Hysteresis when enabled

Input common mode

voltage in normal mode

–

V_ICM1

V_DDD– 0.1

Modes 1 and 2

Input common mode

SID247

SID247A

SID88

V_ICM2

V_ICM3

C_MRR

0

–

V_DDD

V_DDD– 1.15

–

V

voltage in low power mode

Input common mode

voltage in ultra low power

mode

Common mode rejection

ratio

Common mode rejection

ratio

Block current, normal mode

V_DDD≥ 2.2 V at –40°C

50

dB V_DDD≥ 2.7 V

SID88A

SID89

C_MRR

I_CMP1

I_CMP2

42

–

400

100

–

Block current,

low power mode

SID248

–

µA

Block current in ultra

low-power mode

DC Input impedance of

comparator

V_DDD≥ 2.2 V at –40°C

SID259

SID90

I_CMP3

Z_CMP

–

6

–

35

MΩ –

Table 12

Spec ID

Comparator AC specifications

Parameter

Description

Min

Typ Max Unit

Details/conditions

Response time, normal

mode, 50 mV overdrive

Response time, low power

mode, 50 mV overdrive

Response time, ultra-low

power mode, 200 mV

overdrive

SID91

TRESP1

–

38

70

110

200

–

ns

SID258

TRESP2

TRESP3

–

SID92

–

2.3

15

µs V_DDD≥ 2.2 V at –40°C

5.3.3

Temperature Sensor

Table 13

Spec ID

Temperature sensor specifications

Parameter

Description

Min

Typ Max Unit

Details/conditions

Temperature sensor

accuracy

SID93

TSENSACC

–5

±1 °C –40°C to +85°C

5

Datasheet

31

002-00122 Rev. *P

2023-01-23

PSoC™ 4 MCU: PSoC™ 4100S

Based on Arm® Cortex®-M0+ CPU

Electrical specifications

5.3.4

SAR

Table 14

Spec ID

SAR specifications

Parameter

Description

Min

Typ

Max

Unit Details/conditions

SAR ADC DC specifications

SID94

A_RES

Resolution

Number of channels - single

ended

–

12

16

bits

–

SID95

A_CHNLS_S

Number of channels -

differential

Monotonicity

Diff inputs use

SID96

SID97

SID98

A-CHNKS_D

A-MONO

–

4

–

neighboring I/O

Yes

With external

reference.

A_GAINERR Gain error

±0.1

%

Measured with 1-V

reference

–

SID99

A_OFFSET

A_ISAR

Input offset voltage

–

2

1

mV

mA

SID100

SID101

Current consumption

Input voltage range - single

ended

Input voltage range -

differential

A_VINS

V_SS

V_DDA

–

V

SID102

A_VIND

V_SS

–

V_DDA

–

SID103

SID104

A_INRES

A_INCAP

Input resistance

Input capacitance

–

2.2

10

kΩ

pF

–

Trimmed internal reference

to SAR

SID260

VREFSAR

1.188 1.2

1.212

V

–

SAR ADC AC specifications

SID106

SID107

SID108

SID109

A_PSRR

A_CMRR

A_SAMP

A_SNR

Power supply rejection ratio

Common mode rejection

ratio

Sample rate

Signal-to-noise and

distortion ratio (SINAD)

70

66

–

1

–

dB

Measured at 1 V

Msps –

65

dB F_IN= 10 kHz

Input bandwidth without

aliasing

Integral non linearity.

V_DD= 1.71 V to 5.5 V, 1 Msps

Integral non linearity.

V_DDD= 1.71 V to 3.6 V, 1 Msps

Integral non linearity.

V_DD= 1.71 V to 5.5 V, 500 ksps

Differential non linearity.

V_DD= 1.71 V to 5.5 V, 1 Msps

Differential non linearity.

V_DD= 1.71 V to 3.6 V, 1 Msps

SID110

A_BW

A_INL

A_DNL

–

A_samp/2 kHz

–

SID111

–1.7

–1.5

–1

2

V_REF= 1 V to V_DD

V_REF= 1.71 V to V_DD

V_REF= 1 V to V_DD

V_REF= 1.71 V to V_DD

V_REF= 1 V to V_DD

SID111A

SID111B

SID112

1.7

LSB

2.2

SID112A

SID112B

–1

2

Differential non linearity.

V_DD= 1.71 V to 5.5 V, 500 ksps

–1

2.2

Datasheet

32

002-00122 Rev. *P

2023-01-23

PSoC™ 4 MCU: PSoC™ 4100S

Based on Arm® Cortex®-M0+ CPU

Electrical specifications

Table 14

Spec ID

SID113

SAR specifications ^(continued)

Parameter

Description

Total harmonic distortion

SAR operating speed

Min

–

Typ

–

Max

–65

Unit Details/conditions

dB Fin = 10 kHz

A_THD

–

SID261

FSARINTREF without external reference

bypass

100

ksps 12-bit resolution

5.3.5

CSD and IDAC

Table 15

CSD and IDAC specifications

Spec ID

Parameter

Description

Min Typ

Max

Unit Details/conditions

Max allowed ripple on

power supply,

DC to 10 MHz

V_DD> 2 V (with

SYS.PER#3

VDD_RIPPLE

–

±50

ripple), 25°C T_A,

Sensitivity = 0.1 pF

V_DD> 1.75V (with

ripple), 25°C T_A,

Parasitic

mV

Max allowed ripple on

VDD_RIPPLE_1.8 power supply,

DC to 10 MHz

SYS.PER#16

–

±25

capacitance (C_P) <

20 pF,

Sensitivity ≥ 0.4 pF

Maximum block

current for both

IDACs in dynamic

(switching) mode

Maximum block

SID.CSD.BLK

SID.CSD#15

ICSD

–

4000

µA including

comparators,

current

buffer, and

reference

generator.

V_DDA– 0.6 or 4.4,

whichever is lower

Voltage reference for

CSD and comparator

V_REF

0.6 1.2 V_DDA– 0.6

V

External voltage

reference for CSD and 0.6

comparator

V_DDA– 0.6 or 4.4,

whichever is lower

SID.CSD#15A VREF_EXT

–

V

_DDA– 0.6

IDAC1 (7-bits) block

SID.CSD#16

SID.CSD#17

SID308

IDAC1IDD

IDAC2IDD

VCSD

–

1750

5.5

–

current

µA

V

IDAC2 (7-bits) block

current

Voltage range of

operation

Voltage compliance

range of IDAC

DNL

–

1.8 V ± 5% or 1.8 V

to 5.5 V

V_DDA– 0.6 or 4.4,

whichever is lower

1.71

SID308A

SID309

SID310

SID311

SID312

VCOMPIDAC

IDAC1DNL

IDAC1INL

IDAC2DNL

IDAC2INL

0.6

–

V_DDA– 0.6

–1

–2

–1

–2

1

2

1

2

–

INL is ±5.5 LSB for

V_DDA< 2 V

–

INL is ±5.5 LSB for

V_DDA< 2 V

INL

LSB

DNL

INL

Datasheet

33

002-00122 Rev. *P

2023-01-23

PSoC™ 4 MCU: PSoC™ 4100S

Based on Arm® Cortex®-M0+ CPU

Electrical specifications

Table 15

Spec ID

CSD and IDAC specifications ^(continued)

Parameter

Description

Min Typ

Max

Unit Details/conditions

Ratio of counts of

finger to noise.

Guaranteed by

characterization

Capacitance range

of 5 to 35 pF, 0.1-pF

SID313

SNR

5

–

Ratio

sensitivity. All use

cases. V_DDA> 2 V.

Output current of

IDAC1 (7 bits) in low

range

Output current of

IDAC1 (7 bits) in

medium range

Output current of

IDAC1 (7 bits) in high

range

Output current of

IDAC1 (7 bits) in low

range, 2X mode

SID314

IDAC1CRT1

IDAC1CRT2

IDAC1CRT3

IDAC1CRT12

4.2

34

275

8

–

5.4

41

LSB = 37.5-nA typ.

SID314A

SID314B

SID314C

LSB = 300-nA typ.

LSB = 2.4-µA typ.

LSB = 75-nA typ.

330

10.5

Output current of

IDAC1 (7 bits) in

medium range, 2X

mode

Output current of

IDAC1 (7 bits) in high

range, 2X mode

Output current of

IDAC2 (7 bits) in low

range

Output current of

IDAC2 (7 bits) in

medium range

Output current of

IDAC2 (7 bits) in high

range

Output current of

IDAC2 (7 bits) in low

range, 2X mode

SID314D

IDAC1CRT22

69

–

82

LSB = 600-nA typ.

LSB = 4.8-µA typ.

SID314E

SID315

IDAC1CRT32

IDAC2CRT1

IDAC2CRT2

IDAC2CRT3

IDAC2CRT12

540

4.2

34

–

660

5.4

LSB = 37.5-nA typ.

µA

SID315A

SID315B

SID315C

41

LSB = 300-nA typ.

275

8

330

10.5

LSB = 2.4-µA typ.

LSB = 75-nA typ.

Output current of

IDAC2 (7 bits) in

medium range, 2X

mode

SID315D

IDAC2CRT22

69

–

82

LSB = 600-nA typ.

Output current of

IDAC2 (7 bits) in high

range, 2X mode

Output current of IDAC

in 8-bit mode in low

range

SID315E

SID315F

SID315G

IDAC2CRT32

IDAC3CRT13

IDAC3CRT23

540

8

–

660

10.5

82

LSB = 4.8-µA typ.

LSB = 37.5-nA typ.

LSB = 300-nA typ.

Output current of IDAC

in 8-bit mode in

medium range

69

Datasheet

34

002-00122 Rev. *P

2023-01-23

PSoC™ 4 MCU: PSoC™ 4100S

Based on Arm® Cortex®-M0+ CPU

Electrical specifications

Table 15

Spec ID

CSD and IDAC specifications ^(continued)

Parameter

Description

Min Typ

Max

Unit Details/conditions

µA LSB = 2.4-µA typ.

Polarity set by

Output current of IDAC

in 8-bit mode in high

range

SID315H

IDAC3CRT33

540

–

660

Source or Sink.

SID320

IDACOFFSET

IDACGAIN

All zeroes input

–

1

LSB

Offset is 2 LSBs for

37.5 nA/LSB mode

Full-scale error less

offset

SID321

SID322

–

±10

9.2

%

–

Mismatch between

IDACMISMATCH1 IDAC1 and IDAC2 in

Low mode

LSB = 37.5-nA typ.

Mismatch between

IDACMISMATCH2 IDAC1 and IDAC2 in

Medium mode

Mismatch between

IDACMISMATCH3 IDAC1 and IDAC2 in

High mode

SID322A

SID322B

SID323

–

5.6

6.8

10

LSB LSB = 300-nA typ.

LSB = 2.4-µA typ.

Full-scale

transition.

Settling time to 0.5 LSB

for 8-bit IDAC

IDACSET8

No external load.

µs

Full-scale

Settling time to 0.5 LSB

for 7-bit IDAC

SID324

SID325

IDACSET7

–

10

–

transition.

No external load.

External modulator

capacitor.

5-V rating, X7R or

NP0 cap.

CMOD

2.2

nF

Datasheet

35

002-00122 Rev. *P

2023-01-23

PSoC™ 4 MCU: PSoC™ 4100S

Based on Arm® Cortex®-M0+ CPU

Electrical specifications

5.3.6

10-bit CapSense ADC

Table 16

Spec ID

10-bit CAPSENSE™ ADC specifications

Parameter

Description

Min

Typ Max Unit

Details/conditions

Auto-zeroingisrequired

every millisecond

SIDA94

A_RES

Resolution

–

10

bits

Number of channels - single

ended

Monotonicity

SIDA95

SIDA97

A_CHNLS_S

A-MONO

–

16

–

Defined by AMUX Bus

–

InV_REF(2.4 V)modewith

V_DDAbypass

capacitance of 10 µF

Yes

%

SIDA98

SIDA99

A_GAINERR Gain error

–

±2

3

InV_REF(2.4 V)modewith

A_OFFSET

Input offset voltage

mV V_DDAbypass

capacitance of 10 µF

SIDA100

SIDA101

A_ISAR

A_VINS

Current consumption

Input voltage range - single

ended

–

0.25

mA

V

–

V_SSA

V_DDA

–

SIDA103

SIDA104

A_INRES

A_INCAP

Input resistance

Input capacitance

–

2.2

20

–

KΩ

pF

–

InV_REF(2.4 V)modewith

SIDA106

SIDA107

A_PSRR

A_TACQ

Power supply rejection ratio

Sample acquisition time

–

60

1

–

dB V_DDAbypass

capacitance of 10 µF

–

Does not include

Conversion time for 8-bit

resolution at conversion

rate = Fhclk/(2^(N+2)). Clock

frequency = 48 MHz.

acquisition time.

SIDA108

A_CONV8

–

21.3

Equivalent to 44.8 ksps

including acquisition

µs time.

Does not include

acquisition time.

Equivalent to 11.6 ksps

including acquisition

time.

With 10-Hz input sine

wave, external 2.4-V

reference, V_REF(2.4 V)

mode

Conversion time for 10-bit

resolution at conversion

rate = Fhclk/(2^(N+2)). Clock

frequency = 48 MHz.

SIDA108A A_CONV10

–

85.3

–

Signal-to-noise and

Distortion ratio (SINAD)

SIDA109

A_SND

61

dB

Input bandwidth without

aliasing

Integral Non Linearity.

1 ksps

Differential Non Linearity.

1 ksps

SIDA110

SIDA111

SIDA112

A_BW

A_INL

A_DNL

–

22.4 KHz 8-bit resolution

2

1

V_REF= 2.4 V or greater

LSB

–

Datasheet

36

002-00122 Rev. *P

2023-01-23

PSoC™ 4 MCU: PSoC™ 4100S

Based on Arm® Cortex®-M0+ CPU

Electrical specifications

5.4

Digital peripherals

5.4.1

Timer Counter Pulse-width Modulator (TCPWM)

Table 17

TCPWM specifications

Spec ID

Parameter

Description

Min Typ Max Unit

Details/conditions

Block current

SID.TCPWM.1 ITCPWM1

SID.TCPWM.2 ITCPWM2

SID.TCPWM.2A ITCPWM3

–

45

consumption at 3 MHz

Block current

consumption at 12 MHz

Block current

consumption at 48 MHz

155 µA

650

All modes (TCPWM)

–

Fc max = CLK_SYS

Maximum = 48 MHz

For all trigger events^[6]

TCPWM_FREQ

TPWM_ENEXT

SID.TCPWM.3

SID.TCPWM.4

Operating frequency

–

Fc MHz

–

Input trigger pulse

width

2/Fc

Minimum possible width of

Overflow, Underflow, and CC

(Counter equals Compare

value) outputs

Output trigger pulse

widths

TPWM_EXT

SID.TCPWM.5

2/Fc

–

Minimum time between

successive counts

ns

–

TC_RES

SID.TCPWM.5A

SID.TCPWM.5B

Resolution of counter

PWM resolution

1/Fc

–

Minimum pulse width of

PWM Output

PWM_RES

–

Minimum pulse width

between Quadrature phase

inputs

Quadrature inputs

resolution

Q_RES

SID.TCPWM.5C

1/Fc

–

Note

6. Trigger events can be Stop, Start, Reload, Count, Capture, or Kill depending on which mode of operation is selected.

Datasheet

37

002-00122 Rev. *P

2023-01-23

PSoC™ 4 MCU: PSoC™ 4100S

Based on Arm® Cortex®-M0+ CPU

Electrical specifications

5.4.2

I²C

Table 18

Fixed I²C DC specifications^[7]

Spec ID

Parameter

Description

Min

Typ

Max Unit Details/conditions

SID149

SID150

SID151

SID152

I_I2C1

Block current consumption

at 100 kHz

Block current consumption

at 400 kHz

Block current consumption

at 1 Mbps

I²C enabled in Deep Sleep

mode

–

50

–

I_I2C2

I_I2C3

I_I2C4

–

135

–

µA

310

–

1.4

–

Table 19

Fixed I²C AC specifications^[7]

Spec ID

SID153

Parameter

F_I2C1

Description

Bit rate

Min

–

Typ

–

Max

1

Unit Details/conditions

Msps –

Note

7. Guaranteed by characterization.

Datasheet

38

002-00122 Rev. *P

2023-01-23

PSoC™ 4 MCU: PSoC™ 4100S

Based on Arm® Cortex®-M0+ CPU

Electrical specifications

5.4.3

SPI

Table 20

SPI DC specifications^[8]

Spec ID

Parameter

Description

Min

Typ

Max

Unit Details/conditions

Block current

SID163

SID164

SID165

ISPI1

–

360

–

consumption at 1 Mbps

Block current

consumption at 4 Mbps

Block current

consumption at 8 Mbps

ISPI2

ISPI3

–

560

600

µA

–

Table 21

Spec ID

SPI AC specifications^[8]

Parameter

Description

Min

Typ

Max

Unit Details/conditions

SPIoperatingfrequency

(Master; 6X

oversampling)

SID166

FSPI

–

8

MHz SID166

Fixed SPI Master Mode AC specifications

MOSI valid after SClock

driving edge

MISO valid before

SClock capturing edge

Previous MOSI data

hold time

SID167

SID168

SID169

TDMO

TDSI

–

20

0

–

15

–

Full clock, late

ns

MISO sampling

Referred to Slave

capturing edge

THMO

–

Fixed SPI Slave Mode AC specifications

MOSI valid before

SID170

SID171

TDMI

TDSO

40

–

Sclock capturing edge

MISO valid after Sclock

driving edge

MISO valid after Sclock

driving edge in External

Clock mode

42 + (3 × Tcpu)

48

T_CPU= 1/F_CPU

SID171A

TDSO_EXT

–

ns

–

Previous MISO data

hold time

SSEL valid to first SCK

valid edge

SID172

THSO

0

–

SID172A

TSSELSSCK

100

Note

8. Guaranteed by characterization.

Datasheet

39

002-00122 Rev. *P

2023-01-23

PSoC™ 4 MCU: PSoC™ 4100S

Based on Arm® Cortex®-M0+ CPU

Electrical specifications

5.4.4

UART

Table 22

UART DC specifications^[9]

Spec ID Parameter

Description

Min

Typ

Max Unit

Details/conditions

Block current consumption

at 100 Kbps

Block current consumption

at 1000 Kbps

SID160 I_UART1

–

55

µA

312

–

SID161 I_UART2

–

Table 23

UART AC specifications^[9]

Spec ID Parameter

SID162 F_UART

Description

Min

–

Typ

–

Max

1

Unit Details/conditions

Mbps –

Bit rate

5.4.5

LCD

Table 24

LCD direct drive DC specifications^[9]

Spec ID Parameter

Description

Min

Typ

Max Unit

Details/conditions

Operating current in low

power mode

16 × 4 small segment

disp. at 50 Hz

SID154 I_LCDLOW

–

5

–

µA

LCD capacitance per

SID155 C_LCDCAP

SID156 LCD_OFFSET

SID157 I_LCDOP1

–

500

20

2

5000

pF

–

segment/common driver

Long-term segment offset

LCD system operating

current Vbias = 5 V

LCD system operating

current Vbias = 3.3 V

–

mV

32 × 4 segments. 50 Hz.

25°C

32 × 4 segments. 50 Hz.

25°C

mA

SID158 I_LCDOP2

–

2

–

Table 25

LCD direct drive AC specifications^[9]

Spec ID Parameter

SID159 F_LCD

Description

LCD frame rate

Min

10

Typ

50

Max Unit

150 Hz

Details/conditions

–

Note

9. Guaranteed by characterization.

Datasheet

40

002-00122 Rev. *P

2023-01-23

PSoC™ 4 MCU: PSoC™ 4100S

Based on Arm® Cortex®-M0+ CPU

Electrical specifications

5.5

Memory

Flash

5.5.1

Table 26

Flash DC specifications

Spec ID Parameter

SID173 V_PE

Description

Erase and program voltage

Min

1.71

Typ

–

Max Unit

5.5 –

Details/conditions

V

Table 27

Spec ID

Flash AC specifications

Parameter

Description

Min Typ Max

Unit

Row (block) write

time (erase and

program)

Row erase time

Row program time

after erase

[10]

SID174

T_ROWWRITE

T_ROWERASE

–

20

Row (block) = 128 bytes

SID175

SID176

–

16

4

–

ms

[10]

T_ROWPROGRAM

Bulk erase time

(64 KB)

[10]

SID178

T_BULKERASE

–

35

–

Total device

[10]

SID180^[11]

SID181^[11]

T_DEVPROG

F_END

–

7

–

Seconds –

program time

Flash endurance

100 K

Cycles

–

Flash retention.

T_A 55 °C,

100 K P/E cycles

Flash retention.

T_A 85 °C,

10 K P/E cycles

Flash retention.

T_A 105 °C,

10K P/E cycles,

 three years at

T_A≥ 85 °C

SID182^[11]

F_RET

20

10

–

Years

SID182A^[11]

–

SID182B

–

10

–

20

Years

Number of Wait

states at 48 MHz

Number of Wait

states at 24 MHz

SID256

SID257

TWS48

TWS24

2

1

–

CPU execution from

flash

Notes

10.It can take as much as 20 milliseconds to write to flash. During this time the device should not be Reset, or Flash operations may be

interrupted and cannot be relied on to have completed. Reset sources include the XRES pin, software resets, CPU lockup states and

privilege violations, improper power supply levels, and watchdogs. Make certain that these are not inadvertently activated.

11.Guaranteed by characterization.

Datasheet

41

002-00122 Rev. *P

2023-01-23

PSoC™ 4 MCU: PSoC™ 4100S

Based on Arm® Cortex®-M0+ CPU

Electrical specifications

5.6

System resources

5.6.1

Power-on reset (POR)

Table 28

Spec ID

Power-on reset (POR)

Parameter

Description

Min Typ Max Unit Details/conditions

At power-up and

SID.CLK#6 SR_POWER_UP Power supply slew rate

1

–

67

V/ms

V

power-down

SID185^[12]V_RISEIPOR

SID186^[12]V_FALLIPOR

Rising trip voltage

Falling trip voltage

0.80

0.70

–

1.5

1.4

–

Table 29

Spec ID

Brown-out detect (BOD) for V_CCD

Parameter

Description

Min

Typ Max

Unit Details/conditions

BOD trip voltage in active

and sleep modes

BOD trip voltage in Deep

Sleep

SID190^[12]V_FALLPPOR

1.48

–

1.62

1.5

–

V

SID192^[12]V_FALLDPSLP

1.11

–

5.6.2

SWD interface

Table 30

SWD interface specifications

Spec ID

Parameter

Description

Min

Typ

Max Unit Details/conditions

SWDCLK ≤ 1/3 CPU

SID213

F_SWDCLK1

3.3 V  V_DD 5.5 V

–

14

clock frequency

MHz

SWDCLK ≤ 1/3 CPU

clock frequency

SID214

F_SWDCLK2

1.71 V  V_DD 3.3 V

–

7

SID215^[12]

SID216^[12]

SID217^[12]

T_SWDI_SETUP T = 1/f SWDCLK

T_SWDI_HOLD T = 1/f SWDCLK

0.25 × T

–

0.5 × T

–

ns

T_SWDO_VALID T = 1/f SWDCLK

–

1

SID217A^[12]T_SWDO_HOLD T = 1/f SWDCLK

Note

12.Guaranteed by characterization.

Datasheet

42

002-00122 Rev. *P

2023-01-23

PSoC™ 4 MCU: PSoC™ 4100S

Based on Arm® Cortex®-M0+ CPU

Electrical specifications

5.6.3

IMO

Table 31

IMO DC specifications

(Guaranteed by design)

Spec ID

Parameter

Description

Min

Typ

Max Unit Details/conditions

IMO operating current at

48 MHz

IMO operating current at

24 MHz

SID218

I_IMO1

–

250

180

–

µA

SID219

I_IMO2

–

Table 32

IMO AC specifications

Parameter

Spec ID

Description

Min

Typ

Max Unit

Details/conditions

At –40°C to 85°C,

for industrial

SID223^[14]

–

±2.0

±2.5

±2.0

%

temperature range and

original extended

industrial range parts

At –40°C to 105°C,

for all extended

industrial temperature

range parts

At –30°C to 105°C,

for enhanced IMO

extended industrial

temperature range

parts

SID223A^{[13, 14]}

SID223B^{[13, 14]}

–

Frequency

variation at 24, 32,

and 48 MHz

F_IMOTOL1

(trimmed)

At –20°C to 105°C,

for enhanced IMO

extended industrial

temperature range

parts

At 0°C to 85°C,

for enhanced IMO

extended industrial

temperature range

parts

SID223C^{[13, 14]}

–

±1.5

%

SID223D^{[13, 14]}

±1.25

SID226

SID228

T_STARTIMO

T_JITRMSIMO2RMS jitter at 24 MHz

IMO startup time

–

145

7

–

µs

ps

–

Notes

13.The enhanced IMO extended temperature range parts replace the original extended industrial temperature range parts. For details

on how to identify enhanced IMO extended temperature range parts, please refer to KBA235887.

14.Evaluated by characterization. Does not take into account soldering or board-level effects.

Datasheet

43

002-00122 Rev. *P

2023-01-23

PSoC™ 4 MCU: PSoC™ 4100S

Based on Arm® Cortex®-M0+ CPU

Electrical specifications

5.6.4

ILO

Table 33

ILO DC specifications

(Guaranteed by design)

Spec ID Parameter

SID231^[15]I_ILO1

Description

ILO operating current

Min

–

Typ

0.3

Max

1.05

Unit Details/conditions

µA

–

Table 34

Spec ID

ILO AC specifications

Parameter

Description

ILO startup time

ILO duty cycle

Min

–

40

20

Typ

–

50

40

Max

2

60

80

Unit Details/conditions

SID234^[15]T_STARTILO1

SID236^[15]T_ILODUTY

ms

%

–

SID237

F_ILOTRIM1

ILO frequency range

kHz

5.6.5

WCO

Table 35

WCO specifications

Spec ID Parameter

Description

Min

Typ

Max

Unit Details/conditions

SID398

FWCO

Crystal frequency

–

32.768

–

kHz

–

With 20-ppm

crystal

SID399

FTOL

Frequency tolerance

–

50

250

ppm

SID400

SID401

SID402

SID403

SID404

ESR

PD

TSTART

CL

Equivalent series resistance

Drive level

Startup time

Crystal load capacitance

Crystal shunt capacitance

–

6

–

50

–

1.35

–

1

500

12.5

–

kΩ

µW

ms

–

pF

C0

Operating current (high

power mode)

Operating current (low

power mode)

SID405

SID406

IWCO1

IWCO2

–

8

1

–

A

5.6.6

External clock

Table 36

Spec ID

External clock specifications

Parameter

Description

Min

Typ

Max

Unit Details/conditions

External clock input

frequency

Duty cycle; measured at

V_DD/2

SID305^[15]ExtClkFreq

0

–

48

55

MHz

%

–

SID306^[15]ExtClkDuty

45

–

Note

15.Guaranteed by characterization.

Datasheet

44

002-00122 Rev. *P

2023-01-23

PSoC™ 4 MCU: PSoC™ 4100S

Based on Arm® Cortex®-M0+ CPU

Electrical specifications

5.6.7

Block

Table 37

Spec ID

Block specs

Parameter

Description

Min

Typ

Max

Unit Details/conditions

System clock source

switching time

SID262^[16]T_CLKSWITCH

3

–

4

Periods –

5.6.8

Smart I/O

Table 38

Spec ID

Smart I/O pass-through time (Delay in Bypass Mode)

Parameter

Description

Min

Typ

Max

Unit Details/conditions

Max delay added by Smart

I/O in Bypass Mode

SID252 PRG_BYPASS

–

1.6

ns

–

Note

16.Guaranteed by characterization.

Datasheet

45

002-00122 Rev. *P

2023-01-23

PSoC™ 4 MCU: PSoC™ 4100S

Based on Arm® Cortex®-M0+ CPU

Ordering information

6

Ordering information

The marketing part numbers for the PSoC™ 4100S family are listed in the following table.

Table 39

Ordering information

Features

Package


型号：	CY8C4125AZI-S413T
厂家：	Infineon
描述：	32位PSoC™ 4 Arm® Cortex®-M0/M0+
文件：	总62页 (文件大小：909K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

CY8C4125AZI-S413T [INFINEON]

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