CY8C4128LQI-BL593_技术文档

CY8C41xx-BL

PSoC™ 4 MCU with AIROC™ Bluetooth® LE

Based on Arm® Cortex®-M0

General description

PSoC™ 4 is a scalable and reconfigurable platform architecture for a family of programmable embedded system

controllers with an Arm® Cortex®-M0 CPU. It combines programmable and reconfigurable analog and digital

blocks with flexible automatic routing. The PSoC™ 4 CY8C41xx-BL MCU with AIROC™ Bluetooth® LE product

family, based on this platform, is a combination of a microcontroller with an integrated Bluetooth® Low Energy,

also known as Bluetooth® Smart, radio and subsystem (BLESS), compliant with Bluetooth® 4.2 specifications.

The other features include digital programmable logic, high-performance analog-to-digital conversion (ADC),

opamps with comparator mode, and standard communication and timing peripherals. The PSoC™ 4

CY8C41xx-BL MCU with AIROC™ Bluetooth® LE products will be fully upward compatible with members of the

PSoC™ 4 platform for new applications and design needs. The programmable analog and digital subsystems

allow flexibility and in-field tuning of the design.

Features

• 32-bit MCU subsystem

- 24-MHz Arm® Cortex®-M0 CPU with single-cycle multiply

- Up to 256 KB of flash with read accelerator

- Up to 32 KB of SRAM

• Bluetooth® LE radio and subsystem

- 2.4-GHz RF transceiver with Bluetooth® LE 4.2 support and 50-Ω antenna drive

- Digital PHY

- Link layer engine supporting master and slave modes

- RF output power: –18 dBm to +3 dBm

- RX sensitivity: –89 dBm

- RX current: 16.4 mA

- TX current: 15.6 mA at 0 dBm

- Received Signal Strength Indication (RSSI): 1-dB resolution

• Programmable analog

- Two opamps with reconfigurable high-drive external and high-bandwidth internal drive, comparator modes,

and ADC input buffering capability; can operate in Deep-Sleep mode.

- 12-bit, 806 ksps SAR ADC with differential and single-ended modes; channel sequencer with signal averaging

- Two current DACs (IDACs) for general-purpose or capacitive sensing applications on any pin

- Two low-power comparators that operate in Deep-Sleep mode

• Power management

- Active mode: 1.7 mA at 3-MHz flash program execution

- Deep-Sleep mode: 1.3 µA with watch crystal oscillator (WCO) on

- Hibernate mode: 150 nA with RAM retention

- Stop mode: 60 nA

• Capacitive sensing

- Capacitive sigma-delta (CSD) provides best-in-class SNR (> 5:1) and liquid tolerance

- Infineon-supplied software component makes capacitive-sensing design easy

- Automatic hardware-tuning algorithm (SmartSense)

• Segment LCD drive

- LCD drive supported on all pins (common or segment)

- Operates in Deep-Sleep mode with four bits per pin memory

Datasheet

www.infineon.com

Please read the Important Notice and Warnings at the end of this document

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PSoC™ 4 MCU with AIROC™ Bluetooth® LE

Based on Arm® Cortex®-M0

Features

• Serial communication

- Two independent runtime reconfigurable serial communication blocks (SCBs) with reconfigurable I²C, SPI, or

UART functionality

• Timing and pulse-width modulation

- Four 16-bit timer, counter, pulse-width modulator (TCPWM) blocks

- Center-aligned, Edge, and Pseudo-random modes

- Comparator-based triggering of Kill signals for motor drive and other high-reliability digital logic applications

• Up to 36 programmable GPIOs

- 7 mm × 7 mm 56-pin QFN package

- 3.51 mm × 3.91 mm 68-ball CSP package

- Any GPIO pin can be CAPSENSE™, LCD, analog, or digital

- Two overvoltage-tolerant (OVT) pins; drive modes, strengths, and slew rates are programmable

• PSoC™ Creator design environment

- Integrated design environment (IDE) provides schematic design entry and build (with analog and digital

automatic routing)

- API components for all fixed-function and programmable peripherals

• Industry-standard tool compatibility

- After schematic entry, development can be done with Arm®-based industry-standard development tools

Datasheet

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PSoC™ 4 MCU with AIROC™ Bluetooth® LE

Based on Arm® Cortex®-M0

More information

There is a wealth of data at www.infineon.com to help you to select the right PSoC™ device for your design, and

to help you to quickly and effectively integrate the device into your design. For a comprehensive list of resources,

see the introduction page for Bluetooth® Low Energy products. Following is an abbreviated list for PSoC™ 4

CY8C4xxx-BL MCU with AIROC™ Bluetooth® LE:

• Overview: PSoC™ portfolio

• Product selectors: PSoC™ 1, PSoC™ 3, PSoC™ 4, PSoC™ 4 CY8C4xxx-BL MCU with AIROC™ Bluetooth® LE,

PSoC™ 5LP. In addition, PSoC™ Creator includes a device selection tool.

• Application notes: There are a large number of PSoC™ application notes covering a broad range of topics, from

basic to advanced level. Recommended application notes for getting started with PSoC™ 4 CY8C4xxx-BL MCU

with AIROC™ Bluetooth® LE are:

- AN91267: Getting started with PSoC™ 4 CY8C4xxx-BL MCU with AIROC™ Bluetooth® LE

- AN91184: PSoC™ 4 CY8C4xxx-BL MCU with AIROC™ Bluetooth® LE - Designing Bluetooth® LE applications

- AN91162: Creating a Bluetooth® LE Custom Profile

- AN97060: PSoC™ 4 CY8C4xxx-BL MCU with AIROC™ Bluetooth® LE and PRoC-BLE - Over-The-Air (OTA) Device

Firmware Upgrade (DFU) guide

- AN91445: Antenna design and RF layout guidelines

- AN96841: Getting started With EZ-BLE module

- AN85951: PSoC™ 4 CAPSENSE™ design guide

- AN95089: PSoC™ 4/PRoC-Bluetooth® LE crystal oscillator selection and tuning techniques

- AN92584: Designing for low power and estimating battery life for Bluetooth® LE applications

• Technical reference manual (TRM) is in two documents:

- Architecture TRM details each PSoC™ 4 CY8C4xxx-BL MCU with AIROC™ Bluetooth® LE functional block.

- Registers TRM describes each of the PSoC™ 4 CY8C4xxx-BL MCU with AIROC™ Bluetooth® LE registers.

• Development kits:

- CY8CKIT-042-BLE-A Pioneer Kit, is a flexible, Arduino-compatible, Bluetooth® LE development kit for

PSoC™ 4 with AIROC™ Bluetooth® LE.

- CY8CKIT-142, PSoC™ 4 with AIROC™ Bluetooth® LE Module, features a PSoC™ 4 CY8C4xxx-BL MCU with AIROC™

Bluetooth® LE device, two crystals for the antenna matching network, a PCB antenna, and other passives,

while providing access to all GPIOs of the device.

- CY8CKIT-143, PSoC™ 4 with AIROC™ Bluetooth® LE 256 KB module, features a PSoC™ 4 CY8C4xxx-BL MCU with

AIROC™ Bluetooth® LE 256 KB device, two crystals for the antenna matching network, a PCB antenna, and

other passives, while providing access to all GPIOs of the device.

The MiniProg3 device provides an interface for flash programming and debug.

Datasheet

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PSoC™ 4 MCU with AIROC™ Bluetooth® LE

Based on Arm® Cortex®-M0

PSoC™ Creator

PSoC™ Creator is a free Windows-based Integrated Design Environment (IDE). It enables concurrent hardware

and firmware design of PSoC™ 3, PSoC™ 4, and PSoC™ 5LP based systems. Create designs using classic, familiar

schematic capture supported by over 100 pre-verified, production-ready PSoC™ Components; see the list of

component datasheets. With PSoC™ Creator, you can:

1. Drag and drop component icons to build your hardware system design in the main design workspace

2. Codesign your application firmware with the PSoC™ hardware, using the PSoC™ Creator IDE C compiler

3. Configure components using the configuration tools

4. Explore the library of 100+ components

5. Review component datasheets

Figure 1

Multiple-sensor example project in PSoC™ Creator

Datasheet

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PSoC™ 4 MCU with AIROC™ Bluetooth® LE

Based on Arm® Cortex®-M0

Table of contents

General description ...........................................................................................................................1

Features ...........................................................................................................................................1

More information ..............................................................................................................................3

PSoC™ Creator ..................................................................................................................................4

Table of contents...............................................................................................................................5

Block diagram...................................................................................................................................7

1 Functional definition.......................................................................................................................8

1.1 CPU and memory subsystem .................................................................................................................................8

1.1.1 CPU .......................................................................................................................................................................8

1.1.2 Flash .....................................................................................................................................................................8

1.1.3 SRAM.....................................................................................................................................................................8

1.1.4 SROM ....................................................................................................................................................................8

1.2 System resources....................................................................................................................................................8

1.2.1 Power system.......................................................................................................................................................8

1.2.2 Clock system ........................................................................................................................................................9

1.2.3 IMO clock source ..................................................................................................................................................9

1.2.4 ILO clock source...................................................................................................................................................9

1.2.5 External crystal oscillator (ECO)..........................................................................................................................9

1.2.6 Watch crystal oscillator (WCO)............................................................................................................................9

1.2.7 Watchdog timer....................................................................................................................................................9

1.2.8 Reset ...................................................................................................................................................................10

1.2.9 Voltage reference...............................................................................................................................................10

1.3 Bluetooth® smart radio and subsystem...............................................................................................................11

1.4 Analog blocks ........................................................................................................................................................12

1.4.1 12-bit SAR ADC ...................................................................................................................................................12

1.4.2 Opamps (CTBm block).......................................................................................................................................12

1.4.3 Temperature sensor ..........................................................................................................................................13

1.4.4 Low-power comparators ...................................................................................................................................13

1.5 Fixed-function digital............................................................................................................................................13

1.5.1 Timer/counter/PWM block ................................................................................................................................13

1.5.2 Serial Communication Blocks (SCB) .................................................................................................................13

1.6 GPIO.......................................................................................................................................................................14

1.7 Special-function peripherals................................................................................................................................15

1.7.1 LCD segment drive.............................................................................................................................................15

1.7.2 CAPSENSE™........................................................................................................................................................15

2 Pinouts ........................................................................................................................................16

3 Power ..........................................................................................................................................26

4 Development support ...................................................................................................................27

4.1 Documentation .....................................................................................................................................................27

4.2 Online ....................................................................................................................................................................27

4.3 Tools ......................................................................................................................................................................27

5 Electrical specifications.................................................................................................................28

5.1 Absolute maximum ratings .................................................................................................................................28

5.2 Device level specifications....................................................................................................................................29

5.2.1 GPIO....................................................................................................................................................................32

5.2.2 XRES ...................................................................................................................................................................34

5.3 Analog peripherals................................................................................................................................................35

5.3.1 Opamp................................................................................................................................................................35

5.3.2 Temperature sensor ..........................................................................................................................................38

5.3.3 SAR ADC..............................................................................................................................................................38

5.3.4 CSD .....................................................................................................................................................................39

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Based on Arm® Cortex®-M0

Table of contents

5.4 Digital peripherals.................................................................................................................................................40

5.4.1 Timer ..................................................................................................................................................................40

5.4.2 Counter ..............................................................................................................................................................41

5.4.3 Pulse width modulation (PWM) ........................................................................................................................42

5.4.4 I²C .......................................................................................................................................................................43

5.4.5 LCD direct drive..................................................................................................................................................43

5.4.6 SPI specifications...............................................................................................................................................44

5.5 Memory..................................................................................................................................................................45

5.6 System resources..................................................................................................................................................46

5.6.1 Power-on reset (POR) ........................................................................................................................................46

5.6.2 Voltage monitors ...............................................................................................................................................46

5.6.3 SWD interface ....................................................................................................................................................47

5.6.4 Internal main oscillator .....................................................................................................................................47

5.6.5 Internal low-speed oscillator ...........................................................................................................................48

6 Ordering information ....................................................................................................................53

6.1 Ordering code definitions.....................................................................................................................................54

7 Packaging ....................................................................................................................................55

7.1 WLCSP compatibility ............................................................................................................................................57

8 Acronyms.....................................................................................................................................61

9 Document conventions..................................................................................................................65

9.1 Units of measure ...................................................................................................................................................65

Revision history ..............................................................................................................................66

Datasheet

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PSoC™ 4 MCU with AIROC™ Bluetooth® LE

Based on Arm® Cortex®-M0

Block diagram

CPU & Memory

PSoC™ 4100

SWD / TC

Cortex®

FLASH

SRAM

Up to 32KB

ROM

8 KB

32-bit

M0

Up to 256KB

24 MHz

AHB- Lite

FAST MUL

Read Accelerator

SRAM Controller

ROM Controller

NVIC , IRQMX

System Resources

Power

Sleep Control

WIC

System Interconnect (Single-Layer AHB)

Peripherals

POR

REF

LVD

BOD

PWRSYS

PERI

Peripheral Interconnect ( MMIO )

NVLatches

Boost

Clock

Clock Control

WDT

Programmable

Analog

Bluetooth® Low

Energy Subsystem

IMO

ILO

Bluetooth® LE

Baseband Peripheral

x1

Reset

Reset Control

XRES

1

KB SRAM

GFSK Modem

SAR

( 12-bit)

Test

DFT Logic

DFT Analog

2.4 GHz

GFSK

Radio

SMX

CTBm

2x Opamp

x1

Port Interface

I/O: Antenna / Power / Crystal

Power Modes

High-Speed I /O Matrix

36 x GPIOs

Active / Sleep

Deep Sleep

Hibernate

I/ O Subsystem

The PSoC™ 4 CY8C41xx-BL MCU with AIROC™ Bluetooth® LE devices include extensive support for programming,

testing, debugging, and tracing both hardware and firmware.

The Arm® SWD interface supports all programming and debug features of the device.

Complete debug-on-chip functionality enables full-device debugging in the final system using the standard

production device. It does not require special interfaces, debugging pods, simulators, or emulators. Only the

standard programming connections are required to fully support debugging.

The PSoC™ Creator IDE provides fully integrated programming and debugging support for the PSoC™ 4

CY8C41xx-BL MCU with AIROC™ Bluetooth® LE devices. The SWD interface is fully compatible with

industry-standard third-party tools. With the ability to disable debug features, very robust flash protection, and

allowing customer-proprietary functionality to be implemented in on-chip programmable blocks, the PSoC™ 4

CY8C41xx-BL MCU with AIROC™ Bluetooth® LE family provides a level of security not possible with multi-chip

application solutions or with microcontrollers.

Debug circuits are enabled by default and can only be disabled in firmware. If not enabled, the only way to

re-enable them is to erase the entire device, clear flash protection, and reprogram the device with the new

firmware that enables debugging.

Additionally, all device interfaces can be permanently disabled (device security) for applications concerned

about phishing attacks due to a maliciously reprogrammed device or attempts to defeat security by starting and

interrupting flash programming sequences. Because all programming, debug, and test interfaces are disabled

when maximum device security is enabled, PSoC™ 4 CY8C41xx-BL MCU with AIROC™ Bluetooth® LE with device

security enabled may not be returned for failure analysis. This is a trade-off the PSoC™ 4 CY8C41xx-BL MCU with

AIROC™ Bluetooth® LE allows the customer to make.

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PSoC™ 4 MCU with AIROC™ Bluetooth® LE

Based on Arm® Cortex®-M0

Functional definition

1

Functional definition

CPU and memory subsystem

CPU

1.1

1.1.1

The Cortex®-M0 CPU in the PSoC™ 4 CY8C41xx-BL MCU with AIROC™ Bluetooth® LE is part of the 32-bit MCU

subsystem, which is optimized for low-power operation with extensive clock gating. It mostly uses 16-bit

instructions and executes a subset of the Thumb-2 instruction set. This enables fully compatible binary upward

migration of the code to higher-performance processors such as Cortex®-M3 and M4. The implementation

includes a hardware multiplier that provides a 32-bit result in one cycle. It includes a nested vectored interrupt

controller (NVIC) block with 32 interrupt inputs and a wakeup interrupt controller (WIC). The WIC can wake the

processor up from the Deep-Sleep mode, allowing power to the main processor to be switched off when the chip

is in the Deep-Sleep mode. The Cortex®-M0 CPU provides a nonmaskable interrupt (NMI) input, which is made

available to the user when it is not in use for system functions requested by the user.

The CPU also includes an SWD interface, which is a 2-wire form of JTAG; the debug configuration used for PSoC™

4 CY8C41xx-BL MCU with AIROC™ Bluetooth® LE has four break-point (address) comparators and two watchpoint

(data) comparators.

1.1.2

Flash

The PSoC™ 4 CY8C41xx-BL MCU with AIROC™ Bluetooth® LE device has a 128/256-KB flash module with a flash

accelerator, tightly coupled to the CPU to improve average access times from the flash block. The flash block is

designed to deliver with 0 WS access time at 24 MHz. The flash accelerator delivers 85% of single-cycle SRAM

access performance on average. Part of the flash module can be used to emulate EEPROM operation if required.

During flash erase and programming operations (the maximum erase and program time is 20 ms per row), the

Internal Main Oscillator (IMO) will be set to 48 MHz for the duration of the operation. This also applies to the

emulated EEPROM. System design must take this into account because peripherals operating from different IMO

frequencies will be affected. If it is critical that peripherals continue to operate with no change during flash

programming, always set the IMO to 48 MHz and derive peripheral clocks by dividing down from this frequency

1.1.3

SRAM

SRAM memory is retained during Hibernate.

1.1.4

SROM

The 8-KB supervisory ROM contains a library of executable functions for flash programming. These functions are

accessed through supervisory calls (SVC) and enable in-system programming of the flash memory.

1.2

1.2.1

System resources

Power system

The power system is described in detail in the “Power” section on page 26. It provides an assurance that the

voltage levels are as required for the respective modes, and can either delay the mode entry (on power-on reset

(POR), for example) until voltage levels are as required or generate resets (brownout detect (BOD)) or interrupts

when the power supply reaches a particular programmable level between 1.8 V and 4.5 V (low-voltage detect

(LVD)). PSoC™ 4 CY8C41xx-BL MCU with AIROC™ Bluetooth® LE operates with a single external supply (1.71 V to

5.5 V without radio and 1.9 V to 5.5 V with radio). The device has five different power modes; transitions between

these modes are managed by the power system. PSoC™ 4 CY8C41xx-BL MCU with AIROC™ Bluetooth® LE provides

Sleep, Deep-Sleep, Hibernate, and Stop low-power modes. See the Technical Reference Manual for more details.

Datasheet

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PSoC™ 4 MCU with AIROC™ Bluetooth® LE

Based on Arm® Cortex®-M0

Functional definition

1.2.2

Clock system

The PSoC™ 4 CY8C41xx-BL MCU with AIROC™ Bluetooth® LE clock system is responsible for providing clocks to all

subsystems that require clocks and for switching between different clock sources without glitching. In addition,

the clock system ensures that no metastable conditions occur.

The clock system for PSoC™ 4 CY8C41xx-BL MCU with AIROC™ Bluetooth® LE consists of the internal main

oscillator (IMO), the internal low-speed oscillator (ILO), the 24-MHz external crystal oscillator (ECO) and the

32-kHz watch crystal oscillator (WCO). In addition, an external clock may be supplied from a pin.

1.2.3

IMO clock source

The IMO is the primary source of internal clocking in PSoC™ 4 CY8C41xx-BL MCU with AIROC™ Bluetooth® LE. It is

trimmed during testing to achieve the specified accuracy. Trim values are stored in nonvolatile latches (NVL).

Additional trim settings from flash can be used to compensate for changes. The IMO default frequency is 24 MHz

and it can be adjusted between 3 MHz to 48 MHz in steps of 1 MHz. The IMO tolerance with Infineon-provided

calibration settings is ±2%.

1.2.4

ILO clock source

The ILO is a very-low-power oscillator, which is primarily used to generate clocks for the peripheral operation in

the Deep-Sleep mode. ILO-driven counters can be calibrated to the IMO to improve accuracy. A software

component is provided, which does the calibration.

1.2.5

External crystal oscillator (ECO)

The ECO is used as the active clock for the Bluetooth® LE SS to meet the ±50-ppm clock accuracy of the

Bluetooth® 4.2 Specification. PSoC™ 4 CY8C41xx-BL MCU with AIROC™ Bluetooth® LE includes a tunable load

capacitor to tune the crystal-clock frequency by measuring the actual clock frequency. The high-accuracy ECO

clock can also be used as a system clock.

1.2.6

Watch crystal oscillator (WCO)

The WCO is used as the sleep clock for the BLESS to meet the ±500-ppm clock accuracy of the Bluetooth® 4.2

Specification. The sleep clock provides an accurate sleep timing and enables wakeup at the specified

advertisement and connection intervals. The WCO output can be used to realize the real-time clock (RTC)

function in firmware.

1.2.7

Watchdog timer

A watchdog timer is implemented in the clock block running from the ILO or from the WCO; this allows the

watchdog operation during Deep-Sleep and generates a watchdog reset if not serviced before the timeout

occurs. The watchdog reset is recorded in the Reset Cause register. With the WCO and firmware, an accurate

real-time clock (within the bounds of the 32-kHz crystal accuracy) can be realized.

Datasheet

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PSoC™ 4 MCU with AIROC™ Bluetooth® LE

Based on Arm® Cortex®-M0

Functional definition

HFCLK

ECO

Prescaler

SYSCLK

Divider

/2ⁿ(n=0..3)

Divider 0

(/16)

PER0_CLK

IMO

Divider 9

(/16)

EXTCLK

Fractional

Divider 0

(/16.5)

PER15_CLK

LFCLK

Fractional

Divider1

(/16.5)

WCO

ILO

Figure 2

PSoC™ 4 CY8C41xx-BL MCU with AIROC™ Bluetooth® LE MCU clocking architecture

The HFCLK signal can be divided down (see Figure 2) to generate synchronous clocks for the UDBs, and the

analog and digital peripherals. There are a total of 12 clock dividers for PSoC™ 4 CY8C41xx-BL MCU with AIROC™

Bluetooth® LE: ten with 16-bit divide capability and two with 16.5-bit divide capability. This allows the generation

of 16 divided clock signals, which can be used by peripheral blocks. The analog clock leads the digital clocks to

allow analog events to occur before the digital clock-related noise is generated. The 16-bit and 16.5-bit dividers

allow a lot of flexibility in generating fine-grained frequency values and are fully supported in PSoC™ Creator.

1.2.8

Reset

PSoC™ 4 CY8C41xx-BL MCU with AIROC™ Bluetooth® LE can be reset from a variety of sources including a software

reset. Reset events are asynchronous and guarantee reversion to a known state. The reset cause is recorded in a

register, which is sticky through resets and allows the software to determine the cause of the reset. An XRES pin

is reserved for an external reset to avoid complications with the configuration and multiple pin functions during

power-on or reconfiguration. The XRES pin has an internal pull-up resistor that is always enabled.

1.2.9

Voltage reference

The PSoC™ 4 CY8C41xx-BL MCU with AIROC™ Bluetooth® LE reference system generates all internally required

references. A one-percent voltage reference spec is provided for the 12-bit ADC. To allow better signal-to-noise

ratios (SNR) and better absolute accuracy, it is possible to bypass the internal reference using a REF pin or use an

external reference for the SAR. See Table 21 for details.

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PSoC™ 4 MCU with AIROC™ Bluetooth® LE

Based on Arm® Cortex®-M0

Functional definition

1.3

Bluetooth® smart radio and subsystem

PSoC™ 4 CY8C41xx-BL MCU with AIROC™ Bluetooth® LE incorporates a Bluetooth® Smart subsystem that contains

the Physical Layer (PHY) and Link Layer (LL) engines with an embedded AES-128 security engine. The physical

layer consists of the digital PHY and the RF transceiver that transmits and receives GFSK packets at 1 Mbps over

a 2.4-GHz ISM band, which is compliant with Bluetooth® Smart Bluetooth® Specification 4.2. The baseband

controller is a composite hardware and firmware implementation that supports both master and slave modes.

Key protocol elements, such as HCI and link control, are implemented in firmware. Time-critical functional

blocks, such as encryption, CRC, data whitening, and access code correlation, are implemented in hardware (in

the LL engine).

The RF transceiver contains an integrated balun, which provides a single-ended RF port pin to drive a 50-Ω

antenna via a matching/filtering network. In the receive direction, this block converts the RF signal from the

antenna to a digital bit stream after performing GFSK demodulation. In the transmit direction, this block

performs GFSK modulation and then converts a digital baseband signal to a radio frequency before transmitting

it to air through the antenna.

The Bluetooth® smart radio and subsystem (BLESS) requires a 1.9-V minimum supply (the range varies from 1.9 V

to 5.5 V).

Key features of BLESS are as follows:

• Master and slave single-mode protocol stack with logical link control and adaptation protocol (L2CAP), attribute

(ATT), and security manager (SM) protocols

• API access to generic attribute profile (GATT), generic access profile (GAP), and L2CAP

• L2CAP connection-oriented channel

• GAP features

- Broadcaster, Observer, Peripheral, and Central roles

- Security mode 1: Level 1, 2, 3, and 4

- Security mode 2: Level 1 and 2

- User-defined advertising data

- Multiple bond support

• GATT features

- GATT client and server

- Supports GATT sub-procedures

- 32-bit universally unique identifier (UUID)

• Security Manager (SM)

- Pairing methods: Just works, Passkey Entry, Out of Band, and Numeric Comparison

- Authenticated man-in-the-middle (MITM) protection and data signing

- LE secure connections (Bluetooth® 4.2 feature)

• Link layer (LL)

- Master and Slave roles

- 128-bit AES engine

- Encryption

- Low-duty cycle advertising

- LE ping

- LE data packet length extension (Bluetooth® 4.2 feature)

- Link layer privacy (with extended scanning filter policy, Bluetooth® 4.2 feature)

• Supports all SIG-adopted Bluetooth® LE profiles

Datasheet

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PSoC™ 4 MCU with AIROC™ Bluetooth® LE

Based on Arm® Cortex®-M0

Functional definition

1.4

Analog blocks

12-bit SAR ADC

1.4.1

The 12-bit, 806 ksps SAR ADC can operate at a maximum clock rate of 14.508 MHz and requires a minimum of 18

clocks at that frequency to do a 12-bit conversion.

The block functionality is augmented for the user by adding a reference buffer to it (trimmable to ±1%) and by

providing the choice of three internal voltage references, V_DD, V_DD/2, and V_REF(nominally 1.024 V), as well as an

external reference through a REF pin. The sample-and-hold (S/H) aperture is programmable; it allows the gain

bandwidth requirements of the amplifier driving the SAR inputs, which determine its settling time, to be relaxed

if required. System performance will be 65 dB for true 12-bit precision if appropriate references are used and

system noise levels permit it. To improve the performance in noisy conditions, it is possible to provide an external

bypass (through a fixed pin location) for the internal reference amplifier.

The SAR is connected to a fixed set of pins through an 8-input sequencer. The sequencer cycles through the

selected channels autonomously (sequencer scan) and does so with zero switching overhead (that is, the

aggregate sampling bandwidth is equal to 806 ksps whether it is for a single channel or distributed over several

channels). The sequencer switching is effected through a state machine or through firmware-driven switching. A

feature provided by the sequencer is the buffering of each channel to reduce CPU interrupt-service requirements.

To accommodate signals with varying source impedances and frequencies, it is possible to have different sample

times programmable for each channel. Also, the signal range specification through a pair of range registers (low-

and high-range values) is implemented with a corresponding out-of-range interrupt if the digitized value exceeds

the programmed range; this allows fast detection of out-of-range values without having to wait for a sequencer

scan to be completed and the CPU to read the values and check for out-of-range values in software.

The SAR is able to digitize the output of the on-chip temperature sensor for calibration and other

temperature-dependent functions. The SAR is not available in Deep-Sleep and Hibernate modes as it requires a

high-speed clock (up to 18 MHz). The SAR operating range is 1.71 V to 5.5 V.

AHB System Bus and Programmable Logic

Interconnect

SAR Sequencer

Sequencing

and Control

Data and

Status Flags

POS

SARADC

NEG

External

Reference

Selection

and

Bypass

(optional)

VDDD

VREF

VDD/2

Inputs from other Ports

Figure 3

SAR ADC system diagram

1.4.2

Opamps (CTBm block)

PSoC™ 4 CY8C41xx-BL MCU with AIROC™ Bluetooth® LE has two opamps with comparator modes, which allow

most common analog functions to be performed on-chip, eliminating external components. PGAs, voltage

buffers, filters, transimpedance amplifiers, and other functions can be realized with external passives saving

power, cost, and space. The on-chip opamps are designed with enough bandwidth to drive the sample-and-hold

circuit of the ADC without requiring external buffering.

Datasheet

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PSoC™ 4 MCU with AIROC™ Bluetooth® LE

Based on Arm® Cortex®-M0

Functional definition

1.4.3

Temperature sensor

PSoC™ 4 CY8C41xx-BL MCU with AIROC™ Bluetooth® LE has an on-chip temperature sensor. This consists of a

diode, which is biased by a current source that can be disabled to save power. The temperature sensor is

connected to the ADC, which digitizes the reading and produces a temperature value by using a Infineon-supplied

software that includes calibration and linearization.

1.4.4

Low-power comparators

PSoC™ 4 CY8C41xx-BL MCU with AIROC™ Bluetooth® LE has a pair of low-power comparators, which can also

operate in Deep-Sleep and Hibernate modes. This allows the analog system blocks to be disabled while retaining

the ability to monitor external voltage levels during low-power modes. The comparator outputs are normally

synchronized to avoid metastability unless operating in an asynchronous power mode (Hibernate) where the

system wake-up circuit is activated by a comparator-switch event.

1.5

Fixed-function digital

1.5.1

Timer/counter/PWM block

The timer/counter/PWM block consists of four 16-bit counters with user-programmable period length. There is a

capture register to record the count value at the time of an event (which may be an I/O event), a period register

which is used to either stop or auto-reload the counter when its count is equal to the period register, and compare

registers to generate compare value signals which are used as PWM duty cycle outputs. The block also provides

true and complementary outputs with programmable offset between them to allow the use as deadband

programmable complementary PWM outputs. It also has a kill input to force outputs to a predetermined state;

for example, this is used in motor-drive systems when an overcurrent state is indicated and the PWMs driving the

FETs need to be shut off immediately with no time for software intervention.

1.5.2

Serial Communication Blocks (SCB)

PSoC™ 4 CY8C41xx-BL MCU with AIROC™ Bluetooth® LE has two SCBs, each of which can implement an I²C, UART,

or SPI interface.

I²C mode: The hardware I²C block implements a full multi-master and slave interface (it is capable of multimaster

arbitration). This block is capable of operating at speeds of up to 1 Mbps (Fast-Mode Plus) and has flexible

buffering options to reduce the interrupt overhead and latency for the CPU. It also supports EzI²C that creates a

mailbox address range in the memory of PSoC™ 4 CY8C41xx-BL MCU with AIROC™ Bluetooth® LE and effectively

reduces the I²C communication to reading from and writing to an array in the memory. In addition, the block

supports an 8-deep FIFO for receive and transmit, which, by increasing the time given for the CPU to read the

data, greatly reduces the need for clock stretching caused by the CPU not having read the data on time. The FIFO

mode is available in all channels and is very useful in the absence of DMA.

The I²C peripheral is compatible with I²C Standard-mode, Fast-mode, and Fast-Mode Plus devices as defined in

the NXP I²C-bus specification and user manual (UM10204). The I²C bus I/O is implemented with GPIOs in

open-drain modes.

SCB1 is fully compliant with Standard-mode (100 kHz), Fast-mode (400 kHz), and Fast-Mode Plus (1 MHz) I²C

signaling specifications when routed to GPIO pins P5.0 and P5.1, except for hot swap capability during I2C active

communication. The remaining GPIOs do not meet the hot-swap specification (V_DDoff; draw < 10-μA current) for

Fast mode and Fast-Mode Plus, I_OLspec (20 mA) for Fast-Mode Plus, hysteresis spec (0.05 × V_DD) for Fast mode

and Fast-Mode Plus, and minimum fall-time spec for Fast mode and Fast-Mode Plus.

• GPIO cells, including P5.0 and P5.1, cannot be hot-swapped or powered up independent of the rest of the I²C

system.

• The GPIO pins P5.0 and P5.1 are overvoltage-tolerant but cannot be hot-swapped or powered up independent

of the rest of the I²C system.

• Fast-Mode Plus has an I_OLspecification of 20 mA at a V_OLof 0.4 V. The GPIO cells can sink a maximum of 8 mA

I_OLwith a V_OLmaximum of 0.6 V.

Datasheet

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PSoC™ 4 MCU with AIROC™ Bluetooth® LE

Based on Arm® Cortex®-M0

Functional definition

• Fast mode and Fast-Mode Plus specify minimum Fall times, which are not met with the GPIO cell; the

Slow-Strong mode can help meet this spec depending on the bus load.

UART mode: This is a full-feature UART operating at up to 1 Mbps. It supports automotive single-wire interface

(LIN), infrared interface (IrDA), and SmartCard (ISO7816) protocols, all of which are minor variants of the basic

UART protocol. In addition, it supports the 9-bit multiprocessor mode that allows the addressing of peripherals

connected over common RX and TX lines. Common UART functions such as parity error, break detect, and frame

error are supported. An 8-deep FIFO allows much greater CPU service latencies to be tolerated.

SPI mode: The SPI mode supports full Motorola SPI, TI Secure Simple Pairing (SSP) (essentially adds a start pulse

that is used to synchronize SPI Codecs), and National Microwire (half-duplex form of SPI). The SPI block can use

the FIFO for transmit and receive.

1.6

GPIO

PSoC™ 4 CY8C41xx-BL MCU with AIROC™ Bluetooth® LE has 36 GPIOs. The GPIO block implements the following:

• Eight drive-strength modes:

- Analog input mode (input and output buffers disabled)

- Input only

- Weak pull-up with strong pull-down

- Strong pull-up with weak pull-down

- Open drain with strong pull-down

- Open drain with strong pull-up

- Strong pull-up with strong pull-down

- Weak pull-up with weak pull-down

• Input threshold select (CMOS or LVTTL)

• Pins 0 and 1 of Port 5 are overvoltage-tolerant Pins

• Individual control of input and output buffer enabling/disabling in addition to drive-strength modes

• Hold mode for latching the previous state (used for retaining the I/O state in Deep-Sleep and Hibernate modes)

• Selectable slew rates for dV/dt-related noise control to improve EMI

The pins are organized in logical entities called ports, which are 8-bit in width. During power-on and reset, the

blocks are forced to the disable state so as not to crowbar any inputs and/or cause excess turn-on current. A

multiplexing network known as a high-speed I/O matrix (HSIOM) is used to multiplex between various signals that

may connect to an I/O pin. Pin locations for fixed-function peripherals are also fixed to reduce internal

multiplexing complexity (these signals do not go through the DSI network). DSI signals are not affected by this

and any pin may be routed to any UDB through the DSI network.

Data output and pin-state registers store, respectively, the values to be driven on the pins and the states of the

pins themselves.Every I/O pin can generate an interrupt if so enabled and each I/O port has an interrupt request

(IRQ) and interrupt service routine (ISR) vector associated with it (5 for PSoC™ 4 CY8C41xx-BL MCU with AIROC™

Bluetooth® LE since it has 4.5 ports).

Datasheet

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PSoC™ 4 MCU with AIROC™ Bluetooth® LE

Based on Arm® Cortex®-M0

Functional definition

1.7

Special-function peripherals

LCD segment drive

1.7.1

PSoC™ 4 CY8C41xx-BL MCU with AIROC™ Bluetooth® LE has an LCD controller, which can drive up to four

commons and up to 32 segments. It uses full digital methods to drive the LCD segments requiring no generation

of internal LCD voltages. The two methods used are referred to as digital correlation and PWM.

The digital correlation method modulates the frequency and levels of the common and segment signals to

generate the highest RMS voltage across a segment to light it up or to keep the RMS signal zero. This method is

good for STN displays but may result in reduced contrast with TN (cheaper) displays.

The PWM method drives the panel with PWM signals to effectively use the capacitance of the panel to provide the

integration of the modulated pulse-width to generate the desired LCD voltage. This method results in higher

power consumption but can result in better results when driving TN displays. LCD operation is supported during

Deep-Sleep mode, refreshing a small display buffer (four bits; one 32-bit register per port).

1.7.2

CAPSENSE™

CAPSENSE™ is supported on all pins in PSoC™ 4 CY8C41xx-BL MCU with AIROC™ Bluetooth® LE through a

capacitive sigma-delta (CSD) block that can be connected to any pin through an analog mux bus that any GPIO

pin can be connected to via an Analog switch. CAPSENSE™ function can thus be provided on any pin or group of

pins in a system under software control. A component is provided for the CAPSENE™ block to make it easy for the

user.

The shield voltage can be driven on another mux bus to provide liquid-tolerance capability. Liquid tolerance is

provided by driving the shield electrode in phase with the sense electrode to keep the shield capacitance from

attenuating the sensed input.

The CAPSENSE™ block has two IDACs which can be used for general purposes if CAPSENSE™ is not being used

(both IDACs are available in that case) or if CAPSENSE™ is used without liquid tolerance (one IDAC is available).

Datasheet

15

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PSoC™ 4 MCU with AIROC™ Bluetooth® LE

Based on Arm® Cortex®-M0

Pinouts

2

Pinouts

Table 1, Table 2, and Table 3 show pin list for 56-pin QFN, 68-ball WLCSP, and 76-ball WLCSP packages of PSoC™

4 CY8C41xx-BL MCU with AIROC™ Bluetooth® LE respectively. Port 2 consists of the high-speed analog inputs for

the SAR mux. All pins support CSD CAPSENSE™ and analog mux bus connections.

Table 1

PSoC™ 4 CY8C41xx-BL MCU with AIROC™ Bluetooth® LE pin list

(56-pin QFN package)

1

2

3

4

Name

VDDD

XTAL32O/P6.0

XTAL32I/P6.1

XRES

P4.0

Type

POWER

CLOCK

RESET

GPIO

Description

1.71-V to 5.5-V digital supply

32.768-kHz crystal

32.768-kHz crystal or external clock input

Reset, active LOW

5

Port 4 Pin 0, lcd, csd

6

P4.1

GPIO

Port 4 Pin 1, lcd, csd

7

8

9

P5.0

P5.1

GPIO

Port 5 Pin 0, lcd, csd, overvoltage-tolerant

Port 5 Pin 1, lcd, csd, overvoltage-tolerant

Digital ground

1.9-V to 5.5-V radio supply

Antenna shielding ground

Antenna pin

Antenna shielding ground

1.9-V to 5.5-V radio supply

24-MHz crystal or external clock input

24-MHz crystal

1.9-V to 5.5-V radio supply

Port 0 Pin 0, lcd, csd

Port 0 Pin 1, lcd, csd

Port 0 Pin 2, lcd, csd

Port 0 Pin 3, lcd, csd

1.71-V to 5.5-V digital supply

Port 0 Pin 4, lcd, csd

Port 0 Pin 5, lcd, csd

Port 0 Pin 6, lcd, csd

Port 0 Pin 7, lcd, csd

Port 1 Pin 0, lcd, csd

Port 1 Pin 1, lcd, csd

Port 1 Pin 2, lcd, csd

Port 1 Pin 3, lcd, csd

VSSD

VDDR

GANT1

ANT

GANT2

VDDR

XTAL24I

XTAL24O

VDDR

P0.0

P0.1

P0.2

P0.3

VDDD

P0.4

GROUND

POWER

GROUND

ANTENNA

GROUND

POWER

CLOCK

POWER

GPIO

POWER

GPIO

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

P0.5

P0.6

P0.7

P1.0

P1.1

P1.2

P1.3

P1.4

GPIO

Port 1 Pin 4, lcd, csd

Port 1 Pin 5, lcd, csd

Port 1 Pin 6, lcd, csd

Port 1 Pin 7, lcd, csd

P1.5

P1.6

P1.7

GPIO

Datasheet

16

002-23052 Rev. *B

2023-03-29

PSoC™ 4 MCU with AIROC™ Bluetooth® LE

Based on Arm® Cortex®-M0

Pinouts

Table 1

PSoC™ 4 CY8C41xx-BL MCU with AIROC™ Bluetooth® LE pin list

(56-pin QFN package) ^(continued)

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

Name

VDDA

P2.0

P2.1

P2.2

P2.3

P2.4

P2.5

P2.6

P2.7

VREF

VDDA

P3.0

P3.1

P3.2

P3.3

P3.4

P3.5

P3.6

P3.7

VSSA

VCCD

EPAD

Type

POWER

GPIO

REF

POWER

GPIO

Description

1.71-V to 5.5-V analog supply

Port 2 Pin 0, lcd, csd

Port 2 Pin 1, lcd, csd

Port 2 Pin 2, lcd, csd

Port 2 Pin 3, lcd, csd

Port 2 Pin 4, lcd, csd

Port 2 Pin 5, lcd, csd

Port 2 Pin 6, lcd, csd

Port 2 Pin 7, lcd, csd

External reference input or bypass capacitor

1.71-V to 5.5-V analog supply

Port 3 Pin 0, lcd, csd

Port 3 Pin 1, lcd, csd

Port 3 Pin 2, lcd, csd

Port 3 Pin 3, lcd, csd

Port 3 Pin 4, lcd, csd

Port 3 Pin 5, lcd, csd

Port 3 Pin 6, lcd, csd

Port 3 Pin 7, lcd, csd

Analog ground

Regulated 1.8-V supply, connect to 1-µF capacitor

Ground paddle for the QFN package

GPIO

GROUND

POWER

GROUND

Table 2

PSoC™ 4 CY8C41xx-BL MCU with AIROC™ Bluetooth® LE pin list

(68-ball WLCSP package)

A1

A2

A3

A4

A5

A6

A7

A8

B1

B2

B3

B4

B5

Name

VREF

VSSA

P3.3

Type

REF

GROUND

GPIO

Pin description

External reference input or bypass capacitor

Analog ground

Port 3 Pin 3, lcd, csd

Port 3 Pin 7, lcd, csd

Digital ground

Analog ground

Regulated 1.8-V supply, connect to 1-μF capacitor

1.71-V to 5.5-V radio supply

Port 2 Pin 3, lcd, csd

P3.7

GPIO

VSSD

VSSA

VCCD

VDDD

P2.3

VSSA

P2.7

P3.4

GROUND

POWER

GPI

GROUND

GPIO

Analog ground

Port 2 Pin 7, lcd, csd

Port 3 Pin 4, lcd, csd

Port 3 Pin 5, lcd, csd

P3.5

GPIO

Datasheet

17

002-23052 Rev. *B

2023-03-29

PSoC™ 4 MCU with AIROC™ Bluetooth® LE

Based on Arm® Cortex®-M0

Pinouts

Table 2

PSoC™ 4 CY8C41xx-BL MCU with AIROC™ Bluetooth® LE pin list

(68-ball WLCSP package) ^(continued)

B6

B7

B8

C1

C2

C3

C4

C5

C6

C7

C8

D1

D2

D3

D4

D5

D6

D7

D8

E1

E2

E3

E4

E5

E6

E7

E8

F1

F2

F3

F4

F5

F6

F7

F8

G1

G2

G3

G4

Name

P3.6

XTAL32I/P6.1

XTAL32O/P6.0

VSSA

P2.2

Type

GPIO

CLOCK

GROUND

GPIO

RESET

GPIO

POWER

GPIO

GROUND

GPIO

GROUND

GPIO

GROUND

POWER

GPIO

Pin description

Port 3 Pin 6, lcd, csd

32.768-kHz crystal or external clock input

32.768-kHz crystal

Analog ground

Port 2 Pin 2, lcd, csd

Port 2 Pin 6, lcd, csd

Port 3 Pin 0, lcd, csd

Port 3 Pin 1, lcd, csd

Port 3 Pin 2, lcd, csd

Reset, active LOW

Port 4 Pin 0, lcd, csd

Port 1 Pin 7, lcd, csd

1.71-V to 5.5-V analog supply

Port 2 Pin 0, lcd, csd

Port 2 Pin 1, lcd, csd

Port 2 Pin 5, lcd, csd

Digital ground

Port 4 Pin 1, lcd, csd

Port 5 Pin 0, lcd, csd

Port 1 Pin 2, lcd, csd

Port 1 Pin 3, lcd, csd

Port 1 Pin 4, lcd, csd

Port 1 Pin 5, lcd, csd

Port 1 Pin 6, lcd, csd

Port 2 Pin 4, lcd, csd

Port 5 Pin 1, lcd, csd

Digital ground

P2.6

P3.0

P3.1

P3.2

XRES

P4.0

P1.7

VDDA

P2.0

P2.1

P2.5

VSSD

P4.1

P5.0

P1.2

P1.3

P1.4

P1.5

P1.6

P2.4

P5.1

VSSD

P0.7

P0.3

P1.0

P1.1

VSSR

VDDR

P0.6

Digital ground

Port 0 Pin 7, lcd, csd

Port 0 Pin 3, lcd, csd

Port 1 Pin 0, lcd, csd

Port 1 Pin 1, lcd, csd

Radio ground

1.9-V to 5.5-V radio supply

Port 0 Pin 6, lcd, csd

1.71-V to 5.5-V digital supply

Port 0 Pin 2, lcd, csd

Digital ground

VDDD

P0.2

VSSD

POWER

GPIO

GROUND

Datasheet

18

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2023-03-29

PSoC™ 4 MCU with AIROC™ Bluetooth® LE

Based on Arm® Cortex®-M0

Pinouts

Table 2

PSoC™ 4 CY8C41xx-BL MCU with AIROC™ Bluetooth® LE pin list

(68-ball WLCSP package) ^(continued)

G5

G6

G7

G8

H1

H2

H3

H4

H5

H6

H7

J1

Name

VSSR

GANT

VSSR

P0.5

Type

GROUND

GPIO

Pin description

Radio ground

Antenna shielding ground

Radio ground

Port 0 Pin 5, lcd, csd

Port 0 Pin 1, lcd, csd

24-MHz crystal

P0.1

GPIO

XTAL24O

XTAL24I

VSSR

ANT

P0.4

P0.0

VDDR

No Connect

CLOCK

GROUND

ANTENNA

GPIO

24-MHz crystal or external clock input

Radio ground

Antenna pin

Port 0 Pin 4, lcd, csd

Port 0 Pin 0, lcd, csd

1.9-V to 5.5-V radio supply

-

J2

J3

J6

J7

GPIO

POWER

-

Table 3

PSoC™ 4 CY8C41xx-BL MCU with AIROC™ Bluetooth® LE pin list

(76-ball WLCSP package)

Name

NC

Type

NC

Description

A1

A2

A3

A4

A5

A6

A7

A8

A9

B1

B2

B3

B4

B5

B6

B7

B8

B9

C1

Do not connect

VREF

VSSA

P3.3

P3.7

VSSD

VSSA

VCCD

VDDD

NB

P2.3

VSSA

P2.7

P3.4

P3.5

P3.6

REF

GROUND

GPIO

External reference input or bypass capacitor

Analog ground

Port 3 Pin 3, analog/digital/lcd/csd

Port 3 Pin 7, analog/digital/lcd/csd

Digital ground

GPIO

GROUND

POWER

NO BALL

GPIO

GROUND

GPIO

Analog ground

Regulated 1.8-V supply, connect to 1-μF capacitor

1.71-V to 5.5-V digital supply

No Ball

Port 2 Pin 3, analog/digital/lcd/csd

Analog ground

Port 2 Pin 7, analog/digital/lcd/csd

Port 3 Pin 4, analog/digital/lcd/csd

Port 3 Pin 5, analog/digital/lcd/csd

Port 3 Pin 6, analog/digital/lcd/csd

32.768-kHz crystal or external clock input

32.768-kHz crystal

GPIO

XTAL32I/P6.1

XTAL32O/P6.0

NC

CLOCK

NC

Do not connect

Datasheet

19

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PSoC™ 4 MCU with AIROC™ Bluetooth® LE

Based on Arm® Cortex®-M0

Pinouts

Table 3

PSoC™ 4 CY8C41xx-BL MCU with AIROC™ Bluetooth® LE pin list

(76-ball WLCSP package) ^(continued)

Name

VSSA

P2.2

P2.6

P3.0

P3.1

P3.2

XRES

P4.0

NC

Type

GROUND

GPIO

RESET

GPIO

NC

Description

C2

C3

C4

C5

C6

C7

C8

C9

D1

D2

D3

D4

D5

D6

D7

D8

D9

E1

E2

E3

E4

E5

E6

E7

E8

E9

F1

F2

F3

F4

F5

F6

F7

F8

F9

G1

G2

G3

G4

Analog ground

Port 2 Pin 2, analog/digital/lcd/csd

Port 2 Pin 6, analog/digital/lcd/csd

Port 3 Pin 0, analog/digital/lcd/csd

Port 3 Pin 1, analog/digital/lcd/csd

Port 3 Pin 2, analog/digital/lcd/csd

Reset, active LOW

Port 4 Pin 0, analog/digital/lcd/csd

Do not connect

P1.7

VDDA

P2.0

P2.1

P2.5

VSSD

P4.1

P5.0

NC

GPIO

POWER

GPIO

GROUND

GPIO

Port 1 Pin 7, analog/digital/lcd/csd

1.71-V to 5.5-V analog supply

Port 2 Pin 0, analog/digital/lcd/csd

Port 2 Pin 1, analog/digital/lcd/csd

Port 2 Pin 5, analog/digital/lcd/csd

Digital ground

Port 4 Pin 1, analog/digital/lcd/csd

Port 5 Pin 0, analog/digital/lcd/csd

Do not connect

NC

P1.2

P1.3

P1.4

P1.5

P1.6

P2.4

P5.1

VSSD

NC

GPIO

GROUND

NC

Port 1 Pin 2, analog/digital/lcd/csd

Port 1 Pin 3, analog/digital/lcd/csd

Port 1 Pin 4, analog/digital/lcd/csd

Port 1 Pin 5, analog/digital/lcd/csd

Port 1 Pin 6, analog/digital/lcd/csd

Port 2 Pin 4, analog/digital/lcd/csd

Port 5 Pin 1, analog/digital/lcd/csd

Digital ground

Do not connect

VSSD

P0.7

P0.3

P1.0

P1.1

VSSR

VDDR

NC

GROUND

GPIO

GROUND

POWER

NC

Digital ground

Port 0 Pin 7, analog/digital/lcd/csd

Port 0 Pin 3, analog/digital/lcd/csd

Port 1 Pin 0, analog/digital/lcd/csd

Port 1 Pin 1, analog/digital/lcd/csd

Radio ground

1.9-V to 5.5-V radio supply

Do not connect

P0.6

VDDD

P0.2

GPIO

POWER

GPIO

Port 0 Pin 6, analog/digital/lcd/csd

1.71-V to 5.5-V digital supply

Port 0 Pin 2, analog/digital/lcd/csd

Datasheet

20

002-23052 Rev. *B

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PSoC™ 4 MCU with AIROC™ Bluetooth® LE

Based on Arm® Cortex®-M0

Pinouts

Table 3

PSoC™ 4 CY8C41xx-BL MCU with AIROC™ Bluetooth® LE pin list

(76-ball WLCSP package) ^(continued)

Name

VSSD

VSSR

GANT

VSSR

Type

GROUND

NC

Description

G5

G6

G7

G8

G9

H1

H2

H3

H4

H5

H6

H7

H8

J1

Digital ground

Radio ground

Antenna shielding ground

Radio ground

NC

Do not connect

P0.5

P0.1

XTAL24O

XTAL24I

VSSR

ANT

NC

GPIO

Port 0 Pin 5, analog/digital/lcd/csd

Port 0 Pin 1, analog/digital/lcd/csd

24-MHz crystal

24-MHz crystal or external clock input

Radio ground

Antenna pin

Do not connect

CLOCK

GROUND

ANTENNA

NC

J2

J3

J4

J7

P0.4

P0.0

VDDR

NO CONNECT

GPIO

Port 0 Pin 4, analog/digital/lcd/csd

Port 0 Pin 0, analog/digital/lcd/csd

1.9-V to 5.5-V radio supply

–

POWER

–

J8

High-speed I/O matrix (HSIOM) is a group of high-speed switches that routes GPIOs to the resources inside the

device. These resources include CAPSENSE™, TCPWMs, I²C, SPI, UART, and LCD. HSIOM_PORT_SELx are

32-bit-wide registers that control the routing of GPIOs. Each register controls one port; four dedicated bits are

assigned to each GPIO in the port. This provides up to 16 different options for GPIO routing as shown in Table 4.

Table 4

Value

HSIOM port settings

Description

0

Firmware-controlled GPIO

1

2

3

4

Output is firmware-controlled, but Output Enable (OE) is controlled from DSI.

Both output and OE are controlled from DSI.

Output is controlled from DSI, but OE is firmware-controlled.

Pin is a CSD sense pin

5

Pin is a CSD shield pin

6

Pin is connected to AMUXA

7

Pin is connected to AMUXB

8

Pin-specific Active function #0

9

Pin-specific Active function #1

10

11

12

13

Pin-specific Active function #2

Reserved

Pin is an LCD common pin

Pin is an LCD segment pin

Datasheet

21

002-23052 Rev. *B

2023-03-29

PSoC™ 4 MCU with AIROC™ Bluetooth® LE

Based on Arm® Cortex®-M0

Pinouts

Table 4

Value

HSIOM port settings ^(continued)

Description

14

15

Pin-specific Deep-Sleep function #0

Pin-specific Deep-Sleep function #1

Datasheet

22

002-23052 Rev. *B

2023-03-29

PSoC™ 4 MCU with AIROC™ Bluetooth® LE

Based on Arm® Cortex®-M0

Pinouts

The possible pin connections are shown for all analog and digital peripherals (except the radio, LCD, and CSD

blocks, which were shown in Table 1). A typical system application connection diagram is shown in Figure 4.

VDDA

C1

1.0 uF

C2

1.0 uF

C3

36 pF

C4

18 pF

U1

Y2

2

1

VDDD

1

2

3

4

5

6

7

8

9

10

11

12

13

14

42

41

40

39

38

37

36

35

34

33

32

31

30

29

32.768KHz

VDDD

XTAL32O/P6.0

XTAL32I/P6.1

XRES

P4.0

P4.1

P5.0

P5.1

VSS

VDDR

GANT1

ANT

P2.5

P2.4

P2.3

P2.2

P2.1

P2.0

VDDA

P1.7

P1.6

P1.5

P1.4

P1.3

P1.2

P1.1

ANTENNA

VDDA

^PP^SS^oCoC⁴™^XX4^XX^_X^BX^L-^EBLE

56-QFN

VDDR

C6

GANT2

VDDR

C5

L1

VDDR

Y1

24MHz

4

VDDD

2

Figure 4

System application connection diagram

Datasheet

25

002-23052 Rev. *B

2023-03-29

PSoC™ 4 MCU with AIROC™ Bluetooth® LE

Based on Arm® Cortex®-M0

Power

3

Power

The PSoC™ 4 CY8C41xx-BL MCU with AIROC™ Bluetooth® LE device can be supplied from batteries with a voltage

range of 1.9 V to 5.5 V by directly connecting to the digital supply (VDDD), analog supply (VDDA), and radio supply

(VDDR) pins. Internal LDOs in the device regulate the supply voltage to the required levels for different blocks.

The device has one regulator for the digital circuitry and separate regulators for radio circuitry for noise isolation.

Analog circuits run directly from the analog supply (VDDA) input. The device uses separate regulators for

Deep-Sleep and Hibernate (lowered power supply and retention) modes to minimize the power consumption.

The radio stops working below 1.9 V, but the device continues to function down to 1.71 V without RF. Note that

VDDR must be supplied whenever VDDD is supplied.

Bypass capacitors must be used from VDDx (x = A, D, or R) to ground. The typical practice for systems in this

frequency range is to use a capacitor in the 1-µF range in parallel with a smaller capacitor (for example, 0.1 µF).

Note that these are simply rules of thumb and that, for critical applications, the PCB layout, lead inductance, and

the bypass capacitor parasitic should be simulated to design and obtain optimal bypassing.

Table 6

Power supply

Bypass capacitors

VDDD

VDDA

VDDR

VCCD

0.1-µF ceramic at each pin plus bulk capacitor 1 µF to 10 µF.

1-µF ceramic capacitor at the VCCD pin.

VREF (optional)

The internal bandgap may be bypassed with a 1-µF to 10-µF capacitor.

Datasheet

26

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2023-03-29

PSoC™ 4 MCU with AIROC™ Bluetooth® LE

Based on Arm® Cortex®-M0

Development support

4

Development support

The PSoC™ 4 CY8C41xx-BL MCU with AIROC™ Bluetooth® LE family has a rich set of documentation, development

tools, and online resources to assist you during your development process. See PSoC™ 4 MCU with AIROC™

Bluetooth® LE to find out more.

4.1

Documentation

A suite of documentation supports the PSoC™ 4 CY8C41xx-BL MCU with AIROC™ Bluetooth® LE family to ensure

that you can find answers to your questions quickly. This section contains a list of some of the key documents.

Software user guide: A step-by-step guide for using PSoC™ Creator. The software user guide shows you how the

PSoC™ Creator build process works in detail, how to use source control with PSoC™ Creator, and much more.

Component datasheets: The flexibility of PSoC™ allows the creation of new peripherals (Components) long after

the device has gone into production. Component datasheets provide all of the information needed to select and

use a particular Component, including a functional description, API documentation, example code, and AC/DC

specifications.

Application notes: PSoC™ application notes discuss a particular application of PSoC™ in depth; examples

include creating standard and custom Bluetooth® LE profiles. Application notes often include example projects

in addition to the application note document.

Technical reference manual (TRM): The TRM contains all the technical detail you need to use a PSoC™ device,

including a complete description of all PSoC™ registers. The TRM is available in the Documentation section at

PSoC™ 4 MCU.

4.2

Online

In addition to print documentation, the PSoC™ forums connect you with fellow PSoC™ users and experts in

PSoC™ from around the world, 24 hours a day, 7 days a week.

4.3

Tools

With industry standard cores, programming, and debugging interfaces, the PSoC™ 4 CY8C41xx-BL MCU with

AIROC™ Bluetooth® LE family is part of a development tool ecosystem. See the PSoC™ Creator for the latest

information on the revolutionary, easy to use PSoC™ Creator IDE, supported third party compilers, programmers,

debuggers, and development kits.

Datasheet

27

002-23052 Rev. *B

2023-03-29

PSoC™ 4 MCU with AIROC™ Bluetooth® LE

Based on Arm® Cortex®-M0

Electrical specifications

5

Electrical specifications

5.1

Table 7

Absolute maximum ratings

Absolute maximum ratings^[1]

Details/

Spec ID# Parameter

Description

Min

Typ

Max

Unit

conditions

SID1

SID2

SID3

V_{DDD_ABS}

V_{CCD_ABS}

V_{GPIO_ABS}

I_{GPIO_ABS}

Analog, digital, or radio supply

–0.5

–

6

V

Absolute max

relative to V_SS(V_SSD= V_SSA

)

Direct digital core voltage input

relative to V_SSD

GPIO voltage

–0.5

–

1.95

V

V_DD

+0.5

25

0.5

SID4

SID5

Maximum current per GPIO

GPIO injection current, Max for

V_IH> V_DDD, and Min for V_IL< V_SS

–25

–0.5

–

mA Absolute max

I_{GPIO_in-}

jection

mA Absolute max,

current injected

per pin

BID57

BID58

ESD_HBM Electrostatic discharge human 2200^[2]

body model

ESD_CDM Electrostatic discharge charged

device model

–

V

500

V

BID61

LU

Pin current for latch-up

–200

200

mA

Note

1. Usage above the absolute maximum conditions listed in Table 7 may cause permanent damage to the de-

vice. Exposure to absolute maximum conditions for extended periods of time may affect device reliability.

The maximum storage temperature is 150°C in compliance with JEDEC Standard JESD22-A103, High Tem-

perature Storage Life. When used below absolute maximum conditions but above normal operating condi-

tions, the device may not operate to specification.

2. This does not apply to the RF pins (ANT, XTALI, and XTALO). RF pins (ANT, XTALI, and XTALO) are tested for

500-V HBM.

Datasheet

28

002-23052 Rev. *B

2023-03-29

PSoC™ 4 MCU with AIROC™ Bluetooth® LE

Based on Arm® Cortex®-M0

Electrical specifications

5.2

Device level specifications

All specifications are valid for –40°C  TA  105°C, except where noted. Specifications are valid for 1.71 V to 5.5 V,

except where noted.

Table 8

DC specifications

Details/

Spec ID# Parameter

Description

Min

Typ Max

Unit

conditions

Power supply input voltage (V_DDA

With regulator

enabled

SID6

SID7

V_DD

1.8

–

5.5

V

= V_DDD= V_DD

)

Power supply input voltage

unregulated (V_DDA= V_DDD= V_DD

Internally unregu-

lated supply

1.71

1.9

1.8

1.89

)

SID8

SID8A

V_DDR

Radio supply voltage (Radio ON)

Radio supply voltage (Radio OFF) 1.71

–

5.5

V

Digital regulator output voltage

SID9

V_CCD

–

1.8

1.3

–

V

(for core logic)

Digital regulator output bypass

capacitor

X5R ceramic or

better

SID10

C_VCCD

1

1.6

µF

Active mode, V_DD= 1.71 V to 5.5 V

Execute from flash; CPU at 3 MHz

–

1.7

–

mA T = 25°C,

V_DD= 3.3 V

SID13

I_DD3

SID14

SID15

I_DD4

I_DD5

Execute from flash; CPU at 3 MHz

Execute from flash; CPU at 6 MHz

–

2.5

–

mA T = –40°C to 105°C

mA T = 25°C,

V_DD= 3.3 V

SID16

SID17

I_DD6

I_DD7

Execute from flash; CPU at 6 MHz

Execute from flash; CPU at 12

MHz

–

4

–

mA T = –40°C to 105°C

mA T = 25°C,

V_DD= 3.3 V

SID18

SID19

SID20

SID21

SID22

I_DD8

Execute from flash; CPU at 12

MHz

Execute from flash; CPU at 24

MHz

Execute from flash; CPU at 24

MHz

Execute from flash; CPU at 48

MHz

–

7.1

–

mA T = –40°C to 105°C

I_DD9

mA T = 25°C,

V_DD= 3.3 V

mA T = –40°C to 105°C

I_DD10

I_DD11

I_DD12

13.4

–

mA T = 25°C,

V_DD= 3.3 V

mA T = –40°C to 105°C

Execute from flash; CPU at 48

MHz

Sleep mode, V_DD= 1.8 V to 5.5 V

SID23 I_DD13IMO on

–

mA T = 25°C,

VDD = 3.3 V,

SYSCLK = 3 MHz

Sleep mode, V_DDand V_DDR= 1.9 V to 5.5 V

SID24 I_DD14ECO on

mA T = 25°C,

VDD = 3.3 V,

SYSCLK = 3 MHz

Deep-Sleep mode, V_DD= 1.8 V to 3.6 V

SID25

I_DD15

WDT with WCO on

–

1.3

–

µA

T = 25°C,

V_DD= 3.3 V

SID26

I_DD16

WDT with WCO on

T = –40°C to 105°C

Datasheet

29

002-23052 Rev. *B

2023-03-29

PSoC™ 4 MCU with AIROC™ Bluetooth® LE

Based on Arm® Cortex®-M0

Electrical specifications

Table 8

Spec ID# Parameter

Deep-Sleep mode, V_DD= 3.6 V to 5.5 V

DC specifications ^(continued)

Details/

Description

Min

Typ Max

Unit

conditions

SID27

I_DD17

WDT with WCO on

–

µA

T = 25°C,

V_DD= 5 V

SID28

I_DD18

WDT with WCO on

T = –40°C to 105°C

Deep-Sleep mode, V_DD= 1.71 V to 1.89 V (Regulator Bypassed)

SID29

SID30

I_DD19

I_DD20

WDT with WCO on

–

µA

T = 25°C

T = –40°C to 105°C

Deep-Sleep mode, V_DD= 2.5 V to 3.6 V

SID31

I_DD21

Opamp on

–

µA

T = 25°C,

V_DD= 3.3 V

SID32

I_DD22

Opamp on

T = –40°C to 105°C

Deep-Sleep mode, V_DD= 3.6 V to 5.5 V

SID33

I_DD23

Opamp on

–

µA

T = 25°C,

V_DD= 5 V

T = –40°C to 105°C

SID34

I_DD24

Opamp on

Hibernate mode, V_DD= 1.8 V to 3.6 V

SID37

I_DD27

GPIO and reset active

–

150

–

nA

T = 25°C,

V_DD= 3.3 V

SID38

I_DD28

GPIO and reset active

T = –40°C to 105°C

Hibernate mode, V_DD= 3.6 V to 5.5 V

SID39

I_DD29

GPIO and reset active

–

nA

T = 25°C,

V_DD= 5 V

T = –40°C to 105°C

SID40

I_DD30

GPIO and reset active

Hibernate mode, V_DD= 1.71 V to 1.89 V (Regulator Bypassed)

SID41

SID42

I_DD31

I_DD32

GPIO and reset active

–

nA

T = 25°C

T = –40°C to 105°C

Stop mode, V_DD= 1.8 V to 3.6 V

SID43

I_DD33

Stop mode current (V_DD

)

–

20

40

–

nA

T = 25°C,

V_DD= 3.3 V

SID44

I_DD34

Stop mode current (V_DDR

)

–-

T = 25°C,

V_DDR= 3.3 V

T = –40°C to 105°C

T = –40°C to 105°C,

V_DDR= 1.9 V to

3.6 V

SID45

SID46

I_DD35

I_DD36

Stop mode current (V_DD

Stop mode current (V_DDR

)

–

nA

Stop mode, V_DD= 3.6 V to 5.5 V

SID47

I_DD37

Stop mode current (V_DD

)

–

nA

T = 25°C,

V_DD= 5 V

T = 25°C,

V_DDR= 5 V

T = –40°C to 105°C

SID48

I_DD38

Stop mode current (V_DDR

)

SID49

SID50

I_DD39

I_DD40

Stop mode current (V_DD

Stop mode current (V_DDR

)

–

nA

Datasheet

30

002-23052 Rev. *B

2023-03-29

PSoC™ 4 MCU with AIROC™ Bluetooth® LE

Based on Arm® Cortex®-M0

Electrical specifications

Table 8

Spec ID# Parameter

Stop mode, V_DD= 1.71 V to 1.89 V (Regulator Bypassed)

DC specifications ^(continued)

Details/

Description

Min

Typ Max

Unit

conditions

SID51

SID52

I_DD41

I_DD42

Stop mode current (V_DD

)

–

nA

T = 25°C

T = –40°C to 105°C

Table 9

AC specifications

Details/

Spec ID# Parameter

Description

Min Typ

Max

Unit

conditions

SID53

SID54

F_CPU

T_SLEEP

CPU frequency

Wakeup from Sleep mode

DC

–

0

24

–

MHz 1.71 V V_DD5.5 V

µs Guaranteed by

characterization

SID55

T_DEEPSLEEPWakeup from Deep-Sleep mode

T_HIBERNATEWakeup from Hibernate mode

–

25

µs 24-MHz IMO.

Guaranteed by

characterization

SID56

SID57

–

2

ms Guaranteed by

characterization

ms Guaranteed by

characterization

T_STOP

Wakeup from Stop mode

Datasheet

31

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PSoC™ 4 MCU with AIROC™ Bluetooth® LE

Based on Arm® Cortex®-M0

Electrical specifications

5.2.1

GPIO

Table 10

GPIO DC specifications

Details/

Spec ID# Parameter

Description

Min

Typ

Max

Unit

conditions

SID58

SID59

V_IH

V_IL

Input voltage HIGH threshold

Input voltage LOW threshold

0.7 × V_DD

–

V

CMOS input

0.3

× V_DD

SID60

SID61

SID62

SID63

SID64

V_IH

V_IL

V_IH

V_IL

LVTTL input, V_DD< 2.7 V

LVTTL input, V_DD≥ 2.7 V

Output voltage HIGH level

0.7 × V_DD

–

-

V

–

2.0

–

0.3× V_DD

-

0.8

–

V_OH

V_DD–0.6

I_OH= 4 mA at

3.3-V V_DD

SID65

SID66

SID67

SID68

V_OH

Output voltage HIGH level

Output voltage LOW level

Pull-up resistor

V_DD–0.5

–

V

I_OH= 1 mA at

1.8-V V_DD

I_OL= 8 mA at

3.3-V V_DD

I_OL= 4 mA at

1.8-V V_DD

I_OL= 3 mA at

3.3-V V_DD

V_OL

–

0.6

0.4

V_OL

SID69

SID70

SID71

R_PULLUP

3.5

–

5.6

–

8.5

2

kΩ

R_PULLDOWNPull-down resistor

I_IL

Input leakage current (absolute

value)

nA 25°C,

V_DD= 3.3 V

SID72

I_{IL_CTBM}

Input leakage on CTBm input

pins

Input capacitance

Input hysteresis LVTTL

Input hysteresis CMOS

Current through protection

diode to V_DD/V_SS

–

4

7

nA

SID73

SID74

SID75

SID76

C_IN

–

40

–

pF

V_HYSTTL

V_HYSCMOS

I_DIODE

25

0.05 × V_DD

–

mV V_DD> 2.7 V

mV

µA Except for

–

100

–

overvoltage-to

lerant pins

(P5.0 and P5.1)

SID77

I_{TOT_GPIO}

Maximum total source or sink

chip current

–

200

mA

Note

3. V_IHmust not exceed V_DDD+ 0.2 V.

Datasheet

32

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PSoC™ 4 MCU with AIROC™ Bluetooth® LE

Based on Arm® Cortex®-M0

Electrical specifications

Table 11

GPIO AC specifications

Details/

Spec ID# Parameter

Description

Min

Typ

Max

Unit

conditions

SID78

SID79

SID80

SID81

SID82

T_RISEF

Rise time in Fast-Strong mode

2

–

12

ns 3.3-V V_DDD

,

C_LOAD= 25 pF

T_FALLF

T_RISES

T_FALLS

F_GPIOUT1

Fall time in Fast-Strong mode

Rise time in Slow-Strong mode

Fall time in Slow-Strong mode

2

10

–

12

60

33

ns 3.3-V V_DDD

,

C_LOAD= 25 pF

ns 3.3-V V_DDD

,

C_LOAD= 25 pF

ns 3.3-V V_DDD

,

C_LOAD= 25 pF

GPIO Fout; 3.3 V  V_DD5.5 V.

Fast-Strong mode

MHz 90/10%, 25-pF

load, 60/40

duty cycle

SID83

SID84

SID85

SID86

F_GPIOUT2

F_GPIOUT3

F_GPIOUT4

F_GPIOIN

GPIO Fout; 1.7 VV_DD3.3 V.

–

16.7

7

MHz 90/10%, 25-pF

load, 60/40

Fast-Strong mode

duty cycle

GPIO Fout; 3.3 V V_DD5.5 V.

Slow-Strong mode

MHz 90/10%, 25-pF

load, 60/40

duty cycle

GPIO Fout; 1.7 V V_DD3.3 V.

Slow-Strong mode

3.5

48

MHz 90/10%, 25-pF

load, 60/40

duty cycle

GPIO input operating frequency;

1.71 V V_DD5.5 V

MHz 90/10% V_IO

Table 12

OVT GPIO DC specifications (P5_0 and P5_1 only)

Details/

Unit

Spec ID# Parameter

Description

Min

Typ

Max

conditions

SID71A

I_IL

Input leakage current (absolute

value), V_IH> V_DD

–

10

µA 25°C,

V_DD= 0 V, V_IH=

3.0 V

SID66A

V_OL

Output voltage LOW level

–

0.4

V

I_OL= 20 mA,

V_DD> 2.9 V

Table 13

OVT GPIO AC specifications (P5_0 and P5_1 only)

Details/

Spec ID# Parameter

Description

Min

Typ

Max

Unit

conditions

SID78A

SID79A

SID80A

T_{RISE_OVFS}Output rise time in Fast-Strong

mode

1.5

–

12

60

ns

25-pF load,

10%–90%,

V_DD=3.3 V

25-pF load,

10%–90%,

V_DD=3.3 V

25-pF load,

10%–90%,

V_DD=3.3 V

T_{FALL_OVFS}Output fall time in Fast-Strong

mode

1.5

10

ns

T_RISSS

Output rise time in Slow-Strong

mode

Datasheet

33

002-23052 Rev. *B

2023-03-29

PSoC™ 4 MCU with AIROC™ Bluetooth® LE

Based on Arm® Cortex®-M0

Electrical specifications

Table 13

OVT GPIO AC specifications (P5_0 and P5_1 only) ^(continued)

Details/

Spec ID# Parameter

Description

Min

Typ

Max

Unit

conditions

SID81A

SID82A

SID83A

T_FALLSS

Output fall time in Slow-Strong

mode

10

–

60

ns

25-pF load,

10%–90%,

V_DD=3.3 V

F_GPIOUT1

GPIO F_OUT; 3.3 V ≤ V_DD≤ 5.5 V

Fast-Strong mode

–

24

16

MHz 90/10%, 25-pF

load, 60/40

duty cycle

F_GPIOUT2

GPIO F_OUT; 1.71 V ≤ V_DD≤ 3.3 V

Fast-Strong mode

MHz 90/10%, 25-pF

load, 60/40

duty cycle

5.2.2

XRES

Table 14

XRES DC specifications

Description

Input voltage HIGH threshold 0.7 × V_DDD

Details/

Unit

Spec ID# Parameter

Min

Typ

Max

conditions

SID87

SID88

SID89

SID90

SID91

SID92

V_IH

V_IL

–

V

CMOS input

Input voltage LOW threshold

Pull-up resistor

Input capacitance

–

3.5

–

0.3 × V_DDD

Rpullup

C_IN

5.6

3

100

–

8.5

–

kΩ

pF

mV

µA

V_HYSXRES

I_DIODE

Input voltage hysteresis

Current through protection

diode to V_DDD/V_SS

–

100

Table 15

XRES AC specifications

Details/

Spec ID# Parameter

Description

Min

Typ

Max

Unit

conditions

SID93

T_RESETWIDTHReset pulse width

1

–

µs

Datasheet

34

002-23052 Rev. *B

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PSoC™ 4 MCU with AIROC™ Bluetooth® LE

Based on Arm® Cortex®-M0

Electrical specifications

5.3

Analog peripherals

5.3.1

Opamp

Table 16

Opamp specifications

Details/

Spec ID# Parameter

Description

Min

Typ

Max

Unit

conditions

I_DD(Opamp block current. V_DD= 1.8 V. No Load)

SID94

SID95

SID96

I_{DD_HI}

I_{DD_MED}

I_{DD_LOW}

Power = high

Power = medium

Power = low

–

1000

500

250

1300

–

350

µA

GBW (Load = 20 pF, 0.1 mA. V_DDA= 2.7 V)

SID97

SID98

SID99

GBW_HI

GBW_MED

GBW_LO

Power = high

Power = medium

Power = low

6

4

–

1

–

MHz

I_{OUT_MAX}(V_DDA 2.7 V, 500 mV from Rail)

SID100 I_{OUT_MAX_HI}Power = high

SID101 I_{OUT_MAX_MID}Power = medium

SID102 I_{OUT_MAX_LO}Power = low

10

–

5

–

mA

I_OUT(V_DDA= 1.71 V, 500 mV from Rail)

SID103 I_{OUT_MAX_HI}Power = high

SID104 I_{OUT_MAX_MID}Power = medium

SID105 I_{OUT_MAX_LO}Power = low

4

–

2

–

mA

V

SID106 V_IN

SID107 V_CM

Charge pump on, V_DDA 2.7 V

–0.05

V_DDA– 0.2

V

_OUT(V_DDA 2.7 V)

SID108 V_{OUT_1}

SID109 V_{OUT_2}

SID110 V_{OUT_3}

SID111 V_{OUT_4}

SID112 V_{OS_TR}

SID113 V_{OS_TR}

SID114 V_{OS_TR}

SID115 V_{OS_DR_TR}

SID116 V_{OS_DR_TR}

SID117 V_{OS_DR_TR}

SID118 CMRR

Power = high, I_LOAD=10 mA

Power = high, I_LOAD=1 mA

Power = medium, I_LOAD=1 mA

Power = low, I_LOAD=0.1 mA

Offset voltage, trimmed

Offset voltage drift, trimmed

DC

0.5

0.2

1

–

–10

–

V_DDA– 0.5

V_DDA– 0.2

V

–

V

±0.5

±1

±2

±3

±10

70

1

–

10

–

mV

µV/°C

High mode

Medium mode

Low mode

High mode

µV/°C Medium mode

µV/°C

dB

Low mode

65

–

V

_DDD= 3.6 V,

High-power

mode

SID119 PSRR

Noise

SID120 V_N1

At 1 kHz, 100-mV ripple

70

–

85

94

–

dB

V_DDD= 3.6 V

Input referred, 1 Hz–1 GHz,

power = high

µVrms

Datasheet

35

002-23052 Rev. *B

2023-03-29

PSoC™ 4 MCU with AIROC™ Bluetooth® LE

Based on Arm® Cortex®-M0

Electrical specifications

Table 16

Opamp specifications ^(continued)

Details/

Spec ID# Parameter

Description

Min

Typ

Max

Unit

conditions

SID121 V_N2

Input referred, 1 kHz, power =

high

–

72

–

nV/rtH

z

SID122 V_N3

Input referred, 10 kHz, power =

high

Input referred, 100 kHz, power =

high

Stable up to maximum load.

Performance specs at 50 pF

–

6

–

28

15

–

nV/rtH

z

nV/rtH

z

pF

V/µs

µs

SID123 V_N4

SID124 C_LOAD

SID125 Slew_rate

125

–

Cload = 50 pF, Power = High,

–

V

_DDA 2.7 V

SID126 T_op_wake From disable to enable, no

external RC dominating

300

–

Comp_mode (Comparator mode; 50-mV Drive, T_RISE= T_FALL(Approx.)

SID127 T_PD1

SID128 T_PD2

Response time; power = high

Response time; power =

medium

–

150

400

–

ns

SID129 T_PD3

SID130 Vhyst_op

Response time; power = low

Hysteresis

–

2000

10

–

ns

mV

Deep-Sleep mode (Deep-Sleep mode operation is only guaranteed for V_DDA> 2.5 V)

SID131 GBW_DS

SID132 IDD_DS

SID133 Vos_DS

SID134 Vos_dr_DS Offset voltage drift

SID135 Vout_DS

SID136 Vcm_DS

Gain bandwidth product

Current

Offset voltage

–

0.2

50

15

5

20

–

kHz

µA

mV

µV/°C

V

Output voltage

Common mode voltage

V

_DD–0.2

_DD–1.8

–

V

s

Table 17

Comparator DC specifications

Details/

Spec ID# Parameter

Description

Min

Typ

Max

Unit

conditions

SID140 V_OFFSET1

SID141 V_OFFSET2

SID141A V_OFFSET3

Input offset voltage, Factory trim

Input offset voltage, Custom trim

Input offset voltage,

ultra-low-power mode

–

±12

±10

±6

–

mV

mV V_DDD≥ 2.6 V for

Temp < 0°C

V_DDD≥ 1.8 V for

Temp ≥ 0°C

SID142 V_HYST

SID143 V_ICM1

Hysteresis when enabled

Input common mode voltage in

normal mode

–

0

10

–

35

V_DDD

0.1

mV

V

–

Modes 1 and 2

SID144 V_ICM2

Input common mode voltage in

low-power mode

0

–

V_DDD

V

Datasheet

36

002-23052 Rev. *B

2023-03-29

PSoC™ 4 MCU with AIROC™ Bluetooth® LE

Based on Arm® Cortex®-M0

Electrical specifications

Table 17

Comparator DC specifications ^(continued)

Details/

Spec ID# Parameter

Description

Min

Typ

Max

Unit

conditions

SID145 V_ICM3

Input common mode voltage in

ultra low-power mode

0

–

V_DDD

–

V

V_DDD≥ 2.6 V for

Temp < 0 °C

V_DDD≥ 1.8 V for

Temp ≥ 0 °C

1.15

SID146 CMRR

SID147 CMRR

SID148 I_CMP1

SID149 I_CMP2

SID150 I_CMP3

Common mode rejection ratio

Block current, normal mode

Block current, low-power mode

Block current in ultra-low-power

mode

50

42

–

6

–

400

100

–

dB

µA

V

_DDD≥ 2.7 V

_DDD≤ 2.7 V

V

V_DDD≥ 2.6 V for

Temp < 0 °C

V_DDD≥ 1.8 V for

Temp ≥ 0 °C

SID151 Z_CMP

DC input impedance of

comparator

35

–

MΩ

Table 18

Comparator AC specifications

Details/

Spec ID# Parameter

SID152 T_RESP1

Description

Min

Typ

Max

Unit

conditions

Response time, normal mode,

50-mV overdrive

Responsetime,low-powermode,

50-mV overdrive

Response time, ultra-low-power

mode, 50-mV overdrive

–

38

–

ns

µs

50-mV overdrive

SID153 T_RESP2

SID154 T_RESP3

70

–

2.3

200-mV

overdrive

V_DDD≥ 2.6 V for

Temp < 0°C

V_DDD≥ 1.8 V for

Temp ≥ 0°C

Datasheet

37

002-23052 Rev. *B

2023-03-29

PSoC™ 4 MCU with AIROC™ Bluetooth® LE

Based on Arm® Cortex®-M0

Electrical specifications

5.3.2

Temperature sensor

Table 19

Temperature sensor specifications

Details/

Spec ID# Parameter

Description

Min

Typ

Max

Unit

conditions

SID155 T_SENSACC

Temperature-sensor accuracy

–5

±1

5

°C

–40 to +85°C

5.3.3

SAR ADC

Table 20

SAR ADC DC specifications

Details/

Spec ID# Parameter

Description

Resolution

Min

Typ

Max

Unit

conditions

SID156

SID157

A_RES

–

12

8

bits

A_CHNIS_S Number of channels -

single-ended

8 full-speed

SID158

A-CHNKS_D Number of channels - differential

–

4

Diff inputs use

neighboring I/O

SID159

SID160

A-MONO

A_GAINERR Gain error

Monotonicity

–

±0.1

Yes

%

With external

reference

SID161

A_OFFSET Input offset voltage

–

2

mV Measured with

1-V V_REF

SID162

SID163

A_ISAR

A_VINS

Current consumption

Input voltage range -

single-ended

–

V_SS

–

1

V_DDA

mA

V

SID164

SID165

SID166

SID312

A_VIND

Input voltage range - differential

Input resistance

Input capacitance

Trimmed internal reference to

SAR

V_SS

–

V_DDA

2.2

10

V

kΩ

pF

A_INRES

A_INCAP

VREFSAR

–1

1

%

Percentage of

Vbg (1.024 V)

Table 21

SAR ADC AC specifications

Details/

Spec ID# Parameter

Description

Min

Typ

Max

Unit

conditions

SID167

A_PSRR

Power-supply rejection ratio

70

–

dB Measured at 1-V

reference

SID168

SID169

SID313

A_CMRR

A_SAMP

Fsarintref

Common-mode rejection ratio

Sample rate

SAR operating speed without

external ref. bypass

66

–

806

100

dB

ksps

ksps 12-bit resolution

SID170

SID171

A_SNR

A_BW

Signal-to-noise ratio (SNR)

Input bandwidth without aliasing

65

–

dB

F

_IN= 10 kHz

A_SAMP/ kHz

2

SID172

SID173

A_INL

Integral nonlinearity. V_DD= 1.71 V –1.7

to 5.5 V, 1 Msps

–

2

LSB

V

_REF= 1 V to V_DD

_REF= 1.71 V to

Integral nonlinearity. V_DDD

1.71 V to 3.6 V, 1 Msps

=

–1.5

1.7

LSB

V

V_DD

Datasheet

38

002-23052 Rev. *B

2023-03-29

PSoC™ 4 MCU with AIROC™ Bluetooth® LE

Based on Arm® Cortex®-M0

Electrical specifications

Table 21

SAR ADC AC specifications ^(continued)

Description

Details/

Spec ID# Parameter

Min

Typ

Max

Unit

conditions

SID174

SID175

SID176

SID177

SID178

A_INL

A_dnl

Integral nonlinearity. V_DD= 1.71 V –1.5

to 5.5 V, 500 Ksps

–

1.7

LSB V_REF= 1 V to V_DD

Differential nonlinearity. V_DD

1.71 V to 5.5 V, 1 Msps

=

–1

–

2.2

2

A_DNL

A_THD

Differential nonlinearity. V_DD

1.71 V to 3.6 V, 1 Msps

LSB V_REF= 1.71 V to

V_DD

LSB V_REF= 1 V to V_DD

Differential nonlinearity. V_DD

1.71 V to 5.5 V, 500 Ksps

2.2

–65

Total harmonic distortion

dB F_IN= 10 kHz

5.3.4

CSD

Table 22

CSD block specifications

Details/

Spec ID# Parameter

Description

Min

Typ

Max

Unit

conditions

V_CSD

SID179

SID180

SID181

SID182

SID183

Voltage range of operation

DNL for 8-bit resolution

INL for 8-bit resolution

DNL for 7-bit resolution

INL for 7-bit resolution

1.71

–1

–

5.5

V

IDAC1

IDAC2

–

1

3

1

3

LSB

–3

–1

–3

Capacitance

range of 9 pF to

35 pF, 0.1-pF

sensitivity. Radio

is not operating

during the scan

Ratio of counts of finger to

noise

SID184

SNR

5

–

Ratio

Output current of IDAC1 (8bits) in

High range

Output current of IDAC1 (8bits) in

Low range

Output current of IDAC2 (7bits) in

High range

Output current of IDAC2 (7bits) in

Low range

SID185

SID186

SID187

SID188

I_{DAC1_CRT1}

I_{DAC1_CRT2}

I_{DAC2_CRT1}

I_{DAC2_CRT2}

–

612

–

µA

306

305

153

Datasheet

39

002-23052 Rev. *B

2023-03-29

PSoC™ 4 MCU with AIROC™ Bluetooth® LE

Based on Arm® Cortex®-M0

Electrical specifications

5.4

Digital peripherals

5.4.1

Timer

Table 23

Timer DC specifications

Spec ID Parameter

Description

Min

–

Typ

–

Max Unit Details/conditions

SID189

SID189A

42

46

µA 16-bit timer, 85°C

µA 16-bit timer, 105°C

µA 16-bit timer, 85°C

µA 16-bit timer, 105°C

µA 16-bit timer, 85°C

µA 16-bit timer, 105°C

Block current consumption at

3 MHz

I_TIM1

SID190

SID190A

130

137

535

560

Block current consumption at

12 MHz

I_TIM2

SID191

SID191A

–

Block current consumption at

48 MHz

I_TIM3

Table 24

Timer AC specifications

Spec ID Parameter

SID192 T_TIMFREQ

Description

Operating frequency

Min

F_CLK

Typ Max Unit Details/conditions

–

48

MHz

2 ×

T_CLK

SID193 T_CAPWINT

Capture pulse width (internal)

–

ns

2 ×

SID194 T_CAPWEXT

SID195 T_TIMRES

Capture pulse width (external)

Timer resolution

–

ns

T_CLK

2 ×

T_CLK

2 ×

T_CLK

2 ×

T_CLK

SID196 T_TENWIDINTEnable pulse width (internal)

SID197 T_TENWIDEXTEnable pulse width (external)

SID198 T_TIMRESWINTReset pulse width (internal)

SID199 T_TIMRESEXTReset pulse width (external)

–

ns

2 ×

T_CLK

Datasheet

40

002-23052 Rev. *B

2023-03-29

PSoC™ 4 MCU with AIROC™ Bluetooth® LE

Based on Arm® Cortex®-M0

Electrical specifications

5.4.2

Counter

Table 25

Counter DC specifications

Spec ID Parameter

Description

Min

–

Typ Max Unit Details/conditions

SID200

SID200A

–

42

46

130

137

535

560

µA 16-bit timer, 85°C

µA 16-bit timer, 105°C

µA 16-bit timer, 85°C

µA 16-bit timer, 105°C

µA 16-bit timer, 85°C

µA 16-bit timer, 105°C

Block current consumption at

3 MHz

I_CTR1

SID201

SID201A

Block current consumption at

12 MHz

I_CTR2

SID202

SID202A

–

Block current consumption at

48 MHz

I_CTR3

Table 26

Counter AC specifications

Spec ID Parameter

Description

Min

Typ Max Unit Details/conditions

SID203

T_CTRFREQ

Operating frequency

F_CLK

–

48

MHz

2 ×

SID204

T_CTRPWINTCapture pulse width (internal)

T_CTRPWEXTCapture pulse width (external)

–

ns

T_CLK

2 ×

T_CLK

2 ×

T_CLK

2 ×

T_CLK

2 ×

T_CLK

2 ×

T_CLK

SID205

SID206

SID207

–

ns

T_CTRES

Counter Resolution

T_CENWIDINTEnable pulse width (internal)

T_CENWIDEXTEnable pulse width (external)

SID208

SID209

SID210

–

ns

T_CTRRE-

SWINT

Reset pulse width (internal)

T_CTRRE-

SWEXT

Reset pulse width (external)

Datasheet

41

002-23052 Rev. *B

2023-03-29

PSoC™ 4 MCU with AIROC™ Bluetooth® LE

Based on Arm® Cortex®-M0

Electrical specifications

5.4.3

Pulse width modulation (PWM)

Table 27

PWM DC specifications

Details/

Spec ID Parameter

Description

Min

Typ

Max Unit

conditions

SID211

I_PWM1

–

42

46

130

137

535

560

µA 16-bit timer, 85°C

µA 16-bit timer, 105°C

µA 16-bit timer, 85°C

µA 16-bit timer, 105°C

µA 16-bit timer, 85°C

µA 16-bit timer, 105°C

Block current consumption at

3 MHz

SID211A

SID212

SID212A

Block current consumption at

12 MHz

I_PWM2

SID213

SID213A

Block current consumption at

48 MHz

I_PWM3

Table 28

PWM AC specifications

Details/

Spec ID Parameter

Description

Min

Typ

Max Unit

conditions

SID214

SID215

SID216

SID217

SID218

SID219

SID220

SID221

SID222

T_PWMFREQ

T_PWMPWINTPulse width (internal)

T_PWMEXTPulse width (external)

T_PWMKILLINTKill pulse width (internal)

T_PWMKILLEXTKill pulse width (external)

T_PWMEINT

T_PWMENEXT

T_PWMRESWINTReset pulse width (internal)

T_PWMRE-

Operating frequency

F_CLK

–

48

–

MHz

ns

2 × T_CLK

Enable pulse width (internal)

Enable pulse width (external)

Reset pulse width (external)

SWEXT

Datasheet

42

002-23052 Rev. *B

2023-03-29

PSoC™ 4 MCU with AIROC™ Bluetooth® LE

Based on Arm® Cortex®-M0

Electrical specifications

5.4.4

Table 29

I²C

Fixed I²C DC specifications

Details/

Spec ID Parameter

Description

Min

Typ

Max Unit

conditions

SID223

SID224

SID225

SID226

I_I2C1

I_I2C2

I_I2C3

I_I2C4

Block current consumption at

100 kHz

Block current consumption at

400 kHz

Block current consumption at

1 Mbps

I²C enabled in Deep-Sleep mode

–

50

155

390

1.4

µA

–

Table 30

Spec ID

SID227

Fixed I²C AC specifications

Details/

Parameter

Description

Min

Typ

Max Unit

Mbps

conditions

F_I2C1

Bit rate

–

1

5.4.5

LCD direct drive

Table 31

LCD direct drive DC specifications

Details/

Spec ID Parameter

Description

Min Typ

Max Unit

conditions

SID228

I_LCDLOW

Operating current in low-power

mode

–

17.5

–

µA 16 × 4 small

segment display at

50 Hz

SID229

C_LCDCAP

LCD capacitance per

segment/common driver

–

500

5000

pF

SID230

SID231

LCD_OFFSETLong-term segment offset

–

20

2

–

mV

I_LCDOP1

LCD system operating current

V_BIAS= 5 V

mA 32 × 4 segments.

50 Hz at 25°C

SID232

I_LCDOP2

LCD system operating current

V_BIAS= 3.3 V

–

2

–

mA 32 × 4 segments

50 Hz at 25°C

Table 32

LCD direct drive AC specifications

Description

LCD frame rate

Fixed UART DC specifications

Details/

Spec ID Parameter

Min

Typ

Max Unit

conditions

SID233

F_LCD

10

50

150

Hz

Table 33

Details/

Spec ID Parameter

Description

Min

Typ

Max

Unit

conditions

SID234

SID235

I_UART1

I_UART2

Block current consumption at

100 kbps

Block current consumption at

1000 kbps

–

55

µA

–

312

µA

Datasheet

43

002-23052 Rev. *B

2023-03-29

PSoC™ 4 MCU with AIROC™ Bluetooth® LE

Based on Arm® Cortex®-M0

Electrical specifications

Table 34

Fixed UART AC specifications

Description

Details/

Spec ID Parameter

Min

Typ

Max

Unit

conditions

SID236

F_UART

Bit rate

–

1

Mbps

5.4.6

SPI specifications

Table 35

Fixed SPI DC specifications

Details/

Spec ID

Parameter

I_SPI1

Description

Min Typ Max

Unit

conditions

SID237

Block current consumption at

1 Mbps

Block current consumption at

4 Mbps

Block current consumption at

8 Mbps

–

360

560

600

µA

SID238

SID239

I_SPI2

I_SPI3

µA

Table 36

Spec ID

SID240

Fixed SPI AC specifications

Details/

Parameter

Description

Min Typ Max

Unit

conditions

F_SPI

SPI operating frequency (master;

6x oversampling)

–

8

MHz

Table 37

Fixed SPI Master mode AC specifications

Details/

Spec ID Parameter

Description

Min Typ Max Unit

conditions

SID241

SID242

T_DMO

T_DSI

MOSI valid after Sclock driving

edge

MISO valid before Sclock

capturing edge. Full clock, late

MISO sampling used

–

18

–

ns

20

Full clock, late MISO

sampling

SID243

T_HMO

Previous MOSI data hold time

0

–

ns

Referred to Slave

capturing edge

Table 38

Fixed SPI Slave mode AC specifications

Details/

Spec ID Parameter

Description

Min Typ

Max

Unit

conditions

SID244

SID245

SID246

T_DMI

MOSI valid before Sclock

capturing edge

MISO valid after Sclock driving

edge

MISO valid after Sclock driving

edge in external clock mode

40

–

ns

T_DSO

42 + 3 ×

T_SCB

ns

T_{DSO_ext}

–

50

V_DD< 3.0 V

SID247

SID248

T_HSO

T_SSELSCK

Previous MISO data hold time

SSEL valid to first SCK valid edge 100

0

–

ns

Datasheet

44

002-23052 Rev. *B

2023-03-29

PSoC™ 4 MCU with AIROC™ Bluetooth® LE

Based on Arm® Cortex®-M0

Electrical specifications

5.5

Memory

Table 39

Flash DC specifications

Details/

Spec ID

Parameter

V_PE

T_WS32

Description

Min

Typ

Max

Unit

conditions

SID249

SID310

Erase and program voltage 1.71

–

5.5

–

V

1

CPU execution from

flash

Number of Wait states at

16–24 MHz

SID311

T_WS16

0

–

CPU execution from

flash

Number of Wait states for

0–16 MHz

Table 40

Spec ID

Flash AC specifications

Details/

Parameter

Description

Min

Typ

Max

Unit

conditions

[4]

SID250 T_ROWWRITE

Row (block) write time

(erase and program)

Row erase time

–

20

ms

Row (block) =

128 bytes

Row (block) = 128

bytes for 128-KB

flash devices

[4]

SID251 T_ROWERASE

–

13

ms

Row (block) = 256

bytes for 256-KB

flash devices

[4]

SID252 T_ROWPROGRAM

Row program time after

erase

–

7

ms

[4]

SID253 T_BULKERASE

SID254 T_DEVPROG

SID255 F_END

SID256 F_RET

Bulk erase time (128 KB)

Total device program time

Flash endurance

Flash retention. T_A 55°C,

100 K P/E cycles

–

35

25

–

ms

s

cycles

years

[4]

100 K

20

–

SID257 F_RET2

SID257A F_RET3

Note

Flash retention. T_A 85°C,

10

3

–

years

10 K P/E cycles

Flash retention. T_A 105°C,

10 K P/E cycles

years For T_A≥ 85°C

4. It can take as much as 20 milliseconds to write to flash. During this time, the device should not be reset, or

flash operations will be interrupted and cannot be relied on to have completed. Reset sources include the

XRES pin, software resets, CPU lockup states and privilege violations, improper power supply levels, and

watchdogs. Make certain that these are not inadvertently activated.

Datasheet

45

002-23052 Rev. *B

2023-03-29

PSoC™ 4 MCU with AIROC™ Bluetooth® LE

Based on Arm® Cortex®-M0

Electrical specifications

5.6

System resources

5.6.1

Power-on reset (POR)

Table 41

Spec ID

SID258

SID259

SID260

POR DC specifications

Parameter

V_RISEIPOR

Description

Min

0.80

0.75

15

Typ

–

Max

1.45

1.40

200

Unit

V

Details/conditions

Rising trip voltage

Falling trip voltage

Hysteresis

V_FALLIPOR

V_IPORHYST

–

mV

Table 42

Spec ID

SID264

POR AC specifications

Parameter

Description

Min

–

Typ

–

Max

1

Unit Details/conditions

µs

T_{PPOR_TR}

PPOR response time in

Active and Sleep modes

Table 43

Spec ID#

Brown-out detect

Parameter

Description

Min

Typ Max

Unit Details/conditions

SID261 V_FALLPPOR

BOD trip voltage in Active

and Sleep modes

1.64

–

V

SID262 V_FALLDPSLP

BOD trip voltage in

Deep-Sleep mode

1.4

–

V

Table 44

Hibernate reset

Spec ID# Parameter

SID263 V_HBRTRIP

Description

BOD trip voltage in

Hibernate mode

Min

1.1

Typ Max

Unit Details/conditions

V

–

5.6.2

Table 45

Spec ID

SID265

SID266

SID267

SID268

SID269

SID270

SID271

SID272

SID273

SID274

SID275

SID276

SID277

SID278

Voltage monitors

Voltage monitor DC specifications

Parameter

V_LVI1

Description

Min

1.71

1.76

1.85

1.95

2.05

2.15

2.24

2.34

2.44

2.54

2.63

2.73

2.83

2.93

Typ

1.75

1.80

1.90

2.00

2.10

2.20

2.30

2.40

2.50

2.60

2.70

2.80

2.90

3.00

Max

1.79

1.85

1.95

2.05

2.15

2.26

2.36

2.46

2.56

2.67

2.77

2.87

2.97

3.08

Unit Details/conditions

LVI_A/D_SEL[3:0] = 0000b

LVI_A/D_SEL[3:0] = 0001b

LVI_A/D_SEL[3:0] = 0010b

LVI_A/D_SEL[3:0] = 0011b

LVI_A/D_SEL[3:0] = 0100b

LVI_A/D_SEL[3:0] = 0101b

LVI_A/D_SEL[3:0] = 0110b

LVI_A/D_SEL[3:0] = 0111b

LVI_A/D_SEL[3:0] = 1000b

LVI_A/D_SEL[3:0] = 1001b

LVI_A/D_SEL[3:0] = 1010b

LVI_A/D_SEL[3:0] = 1011b

LVI_A/D_SEL[3:0] = 1100b

LVI_A/D_SEL[3:0] = 1101b

V

V_LVI2

V_LVI3

V_LVI4

V_LVI5

V_LVI6

V_LVI7

V_LVI8

V_LVI9

V_LVI10

V_LVI11

V_LVI12

V_LVI13

V_LVI14

Datasheet

46

002-23052 Rev. *B

2023-03-29

PSoC™ 4 MCU with AIROC™ Bluetooth® LE

Based on Arm® Cortex®-M0

Electrical specifications

Table 45

Spec ID

SID279

SID280

SID281

Voltage monitor DC specifications ^(continued)

Parameter

V_LVI15

Description

LVI_A/D_SEL[3:0] = 1110b

LVI_A/D_SEL[3:0] = 1111b

Block current

Min

3.12

4.39

–

Typ

3.20

4.50

–

Max

3.28

4.61

100

Unit Details/conditions

V

V_LVI16

LVI_IDD

µA

Table 46

Spec ID

Voltage monitor AC specifications

Parameter

Description

Min

Typ

Max

Unit Details/conditions

SID282 T_MONTRIP

Voltage monitor trip time

–

1

µs

5.6.3

SWD interface

Table 47

SWD interface specifications

Spec ID

Parameter

Description

Min

Typ Max

Unit Details/conditions

SID283 F_SWDCLK1

3.3 V  V_DD 5.5 V

–

14

MHz SWDCLK ≤ 1/3 CPU

clock frequency

SID284 F_SWDCLK2

1.71 V  V_DD 3.3 V

–

7

MHz SWDCLK ≤ 1/3 CPU

clock frequency

SID285 T_SWDI_SETUP T = 1/f SWDCLK

SID286 T_SWDI_HOLD T = 1/f SWDCLK

SID287 T_SWDO_VALID T = 1/f SWDCLK

SID288 T_SWDO_HOLD T = 1/f SWDCLK

0.25 × T

–

ns

–

0.5 × T

–

1

5.6.4

Internal main oscillator

Table 48

Spec ID

SID289

SID290

SID291

SID292

SID293

IMO DC specifications

Parameter

I_IMO1

Description

Min

Typ

Max

1000

325

Unit Details/conditions

IMO operating current at 48 MHz

IMO operating current at 24 MHz

IMO operating current at 12 MHz

IMO operating current at 6 MHz

IMO operating current at 3 MHz

–

µA

I_IMO2

I_IMO3

I_IMO4

I_IMO5

225

180

150

Table 49

IMO AC specifications

Spec ID Parameter

Description

Min

Typ

Max

Unit Details/conditions

SID296 F_IMOTOL3

Frequency variation from 3 to

48 MHz

–

±2

%

With API-called

calibration

SID297 F_IMOTOL3

IMO startup time

–

12

µs

Datasheet

47

002-23052 Rev. *B

2023-03-29

PSoC™ 4 MCU with AIROC™ Bluetooth® LE

Based on Arm® Cortex®-M0

Electrical specifications

5.6.5

Internal low-speed oscillator

Table 50

Spec ID

SID298

ILO DC specifications

Parameter

I_ILO2

Description

ILO operating current at

32 kHz

Min

–

Typ

0.3

Max

1.05

Unit

µA

Details/conditions

Guaranteed by

design

Table 51

Spec ID

SID299

SID300

ILO AC specifications

Parameter

T_STARTILO1

F_ILOTRIM1

Description

ILO startup time

32-kHz trimmed

frequency

Min

–

15

Typ

–

32

Max

2

50

Unit

ms

kHz

Details/conditions

Table 52

Spec ID

External clock specifications

Parameter

Description

Min

Typ

Max

Unit

Details/conditions

SID301 ExtClkFreq

External clock input

frequency

0

–

48

MHz CMOS input level

only

SID302 ExtClkDuty

Duty cycle; Measured at

V_DD/2

45

–

55

%

CMOS input level

only

Table 53

Spec ID

UDB AC specifications

Parameter Description

Min

Typ

Max

Unit

Details/conditions

Data path performance

SID303 F_MAX-TIMER

Max frequency of 16-bit

timer in a UDB pair

Max frequency of 16-bit

adder in a UDB pair

Max frequency of 16-bit

CRC/PRS in a UDB pair

–

48

MHz

SID304 F_MAX-ADDER

SID305 F_{MAX_CRC}

PLD performance in UDB

SID306 F_{MAX_PLD}

Max frequency of 2-pass

PLD function in a UDB pair

–

48

MHz

Clock to output performance

SID307 T_{CLK_OUT_UDB1}Prop. delay for clock in to

data out at 25 °C, Typical

SID308 T_{CLK_OUT_UDB2}Prop. delay for clock in to

data out, Worst case

–

15

25

–

ns

Datasheet

48

002-23052 Rev. *B

2023-03-29

PSoC™ 4 MCU with AIROC™ Bluetooth® LE

Based on Arm® Cortex®-M0

Electrical specifications

Table 54

Spec ID#

Bluetooth® LE subsystem

Parameter Description

Min Typ Max

Unit

Details/conditions

RF receiver specification

SID340

RXS, IDLE

RX sensitivity with idle

transmitter

RX sensitivity with idle

transmitter excluding

Balun loss

–

–89

–91

–

dBm

SID340A

dBm Guaranteedbydesign

simulation

SID341

SID342

SID343

SID344

RXS, DIRTY

RX sensitivity with dirty

transmitter

–

–87 –70

dBm RF-PHY Specification

(RCV-LE/CA/01/C)

dBm

RXS, HIGHGAIN RX sensitivity in high-gain

mode with idle transmitter

PRXMAX

–91

–1

9

–

Maximum input power

–10

–

dBm RF-PHY Specification

(RCV-LE/CA/06/C)

CI1

Cochannel interference,

Wanted signal at –67 dBm and

Interferer at FRX

21

dB

RF-PHY Specification

(RCV-LE/CA/03/C)

SID345

SID346

SID347

SID348

CI2

CI3

CI4

CI5

Adjacent channel

–

3

15

–

dB

RF-PHY Specification

(RCV-LE/CA/03/C)

interference

Wanted signal at –67 dBm and

Interferer at FRX ±1 MHz

Adjacent channel

interference

Wanted signal at –67 dBm and

Interferer at FRX ±2 MHz

Adjacent channel

interference

Wanted signal at –67 dBm and

Interferer at ≥FRX ±3 MHz

–29

–39

–20

dB

RF-PHY Specification

(RCV-LE/CA/03/C)

–

RF-PHY Specification

(RCV-LE/CA/03/C)

Adjacent channel

interference

–

RF-PHY Specification

(RCV-LE/CA/03/C)

Wanted Signal at –67dBm and

Interferer at Image frequency

(F_IMAGE

)

SID349

CI3

Adjacent channel

interference

–

–30

–

dB

RF-PHY Specification

(RCV-LE/CA/03/C)

Wanted signal at –67 dBm and

Interferer at Image frequency

(F_IMAGE± 1 MHz)

SID350

SID351

OBB1

OBB2

Out-of-band blocking,

–30 –27

–35 –27

–

dBm RF-PHY Specification

(RCV-LE/CA/04/C)

Wanted signal at –67 dBm and

Interferer at F = 30–2000 MHz

Out-of-band blocking,

Wanted signal at –67 dBm and

Interferer at F = 2003–

2399 MHz

dBm RF-PHY Specification

(RCV-LE/CA/04/C)

SID352

OBB3

Out-of-band blocking,

Wanted signal at –67 dBm and

Interferer at F = 2484–

2997 MHz

–35 –27

–

dBm RF-PHY Specification

(RCV-LE/CA/04/C)

Datasheet

49

002-23052 Rev. *B

2023-03-29

PSoC™ 4 MCU with AIROC™ Bluetooth® LE

Based on Arm® Cortex®-M0

Electrical specifications

Table 54

Spec ID#

SID353

Bluetooth® LE subsystem ^(continued)

Parameter

OBB4

Description

Min Typ Max

Unit

Details/conditions

Out-of-band blocking,

Wanted signal a –67 dBm and

Interferer at F = 3000–

12750 MHz

–30 –27

–

dBm RF-PHY Specification

(RCV-LE/CA/04/C)

SID354

IMD

Intermodulation

performance

–50

–

dBm RF-PHY Specification

(RCV-LE/CA/05/C)

Wanted signal at –64 dBm and

1-Mbps Bluetooth® LE, third,

fourth, and fifth offset

channel

SID355

SID356

RXSE1

RXSE2

Receiver spurious emission

30 MHz to 1.0 GHz

–

–57

–47

dBm 100-kHz

measurement

bandwidth

ETSI EN300 328 V1.8.1

Receiver spurious emission

1.0 GHz to 12.75 GHz

dBm 1-MHz measurement

bandwidth

ETSI EN300 328 V1.8.1

RF transmitter specifications

SID357

SID358

SID359

TXP, ACC

TXP, RANGE

TXP, 0dBm

RF power accuracy

RF power control range

Output power, 0-dB Gain

setting (PA7)

–

±1

20

0

–

dB

dBm

SID360

SID361

SID362

SID363

SID364

SID365

SID366

SID367

SID368

SID369

SID370

SID371

TXP, MAX

TXP, MIN

F2AVG

Output power, maximum

power setting (PA10)

Output power, minimum

power setting (PA1)

Average frequency deviation 185

for 10101010 pattern

Average frequency deviation 225 250 275

for 11110000 pattern

–

3

–18

–

dBm

kHz RF-PHY Specification

(TRM-LE/CA/05/C)

kHz RF-PHY Specification

(TRM-LE/CA/05/C)

F1AVG

EO

Eye opening =

∆F2AVG/∆F1AVG

0.8

–150

–50

–20

–

RF-PHY Specification

(TRM-LE/CA/05/C)

FTX, ACC

FTX, MAXDR

FTX, INITDR

FTX, DR

IBSE1

Frequency accuracy

Maximum frequency drift

Initial frequency drift

Maximum drift rate

150

50

kHz RF-PHY Specification

(TRM-LE/CA/06/C)

kHz RF-PHY Specification

(TRM-LE/CA/06/C)

kHz RF-PHY Specification

(TRM-LE/CA/06/C)

kHz/ RF-PHY Specification

50 µs (TRM-LE/CA/06/C)

dBm RF-PHY Specification

(TRM-LE/CA/03/C)

dBm RF-PHY Specification

(TRM-LE/CA/03/C)

20

In-band spurious emission at

2-MHz offset

In-band spurious emission at

≥3-MHz offset

–20

-30

IBSE2

–

TXSE1

Transmitter spurious

emissions (average), <1.0 GHz

–

-55.5 dBm FCC-15.247

Datasheet

50

002-23052 Rev. *B

2023-03-29

PSoC™ 4 MCU with AIROC™ Bluetooth® LE

Based on Arm® Cortex®-M0

Electrical specifications

Table 54

Spec ID#

SID372

Bluetooth® LE subsystem ^(continued)

Parameter

TXSE2

Description

Transmitter spurious

emissions (average), >1.0 GHz

Min Typ Max

Unit

Details/conditions

–

-41.5 dBm FCC-15.247

RF current specifications

SID373 IRX

Receive current in normal

mode

Radio receive current in

normal mode

–

18.7

16.4

21.5

20

–

mA

SID373A IRX_RF

mA Measured at V_DDR

SID374

SID375

SID376

IRX, HIGHGAIN Receive current in high-gain

mode

ITX, 3dBm

mA

TX current at 3-dBm setting

(PA10)

TX current at 0-dBm setting

(PA7)

mA

ITX, 0dBm

16.5

15.6

14.2

15.5

14.5

13.2

12.5

mA

SID376A ITX_RF, 0dBm Radio TX current at 0 dBm

setting (PA7)

SID376B ITX_RF, 0dBm Radio TX current at 0 dBm

excluding Balun loss

mA Measured at V_DDR

mA Guaranteedbydesign

simulation

mA

SID377

SID378

SID379

SID380

ITX,-3dBm

ITX,-6dBm

ITX,-12dBm

ITX,-18dBm

TX current at –3-dBm setting

(PA4)

TX current at –6-dBm setting

(PA3)

TX current at –12-dBm setting

(PA2)

TX current at –18-dBm setting

(PA1)

mA

Average current at 1-second

Bluetooth® LE connection

interval

Average current at 4-second

Bluetooth® LE connection

interval

TXP: 0 dBm; ±20-ppm

Iavg_1sec,

0dBm

SID380A

SID380B

–

17.1

6.1

–

µA

master and slave

clock accuracy.

TXP: 0 dBm; ±20-ppm

master and slave

clock accuracy.

Iavg_4sec,

0dBm

General RF specifications

SID381

SID382

SID383

SID384

FREQ

CHBW

DR

RF operating frequency

Channel spacing

On-air data rate

Bluetooth® LE.IDLE to

Bluetooth® LE. TX

transition time

2400

–

2

1000

2482

–

MHz

kbps

µs

–

IDLE2TX

120 140

SID385

IDLE2RX

Bluetooth® LE.IDLE to

Bluetooth® LE. RX transition

time

–

75

120

µs

RSSI specifications

SID386

SID387

SID388

RSSI, ACC

RSSI, RES

RSSI, PER

RSSI accuracy

RSSI resolution

RSSI sample period

–

±5

1

6

–

dB

µs

Datasheet

51

002-23052 Rev. *B

2023-03-29

PSoC™ 4 MCU with AIROC™ Bluetooth® LE

Based on Arm® Cortex®-M0

Electrical specifications

Table 55

ECO specifications

Spec ID# Parameter

SID389 F_ECO

SID390 F_TOL

SID391 ESR

SID392 PD

SID393 T_START1

SID394 T_START2

SID395 C_L

Description

Crystal frequency

Frequency tolerance

Equivalent series resistance

Drive level

Startup time (Fast Charge on)

Startup time (Fast Charge off)

Load capacitance

Min Typ

Max

–

Unit Details/conditions

–

–50

–

24

–

MHz

ppm

Ω

µW

µs

50

60

100

850

3

–

ms

pF

–

8

–

SID396 C0

SID397 I_ECO

Shunt capacitance

Operating current

–

1.1

1400

–

pF

µA Includes LDO+BG

current

Table 56

WCO specifications

Spec ID# Parameter

SID398 F_WCO

SID399 FTOL

SID400 ESR

SID401 PD

SID402 T_START

SID403 C_L

SID404 C0

Description

Crystal frequency

Frequency tolerance

Equivalent series resistance

Drive level

Startup time

Crystal load capacitance

Crystal shunt capacitance

Min

–

6

–

Typ

32.768

50

–

1.35

–

Max

–

1

500

12.5

–

Unit Details/conditions

kHz

ppm

kΩ

µW

ms

pF

µA

SID405 I_WCO1

Operating current

(High-Power mode)

8

SID406 I_WCO2

SID406A

Operating current

(low-power mode)

–

1

2.6

µA

85°C

105°C

Datasheet

52

002-23052 Rev. *B

2023-03-29

PSoC™ 4 MCU with AIROC™ Bluetooth® LE

Based on Arm® Cortex®-M0

Ordering information

6

Ordering information

The PSoC™ 4 CY8C41xx-BL MCU with AIROC™ Bluetooth® LE part numbers and features are listed in the following

table.

Table 57

PSoC™ 4 CY8C41xx-BL MCU with AIROC™ Bluetooth® LE part numbers

Product

family

MPN

CY8C4127LQI-BL473

CY8C4127LQI-BL453

CY8C4127LQI-BL483

CY8C4127FNI-BL483

CY8C4127LQI-BL493

CY8C4127FNI-BL493

CY8C4128LQI-BL473

CY8C4128LQI-BL483

CY8C4128LQI-BL543

CY8C4128LQI-BL573

CY8C4128FNI-BL573

CY8C4128LQI-BL553

CY8C4128LQI-BL563

CY8C4128LQI-BL583

CY8C4128LQI-BL593

24 4.1 128 16

24 4.1 256 32

24 4.2 256 32

–

2

–

1

–

1

–

1

–

1

–

1

–

1

–

1

–

1

–

1

806 ksps

–

1

2

–

2

4

2

36

QFN

85°C

36 68-CSP 85°C

36 QFN 85°C

36 68-CSP 85°C

36

QFN

85°C

36 76-CSP 85°C

36

QFN

85°C

Datasheet

53

002-23052 Rev. *B

2023-03-29

PSoC™ 4 MCU with AIROC™ Bluetooth® LE

Based on Arm® Cortex®-M0

Ordering information

6.1

Ordering code definitions

PSoC™ 4 devices follow the part numbering convention described in the following table. All fields are

single-character alphanumeric (0, 1, 2, …, 9, A,B, …, Z) unless stated otherwise.

The part numbers are of the form CY8C4ABCDEF-XYZ where the fields are defined as follows.

CY8C

4

A

B

C

D

E

F

- X Y Z

Example

Cypress prefix

Architecture

CY8C

4: PSoC™ 4

1: 4100 Family

2: 24 MHz

Family within architecture

Speed grade

Flash capacity

8: 256 KB

LQ: QFN

FN: WLCSP

Package code

I: Industrial

Temperature range

Attributes code

Q: Extended Industrial

BL483: Attributes

The field values are listed in the following table.

Field Description

CY8C Cypress prefix

Values

Meaning

4

Architecture

4

1

PSoC™ 4

PSoC™ 4 CY8C41xx-BL MCU with AIROC™

Bluetooth® LE family

A

Family within architecture

B

C

CPU speed

Flash capacity

2

7, 8

FN

LQ

I

Q

24 MHz

128KB, 256KB respectively

WLCSP

QFN

Industrial 85°C

Extended Industrial 105°C

Bluetooth® 4.1 compliant

Bluetooth® 4.2 compliant

DE

F

Package code

Temperature range

Attributes code

BL400-BL499

BL500-BL599

XYZ

Datasheet

54

002-23052 Rev. *B

2023-03-29

PSoC™ 4 MCU with AIROC™ Bluetooth® LE

Based on Arm® Cortex®-M0

Packaging

7

Packaging

Table 58

Parameter

T_A

T_J

T_JA

Package characteristics

Description

Operating ambient temperature

Operating junction temperature

Package _JA(56-pin QFN)

Conditions

Min

–40

–

Typ

25.00

–

16.9

9.7

Max

105

125

–

Unit

°C

–

°C/watt

T_JC

Package _JC(56-pin QFN)

–

T_JA

T_JC

T_JA

T_JC

T_JA

T_JC

T_JA

T_JC

Package _JA(76-ball WLCSP)

Package _JC(76-ball WLCSP)

Package _JA(76-ball thin WLCSP)

Package _JC(76-ball thin WLCSP)

Package _JA(68-ball WLCSP)

Package _JC(68-ball WLCSP)

Package _JA(68-ball thin WLCSP)

Package _JC(68-ball thin WLCSP)

–

20.1

0.19

20.9

0.17

16.6

0.19

16.6

0.19

–

Table 59

Table 60

Solder reflow peak temperature

Package

Maximum peak

temperature

Maximum time at peak

temperature

All packages

260°C

30 seconds

Package moisture sensitivity level (MSL), IPC/JEDEC J-STD-2

Package

56-pin QFN

All WLCSP packages

MSL

MSL 3

MSL 1

Table 61

Package details

Spec ID

Package

Description

001-58740 Rev. *C

001-96603 Rev. *B

002-10658 Rev. **

001-92343 Rev. *A

001-99408 Rev. **

56-pin QFN

7.0 mm × 7.0 mm × 0.6 mm

4.04 mm × 3.87 mm × 0.55 mm

4.04 mm × 3.87 mm × 0.4 mm

3.52 mm × 3.91 mm × 0.55 mm

52 mm × 3.91 mm × 0.4 mm

76-ball WLCSP

76-ball thin WLCSP

68-ball WLCSP

68-ball thin WLCSP

Datasheet

55

002-23052 Rev. *B

2023-03-29

PSoC™ 4 MCU with AIROC™ Bluetooth® LE

Based on Arm® Cortex®-M0

Packaging

TOP VIEW

SIDE VIEW

BOTTOM VIEW

NOTES:

1. HATCH AREA IS SOLDERABLE EXPOSED PAD

2. BASED ON REF JEDEC # MO-248

001-58740 *C

3. ALL DIMENSIONS ARE IN MILLIMETERS

Figure 5

56-pin QFN 7 mm × 7 mm × 0.6 mm

The center pad on the QFN package must be connected to ground (V_SS) for the proper operation of the device.

Datasheet

56

002-23052 Rev. *B

2023-03-29

PSoC™ 4 MCU with AIROC™ Bluetooth® LE

Based on Arm® Cortex®-M0

Packaging

7.1

WLCSP compatibility

The PSoC™ 4XXX-BLE family has products with 128 KB (16KB SRAM) and 256 KB (32KB SRAM) Flash. Package

pin-outs and sizes are identical for the 56-pin QFN package but are different in one dimension for the 68-ball

WLCSP.

The 256KB Flash product has an extra column of balls which are required for mechanical integrity purposes in

the Chip-Scale package. With consideration for this difference, the land pattern on the PCB may be designed such

that either product may be used with no change to the PCB design.

Figure 6 shows the 128KB and 256 KB Flash CSP packages.

128K Bluetooth® LE

256K Bluetooth® LE

128K BLE

256K BLE

CONNECTED PADS

NC PADS

PACKAGE CENTER

PACK BOUNDARY

FIDUCIAL FOR128K

FIDUCIAL FOR256K

Figure 6

128-KB and 256-KB Flash CSP packages

The rightmost column of (all NC, No Connect) balls in the 256K Bluetooth® LE WLCSP is for mechanical integrity

purposes. The package is thus wider (3.2 mm versus 2.8 mm). All other dimensions are identical. Infineon will

provide layout symbols for printed circuit board (PCB) layout.

The scheme in Figure 6 is implemented to design the PCB for the 256K Bluetooth® LE package with the

appropriate space requirements thus allowing use of either package at a later time without redesigning the PCB.

Datasheet

57

002-23052 Rev. *B

2023-03-29

PSoC™ 4 MCU with AIROC™ Bluetooth® LE

Based on Arm® Cortex®-M0

Packaging

001-92343 *A

Figure 7

68-ball WLCSP package outline

SIDE VIEW

BOTTOM VIEW

TOP VIEW

1

2

3

4

5

6

7

8

7

6

5

4

3

2

1

A

B

C

D

E

F

A

B

C

D

E

F

G

H

G

H

J

NOTES:

1. REFERENCE JEDEC PUBLICATION 95, DESIGN GUIDE 4.18

2. ALL DIMENSIONS ARE IN MILLIMETERS

001-99408 **

Figure 8

68-ball thin WLCSP

Datasheet

58

002-23052 Rev. *B

2023-03-29

PSoC™ 4 MCU with AIROC™ Bluetooth® LE

Based on Arm® Cortex®-M0

Packaging

PIN #1 MARK

B

1

2

3

4

5

6

7

8

9

8

7

6

5

4

3

2

1

7

A

B

C

D

E

F

A

B

C

D

E

F

6

SD

D1

D

G

H

J

G

H

J

eD

SE

A

E

eE

6

E1

TOP VIEW

BOTTOM VIEW

0.10 C

5

DETAIL A

A1

0.05 C

C

76XØb

Ø0.06 M C A B

Ø0.03 M C

A

DETAIL A

SIDE VIEW

NOTES:

1. ALL DIMENSIONS ARE IN MILLIMETERS.

DIMENSIONS

NOM.

SYMBOL

2. SOLDER BALL POSITION DESIGNATION PER JEP95, SECTION 3, SPP-020.

3. "e" REPRESENTS THE SOLDER BALL GRID PITCH.

MIN.

MAX.

0.55

0.24

A

-

0.21

4. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D" DIRECTION.

SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION.

N IS THE NUMBER OF POPULATED SOLDER BALL POSITIONS FOR MATRIX

SIZE MD X ME.

A1

D

0.18

3.87 BSC

E

4.04 BSC

3.20 BSC

9

D1

E1

MD

ME

N

5.

DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A

PLANE PARALLEL TO DATUM C.

6.

"SD" AND "SE" ARE MEASURED WITH RESPECT TO DATUMS A AND B AND

DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW.

9

76

WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW,

"SD" OR "SE" = 0.

0.26

b

0.23

0.29

eD

eE

SD

SE

0.40 BSC

0.381 BSC

0.321 BSC

WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW,

"SD" = eD/2 AND "SE" = eE/2.

A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK

METALIZED MARK, INDENTATION OR OTHER MEANS.

7.

8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED SOLDER

BALLS.

9. JEDEC SPECIFICATION NO. REF : N/A

001-96603 *B

Figure 9

76-ball WLCSP package outline

Datasheet

59

002-23052 Rev. *B

2023-03-29

PSoC™ 4 MCU with AIROC™ Bluetooth® LE

Based on Arm® Cortex®-M0

Packaging

PIN #1 MARK

B

1

2

3

4

5

6

7

8

9

8

7

6

5

4

3

2

1

7

A

B

C

D

E

F

A

B

C

D

E

F

6

SD

D1

D

G

H

J

G

H

J

eD

SE

A

E

eE

6

E1

TOP VIEW

BOTTOM VIEW

0.10 C

5

DETAIL A

A1

0.05 C

C

76XØb

Ø0.06 M C A B

Ø0.03 M C

A

DETAIL A

SIDE VIEW

NOTES:

1. ALL DIMENSIONS ARE IN MILLIMETERS.

DIMENSIONS

NOM.

SYMBOL

2. SOLDER BALL POSITION DESIGNATION PER JEP95, SECTION 3, SPP-020.

3. "e" REPRESENTS THE SOLDER BALL GRID PITCH.

MIN.

MAX.

0.40

A

-

0.08

4. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D" DIRECTION.

SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION.

N IS THE NUMBER OF POPULATED SOLDER BALL POSITIONS FOR MATRIX

SIZE MD X ME.

0.088

A1

D

0.072

3.87 BSC

E

4.04 BSC

3.20 BSC

9

D1

E1

MD

ME

N

5.

DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A

PLANE PARALLEL TO DATUM C.

6.

"SD" AND "SE" ARE MEASURED WITH RESPECT TO DATUMS A AND B AND

DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW.

9

76

WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW,

"SD" OR "SE" = 0.

0.25

b

0.22

0.28

eD

eE

SD

SE

0.40 BSC

0.381

WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW,

"SD" = eD/2 AND "SE" = eE/2.

A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK

METALIZED MARK, INDENTATION OR OTHER MEANS.

7.

0.321

8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED SOLDER

BALLS.

002-10658 **

Figure 10

76-ball thin WLCSP package outline

Datasheet

60

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PSoC™ 4 MCU with AIROC™ Bluetooth® LE

Based on Arm® Cortex®-M0

Acronyms

8

Acronyms

Table 62

Acronym

ABUS

ADC

Acronyms used in this document

Description

analog local bus

analog-to-digital converter

analog global

AG

AHB

AMBA (advanced microcontroller bus architecture) high-performance bus, an Arm® data transfer

bus

ALU

arithmetic logic unit

AMUXBUS analog multiplexer bus

API

application programming interface

APSR

Arm^®

ATM

BW

application program status register

advanced RISC machine, a CPU architecture

automatic thump mode

bandwidth

CAN

CMRR

CPU

CRC

DAC

DFB

DIO

DMIPS

DMA

DNL

DNU

DR

Controller Area Network, a communications protocol

common-mode rejection ratio

central processing unit

cyclic redundancy check, an error-checking protocol

digital-to-analog converter, see also IDAC, VDAC

digital filter block

digital input/output, GPIO with only digital capabilities, no analog. See GPIO.

Dhrystone million instructions per second

direct memory access, see also TD

differential nonlinearity, see also INL

do not use

port write data registers

DSI

digital system interconnect

DWT

ECC

data watchpoint and trace

error correcting code

ECO

EEPROM

EMI

EMIF

EOC

EOF

EPSR

ESD

ETM

FET

external crystal oscillator

electrically erasable programmable read-only memory

electromagnetic interference

external memory interface

end of conversion

end of frame

execution program status register

electrostatic discharge

embedded trace macrocell

field-effect transistor

FIR

finite impulse response, see also IIR

Datasheet

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Based on Arm® Cortex®-M0

Acronyms

Table 62

Acronym

FPB

Acronyms used in this document ^(continued)

Description

flash patch and breakpoint

FS

full-speed

GPIO

HCI

HVI

general-purpose input/output, applies to a PSoC™ pin

host controller interface

high-voltage interrupt, see also LVI, LVD

integrated circuit

IC

IDAC

IDE

current DAC, see also DAC, VDAC

integrated development environment

I²C, or IIC Inter-Integrated Circuit, a communications protocol

IIR

ILO

IMO

INL

I/O

IPOR

IPSR

IRQ

infinite impulse response, see also FIR

internal low-speed oscillator, see also IMO

internal main oscillator, see also ILO

integral nonlinearity, see also DNL

input/output, see also GPIO, DIO, SIO, USBIO

initial power-on reset

interrupt program status register

interrupt request

ITM

LCD

LIN

instrumentation trace macrocell

liquid crystal display

Local Interconnect Network, a communications protocol.

link register

LR

LUT

LVD

LVI

LVTTL

MAC

MCU

MISO

NC

lookup table

low-voltage detect, see also LVI

low-voltage interrupt, see also HVI

low-voltage transistor-transistor logic

multiply-accumulate

microcontroller unit

master-in slave-out

no connect

NMI

NRZ

NVIC

NVL

Opamp

PAL

PC

nonmaskable interrupt

non-return-to-zero

nested vectored interrupt controller

nonvolatile latch, see also WOL

operational amplifier

programmable array logic, see also PLD

program counter

PCB

PGA

PHUB

PHY

printed circuit board

programmable gain amplifier

peripheral hub

physical layer

Datasheet

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PSoC™ 4 MCU with AIROC™ Bluetooth® LE

Based on Arm® Cortex®-M0

Acronyms

Table 62

Acronym

PICU

PLA

PLD

PLL

Acronyms used in this document ^(continued)

Description

port interrupt control unit

programmable logic array

programmable logic device, see also PAL

phase-locked loop

PMDD

POR

PRES

PRS

package material declaration data sheet

power-on reset

precise power-on reset

pseudo random sequence

port read data register

PS

PSoC™

PSRR

PWM

RAM

RISC

RMS

RTC

Programmable system on chip

power supply rejection ratio

pulse-width modulator

random-access memory

reduced-instruction-set computing

root-mean-square

real-time clock

RTL

RTR

RX

register transfer language

remote transmission request

receive

SAR

SC/CT

SCL

successive approximation register

switched capacitor/continuous time

I²C serial clock

SDA

I²C serial data

S/H

sample and hold

SINAD

SIO

SOC

SOF

signal to noise and distortion ratio

special input/output, GPIO with advanced features. See GPIO.

start of conversion

start of frame

SPI

SR

Serial Peripheral Interface, a communications protocol

slew rate

SRAM

SRES

STN

static random access memory

software reset

super twisted nematic

SWD

SWV

TD

THD

TIA

serial wire debug, a test protocol

single-wire viewer

transaction descriptor, see also DMA

total harmonic distortion

transimpedance amplifier

twisted nematic

TN

TRM

technical reference manual

Datasheet

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PSoC™ 4 MCU with AIROC™ Bluetooth® LE

Based on Arm® Cortex®-M0

Acronyms

Table 62

Acronym

TTL

Acronyms used in this document ^(continued)

Description

transistor-transistor logic

TX

transmit

UART

WOL

WRES

XRES

XTAL

Universal Asynchronous Transmitter Receiver, a communications protocol

write once latch, see also NVL

watchdog timer reset

external reset I/O pin

crystal

UDB

universal digital block

USB

Universal Serial Bus

USBIO

VDAC

WDT

USB input/output, PSoC™ pins used to connect to a USB port

voltage DAC, see also DAC, IDAC

watchdog timer

Datasheet

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PSoC™ 4 MCU with AIROC™ Bluetooth® LE

Based on Arm® Cortex®-M0

Document conventions

9

Document conventions

9.1

Units of measure

Table 63

Units of measure

Symbol

Units of measure

°C

dB

degrees Celsius

decibel

dBm

fF

Hz

decibel-milliwatts

femtofarads

hertz

KB

1024 bytes

kbps

Khr

kHz

k

ksps

LSB

Mbps

MHz

M

Msps

µA

kilobits per second

kilohour

kilohertz

kilo ohm

kilosamples per second

least significant bit

megabits per second

megahertz

mega-ohm

megasamples per second

microampere

microfarad

µF

µH

µs

µV

microhenry

microsecond

microvolt

µW

mA

ms

mV

nA

microwatt

milliampere

millisecond

millivolt

nanoampere

nanosecond

nanovolt

ns

nV



ohm

pF

picofarad

ppm

ps

s

parts per million

picosecond

second

sps

sqrtHz

V

samples per second

square root of hertz

volt

Datasheet

65

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PSoC™ 4 MCU with AIROC™ Bluetooth® LE

Based on Arm® Cortex®-M0

Revision history

Document

Date

Description of changes

revision

**

2018-02-22

New datasheet

Updated datasheet to IFX template.

*A

*B

2021-06-16

2023-03-29

Changed title to “PSoC™ 4 CY8C41xx-BL MCU with AIROC™ Bluetooth® LE

Family Datasheet”.

Updated to the latest template

Added Table 3 for 76-ball WLCSP package

Removed the following part numbers from Table 57:

CY8C4128FNI-BL543, CY8C4128FNI-BL553, CY8C4128FNI-BL563,

CY8C4128FNI-BL583, and CY8C4128FNI-BL593

Datasheet

66

002-23052 Rev. *B

2023-03-29

Please read the Important Notice and Warnings at the end of this document

Trademarks

All referenced product or service names and trademarks are the property of their respective owners.

IMPORTANT NOTICE

WARNINGS

The information given in this document shall in no Due to technical requirements products may contain

Edition 2023-03-29

Published by

event be regarded as a guarantee of conditions or dangerous substances. For information on the types

characteristics (“Beschaffenheitsgarantie”).

in question please contact your nearest Infineon

Technologies office.

With respect to any examples, hints or any typical

Infineon Technologies AG

81726 Munich, Germany

values stated herein and/or any information Except as otherwise explicitly approved by Infineon

regarding the application of the product, Infineon Technologies in

a

written document signed by

Technologies hereby disclaims any and all authorized

representatives of Infineon

warranties and liabilities of any kind, including Technologies, Infineon Technologies’ products may

without limitation warranties of non-infringement of not be used in any applications where a failure of the

intellectual property rights of any third party.

product or any consequences of the use thereof can

reasonably be expected to result in personal injury.

In addition, any information given in this document

is subject to customer’s compliance with its

obligations stated in this document and any

applicable legal requirements, norms and standards

concerning customer’s products and any use of the

product of Infineon Technologies in customer’s

applications.

Do you have a question about this

document?

Email:

erratum@infineon.com

The data contained in this document is exclusively

intended for technically trained staff. It is the

responsibility of customer’s technical departments

to evaluate the suitability of the product for the

intended application and the completeness of the

product information given in this document with

respect to such application.

Document reference

002-23052 Rev. *B


型号：	CY8C4128LQI-BL593
厂家：	Infineon
描述：	32位PSoC™ 4 Arm® Cortex®-M0/M0+
文件：	总67页 (文件大小：1605K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

CY8C4128LQI-BL593 [INFINEON]

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