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PSoC 4: PSoC 4100PS Datasheet

Programmable System-on-Chip (PSoC)

General Description

Cypress' PSoC^®4 is a scalable and reconfigurable platform architecture for a family of programmable embedded system controllers

with an Arm^®Cortex™-M0+ CPU. It combines programmable and reconfigurable analog and digital blocks with flexible automatic

routing. PSoC 4100PS is a member of the PSoC 4 platform architecture. It is a combination of a microcontroller with standard

communication and timing peripherals, a capacitive touch-sensing system (CapSense) with best-in-class performance, programmable

general-purpose continuous-time and switched-capacitor analog blocks, and programmable connectivity.

Features

Programmable Analog Blocks

Low-Power Operation

■ Two dedicated analog-to-digital converters (ADC) including a

■ 1.71-V to 5.5-V operation

12-bit SAR ADC and a 10-bit single-slope ADC

■ Deep-Sleep mode with operational analog and 2.5-µA digital

■ Four opamps, two low-power comparators, and a flexible

38-channel analog mux to create custom Analog Front Ends

(AFE)

system current

■ Watch Crystal Oscillator (WCO)

Programmable GPIO Pins

■ Two 13-bit Voltage DACs

■ Up to 38 GPIOs that can be used for analog, digital, CapSense,

orLCDfunctionswithprogrammabledrivemodes,strengthand

slew rates

■ Two 7-bit Current DACs (IDACs) for general-purpose or capac-

itive sensing applications on any pin

®

CapSense Capacitive Sensing

■ Includes eight Smart I/Os to implement pin-level Boolean

■ Cypress's fourth-generation CapSense Sigma-Delta (CSD)

providing best-in-class signal-to-noise ratio (SNR) and water

tolerance

operations on input and output signals

■ 48-pin QFN, 48-pin TQFP, 28-pin SSOP, and 45-ball WLCSP

packages

■ Cypress-supplied software component makes capacitive

sensing design easy

PSoC Creator Design Environment

■ Integrated Design Environment (IDE) provides

schematic-capture design entry and build (with automatic

routing of analog and digital signals) and concurrent firmware

development with an Arm-SWD debugger

■ Automatic hardware tuning (SmartSense™)

Segment LCD Drive

■ LCD drive supported on all pins (common or segment)

■ Operates in Deep-Sleep mode with four bits per pin memory

■ GUI-based configurable PSoC Components with fully

engineered embedded initialization, calibration and correction

algorithms

Programmable Digital Peripherals

■ Application Programming Interfaces (API) for all fixed-function

and programmable peripherals

■ Three independent serial communication blocks (SCBs) that

are run-time configurable as I2C, SPI or UART

Industry-Standard Tool Compatibility

■ Eight 16-bit timer/counter/pulse-width modulator (TCPWM)

blocks with center-aligned, edge, and pseudo-random modes

■ After schematic-capture, firmware development can be done

with Arm-based industry-standard development tools

32-bit Signal Processing Engine

■ Arm Cortex-M0+ CPU up to 48 MHz

■ Up to 32 KB of flash with read accelerator

■ Up to 4 KB of SRAM

■ Eight-channel descriptor-based DMA controller

Cypress Semiconductor Corporation

Document Number: 002-22097 Rev. *E

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised December 17, 2020

PSoC 4: PSoC 4100PS Datasheet

More Information

Cypress provides a wealth of data at www.cypress.com to help you to select the right PSoC device for your design, and to help you

to quickly and effectively integrate the device into your design. For a comprehensive list of resources, see the knowledge base article

KBA86521, How to Design with PSoC 3, PSoC 4, and PSoC 5LP. Following is an abbreviated list for PSoC 4:

■ Overview: PSoC Portfolio, PSoC Roadmap

■ Software User Guide:

❐ A step-by-step guide for using PSoC Creator. The software

user guide shows you how the PSoC Creator build process

works in detail, how to use source control with PSoC Creator,

and much more.

■ Product Selectors: PSoC 1, PSoC 3, PSoC 4, PSoC 5LP

In addition, PSoC Creator includes a device selection tool.

■ Application notes: Cypress offers a large number of PSoC

application notes covering a broad range of topics, from basic

to advanced level. Recommended application notes for getting

started with PSoC 4 are:

❐ AN79953: Getting Started With PSoC 4

❐ AN88619: PSoC 4 Hardware Design Considerations

❐ AN86439: Using PSoC 4 GPIO Pins

■ Component Datasheets:

❐ The flexibility of PSoC allows the creation of new peripherals

(components) long after the device has gone into production.

Component datasheets provide all the information needed to

select and use a particular component, including a functional

description, API documentation, example code, and AC/DC

specifications.

❐ AN57821: Mixed Signal Circuit Board Layout

❐ AN81623: Digital Design Best Practices

❐ AN73854: Introduction To Bootloaders

❐ AN89610: Arm Cortex Code Optimization

■ Online:

❐ In addition to print documentation, the Cypress PSoC forums

connect you with fellow PSoC users and experts in PSoC

from around the world, 24 hours a day, 7 days a week.

❐ AN85951: PSoC^®4 and PSoC Analog Coprocessor

CapSense^®Design Guide

■ Technical Reference Manual (TRM) is in two documents:

❐ Architecture TRM details each PSoC 4 functional block.

❐ Registers TRM describes each of the PSoC 4 registers.

■ Development Kits:

❐ CY8CKIT-147 PSoC^®4100PS Prototyping Kit enables you

to evaluate and develop with PSoC 4100PS devices at a low

cost.

The MiniProg3 device provides an interface for flash

programming and debug.

Document Number: 002-22097 Rev. *E

Page 2 of 45

PSoC 4: PSoC 4100PS Datasheet

PSoC Creator

PSoC Creator is a free Windows-based Integrated Design Environment (IDE). It enables concurrent hardware and firmware design

of PSoC 3, PSoC 4, and PSoC 5LP based systems. Create designs using classic, familiar schematic capture supported by over 100

pre-verified, production-ready PSoC Components; see the list of component datasheets. With PSoC Creator, you can:

1. Drag and drop component icons to build your hardware

system design in the main design workspace

3. Configure components using the configuration tools

4. Explore the library of 100+ components

5. Review component datasheets

2. Codesign your application firmware with the PSoC hardware,

using the PSoC Creator IDE C compiler

Figure 1. Multiple-Sensor Example Project in PSoC Creator

1

2

3

4

5

Document Number: 002-22097 Rev. *E

Page 3 of 45

PSoC 4: PSoC 4100PS Datasheet

Contents

Functional Definition ........................................................6

CPU and Memory Subsystem .....................................6

System Resources ......................................................6

Analog Blocks ..............................................................7

Fixed Function Digital ..................................................8

GPIO ...........................................................................8

Special Function Peripherals .......................................9

WLCSP Package Bootloader ......................................9

Pinouts ............................................................................10

Alternate Pin Functions .............................................12

Power ...............................................................................14

Mode 1: 1.8 V to 5.5 V External Supply ....................14

Development Support ....................................................15

Documentation ..........................................................15

Online ........................................................................15

Tools ..........................................................................15

Electrical Specifications ................................................16

Absolute Maximum Ratings ......................................16

Device Level Specifications .......................................16

Analog Peripherals ....................................................20

Digital Peripherals .....................................................30

Memory .....................................................................32

System Resources ....................................................33

Ordering Information ......................................................35

Packaging ........................................................................37

Package Diagrams ....................................................38

Acronyms ........................................................................41

Document Conventions .................................................43

Units of Measure .......................................................43

Revision History .............................................................44

Sales, Solutions, and Legal Information ......................45

Worldwide Sales and Design Support .......................45

Products ....................................................................45

PSoC® Solutions ......................................................45

Cypress Developer Community .................................45

Technical Support .....................................................45

Document Number: 002-22097 Rev. *E

Page 4 of 45

PSoC 4: PSoC 4100PS Datasheet

Figure 2. Block Diagram

CPCUPUSuSbusbysytesmtem

PSoC 4100PS

Architecture

SWD/ TC

Cortex

M0+

SPCIF

FLASH

32KB

SRAM

4KB

ROM

8 KB

DataWire/

DMA

32-bit

48 MHz

AHB-Lite

FAST MUL

Read Accelerator

SRAM Controller

ROM Controller

Initiator / MMIO

NVIC, IRQMX

System Resources

Lite

System Interconnect(Multi Layer AHB)

Peripheral Interconnect (MMIO)

Power

Sleep Control

WIC

Peripherals

POR

REF

PCLK

PWRSYS

Clock

Clock Control

WDT

Programmable

Analog

IMO

ILO

Reset

Reset Control

XRES

VDAC

(13-bit)

SAR ADC

(12-bit)

Test

DFT Logic

x1

x2

DFT Analog

SARMUX

CTB

2x Opamp

x2

Power Modes

Active/Sleep

Deep Sleep

High Speed I /O Matrix , Smart I/O

38 x GPIO, LCD

I/O Subsystem

PSoC 4100PS devices include extensive support for

programming, testing, debugging, and tracing both hardware

and firmware.

The debug circuits are enabled by default and can be disabled

in firmware. If they are not enabled, the only way to re-enable

them is to erase the entire device, clear flash protection, and

reprogram the device with new firmware that enables debugging.

Thus firmware control of debugging cannot be over-ridden

without erasing the firmware thus providing security.

The Arm Serial-Wire Debug (SWD) interface supports all

programming and debug features of the device.

Complete debug-on-chip functionality enables full-device

debugging in the final system using the standard production

device. It does not require special interfaces, debugging pods,

simulators, or emulators. Only the standard programming

connections are required to fully support debug.

Additionally, all device interfaces can be permanently disabled

(device security) for applications concerned about phishing

attacks due to a maliciously reprogrammed device or attempts to

defeat security by starting and interrupting flash programming

sequences. All programming, debug, and test interfaces are

disabled when maximum device security is enabled. Therefore,

PSoC 4100PS, with device security enabled, may not be

returned for failure analysis. This is a trade-off the PSoC 4100PS

allows the customer to make.

The PSoC Creator IDE provides fully integrated programming

and debug support for the PSoC 4100PS devices. The SWD

interface is fully compatible with industry-standard third-party

tools. The PSoC 4100PS family provides a level of security not

possible with multi-chip application solutions or with

microcontrollers. It has the following advantages:

■ Allows disabling of debug features

■ Robust flash protection

■ Allows customer-proprietary functionality to be implemented in

on-chip programmable blocks

Document Number: 002-22097 Rev. *E

Page 5 of 45

PSoC 4: PSoC 4100PS Datasheet

instantaneous wake-up on a wake-up event. In Deep Sleep

mode, the high-speed clock and associated circuitry is switched

off; wake-up from this mode takes 35 µs. The opamps can

remain operational in Deep Sleep mode.

Functional Definition

CPU and Memory Subsystem

CPU

Clock System

The Cortex-M0+ CPU in the PSoC 4100PS is part of the 32-bit

MCU subsystem, which is optimized for low-power operation

with extensive clock gating. Most instructions are 16 bits in length

and the CPU executes a subset of the Thumb-2 instruction set.

It includes a nested vectored interrupt controller (NVIC) block

with eight interrupt inputs and also includes a Wakeup Interrupt

Controller (WIC). The WIC can wake the processor from Deep

Sleep mode, allowing power to be switched off to the main

processor when the chip is in Deep Sleep mode.

The PSoC 4100PS clock system is responsible for providing

clocks to all subsystems that require clocks and for switching

between different clock sources without glitching. In addition, the

clock system ensures that there are no metastable conditions.

The clock system for the PSoC 4100PS consists of the internal

main oscillator (IMO), internal low-frequency oscillator (ILO), a

32 kHz Watch Crystal Oscillator (WCO) and provision for an

external clock. Clock dividers are provided to generate clocks for

peripherals on a fine-grained basis. Fractional dividers are also

provided to enable clocking of higher data rates for UARTs.

The CPU also includes a debug interface, the serial wire debug

(SWD) interface, which is a two-wire form of JTAG. The debug

configuration used for PSoC 4100PS has four breakpoint

(address) comparators and two watchpoint (data) comparators.

Figure 3. PSoC 4100PS MCU Clocking Architecture

IMO

DMA/DataWire

HFCLK

Divide By

2,4,8

The DMA engine will be capable of doing independent data

transfers anywhere within the memory map via a user-program-

mable descriptor chain. The DataWire capability is used to effect

single-element transfers from one location in memory to another.

There are eight DMA channels with a range of selectable trigger

sources.

External Clock

WDC0

16-bits

WCO

LFCLK

W DC1

16-bits

ILO

W DC2

32-bits

Watchdog Counters (W DC)

WDT

Flash

Watchdog Timer (WDT)

The PSoC 4100PS device has a flash module with a flash

accelerator, tightly coupled to the CPU to improve average

access times from the flash block. The low-power flash block is

designed to deliver two wait-state (WS) access time at 48 MHz.

The flash accelerator delivers 85% of single-cycle SRAM access

performance on average.

Prescaler

SYSCLK

7X 16-bit

HFCLK

Integer

Dividers

Fractional

Dividers

3X 16.5-bit, 1X 24.5 bit

SRAM

Four KB of SRAM are provided with zero wait-state access at

48 MHz.

The HFCLK signal can be divided down to generate

synchronous clocks for the analog and digital peripherals. There

are 11 clock dividers for PSoC 4100PS as shown in the diagram

above.. The 16-bit capability allows flexible generation of

fine-grained frequency values (there is one 24-bit divider for

large divide ratios), and is fully supported in PSoC Creator.

SROM

Eight KB of SROM are provided that contain boot and configu-

ration routines.

System Resources

IMO Clock Source

Power System

The IMO is the primary source of internal clocking in

PSoC 4100PS. It is trimmed during testing to achieve the

specified accuracy.The IMO default frequency is 24 MHz and it

can be adjusted from 24 to 48 MHz in steps of 4 MHz. The IMO

tolerance with Cypress-provided calibration settings is ±2%.

The power system is described in detail in the section Power on

page 14. It provides an assurance that voltage levels are as

required for each respective mode and either delays mode entry

(for example, on power-on reset (POR) until voltage levels are

as required for proper functionality, or generates resets (for

example, on brown-out detection). PSoC 4100PS operates with

a single external supply over the range of either 1.8 V ±5%

(externally regulated) or 1.8 to 5.5 V (internally regulated) and

has three different power modes, transitions between which are

managed by the power system. PSoC 4100PS provides Active,

Sleep, and Deep Sleep low-power modes.

ILO Clock Source

The ILO is a very low power, nominally 40-kHz oscillator, which

is primarily used to generate clocks for the watchdog timer

(WDT) and peripheral operation in Deep Sleep mode. ILO-driven

counters can be calibrated to the IMO to improve accuracy.

Cypress provides a software component, which does the

calibration.

All subsystems are operational in Active mode. The CPU

subsystem (CPU, flash, and SRAM) is clock-gated off in Sleep

mode, while all peripherals and interrupts are active with

Document Number: 002-22097 Rev. *E

Page 6 of 45

PSoC 4: PSoC 4100PS Datasheet

Watch Crystal Oscillator (WCO)

Analog Blocks

The PSoC 4100PS clock subsystem also implements a

low-frequency (32-kHz watch crystal) oscillator that can be used

for Watchdog timing applications.

12-bit SAR ADC

The 12-bit, 1-Msps SAR ADC can operate at a maximum clock

rate of 18 MHz and requires a minimum of 18 clocks at that

frequency to do a 12-bit conversion.

Watchdog Timer

A watchdog timer is implemented in the clock block running from

the ILO; this allows watchdog operation during Deep Sleep and

generates a watchdog reset if not serviced before the set timeout

occurs. The watchdog reset is recorded in a Reset Cause

register, which is firmware readable.

The Sample-and-Hold (S/H) aperture is programmable allowing

the gain bandwidth requirements of the amplifier driving the SAR

inputs, which determine its settling time, to be relaxed if required.

It is possible to provide an external bypass (through a fixed pin

location) for the internal reference amplifier.

The SAR is connected to a fixed set of pins through an 8-input

sequencer. The sequencer cycles through selected channels

autonomously (sequencer scan) with zero switching overhead

(that is, aggregate sampling bandwidth is equal to 1 Msps

whether it is for a single channel or distributed over several

channels). The sequencer switching is effected through a state

machine or through firmware driven switching. A feature

provided by the sequencer is buffering of each channel to reduce

CPU interrupt service requirements. To accommodate signals

with varying source impedance and frequency, it is possible to

have different sample times programmable for each channel.

Also, signal range specification through a pair of range registers

(low and high range values) is implemented with a corresponding

out-of-range interrupt if the digitized value exceeds the

programmed range; this allows fast detection of out-of-range

values without the necessity of having to wait for a sequencer

scan to be completed and the CPU to read the values and check

for out-of-range values in software.

Reset

PSoC 4100PS can be reset from a variety of sources including

a software reset. Reset events are asynchronous and guarantee

reversion to a known state. The reset cause is recorded in a

register, which is sticky through reset and allows software to

determine the cause of the reset. An XRES pin is reserved for

external reset by asserting it active low. The XRES pin has an

internal pull-up resistor that is always enabled.

Voltage Reference

The PSoC 4100PS reference system generates all internally

required references. A1.2-V voltage reference is provided for the

comparator. The IDACs are based on a ±5% reference.

The SAR is not available in Deep Sleep mode as it requires a

high-speed clock (up to 18 MHz). The SAR operating range is

1.71 V to 5.5 V.

Figure 4. SAR ADC

AHB System Bus and Programmable Logic

Interconnect

SAR Sequencer

Sequencing

and Control

Data and

Status Flags

POS

NEG

SARADC

External

Reference

and

Bypass

(optional )

Reference

Selection

VDDA

VREF

VDDA/2

Inputs from other Ports

Four Opamps (Continuous-Time Block; CTB)

VDAC (13 bits)

PSoC 4100PS has four opamps with Comparator modes which

allow most common analog functions to be performed on-chip

eliminating external components; PGAs, Voltage Buffers, Filters,

Trans-Impedance Amplifiers, and other functions can be

realized, in some cases with external passives, saving power,

cost, and space. The on-chip opamps are designed with enough

bandwidth to drive the Sample-and-Hold circuit of the ADC

without requiring external buffering.

The PSoC 4100PS has two 13-bit resolution Voltage DACs.

Low-power Comparators (LPC)

PSoC 4100PS has a pair of low-power comparators, which can

also operate in Deep Sleep modes. This allows the analog

system blocks to be disabled while retaining the ability to monitor

external voltage levels during low-power modes. The

comparator outputs are normally synchronized to avoid

metastability unless operating in an asynchronous power mode

where the system wake-up circuit is activated by a comparator

switch event. The LPC outputs can be routed to pins.

Document Number: 002-22097 Rev. *E

Page 7 of 45

PSoC 4: PSoC 4100PS Datasheet

Current DACs

■ GPIO cells are not overvoltage tolerant and, therefore, cannot

be hot-swapped or powered up independently of the rest of the

I²C system.

PSoC 4100PS has two IDACs, which can drive any of the pins

on the chip. These IDACs have programmable current ranges.

UART Mode: This is a full-feature UART operating at up to

1 Mbps. It supports automotive single-wire interface (LIN),

infrared interface (IrDA), and SmartCard (ISO7816) protocols, all

of which are minor variants of the basic UART protocol. In

addition, it supports the 9-bit multiprocessor mode that allows

addressing of peripherals connected over common RX and TX

lines. Common UART functions such as parity error, break

detect, and frame error are supported. An 8-deep FIFO allows

much greater CPU service latencies to be tolerated.

Analog Multiplexed Buses

PSoC 4100PS has two concentric independent buses that go

around the periphery of the chip. These buses (called amux

buses) are connected to firmware-programmable analog

switches that allow the chip's internal resources (IDACs,

comparator) to connect to any pin on the I/O Ports.

Temperature Sensor

There is an on-chip temperature sensor which is calibrated

during production to achieve ±1% typical (±5% maximum)

deviation from accuracy. The SAR ADC is used to measure the

temperature.

SPI Mode: The SPI mode supports full Motorola SPI, TI SSP

(adds a start pulse used to synchronize SPI Codecs), and

National Microwire (half-duplex form of SPI). The SPI block can

use the FIFO.

Fixed Function Digital

GPIO

PSoC 4100PS has up to 38 GPIOs. The GPIO block implements

the following:

■ Eight drive modes:

Timer/Counter/PWM (TCPWM) Block

The TCPWM block consists of

a 16-bit counter with

user-programmable period length. There is a capture register to

record the count value at the time of an event (which may be an

I/O event), a period register that is used to either stop or

auto-reload the counter when its count is equal to the period

register, and compare registers to generate compare value

signals that are used as PWM duty cycle outputs. The block also

provides true and complementary outputs with programmable

offset between them to allow use as dead-band programmable

complementary PWM outputs. It also has a Kill input to force

outputs to a predetermined state; for example, this is used in

motor drive systems when an over-current state is indicated and

the PWM driving the FETs needs to be shut off immediately with

no time for software intervention. There are eight TCPWM blocks

in PSoC 4100PS.

❐ Analog input mode (input and output buffers disabled)

❐ Input only

❐ Weak pull-up with strong pull-down

❐ Strong pull-up with weak pull-down

❐ Open drain with strong pull-down

❐ Open drain with strong pull-up

❐ Strong pull-up with strong pull-down

❐ Weak pull-up with weak pull-down

■ Input threshold select (CMOS or LVTTL)

■ Individual control of input and output buffer enabling/disabling

in addition to the drive strength modes

■ Selectable slew rates for dV/dt related noise control to improve

EMI.

Serial Communication Block (SCB)

The pins are organized in logical entities called ports, which are

8-bit in width (less for Ports 2 and 3). During power-on and reset,

the blocks are forced to the disable state so as not to crowbar

any inputs and/or cause excess turn-on current. A multiplexing

network known as a high-speed I/O matrix is used to multiplex

between various signals that may connect to an I/O pin.

PSoC 4100PS has three serial communication blocks, which can

be programmed to have SPI, I²C, or UART functionality.

I²C Mode: The hardware I²C block implements

a full

multi-master and slave interface (it is capable of multi-master

arbitration). This block is capable of operating at speeds of up to

1 Mbps (Fast Mode Plus) and has flexible buffering options to

reduce interrupt overhead and latency for the CPU. It also

supports EZI2C that creates a mailbox address range in the

memory of PSoC 4100PS and effectively reduces I²C communi-

cation to reading from and writing to an array in memory. In

addition, the block supports an 8-deep FIFO for receive and

transmit which, by increasing the time given for the CPU to read

data, greatly reduces the need for clock stretching caused by the

CPU not having read data on time.

Data output and pin state registers store, respectively, the values

to be driven on the pins and the states of the pins themselves.

Every I/O pin can generate an interrupt if so enabled; each I/O

port has an interrupt request (IRQ) and interrupt service routine

(ISR) vector associated with it (4 for PSoC 4100PS). The Smart

I/O block is a fabric of switches and LUTs that allows Boolean

functions to be performed on signals being routed to the pins of

a GPIO port. The Smart I/O block can perform logical operations

on input pins to the chip and on signals going out as outputs.

The I²C peripheral is compatible with the I²C Standard-mode and

Fast-mode devices as defined in the NXP I²C-bus specification

and user manual (UM10204). The I²C bus I/O is implemented

with GPIO in open-drain modes.

PSoC 4100PS is not completely compliant with the I²C spec in

the following respect:

Document Number: 002-22097 Rev. *E

Page 8 of 45

PSoC 4: PSoC 4100PS Datasheet

Special Function Peripherals

WLCSP Package Bootloader

The WLCSP package is supplied with an I²C bootloader installed

in flash. The bootloader is compatible with PSoC Creator

bootloader project files.

CapSense

CapSense is supported in PSoC 4100PS through a CSD block

that can be connected to any pins through an analog mux bus

via an analog switch. CapSense function can thus be provided

on any available pin or group of pins in a system under software

control. A PSoC Creator component is provided for the

CapSense block to make it easy for the user.

Shield voltage can be driven on another mux bus to provide

water-tolerance capability. Water tolerance is provided by driving

the shield electrode in phase with the sense electrode to keep

the shield capacitance from attenuating the sensed input.

Proximity sensing can also be implemented.

The CapSense block has two IDACs, which can be used for

general purposes if CapSense is not being used (both IDACs are

available in that case) or if CapSense is used without water

tolerance (one IDAC is available). The CapSense block also

provides a 10-bit Slope ADC function, which can be used in

conjunction with the CapSense function.

The CapSense block is an advanced, low-noise, programmable

block with programmable voltage references and current source

ranges for improved sensitivity and flexibility. It can also use an

external reference voltage. It has a full-wave CSD mode that

alternates sensing to VDDA and ground to null out power-supply

related noise

Document Number: 002-22097 Rev. *E

Page 9 of 45

PSoC 4: PSoC 4100PS Datasheet

Pinouts

The following table provides the pin list for PSoC 4100PS for the 48-QFN, 48-TQFP, 45-WLCSP, and 28-SSOP packages. All port

pins support GPIO.

Packages

48-QFN

Name

48-TQFP

Name

28-SSOP

Name

45-CSP

Name

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

21

D3

E2

D2

C3

D1

E1

C2

B2

B3

A1

B1

B4

C1

A2

A3

J2

P0.0

P0.1

P0.2

P0.3

P0.4

P0.5

P0.6

P0.7

XRES

P4.0

P4.1

P5.0

P5.1

P5.2

P5.3

VDDA

VSSA

VCCD

P0.0

P0.1

P0.2

P0.3

P0.4

P0.5

P0.6

P0.7

XRES

P4.0

P4.1

P5.0

P5.1

P5.2

P5.3

VDDA

VSSA

VCCD

P0.0

P0.1

P0.2

P0.0

P0.1

22

23

P0.2

P0.3

P0.4

P0.5

P0.6

P0.7

24

25

XRES

P5.0

XRES

P4.0

P4.1

P5.0

P5.1

26

27

28

P5.2

P5.3

P5.2

P5.3

VDDA

VSSA

VCCD

VDDD

VSSD

J3

1

VCCD

A4

B5

A5

46

47

48

1

VSSD

VDDD

P1.0

P1.1

P1.2

P1.3

P1.4

P1.5

P1.6

P1.7

VDDA

VSSA

P2.0

P2.1

P2.2

P2.3

P2.4

P2.5

P2.6

46

47

48

1

VSSD

VDDD

P1.0

P1.1

P1.2

P1.3

P1.4

P1.5

P1.6

P1.7

VDDA

VSSA

P2.0

P2.1

P2.2

P2.3

P2.4

P2.5

P2.6

2

3

4

5

6

7

VSSD

VDDD

P1.0

C5

C4

D5

D4

E3

E4

P1.0

P1.1

P1.2

P1.3

P1.4

P1.5

P1.1

2

P1.2

3

P1.3

4

5

6

7

G3

E5

F5

F4

F3

G4

G5

H5

J4

P1.7

VDDA

VSSA

P2.0

P2.1

P2.2

P2.3

P2.4

P2.5

P2.6

8

VDDA

VSSA

P2.0

9

10

11

12

13

14

15

16

10

11

12

13

14

15

16

10

11

12

13

P2.1

P2.2

P2.3

H4

Document Number: 002-22097 Rev. *E

Page 10 of 45

PSoC 4: PSoC 4100PS Datasheet

Packages

48-QFN

Name

48-TQFP

Name

28-SSOP

Name

45-CSP

17

18

19

20

21

22

23

24

25

26

27

17

18

19

20

21

22

23

24

25

26

27

J5

Name

P2.7/VREF

VSSA

VDDA

P3.0

P2.7/VREF

VSSA

VDDA

P3.0

P2.7/VREF

VSSA

VDDA

P3.0

14

P2.7/VREF

J3

15

VDDA

J2

H2

F2

J1

P3.1

16

17

18

P3.1

P3.2

P3.3

P3.1

P3.2

P3.3

H3

F1

G2

G1

H1

P3.3

P3.4

P3.5

P3.6

19

20

P3.6

P3.7

P3.6

P3.7

Descriptions of the Power pins are as follows:

VDDD: Power supply for the digital section.

VDDA: Power supply for the analog section.

VSS: Ground pin.

VCCD: Regulated digital supply (1.8 V ±5%)

The 48-pin packages have 38 I/O pins. The 45 CSP and the 28 SSOP have 37 and 20 I/O pins respectively.

Document Number: 002-22097 Rev. *E

Page 11 of 45

PSoC 4: PSoC 4100PS Datasheet

There are two distinct modes of operation. In Mode 1, the supply

voltage range is 1.8 V to 5.5 V (unregulated externally; internal

regulator operational). In Mode 2, the supply range is1.8 V ±5%

(externally regulated; 1.71 to 1.89, internal regulator bypassed).

Power

The following power system diagram shows the set of power

supply pins as implemented for the PSoC 4100PS. The system

has one regulator in Active mode for the digital circuitry. There is

no analog regulator; the analog circuits run directly from the

Mode 1: 1.8 V to 5.5 V External Supply

V

_DDAinput.

In this mode, the PSoC 4100PS is powered by an external power

supply that can be anywhere in the range of 1.8 to 5.5 V. This

range is also designed for battery-powered operation. For

example, the chip can be powered from a battery system that

starts at 3.5 V and works down to 1.8 V. In this mode, the internal

regulator of the PSoC 4100PS supplies the internal logic and its

output is connected to the V_CCDpin. The V_CCDpin must be

bypassed to ground via an external capacitor (0.1 µF; X5R

ceramic or better) and must not be connected to anything else.

Note that VDDD and VDDA must be shorted together on the

PCB.

Figure 5. Power Supply Connections

VDDA

Digital

Domain

Analog

Domain

VSSA

Mode 2: 1.8 V ±5% External Supply

In this mode, the PSoC 4100PS is powered by an external power

supply that must be within the range of 1.71 to 1.89 V; note that

this range needs to include the power supply ripple too. In this

mode, the V_DDDand V_CCDpins are shorted together and

bypassed.

VDDD

VCCD

VDDD

VSSD

1.8 Volt

Reg

Bypass capacitors must be used from V_DDDand V_DDAto ground.

The typical practice for systems in this frequency range is to use

a capacitor in the 1-µF range, in parallel with a smaller capacitor

(0.1 µF, for example). Note that these are simply rules of thumb

and that, for critical applications, the PCB layout, lead induc-

tance, and the bypass capacitor parasitic should be simulated to

design and obtain optimal bypassing.

Figure 6 shows an example of a bypass scheme.

Figure 6. External Supply Range from 1.8 V to 5.5 V with Internal Regulator Active

Power supply bypass connections example

1. 8V to 5.5 V

0. 1µF

1. 8 V to 5.5V

0. 1µF

V_DDA

V_DDD

1 µF

V_CCD

PSoC CY8C4Axx

0. 1µF

V_SS

Document Number: 002-22097 Rev. *E

Page 14 of 45

PSoC 4: PSoC 4100PS Datasheet

Technical Reference Manual: The Technical Reference Manual

(TRM) contains all the technical detail you need to use a PSoC

device, including a complete description of all PSoC registers.

The TRM is available in the Documentation section at

www.cypress.com/psoc4.

Development Support

The PSoC 4100PS family has a rich set of documentation,

development tools, and online resources to assist you during

your development process. Visit www.cypress.com/psoc4 to find

out more.

Online

Documentation

In addition to print documentation, the Cypress PSoC forums

connect you with fellow PSoC users and experts in PSoC from

around the world, 24 hours a day, 7 days a week.

A suite of documentation supports the PSoC 4100PS family to

ensure that you can find answers to your questions quickly. This

section contains a list of some of the key documents.

Tools

Software User Guide: A step-by-step guide for using PSoC

Creator. The software user guide shows you how the PSoC

Creator build process works in detail, how to use source control

with PSoC Creator, and much more.

With industry standard cores, programming, and debugging

interfaces, the PSoC 4100PS family is part of a development tool

ecosystem. Visit us at www.cypress.com/psoccreator for the

latest information on the revolutionary, easy to use PSoC Creator

IDE, supported third party compilers, programmers, debuggers,

and development kits.

Component Datasheets: The flexibility of PSoC allows the

creation of new peripherals (components) long after the device

has gone into production. Component data sheets provide all of

the information needed to select and use a particular component,

including a functional description, API documentation, example

code, and AC/DC specifications.

Application Notes: PSoC application notes discuss a particular

application of PSoC in depth; examples include brushless DC

motor control and on-chip filtering. Application notes often

include example projects in addition to the application note

document.

Document Number: 002-22097 Rev. *E

Page 15 of 45

PSoC 4: PSoC 4100PS Datasheet

Electrical Specifications

Absolute Maximum Ratings

Table 1. Absolute Maximum Ratings^[1]

Details/

Spec ID#

SID1

Parameter

V_{DD_ABS}

Description

Min

–0.5

Typ

–

Max

6

Unit

Conditions

V_DDD, V_DDA

,

Digital or Analog supply relative to V_SS

Absolute Max

Direct digital core voltage input relative

to V_SS

V

SID2

V_{CCD_ABS}

–

1.95

–

SID3

SID4

V_{GPIO_ABS}

I_{GPIO_ABS}

GPIO voltage

–0.5

–25

–

V_DD+0.5

25

–

Maximum current per GPIO

mA

GPIO injection current, Max for V_IH

_DDD, and Min for V_IL< V_SS

>

Current injected

per pin

SID5

I_{GPIO_injection}

ESD_HBM

–0.5

–

0.5

–

V

Electrostatic discharge human body

model

BID44

2200

–

V

Electrostatic discharge charged device

model

BID45

BID46

ESD_CDM

LU

500

–

Pin current for latch-up

–140

140

mA

Device Level Specifications

All specifications are valid for –40 °C  T_A 105 °C and T_J 125 °C, except where noted. Specifications are valid for 1.71 V to 5.5 V,

except where noted.

Table 2. DC Specifications

Typical values measured at V_DD= 3.3 V and 25 °C.

Details/

Conditions

Spec ID#

SID53

Parameter

V_DD

Description

Min

Typ

Max

Unit

With regulator

enabled

Power supply input voltage

1.8

–

5.5

V

Internally

unregulated supply

SID255

SID54

SID55

V_DD

1.71

–

1.89

V_DD

–

(V_CCD= V_DD

)

V_DDIO

C_EFC

V_DDIOdomain supply

–

X5R ceramic or

better

External regulator voltage bypass

0.1

µF

X5R ceramic or

better

SID56

C_EXC

Power supply bypass capacitor

–

1

–

Active Mode, V_DD= 1.8 V to 5.5 V. Typical values measured at VDD = 3.3 V and 25 °C.

SID10

SID16

SID19

I_DD5

I_DD8

I_DD11

Execute from flash; CPU at 6 MHz

Execute from flash; CPU at 24 MHz

Execute from flash; CPU at 48 MHz

–

2

–

5.6

mA

10.4

Sleep Mode, VDDD = 1.8 V to 5.5 V (Regulator on)

SID22

SID25

I_DD17

I_DD20

I²C wakeup WDT, and Comparators on.

I²C wakeup, WDT, and Comparators on.

–

1.1

3.1

–

mA 6 MHz

12 MHz

Note

1. Usage above the absolute maximum conditions listed in Table 1 may cause permanent damage to the device. Exposure to Absolute Maximum conditions for extended

periods of time may affect device reliability. The Maximum Storage Temperature is 150 °C in compliance with JEDEC Standard JESD22-A103, High Temperature

Storage Life. When used below Absolute Maximum conditions but above normal operating conditions, the device may not operate to specification.

Document Number: 002-22097 Rev. *E

Page 16 of 45

PSoC 4: PSoC 4100PS Datasheet

Table 2. DC Specifications (continued)

Typical values measured at V_DD= 3.3 V and 25 °C.

Details/

Conditions

Spec ID#

Parameter

Description

Min

Typ

Max

Unit

Sleep Mode, V_DDD= 1.71 V to 1.89 V (Regulator bypassed)

SID28

I_DD23

I²C wakeup, WDT, and Comparators on.

–

1.1

3.1

–

mA 6 MHz

mA 12 MHz

SID28A

I_DD23A

Deep Sleep Mode, V_DD= 1.8 V to 3.6 V (Regulator on)

SID31 I_DD26

I²C wakeup and WDT on

Deep Sleep Mode, V_DD= 3.6 V to 5.5 V (Regulator on)

SID34 I_DD29

I²C wakeup and WDT on

Deep Sleep Mode, V_DD= 1.71 V to 1.89 V (Regulator bypassed)

–

2.5

115

–

µA

–

SID37

I_DD32

I²C wakeup and WDT on

–

XRES Current

SID307

I_{DD_XR}

Supply current while XRES asserted

300

Table 3. AC Specifications

Spec ID# Parameter

SID48 F_CPU

Description

CPU frequency

Min

Typ

Max

Unit Details/Conditions

DC

–

0

48

–

MHz 1.71 V_DD5.5

SID49^[2]

SID50^[2]

T_SLEEP

Wakeup from Sleep mode

Wakeup from Deep Sleep mode

–

µs

–

T_DEEPSLEEP

–

35

–

Note

2. Guaranteed by characterization.

Document Number: 002-22097 Rev. *E

Page 17 of 45

PSoC 4: PSoC 4100PS Datasheet

GPIO

Table 4. GPIO DC Specifications

Spec ID#

SID57

Parameter

Description

Min

Typ

Max

Unit

Details/Conditions

[3]

V_IH

Input voltage high threshold

0.7 V_DDD

–

CMOS Input

0.3 

SID58

V_IL

V_IH

V_IL

Input voltage low threshold

LVTTL input, V_DDD< 2.7 V

–

CMOS Input

V_DDD

[3]

SID241

SID242

0.7 V_DDD

–

0.3 

–

V_DDD

SID243

SID244

SID59

SID60

SID61

SID62

SID62A

SID63

SID64

V_IH

V_IL

LVTTL input, V_DDD 2.7 V

Output voltage high level

Output voltage low level

Pull-up resistor

2.0

–

V

–

0.8

–

V_OH

V_DDD–0.6

–

I_OH= 4 mA at 3 V V_DDD

V_OH

V_DDD–0.5

–

I_OH= 1 mA at 1.8 V V_DDD

V_OL

–

0.6

0.4

8.5

I_OL= 4 mA at 1.8 V V_DDD

V_OL

–

I_OL= 10 mA at 3 V V_DDD

V_OL

–

I_OL= 3 mA at 3 V V_DDD

R_PULLUP

R_PULLDOWN

3.5

5.6

–

kΩ

Pull-down resistor

Input leakage current (absolute

value)

SID65

I_IL

–

2

–

nA

pF

SID66

C_IN

Input capacitance

–

15

3

40

–

7

–

SID67^[4]

SID68^[4]

SID68A^[4]

V_HYSTTL

V_HYSCMOS

Input hysteresis LVTTL

Input hysteresis CMOS

V_DDD 2.7 V

0.05 × V_DDD

200

mV V_DD< 4.5 V

V_DD> 4.5 V

V_HYSCMOS5V5Input hysteresis CMOS

–

Currentthroughprotectiondiodeto

_DD/V_SS

–

SID69^[4]

I_DIODE

–

100

85

µA

V

Maximum total source or sink chip

current

–

SID69A^[4]

I_{TOT_GPIO}

mA

Notes

3.

V

must not exceed V

+ 0.2 V.

IH

DDD

4. Guaranteed by characterization.

Document Number: 002-22097 Rev. *E

Page 18 of 45

PSoC 4: PSoC 4100PS Datasheet

Table 5. GPIO AC Specifications

(Guaranteed by Characterization)

Spec ID#

SID70

Parameter

Description

Min

Typ

Max

Unit

Details/Conditions

3.3 V V_DDD

Cload = 25 pF

3.3 V V_DDD

Cload = 25 pF

3.3 V V_DDD

Cload = 25 pF

3.3 V V_DDD

,

T_RISEF

Rise time in fast strong mode

2

–

12

ns

,

SID71

SID72

SID73

SID74

SID75

SID76

SID245

SID246

T_FALLF

Fall time in fast strong mode

Rise time in slow strong mode

Fall time in slow strong mode

2

10

–

12

60

16

7

,

T_RISES

ns

,

T_FALLS

Cload = 25 pF

GPIO F_OUT; 3.3 V  V_DDD5.5 V

Fast strong mode

90/10%, 25-pF load,

60/40 duty cycle

F_GPIOUT1

F_GPIOUT2

F_GPIOUT3

F_GPIOUT4

F_GPIOIN

GPIO F_OUT; 1.71 VV_DDD3.3 V

Fast strong mode

90/10%, 25-pF load,

60/40 duty cycle

–

GPIO F_OUT; 3.3 V V_DDD5.5 V

Slow strong mode

90/10%, 25-pF load,

60/40 duty cycle

–

MHz

GPIO F_OUT; 1.71 V V_DDD3.3 V

Slow strong mode.

90/10%, 25-pF load,

60/40 duty cycle

–

3.5

48

GPIO input operating frequency;

1.71 V V_DDD5.5 V

–

90/10% V_IO

XRES

Table 6. XRES DC Specifications

Spec ID# Parameter

SID77 V_IH

Description

Min

Typ

Max

Unit

Details/Conditions

Input voltage high threshold 0.7 × V_DDD

–

V

CMOS Input

SID78

SID79

SID80

V_IL

Input voltage low threshold

Pull-up resistor

–

0.3  V_DDD

R_PULLUP

C_IN

60

3

–

7

kΩ

pF

–

Input capacitance

0.05 

V_DD

Typical hysteresis is

200 mV for V_DD> 4.5 V

SID81^[5]

V_HYSXRES

Input voltage hysteresis

–

mV

Table 7. XRES AC Specifications

Spec ID#

SID83^[5]

Parameter

Description

Reset pulse width

Min

Typ

Max

Unit

Details/Conditions

T_RESETWIDTH

1

–

µs

–

Wake-up time from reset

release

–

BID194^[5]

T_RESETWAKE

–

2.5

ms

Note

5. Guaranteed by characterization.

Document Number: 002-22097 Rev. *E

Page 19 of 45

PSoC 4: PSoC 4100PS Datasheet

Analog Peripherals

Table 8. CTB Opamp Specifications

Spec ID#

Parameter

I_DD

Description

Opamp block current, No load

power=hi

Min

Typ

Max

Unit

Details/Conditions

SID269

SID270

SID271

I_{DD_HI}

–

1100

550

150

2070

950

–

I_{DD_MED}

I_{DD_LOW}

power=med

µA

power=lo

350

Load = 20 pF, 0.1 mA

G_BW

V_DDA= 2.7 V

Input and output are

0.2 V to V_DDA-0.2 V

SID272

SID273

SID274

G_{BW_HI}

G_{BW_MED}

power=hi

6

3

–

1

–

Input and output are

0.2 V to V_DDA-0.2 V

power=med

MHz

Input and output are

0.2 V to V_DDA-0.2 V

G_{BW_LO}

power=lo

I_{OUT_MAX}

I_{OUT_MAX_HI}

V_DDA= 2.7 V, 500 mV from rail

power=hi

Output is 0.5 V

SID275

SID276

SID277

10

–

5

–

V

_DDA-0.5 V

Output is 0.5 V

_DDA-0.5 V

Output is 0.5 V

_DDA-0.5 V

I_{OUT_MAX_MID}

power=mid

mA

V

I_{OUT_MAX_LO}

I_OUT

power=lo

V

V_DDA= 1.71 V, 500 mV from rail

power=hi

Output is 0.5 V

V_DDA-0.5 V

SID278

SID279

SID280

I_{OUT_MAX_HI}

4

–

Output is 0.5 V

power=mid

power=lo

I_{OUT_MAX_MID}

I_{OUT_MAX_LO}

mA

V_DDA-0.5 V

Output is 0.5 V

2

V_DDA-0.5 V

I_{DD_Int}

Opamp block current Internal Load

power=hi

–

I_{DD_HI_Int}

I_{DD_MED_Int}

G_BW

SID269_I

SID270_I

1500

700

2300

1200

µA

power=med

V_DDA= 2.7 V

Output is 0.25 V to

V_DDA-0.25 V

–

G_{BW_HI_Int}

SID272_I

power=hi

8

MHz

General opamp specs for both internal and external modes

Charge-pump on,

–

V_IN

V_DDA-0.2

SID281

SID282

–0.05

V_DDA= 2.7 V

V

–

V_CM

Charge-pump on, V_DDA= 2.7 V

V_DDA-0.2

-0.05

Document Number: 002-22097 Rev. *E

Page 20 of 45

PSoC 4: PSoC 4100PS Datasheet

Table 8. CTB Opamp Specifications (continued)

Spec ID#

Parameter

V_{OUT_1}

Description

Min

Typ

Max

Unit

Details/Conditions

V

_DD= 2.7 V

V_DDA

-0.5

–

SID283

power=hi, Iload=10 mA

0.5

_DDA= 2.7 V

V_DDA

-0.2

–

V_{OUT_2}

V_{OUT_3}

V_{OUT_4}

V_{OS_TR}

SID284

SID285

SID286

SID288

SID288A

SID288B

power=hi, Iload=1 mA

power=med, Iload=1 mA

power=lo, Iload=0.1 mA

Offset voltage, trimmed

0.2

–1.0

–

V

V_DDA

-0.2

V_DDA

-0.2

High mode, input 0 V

to V_DDA-0.2 V

1.0

–

0.5

1

Medium mode, input

0 V to V_DDA-0.2 V

mV

Low mode, input 0 V

to V_DDA-0.2 V

–

2

V_{OS_DR_TR}

SID290

Offset voltage drift, trimmed

-10

–

10

–

µV/C High mode

3

SID290A

SID290B

Medium mode

µV/C

10

–

Low mode

Input is 0 V to

V

_DDA-0.2 V, Output is

–

SID291

SID291A

SID292

CMRR

CMRR2

PSRR

DC

70

60

70

80

70

85

0.2 V to V_DDA-0.2 V,

V_DDA≥ 2.7 V

Input is 0 V to

V_DDA-0.2 V, Output is

dB

DC

0.2 V to V_DDA-0.2 V.

1.71 V  V_DDA< 2.7 V

V_DDD= 3.6 V,

high-power mode,

input is 0.2 V to

At 1 kHz, 10-mV ripple

V_DDA-0.2 V

Noise

VN2

Input and output are

at 0.2 V to V_DDA-0.2 V

–

SID294

SID295

SID296

Input-referred, 1 kHz, power=Hi

Input-referred, 10 kHz, power=Hi

Input-referred, 100 kHz, power=Hi

72

28

15

Input and output are

at 0.2 V to V_DDA-0.2 V

nV/

rtHz

VN3

VN4

Input and output are

at 0.2 V to V_DDA-0.2 V

–

Stable up to max. load. Performance

specs at 50 pF.

–

C_LOAD

SID297

SID298

SID299

125

–

pF

V/µs

µs

C_LOAD= 50 pF, Power = High, V_DDA

= 2.7 V

SLEW_RATE

T_OP_WAKE

6

–

From disable to enable, no external

RC dominating

25

Document Number: 002-22097 Rev. *E

Page 21 of 45

PSoC 4: PSoC 4100PS Datasheet

Table 8. CTB Opamp Specifications (continued)

Spec ID#

Parameter

OL_GAIN

Description

Open Loop Gain

Min

Typ

Max

Unit

Details/Conditions

–

SID299A

90

–

dB

Comparator mode; 50-mV drive, T_rise=T_fall(approx)

–

150

COMP_MODE

T_PD1

Input is 0.2 V to

V_DDA-0.2 V

175

–

SID300

SID301

Response time; power=hi

Input is 0.2 V to

–

T_PD2

Response time; power=med

500

ns

V_DDA-0.2 V

Input is 0.2 V to

–

T_PD3

SID302

SID303

SID304

Response time; power=lo

Hysteresis

2500

V_DDA-0.2 V

–

V_{HYST_OP}

WUP_CTB

10

–

mV

µs

–

Wake-up time from Enabled to

Usable

25

Opamp Deep

Sleep Mode

Mode 2 is lowest current range. Mode 1 has higher GBW.

–

I_{DD_HI_M1}

SID_DS_1

SID_DS_2

SID_DS_3

SID_DS_4

SID_DS_5

SID_DS_6

Mode 1, High current

Mode 1, Medium current

Mode 1, Low current

Mode 2, High current

Mode 2, Medium current

Mode 2, Low current

1400

700

200

120

60

–

I_{DD_MED_M1}

I_{DD_LOW_M1}

I_{DD_HI_M2}

µA

I_{DD_MED_M2}

I_{DD_LOW_M2}

15

20-pF load, no DC

load

0.2 V to V_DDA-0.2 V

–

G_{BW_HI_M1}

SID_DS_7

SID_DS_8

SID_DS_9

SID_DS_10

SID_DS_11

SID_DS_12

Mode 1, High current

Mode 1, Medium current

Mode 1, Low current

Mode 2, High current

Mode 2, Medium current

Mode 2, Low current

4

20-pF load, no DC

load 0.2 V to

G_{BW_MED_M1}

G_{BW_LOW_M1}

G_{BW_HI_M2}

2

V_DDA-0.2 V

20-pF load, no DC

load 0.2 V to

0.5

0.2

0.1

V_DDA-0.2 V

MHz

20-pF load, no DC

load 0.2 V to

V_DDA-0.2 V

20-pF load, no DC

load 0.2 V to

G_{BW_MED_M2}

V_DDAA-0.2 V

20-pF load, no DC

load 0.2 V to

G_{BW_Low_M2}

V_DDA-0.2 V

Document Number: 002-22097 Rev. *E

Page 22 of 45

PSoC 4: PSoC 4100PS Datasheet

Table 8. CTB Opamp Specifications (continued)

Spec ID#

Parameter

Description

Mode 1, High current

Min

Typ

Max

Unit

Details/Conditions

With trim 25 °C, 0.2 V

to V_DDA-1.5 V

–

V_{OS_HI_M1}

SID_DS_13

5

With trim 25 °C, 0.2 V

to V_DDA-1.5 V

–

V_{OS_MED_M1}

V_{OS_LOW_M1}

V_{OS_HI_M2}

SID_DS_14

SID_DS_15

SID_DS_16

SID_DS_17

SID_DS_18

SID_DS_19

SID_DS_20

SID_DS_21

Mode 1, Medium current

Mode 1, Low current

Mode 2, High current

Mode 2, Medium current

Mode 2, Low current

Mode 1, High current

Mode 1, Medium current

Mode 1, Low current

5

With trim 25 °C, 0.2 V

to V_DDA-1.5 V

mV

With trim 25 °C, 0.2V

to V_DDA-1.5 V

5

With trim 25 °C, 0.2 V

to V_DDA-1.5 V

V_{OS_MED_M2}

V_{OS_LOW_M2}

I_{OUT_HI_M1}

5

With trim 25 °C, 0.2 V

to V_DDA-1.5 V

5

Output is 0.5 V to

10

4

V_DDA-0.5 V

Output is 0.5 V to

I_{OUT_MED_M1}

I_{OUT_LOW_M1}

V_DDA-0.5 V

Output is 0.5 V to

mA

V_DDA-0.5 V

–

I_{OUT_HI_M2}

I_{OU_MED_M2}

I_{OU_LOW_M2}

SID_DS_22

SID_DS_23

SID_DS_24

Mode 2, High current

Mode 2, Medium current

Mode 2, Low current

1

–

0.5

Table 9. PGA Specifications

Spec ID#

Parameter

Description

Min

Typ

Max

Unit

Details/Conditions

PGA Gain

Values

–

Gain Values are 2,4,16, and 32.

Gain Error for Low range; Gain = 2

2

–

32

–

1

–

1

–

3

–

%

–

SID_PGA_1 PGA_ERR_1 Gain Error for Medium range; Gain = 2

Gain Error for High range; Gain = 2

1.5

–

Gain Error for Low range; Gain = 4

SID_PGA_2 PGA_ERR_2 Gain Error for Medium range; Gain = 4

Gain Error for High range; Gain = 4

1.5

–

Gain Error for Low range; Gain = 16

Gain Error for Medium range;

SID_PGA_3 PGA_ERR_3

–

3

–

%

Gain = 16

Gain Error for High range; Gain = 16

Gain Error for Low range; Gain = 32

–

3

5

–

%

–

Gain Error for Medium range;

SID_PGA_4 PGA_ERR_4

–

5

–

%

Gain = 32

Gain Error for High range; Gain = 32

–

Document Number: 002-22097 Rev. *E

Page 23 of 45

PSoC 4: PSoC 4100PS Datasheet

Table 10. Voltage DAC Specifications

(VDAC specs are valid from –20 to 85 °C)

Spec ID#

13-bit DAC

SID_DAC_1

SID_DAC_2

Parameter

Description

Min

Typ

Max

Unit

LSB

V

Details/Conditions

INL_VDAC1

Integral non linearity (INL)

–6

–1

–

5

4

–

DNL_VDAC1 Differential non linearity (DNL)

Valid output range is 200

LSBs from rails. Full

settling bandwidth to

within 200 mV of rail.

SID_DAC_3

VOUT_VDAC1 Output voltage range

0.2

–

V_DDA-0.2

Zero scale error (output with all

Zero scale is at analog

ground

SID_DAC_4

SID_DAC_5

ZSE_VDAC1

zeroes input)

–

20

–

2

mV

%

V_DDA≥ 2.7 V,

GE_VDAC1

IDD_VDAC1

Full scale error less offset

Block current

0.3

VREF = V_DDA/2

SID_DAC_6

SID_DAC_7

–

1.8

50

–

mA

dB

–

PSRR_VDAC1 Power supply rejection ratio

2.7 V < V_DDA 5.5 V

Wake-up time from Enabled to

SID_DAC_8

WUP_VDAC1

Usable

–

32

72

µs

2.7 V < V_DDA5.5 V

Wake-up time from Enabled to

Usable

SID_DAC_8A WUP_VDAC2

SID_DAC_9 TS_VDAC1

V_DDA 2.7 V

500 ksps operation,

Settling time for DAC

–

2

µs

V_DDA≥ 2.7 V

100 ksps operation,

V_DDA 2.7 V

SID_DAC_9A TS_VDAC2

Settling time for DAC

10

Note

6. Guaranteed by characterization.

Document Number: 002-22097 Rev. *E

Page 24 of 45

PSoC 4: PSoC 4100PS Datasheet

Table 11. Comparator DC Specifications

Spec ID# Parameter

SID84 V_OFFSET1

V_OFFSET2

V_HYST

Description

Min Typ

Max

±10

±4

Unit Details/Conditions

Input offset voltage, Factory trim

Input offset voltage, Custom trim

Hysteresis when enabled

–

SID85

SID86

mV

–

10

35

Input common mode voltage in normal

mode

SID87

V_ICM1

V_ICM2

0

–

V_DDD-0.1

V_DDD

Modes 1 and 2

–

Input common mode voltage in low

power mode

SID247

V

V_DDD≥ 2.2 V for

Temp < 0 °C, V_DDD

≥ 1.8 V for Temp >

0 °C

Input common mode voltage in ultra

low power mode

SID247A

V_ICM3

0

–

V_DDD-1.15

SID88

C_MRR

I_CMP1

I_CMP2

Common mode rejection ratio

Block current, normal mode

Block current, low power mode

50

42

–

V_DDD≥ 2.7V

dB

SID88A

SID89

–

V_DDD≤ 2.7V

400

100

–

SID248

–

µA V_DDD≥ 2.2 V for

Temp < 0 °C, V_DDD

≥ 1.8 V for Temp >

0 °C

SID259

SID90

I_CMP3

Block current in ultra low-power mode

DC Input impedance of comparator

–

28

–

Z_CMP

35

MΩ

–

Table 12. Comparator AC Specifications

Spec ID# Parameter

SID91 TRESP1

Description

Min Typ

Max

Unit Details/Conditions

Response time, normal mode, 50 mV

overdrive

–

38

70

110

All V_DD

ns

–

Response time, low power mode, 50 mV

overdrive

SID258

SID92

TRESP2

TRESP3

200

15

V_DDD≥ 2.2 V for

Response time, ultra-low power mode,

200 mV overdrive

Temp < 0 °C, V_DDD

≥ 1.8 V for Temp >

–

2.3

µs

0 °C

Table 13. Temperature Sensor Specifications

Spec ID#

SID93

Parameter

Description

Min

Typ

Max

Unit

Details/Conditions

TSENSACC

Temperature sensor accuracy

–5

±1

5

°C

–40 to +85 °C

Document Number: 002-22097 Rev. *E

Page 25 of 45

PSoC 4: PSoC 4100PS Datasheet

Table 14. SAR Specifications

Spec ID# Parameter

SAR ADC DC Specifications

Description

Min Typ

Max

Unit Details/Conditions

SID94

SID95

SID96

SID97

A_RES

Resolution

–

12

8

bits

–

A_CHNLS_S

A-CHNKS_D

A-MONO

Number of channels - single ended

Number of channels - differential

Monotonicity

8 full speed.

4

–

Yes.

With external

reference.

SID98

SID99

A_GAINERR

A_OFFSET

Gain error

–

±0.1

2

%

Measured with 1-V

reference

Input offset voltage

mV

SID100

SID101

SID102

SID103

SID104

SID260

A_ISAR

Current consumption

–

V_SS

–

1

mA

V

–

A_VINS

Input voltage range - single ended

Input voltage range - differential[

Input resistance

V_DDA

2.2

A_VIND

V

A_INRES

A_INCAP

VREFSAR

KΩ

pF

V

Input capacitance

–

10

Trimmed internal reference to SAR

–

TBD

SAR ADC AC Specifications

SID106

SID107

SID108

A_PSRR

A_CMRR

A_SAMP

Power supply rejection ratio

Common mode rejection ratio

Sample rate

70

66

–

1

dB

–

Measured at 1 V

–

Msps

Signal-to-noise and distortion ratio

(SINAD)

SID109

SID110

SID111

A_SNR

A_BW

A_INL

65

–

dB

F

–

_IN= 10 kHz

Input bandwidth without aliasing

A_samp/2 kHz

Integral non linearity. V_DD= 1.71 to 5.5,

1 Msps

–1.7

2

LSB

V

_REF= 1 to V_DD

_REF= 1.71 to V_DD

_REF= 1 to V_DD

_REF= 1.71 to V_DD

_REF= 1 to V_DD

Integral non linearity. V_DDD= 1.71 to 3.6,

1 Msps

SID111A

SID111B

SID112

A_INL

A_DNL

–1.5

–1

–

1.7

2.2

2

Integral non linearity. V_DD= 1.71 to 5.5,

500 ksps

Differential non linearity. V_DD= 1.71 to

5.5, 1 Msps

Differential non linearity. V_DD= 1.71 to

3.6, 1 Msps

SID112A

–1

Differential non linearity. V_DD= 1.71 to

5.5, 500 ksps

–

SID112B

SID113

SID261

A_DNL

–1

–

2.2

–65

100

LSB

dB

A_THD

Total harmonic distortion

F_IN= 10 kHz

SAR operating speed without external

ref. bypass

–

FSARINTREF

ksps 12-bit resolution

Document Number: 002-22097 Rev. *E

Page 26 of 45

PSoC 4: PSoC 4100PS Datasheet

Table 15. CapSense and IDAC Specifications^[7]

Spec ID#

Parameter

Description

Min

Typ

Max

Unit Details/Conditions

_DD> 2 V (with

mV ripple), 25 °C T_A,

V

Max allowed ripple on power supply,

DC to 10 MHz

SYS.PER#3

VDD_RIPPLE

–

±50

Sensitivity = 0.1pF

V_DD> 1.75 V (with

ripple), 25 °C T_A,

mV Parasitic Capaci-

tance (CP) < 20 pF,

Max allowed ripple on power supply,

DC to 10 MHz

SYS.PER#16 VDD_RIPPLE_1.8

–

±25

Sensitivity ≥ 0.4 pF

SID.CSD.BLK ICSD

SID.CSD#15 VREF

Maximum block current

4000

µA

V

–

Voltage reference for CSD and

Comparator

V_DDA

0.6

-

V

_DDA- 0.6 or 4.4,

0.6

1.2

whichever is lower

ExternalVoltagereferenceforCSDand

Comparator

V_DDA

0.6

-

V_DDA- 0.6 or 4.4,

whichever is lower

SID.CSD#15A VREF_EXT

V

SID.CSD#16 IDAC1IDD

SID.CSD#17 IDAC2IDD

IDAC1 (7 bits) block current

IDAC2 (7 bits) block current

–

1750

µA

–

1.8 V ±5% or 1.8 V

to 5.5 V

SID308

VCSD

Voltage range of operation

1.71

0.6

–

5.5

V

V_DDA

0.6

–

V_DDA–0.6 or 4.4,

whichever is lower

SID308A

VCOMPIDAC

Voltage compliance range of IDAC

SID309

SID310

SID311

SID312

IDAC1DNL

IDAC1INL

IDAC2DNL

IDAC2INL

DNL

INL

–1

–3

–1

–3

–

1

3

LSB

–

DNL

INL

1.0

3

Capacitance range

of 5 to 200 pF,

Ratio 0.1 pFsensitivity.All

Ratio of counts of finger to noise.

Guaranteed by characterization

SID313

SNR

5.0

–

use cases. V_DDA

>

2 V.

Maximum Source current of 7-bit IDAC

in low range

SID314

IDAC7_SRC1

IDAC7_SRC2

IDAC7_SRC3

IDAC7_SRC4

IDAC7_SRC5

IDAC7_SRC6

IDAC7_SINK_1

IDAC7_SINK_2

IDAC7_SINK_3

4.2

34

5.4

41

µA LSB = 37.5 nA typ.

µA LSB = 300 nA typ.

µA LSB = 2.4 µA typ.

Maximum Source current of 7-bit IDAC

in medium range

SID314A

SID314B

SID314C

SID314D

SID314E

SID315

Maximum Source current of 7-bit IDAC

in high range

275

8

330

10.5

82

Maximum Source current of 7-bit IDAC

in low range, 2X mode

LSB = 37.5 nA typ.

µA

2X output stage

Maximum Source current of 7-bit IDAC

in medium range, 2X mode

LSB = 300 nA typ.

µA

69

2X output stage

Maximum Source current of 7-bit IDAC

in high range, 2X mode

LSB= 2.4 µAtyp.2X

output stage

540

4.2

34

660

5.7

44

µA

Maximum Sink current of 7-bit IDAC in

low range

µA LSB = 37.5 nA typ.

µA LSB = 300 nA typ.

µA LSB = 2.4 µA typ.

Maximum Sink current of 7-bit IDAC in

medium range

SID315A

Maximum Sink current of 7-bit IDAC in

high range

SID315B

260

340

Note

7. For optimal CapSense performance, Ports 0, 4, and 5 must be used for large DC loads.

Document Number: 002-22097 Rev. *E

Page 27 of 45

PSoC 4: PSoC 4100PS Datasheet

Table 15. CapSense and IDAC Specifications^[7](continued)

Spec ID#

SID315C

Parameter

Description

Min

Typ

Max

Unit Details/Conditions

Maximum Sink current of 7-bit IDAC in

low range, 2X mode

LSB = 37.5 nA typ.

µA

IDAC7_SINK_4

8

11.5

2X output stage

Maximum Sink current of 7-bit IDAC in

medium range, 2X mode

LSB = 300 nA typ.

µA

SID315D

SID315E

SID315F

SID315G

SID315H

SID315J

SID315K

SID315L

SID320

IDAC7_SINK_5

IDAC7_SINK_6

IDAC8_SRC_1

IDAC8_SRC_2

IDAC8_SRC_3

IDAC8_SINK_1

IDAC8_SINK_2

IDAC8_SINK_3

IDACOFFSET1

68

540

8.4

68

86

700

10.8

82

2X output stage

Maximum Sink current of 7-bit IDAC in

high range, 2X mode

LSB= 2.4 µAtyp.2X

output stage

µA

Maximum Source current of 8-bit IDAC

in low range

µA LSB = 37.5 nA typ.

µA LSB = 300 nA typ.

µA LSB = 2.4 µA typ.

µA LSB = 37.5 nA typ.

µA LSB = 300 nA typ.

µA LSB = 2.4 µA typ.

Maximum Source current of 8-bit IDAC

in medium range

Maximum Source current of 8-bit IDAC

in high range

550

8.4

68

680

11.4

88

Maximum Sink current of 8-bit IDAC in

low range

Maximum Sink current of 8-bit IDAC in

medium range

Maximum Sink current of 8-bit IDAC in

high range

540

–

670

1

All zeroes input; Medium and High

range

Polarity set by

LSB

–

Source or Sink

Polarity set by

LSB

SID320A

SID321

SID322

IDACOFFSET2

IDACGAIN

All zeroes input; Low range

–

2

Source or Sink

Full-scale error less offset

±20

9.2

%

Mismatch between IDAC1 and IDAC2

in Low mode

IDACMISMATCH1

LSB LSB = 37.5 nA typ.

Mismatch between IDAC1 and IDAC2

in Medium mode

SID322A

SID322B

SID323

SID324

SID325

IDACMISMATCH2

IDACMISMATCH3

IDACSET8

–

6

6.8

10

–

LSB LSB = 300 nA typ.

LSB LSB = 2.4 µA typ.

Mismatch between IDAC1 and IDAC2

in High mode

Full-scaletransition.

µs

Settling time to 0.5 LSB for 8-bit IDAC

Settling time to 0.5 LSB for 7-bit IDAC

External modulator capacitor.

–

No external load.

Full-scaletransition.

µs

IDACSET7

–

No external load.

5-V rating, X7R or

NP0 cap.

CMOD

2.2

nF

Document Number: 002-22097 Rev. *E

Page 28 of 45

PSoC 4: PSoC 4100PS Datasheet

Table 16. 10-bit CapSense ADC Specifications

Spec ID#

Parameter

Description

Min Typ

Max

Unit

Details/Conditions

–

SIDA94

A_RES

Resolution

10

bits 8 full speed.

SID95

A_CHNLS_S Number of channels - single-ended

A-MONO Monotonicity

A_GAINERR Gain error

16

–

Diff inputs use neighboring I/O

Yes Yes

SIDA97

SIDA98

TBD

%

With external reference.

–

SIDA99

A_OFFSET

Input offset voltage

mV Measured with 1-V reference

–

SIDA100

SIDA101

A_ISAR

A_VINS

Current consumption

TBD

mA

V

V_SSA

V_DDA

Input voltage range - single-ended

–

2.2

20

–

SIDA103

SIDA104

SIDA106

SIDA107

A_INRES

A_INCAP

A_PSRR

A_TACQ

Input resistance

–

KΩ

pF

dB

µs

Input capacitance

–

Power supply rejection ratio

Sample acquisition time

TBD

–

1

–

SIDA108

A_CONV8

Conversion time for 8-bit resolution at

conversion rate = Fhclk/(2^(N+2)).

Clock frequency = 48 MHz.

–

21.3

Does not include acquisition

time. Equivalent to 44.8 ksps

including acquisition time.

SIDA108A A_CONV10

Conversion time for 10-bit resolution

at conversion rate = Fhclk/(2^(N+2)).

Clock frequency = 48 MHz.

–

85.3

µs

Does not include acquisition

time. Equivalent to 11.6 ksps

including acquisition time.

–

Signal-to-noise and distortion ratio

(SINAD)

–

22.4

2

SIDA109

SIDA110

SIDA111

A_SND

A_BW

A_INL

TBD

–

dB

Input bandwidth without aliasing

kHz 8-bit resolution

Integral non linearity. V_DD= 1.71 to

5.5, 1 ksps

–

V

_REF= 2.4 V or greater

LSB

–

Differential non linearity. V_DD= 1.71

to 5.5, 1 ksps

–

SIDA112

A_DNL

1

Document Number: 002-22097 Rev. *E

Page 29 of 45

PSoC 4: PSoC 4100PS Datasheet

Digital Peripherals

Timer Counter Pulse-Width Modulator (TCPWM)

Table 17. TCPWM Specifications

Spec ID#

Parameter

Description

Min

Typ

Max

Unit

Details/Conditions

SID.TCPWM.1 ITCPWM1

SID.TCPWM.2 ITCPWM2

SID.TCPWM.2A ITCPWM3

Block current consumption at 3 MHz

–

45

All modes (TCPWM)

Block current consumption at 12 MHz

Block current consumption at 48 MHz

–

155

650

μA All modes (TCPWM)

All modes (TCPWM)

Fc max = CLK_SYS

MHz

TCPWM_FREQ

TPWM_ENEXT

SID.TCPWM.3

SID.TCPWM.4

Operating frequency

–

Fc

–

Maximum = 48 MHz

For all trigger events^[8]

Input trigger pulse width

2/Fc

Minimum possible

width of Overflow,

Underflow, and CC

(Counter equals

Compare value)

outputs

TPWM_EXT

SID.TCPWM.5

Output trigger pulse widths

2/Fc

–

ns

Minimum time

between successive

counts

TC_RES

PWM_RES

Q_RES

SID.TCPWM.5A

SID.TCPWM.5B

SID.TCPWM.5C

Resolution of counter

PWM resolution

1/Fc

–

Minimum pulse width

of PWM Output

Minimum pulse width

between Quadrature

phase inputs

Quadrature inputs resolution

I²C

Table 18. Fixed I²C DC Specifications^[9]

Spec ID Parameter

SID149 I_I2C1

Description

Min

Typ

Max

50

Unit

Details/Conditions

Block current consumption at 100 kHz

Block current consumption at 400 kHz

Block current consumption at 1 Mbps

I²C enabled in Deep Sleep mode

–

SID150

SID151

SID152

I_I2C2

I_I2C3

I_I2C4

135

310

1.4

µA

Table 19. Fixed I²C AC Specifications^[9]

Spec ID# Parameter

SID153 F_I2C1

Description

Min

Typ

Max

Unit

Details/Conditions

Bit rate

–

1

Msps –

Table 20. SPI DC Specifications^[10]

Spec ID# Parameter

SID163 ISPI1

Description

Min

Typ

Max

Unit

Block current consumption at

1 Mbits/sec

–

360

Block current consumption at

4 Mbits/sec

–

SID164

ISPI2

ISPI3

–

560

600

µA

Block current consumption at

8 Mbits/sec

–

SID165

Note

8. Trigger events can be Stop, Start, Reload, Count, Capture, or Kill depending on which mode of operation is selected.

9. Guaranteed by characterization.

Document Number: 002-22097 Rev. *E

Page 30 of 45

PSoC 4: PSoC 4100PS Datasheet

Table 21. SPI AC Specifications^[10]

Spec ID#

Parameter

FSPI

Description

Min

Typ

Max

Unit

Details/Conditions

SPIOperatingfrequency(Master;6X

Oversampling)

SID166

–

8

MHz SID166

Fixed SPI Master Mode AC Specifications

SID167

SID168

TDMO

TDSI

MOSI Valid after SClock driving edge

–

15

–

MISO Valid before SClock capturing

edge

Full clock, late MISO

ns sampling

20

Referred to Slave capturing

edge

SID169

THMO

Previous MOSI data hold time

0

–

Fixed SPI Slave Mode AC Specifications

MOSI Valid before Sclock Capturing

edge

–

SID170

SID171

TDMI

40

–

42 +

3*Tscb

TDSO

MISO Valid after Sclock driving edge

T

_{scb =}SCB clock

ns

MISO Valid after Sclock driving edge

in Ext. Clk mode

–

SID171A TDSO_EXT

SID172 THSO

–

0

–

48

–

Previous MISO data hold time

–

Table 22. UART DC Specifications^[10]

Spec ID# Parameter

Description

Min

Typ

Max

Unit

Details/Conditions

Block current consumption at

100 Kbits/sec

–

SID160

SID161

I_UART1

I_UART2

–

55

µA

Block current consumption at

1000 Kbits/sec

–

312

µA

Table 23. UART AC Specifications^[10]

Spec ID#

Parameter

F_UART

Description

Min

Typ

Max

Unit

Details/Conditions

SID162

Bit rate

–

1

Mbps –

Table 24. LCD Direct Drive DC Specifications^[10]

Spec ID# Parameter

Description

Min

Typ

Max

Unit

Details/Conditions

Operating current in low power

mode

SID154

I_LCDLOW

5

–

µA 16  4 small segment disp. at Hz

–

LCD capacitance per

segment/common driver

–

SID155

SID156

SID157

C_LCDCAP

LCD_OFFSET

I_LCDOP1

500

20

2

5000

pF

–

Long-term segment offset

–

mV

–

LCD system operating current

Vbias = 5 V

32  4 segments. 50 Hz. 25 °C

–

mA

LCD system operating current

Vbias = 3.3 V

32  4 segments. 50 Hz. 25 °C

4 segments. 50 Hz. 25 °C.

SID158

I_LCDOP2

2

–

Note

10. Guaranteed by characterization.

Document Number: 002-22097 Rev. *E

Page 31 of 45

PSoC 4: PSoC 4100PS Datasheet

Table 25. LCD Direct Drive AC Specifications^[10]

Spec ID#

SID159

Parameter

F_LCD

Description

Min

Typ

Max

Unit

Details/Conditions

LCD frame rate

10

50

150

Hz

–

Memory

Table 26. Flash DC Specifications

Spec ID#

Parameter

V_PE

Description

Min

Typ

Max

Unit

SID173

Erase and program voltage

1.71

–

5.5

V

–

Table 27. Flash AC Specifications

Spec ID#

Parameter

Description

Min

Typ

Max

Unit

Row (block) write time (erase and

program)

[11]

SID174

T_ROWWRITE

–

20

Row (block) = 64 bytes

[11]

SID175

SID176

SID178

SID180^[12]T_DEVPROG

SID181^[12]F_END

T_ROWERASE

Row erase time

–

13

7

–

ms

[11]

T_ROWPROGRAM

Row program time after erase

Bulk erase time (16 KB)

Total device program time

Flash endurance

–

[11]

T_BULKERASE

15

7.5

–

[11]

–

Seconds –

100 K

Cycles

–

Flash retention. T_A 55 °C, 100 K

SID182^[12]F_RET

20

10

–

P/E cycles

Flash retention. T_A 85 °C, 10 K

P/E cycles

SID182A^[12]

–

Years

Flash retention. T_A 105 °C, 10 K

Guaranteed by

characterization

SID182B^[12]F_RETQ

P/E cycles;  three years at T_A



10

–

85 °C

CPU execution from

Flash

SID256

SID257

TWS48

TWS24

Number of Wait states at 48 MHz

Number of Wait states at 24 MHz

2

1

–

CPU execution from

Flash

Notes

11. It can take as much as 20 milliseconds to write to Flash. During this time the device should not be Reset, or Flash operations will be interrupted and cannot be relied

on to have completed. Reset sources include the XRES pin, software resets, CPU lockup states and privilege violations, improper power supply levels, and watchdogs.

Make certain that these are not inadvertently activated.

12. Guaranteed by characterization.

Document Number: 002-22097 Rev. *E

Page 32 of 45

PSoC 4: PSoC 4100PS Datasheet

System Resources

Power-on Reset (POR)

Table 28. Power On Reset (PRES)

Spec ID#

Parameter

Description

Min

Typ

Max

Unit

Details/Conditions

At power-up and

power-down.

SID.CLK#6 SR_POWER_UP Power supply slew rate

1

–

67

V/ms

SID185^[13]V_RISEIPOR

SID186^[13]V_FALLIPOR

Rising trip voltage

Falling trip voltage

0.80

0.70

–

1.5

1.4

–

V

Table 29. Brown-out Detect (BOD) for V_CCD

Spec ID

Parameter

Description

Min

1.48

1.1

Typ

–

Max

1.62

1.5

Unit

Details/Conditions

BOD trip voltage in active and sleep

modes

SID190^[13]V_FALLPPOR

SID192^[13]V_FALLDPSLP

–

V

BOD trip voltage in Deep Sleep

–

SWD Interface

Table 30. SWD Interface Specifications

Spec ID#

Parameter

Description

3.3 V  V_DD 5.5 V

Min

Typ

Max

Unit

Details/Conditions

SWDCLK ≤ 1/3 CPU

clock frequency

SID213

F_SWDCLK1

–

14

MHz

SWDCLK ≤ 1/3 CPU

clock frequency

SID214

F_SWDCLK2

1.71 V  V_DD 3.3 V

–

7

SID215^[13]T_SWDI_SETUP T = 1/f SWDCLK

SID216^[13]T_SWDI_HOLD T = 1/f SWDCLK

SID217^[13]T_SWDO_VALID T = 1/f SWDCLK

SID217A^[13]T_SWDO_HOLD T = 1/f SWDCLK

0.25*T

–

0.25*T

ns

–

1

0.5*T

–

Internal Main Oscillator

Table 31. IMO DC Specifications

(Guaranteed by Design)

Spec ID#

SID218

Parameter

I_IMO1

I_IMO2

Description

Min

–

Typ

–

Max

250

180

Unit

µA

Details/Conditions

IMO operating current at 48 MHz

IMO operating current at 24 MHz

–

SID219

–

µA

Table 32. IMO AC Specifications

Spec ID

Parameter

F_IMOTOL1

Description

Min

Typ

Max

Unit

Details/Conditions

Frequency range from 24 to

48 MHz (4-MHz increments)

2 V  V_DD 5.5 V, and

–25 °C  T_A 85 °C

SID223

–2

–

+2

%

SID226

SID228

T_STARTIMO

IMO startup time

–

7

–

µs

ps

–

T_JITRMSIMO2

RMS jitter at 24 MHz

145

Note

13. Guaranteed by characterization.

Document Number: 002-22097 Rev. *E

Page 33 of 45

PSoC 4: PSoC 4100PS Datasheet

Internal Low-Speed Oscillator

Table 33. ILO DC Specifications

(Guaranteed by Design)

Spec ID

Parameter

Description

Min

Typ

Max

Unit

Details/Conditions

SID231^[14]I_ILO1

ILO operating current

–

0.3

1.05

µA

–

Table 34. ILO AC Specifications

Spec ID Parameter

Description

ILO startup time

Min

–

Typ

–

Max

2

Unit

ms

Details/Conditions

SID234^[14]T_STARTILO1

SID236^[14]T_ILODUTY

–

ILO duty cycle

40

20

50

40

60

80

%

SID237

F_ILOTRIM1

ILO frequency range

kHz

Table 35. Watch Crystal Oscillator (WCO) Specifications

Spec ID

SID398

SID399

SID400

SID401

SID402

SID403

SID404

SID405

Parameter

FWCO

Description

Crystal Frequency

Min

–

Typ

Max

Unit

Details/Conditions

32.768

–

250

–

kHz

–

FTOL

ESR

PD

Frequency tolerance

–

50

–

ppm With 20-ppm crystal

Equivalent series resistance

Drive Level

–

kΩ

µW

ms

pF

–

1

TSTART

CL

Startup time

–

500

12.5

–

Crystal Load Capacitance

Crystal Shunt Capacitance

Operating Current (high power mode)

6

–

C0

–

1.35

–

pF

IWCO1

–

8

µA

Table 36. External Clock Specifications

Spec ID Parameter

Description

Min

0

Typ

–

Max

48

Unit

MHz

%

Details/Conditions

SID305^[14]ExtClkFreq

SID306^[14]ExtClkDuty

External clock input frequency

Duty cycle; measured at V_DD/2

–

45

–

55

–

Table 37. Block Specs

Spec ID

SID262^[14]T_CLKSWITCH

Parameter

Description

Min

Typ

Max

Unit

Details/Conditions

System clock source switching time

3

–

4

Periods –

Table 38. PRGIO Pass-through Time (Delay in Bypass Mode)

Spec ID

Parameter

Description

Min

Typ

Max

Unit

Max. delay added by PRGIO in bypass

mode

SID252

PRG_BYPASS

–

1.6

ns

–

Note

14. Guaranteed by characterization.

Document Number: 002-22097 Rev. *E

Page 34 of 45

PSoC 4: PSoC 4100PS Datasheet

Ordering Information

Features

Package

806

CY8C4125PVI-PS421 24

✔

32

4

2

4

–

✔

2

8

2

3

8

20

37

38

20

37

38

20

37

38

✔

–

✔

–

ksps

806

ksps

CY8C4125FNI-PS423 24

4125

806

ksps

CY8C4125AZI-PS423 24

–

✔

–

–40 to

85

806

ksps

CY8C4125LQI-PS423 24

CY8C4145PVI-PS421 48

CY8C4145FNI-PS423 48

CY8C4145FNQ-PS423 48

CY8C4145AZI-PS423 48

–

✔

–

1000

ksps

–

✔

–

1000

ksps

–

✔

–

1000

ksps

–40 to

105

–

1000

ksps

–

✔

–

1000

ksps

CY8C4145LQI-PS423 48

4145

–

✔

–

–40 to

85

1000

ksps

CY8C4145PVI-PS431 48

✔

–

1000

ksps

CY8C4145FNI-PS433 48

CY8C4145FNQ-PS433 48

CY8C4145AZI-PS433 48

CY8C4145LQI-PS433 48

✔

–

1000

ksps

–40 to

105

–

1000

ksps

–

✔

–

–40 to

85

1000

ksps

–

✔

Document Number: 002-22097 Rev. *E

Page 35 of 45

PSoC 4: PSoC 4100PS Datasheet

The nomenclature used in the preceding table is based on the following part numbering convention:

Field

CY8C

4

Description

Cypress Prefix

Architecture

Family

Values

Meaning

4

Arm Cortex-M0+ CPU

A

1

4100PS Family

2

24 MHz

B

C

Maximum frequency

4

5

48 MHz

Flash Memory Capacity

32 KB

AZ

LQ

PV

FN

PS

I

TQFP (0.5mm pitch)

QFN

DE

Package Code

SSOP

CSP

S-Series

S

F

Series Designator

Temperature Range

Attributes Code

Industrial

Q

Extended Industrial

Code of feature set in the specific family

XYZ

000-999

The following is an example of a part number:

S

XYZ

Example

CY8C 4 A B C DE F –

Cypress Prefix

Architecture

Family within Architecture

CPU Speed

4 : PSoC 4

1 :4100 Family

4 : 48 MHz

5 : 32KB

Flash Capacity

Package Code

AZ :TQFP

I: Industrial

Temperature Range

Series Designator

Attributes Code

Document Number: 002-22097 Rev. *E

Page 36 of 45

PSoC 4: PSoC 4100PS Datasheet

Packaging

Spec ID#

BID20

Package

48-pin TQFP

48-pin QFN

Description

Package DWG #

51-85135

7 × 7 × 1.4 mm height with 0.5-mm pitch

6 × 6 × 0.6 mm height with 0.4-mm pitch

BID27

001-57280

002-24003

51-85079

BID34

45-ball WLCSP 1.986 × 3.691 × 0.482-mm height with 0.38-mm pitch

28-pin SSOP 5.3 × 10.2 × 0.65-mm pitch

BID34A

Table 39. Package Thermal Characteristics

Parameter

TA

Description

Operating Ambient temperature

Operating junction temperature

Package θ_JA

Package

Min

–40

–

Typ

25

Max

Unit

°C

–

105

125

–

TJ

–

°C

TJA

TJC

TJA

TJC

TJA

TJC

TJA

TJC

48-pin TQFP

48-pin QFN

71

°C/Watt

Package θ_JC

–

34.3

18

–

Package θ_JA

–

Package θ_JC

48-pin QFN

–

4.5

37.2

0.31

60

–

Package θ_JA

45-Ball WLCSP

28-pin SSOP

–

Package θ_JC

–

Package θ_JA

–

Package θ_JC

–

25

–

Table 40. Solder Reflow Peak Temperature

Maximum Peak

Temperature

Package

Maximum Time at Peak Temperature

All

260 °C

30 seconds

Table 41. Package Moisture Sensitivity Level (MSL), IPC/JEDEC J-STD-020

Package

MSL

All

MSL 3

Document Number: 002-22097 Rev. *E

Page 37 of 45

PSoC 4: PSoC 4100PS Datasheet

Package Diagrams

Figure 7. 48-pin TQFP Package Outline

51-85135 *C

Figure 8. 48-Pin QFN Package Outline

001-57280 *E

Document Number: 002-22097 Rev. *E

Page 38 of 45

PSoC 4: PSoC 4100PS Datasheet

Figure 9. 45-Ball WLCSP Dimensions

6

7

5

4

3

2

1

A

B

C

D

E

F

G

H

J

5

NOTES:

DIMENSIONS

NOM

1. ALL DIMENSIONS ARE IN MILLIMETERS.

SYMBOL

MIN

-

MAX

0.482

-

2. SOLDER BALL POSITION DESIGNATION PER JEP95, SECTION 3, SPP-020.

3. "e" REPRESENTS THE SOLDER BALL GRID PITCH.

A

A1

D

-

0.141

-

4. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D" DIRECTION.

SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION.

N IS THE NUMBER OF POPULATED SOLDER BALL POSITIONS FOR MATRIX

SIZE MD X ME.

1.986 BSC

3.691 BSC

1.52 BSC

3.04 BSC

0.263 BSC

0.388 BSC

E

D1

E1

E2

E3

5.

DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A

PLANE PARALLEL TO DATUM C.

6.

"SD" AND "SE" ARE MEASURED WITH RESPECT TO DATUMS A AND B AND

DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW.

WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW,

"SD" OR "SE" = 0.

MD

ME

5

9

WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW,

"SD" = eD/2 AND "SE" = eE/2.

N

45

Øb

eD

0.19

0.22

0.25

A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK,

METALIZED MARK, INDENTATION OR OTHER MEANS.

7.

0.38 BSC

8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED SOLDER

eE

0.38 BSC

0.00 BSC

BALLS.

SD

9. JEDEC SPECIFICATION NO. REF. : N/A.

SE

0.063 BSC

002-24003 **

CYPRESS

Company Confidential

Document Number: 002-22097 Rev. *E

Page 39 of 45

PSoC 4: PSoC 4100PS Datasheet

Figure 10. 28-Pin SSOP Package Outline

51-85079 *G

Document Number: 002-22097 Rev. *E

Page 40 of 45

PSoC 4: PSoC 4100PS Datasheet

Acronyms

Table 42. Acronyms used in this Document (continued)

Table 42. Acronyms used in this Document

Acronym

ESD

Description

electrostatic discharge

Acronym

abus

Description

analog local bus

ETM

FIR

embedded trace macrocell

finite impulse response, see also IIR

flash patch and breakpoint

full-speed

ADC

AG

analog-to-digital converter

analog global

FPB

FS

AHB

AMBA (advanced microcontroller bus

architecture) high-performance bus, anArm data

transfer bus

GPIO

general-purpose input/output, applies to a PSoC

ALU

arithmetic logic unit

HVI

high-voltage interrupt, see also LVI, LVD

integrated circuit

AMUXBUS analog multiplexer bus

IC

API

application programming interface

IDAC

current DAC, see also DAC, VDAC

integrated development environment

APSR

Arm^®

ATM

BW

application program status register

advanced RISC machine, a CPU architecture

automatic thump mode

IDE

I²C, or IIC

Inter-Integrated Circuit, a communications

protocol

bandwidth

IIR

infinite impulse response, see also FIR

internal low-speed oscillator, see also IMO

internal main oscillator, see also ILO

integral nonlinearity, see also DNL

input/output, see also GPIO, DIO, SIO, USBIO

initial power-on reset

CAN

Controller Area Network, a communications

protocol

ILO

IMO

INL

CMRR

CPU

common-mode rejection ratio

central processing unit

I/O

CRC

cyclic redundancy check, an error-checking

protocol

IPOR

IPSR

IRQ

ITM

LCD

LIN

DAC

digital-to-analog converter, see also IDAC,

VDAC

interrupt program status register

interrupt request

DFB

DIO

digital filter block

instrumentation trace macrocell

liquid crystal display

digital input/output, GPIO with only digital

capabilities, no analog. See GPIO.

Local Interconnect Network, a communications

protocol.

DMIPS

DMA

DNL

Dhrystone million instructions per second

direct memory access, see also TD

differential nonlinearity, see also INL

do not use

LR

link register

LUT

lookup table

DNU

DR

LVD

low-voltage detect, see also LVI

low-voltage interrupt, see also HVI

low-voltage transistor-transistor logic

multiply-accumulate

port write data registers

LVI

DSI

digital system interconnect

data watchpoint and trace

error correcting code

LVTTL

MAC

MCU

MISO

NC

DWT

ECC

microcontroller unit

ECO

EEPROM

external crystal oscillator

master-in slave-out

electrically erasable programmable read-only

memory

no connect

NMI

nonmaskable interrupt

non-return-to-zero

EMI

electromagnetic interference

external memory interface

end of conversion

NRZ

NVIC

NVL

opamp

EMIF

EOC

EOF

EPSR

nested vectored interrupt controller

nonvolatile latch, see also WOL

operational amplifier

end of frame

execution program status register

Document Number: 002-22097 Rev. *E

Page 41 of 45

PSoC 4: PSoC 4100PS Datasheet

Table 42. Acronyms used in this Document (continued)

Acronym

PAL

Description

programmable array logic, see also PLD

program counter

Acronym

SWD

Description

serial wire debug, a test protocol

single-wire viewer

PC

SWV

TD

PCB

PGA

PHUB

PHY

PICU

PLA

printed circuit board

transaction descriptor, see also DMA

total harmonic distortion

transimpedance amplifier

technical reference manual

transistor-transistor logic

transmit

programmable gain amplifier

peripheral hub

THD

TIA

physical layer

TRM

TTL

TX

port interrupt control unit

programmable logic array

programmable logic device, see also PAL

phase-locked loop

PLD

UART

UniversalAsynchronous Transmitter Receiver, a

communications protocol

PLL

UDB

universal digital block

Universal Serial Bus

PMDD

POR

PRES

PRS

PS

package material declaration data sheet

power-on reset

USB

USBIO

USB input/output, PSoC pins used to connect to

a USB port

precise power-on reset

pseudo random sequence

port read data register

VDAC

WDT

voltage DAC, see also DAC, IDAC

watchdog timer

PSoC^®

PSRR

PWM

RAM

RISC

RMS

RTC

RTL

Programmable System-on-Chip™

power supply rejection ratio

pulse-width modulator

WOL

write once latch, see also NVL

watchdog timer reset

external reset I/O pin

crystal

WRES

XRES

XTAL

random-access memory

reduced-instruction-set computing

root-mean-square

real-time clock

register transfer language

remote transmission request

receive

RTR

RX

SAR

SC/CT

SCL

successive approximation register

switched capacitor/continuous time

I²C serial clock

SDA

S/H

I²C serial data

sample and hold

SINAD

SIO

signal to noise and distortion ratio

special input/output, GPIO with advanced

features. See GPIO.

SOC

SOF

SPI

start of conversion

start of frame

Serial Peripheral Interface, a communications

protocol

SR

slew rate

SRAM

SRES

static random access memory

software reset

Document Number: 002-22097 Rev. *E

Page 42 of 45

PSoC 4: PSoC 4100PS Datasheet

Document Conventions

Units of Measure

Table 43. Units of Measure

Symbol

°C

Unit of Measure

degrees Celsius

decibel

dB

fF

femto farad

hertz

Hz

KB

kbps

Khr

kHz

k

1024 bytes

kilobits per second

kilohour

kilohertz

kilo ohm

ksps

LSB

Mbps

MHz

M

Msps

µA

kilosamples per second

least significant bit

megabits per second

megahertz

mega-ohm

megasamples per second

microampere

microfarad

µF

µH

microhenry

microsecond

microvolt

µs

µV

µW

mA

ms

mV

nA

microwatt

milliampere

millisecond

millivolt

nanoampere

nanosecond

nanovolt

ns

nV



ohm

pF

picofarad

ppm

ps

parts per million

picosecond

second

s

sps

sqrtHz

V

samples per second

square root of hertz

volt

Document Number: 002-22097 Rev. *E

Page 43 of 45

PSoC 4: PSoC 4100PS Datasheet

Revision History

Description Title: PSoC 4: PSoC 4100PS Datasheet Programmable System-on-Chip (PSoC)

Document Number: 002-22097

Submission

Revision

ECN

Description of Change

Date

**

6049408

6155846

6164274

6318827

01/30/2018 New spec

Updated number of VDACs to 2.

Updated Voltage DAC Specifications.

05/03/2018 Corrected typo in Ordering Information.

Updated Table 2, Table 6, Table 8, Table 10, Table 27, and Table 36.

*A

*B

*C

04/27/2018

09/25/2018

Updated 45-ball WLCSP package drawing.

Updated Device Level Specifications and Ordering Information.

12/06/2019 Updated Table 27 and Table 39.

Updated Sales page and Copyright information.

*D

*E

6740728

7047124

Updated Conditions for SR_POWER_UP in Table 28.

12/17/2020 Updated Figure 10 (spec 51-85079 *F to *G) in Packaging.

Updated Sales, Solutions, and Legal Information.

Document Number: 002-22097 Rev. *E

Page 44 of 45

PSoC 4: PSoC 4100PS Datasheet

Sales, Solutions, and Legal Information

Worldwide Sales and Design Support

Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office

closest to you, visit us at Cypress Locations.

®

Products

PSoC Solutions

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Automotive

Cypress Developer Community

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Training | Components

Internet of Things

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Technical Support

cypress.com/memory

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cypress.com/support

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cypress.com/psoc

cypress.com/pmic

cypress.com/touch

cypress.com/usb

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USB Controllers

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cypress.com/wireless

firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries worldwide. Cypress

reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other intellectual property

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Software is prohibited.

TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE

OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. No computing

device can be absolutely secure. Therefore, despite security measures implemented in Cypress hardware or software products, Cypress shall have no liability arising out of any security breach, such

as unauthorized access to or use of a Cypress product. CYPRESS DOES NOT REPRESENT, WARRANT, OR GUARANTEE THAT CYPRESS PRODUCTS, OR SYSTEMS CREATED USING

CYPRESS PRODUCTS, WILLBE FREE FROM CORRUPTION,ATTACK, VIRUSES, INTERFERENCE, HACKING, DATALOSS OR THEFT, OR OTHER SECURITY INTRUSION (collectively, "Security

Breach"). Cypress disclaims any liability relating to any Security Breach, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from any Security Breach. In

addition, the products described in these materials may contain design defects or errors known as errata which may cause the product to deviate from published specifications. To the extent permitted

by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any product or

circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is the

responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. "High-Risk Device"

means any device or system whose failure could cause personal injury, death, or property damage. Examples of High-Risk Devices are weapons, nuclear installations, surgical implants, and other

medical devices. "Critical Component" means any component of a High-Risk Device whose failure to perform can be reasonably expected to cause, directly or indirectly, the failure of the High-Risk

Device, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from any use of

a Cypress product as a Critical Component in a High-Risk Device. You shall indemnify and hold Cypress, its directors, officers, employees, agents, affiliates, distributors, and assigns harmless from

and against all claims, costs, damages, and expenses, arising out of any claim, including claims for product liability, personal injury or death, or property damage arising from any use of a Cypress

product as a Critical Component in a High-Risk Device. Cypress products are not intended or authorized for use as a Critical Component in any High-Risk Device except to the limited extent that (i)

Cypress's published data sheet for the product explicitly states Cypress has qualified the product for use in a specific High-Risk Device, or (ii) Cypress has given you advance written authorization to

use the product as a Critical Component in the specific High-Risk Device and you have signed a separate indemnification agreement.

Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in

the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.

Document Number: 002-22097 Rev. *E

Revised December 17, 2020

Page 45 of 45


型号：	CY8C4145LQI-PS433
厂家：	Infineon
描述：	32位PSoC™ 4 Arm® Cortex®-M0/M0+
文件：	总46页 (文件大小：803K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

CY8C4145LQI-PS433 [INFINEON]

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