CY8C4147LQS-S473 [INFINEON]
Automotive PSoC™ 4100S Plus;
| 型号： | CY8C4147LQS-S473 |
| 厂家： | 
Infineon |
| 描述： | Automotive PSoC™ 4100S Plus |
| 文件： | 总65页 (文件大小：1465K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY8C41xx
Automotive PSoC™ 4: PSoC™ 4100S Plus
Based on Arm® Cortex®-M0+ CPU
General description
PSoC™ 4 is a scalable and reconfigurable platform architecture for a family of programmable embedded system
controllers with an Arm® Cortex®-M0+ CPU while being AEC-Q100 compliant. It combines programmable and
reconfigurable analog and digital blocks with flexible automatic routing. PSoC™ 4100S Plus is a member of the
PSoC™ 4 platform architecture. It is a combination of a microcontroller with standard communication and timing
peripherals, a capacitive touch-sensing system (CAPSENSE™) with best-in-class performance, programmable
general-purpose continuous-time and switched-capacitor analog blocks, and programmable connectivity.
PSoC™ 4100S Plus products will be upward compatible with members of the PSoC™ 4 platform for new
applications and design needs.
Features
• Automotive Electronics Council (AEC) AEC-Q100 Qualified
• 32-bit MCU subsystem
- 48-MHz Arm® Cortex®-M0+ CPU
- Up to 128 KB of flash with Read Accelerator
- Up to 16 KB of SRAM
- 8-channel DMA engine
• Programmable analog
- Two opamps with reconfigurable high-drive external and high-bandwidth internal drive and comparator
modes and ADC input buffering capability. Opamps can operate in Deep Sleep low-power mode.
- 12-bit 1-Msps SAR ADC with differential and single-ended modes, and channel sequencer with signal averaging
- Single-slope 10-bit ADC function provided by a capacitance sensing block
- Two current DACs (IDACs) for general-purpose or capacitive sensing applications on any pin
- Two low-power comparators that operate in Deep Sleep low-power mode
• Programmable digital
- Programmable logic blocks allowing Boolean operations to be performed on port inputs and outputs
• Low-power 1.71 V to 5.5 V operation
- Deep Sleep mode with operational analog and 2.5 A digital system current
• Capacitive sensing
- Capacitive sigma-delta (CSD) provides best-in-class signal-to-noise ratio (SNR) (> 5:1) and water tolerance
- Infineon-supplied software component makes capacitive sensing design easy
- Automatic hardware tuning (SmartSense)
• LCD drive capability
- LCD segment drive capability on GPIOs
• Serial communication
- Five independent run-time reconfigurable serial communication blocks (SCBs) with re-configurable I2C, SPI,
UART functionality, or LIN slave functionality
• Timing and pulse-width modulation
- Eight 16-bit timer/counter/pulse-width modulator (TCPWM) blocks
- Center-aligned, Edge, and Pseudo-random modes
- Comparator-based triggering of Kill signals for motor drive and other high-reliability digital logic applications
- Quadrature decoder
Datasheet
www.infineon.com
Please read the Important Notice and Warnings at the end of this document
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Automotive PSoC™ 4: PSoC™ 4100S Plus
Based on Arm® Cortex®-M0+ CPU
Features
• Clock sources
- 4 to 33 MHz external crystal oscillator (ECO)
- PLL to generate 48-MHz frequency
- 32-kHz watch crystal oscillator (WCO)
- ±2% internal main oscillator (IMO)
- 32-kHz internal low-power oscillator (ILO)
• True random number generator (TRNG)
- TRNG generates truly random number for secure key generation for cryptography applications
• CAN block
- CAN 2.0B block with support for time-triggered CAN (TTCAN)
• Temperature range
- Grade-A: –40°C to +85°C
- Grade-S: –40°C to +105°C
- Grade-E: –40°C to +125°C
• Up to 54 programmable GPIO pins
- 40-pin QFN, 64-pin QFN, and 64-pin TQFP packages
- Any GPIO pin can be CAPSENSE™, analog, or digital
- Drive modes, strengths, and slew rates are programmable
• PSoC™ Creator design environment
- Integrateddevelopment environment (IDE)providesschematicdesign entry andbuild (with analogand digital
automatic routing)
- Applications programming interface (API) component for all fixed-function and programmable peripherals
• Industry-standard tool compatibility
- After schematic entry, development can be done with Arm®-based industry-standard development tools
Datasheet
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Automotive PSoC™ 4: PSoC™ 4100S Plus
Based on Arm® Cortex®-M0+ CPU
More information
More information
Infineon provides a wealth of data at www.infineon.com to help you to select the right PSoC™ device for your
design, and to help you to quickly and effectively integrate the device into your design. For a comprehensive list
of resources, see the knowledge base article How to design with PSoC™ 3, PSoC™ 4, and PSoC™ 5LP -
KBA86521. Following is an abbreviated list for PSoC™ 4:
• Overview: PSoC™ portfolio
• Product selectors: PSoC™ 1, PSoC™ 3, PSoC™ 4, PSoC™ 5LP
In addition, PSoC™ Creator includes a device selection tool.
• Application notes: Infineon offers a large number of PSoC™ application notes covering a broad range of topics,
from basic to advanced level. Recommended application notes for getting started with PSoC™ 4 are:
- AN79953: Getting started With PSoC™ 4
- AN88619: PSoC™ 4 hardware design considerations
- AN86439: Using PSoC™ 4 GPIO pins
- AN57821: Mixed signal circuit board layout
- AN81623: Digital design best practices
- AN73854: Introduction to bootloaders
- AN89610: Arm® Cortex® code optimization
- AN85951: PSoC™ 4 and PSoC™ analog coprocessor CAPSENSE™ design guide
• Technical reference manual (TRM) is in two documents:
- Architecture TRM details each PSoC™ 4 functional block.
- Registers TRM describes each of the PSoC™ 4 registers.
• Development kits:
- CY8CKIT-041-41XX PSoC™ 4100S CAPSENSE™ Pioneer Kit, is an easy-to-use and inexpensive development
platform. This kit includes connectors for Arduino™ compatible shields.
- CY8CKIT-149 PSoC™ 4100S Plus prototyping kit enables you to evaluate and develop with Infineon’s
fourth-generation, low-power CAPSENSE™ solution using the PSoC™ 4100S Plus devices.
The MiniProg3 device provides an interface for flash programming and debug.
• Software user guide:
- A step-by-step guide for using PSoC™ Creator. The software user guide shows you how the PSoC™ Creator
build process works in detail, how to use source control with PSoC™ Creator, and much more.
• Component datasheets:
- The flexibility of PSoC™ allows the creation of new peripherals (components) long after the device has gone
into production. Component datasheets provide all the information needed to select and use a particular
component, including a functional description, API documentation, example code, and AC/DC specifications.
• Online:
- In addition to print documentation, the Infineon community page connects you with fellow PSoC™ users and
experts in PSoC™ from around the world, 24 hours a day, 7 days a week.
Datasheet
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Automotive PSoC™ 4: PSoC™ 4100S Plus
Based on Arm® Cortex®-M0+ CPU
PSoC™ Creator
PSoC™ Creator
PSoC™ Creator is a free Windows-based integrated design environment (IDE). It enables concurrent hardware
and firmware design of PSoC™ 3, PSoC™ 4, and PSoC™ 5LP based systems. Create designs using classic, familiar
schematic capture supported by over 100 pre-verified, production-ready PSoC™ Components; see the list of
component datasheets. With PSoC™ Creator, you can:
1. Drag and drop component icons to build your hardware system design in the main design workspace
2. Codesign your application firmware with the PSoC™ hardware, using the PSoC™ Creator IDE C compiler
3. Configure components using the configuration tools
4. Explore the library of 100+ components
5. Review component datasheets
1
2
3
4
5
Figure 1
Multiple-sensor example project in PSoC™ Creator
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Automotive PSoC™ 4: PSoC™ 4100S Plus
Based on Arm® Cortex®-M0+ CPU
Table of contents
Table of contents
General description ...........................................................................................................................1
Features ...........................................................................................................................................1
More information ..............................................................................................................................3
PSoC™ Creator ..................................................................................................................................4
Table of contents...............................................................................................................................5
Block diagram...................................................................................................................................7
1 Functional definition.......................................................................................................................8
1.1 CPU and memory subsystem .................................................................................................................................8
1.1.1 CPU .......................................................................................................................................................................8
1.1.2 Flash .....................................................................................................................................................................8
1.1.3 SRAM.....................................................................................................................................................................8
1.1.4 SROM ....................................................................................................................................................................8
1.2 System resources....................................................................................................................................................8
1.2.1 Power system.......................................................................................................................................................8
1.2.2 Clock system ........................................................................................................................................................9
1.2.3 IMO clock source ..................................................................................................................................................9
1.2.4 ILO clock source...................................................................................................................................................9
1.2.5 WCO ....................................................................................................................................................................10
1.2.6 ECO .....................................................................................................................................................................10
1.2.7 WDT.....................................................................................................................................................................10
1.2.8 Reset ...................................................................................................................................................................10
1.3 Analog blocks ........................................................................................................................................................10
1.3.1 12-bit SAR ADC ...................................................................................................................................................10
1.3.2 Two opamps (continuous-time block; CTB).....................................................................................................11
1.3.3 Low-power comparators (LPC) .........................................................................................................................11
1.3.4 Current DACs ......................................................................................................................................................11
1.3.5 Analog multiplexed buses .................................................................................................................................11
1.4 Programmable digital blocks...............................................................................................................................11
1.4.1 Smart I/O block ..................................................................................................................................................11
1.5 Fixed function digital blocks ................................................................................................................................12
1.5.1 Timer/counter/PWM (TCPWM) block ................................................................................................................12
1.5.2 Serial Communication Block (SCB)...................................................................................................................12
1.5.3 CAN .....................................................................................................................................................................12
1.6 GPIO.......................................................................................................................................................................13
1.7 Special function peripherals ................................................................................................................................13
1.7.1 CAPSENSE™........................................................................................................................................................13
1.7.2 LCD segment drive.............................................................................................................................................13
2 Pinouts ........................................................................................................................................14
2.1 Alternate pin functions .........................................................................................................................................17
3 Power ..........................................................................................................................................20
3.1 Mode 1: 1.8 V to 5.5 V external supply..................................................................................................................20
3.2 Mode 2: 1.8 V ± 5% external supply ......................................................................................................................20
4 Electrical specifications.................................................................................................................22
4.1 Absolute maximum ratings ..................................................................................................................................22
4.2 Device-level specifications ...................................................................................................................................23
4.2.1 GPIO....................................................................................................................................................................24
4.2.2 XRES....................................................................................................................................................................26
4.3 Analog peripherals................................................................................................................................................27
4.3.1 CTBm opamp .....................................................................................................................................................27
4.3.2 Comparator........................................................................................................................................................31
4.3.3 Temperature sensor ..........................................................................................................................................32
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Based on Arm® Cortex®-M0+ CPU
Table of contents
4.3.4 SAR ADC..............................................................................................................................................................32
4.3.5 CSD and IDAC .....................................................................................................................................................33
4.3.6 10-bit CAPSENSE™ ADC......................................................................................................................................36
4.4 Digital peripherals.................................................................................................................................................37
4.4.1 Timer counter pulse-width modulator (TCPWM) .............................................................................................37
4.4.2 I2C .......................................................................................................................................................................38
4.4.3 SPI.......................................................................................................................................................................39
4.4.4 UART ...................................................................................................................................................................40
4.4.5 LCD Direct Drive .................................................................................................................................................40
4.5 Memory..................................................................................................................................................................41
4.5.1 Flash ...................................................................................................................................................................41
4.6 System resources..................................................................................................................................................42
4.6.1 Power-on reset (POR) ........................................................................................................................................42
4.6.2 Brown-out detect (BOD) ....................................................................................................................................42
4.6.3 SWD interface.....................................................................................................................................................42
4.6.4 Internal main oscillator .....................................................................................................................................43
4.6.5 Internal low-speed oscillator ............................................................................................................................44
4.6.6 Watch crystal oscillator (WCO)..........................................................................................................................44
4.6.7 External clock.....................................................................................................................................................44
4.6.8 External crystal oscillator and PLL....................................................................................................................45
4.6.9 System clock ......................................................................................................................................................46
4.6.10 Smart I/O ..........................................................................................................................................................46
4.6.11 CAN ...................................................................................................................................................................46
5 Ordering information ....................................................................................................................47
6 Packaging ....................................................................................................................................55
6.1 Package diagrams.................................................................................................................................................56
7 Acronyms.....................................................................................................................................59
8 Document conventions..................................................................................................................63
8.1 Units of measure ...................................................................................................................................................63
Revision history ..............................................................................................................................64
Datasheet
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Automotive PSoC™ 4: PSoC™ 4100S Plus
Based on Arm® Cortex®-M0+ CPU
Block diagram
Block diagram
CPU Subsystem
PSoC™ 4100S
SWD/TC, MTB
SPCIF
Plus
DataWire/
DMA
Cortex® M0+
48 MHz
FLASH
128 KB
SRAM
16 KB
ROM
8 KB
32-bit
FAST MUL
NVIC, IRQMUX, MPU
Initiator/MMIO
AHB-Lite
Read Accelerator
SRAM Controller
ROM Controller
System Resources
Lite
System Interconnect (Single Layer AHB)
Peripheral Interconnect (MMIO)
Power
Sleep Control
WIC
Peripherals
PCLK
POR
REF
PWRSYS
Clock
Clock Control
WDT
Programmable
Analog
ILO
IMO
SAR ADC
(12-bit)
Reset
Reset Control
XRES
Test
TestMode Entry
Digital DFT
Analog DFT
x1
CTBm
2x OpAmp
SARMUX
High Speed I/O Matrix & Sm art I/O
Power Modes
Active/Sleep
DeepSleep
Up to 54x GPIOs
I/O Subsystem
PSoC™ 4100S Plus devices include extensive support for programming, testing, debugging, and tracing both
hardware and firmware.
The Arm® serial-wire debug (SWD) interface supports all programming and debug features of the device.
Complete debug-on-chip functionality enables full-device debugging in the final system using the standard
production device. It does not require special interfaces, debugging pods, simulators, or emulators. Only the
standard programming connections are required to fully support debug.
The PSoC™ Creator IDE provides fully integrated programming and debug support for the PSoC™ 4100S Plus
devices. The SWD interface is fully compatible with industry-standard third-party tools. PSoC™ 4100S Plus
provides a level of security not possible with multi-chip application solutions or with microcontrollers. It has the
following advantages:
• Allows disabling of debug features
• Robust flash protection
• Allows customer-proprietary functionality to be implemented in on-chip programmable blocks
The debug circuits are enabled by default and can be disabled in firmware. If they are not enabled, the only way
to re-enable them is to erase the entire device, clear flash protection, and reprogram the device with new
firmware that enables debugging. Thus firmware control of debugging cannot be over-ridden without erasing the
firmware thus providing security.
Additionally, all device interfaces can be permanently disabled (device security) for applications concerned
about phishing attacks due to a maliciously reprogrammed device or attempts to defeat security by starting and
interrupting flash programming sequences. All programming, debug, and test interfaces are disabled when
maximum device security is enabled. Therefore, PSoC™ 4100S Plus, with device security enabled, may not be
returned for failure analysis. This is a trade-off the PSoC™ 4100S Plus allows the customer to make.
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Based on Arm® Cortex®-M0+ CPU
Functional definition
1
Functional definition
CPU and memory subsystem
CPU
1.1
1.1.1
The Cortex®-M0+ CPU in the PSoC™ 4100S Plus is part of the 32-bit MCU subsystem, which is optimized for
low-power operation with extensive clock gating. Most instructions are 16 bits in length and the CPU executes a
subset of the Thumb-2 instruction set. It includes a nested vectored interrupt controller (NVIC) block with eight
interrupt inputs and also includes a Wakeup Interrupt Controller (WIC). The WIC can wake the processor from
Deep Sleep mode, allowing power to be switched off to the main processor when the chip is in Deep Sleep mode.
The CPU subsystem includes an 8-channel DMA engine and also includes a debug interface, the SWD interface,
which is a 2-wire form of JTAG. The debug configuration used for PSoC™ 4100S Plus has four breakpoint (address)
comparators and two watchpoint (data) comparators.
1.1.2
Flash
The PSoC™ 4100S Plus device has a flash module with a flash accelerator, tightly coupled to the CPU to improve
average access times from the flash block. The low-power flash block is designed to deliver two wait-state (WS)
access time at 48 MHz. The flash accelerator delivers 85% of single-cycle SRAM access performance on average.
1.1.3
SRAM
16 KB of SRAM are provided with zero wait-state access at 48 MHz.
1.1.4
SROM
An 8-KB supervisory ROM that contains boot and configuration routines is provided.
1.2
1.2.1
System resources
Power system
The power system is described in detail in the section “Power” on page 20. It provides assurance that voltage
levels are as required for each respective mode and either delays mode entry (for example, on power-on reset
(POR)) until voltage levels are as required for proper functionality, or generates resets (for example, on brownout
detection). PSoC™ 4100S Plus operates with a single external supply over the range of either 1.8 V ±5% (externally
regulated) or 1.8 V to 5.5 V (internally regulated) and has three different power modes, transitions between which
are managed by the power system. PSoC™ 4100S Plus provides Active, Sleep, and Deep Sleep low-power modes.
All subsystems are operational in Active mode. The CPU subsystem (CPU, flash, and SRAM) is clock-gated off in
Sleep mode, while all peripherals and interrupts are active with instantaneous wake-up on a wake-up event. In
Deep Sleep mode, the high-speed clock and associated circuitry is switched off; wake-up from this mode takes
35 µs. The opamps can remain operational in Deep Sleep mode.
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Based on Arm® Cortex®-M0+ CPU
Functional definition
1.2.2
Clock system
The PSoC™ 4100S Plus clock system is responsible for providing clocks to all subsystems that require clocks and
for switching between different clock sources without glitching. In addition, the clock system ensures that there
are no metastable conditions.
The clock system for the PSoC™ 4100S Plus consists of the IMO, ILO, a 32-kHz watch crystal oscillator (WCO), MHz
ECO and PLL, and provision for an external clock. The WCO block allows locking the IMO to the 32-kHz oscillator.
External Clock
HFCLK
Divide By
2, 4, 8
IMO
ECO
PLL
WDC1
WCO
ILO
16-bits
LFCLK
WDC1
16-bits
WDC2
32-bits
WDT
Watchdog Counters (WDC)
Watchdog Timer (WDT)
Prescaler
SYSCLK
HFCLK
Integer
Dividers
12X 16-bit
Fractional
Dividers
5X 16.5-bit, 1X 24.5 bit
Figure 2
PSoC™ 4100S Plus MCU clocking architecture
The HFCLK signal can be divided down as shown to generate synchronous clocks for the Analog and Digital
peripherals. There are 18 clock dividers for the PSoC™ 4100S Plus (six with fractional divide capability, twelve with
integer divide only). The twelve 16-bit integer divide capability allows a lot of flexibility in generating fine-grained
frequency. In addition, there are five 16-bit fractional dividers and one 24-bit fractional divider.
1.2.3
IMO clock source
The IMO is the primary source of internal clocking in the PSoC™ 4100S Plus. It is trimmed during testing to achieve
the specified accuracy.The IMO default frequency is 24 MHz and it can be adjusted from 24 to 48 MHz in steps of
4 MHz. The IMO tolerance with Infineon-provided calibration settings is ±2% over the entire voltage and
temperature range.
1.2.4
ILO clock source
The ILO is a very low power, nominally 40-kHz oscillator, which is primarily used to generate clocks for the
watchdog timer (WDT) and peripheral operation in Deep Sleep mode. ILO-driven counters can be calibrated to
the IMO to improve accuracy. Infineon provides a software component, which does the calibration.
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Based on Arm® Cortex®-M0+ CPU
Functional definition
1.2.5
WCO
The PSoC™ 4100S Plus clock subsystem also implements a low-frequency (32-kHz watch crystal) oscillator that
can be used for precision timing applications.
1.2.6
ECO
The PSoC™ 4100S Plus also implements a 4 to 33 MHz crystal oscillator.
1.2.7
WDT
A watchdog timer is implemented in the clock block running from the ILO; this allows watchdog operation during
Deep Sleep and generates a watchdog reset if not serviced before the set timeout occurs. The watchdog reset is
recorded in a Reset Cause register, which is firmware readable.
1.2.8
Reset
PSoC™ 4100S Plus can be reset from a variety of sources including a software reset. Reset events are
asynchronous and guarantee reversion to a known state. The reset cause is recorded in a register, which is sticky
through reset and allows software to determine the cause of the reset. An XRES pin is reserved for external reset
by asserting it active low. The XRES pin has an internal pull-up resistor that is always enabled.
1.3
Analog blocks
12-bit SAR ADC
1.3.1
The 12-bit, 1-Msps SAR ADC can operate at a maximum clock rate of 18 MHz and requires a minimum of 18 clocks
at that frequency to do a 12-bit conversion.
The sample-and-hold (S/H) aperture is programmable allowing the gain bandwidth requirements of the amplifier
driving the SAR inputs, which determine its settling time, to be relaxed if required. It is possible to provide an
external bypass (through a fixed pin location) for the internal reference amplifier.
The SAR is connected to a fixed set of pins through an 8-input sequencer. The sequencer cycles through selected
channels autonomously (sequencer scan) with zero switching overhead (that is, aggregate sampling bandwidth
is equal to 1 Msps whether it is for a single channel or distributed over several channels). The sequencer switching
is effected through a state machine or through firmware driven switching. A feature provided by the sequencer
is buffering of each channel to reduce CPU interrupt service requirements. To accommodate signals with varying
source impedance and frequency, it is possible to have different sample times programmable for each channel.
Also, signal range specification through a pair of range registers (low and high range values) is implemented with
a corresponding out-of-range interrupt if the digitized value exceeds the programmed range; this allows fast
detection of out-of-range values without the necessity of having to wait for a sequencer scan to be completed
and the CPU to read the values and check for out-of-range values in software.
The SAR is not available in Deep Sleep mode as it requires a high-speed clock (up to 18 MHz). The SAR operating
range is 1.71 V to 5.5 V.
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Functional definition
AHB System Bus and Programmable Logic Interconnect
SAR Sequencer
Sequencing
and Control
Data and
Status Flags
POS
NEG
SARADC
External
Reference and
Bypass
Reference
Section
(optional )
VDDA
VREF
VDDA /2
Inputs from other Ports
Figure 3
SAR ADC
1.3.2
Two opamps (continuous-time block; CTB)
PSoC™ 4100S Plus has two opamps with Comparator modes which allow most common analog functions to be
performed on-chip eliminating external components; PGAs, voltage buffers, filters, trans-impedance amplifiers,
and other functions can be realized, in some cases with external passives. saving power, cost, and space. The
on-chip opamps are designed with enough bandwidth to drive the sample-and-hold circuit of the ADC without
requiring external buffering.
1.3.3
Low-power comparators (LPC)
PSoC™ 4100S Plus has a pair of low-power comparators, which can also operate in Deep Sleep modes. This allows
the analog system blocks to be disabled while retaining the ability to monitor external voltage levels during
low-power modes. The comparator outputs are normally synchronized to avoid metastability unless operating
in an asynchronous power mode where the system wake-up circuit is activated by a comparator switch event.
The LPC outputs can be routed to pins.
1.3.4
Current DACs
PSoC™ 4100S Plus has two IDACs, which can drive any of the pins on the chip. These IDACs have programmable
current ranges.
1.3.5
Analog multiplexed buses
PSoC™ 4100S Plus has two concentric independent buses that go around the periphery of the chip. These buses
(called amux buses) are connected to firmware-programmable analog switches that allow the chip's internal
resources (IDACs, comparator) to connect to any pin on the I/O ports.
1.4
Programmable digital blocks
Smart I/O block
1.4.1
The Smart I/O block is a fabric of switches and LUTs that allows Boolean functions to be performed in signals
being routed to the pins of a GPIO port. The Smart I/O can perform logical operations on input pins to the chip
and on signals going out as outputs.
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Functional definition
1.5
Fixed function digital blocks
1.5.1
Timer/counter/PWM (TCPWM) block
The TCPWM block consists of a 16-bit counter with user-programmable period length. There is a capture register
to record the count value at the time of an event (which may be an I/O event), a period register that is used to
either stop or auto-reload the counter when its count is equal to the period register, and compare registers to
generate compare value signals that are used as PWM duty cycle outputs. The block also provides true and
complementary outputs with programmable offset between them to allow use as dead-band programmable
complementary PWM outputs. It also has a Kill input to force outputs to a predetermined state; for example, this
is used in motor drive systems when an over-current state is indicated and the PWM driving the FETs needs to be
shut off immediately with no time for software intervention. Each block also incorporates a quadrature decoder.
There are eight TCPWM blocks in PSoC™ 4100S Plus.
1.5.2
Serial Communication Block (SCB)
PSoC™ 4100S Plus has five serial communication blocks, which can be programmed to have SPI, I2C, UART, or LIN
Slave functionality.
I2C mode: The hardware I2C block implements a full multi-master and slave interface (it is capable of
multi-master arbitration). This block is capable of operating at speeds of up to 1 Mbps (Fast Mode Plus) and has
flexible buffering options to reduce interrupt overhead and latency for the CPU. It also supports EZI2C that creates
a mailbox address range in the memory of PSoC™ 4100S Plus and effectively reduces I2C communication to
reading from and writing to an array in memory. In addition, the block supports an 8-deep FIFO for receive and
transmit which, by increasing the time given for the CPU to read data, greatly reduces the need for clock
stretching caused by the CPU not having read data on time.
The I2C peripheral is compatible with the I2C Standard-mode and Fast-mode Plus devices as defined in the NXP
I2C-bus specification and user manual (UM10204). The I2C bus I/O is implemented with GPIO in open-drain
modes.
PSoC™ 4100S Plus is not completely compliant with the I2C spec in the following respect:
• GPIO cells are not over-voltage tolerant and, therefore, cannot be hot-swapped or powered up independently
of the rest of the I2C system.
UART mode: This is a full-feature UART operating at up to 1 Mbps. It supports automotive single-wire interface
(LIN), infrared interface (IrDA), and SmartCard (ISO7816) protocols, all of which are minor variants of the basic
UART protocol. In addition, it supports the 9-bit multiprocessor mode that allows addressing of peripherals
connected over common RX and TX lines. Common UART functions such as parity error, break detect, and frame
error are supported. An 8-deep FIFO allows much greater CPU service latencies to be tolerated.
SPI mode: The SPI mode supports full Motorola SPI, TI SSP (adds a start pulse used to synchronize SPI Codecs),
and National Microwire (half-duplex form of SPI). The SPI block can use the FIFO.
LIN Slave mode: The LIN slave mode uses the SCB hardware block and implements a full LIN slave interface. This
LIN slave is compliant with LIN v1.3, v2.1/2.2, ISO 17987-6, and SAE J2602-2 specification standards. It is certified
by C&S GmbH based on the standard protocol and data link layer conformance tests. LIN slave can be operated
at baud rates of up to ~20 Kbps with a maximum of 40-meter cable length. The PSoC™ Creator software supports
up to two LIN slave interfaces in the PSoC™ 4 device, providing built-in application programming interfaces (APIs)
based on the LIN specification standard.
1.5.3
CAN
There is one CAN block, which implements CAN 2.0B as defined in the Bosch specifications and conform to the
ISO-11898-1 standard.
Datasheet
12
002-20072 Rev. *P
2023-05-02
Automotive PSoC™ 4: PSoC™ 4100S Plus
Based on Arm® Cortex®-M0+ CPU
Functional definition
1.6
GPIO
PSoC™ 4100S Plus has up to 54 GPIOs. The GPIO block implements the following:
• Eight drive modes:
- Analog input mode (input and output buffers disabled)
- Input only
- Weak pull-up with strong pull-down
- Strong pull-up with weak pull-down
- Open drain with strong pull-down
- Open drain with strong pull-up
- Strong pull-up with strong pull-down
- Weak pull-up with weak pull-down
• Input threshold select (CMOS or LVTTL).
• Individual control of input and output buffer enabling/disabling in addition to the drive strength modes
• Selectable slew rates for dV/dt related noise control to improve EMI
The pins are organized in logical entities called ports, which are 8-bit in width (less for Ports 5 and 6). During
power-on and reset, the blocks are forced to the disabled state so as not to crowbar any inputs and/or cause
excess turn-on current. A multiplexing network known as a high-speed I/O matrix is used to multiplex between
various signals that may connect to an I/O pin.
Data output and pin state registers store, respectively, the values to be driven on the pins and the states of the
pins themselves.
Every I/O pin can generate an interrupt if so enabled and each I/O port has an interrupt request (IRQ) and interrupt
service routine (ISR) vector associated with it.
1.7
1.7.1
Special function peripherals
CAPSENSE™
CAPSENSE™ is supported in the PSoC™ 4100S Plus through a CAPSENSE™ sigma-delta (CSD) block that can be
connected to any pins through an analog multiplex bus via analog switches. CAPSENSE™ function can thus be
provided on any available pin or group of pins in a system under software control. A PSoC™ Creator component
is provided for the CAPSENSE™ block to make it easy for the user.
Shield voltage can be driven on another analog multiplex bus to provide water-tolerance capability. Water
tolerance is provided by driving the shield electrode in phase with the sense electrode to keep the shield
capacitance from attenuating the sensed input. Proximity sensing can also be implemented.
The CAPSENSE™ block has two IDACs, which can be used for general purposes if CAPSENSE™ is not being used
(both IDACs are available in that case) or if CAPSENSE™ is used without water tolerance (one IDAC is available).
The CAPSENSE™ block also provides a 10-bit Slope ADC function which can be used in conjunction with the
CAPSENSE™ function.
The CAPSENSE™ block is an advanced, low-noise, programmable block with programmable voltage references
and current source ranges for improved sensitivity and flexibility. It can also use an external reference voltage. It
has a full-wave CSD mode that alternates sensing to VDDA and ground to null out power-supply related noise.
1.7.2
LCD segment drive
PSoC™ 4100S Plus has an LCD controller, which can drive up to 4 commons and up to 50 segments. It uses full
digital methods to drive the LCD segments requiring no generation of internal LCD voltages. The two methods
used are referred to as Digital Correlation and PWM. Digital Correlation pertains to modulating the frequency and
drive levels of the common and segment signals to generate the highest RMS voltage across a segment to light it
up or to keep the RMS signal to zero. This method is good for STN displays but may result in reduced contrast
with TN (cheaper) displays. PWM pertains to driving the panel with PWM signals to effectively use the capacitance
of the panel to provide the integration of the modulated pulse-width to generate the desired LCD voltage. This
method results in higher power consumption but can result in better results when driving TN displays. LCD
operation is supported during Deep Sleep refreshing a small display buffer (4 bits; one 32-bit register per port).
Datasheet
13
002-20072 Rev. *P
2023-05-02
Automotive PSoC™ 4: PSoC™ 4100S Plus
Based on Arm® Cortex®-M0+ CPU
Pinouts
2
Pinouts
Table 1
40-pin QFN package pin list
Pin
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
Name
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
XRES
VCCD
VSSD
VDD
VSSA
P1.0
P1.1
P1.2
P1.3
P1.4
P1.7/VREF
P2.3
P2.4
P2.5
P2.6
P2.7
P6.0
P6.1
P6.2
VSSD
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
P4.0
Datasheet
14
002-20072 Rev. *P
2023-05-02
Automotive PSoC™ 4: PSoC™ 4100S Plus
Based on Arm® Cortex®-M0+ CPU
Pinouts
Table 1
40-pin QFN package pin list (continued)
Pin
19
Name
P4.1
20
P4.2
21
P4.3
Table 2
64-pin QFN and 64-pin TQFP packages pin list
Pin
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
1
Name
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
XRES
VCCD
VSSD
VDDD
P5.0
P5.1
P5.2
P5.3
P5.5
VDDA
VSSA
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
2
3
4
5
6
7
8
Datasheet
15
002-20072 Rev. *P
2023-05-02
Automotive PSoC™ 4: PSoC™ 4100S Plus
Based on Arm® Cortex®-M0+ CPU
Pinouts
Table 2
64-pin QFN and 64-pin TQFP packages pin list (continued)
Pin
9
Name
P2.7
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
VSSD
No Connect (NC)
P6.0
P6.1
P6.2
P6.4
P6.5
VSSD
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
VDDD
P4.0
P4.1
P4.2
P4.3
P4.4
P4.5
P4.6
P4.7
P5.6
P5.7
P7.0
P7.1
Descriptions of the Power pins are as follows:
VDDD: Power supply for the digital section.
VDDA: Power supply for the analog section.
VSSD, VSSA: Ground pins for the digital and analog sections respectively.
VCCD: Regulated digital supply (1.8 V ± 5%)
VDD: On some packages, VDDA and VDDD are shorted inside and brought out as a single power supply
GPIOs: 54
Datasheet
16
002-20072 Rev. *P
2023-05-02
2.1
Alternate pin functions
Each port pin has can be assigned to one of multiple functions; it can, for example, be an analog I/O, a digital peripheral function, an LCD pin, or a
CAPSENSE™ pin. The pin assignments are shown in the following table.
Table 3
Port/Pin
P0.0
Pin assignments
Analog
lpcomp.in_p[0]
lpcomp.in_n[0]
lpcomp.in_p[1]
lpcomp.in_n[1]
wco.wco_in
wco.wco_out
exco.eco_in
Smart I/O
ACT #0
ACT #1
ACT #3
DS #2
scb[2].i2c_scl:0
DS #3
tcpwm.tr_in[0] scb[2].uart_cts:0
tcpwm.tr_in[1] scb[2].uart_rts:0 scb[2].i2c_sda:0
scb[0].spi_select1:0
scb[0].spi_select2:0
scb[0].spi_select3:0
scb[2].spi_select0:1
scb[1].spi_mosi:1
scb[1].spi_miso:1
scb[1].spi_clk:1
scb[1].spi_select0:1
scb[2].spi_mosi:0
scb[2].spi_miso:0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
P5.0
scb[1].uart_rx:0 scb[2].uart_rx:0
scb[1].uart_tx:0 scb[2].uart_tx:0
scb[1].uart_cts:0 scb[2].uart_tx:1
scb[1].uart_rts:0
scb[1].i2c_scl:0
scb[1].i2c_sda:0
srss.ext_clk:0
tcpwm.line[0]:3
tcpwm.line[4]:2
tcpwm.line_
compl[4]:2
exco.eco_out
scb[2].uart_rx:1
scb[2].uart_tx:2
scb[2].i2c_scl:1
scb[2].i2c_sda:1
P5.1
P5.2
P5.3
tcpwm.line[5]:2
tcpwm.line_
compl[5]:2
scb[2].uart_cts:1 lpcomp.comp[0]:2
scb[2].uart_rts:1 lpcomp.comp[1]:0
scb[2].spi_clk:0
scb[2].spi_select0:0
P5.4
P5.5
tcpwm.line[6]:2
tcpwm.line_-
compl[6]:2
scb[2].spi_select1:0
scb[2].spi_select2:0
P1.0
P1.1
ctb0_oa0+
ctb0_oa0-
SmartIo[2].io[0]
SmartIo[2].io[1]
tcpwm.line[2]:1
tcpwm.line_
compl[2]:1
scb[0].uart_rx:1
scb[0].uart_tx:1
scb[0].i2c_scl:0
scb[0].i2c_sda:0
scb[0].spi_mosi:1
scb[0].spi_miso:1
P1.2
P1.3
ctb0_oa0_out
ctb0_oa1_out
SmartIo[2].io[2]
SmartIo[2].io[3]
tcpwm.line[3]:1
tcpwm.line_
compl[3]:1
scb[0].uart_cts:1 tcpwm.tr_in[2]
scb[0].uart_rts:1 tcpwm.tr_in[3]
scb[2].i2c_scl:2
scb[2].i2c_sda:2
scb[0].spi_clk:1
scb[0].spi_select0:1
P1.4
P1.5
ctb0_oa1-
ctb0_oa1+
SmartIo[2].io[4]
SmartIo[2].io[5]
tcpwm.line[6]:1
tcpwm.line_
compl[6]:1
scb[3].i2c_scl:0
scb[3].i2c_sda:0
scb[0].spi_select1:1
scb[0].spi_select2:1
P1.6
ctb0_oa0+
SmartIo[2].io[6]
tcpwm.line[7]:1
scb[0].spi_select3:1
Table 3
Port/Pin
P1.7
Pin assignments (continued)
Analog
Smart I/O
ACT #0
tcpwm.line_-
compl[7]:1
ACT #1
ACT #3
DS #2
DS #3
scb[2].spi_clk:1
ctb0_oa1+
sar_ext_vref0
sar_ext_vref1
SmartIo[2].io[7]
P2.0
P2.1
sarmux[0]
sarmux[1]
SmartIo[0].io[0]
SmartIo[0].io[1]
tcpwm.line[4]:0
tcpwm.line_
compl[4]:0
csd.comp
tcpwm.tr_in[4]
tcpwm.tr_in[5]
scb[1].i2c_scl:1
scb[1].i2c_sda:1
scb[1].spi_mosi:2
scb[1].spi_miso:2
P2.2
P2.3
sarmux[2]
sarmux[3]
SmartIo[0].io[2]
SmartIo[0].io[3]
tcpwm.line[5]:1
tcpwm.line_
compl[5]:1
scb[1].spi_clk:2
scb[1].spi_select0:2
P2.4
P2.5
sarmux[4]
sarmux[5]
SmartIo[0].io[4]
SmartIo[0].io[5]
tcpwm.line[0]:1
tcpwm.line_
compl[0]:1
scb[3].uart_rx:1
scb[3].uart_tx:1
scb[1].spi_select1:1
scb[1].spi_select2:1
P2.6
P2.7
sarmux[6]
sarmux[7]
SmartIo[0].io[6]
SmartIo[0].io[7]
tcpwm.line[1]:1
tcpwm.line_
compl[1]:1
scb[3].uart_cts:1
scb[3].uart_rts:1
scb[1].spi_select3:1
scb[2].spi_mosi:1
lpcomp.comp[0]:0
scb[3].i2c_scl:1
scb[3].i2c_sda:1
P6.0
P6.1
tcpwm.line[4]:1
scb[3].uart_rx:0
scb[3].uart_tx:0
scb[3].uart_cts:0
can.can_
scb[3].spi_mosi:0
scb[3].spi_miso:0
tx_enb_n:0
tcpwm.line_
compl[4]:1
tcpwm.line[5]:0
tcpwm.line[6]:0
tcpwm.line_
compl[6]:0
can.can_rx:0
P6.2
P6.4
P6.5
can.can_tx:0
scb[3].spi_clk:0
scb[3].spi_select1:0
scb[3].spi_select2:0
scb[4].i2c_scl
scb[4].i2c_sda
P3.0
P3.1
SmartIo[1].io[0]
SmartIo[1].io[1]
tcpwm.line[0]:0
tcpwm.line_
compl[0]:0
scb[1].uart_rx:1
scb[1].uart_tx:1
scb[1].i2c_scl:2
scb[1].i2c_sda:2
scb[1].spi_mosi:0
scb[1].spi_miso:0
P3.2
P3.3
SmartIo[1].io[2]
SmartIo[1].io[3]
tcpwm.line[1]:0
tcpwm.line_
compl[1]:0
scb[1].uart_cts:1
scb[1].uart_rts:1
cpuss.swd_data
cpuss.swd_clk
scb[1].spi_clk:0
scb[1].spi_select0:0
P3.4
P3.5
SmartIo[1].io[4]
SmartIo[1].io[5]
tcpwm.line[2]:0
tcpwm.line_
compl[2]:0
tcpwm.tr_in[6]
scb[1].spi_select1:0
scb[1].spi_select2:0
Table 3
Port/Pin
P3.6
Pin assignments (continued)
Analog
Smart I/O
ACT #0
tcpwm.line[3]:0
tcpwm.line_
compl[3]:0
ACT #1
ACT #3
DS #2
scb[4].spi_select3
lpcomp.comp[1]:1
DS #3
scb[1].spi_select3:0
scb[2].spi_miso:1
SmartIo[1].io[6]
SmartIo[1].io[7]
P3.7
P4.0
P4.1
P4.2
csd.vref_ext
csd.cshield
csd.cmod
scb[0].uart_rx:0
scb[0].uart_tx:0
scb[0].uart_cts:0
can.can_rx:1
can.can_tx:1
can.can_
tx_enb_n:1
scb[0].i2c_scl:1
scb[0].i2c_sda:1
lpcomp.comp[0]:1
scb[0].spi_mosi:0
scb[0].spi_miso:0
scb[0].spi_clk:0
P4.3
P4.4
P4.5
P4.6
P4.7
P5.6
P5.7
csd.csh_tank
scb[0].uart_rts:0
scb[4].uart_rx
scb[4].uart_tx
scb[4].uart_cts
scb[4].uart_rts
lpcomp.comp[1]:2
scb[4].spi_mosi
scb[4].spi_miso
scb[4].spi_clk
scb[4].spi_select0
scb[4].spi_select1
scb[4].spi_select2
scb[0].spi_select0:0
scb[0].spi_select1:2
scb[0].spi_select2:2
scb[0].spi_select3:2
tcpwm.line[7]:0
tcpwm.line_
compl[7]:0
scb[2].spi_select3:0
P7.0
P7.1
tcpwm.line[0]:2
tcpwm.line_
compl[0]:2
scb[3].uart_rx:2
scb[3].uart_tx:2
scb[3].i2c_scl:2
scb[3].i2c_sda:2
scb[3].spi_mosi:1
scb[3].spi_miso:1
P7.2
tcpwm.line[1]:2
scb[3].uart_cts:2
scb[3].spi_clk:1
Automotive PSoC™ 4: PSoC™ 4100S Plus
Based on Arm® Cortex®-M0+ CPU
Power
3
Power
The following power system diagram shows the set of power supply pins as implemented for the
PSoC™ 4100S Plus. The system has one regulator in Active mode for the digital circuitry. There is no analog
regulator; the analog circuits run directly from the VDDA input.
VDDA
VDDD
VDDA
VSSA
VDDD
VSSD
Analog
Domain
Digital
Domain
VCCD
1.8 Volt
Regulator
Figure 4
Power supply connections
There are two distinct modes of operation. In Mode 1, the supply voltage range is 1.8 V to 5.5 V (unregulated
externally; internal regulator operational). In Mode 2, the supply range is1.8 V ±5% (externally regulated; 1.71 to
1.89, internal regulator bypassed).
3.1
Mode 1: 1.8 V to 5.5 V external supply
In this mode, PSoC™ 4100S Plus is powered by an external power supply that can be anywhere in the range of 1.8
to 5.5 V. This range is also designed for battery-powered operation. For example, the chip can be powered from
a battery system that starts at 3.5 V and works down to 1.8 V. In this mode, the internal regulator of PSoC™ 4100S
Plus supplies the internal logic and its output is connected to the VCCD pin. The VCCD pin must be bypassed to
ground via an external capacitor (0.1 µF; X5R ceramic or better) and must not be connected to anything else.
3.2
Mode 2: 1.8 V ± 5% external supply
In this mode, PSoC™ 4100S Plus is powered by an external power supply that must be within the range of 1.71 to
1.89 V; note that this range needs to include the power supply ripple too. In this mode, the VDD and VCCD pins
are shorted together and bypassed.
Bypass capacitors must be used from VDDD to ground. The typical practice for systems in this frequency range is
to use a capacitor in the 1-µF range, in parallel with a smaller capacitor (0.1 µF, for example). Note that these are
simply rules of thumb and that, for critical applications, the PCB layout, lead inductance, and the bypass
capacitor parasitic should be simulated to design and obtain optimal bypassing. On some packages, VDDD and
VDDA pins are shorted inside the package and brought out as a generic VDD pin. In that case, only 0.1-µF and 1-µF
decoupling capacitors are required on the VDD pin.
Datasheet
20
002-20072 Rev. *P
2023-05-02
Automotive PSoC™ 4: PSoC™ 4100S Plus
Based on Arm® Cortex®-M0+ CPU
Power
An example of a bypass scheme is shown in the following diagram.
Power supply bypass connections example
1.8 V to 5.5 V
0.1 µF
1.8 V to 5.5 V
0.1 µF
VDDA
VDDD
1 µF
1 µF
VCCD
PSoC™ 4100S Plus
0.1 µF
VSS
Figure 5
External supply range from 1.8 V to 5.5 V with internal regulator active
Datasheet
21
002-20072 Rev. *P
2023-05-02
Automotive PSoC™ 4: PSoC™ 4100S Plus
Based on Arm® Cortex®-M0+ CPU
Electrical specifications
4
Electrical specifications
4.1
Absolute maximum ratings
Absolute maximum ratings[1]
Table 4
Details/
Spec ID# Parameter
Description
Min
Typ
Max
Unit
conditions
SID1
SID2
VDDD_ABS
VCCD_ABS
Digital supply relative to VSS
–0.5
–0.5
–
–
6
V
–
–
Direct digital core voltage
input relative to VSS
1.95
SID3
SID4
SID5
VGPIO_ABS GPIO voltage
–0.5
–25
–0.5
–
–
–
VDD + 0.5
25
–
–
IGPIO_ABS
Maximum current per GPIO
mA
V
IGPIO_in-
jection
GPIO injection current,
Max for VIH > VDDD, and
Min for VIL < VSS
0.5
Current injected
per pin
BID44
BID45
BID46
ESD_HBM Electrostatic discharge
human body model
ESD_CDM Electrostatic discharge
charged device model
2200
500
–
–
–
–
–
–
–
–
LU
Pin current for latch-up
–140
140
mA
Note
1. Usage above the absolute maximum conditions listed in Table 4 may cause permanent damage to the device. Exposure to Absolute
Maximum conditions for extended periods of time may affect device reliability. The Maximum Storage Temperature is 150°C in
compliance with JEDEC Standard JESD22-A103, High Temperature Storage Life. When used below Absolute Maximum conditions
but above normal operating conditions, the device may not operate to specification.
Datasheet
22
002-20072 Rev. *P
2023-05-02
Automotive PSoC™ 4: PSoC™ 4100S Plus
Based on Arm® Cortex®-M0+ CPU
Electrical specifications
4.2
Device-level specifications
All specifications are valid for –40°C TA 85°C for Grade-A devices, –40°C TA 105°C for Grade-S devices, and
–40°C TA 125°C for Grade-E devices. Specifications are valid for 1.71 V to 5.5 V, except where noted.
Table 5
DC specifications
Typical values measured at VDD = 3.3 V and 25°C.
Spec ID# Parameter
Description
Min Typ Max Unit
Details/conditions
SID53
VDD
Power supply input voltage
1.8
–
5.5
V
Internally regulated
supply
SID255
VDD
Power supply input voltage
1.71
–
1.89
Internally unregulated
supply
(VCCD = VDDD = VDDA
)
SID54
SID55
VCCD
CEFC
Output voltage (for core logic)
External regulator voltage
bypass
–
–
1.8
0.1
–
–
–
µF X5R ceramic or better
SID56
CEXC
Power supply bypass
capacitor
–
1
–
X5R ceramic or better
Active mode, VDD = 1.8 V to 5.5 V. Typical values measured at VDD = 3.3 V and 25°C.
SID10
SID16
SID19
IDD5
IDD8
IDD11
Execute from flash;
CPU at 6 MHz
Execute from flash;
CPU at 24 MHz
Execute from flash;
CPU at 48 MHz
–
–
–
1.8
3.0
5.4
2.7 mA Max is at 125°C and 5.5 V
5
Max is at 125°C and 5.5 V
Max is at 125°C and 5.5 V
7.6
Sleep mode, VDDD = 1.8 V to 5.5 V (Regulator on)
SID22
IDD17
I2C wakeup WDT, and
Comparators on
I2C wakeup, WDT, and
Comparators on
–
–
1.1
1.5
2.2 mA 6 MHz. Max is at 125°C
and 5.5 V
SID25
IDD20
2.5
12 MHz. Max is at 125°C
and 5.5 V
Sleep mode, VDDD = 1.71 V to 1.89 V (Regulator bypassed)
SID28
IDD23
I2C wakeup, WDT, and
Comparators on
I2C wakeup, WDT, and
Comparators on
–
–
1.1
1.5
1.8 mA 6 MHz. Max is at 125°C
and 1.89 V.
SID28A
IDD23A
2.1
12 MHz. Max is at 125°C
and 1.89 V.
Deep Sleep mode, VDD = 1.8 V to 3.6 V (Regulator on)
SID30
SID31
IDD25
IDD26
I2C wakeup and WDT on
I2C wakeup and WDT on
–
–
2.5
2.5 350
40
µA T = –40°C to 60°C
Max is at 3.6 V and 125°C
Deep Sleep mode, VDD = 3.6 V to 5.5 V (Regulator on)
SID33
SID34
IDD28
IDD29
I2C wakeup and WDT on
I2C wakeup and WDT on
–
–
2.5
2.5 350
40
µA T = –40°C to 60°C
Max is at 5.5 V and 125°C
Deep Sleep mode, VDD = VCCD = 1.71 V to 1.89 V (Regulator bypassed)
SID36
SID37
IDD31
IDD32
I2C wakeup and WDT on
I2C wakeup and WDT on
–
–
2.5
2.5 400
60
µA T = –40°C to 60°C
Max is at 125°C and 1.89 V
XRES current
SID307
IDD_XR
Supply current while XRES
asserted
–
2
5
mA –
Datasheet
23
002-20072 Rev. *P
2023-05-02
Automotive PSoC™ 4: PSoC™ 4100S Plus
Based on Arm® Cortex®-M0+ CPU
Electrical specifications
Table 6
AC specifications
Spec ID# Parameter
Description
CPU frequency
Wakeup from Sleep mode
Min Typ Max Unit
Details/conditions
SID48
SID49
SID50
FCPU
TSLEEP
DC
–
–
0
48 MHz 1.71 VDD 5.5
–
–
µs
–
–
TDEEPSLEEP Wakeup from Deep Sleep
mode
–
35
4.2.1
GPIO
Table 7
GPIO DC specifications
Spec ID# Parameter
Description
Input voltage high threshold 0.7 VDDD
Min
Typ
–
–
–
–
–
–
–
Max
–
0.3 VDDD
Unit Details/conditions
[2]
SID57
SID58
VIH
VIL
VIH
VIL
VIH
VIL
V
CMOS Input
Input voltage low threshold
LVTTL input, VDDD < 2.7 V
LVTTL input, VDDD < 2.7 V
LVTTL input, VDDD 2.7 V
LVTTL input, VDDD 2.7 V
Output voltage high level
–
CMOS Input
[2]
[2]
SID241
SID242
SID243
SID244
SID59
0.7 VDDD
–
–
–
–
–
–
2.0
–
0.3 VDDD
–
0.8
–
VOH
VDDD – 0.6
IOH = 4 mA at 3 V
VDDD
SID60
SID61
SID62
SID62A
VOH
Output voltage high level
Output voltage low level
Output voltage low level
Output voltage low level
Pull-up resistor
VDDD – 0.5
–
–
–
–
–
IOH = 1 mA at 1.8 V
VDDD
IOL = 4 mA at 1.8 V
VDDD
IOL = 10 mA at 3 V
VDDD
IOL = 3 mA at 3 V
VDDD
VOL
–
–
–
0.6
0.6
0.4
VOL
VOL
SID63
SID64
SID65
RPULLUP
3.5
3.5
–
5.6
5.6
–
8.5
8.5
2
kΩ
–
–
RPULLDOWN Pull-down resistor
IIL
Input leakage current
(absolute value)
nA 25°C, VDDD = 3.0 V
SID66
CIN
VHYSTTL
VHYSCMOS
Input capacitance
Input hysteresis LVTTL
Input hysteresis CMOS
–
25
0.05 ×
VDDD
200
–
–
40
–
7
–
–
pF
mV
–
V
SID67[3]
SID68[3]
DDD 2.7 V
VDD < 4.5 V
SID68A[3] VHYSCMOS5V5 Input hysteresis CMOS
SID69[3]
–
–
–
100
VDD > 4.5 V
–
IDIODE
Current through protection
diode to VDD/VSS
Maximum total source or
sink chip current
µA
SID69A[3] ITOT_GPIO
–
–
200
mA
–
Notes
2. VIH must not exceed VDDD + 0.2 V.
3. Guaranteed by characterization.
Datasheet
24
002-20072 Rev. *P
2023-05-02
Automotive PSoC™ 4: PSoC™ 4100S Plus
Based on Arm® Cortex®-M0+ CPU
Electrical specifications
Table 8
GPIO AC specifications
(Guaranteed by Characterization)
Spec ID# Parameter
Description
Min
Typ Max Unit Details/conditions
SID70
SID71
SID72
SID73
SID74
TRISEF
Rise time in fast strong
mode
Fall time in fast strong mode
2
–
–
–
–
–
12
12
60
60
33
ns 3.3 V VDDD
,
Cload = 25 pF
TFALLF
TRISES
TFALLS
FGPIOUT1
2
10
10
–
3.3 V VDDD
,
Cload = 25 pF
Rise time in slow strong
mode
Fall time in slow strong
mode
–
–
3.3 V VDDD
,
Cload = 25 pF
3.3 V VDDD
,
Cload = 25 pF
GPIO FOUT
;
MHz 90/10%, 25 pF load,
60/40 duty cycle
3.3 V VDDD 5.5 V
Fast strong mode
SID75
FGPIOUT2
FGPIOUT3
FGPIOUT4
FGPIOIN
GPIO FOUT
;
–
–
–
–
–
–
–
–
16.7
7
90/10%, 25 pF load,
60/40 duty cycle
1.71 V VDDD 3.3 V
Fast strong mode
SID76
GPIO FOUT
;
90/10%, 25 pF load,
60/40 duty cycle
3.3 V VDDD 5.5 V
Slow strong mode
SID245
SID246
GPIO FOUT
;
3.5
48
90/10%, 25 pF load,
60/40 duty cycle
1.71 V VDDD 3.3 V
Slow strong mode.
GPIO input operating
frequency;
1.71 V VDDD 5.5 V
90/10% VIO
Datasheet
25
002-20072 Rev. *P
2023-05-02
Automotive PSoC™ 4: PSoC™ 4100S Plus
Based on Arm® Cortex®-M0+ CPU
Electrical specifications
4.2.2
XRES
Table 9
XRES DC specifications
Spec ID# Parameter
Description
Min
Typ
Max
Unit Details/conditions
SID77
VIH
Input voltage high
threshold
0.7 × VDDD
–
–
V
CMOS Input
SID78
VIL
Input voltage low
threshold
–
–
0.3 VDDD
SID79
RPULLUP
CIN
VHYSXRES
Pull-up resistor
–
–
–
60
–
100
–
7
–
kΩ
–
–
SID80
SID81[4]
Input capacitance
Input voltage hysteresis
pF
mV Typical hysteresis is
200 mV for VDD > 4.5 V
SID82
IDIODE
Current through
protection diode to
VDD/VSS
–
–
100
µA –
Table 10
XRES AC specifications
Description
TRESETWIDTH Reset pulse width
Spec ID# Parameter
SID83[4]
BID194[4] TRESETWAKE Wake-up time from
reset release
Min
1
–
Typ
–
–
Max
–
2.7
Unit Details/conditions
µs
–
–
ms
Note
4. Guaranteed by characterization.
Datasheet
26
002-20072 Rev. *P
2023-05-02
Automotive PSoC™ 4: PSoC™ 4100S Plus
Based on Arm® Cortex®-M0+ CPU
Electrical specifications
4.3
Analog peripherals
4.3.1
CTBm opamp
Table 11
CTBm opamp specifications
Spec ID# Parameter
Description
Min
Typ
Max
Units Details/conditions
IDD
Opamp block current,
External load
SID269
SID270
SID271
IDD_HI
IDD_MED
IDD_LOW
GBW
power = hi
power = med
power = lo
Load = 20 pF, 0.1 mA
VDDA = 2.7 V
–
–
–
1100
550
150
1850
950
350
µA
–
–
–
SID272
SID273
SID274
GBW_HI
power = hi
power = med
power = lo
6
3
–
–
–
1
–
–
–
MHz Input and output
are 0.2 V to
VDDA – 0.2 V
GBW_MED
GBW_LO
IOUT_MAX
Input and output
are 0.2 V to
VDDA – 0.2 V
Input and output
are 0.2 V to
VDDA – 0.2 V
VDDA = 2.7 V, 500 mV
from rail
SID275
SID276
SID277
IOUT_MAX_HI power = hi
IOUT_MAX_MID power = mid
IOUT_MAX_LO power = lo
10
10
–
–
–
5
–
–
–
mA Output is 0.5 V to
VDDA – 0.5 V
Output is 0.5 V to
VDDA – 0.5 V
Output is 0.5 V to
VDDA – 0.5 V
IOUT
VDDA = 1.71 V, 500 mV
from rail
SID278
SID279
SID280
IOUT_MAX_HI power = hi
4
–
–
2
–
–
–
mA Output is 0.5 V to
VDDA – 0.5 V
power = mid
IOUT_MAX_MID
Output is 0.5 V to
VDDA – 0.5 V
Output is 0.5 V to
VDDA – 0.5 V
4
–
IOUT_MAX_LO power = lo
IDD_Int
SID269_I IDD_HI_Int
SID270_I IDD_MED_Int power = med
SID271_I IDD_LOW_Int power = lo
Opamp block current
Internal Load
power = hi
–
–
–
–
8
1500
700
–
–
–
1700
900
–
–
–
µA
–
–
–
–
GBW
VDDA = 2.7 V
power = hi
SID272_I GBW_HI_Int
MHz Output is 0.25 V to
VDDA – 0.25 V
Datasheet
27
002-20072 Rev. *P
2023-05-02
Automotive PSoC™ 4: PSoC™ 4100S Plus
Based on Arm® Cortex®-M0+ CPU
Electrical specifications
Table 11
CTBm opamp specifications (continued)
Spec ID# Parameter
Description
Min
Typ
Max
Units Details/conditions
General opamp specs
for both internal and
external modes
SID281
SID282
VIN
Charge-pump on,
VDDA = 2.7 V
Charge-pump on,
VDDA = 2.7 V
VDDA = 2.7 V
power = hi,
Iload = 10 mA
power = hi,
Iload = 1 mA
power = med,
Iload = 1 mA
power = lo,
Iload = 0.1 mA
Offset voltage, trimmed
Offset voltage, trimmed
–0.05
–0.05
–
–
V
V
DDA – 0.2
DDA – 0.2
V
V
–
–
VCM
VOUT
VOUT_1
SID283
SID284
SID285
SID286
SID288
SID288A
0.5
0.2
0.2
0.2
–1.0
–
–
–
VDDA – 0.5
VDDA – 0.2
VDDA – 0.2
VDDA – 0.2
1.0
–
–
–
–
VOUT_2
VOUT_3
VOUT_4
VOS_TR
VOS_TR
–
–
0.5
1.4
mV High mode, input
0 V to VDDA – 0.2 V
–
Medium mode,
input 0 V to
VDDA – 0.2 V
SID288B
SID290
VOS_TR
Offset voltage, trimmed
–
–10
–
2
3
–
10
–
Low mode, input
0 V to VDDA – 0.2 V
VOS_DR_TR
VOS_DR_TR
Offset voltage drift,
trimmed
Offset voltage drift,
trimmed
Offset voltage drift,
trimmed
DC
µV/°C High mode
µV/°C Medium mode
Low mode
SID290A
10
10
80
–
–
SID290B
SID291
VOS_DR_TR
CMRR
70
–
dB Input is 0 V to
VDDA – 0.2 V,
Output is 0.2 V to
VDDA – 0.2 V
At 1 kHz, 10-mV ripple
70
85
–
VDDD = 3.6 V,
SID292
PSRR
high-power mode,
input is 0.2 V to
VDDA – 0.2 V
Noise
VN2
SID294
SID295
Input-referred, 1 kHz,
power = Hi
Input-referred, 10 kHz,
power = Hi
–
–
72
28
–
–
nV/
rtHz
3
VN3
VN4
Input and output
are at 0.2 V to
VDDA – 0.2 V
SID296
Input-referred, 100 kHz,
power = Hi
–
15
–
Input and output
are at 0.2 V to
VDDA – 0.2 V
Datasheet
28
002-20072 Rev. *P
2023-05-02
Automotive PSoC™ 4: PSoC™ 4100S Plus
Based on Arm® Cortex®-M0+ CPU
Electrical specifications
Table 11
CTBm opamp specifications (continued)
Spec ID# Parameter
Description
Min
Typ
Max
Units Details/conditions
SID297
SID298
SID299
SID299A
CLOAD
Stable up to max. load.
Performance specs at
50 pF.
–
–
125
pF
V/µs
µs
–
–
–
–
SLEW_RATE Cload = 50 pF,
Power = High,
6
–
–
–
–
–
25
–
VDDA = 2.7 V
T_OP_WAKE From disable to enable,
no external RC
dominating
Open Loop Gain
OL_GAIN
90
dB
COMP_
MODE
Comparator mode;
50 mV drive,
Trise = Tfall (approx.)
SID300
SID301
SID302
TPD1
TPD2
TPD3
Response time;
power = hi
–
–
–
150
500
–
–
–
ns
Input is 0.2 V to
V
DDA – 0.2 V
Response time;
power = med
Input is 0.2 V to
V
DDA – 0.2 V
Response time;
power = lo
2500
Input is 0.2 V to
V
–
–
DDA – 0.2 V
SID303
SID304
VHYST_OP
WUP_CTB
Hysteresis
Wake-up time from
Enabled to Usable
–
–
10
–
–
25
mV
µs
Deep Sleep Mode 2 is lowest current
Mode
range. Mode 1 has
higher GBW.
SID_DS_1 IDD_HI_M1
Mode 1, High current
–
–
–
–
1400
700
µA 25°C
25°C
SID_DS_2 IDD_MED_M1 Mode 1, Medium
current
SID_DS_3 IDD_LOW_M1 Mode 1, Low current
–
–
–
–
–
–
200
120
60
25°C
25°C
25°C
SID_DS_4 IDD_HI_M2
Mode 2, High current
SID_DS_5 IDD_MED_M2 Mode 2, Medium
current
SID_DS_6 IDD_LOW_M2 Mode 2, Low current
–
–
15
25°C
Datasheet
29
002-20072 Rev. *P
2023-05-02
Automotive PSoC™ 4: PSoC™ 4100S Plus
Based on Arm® Cortex®-M0+ CPU
Electrical specifications
Table 11
CTBm opamp specifications (continued)
Spec ID# Parameter
Description
Min
Typ
Max
Units Details/conditions
SID_DS_7 GBW_HI_M1
Mode 1, High current
–
4
–
MHz 20-pF load, no DC
load 0.2 V to
VDDA – 0.2 V
SID_DS_8 GBW_MED_M1 Mode 1, Medium
current
–
–
–
–
–
2
–
–
–
–
–
20-pF load, no DC
load 0.2 V to
VDDA – 0.2 V
SID_DS_9 GBW_LOW_M1 Mode 1, Low current
0.5
0.5
0.2
0.1
20-pF load, no DC
load 0.2 V to
VDDA – 0.2 V
20-pF load, no DC
load 0.2 V to
VDDA – 0.2 V
20-pF load, no DC
load 0.2 V to
VDDA – 0.2 V
20-pF load, no DC
load 0.2 V to
VDDA – 0.2 V
SID_DS_ GBW_HI_M2
10
Mode 2, High current
SID_DS_ GBW_MED_M2 Mode 2, Medium
11 current
SID_DS_ GBW_Low_M2 Mode 2, Low current
12
SID_DS_ VOS_HI_M1
13
SID_DS_ VOS_MED_M1 Mode 1, Medium
14 current
SID_DS_ VOS_LOW_M2 Mode 1, Low current
15
SID_DS_ VOS_HI_M2
16
SID_DS_ VOS_MED_M2 Mode 2, Medium
17 current
SID_DS_ VOS_LOW_M2 Mode 2, Low current
18
SID_DS_ IOUT_HI_M1
19
SID_DS_ IOUT_MED_M1 Mode 1, Medium
20 current
SID_DS_ IOUT_LOW_M1 Mode 1, Low current
21
SID_DS_ IOUT_HI_M2
22
SID_DS_ IOU_MED_M2 Mode 2, Medium
23 current
SID_DS_ IOU_LOW_M2 Mode 2, Low current
24
Mode 1, High current
–
–
–
–
–
–
–
–
–
–
–
–
5
5
–
–
–
–
–
–
–
–
–
–
–
–
mV With trim 25°C,
0.2 V to VDDA – 0.2 V
With trim 25°C,
0.2 V to VDDA – 0.2 V
With trim 25°C,
0.2 V to VDDA – 0.2 V
With trim 25°C,
0.2 V to VDDA – 0.2 V
With trim 25°C,
0.2 V to VDDA – 0.2 V
5
Mode 2, High current
5
5
5
With trim 25°C,
0.2 V to VDDA – 0.2 V
Mode 1, High current
10
10
4
Output is 0.5 V to
mA
VDDA – 0.5 V
Output is 0.5 V to
V
DDA – 0.5 V
Output is 0.5 V to
VDDA – 0.5 V
Mode 2, High current
1
–
–
–
1
0.5
Datasheet
30
002-20072 Rev. *P
2023-05-02
Automotive PSoC™ 4: PSoC™ 4100S Plus
Based on Arm® Cortex®-M0+ CPU
Electrical specifications
4.3.2
Comparator
Table 12
Comparator DC specifications
Spec ID# Parameter
Description
Min
Typ
Max
Units Details/conditions
SID84
SID85
SID86
SID87
SID247
VOFFSET1
VOFFSET2
VHYST
Input offset voltage,
Factory trim
Input offset voltage,
Custom trim
–
–
±10
mV
–
–
–
0
0
–
10
–
±4
35
–
Hysteresis when
enabled
Input common mode
voltage in normal mode
Input common mode
voltage in low power
mode
–
VICM1
VDDD – 0.1
VDDD
V
Modes 1 and 2
–
VICM2
–
SID247A
VICM3
Input common mode
voltage in ultra low
power mode
0
–
VDDD – 1.15
VDDD ≥ 2.2 V at
–40°C
SID88
CMRR
CMRR
ICMP1
ICMP2
ICMP3
ZCMP
Common mode
rejection ratio
Common mode
rejection ratio
Block current, normal
mode
Block current, low
power mode
Block current in ultra
low-power mode
DC Input impedance of
comparator
50
42
–
–
–
–
–
–
–
–
–
dB VDDD ≥ 2.7V
VDDD ≤ 2.7V
SID88A
SID89
400
100
6
µA
–
–
SID248
SID259
SID90
–
–
VDDD ≥ 2.2 V at
–40°C
35
–
MΩ
–
Table 13
Comparator AC specifications
Spec ID# Parameter
Description
Min
Typ
Max
Unit Details/conditions
SID91
TRESP1
Response time, normal
mode, 50 mV overdrive
–
38
110
ns
–
SID258
TRESP2
Response time, low
power mode, 50 mV
overdrive
Response time,
ultra-low power mode,
200 mV overdrive
–
70
200
15
–
SID92
TRESP3
–
2.3
µs VDDD ≥ 2.2 V at
–40°C
Datasheet
31
002-20072 Rev. *P
2023-05-02
Automotive PSoC™ 4: PSoC™ 4100S Plus
Based on Arm® Cortex®-M0+ CPU
Electrical specifications
4.3.3
Temperature sensor
Table 14
Temperature sensor specifications
Spec ID# Parameter
Description
Min
Typ
Max
Unit Details/conditions
SID93
TSENSACC
Temperature sensor
accuracy
–5
±1
5
°C –40 to +85°C
SID93A
TSENSACC
Temperature sensor
accuracy
–15
±1
+15
°C +85 to +150°C
4.3.4
SAR ADC
Table 15
SAR ADC specifications
Spec ID# Parameter
SAR ADC DC specifications
Description
Resolution
Min
Typ
Max
Unit Details/conditions
SID94
SID95
A_RES
–
–
–
–
12
16
bits
–
–
A_CHNLS_S Number of channels -
single ended
SID96
A-CHNKS_D Number of channels -
differential
–
–
4
Diff inputs use
neighboring I/O
SID97
SID98
A-MONO
A_GAINERR Gain error
Monotonicity
–
–
–
–
–
±0.1
Yes
%
With external
reference
SID99
A_OFFSET
Input offset voltage
–
–
2
mV Measured with 1 V
reference
SID100
SID101
A_ISAR
A_VINS
Current consumption
Input voltage range -
single ended
–
VSS
–
–
1
VDDA
mA
V
–
–
SID102
A_VIND
Input voltage range -
differential
VSS
–
VDDA
V
–
SID103
SID104
SID260
A_INRES
A_INCAP
VREFSAR
Input resistance
Input capacitance
Trimmed internal
reference to SAR
–
–
–
–
1.2
2.2
10
1.212
KΩ
pF
V
–
–
–
1.188
SAR ADC AC specifications
SID106
A_PSRR
Power supply rejection
ratio
Common mode
rejection ratio
70
66
–
–
–
–
dB
–
SID107
A_CMRR
dB Measured at 1 V
SID108
SID109
A_SAMP
A_SNR
Sample rate
Signal-to-noise and
distortion ratio (SINAD)
–
65
–
–
1
–
Msps –
dB FIN = 10 kHz
SID110
SID111
A_BW
A_INL
Input bandwidth
without aliasing
Integral non linearity.
VDD = 1.71 to 5.5, 1 Msps
–
–
–
A_samp/2 kHz
–
–1.7
2
LSB VREF = 1 to VDD
Datasheet
32
002-20072 Rev. *P
2023-05-02
Automotive PSoC™ 4: PSoC™ 4100S Plus
Based on Arm® Cortex®-M0+ CPU
Electrical specifications
Table 15
SAR ADC specifications (continued)
Spec ID# Parameter
Description
Min
Typ
Max
Unit Details/conditions
SID111A
SID111B
SID112
A_INL
A_INL
A_DNL
A_DNL
A_DNL
Integral non linearity.
VDDD = 1.71 to 3.6,
1 Msps
Integral non linearity.
VDD = 1.71 to 5.5,
500 ksps
Differential non
linearity.
VDD = 1.71 to 5.5, 1 Msps
Differential non
linearity.
VDD = 1.71 to 3.6, 1 Msps
Differential non
linearity.
VDD = 1.71 to 5.5,
500 ksps
–1.5
–
1.7
LSB VREF = 1.71 to VDD
–1.5
–1
–
–
1.7
2.2
2
LSB VREF = 1 to VDD
LSB VREF = 1 to VDD
LSB VREF = 1.71 to VDD
LSB VREF = 1 to VDD
–
–
SID112A
SID112B
–1
–1
2.2
–
–
–
–
SID113
SID261
A_THD
Total harmonic
distortion
–65
100
dB Fin = 10 kHz
FSARINTREF SAR operating speed
without external
ksps 12-bit resolution
reference bypass
4.3.5
CSD and IDAC
Table 16
CSD and IDAC specifications
Spec ID#
Parameter
Description
Min Typ
Max
Unit
Details/conditions
SYS.PER#3
VDD_RIPPLE
Max allowed ripple
on power supply,
DC to 10 MHz
–
–
±50
mV VDD > 2 V (with ripple),
25°C TA,
Sensitivity = 0.1 pF
SYS.PER#16
VDD_RIPPLE_1.8 Max allowed ripple
on power supply,
–
–
–
±25
mV VDD >1.75V(withripple),
25°C TA,
DC to 10 MHz
Parasitic Capacitance
(CP) < 20 pF,
Sensitivity ≥ 0.4 pF
SID.CSD.BLK
SID.CSD#15
ICSD
Maximum block
current
–
4000
µA Maximum block current
for both IDACs in
dynamic (switching)
mode including
comparators, buffer,
and reference
generator
VREF
Voltage reference
for CSD and
0.6 1.2 VDDA – 0.6
V
V
VDDA – 0.06 or 4.4,
whichever is lower
Comparator
SID.CSD#15A VREF_EXT
External Voltage
reference for CSD
and Comparator
0.6
–
–
–
VDDA – 0.6
1750
VDDA – 0.06 or 4.4,
whichever is lower
SID.CSD#16
IDAC1IDD
IDAC1 (7-bits) block
current
µA
–
Datasheet
33
002-20072 Rev. *P
2023-05-02
Automotive PSoC™ 4: PSoC™ 4100S Plus
Based on Arm® Cortex®-M0+ CPU
Electrical specifications
Table 16
Spec ID#
SID.CSD#17
CSD and IDAC specifications (continued)
Parameter
IDAC2IDD
Description
IDAC2 (7-bits) block
current
Min Typ
Max
1750
Unit
µA
Details/conditions
–
–
–
–
–
SID308
VCSD
Voltage range of
operation
1.71
0.6
5.5
V
V
1.8 V ± 5% or 1.8 V to
5.5 V
VDDA – 0.06 or 4.4,
whichever is lower
SID308A
VCOMPIDAC
Voltage
V
DDA – 0.6
compliance range
of IDAC
SID309
SID310
IDAC1DNL
IDAC1INL
DNL
INL
–1
–2
–
–
1
2
LSB
–
LSB INL is ±5.5 LSB for
V
DDA < 2 V
SID311
SID312
IDAC2DNL
IDAC2INL
DNL
INL
–1
–2
–
–
1
2
LSB
–
LSB INL is ±5.5 LSB for
VDDA < 2 V
SID313
SNR
Ratio of counts of
finger to noise.
Guaranteed by
characterization
5
–
–
Ratio Capacitance range of 5
to 35 pF, 0.1-pF
sensitivity.Allusecases.
VDDA > 2 V.
SID314
IDAC1CRT1
IDAC1CRT2
IDAC1CRT3
IDAC1CRT12
IDAC1CRT22
Output current of
IDAC1 (7 bits) in low
range
Output current of
IDAC1(7 bits) in
medium range
Output current of
IDAC1(7 bits) in
high range
Output current of
IDAC1 (7 bits) in low
range, 2X mode
4.2
34
275
8
–
–
–
–
–
5.4
41
µA LSB = 37.5 nA typ
µA LSB = 300 nA typ
µA LSB = 2.4 µA typ
µA LSB = 75 nA typ
µA LSB = 600 nA typ.
SID314A
SID314B
SID314C
SID314D
330
10.5
82
Output current of
IDAC1 (7 bits) in
medium range, 2X
mode
69
SID314E
IDAC1CRT32
Output current of
IDAC1 (7 bits) in
high range, 2X
mode
540
–
660
µA LSB = 4.8 µA typ
SID315
IDAC2CRT1
IDAC2CRT2
IDAC2CRT3
IDAC2CRT12
Output current of
IDAC2 (7 bits) in low
range
Output current of
IDAC2 (7 bits) in
medium range
Output current of
IDAC2 (7 bits) in
high range
Output current of
IDAC2 (7 bits) in low
range, 2X mode
4.2
34
275
8
–
–
–
–
5.4
41
µA LSB = 37.5 nA typ
µA LSB = 300 nA typ
µA LSB = 2.4 µA typ
µA LSB = 75 nA typ
SID315A
SID315B
SID315C
330
10.5
Datasheet
34
002-20072 Rev. *P
2023-05-02
Automotive PSoC™ 4: PSoC™ 4100S Plus
Based on Arm® Cortex®-M0+ CPU
Electrical specifications
Table 16
Spec ID#
CSD and IDAC specifications (continued)
Parameter
Description
Min Typ
Max
Unit
Details/conditions
SID315D
IDAC2CRT22
Output current of
IDAC2 (7 bits) in
medium range, 2X
mode
69
–
82
µA LSB = 600 nA typ
SID315E
IDAC2CRT32
Output current of
IDAC2 (7 bits) in
high range, 2X
mode
540
–
660
µA LSB = 4.8 µA typ
SID315F
SID315G
SID315H
SID320
IDAC3CRT13
IDAC3CRT23
IDAC3CRT33
IDACOFFSET
IDACGAIN
Output current of
IDAC in 8-bit mode
in low range
Output current of
IDAC in 8-bit mode
in medium range
Output current of
IDAC in 8-bit mode
in high range
8
69
540
–
–
–
–
–
10.5
82
µA LSB = 37.5 nA typ
µA LSB = 300 nA typ
µA LSB = 2.4 µA typ
660
1
All zeroes input
LSB Polarity set by Source or
Sink. Offset is 2 LSBs for
37.5 nA/LSB mode
SID321
SID322
Full-scale error less
offset
–
–
–
–
±10
9.2
%
–
IDACMISMATCH1 Mismatch between
IDAC1 and IDAC2 in
LSB LSB = 37.5 nA typ
LSB LSB = 300 nA typ
LSB LSB = 2.4 µA typ
Low mode
SID322A
SID322B
IDACMISMATCH2 Mismatch between
IDAC1 and IDAC2 in
–
–
–
–
5.6
6.8
Medium mode
IDACMISMATCH3 Mismatch between
IDAC1 and IDAC2 in
High mode
SID323
SID324
SID325
IDACSET8
IDACSET7
CMOD
Settling time to 0.5
LSB for 8-bit IDAC
Settling time to 0.5
LSB for 7-bit IDAC
External modulator
capacitor.
–
–
–
–
–
5
5
–
µs Full-scale transition. No
external load
µs Full-scale transition. No
external load
nF 5-V rating, X7R or NP0
cap
2.2
Datasheet
35
002-20072 Rev. *P
2023-05-02
Automotive PSoC™ 4: PSoC™ 4100S Plus
Based on Arm® Cortex®-M0+ CPU
Electrical specifications
4.3.6
10-bit CAPSENSE™ ADC
Table 17
10-bit CAPSENSE™ ADC specifications
Spec ID# Parameter
Description
Resolution
Min
–
Typ
–
Max
10
Unit Details/conditions
SIDA94
A_RES
bits Auto-zeroing is
required every
millisecond
SIDA95
A_CHNLS_S Number of channels -
single ended
–
–
16
Defined by AMUX
Bus
SIDA97
SIDA98
A-MONO
A_GAINERR Gain error
Monotonicity
–
–
–
–
–
±3
Yes
%
–
In VREF (2.4 V) mode
with VDDA bypass
capacitance of
10 µF
SIDA99
A_OFFSET
A_VINS
Input offset voltage
–
–
–
±18
mV In VREF (2.4 V) mode
with VDDA bypass
capacitance of
10 µF
SIDA101
Input voltage range -
single ended
VSSA
VDDA
V
–
SIDA103
SIDA104
SIDA106
A_INRES
A_INCAP
A_PSRR
Input resistance
Input capacitance
Power supply rejection
ratio
–
–
–
2.2
20
60
–
–
–
KΩ
pF
–
–
dB In VREF (2.4 V) mode
with VDDA bypass
capacitance of
10 µF
SIDA107
SIDA108
A_TACQ
Sample acquisition
time
–
–
1
–
–
µs
–
A_CONV8
Conversion time for
8-bit resolution at
conversion rate =
Fhclk/(2^(N+2)).
Clock frequency =
48 MHz.
21.3
µs Does not include
acquisition time.
Equivalent to
44.8 ksps including
acquisition time.
SIDA108A A_CONV10
Conversion time for
10-bit resolution at
conversion rate =
Fhclk/(2^(N+2)).
Clock frequency =
48 MHz.
–
–
–
85.3
µs Does not include
acquisition time.
Equivalent to
11.6 ksps including
acquisition time.
SIDA109
A_SND
Signal-to-noise and
Distortion ratio (SINAD)
61
–
dB With 10-Hz input
sine wave, external
2.4-V reference,
VREF (2.4 V) mode
SIDA110
SIDA111
SIDA112
A_BW
A_INL
A_DNL
Input bandwidth
without aliasing
Integral Non Linearity.
1 ksps
Differential Non
Linearity. 1 ksps
–
–
–
–
–
–
22.4
2
KHz 8-bit resolution
LSB VREF = 2.4 V or
greater
1
–
Datasheet
36
002-20072 Rev. *P
2023-05-02
Automotive PSoC™ 4: PSoC™ 4100S Plus
Based on Arm® Cortex®-M0+ CPU
Electrical specifications
4.4
Digital peripherals
4.4.1
Table 18
Timer counter pulse-width modulator (TCPWM)
TCPWM specifications
Spec ID
Parameter
Description
Block current consumption
at 3 MHz
Block current consumption
at 12 MHz
Min
–
Typ Max Units Details/conditions
SID.TCPWM.1 ITCPWM1
SID.TCPWM.2 ITCPWM2
SID.TCPWM.2A ITCPWM3
–
–
–
–
45
155
650
Fc
µA
All modes (TCPWM)
All modes (TCPWM)
All modes (TCPWM)
–
–
–
Block current consumption
at 48 MHz
SID.TCPWM.3 TCPWMFREQ Operating frequency
MHz
ns
Fc max = CLK_SYS
Maximum = 48 MHz
SID.TCPWM.4 TPWMENEXT Input trigger pulse width
2/Fc
–
–
–
–
For all trigger
events[5]
SID.TCPWM.5 TPWMEXT
Output trigger pulse widths 2/Fc
Minimum possible
width of Overflow,
Underflow, and CC
(Counter equals
Compare value)
outputs
SID.TCPWM.5A TCRES
SID.TCPWM.5B PWMRES
SID.TCPWM.5C QRES
Resolution of counter
PWM resolution
1/Fc
1/Fc
1/Fc
–
–
–
–
–
–
Minimum time
between
successive counts
Minimum pulse
width of PWM
Output
Minimum pulse
width between
Quadrature phase
inputs
Quadrature inputs
resolution
Datasheet
37
002-20072 Rev. *P
2023-05-02
Automotive PSoC™ 4: PSoC™ 4100S Plus
Based on Arm® Cortex®-M0+ CPU
Electrical specifications
4.4.2
I2C
Table 19
Fixed I2C DC specifications[5]
Spec ID# Parameter
Description
Min
Typ
Max
Unit Details/conditions
–
SID149
II2C1
Block current
consumption at
100 kHz
–
–
50
µA
–
SID150
II2C2
Block current
consumption at
400 kHz
–
–
135
–
–
SID151
SID152
II2C3
II2C4
Block current
–
–
–
1
310
–
consumption at 1 Mbps
I2C enabled in Deep
Sleep mode
Table 20
Fixed I2C AC specifications[5]
Description
Bit rate
Spec ID# Parameter
SID153
Min
Typ
Max
Unit Details/conditions
FI2C1
–
–
1
Msps –
Note
5. Guaranteed by characterization.
Datasheet
38
002-20072 Rev. *P
2023-05-02
Automotive PSoC™ 4: PSoC™ 4100S Plus
Based on Arm® Cortex®-M0+ CPU
Electrical specifications
4.4.3
SPI
Table 21
SPI DC specifications[6]
Spec ID# Parameter
Description
Min
Typ
Max
Unit Details/conditions
SID163
SID164
SID165
ISPI1
ISPI2
ISPI3
Block current
–
–
360
µA
–
–
–
consumption at 1 Mbps
Block current
consumption at 4 Mbps
Block current
consumption at 8 Mbps
–
–
–
–
560
600
Table 22
SPI AC specifications[6]
Spec ID# Parameter
SID166 FSPI
Description
Min
–
Typ
–
Max
8
Unit Details/conditions
SPI Operating
frequency (Master; 6X
Oversampling)
MHz
–
Fixed SPI Master mode AC specifications
SID167
SID168
SID169
TDMO
MOSI Valid after SClock
driving edge
MISO Valid before
SClock capturing edge
Previous MOSI data
hold time
–
20
0
–
–
–
15
–
ns
–
TDSI
Full clock, late
MISO sampling
Referred to Slave
capturing edge
THMO
–
Fixed SPI Slave mode AC specifications
SID170
SID171
SID171A
TDMI
MOSI Valid before
40
–
–
–
–
–
42 + (3 × Tcpu)
48
ns
–
Sclock Capturing edge
TDSO
MISO Valid after Sclock
driving edge
MISO Valid after Sclock
driving edge in Ext. Clk
mode
TCPU = 1/FCPU
–
TDSO_EXT
–
SID172
THSO
Previous MISO data
hold time
0
–
–
–
–
–
–
SID172A
TSSELSSCK SSEL Valid to first SCK
Valid edge
100
ns
Datasheet
39
002-20072 Rev. *P
2023-05-02
Automotive PSoC™ 4: PSoC™ 4100S Plus
Based on Arm® Cortex®-M0+ CPU
Electrical specifications
4.4.4
UART
UART DC specifications[6]
Table 23
Spec ID# Parameter
Description
Min
Typ
Max
Unit Details/conditions
SID160
IUART1
Block current
consumption
at 100 Kbps
–
–
55
µA
–
SID161
IUART2
Block current
consumption
at 1000 Kbps
–
–
312
µA
–
Table 24
UART AC specifications[6]
Description
Bit rate
Spec ID# Parameter
SID162
Min
Typ
Max
Unit Details/conditions
FUART
–
–
1
Mbps –
4.4.5
LCD Direct Drive
LCD Direct Drive DC specifications[6]
Table 25
Spec ID# Parameter
Description
Min
Typ
Max
Unit Details/conditions
SID154
ILCDLOW
Operating current in
low power mode
–
5
–
µA 16 4 small
segment disp. at
50 Hz
SID155
CLCDCAP
LCD capacitance per
segment/common
driver
–
500
5000
pF
–
SID156
SID157
SID158
LCDOFFSET
ILCDOP1
Long-term segment
offset
LCD system operating
current Vbias = 5 V
LCD system operating
current Vbias = 3.3 V
–
–
–
20
2
–
–
–
mV
–
mA 32 4 segments at
50 Hz, 25°C
32 4 segments at
50 Hz, 25°C
ILCDOP2
2
Table 26
LCD Direct Drive AC specifications[6]
Description
LCD frame rate
Spec ID# Parameter
SID159
Min
Typ
Max
Unit Details/conditions
FLCD
10
50
150
Hz
–
Note
6. Guaranteed by characterization.
Datasheet
40
002-20072 Rev. *P
2023-05-02
Automotive PSoC™ 4: PSoC™ 4100S Plus
Based on Arm® Cortex®-M0+ CPU
Electrical specifications
4.5
Memory
4.5.1
Flash
Table 27
Flash DC specifications
Spec ID# Parameter
Description
Min
Typ
Max
Unit Details/conditions
SID173
VPE
Erase and program
voltage
1.71
–
5.5
V
–
Table 28
Flash AC specifications
Spec ID#
SID174
Parameter
TROWWRITE
Description
Row (block) write time
(erase and program)
Row erase time
Row program time after
erase
Bulk erase time (64 KB)
Total device program
time
Min Typ Max Unit
Details/conditions
Row (block) = 256 bytes
[7]
–
–
20
ms
[7]
SID175
SID176
TROWERASE
–
–
–
–
16
4
–
–
[7]
TROWPROGRAM
[7]
SID178
SID180[7] TDEVPROG
TBULKERASE
–
–
–
–
35
7
–
[7]
Seconds –
SID181[7] FEND
SID182[7] FRET
Flash endurance
100K
20
–
–
–
–
Cycles
Years
–
–
Flash retention.
TA 55°C,
100K P/E cycles
Flash retention.
TA 85°C,
10K P/E cycles
SID182A[7] FRET
10
10
–
–
–
–
–
SID182B
FRETQ
Flash retention.
TA 105°C,
Guaranteed by design
10K P/E cycles with no
more than 3 years at
TA 85°C
SID256
SID257
TWS48
TWS24
Number of Wait states
at 48 MHz
Number of Wait states
at 24 MHz
2
1
–
–
–
–
CPU execution from
Flash
CPU execution from
Flash
Note
7. It can take as much as 20 milliseconds to write to Flash. During this time the device should not be Reset, or Flash operations will be
interrupted and cannot be relied on to have completed. Reset sources include the XRES pin, software resets, CPU lockup states and
privilege violations, improper power supply levels, and watchdogs. Make certain that these are not inadvertently activated.
Datasheet
41
002-20072 Rev. *P
2023-05-02
Automotive PSoC™ 4: PSoC™ 4100S Plus
Based on Arm® Cortex®-M0+ CPU
Electrical specifications
4.6
System resources
4.6.1
Power-on reset (POR)
Table 29
Power-on reset (PRES)
Spec ID# Parameter
SID.CLK#6 SR_POWER Power supply slew rate
Description
Min
1[8]
Typ
–
Max
67
Units Details/conditions
V/ms On power-up and
power-down
SID185[9] VRISEIPOR
SID186[9] VFALLIPOR
Rising trip voltage
Falling trip voltage
0.80
0.70
–
–
1.5
1.4
V
–
–
4.6.2
Brown-out detect (BOD)
Table 30
Brown-out detect (BOD) for VCCD
Spec ID# Parameter
Description
BOD trip voltage in
active and sleep modes
BOD trip voltage in
Deep Sleep
Min
1.48
Typ
–
Max
1.62
Unit Details/conditions
SID190[9] VFALLPPOR
V
–
SID192[9] VFALLDPSLP
1.11
–
1.5
–
4.6.3
SWD interface
Table 31
SWD interface specifications
Spec ID#
SID213
Parameter
F_SWDCLK1
Description
3.3 V VDD 5.5 V
Min
–
Typ
–
Max
14
Unit Details/conditions
MHz SWDCLK ≤ 1/3 CPU
clock frequency
SID214
F_SWDCLK2
1.71 V VDD 3.3 V
–
–
7
SWDCLK ≤ 1/3 CPU
clock frequency
SID215[9] T_SWDI_SETUP
SID216[9] T_SWDI_HOLD
SID217[9] T_SWDO_VALID
SID217A[9] T_SWDO_HOLD
T = 1/f SWDCLK
T = 1/f SWDCLK
T = 1/f SWDCLK
T = 1/f SWDCLK
0.25 × T
0.25 × T
–
–
–
–
–
ns
–
–
–
–
–
0.5 × T
–
–
1
Notes
8. If minimum ramp rate cannot be met, XRES should be asserted during voltage ramp (1.5 V > VDDD > 1.0 V for ramp-down or until voltage
is stable for ramp-up). Note that a glitch on the I2C bus could occur during voltage ramp in this case.
9. Guaranteed by characterization.
Datasheet
42
002-20072 Rev. *P
2023-05-02
Automotive PSoC™ 4: PSoC™ 4100S Plus
Based on Arm® Cortex®-M0+ CPU
Electrical specifications
4.6.4
Internal main oscillator
Table 32
IMO DC specifications
(Guaranteed by design)
Spec ID# Parameter
Description
Min
Typ
Max
Unit Details/conditions
SID218
IIMO1
IMO operating current
at 48 MHz
–
–
250
µA
–
SID219
IIMO2
IMO operating current
at 24 MHz
–
–
180
µA
–
Table 33
IMO AC specifications
Spec ID# Parameter
Description
Min
Typ
Max
Unit Details/conditions
SID223
SID223A
SID333
FIMOTOL1
FIMOTOL1A
IMOWCO
Frequency variation at
24, 32, and 48 MHz
(trimmed)
Frequency variation at
24, 32, and 48 MHz
(trimmed)
–
–
±2
%
%
%
–40°C ≤ TA ≤ 105°C
–
–
–
–
±2.5
–40°C ≤ TA ≤ 125°C
All IMO settings
±0.25
IMO variation in
WCO-locked DPLL
mode
SID226
SID228
TSTARTIMO
TJITRMSIMO2 RMS jitter at 24 MHz
IMO startup time
–
–
–
145
7
–
µs
ps
–
–
Datasheet
43
002-20072 Rev. *P
2023-05-02
Automotive PSoC™ 4: PSoC™ 4100S Plus
Based on Arm® Cortex®-M0+ CPU
Electrical specifications
4.6.5
Internal low-speed oscillator
Table 34
ILO DC specifications
(Guaranteed by Design)
Spec ID# Parameter
Description
ILO operating current
Min
–
Typ
0.3
Max
1.05
Unit Details/conditions
µA
SID231
IILO1
–
Table 35
ILO AC specifications
Spec ID# Parameter
SID234[10] TSTARTILO1
SID236[10] TILODUTY
Description
ILO startup time
ILO duty cycle
Min
–
40
20
Typ
–
50
40
Max
2
60
80
Unit Details/conditions
ms
%
–
–
–
SID237
FILOTRIM1
ILO frequency range
kHz
4.6.6
Watch crystal oscillator (WCO)
Table 36
WCO specifications
Spec ID# Parameter
Description
Crystal frequency
Frequency tolerance
Min
–
–
Typ
32.768
50
Max
–
250
Unit Details/conditions
kHz
ppm With 20-ppm
crystal
SID398
SID399
FWCO
FTOL
–
SID400
ESR
Equivalent series
resistance
–
50
–
kΩ
–
SID401
SID402
SID403
PD
TSTART
CL
Drive Level
Startup time
Crystal Load
Capacitance
–
–
6
–
–
–
1
500
12.5
µW
ms
pF
–
–
–
–
–
SID404
SID405
C0
Crystal Shunt
Capacitance
Operating Current (high
power mode)
–
–
1.35
–
–
8
pF
µA
IWCO1
4.6.7
External clock
Table 37
External clock specifications
Spec ID# Parameter
Description
Min
0
Typ
–
Max
48
Unit Details/conditions
MHz –40°C ≤ TA ≤ 85°C
SID305[11] ExtClkFreq External clock input
frequency
SID306[11] ExtClkDuty Duty cycle; measured at
VDD/2
45
–
55
%
–40°C ≤ TA ≤ 85°C
Notes
10.Guaranteed by characterization.
11.Guaranteed by design.
Datasheet
44
002-20072 Rev. *P
2023-05-02
Automotive PSoC™ 4: PSoC™ 4100S Plus
Based on Arm® Cortex®-M0+ CPU
Electrical specifications
4.6.8
External crystal oscillator and PLL
Table 38
External crystal oscillator (ECO) specifications
Spec ID# Parameter
Description
External clock input
frequency
Min
–
Typ
–
Max
1.5
Unit Details/conditions
SID316[12] IECO1
mA
–
SID317[12] FECO
Crystal frequency range
4
–
33
MHz
–
Table 39
PLL specifications
Spec ID# Parameter
Description
Min
–
–
1
1
Typ
530
300
–
Max
610
405
48
Unit Details/conditions
SID410
SID411
SID412
SID413
IDD_PLL_48 In = 3 MHz, Out = 48 MHz
IDD_PLL_24 In = 3 MHz, Out = 24 MHz
Fpllin
µA
µA
–
–
–
–
PLL input frequency
MHz
MHz
Fpllint
PLL intermediate
frequency; prescaler
out
–
3
SID414
SID415
Fpllvco
Divvco
VCO output frequency
before post-divide
VCO Output
post-divider range; PLL
output frequency is
Fpplvco/Divvco
22.5
1
–
–
104
8
MHz
–
–
SID416
SID417
Plllocktime Lock time at startup
–
–
–
–
250
150
µs
–
Jperiod_1
Period jitter for
VCO ≥ 67 MHz
ps Guaranteed by
design
–40°C ≤ TA ≤ 85°C
SID416A
Jperiod_2
Period jitter for
VCO ≤ 67 MHz
–
–
200
ps Guaranteed by
design
–40°C ≤ TA ≤ 85°C
Datasheet
45
002-20072 Rev. *P
2023-05-02
Automotive PSoC™ 4: PSoC™ 4100S Plus
Based on Arm® Cortex®-M0+ CPU
Electrical specifications
4.6.9
System clock
Table 40
Block specs
Spec ID# Parameter
Description
Min
3
Typ
–
Max
4
Unit Details/conditions
Periods –
SID262[12] TCLKSWITCH System clock source
switching time
4.6.10
Smart I/O
Table 41
Smart I/O pass-through time (Delay in Bypass Mode)
Spec ID#
Parameter
Description
Min
Typ
Max
Unit Details/conditions
SID252
PRG_BYPASS Max delay added by
Smart I/O in bypass
mode
–
–
1.6
ns
–
4.6.11
CAN
Table 42
CAN specifications
Spec ID# Parameter
Description
Min
–
Typ
–
Max
200
Unit Details/conditions
µA
SID420
IDD_CAN
Block current
consumption
CAN Bit rate
–
SID421
CAN_bits
–
–
1
Mbps Min 8-MHz clock
Note
12.Guaranteed by characterization.
Datasheet
46
002-20072 Rev. *P
2023-05-02
5
Ordering information
Table 43 lists the marketing part numbers (MPNs) for the PSoC™ 4100S Plus devices[13]
.
Table 43 Ordering information
Operating
temperaure
MPN
Features
Packages
CY8C4126AZA-S455
CY8C4146AZA-S245
CY8C4146AZA-S255
CY8C4146AZA-S265
CY8C4146AZA-S275
CY8C4146AZA-S455
CY8C4127AZA-S445
CY8C4127AZA-S455
CY8C4147AZA-S245
CY8C4147AZA-S255
CY8C4147AZA-S265
CY8C4147AZA-S275
CY8C4147AZA-S285
CY8C4147AZA-S295
CY8C4147AZA-S445
CY8C4147AZA-S455
CY8C4147AZA-S465
CY8C4147AZA-S475
CY8C4126AZS-S455
CY8C4146AZS-S245
CY8C4146AZS-S255
CY8C4146AZS-S265
CY8C4146AZS-S275
CY8C4146AZS-S455
CY8C4127AZS-S445
24
48
48
48
48
48
24
24
48
48
48
48
48
48
48
48
48
48
24
48
48
48
48
48
24
64
64
8
8
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
2
-
X
-
X
806 Ksps
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
-
-
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1000 Ksps
1000 Ksps
1000 Ksps
1000 Ksps
1000 Ksps
806 Ksps
64
8
-
-
X
-
-
-
64
8
-
X
X
X
-
-
-
64
8
-
X
X
X
X
-
-
-
64
8
2
2
2
-
-
-
128
128
128
128
128
128
128
128
128
128
128
128
64
16
16
16
16
16
16
16
16
16
16
16
16
8
-
-
X
-
806 Ksps
-
-
1000 Ksps
1000 Ksps
1000 Ksps
1000 Ksps
1000 Ksps
1000 Ksps
1000 Ksps
1000 Ksps
1000 Ksps
1000 Ksps
806 Ksps
-
-
-
-
X
-
-
-
-
X
X
-
-
-
-
X
X
X
X
X
X
X
X
-
-
-
-
1
1
-
-
-
X
-
-
2
2
2
2
2
-
-
X
-
-
-
1
1
-
-
X
X
-
-
X
X
X
X
X
X
X
64
8
1000 Ksps
1000 Ksps
1000 Ksps
1000 Ksps
1000 Ksps
806 Ksps
-
-
64
8
-
-
X
-
-
-
64
8
-
X
X
X
-
-
-
64
8
-
X
X
X
-
-
64
8
2
2
-
-
128
16
-
-
Note
13. Contact Infineon Support for the availability of Grade-E devices.
14. Alternate fab available.
Table 43
Ordering information (continued)
Operating
MPN
Features
Packages
temperaure
CY8C4127AZS-S455
CY8C4147AZS-S245
CY8C4147AZS-S255
24
48
48
48
48
48
48
48
48
48
48
24
48
48
48
48
48
24
24
48
48
48
48
48
48
48
48
48
48
24
128
128
128
128
128
128
128
128
128
128
128
64
16
16
16
16
16
16
16
16
16
16
16
8
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
2
-
X
-
X
806 Ksps
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
5
5
5
5
5
5
5
5
5
5
5
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
-
-
54
54
54
54
54
54
54
54
54
54
54
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
X
X
X
X
X
X
X
X
X
X
X
-
-
-
X
X
X
X
X
X
X
X
X
X
X
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1000 Ksps
1000 Ksps
1000 Ksps
1000 Ksps
1000 Ksps
1000 Ksps
1000 Ksps
1000 Ksps
1000 Ksps
1000 Ksps
806 Ksps
-
-
X
-
-
-
-
[14]
CY8C4147AZS-S265
CY8C4147AZS-S275
-
X
X
-
-
-
-
-
X
X
X
X
X
X
X
X
-
-
-
-
[14]
CY8C4147AZS-S285
CY8C4147AZS-S295
CY8C4147AZS-S445
CY8C4147AZS-S455
CY8C4147AZS-S465
CY8C4147AZS-S475
CY8C4126LQA-S453
CY8C4146LQA-S243
CY8C4146LQA-S253
CY8C4146LQA-S263
CY8C4146LQA-S273
CY8C4146LQA-S453
CY8C4127LQA-S443
CY8C4127LQA-S453
CY8C4147LQA-S243
CY8C4147LQA-S253
CY8C4147LQA-S263
CY8C4147LQA-S273
CY8C4147LQA-S283
CY8C4147LQA-S293
CY8C4147LQA-S443
CY8C4147LQA-S453
CY8C4147LQA-S463
CY8C4147LQA-S473
CY8C4126LQS-S453
-
1
1
-
-
-
-
X
-
-
-
2
2
2
2
2
-
-
-
X
-
-
-
-
1
1
-
-
-
X
X
-
-
-
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
-
64
8
1000 Ksps
1000 Ksps
1000 Ksps
1000 Ksps
1000 Ksps
806 Ksps
-
-
-
64
8
-
-
X
-
-
-
-
64
8
-
X
X
X
-
-
-
-
64
8
-
X
X
X
X
-
-
-
-
64
8
2
2
2
-
-
-
-
128
128
128
128
128
128
128
128
128
128
128
128
64
16
16
16
16
16
16
16
16
16
16
16
16
8
-
-
-
X
-
806 Ksps
-
-
-
1000 Ksps
1000 Ksps
1000 Ksps
1000 Ksps
1000 Ksps
1000 Ksps
1000 Ksps
1000 Ksps
1000 Ksps
1000 Ksps
806 Ksps
-
-
-
-
-
X
-
-
-
-
-
X
X
-
-
-
-
-
X
X
X
X
X
X
X
X
-
-
-
-
1
1
-
-
-
-
X
-
-
-
2
2
2
2
2
-
-
X
-
-
-
-
1
1
-
-
-
X
X
-
-
-
X
Note
13. Contact Infineon Support for the availability of Grade-E devices.
14. Alternate fab available.
Table 43
Ordering information (continued)
Operating
MPN
Features
Packages
temperaure
CY8C4146LQS-S243
CY8C4146LQS-S253
CY8C4146LQS-S263
CY8C4146LQS-S273
CY8C4146LQS-S453
CY8C4127LQS-S443
CY8C4127LQS-S453
CY8C4147LQS-S243
CY8C4147LQS-S253
CY8C4147LQS-S263
CY8C4147LQS-S273
48
48
48
48
48
24
24
48
48
48
48
48
48
48
48
48
48
24
48
48
48
48
48
24
24
48
48
48
48
48
64
64
8
8
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1000 Ksps
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
-
-
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
34
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
-
-
-
X
-
1000 Ksps
1000 Ksps
1000 Ksps
1000 Ksps
806 Ksps
64
8
-
X
X
X
-
-
-
64
8
-
X
X
X
X
-
-
-
64
8
2
2
2
-
-
-
128
128
128
128
128
128
128
128
128
128
128
128
64
16
16
16
16
16
16
16
16
16
16
16
16
8
-
-
X
-
806 Ksps
-
-
1000 Ksps
1000 Ksps
1000 Ksps
1000 Ksps
1000 Ksps
1000 Ksps
1000 Ksps
1000 Ksps
1000 Ksps
1000 Ksps
806 Ksps
-
-
-
-
X
-
-
-
-
X
X
-
-
-
-
X
X
X
X
X
X
X
X
-
-
-
[14]
CY8C4147LQS-S283
CY8C4147LQS-S293
CY8C4147LQS-S443
CY8C4147LQS-S453
CY8C4147LQS-S463
CY8C4147LQS-S473
CY8C4126LQE-S453
CY8C4146LQE-S243
CY8C4146LQE-S253
CY8C4146LQE-S263
CY8C4146LQE-S273
CY8C4146LQE-S453
CY8C4127LQE-S443
CY8C4127LQE-S453
CY8C4147LQE-S243
CY8C4147LQE-S253
CY8C4147LQE-S263
CY8C4147LQE-S273
-
1
1
-
-
-
X
-
-
2
2
2
2
2
-
-
X
-
-
-
1
1
-
-
X
X
-
-
X
X
X
X
X
X
X
X
X
X
X
X
X
64
8
1000 Ksps
1000 Ksps
1000 Ksps
1000 Ksps
1000 Ksps
806 Ksps
-
-
64
8
-
-
X
-
-
-
64
8
-
X
X
X
-
-
-
64
8
-
X
X
X
X
-
-
-
64
8
2
2
2
-
-
-
128
128
128
128
128
128
128
16
16
16
16
16
16
16
-
-
X
-
806 Ksps
-
-
1000 Ksps
1000 Ksps
1000 Ksps
1000 Ksps
1000 Ksps
-
-
-
-
X
-
-
-
-
X
X
-
-
-
-
X
X
-
-
[14]
CY8C4147LQE-S283
-
1
-
Note
13. Contact Infineon Support for the availability of Grade-E devices.
14. Alternate fab available.
Table 43
Ordering information (continued)
Operating
MPN
Features
Packages
temperaure
CY8C4147LQE-S293
48
48
48
48
48
24
48
48
48
48
48
24
24
48
48
48
48
48
48
48
48
48
48
24
48
48
48
48
48
24
128
128
128
128
128
64
16
16
16
16
16
8
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
2
2
2
2
2
-
X
-
X
X
X
X
X
X
-
1000 Ksps
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
4
4
4
4
4
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
24
24
24
24
24
24
-
1
-
34
34
34
34
34
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
X
X
X
X
X
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
-
[14]
CY8C4147LQE-S443
CY8C4147LQE-S453
CY8C4147LQE-S463
CY8C4147LQE-S473
CY8C4126AZE-S455
CY8C4146AZE-S245
CY8C4146AZE-S255
CY8C4146AZE-S265
CY8C4146AZE-S275
CY8C4146AZE-S455
CY8C4127AZE-S445
CY8C4127AZE-S455
CY8C4147AZE-S245
CY8C4147AZE-S255
CY8C4147AZE-S265
CY8C4147AZE-S275
CY8C4147AZE-S285
1000 Ksps
1000 Ksps
1000 Ksps
1000 Ksps
806 Ksps
X
-
-
-
-
-
1
1
-
-
-
-
X
X
-
-
-
-
-
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
-
-
64
8
1000 Ksps
1000 Ksps
1000 Ksps
1000 Ksps
1000 Ksps
806 Ksps
-
-
-
-
64
8
-
-
X
-
-
-
-
-
-
64
8
-
X
X
X
-
-
-
-
-
-
64
8
-
X
X
X
X
-
-
-
-
-
-
64
8
2
2
2
-
24
24
24
-
-
-
-
-
128
128
128
128
128
128
128
128
128
128
128
128
64
16
16
16
16
16
16
16
16
16
16
16
16
8
-
-
-
-
X
-
806 Ksps
-
-
-
-
1000 Ksps
1000 Ksps
1000 Ksps
1000 Ksps
1000 Ksps
1000 Ksps
1000 Ksps
1000 Ksps
1000 Ksps
1000 Ksps
806 Ksps
-
-
-
-
-
-
X
-
-
-
-
-
-
X
X
-
-
-
-
-
-
-
X
X
X
X
X
X
X
X
-
-
-
-
-
-
-
24
24
24
24
24
24
24
24
24
24
24
24
24
1
1
-
-
-
-
[14]
CY8C4147AZE-S295
CY8C4147AZE-S445
CY8C4147AZE-S455
CY8C4147AZE-S465
CY8C4147AZE-S475
CY8C4126LQA-S455
CY8C4146LQA-S245
CY8C4146LQA-S255
CY8C4146LQA-S265
CY8C4146LQA-S275
CY8C4146LQA-S455
CY8C4127LQA-S445
-
X
-
-
-
-
2
2
2
2
2
-
-
-
-
X
-
-
-
-
-
1
1
-
-
-
-
X
X
-
-
-
-
-
X
X
X
X
X
X
X
X
X
X
X
X
X
X
64
8
1000 Ksps
1000 Ksps
1000 Ksps
1000 Ksps
1000 Ksps
806 Ksps
-
-
-
-
64
8
-
-
X
-
-
-
-
-
64
8
-
X
X
X
-
-
-
-
-
64
8
-
X
X
X
-
-
-
-
64
8
2
2
-
-
-
-
128
16
-
-
-
-
Note
13. Contact Infineon Support for the availability of Grade-E devices.
14. Alternate fab available.
Table 43
Ordering information (continued)
Operating
MPN
Features
Packages
temperaure
CY8C4127LQA-S455
CY8C4147LQA-S245
CY8C4147LQA-S255
CY8C4147LQA-S265
CY8C4147LQA-S275
CY8C4147LQA-S285
CY8C4147LQA-S295
CY8C4147LQA-S445
CY8C4147LQA-S455
CY8C4147LQA-S465
CY8C4147LQA-S475
CY8C4126LQS-S455
CY8C4146LQS-S245
CY8C4146LQS-S255
CY8C4146LQS-S265
CY8C4146LQS-S275
CY8C4146LQS-S455
CY8C4127LQS-S445
CY8C4127LQS-S455
CY8C4147LQS-S245
CY8C4147LQS-S255
24
48
48
48
48
48
48
48
48
48
48
24
48
48
48
48
48
24
24
48
48
48
48
48
48
48
48
48
48
24
128
128
128
128
128
128
128
128
128
128
128
64
16
16
16
16
16
16
16
16
16
16
16
8
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
2
-
X
-
X
806 Ksps
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
-
-
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
X
X
X
X
X
X
X
X
X
X
X
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
X
-
1000 Ksps
1000 Ksps
1000 Ksps
1000 Ksps
1000 Ksps
1000 Ksps
1000 Ksps
1000 Ksps
1000 Ksps
1000 Ksps
806 Ksps
-
-
X
-
-
-
-
X
X
-
-
-
-
X
X
X
X
X
X
X
X
-
-
-
-
1
1
-
-
-
X
-
-
2
2
2
2
2
-
-
X
-
-
-
1
1
-
-
X
X
-
-
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
-
64
8
1000 Ksps
1000 Ksps
1000 Ksps
1000 Ksps
1000 Ksps
806 Ksps
-
-
64
8
-
-
X
-
-
-
64
8
-
X
X
X
-
-
-
64
8
-
X
X
X
X
-
-
-
64
8
2
2
2
-
-
-
128
128
128
128
128
128
128
128
128
128
128
128
64
16
16
16
16
16
16
16
16
16
16
16
16
8
-
-
X
-
806 Ksps
-
-
1000 Ksps
1000 Ksps
1000 Ksps
1000 Ksps
1000 Ksps
1000 Ksps
1000 Ksps
1000 Ksps
1000 Ksps
1000 Ksps
806 Ksps
-
-
-
-
X
-
-
-
[14]
CY8C4147LQS-S265
CY8C4147LQS-S275
CY8C4147LQS-S285
CY8C4147LQS-S295
CY8C4147LQS-S445
CY8C4147LQS-S455
CY8C4147LQS-S465
CY8C4147LQS-S475
CY8C4126LQE-S455
-
X
X
-
-
-
-
X
X
X
X
X
X
X
X
-
-
-
1
1
-
-
-
X
-
-
2
2
2
2
2
-
X
-
-
-
1
1
-
-
X
X
-
-
Note
13. Contact Infineon Support for the availability of Grade-E devices.
14. Alternate fab available.
Table 43
Ordering information (continued)
Operating
MPN
Features
Packages
temperaure
CY8C4146LQE-S245
CY8C4146LQE-S255
CY8C4146LQE-S265
CY8C4146LQE-S275
CY8C4146LQE-S455
CY8C4127LQE-S445
CY8C4127LQE-S455
CY8C4147LQE-S245
CY8C4147LQE-S255
CY8C4147LQE-S265
CY8C4147LQE-S275
CY8C4147LQE-S285
CY8C4147LQE-S295
CY8C4147LQE-S445
CY8C4147LQE-S455
CY8C4147LQE-S465
CY8C4147LQE-S475
48
48
48
48
48
24
24
48
48
48
48
48
48
48
48
48
48
64
64
8
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1000 Ksps
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
-
-
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
8
X
-
1000 Ksps
1000 Ksps
1000 Ksps
1000 Ksps
806 Ksps
64
8
-
X
X
X
-
-
64
8
-
X
X
X
X
-
-
64
8
2
2
2
-
-
128
128
128
128
128
128
128
128
128
128
128
128
16
16
16
16
16
16
16
16
16
16
16
16
-
X
-
806 Ksps
-
1000 Ksps
1000 Ksps
1000 Ksps
1000 Ksps
1000 Ksps
1000 Ksps
1000 Ksps
1000 Ksps
1000 Ksps
1000 Ksps
-
-
-
X
-
-
-
X
X
-
-
-
X
X
X
X
X
X
X
-
-
1
1
-
-
X
-
2
2
2
2
X
-
-
1
1
X
Note
13. Contact Infineon Support for the availability of Grade-E devices.
14. Alternate fab available.
Automotive PSoC™ 4: PSoC™ 4100S Plus
Based on Arm® Cortex®-M0+ CPU
Ordering information
The nomenclature used in the preceding table is based on the following part numbering convention:
Field
Description
Values
Meaning
CY8C
Cypress (an Infineon
company) prefix
4
A
B
Architecture
Family
CPU speed
4
1
2
PSoC™ 4
4100 family
24 MHz
4
4
48 MHz
16 KB
C
Flash capacity
5
32 KB
6
64 KB
7
128 KB
DE
F
Package code
AZ
LQ
A
S
E
S
TQFP (0.5-mm pitch)
QFN
Automotive (AEC-Q100: –40°C to +85°C)
Automotive (AEC-Q100: –40°C to +105°C)
Automotive (AEC-Q100: –40°C to +125°C)
PSoC™ 4 S-Series
Temperature range
S
Silicon family
M
L
PSoC™ 4 M-Series
PSoC™ 4 L-Series
BL
000–999
PSoC™ 4 Bluetooth® LE-Series
Code of feature set in the specific family
XYZ
Attributes code
Datasheet
53
002-20072 Rev. *P
2023-05-02
Automotive PSoC™ 4: PSoC™ 4100S Plus
Based on Arm® Cortex®-M0+ CPU
Ordering information
The following is an example of a part number:
CY8C
4
A
B
C
DE
F
S
XYZ
T
T = Tape and reel
Attributes code
Silicon family
Temperature range
Package code
Flash capacity
CPU Speed
Family within architecture
Architecture
Cypress (an Infineon company) Prefix
Example
4: PSoC™ 4
1: 4100 family
4: 48 MHz
6: 64 KB
AZ: TQFP
A, S, E: Automotive
Datasheet
54
002-20072 Rev. *P
2023-05-02
Automotive PSoC™ 4: PSoC™ 4100S Plus
Based on Arm® Cortex®-M0+ CPU
Packaging
6
Packaging
The PSoC™ 4100S Plus will be offered in 40-pin QFN, 64-pin QFN, and 64-pin TQFP packages.
Table 44 provides the package dimensions and Infineon drawing numbers.
Table 44
Spec ID#
Package list
Package
Description
10 × 10 × 1.6-mm height with 0.5-mm pitch
6 × 6 × 0.6-mm height with 0.5-mm pitch with
wettable flanks
Package Dwg
51-85051
002-25105
BID27
BID27A
64-pin TQFP
40-pin QFN
BID29
64-pin QFN
9.0 × 9.0 × 0.9 mm
002-31760
Table 45
Parameter
TA
Package thermal characteristics
Description
Package
Conditions
For A-grade devices
For S-grade devices
For E-grade devices
For A-grade devices
For S-grade devices
For E-grade devices
–
Min
–40
–40
–40
–40
–40
–40
–
Typ
25
25
25
–
Max
85
Unit
°C
Operating ambient
temperature
–
–
105
125
100
115
140
TJ
Operating junction
temperature
–
–
TJA
TJC
Package θJA
Package θJC
64-pin TQFP
40-pin QFN
64-pin QFN
64-pin TQFP
40-pin QFN
64-pin QFN
46
25
17
10
3
–
–
°C/W
°C/W
–
–
–
–
–
–
–
–
6
Table 46
Solder reflow peak temperature
Package Maximum peak temperature
All 260°C
Maximum time at peak temperature
30 seconds
Table 47
Package moisture sensitivity level (MSL), IPC/JEDEC J-STD-020
Package
MSL
MSL 3
All
Datasheet
55
002-20072 Rev. *P
2023-05-02
Automotive PSoC™ 4: PSoC™ 4100S Plus
Based on Arm® Cortex®-M0+ CPU
Packaging
6.1
Package diagrams
51-85051 *D
Figure 6
64-pin TQFP (10 × 10 × 1.4 mm) package outline, 51-85051
Datasheet
56
002-20072 Rev. *P
2023-05-02
Automotive PSoC™ 4: PSoC™ 4100S Plus
Based on Arm® Cortex®-M0+ CPU
Packaging
002-25105 *A
40-pin QFN ((6 × 6 × 0.6 mm) 4.6 × 4.6 mm E-Pad (Sawn)) package outline, 002-25105
Figure 7
Datasheet
57
002-20072 Rev. *P
2023-05-02
Automotive PSoC™ 4: PSoC™ 4100S Plus
Based on Arm® Cortex®-M0+ CPU
Packaging
NOTES:
DIMENSIONS
SYMBOL
e
N
ND
1. ALL DIMENSIONS ARE IN MILLIMETERS.
2. N IS THE TOTAL NUMBER OF TERMINALS.
MIN.
0.30
NOM.
0.50 BSC
64
16
0.40
MAX.
0.50
3
DIMENSION "b" APPLIES TO METALLIZED TERMINAL AND IS MEASURED
BETWEEN 0.15 AND 0.30mm FROM TERMINAL TIP. IF THE TERMINAL HAS
THE OPTIONAL RADIUS ON THE OTHER END OF THE TERMINAL, THE
DIMENSION "b" SHOULD NOT BE MEASURED IN THAT RADIUS AREA.
ND REFERS TO THE NUMBER OF TERMINALS ON D SIDE.
L
b
D2
E2
D
0.18
7.60
7.60
0.25
7.70
0.30
7.80
7.80
4
5
6
PIN #1 ID ON TOP WILL BE LOCATED WITHIN THE INDICATED ZONE.
COPLANARITY ZONE APPLIES TO THE EXPOSED HEAT SINK
SLUG AS WELL AS THE TERMINALS.
7.70
9.00 BSC
E
A
A1
A3
R
9.00 BSC
7. JEDEC SPECIFICATION NO. REF. : N/A.
-
-
-
0.90
0.05
0.00
0.203 REF
0.20 TYP
0.25 MIN
K
002-31760 **
64-pin QFN (9 × 9 × 0.9 mm) 7.70 × 7.70 mm E-Pad (Sawn)) package outline, 002-31760
Figure 8
Datasheet
58
002-20072 Rev. *P
2023-05-02
Automotive PSoC™ 4: PSoC™ 4100S Plus
Based on Arm® Cortex®-M0+ CPU
Acronyms
7
Acronyms
Table 48
Acronym
abus
Acronyms used in this document
Description
analog local bus
ADC
AG
analog-to-digital converter
analog global
AMBA (advanced microcontroller bus architecture) high-performance bus, an Arm® data
transfer bus
AHB
ALU
arithmetic logic unit
AMUXBUS
API
APSR
Arm®
ATM
BW
analog multiplexer bus
application programming interface
application program status register
advanced RISC machine, a CPU architecture
automatic thump mode
bandwidth
CAN
CMRR
CPU
CRC
DAC
DFB
Controller Area Network, a communications protocol
common-mode rejection ratio
central processing unit
cyclic redundancy check, an error-checking protocol
digital-to-analog converter, see also IDAC, VDAC
digital filter block
DIO
digital input/output, GPIO with only digital capabilities, no analog. See GPIO.
Dhrystone million instructions per second
direct memory access, see also TD
differential nonlinearity, see also INL
do not use
DMIPS
DMA
DNL
DNU
DR
port write data registers
DSI
digital system interconnect
DWT
ECC
data watchpoint and trace
error correcting code
ECO
EEPROM
EMI
EMIF
EOC
EOF
external crystal oscillator
electrically erasable programmable read-only memory
electromagnetic interference
external memory interface
end of conversion
end of frame
EPSR
ESD
execution program status register
electrostatic discharge
ETM
FIR
FPB
embedded trace macrocell
finite impulse response, see also IIR
flash patch and breakpoint
Datasheet
59
002-20072 Rev. *P
2023-05-02
Automotive PSoC™ 4: PSoC™ 4100S Plus
Based on Arm® Cortex®-M0+ CPU
Acronyms
Table 48
Acronym
FS
Acronyms used in this document (continued)
Description
full-speed
GPIO
HVI
IC
general-purpose input/output, applies to a PSoC™ pin
high-voltage interrupt, see also LVI, LVD
integrated circuit
IDAC
IDE
I2C, or IIC
IIR
ILO
IMO
INL
current DAC, see also DAC, VDAC
integrated development environment
Inter-Integrated Circuit, a communications protocol
infinite impulse response, see also FIR
internal low-speed oscillator, see also IMO
internal main oscillator, see also ILO
integral nonlinearity, see also DNL
input/output, see also GPIO, DIO, SIO, USBIO
initial power-on reset
I/O
IPOR
IPSR
IRQ
interrupt program status register
interrupt request
ITM
LCD
instrumentation trace macrocell
liquid crystal display
LIN
LR
Local Interconnect Network, a communications protocol.
link register
LUT
lookup table
LVD
LVI
low-voltage detect, see also LVI
low-voltage interrupt, see also HVI
low-voltage transistor-transistor logic
multiply-accumulate
microcontroller unit
master-in slave-out
LVTTL
MAC
MCU
MISO
NC
no connect
NMI
nonmaskable interrupt
NRZ
NVIC
NVL
opamp
PAL
non-return-to-zero
nested vectored interrupt controller
nonvolatile latch, see also WOL
operational amplifier
programmable array logic, see also PLD
program counter
PC
PCB
PGA
PHUB
PHY
PICU
PLA
printed circuit board
programmable gain amplifier
peripheral hub
physical layer
port interrupt control unit
programmable logic array
Datasheet
60
002-20072 Rev. *P
2023-05-02
Automotive PSoC™ 4: PSoC™ 4100S Plus
Based on Arm® Cortex®-M0+ CPU
Acronyms
Table 48
Acronym
PLD
Acronyms used in this document (continued)
Description
programmable logic device, see also PAL
phase-locked loop
PLL
PMDD
POR
PRES
PRS
package material declaration data sheet
power-on reset
precise power-on reset
pseudo random sequence
port read data register
PS
PSoC™
PSRR
PWM
RAM
RISC
RMS
RTC
Programmable system-on-chip
power supply rejection ratio
pulse-width modulator
random-access memory
reduced-instruction-set computing
root-mean-square
real-time clock
RTL
RTR
RX
register transfer language
remote transmission request
receive
SAR
SC/CT
SCL
successive approximation register
switched capacitor/continuous time
I2C serial clock
SDA
I2C serial data
S/H
sample and hold
SINAD
SIO
SOC
SOF
signal to noise and distortion ratio
special input/output, GPIO with advanced features. See GPIO.
start of conversion
start of frame
SPI
SR
Serial Peripheral Interface, a communications protocol
slew rate
SRAM
SRES
SWD
SWV
TD
THD
TIA
TRM
TTL
static random access memory
software reset
serial wire debug, a test protocol
single-wire viewer
transaction descriptor, see also DMA
total harmonic distortion
transimpedance amplifier
technical reference manual
transistor-transistor logic
transmit
TX
UART
UDB
Universal Asynchronous Transmitter Receiver, a communications protocol
universal digital block
Datasheet
61
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Automotive PSoC™ 4: PSoC™ 4100S Plus
Based on Arm® Cortex®-M0+ CPU
Acronyms
Table 48
Acronym
USB
Acronyms used in this document (continued)
Description
Universal Serial Bus
USBIO
VDAC
WDT
USB input/output, PSoC™ pins used to connect to a USB port
voltage DAC, see also DAC, IDAC
watchdog timer
WOL
WRES
XRES
write once latch, see also NVL
watchdog timer reset
external reset I/O pin
XTAL
crystal
Datasheet
62
002-20072 Rev. *P
2023-05-02
Automotive PSoC™ 4: PSoC™ 4100S Plus
Based on Arm® Cortex®-M0+ CPU
Document conventions
8
Document conventions
8.1
Units of measure
Table 49
Symbol
°C
Units of measure
Unit of measure
degrees Celsius
decibel
dB
fF
Hz
femto farad
hertz
KB
1024 bytes
kbps
Khr
kHz
k
kilobits per second
kilohour
kilohertz
kilo ohm
ksps
LSB
Mbps
MHz
M
Msps
µA
kilosamples per second
least significant bit
megabits per second
megahertz
mega-ohm
megasamples per second
microampere
microfarad
µF
µH
µs
µV
microhenry
microsecond
microvolt
µW
mA
ms
mV
nA
microwatt
milliampere
millisecond
millivolt
nanoampere
nanosecond
nanovolt
ns
nV
ohm
pF
picofarad
ppm
ps
parts per million
picosecond
s
second
sps
sqrtHz
V
samples per second
square root of hertz
volt
Datasheet
63
002-20072 Rev. *P
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Automotive PSoC™ 4: PSoC™ 4100S Plus
Based on Arm® Cortex®-M0+ CPU
Revision history
Revision history
Document
Date
Description of changes
revision
*O
2023-01-20
Post to external web.
Updated Table 1 in Pinouts.
Updated Table 44 in Packaging.
Removed spec 002-29721 ** in Package diagrams.
Removed 48-pin QFN throughout the document.
*P
2023-05-02
Datasheet
64
002-20072 Rev. *P
2023-05-02
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