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PSoC^™4: PSoC 4200L Datasheet

Programmable System-on-Chip (PSoC^®)

General Description

PSoC^™4 is a scalable and reconfigurable platform architecture for a family of programmable embedded system controllers with an

Arm^®Cortex^®-M0 CPU. It combines programmable and reconfigurable analog and digital blocks with flexible automatic routing. The

PSoC 4200L product family, based on this platform, is a combination of a microcontroller with digital programmable logic, program-

mable analog, programmable interconnect, secure expansion of memory off-chip, high-performance analog-to-digital conversion,

opamps with Comparator mode, and standard communication and timing peripherals. The PSoC 4200L products will be fully

compatible with members of the PSoC 4 platform for new applications and design needs. The programmable analog and digital

subsystems allow flexibility and in-field tuning of the design.

Features

32-bit MCU Subsystem

Serial Communication

■ 48 MHz Arm Cortex-M0 CPU with single-cycle multiply

■ Up to 256 kB of flash with Read Accelerator

■ Up to 32 kB of SRAM

■ Four independent run-time reconfigurable serial communi-

cation blocks (SCBs) with reconfigurable I²C, SPI, or UART

functionality

■ USB Full-Speed device interface 12 Mbits/sec with Battery

Charger Detect capability

■ DMA engine with 32 channels

Programmable Analog

■ Two independent CAN blocks for industrial and automotive

networking

■ Four opamps that operate in Deep Sleep mode at very low

current levels

Timing and Pulse-Width Modulation

■ All opamps have reconfigurable high current pin-drive,

high-bandwidth internal drive, ADC input buffering, and

Comparator modes with flexible connectivity allowing input

connections to any pin

■ Eight 16-bit timer/counter pulse-width modulator (TCPWM)

blocks

■ Center-aligned, Edge, and Pseudo-random modes

■ Four current DACs (IDACs) for general-purpose or capacitive

sensing applications on any pin

■ Comparator-based triggering of Kill signals for motor drive and

other high-reliability digital logic applications

■ Two low-power comparators that operate in Deep Sleep mode

Up to 98 Programmable GPIOs

Programmable Digital

■ 124-ball VFBGA, 64-pin TQFP, 48-pin TQFP, and 68-pin QFN

packages

■ Eight programmable logic blocks, each with 8 Macrocells and

an 8-bit data path (called universal digital blocks or UDBs)

■ Cypress-provided peripheral component library, user-defined

state machines, and Verilog input

■ Any of up to 94 GPIO pins can be CapSense, analog, or digital

■ Drive modes, strengths, and slew rates are programmable

Low Power 1.71 V to 5.5 V Operation

PSoC Creator Design Environment

■ 20-nA Stop Mode with GPIO pin wakeup

■ Integrated Development Environment (IDE) provides

schematic design entry and build (with analog and digital

automatic routing)

■ Hibernate and Deep Sleep modes allow wakeup-time versus

power trade-offs

Capacitive Sensing

■ Applications Programming Interface (API component) for all

fixed-function and programmable peripherals

■ Two Cypress Capacitive Sigma-Delta (CSD) blocks provide

best-in-class SNR (>5:1) and water tolerance

Industry-Standard Tool Compatibility

■ Cypress-supplied software component makes capacitive

sensing design easy

■ After schematic entry, development can be done with

Arm-based industry-standard development tools

■ Automatic hardware tuning (SmartSense™)

Segment LCD Drive

■ LCD drive supported on any pin with up to a maximum of 64

outputs (common or segment)

■ Operates in Deep Sleep mode with 4 bits per pin memory

Cypress Semiconductor Corporation

Document Number: 001-91686 Rev. *K

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised April 12, 2021

PSoC^™4: PSoC 4200L Datasheet

More Information

Cypress provides a wealth of data at www.cypress.com to help you to select the right PSoC device for your design, and to help you

to quickly and effectively integrate the device into your design. For a comprehensive list of resources, see the knowledge base article

KBA86521, How to Design with PSoC 3, PSoC 4, and PSoC 5LP. Following is an abbreviated list for PSoC 4:

■ Overview: PSoC Portfolio, PSoC Roadmap

■ Technical Reference Manual (TRM) is in two documents:

❐ Architecture TRM details each PSoC 4 functional block.

❐ Registers TRM describes each of the PSoC 4 registers.

■ Product Selectors: PSoC 1, PSoC 3, PSoC 4, PSoC 5LP

In addition, PSoC Creator includes a device selection tool.

■ Application notes: Cypress offers a large number of PSoC

application notes covering a broad range of topics, from basic

to advanced level. Recommended application notes for getting

started with PSoC 4 are:

❐ AN79953: Getting Started With PSoC 4

❐ AN88619: PSoC 4 Hardware Design Considerations

❐ AN86439: Using PSoC 4 GPIO Pins

❐ AN57821: Mixed Signal Circuit Board Layout

❐ AN81623: Digital Design Best Practices

❐ AN73854: Introduction To Bootloaders

❐ AN89610: Arm Cortex Code Optimization

■ Development Kits:

❐ CY8CKIT-042, PSoC 4 Pioneer Kit, is an easy-to-use and

inexpensive development platform. This kit includes

connectors for Arduino™ compatible shields and Digilent®

Pmod™ daughter cards.

❐ CY8CKIT-046, PSoC 4 L-Series Pioneer Kit, is an

easy-to-use and inexpensive development platform. This kit

includes connectors for Arduino™ compatible shields.

❐ CY8CKIT-049 is a very low-cost prototyping platform. It is a

low-cost alternative to sampling PSoC 4 devices.

❐ CY8CKIT-001 is a common development platform for any

one of the PSoC 1, PSoC 3, PSoC 4, or PSoC 5LP families

of devices.

❐ AN85951: PSoC 4 and PSoC 6 MCU CapSense Design

Guide

The MiniProg3 device provides an interface for flash

programming and debug.

PSoC Creator

PSoC Creator is a free Windows-based Integrated Design Environment (IDE). It enables concurrent hardware and firmware design

of PSoC 3, PSoC 4, and PSoC 5LP based systems. Create designs using classic, familiar schematic capture supported by over 100

pre-verified, production-ready PSoC Components; see the list of component datasheets. With PSoC Creator, you can:

1. Drag and drop component icons to build your hardware

system design in the main design workspace

2. Codesign your application firmware with the PSoC hardware,

using the PSoC Creator IDE C compiler

3. Configure components using the configuration tools

4. Explore the library of 100+ components

5. Review component datasheets

Figure 1. Multiple-Sensor Example Project in PSoC Creator Contents

1

2

3

4

5

Document Number: 001-91686 Rev. *K

Page 2 of 47

PSoC^™4: PSoC 4200L Datasheet

Contents

PSoC 4200L Block Diagram............................................. 4

Functional Definition........................................................ 5

CPU and Memory Subsystem..................................... 5

System Resources ...................................................... 5

Analog Blocks.............................................................. 6

Programmable Digital.................................................. 7

Fixed Function Digital.................................................. 8

GPIO ........................................................................... 9

SIO .............................................................................. 9

Special Function Peripherals....................................... 9

Pinouts ............................................................................ 10

Power............................................................................... 15

Unregulated External Supply..................................... 15

Regulated External Supply........................................ 15

Electrical Specifications ................................................ 16

Absolute Maximum Ratings....................................... 16

Device Level Specifications....................................... 16

Analog Peripherals.................................................... 20

Digital Peripherals ..................................................... 25

Memory ..................................................................... 28

System Resources.................................................... 29

Ordering Information...................................................... 36

Part Numbering Conventions .................................... 37

Packaging........................................................................ 38

Acronyms........................................................................ 41

Document Conventions ................................................. 43

Units of Measure ....................................................... 43

Revision History ............................................................. 44

Sales, Solutions, and Legal Information ...................... 45

Worldwide Sales and Design Support....................... 45

Products.................................................................... 45

PSoC® Solutions ...................................................... 45

Cypress Developer Community................................. 45

Technical Support ..................................................... 45

Document Number: 001-91686 Rev. *K

Page 3 of 47

PSoC^™4: PSoC 4200L Datasheet

Figure 2. Block Diagram

CPU Subsystem

PSoC 4200L

Architecture

SWD/TC

Cortex

M0

SPCIF

FLASH

256KB

SRAM

32KB

ROM

8 KB

DataWire/

DMA

32-bit

48MHz

AHB- Lite

FAST MUL

Read Accelerator

SRAM Controller

ROM Controller

Initiator/ MMIO

NVIC, IRQMX

System Resources

Power

Sleep Control

WIC

System Interconnect (Multi Layer AHB)

Peripheral Interconnect (MMIO)

Peripherals

POR

REF

LVD

BOD

PWRSYS

NVLatches

PCLK

Clock

Clock Control

WDT

Programmable

Digital

Programmable

Analog

512B

IMO

ILO

ECO 2x PLL

SAR ADC

(12-bit)

UDB

...

UDB

Reset

Reset Control

XRES

x1

x8

Test

DFT Logic

DFT Analog

SMX

CTBm

x2

2x OpAmp

Port Interface & Digital System Interconnect (DSI)

Power Modes

Active/ Sleep

Deep Sleep

Hibernate

High Speed I / O Matrix, 1x Programmable I/O

80 x GPIO, 14 x GPIO_OVT,2x SIO

I/O Subsystem

to disable debug features, robust flash protection, and because

it allows customer-proprietary functionality to be implemented in

on-chip programmable blocks.

PSoC 4200L Block Diagram

The PSoC 4200L devices include extensive support for

programming, testing, debugging, and tracing both hardware

and firmware.

The debug circuits are enabled by default and can only be

disabled in firmware. If not enabled, the only way to re-enable

them is to erase the entire device, clear flash protection, and

reprogram the device with new firmware that enables debugging.

The Arm Serial_Wire Debug (SWD) interface supports all

programming and debug features of the device.

Additionally, all device interfaces can be permanently disabled

(device security) for applications concerned about phishing

attacks due to a maliciously reprogrammed device or attempts to

defeat security by starting and interrupting flash programming

sequences. Because all programming, debug, and test inter-

faces are disabled when maximum device security is enabled,

PSoC 4200L with device security enabled may not be returned

for failure analysis. This is a trade-off the PSoC 4200Lallows the

customer to make.

Complete debug-on-chip functionality enables full-device

debugging in the final system using the standard production

device. It does not require special interfaces, debugging pods,

simulators, or emulators. Only the standard programming

connections are required to fully support debug.

The PSoC Creator Integrated Development Environment (IDE)

provides fully integrated programming and debug support for

PSoC 4200Ldevices. The SWD interface is fully compatible with

industry-standard third-party tools. The PSoC 4200L family

provides a level of security not possible with multi-chip appli-

cation solutions or with microcontrollers. This is due to its ability

Document Number: 001-91686 Rev. *K

Page 4 of 47

PSoC^™4: PSoC 4200L Datasheet

Clock System

Functional Definition

CPU and Memory Subsystem

CPU

The PSoC 4200L clock system is responsible for providing

clocks to all subsystems that require clocks and for switching

between different clock sources without glitching. In addition, the

clock system ensures that no meta-stable conditions occur.

The Cortex-M0 CPU in the PSoC 4200Lis part of the 32-bit MCU

subsystem, which is optimized for low-power operation with

extensive clock gating. Most instructions are 16 bits in length and

execute a subset of the Thumb-2 instruction set. This enables

fully compatible binary upward migration of the code to higher

performance processors such as the Cortex-M3 and M4, thus

enabling upward compatibility. The Cypress implementation

includes a hardware multiplier that provides a 32-bit result in one

cycle. It includes a nested vectored interrupt controller (NVIC)

block with 32 interrupt inputs and also includes a Wakeup

Interrupt Controller (WIC), which can wake the processor up

from the Deep Sleep mode allowing power to be switched off to

the main processor when the chip is in the Deep Sleep mode.

The Cortex-M0 CPU provides a Non-Maskable Interrupt (NMI)

input, which is made available to the user when it is not in use

for system functions requested by the user.

The clock system for the PSoC 4200L consists of a crystal oscil-

lator (4 to 33 MHz), a watch crystal oscillator (32 kHz), a

phase-locked loop (PLL), the IMO and the ILO internal oscil-

lators, and provision for an external clock.

Figure 3. PSoC 4200L MCU Clocking Architecture

IMO

clk_hf

clk_ext

PLL #1

ECO

(optional )

PLL #0

dsi_in[0]

dsi_in[1]

dsi_in[2]

dsi_in[3]

The CPU also includes a debug interface, the serial wire debug

(SWD) interface, which is a 2-wire form of JTAG; the debug

configuration used for PSoC 4200L has four break-point

(address) comparators and two watchpoint (data) comparators.

dsi_out[3:0]

ILO

Flash

clk_lf

WCO

The PSoC 4200L has a flash module with a flash accelerator,

tightly coupled to the CPU to improve average access times from

the flash block. The flash block is designed to deliver 2 wait-state

(WS) access time at 48 MHz and with 1-WS access time at

24 MHz. The flash accelerator delivers 85% of single-cycle

SRAM access performance on average. Part of the flash module

can be used to emulate EEPROM operation if required.

The clk_hf signal can be divided down to generate synchronous

clocks for the UDBs, and the analog and digital peripherals.

There are a total of 16 clock dividers for the PSoC 4200L, each

with 16-bit divide capability; this allows 12 to be used for the

fixed-function blocks and four for the UDBs. The analog clock

leads the digital clocks to allow analog events to occur before

digital clock-related noise is generated. The 16-bit capability

allows a lot of flexibility in generating fine-grained frequency

values and is fully supported in PSoC Creator.

SRAM

SRAM memory is retained during Hibernate.

SROM

IMO Clock Source

Asupervisory ROM that contains boot and configuration routines

is provided.

The IMO is the primary source of internal clocking in the

PSoC 4200L. It is trimmed during testing to achieve the specified

accuracy. Trim values are stored in nonvolatile latches (NVL).

Additional trim settings from flash can be used to compensate for

changes. The IMO default frequency is 24 MHz and it can be

adjusted between 3 to 48 MHz in steps of 1 MHz. IMO tolerance

with Cypress-provided calibration settings is ±2%.

DMA

A DMA engine is provided that can do 32-bit transfers and has

chainable ping-pong descriptors.

System Resources

Power System

ILO Clock Source

The power system is described in detail in the section Power on

page 15. It provides assurance that voltage levels are as

required for each respective mode and either delay mode entry

(on power-on reset (POR), for example) until voltage levels are

as required for proper function or generate resets (brown-out

detect (BOD)) or interrupts (low voltage detect (LVD)). The

PSoC 4200L operates with a single external supply over the

range of 1.71 to 5.5 V and has five different power modes, transi-

tions between which are managed by the power system. The

PSoC 4200L provides Sleep, Deep Sleep, Hibernate, and Stop

low-power modes.

The ILO is a very low power oscillator, nominally 32 kHz, which

is primarily used to generate clocks for peripheral operation in

Deep Sleep mode. ILO-driven counters can be calibrated to the

IMO to improve accuracy. Cypress provides a software

component, which does the calibration.

Crystal Oscillators and PLL

The PSoC 4200L clock subsystem also implements two oscil-

lators: high-frequency (4 to 33 MHz) and low-frequency (32-kHz

watch crystal) that can be used for precision timing applications.

The PLL can generate a 48-MHz output from the high-frequency

oscillator.

Document Number: 001-91686 Rev. *K

Page 5 of 47

PSoC^™4: PSoC 4200L Datasheet

Watchdog Timer

external reference through a GPIO pin. The Sample-and-Hold

(S/H) aperture is programmable allowing the gain bandwidth

requirements of the amplifier driving the SAR inputs, which

determine its settling time, to be relaxed if required. The system

performance will be 65 dB for true 12-bit precision if appropriate

references are used and system noise levels permit. To improve

performance in noisy conditions, it is possible to provide an

external bypass (through a fixed pin location) for the internal

reference amplifier.

Awatchdog timer is implemented in the clock block running from

the ILO; this allows watchdog operation during Deep Sleep and

generates a watchdog reset if not serviced before the timeout

occurs. The watchdog reset is recorded in the Reset Cause

register.

Reset

The PSoC 4200Lcan be reset from a variety of sources including

a software reset. Reset events are asynchronous and guarantee

reversion to a known state. The reset cause is recorded in a

register, which is sticky through reset and allows software to

determine the cause of the reset. An XRES pin is reserved for

external reset to avoid complications with configuration and

multiple pin functions during power-on or reconfiguration.

The SAR is connected to a fixed set of pins through an 8-input

sequencer (expandable to 16 inputs). The sequencer cycles

through selected channels autonomously (sequencer scan) and

does so with zero switching overhead (that is, the aggregate

sampling bandwidth is equal to 1 Msps, whether it is for a single

channel or distributed over several channels). The sequencer

switching is effected through a state machine or through

firmware-driven switching. A feature provided by the sequencer

is buffering of each channel to reduce CPU interrupt service

requirements. To accommodate signals with varying source

impedance and frequency, it is possible to have different sample

times programmable for each channel. In addition, the signal

range specification through a pair of range registers (low and

high range values) is implemented with a corresponding

out-of-range interrupt if the digitized value exceeds the

programmed range; this allows fast detection of out-of-range

values without the necessity of having to wait for a sequencer

scan to be completed and the CPU to read the values and check

for out-of-range values in software.

Voltage Reference

The PSoC 4200L reference system generates all internally

required references. A1% voltage reference spec is provided for

the 12-bit ADC. To allow better signal-to-noise ratios (SNR) and

better absolute accuracy, it is possible to add an external bypass

capacitor to the internal reference using a GPIO pin or to use an

external reference for the SAR.

Analog Blocks

12-bit SAR ADC

The 12-bit, 1-Msps SAR ADC can operate at a maximum clock

rate of 18 MHz and requires a minimum of 18 clocks at that

frequency to do a 12-bit conversion.

The SAR is able to digitize the output of the on-board

temperature sensor for calibration and other

temperature-dependent functions. The SAR is not available in

Deep Sleep and Hibernate modes as it requires a high-speed

clock (up to 18 MHz). The SAR operating range is 1.71 to 5.5 V.

The block functionality is augmented for the user by adding a

reference buffer to it (trimmable to ±1%) and by providing the

choice (for the PSoC 4200L case) of three internal voltage refer-

ences: V_DD, V_DD/2, and V_REF(nominally 1.024 V) as well as an

Figure 4. SAR ADC System Diagram

AHB System Bus and Programmable Logic

Interconnect

SARSEQ

Sequencing

and Control

Data and

Status Flags

POS

NEG

SARADC

External

Reference

and

Reference

Selection

Bypass

(optional)

VDDD

VREF

VDD/2

Inputs from other Ports

Document Number: 001-91686 Rev. *K

Page 6 of 47

PSoC^™4: PSoC 4200L Datasheet

Analog Multiplex Bus

to any pin on the chip. Analog switch connectivity is controllable

by user firmware as well as user-defined programmable digital

state machines (implemented via UDBs).

The PSoC4200L has two concentric analog buses (Analog Mux

Bus A and Analog Mux Bus B) that circumnavigate the periphery

of the chip. These buses can transport analog signals from any

pin to various analog blocks (including the opamps) and to the

CapSense blocks allowing, for instance, the ADC to monitor any

pin on the chip. These buses are independent and can also be

split into three independent sections. This allows one section to

be used for CapSense purposes, one for general analog signal

processing, and the third for general-purpose digital peripherals

and GPIO.

The opamps operate in Deep Sleep mode at very low currents

allowing analog circuits to remain operational during Deep

Sleep.

Temperature Sensor

The PSoC 4200L has one on-chip temperature sensor. This

consists of a diode, which is biased by a current source that can

be disabled to save power. The temperature sensor is connected

to the ADC, which digitizes the reading and produces a

temperature value using Cypress-supplied software that

includes calibration and linearization.

Four Opamps (CTBm Blocks)

The PSoC 4200L has four opamps with Comparator modes,

which allow most common analog functions to be performed

on-chip eliminating external components; PGAs, voltage buffers,

filters, trans-impedance amplifiers, and other functions can be

realized with external passives saving power, cost, and space.

The on-chip opamps are designed with enough bandwidth to

drive the Sample-and-Hold circuit of the ADC without requiring

external buffering. The opamps can operate in the Deep Sleep

mode at very low power levels. The following diagram shows one

of two identical opamp pairs of the opamp subsystem.

Low-power Comparators

The PSoC 4200L has a pair of low-power comparators, which

can also operate in the Deep Sleep and Hibernate modes. This

allows the analog system blocks to be disabled while retaining

the ability to monitor external voltage levels during low-power

modes. The comparator outputs are normally synchronized to

avoid meta-stability unless operating in an asynchronous power

mode (Hibernate) where the system wake-up circuit is activated

by a comparator switch event.

Figure 5. Identical Opamp Pairs in Opamp Subsystem

Programmable Digital

Universal Digital Blocks (UDBs) and Port Interfaces

The PSoC 4200L has eight UDBs; the UDB array also provides

a switched Digital System Interconnect (DSI) fabric that allows

signals from peripherals and ports to be routed to and through

the UDBs for communication and control. The UDB array is

shown in the following figure.

OA0

10x

+

Figure 6. UDB Array

-

Internal

Out0

1x

P0

P1

P2

P3

P4

P5

P6

P7

AHB Bridge CPUSS Dig CLKS

4to8

8 to32

UDBIF

OA1

-

1x

BUS IF

CLK IF

IRQ IF

Port IF

+

Internal

Out1

10x

DSI

Scalable array of

UDBs(max 8 )

=

UDB

Routing

Channels

The ovals in Figure 5 represent analog switches, which may be

controlled via user firmware, the SAR sequencer, or user-defined

programmable logic. The opamps (OA0 and OA1) are configu-

rable via these switches to perform all standard opamp functions

with appropriate feedback components.

UDB

The opamps (OA0 and OA1) are programmable and reconfigu-

rable to provide standard opamp functionality via switchable

feedback components, unity gain functionality for driving pins

directly, or for internal use (such as buffering SAR ADC inputs as

indicated in the diagram), or as true comparators.

DSI

Programmable Digital Subsystem

The opamp inputs provide highly flexible connectivity and can

connect directly to dedicated pins or, via the analog mux buses,

Document Number: 001-91686 Rev. *K

Page 7 of 47

PSoC^™4: PSoC 4200L Datasheet

UDBs can be clocked from a clock divider block, from a port

interface (required for peripherals such as SPI), and from the DSI

network directly or after synchronization.

as SPI to operate at higher clock speeds by eliminating the delay

for the port input to be routed over DSI and used to register other

inputs. The port interface is shown in Figure 7.

A port interface is defined, which acts as a register that can be

clocked with the same source as the PLDs inside the UDB array.

This allows faster operation because the inputs and outputs can

be registered at the port interface close to the I/O pins and at the

edge of the array. The port interface registers can be clocked by

one of the I/Os from the same port. This allows interfaces such

The UDBs can generate interrupts (one UDB at a time) to the

interrupt controller. The UDBs retain the ability to connect to most

of the pins on the chip through the DSI, with the exception of the

pins from Port 7, 8, and 9.

Figure 7. Port Interface

High Speed I/O Matrix

To Clock

Tree

8

4

Input Registers

Output Registers

Enables

7

6

. . .

0

7

6

. . .

0

3

2

1

0

Digital

GlobalClocks

9

4

[1]

[0]

[1]

Clock Selector

Block from

UDB

2

3 DSI Signals ,

1 I/O Signal

4

8

[1]

[0]

[1]

Reset Selector

Block from

UDB

From DSI

To DSI

From DSI

addition, the block supports an 8-deep FIFO for receive and

transmit which, by increasing the time given for the CPU to read

data, greatly reduces the need for clock stretching caused by the

CPU not having read data on time. The FIFO mode is available

in all channels and is very useful in the absence of DMA.

The I²C peripheral is compatible with the I²C Standard-mode,

Fast-mode, and Fast-mode Plus devices as defined in the NXP

I²C-bus specification and user manual (UM10204). The I²C bus

I/O is implemented with GPIO in open-drain modes.

Fixed Function Digital

Timer/Counter/PWM (TCPWM) Block

The TCPWM block consists of one 16-bit counter with

user-programmable period length. There is a Capture register to

record the count value at the time of an event (which may be an

I/O event), a period register which is used to either stop or

auto-reload the counter when its count is equal to the period

register, and compare registers to generate compare value

signals, which are used as PWM duty cycle outputs. The block

also provides true and complementary outputs with program-

mable offset between them to allow use as deadband program-

mable complementary PWM outputs. It also has a Kill input to

force outputs to a predetermined state; for example, this is used

in motor drive systems when an overcurrent state is indicated

and the PWMs driving the FETs need to be shut off immediately

with no time for software intervention. The PSoC 4200L has

eight TCPWM blocks.

UART Mode: This is a full-feature UART operating at up to

1 Mbps. It supports automotive single-wire interface (LIN),

infrared interface (IrDA), and SmartCard (ISO7816) protocols, all

of which are minor variants of the basic UART protocol. In

addition, it supports the 9-bit multiprocessor mode that allows

addressing of peripherals connected over common RX and TX

lines. Common UART functions such as parity error, break

detect, and frame error are supported. An 8-deep FIFO allows

much greater CPU service latencies to be tolerated.

Serial Communication Blocks (SCB)

SPI Mode: The SPI mode supports full Motorola SPI, TI SSP

(essentially adds a start pulse used to synchronize SPI Codecs),

and National Microwire (half-duplex form of SPI). The SPI block

can use the FIFO.

The PSoC 4200L has four SCBs, which can each implement an

I²C, UART, or SPI interface.

I²C Mode: The hardware I²C block implements a full

multi-master and slave interface (it is capable of multimaster

arbitration). This block is capable of operating at speeds of up to

1 Mbps (Fast Mode Plus) and has flexible buffering options to

reduce interrupt overhead and latency for the CPU. It also

supports EzI2C that creates a mailbox address range in the

memory of the PSoC 4200L and effectively reduces I²C commu-

nication to reading from and writing to an array in memory. In

USB Device

A Full-speed USB 2.0 device interface is provided. It has a

Control endpoint and eight other endpoints. The interface has a

USB transceiver and can be operated from the IMO obviating the

need for a crystal oscillator.

Document Number: 001-91686 Rev. *K

Page 8 of 47

PSoC^™4: PSoC 4200L Datasheet

CAN Blocks

They allow interfacing to buses, such as I²C with full I²C compat-

ibility and interfacing to devices operating at different voltage

levels. There are two SIO pins on the PSoC4200L.

There are two independent CAN 2.0B blocks, which are certified

CAN conformant.

Special Function Peripherals

GPIO

The PSoC 4200L has 96 GPIOs. The GPIO block implements

the following:

LCD Segment Drive

The PSoC 4200L has an LCD controller, which can drive up to

eight commons and up to 56 segments. Any pin can be either a

common or a segment pin. It uses full digital methods to drive the

LCD segments requiring no generation of internal LCD voltages.

The two methods used are referred to as digital correlation and

PWM.

■ Eight drive strength modes including strong push-pull, resistive

pull-up and pull-down, weak (resistive) pull-up and pull-down,

open drain and open source, input only, and disabled

■ Input threshold select (CMOS or LVTTL)

■ Individual control of input and output disables

Digital correlation pertains to modulating the frequency and

levels of the common and segment signals to generate the

highest RMS voltage across a segment to light it up or to keep

the RMS signal zero. This method is good for STN displays but

may result in reduced contrast with TN (cheaper) displays.

■ Hold mode for latching previous state (used for retaining I/O

state in Deep Sleep mode and Hibernate modes)

■ Selectable slew rates for dV/dt related noise control to improve

EMI

PWM pertains to driving the panel with PWM signals to effec-

tively use the capacitance of the panel to provide the integration

of the modulated pulse-width to generate the desired LCD

voltage. This method results in higher power consumption but

can result in better results when driving TN displays.

The pins are organized in logical entities called ports, which are

8-bit in width. During power-on and reset, the blocks are forced

to the disable state so as not to crowbar any inputs and/or cause

excess turn-on current. A multiplexing network known as a

high-speed I/O matrix is used to multiplex between various

signals that may connect to an I/O pin. Pin locations for

fixed-function peripherals are also fixed to reduce internal multi-

plexing complexity (these signals do not go through the DSI

network). DSI signals are not affected by this and any pin may

be routed to any UDB through the DSI network, with the

exception of pins from Port 7, 8, and 9.

CapSense

CapSense is supported on all pins in the PSoC 4200L through

two CapSense Sigma-Delta (CSD) blocks that can be connected

to any pin through an analog mux bus that any GPIO pin can be

connected to via an Analog switch. CapSense function can thus

be provided on any pin or group of pins in a system under

software control. A component is provided for the CapSense

block to make it easy for the user.

Data output and pin state registers store, respectively, the values

to be driven on the pins and the states of the pins themselves.

Shield voltage can be driven on another Mux Bus to provide

water tolerance capability. Water tolerance is provided by driving

the shield electrode in phase with the sense electrode to keep

the shield capacitance from attenuating the sensed input.

Every I/O pin can generate an interrupt if so enabled and each

I/O port has an interrupt request (IRQ) and interrupt service

routine (ISR) vector associated with it (13 for PSoC 4200L).

There are 14 GPIO pins that are overvoltage tolerant (V_INcan

exceed V_DD). The overvoltage cells will not sink more than 10 µA

when their inputs exceed V_DDIOin compliance with I²C specifi-

cations. Meeting the I²C minimum fall time requirement for FM

and FM+ may require the slower slew rate setting depending on

bus loading (also applies to all GPIO and SIO pins).

Each CapSense block has two IDACs which can be used for

general purposes if CapSense is not being used.(both IDACs are

available in that case) or if CapSense is used without water

tolerance (one IDAC is available). The two CapSense blocks can

be used independently.

SIO

The Special I/O (SIO) pins have the following features in addition

to the GPIO features:

■ Overvoltage protection and hot swap capability

■ Programmable switching thresholds

■ Programmable output pull-up voltage capability

Document Number: 001-91686 Rev. *K

Page 9 of 47

PSoC^™4: PSoC 4200L Datasheet

Pinouts

The following is the pin list for the PSoC 4200L.

124-BGA

Name

68-QFN

Name

64-TQFP

Name

48-TQFP

Name

48-TQFP-USB

Name

P0.0

H13

H12

G13

G12

K10

G11

F13

F12

F11

E13

E12

E11

D13

D12

C13

C12

B12

C11

A12

D10

B13

A13

A11

B11

A10

B10

C10

A9

42

43

44

45

39

40

41

42

28

29

30

31

28

29

30

31

P0.0

P0.1

P0.2

P0.3

VSSD

P0.4

P0.5

P0.6

P0.7

P8.0

P8.1

P8.2

P8.3

P8.4

P8.5

P8.6

P8.7

XRES

VCCD

VSSD

VDDD

P9.0

P9.1

P9.2

P9.3

P9.4

P9.5

P9.6

P9.7

P0.0

P0.1

P0.2

P0.3

P0.0

P0.1

P0.2

P0.3

P0.0

P0.1

P0.2

P0.3

P0.1

P0.2

P0.3

46

47

48

49

P0.4

P0.5

P0.6

P0.7

43

44

45

46

P0.4

P0.5

P0.6

P0.7

32

33

34

35

P0.4

P0.5

P0.6

P0.7

32

33

34

35

P0.4

P0.5

P0.6

P0.7

50

51

52

53

XRES

VCCD

VSSD

VDDD

47

48

49

50

XRES

VCCD

VSSD

VDDD

36

37

38

39

XRES

VCCD

VSSD

VDDD

36

37

38

39

XRES

VCCD

VSSD

VDDD

B9

C9

40

VDDA

40

VDDA

C8

B8

A8

A7

B7

C7

A6

B6

A2

B2

P5.0

P5.1

P5.2

P5.3

P5.4

P5.5

P5.6

P5.7

VDDA

54

55

56

57

58

59

P5.0

P5.1

P5.2

P5.3

P5.4

P5.5

51

52

53

54

P5.0

P5.1

P5.2

P5.3

55

P5.5

60

VDDA

56

VDDA

40

VDDA

40

VDDA

Document Number: 001-91686 Rev. *K

Page 10 of 47

PSoC^™4: PSoC 4200L Datasheet

124-BGA

Name

68-QFN

Name

64-TQFP

Name

48-TQFP

Name

48-TQFP-USB

Name

C3

C5

B5

A5

A4

B4

C4

A3

B3

B1

C3

D4

B2

C1

C2

D1

D2

D3

E1

E2

E3

K4

A1

F1

F2

F3

G1

G2

G3

H1

H2

K4

J1

61

62

63

64

65

66

67

68

1

57

58

59

60

61

62

63

64

1

41

42

43

44

45

46

47

48

1

41

42

43

44

45

46

47

48

1

VSSA

P1.0

VSSA

P1.0

VSSA

P1.0

VSSA

P1.0

VSSA

P1.0

P1.1

P1.2

P1.3

P1.4

P1.5

P1.6

P1.7

P1.7/VREF

VREF

VSSA

VDDA

P2.0

1

2

3

P2.0

P2.1

P2.2

P2.3

P2.4

P2.5

P2.6

P2.7

VSSA

VDDA

2

3

P2.0

P2.1

P2.2

P2.3

P2.4

P2.5

P2.6

P2.7

VSSA

VDDA

2

3

P2.0

P2.1

P2.2

P2.3

P2.4

P2.5

P2.6

P2.7

VSSD

2

3

P2.0

P2.1

P2.2

P2.3

P2.4

P2.5

P2.6

P2.7

VSSD

P2.1

P2.2

4

P2.3

5

P2.4

6

P2.5

7

P2.6

8

P2.7

9

VSSD

VDDA

P10.0

P10.1

P10.2

P10.3

P10.4

P10.5

P10.6

P10.7

VSSD

P6.0

10

11

10

11

10

12

13

14

15

16

17

18

19

20

21

P6.0

P6.1

12

13

14

P6.0

P6.1

P6.2

J2

P6.1

J3

P6.2

K1

K2

L1

P6.3

P6.4

P6.4/P12.0

P6.5/P12.1

VSSIO

P3.0

15

16

17

18

19

20

P6.4/P12.0

P6.5/P12.1

VSSIO

P12.0

P12.1

P6.5

L2

K3

L3

VSSD

P3.0

10

12

13

14

VSSD

P3.0

P3.1

P3.2

10

12

13

14

VSSD

P3.0

P3.1

P3.2

N2

M2

N3

P3.0

P3.1

P3.2

Document Number: 001-91686 Rev. *K

Page 11 of 47

PSoC^™4: PSoC 4200L Datasheet

124-BGA

Name

68-QFN

Name

64-TQFP

Name

48-TQFP

Name

48-TQFP-USB

Name

P3.3

M3

N4

22

23

24

25

26

27

21

22

23

24

25

26

16

17

18

19

20

21

16

17

18

19

20

21

P3.3

P3.4

P3.3

P3.4

P3.3

P3.4

P3.3

P3.4

M4

N5

P3.5

P3.6

M5

M1

N1

P3.7

VDDIO

P11.0

P11.1

P11.2

P11.3

P11.4

P11.5

P11.6

P11.7

VDDIO

P4.0

VDDIO

N6

M6

L6

N7

M7

L7

N8

M8

N12

N13

L8

27

28

29

30

31

32

33

34

35

VDDIO

P4.0

26

27

28

29

30

31

32

33

VDDIO

P4.0

21

22

23

24

25

VDDIO

P4.0

21

22

VDDIO

P4.0

N9

P4.1

M9

N10

M10

N11

M11

M12

L11

L12

L13

M13

L9

P4.2

P4.3

P4.4

P4.5

P4.6

P4.7

VSSD

D+/P13.0

D-/P13.1

VBUS/P13.2

P7.0

36

37

38

39

40

41

D+/P13.0

D-/P13.1

VBUS/P13.2

P7.0

34

35

36

37

38

D+/P13.0

D-/P13.1

VBUS/P13.2

P7.0

23

24

25

26

27

D+/P13.0

D-/P13.1

VBUS/P13.2

P7.0

26

27

P7.0

P7.1

L10

K13

K12

K11

J13

J12

J11

P7.1

P7.2

P7.3

P7.4

P7.5

P7.6

P7.7

Port 12 (Port pins 12.0 and 12.1) are SIO pins.

Port 13 (Port pins 13.0 and 13.1) require VBUS (P13.2) to be powered.

Ports 6 (Port pins P6.0..6.5) and 9 (Port pins 9.0..9.7) are overvoltage tolerant (GPIO_OVT)

Balls C6, D11, H11, H3, L4, and L5 are No Connects (NC) on the 124-BGApackage. Pins 11 and 15 are NC on the 48-TQFP packages.

Document Number: 001-91686 Rev. *K

Page 12 of 47

PSoC^™4: PSoC 4200L Datasheet

Each of the pins shown in the previous table can have multiple programmable functions as shown in the following table.

Port/Pin

Analog

USB

Alt. Function 1

Alt. Function 2

Alt. Function 3

Alt. Function 4

Alt. Function 5

P0.0

lpcomp.in_p[0]

can[1].can_rx:0

usb.vbus_valid

scb[0].spi_select1:3

P0.1

P0.2

P0.3

P0.4

P0.5

P0.6

P0.7

lpcomp.in_n[0]

lpcomp.in_p[1]

lpcomp.in_n[1]

wco_in

can[1].can_tx:0

scb[0].spi_select2:3

scb[0].spi_select3:3

scb[1].uart_rx:0

scb[1].uart_tx:0

scb[1].uart_cts:0

scb[1].uart_rts:0

scb[1].i2c_scl:0

scb[1].i2c_sda:0

scb[1].spi_mosi:0

scb[1].spi_miso:0

scb[1].spi_clk:0

wco_out

srss.ext_clk:0

can[1].can_tx-

_enb_n:0

srss.wakeup

scb[1].spi_select0:0

P8.0

P8.1

P8.2

P8.3

P8.4

P8.5

P8.6

P8.7

P9.0

P9.1

P9.2

P9.3

P9.4

P9.5

P9.6

P9.7

P5.0

scb[3].uart_rx:0

scb[3].uart_tx:0

scb[3].uart_cts:0

scb[3].uart_rts:0

scb[3].i2c_scl:0

scb[3].i2c_sda:0

lpcomp.comp[0]:0

lpcomp.comp[1]:0

scb[3].spi_mosi:0

scb[3].spi_miso:0

scb[3].spi_clk:0

scb[3].spi_select0:0

scb[3].spi_select1:0

scb[3].spi_select2:0

scb[3].spi_select3:0

tcpwm.line[0]:2

tcpwm.line_compl[0]:2

tcpwm.line[1]:2

scb[0].uart_rx:0

scb[0].uart_tx:0

scb[0].uart_cts:0

scb[0].uart_rts:0

scb[0].i2c_scl:0

scb[0].i2c_sda:0

scb[0].spi_mosi:0

scb[0].spi_miso:0

scb[0].spi_clk:0

tcpwm.line_compl[1]:2

tcpwm.line[2]:2

scb[0].spi_select0:0

scb[0].spi_select1:0

scb[0].spi_select2:0

scb[0].spi_select3:0

tcpwm.line_compl[2]:2

tcpwm.line[3]:2

scb[3].i2c_scl:3

scb[3].i2c_sda:3

scb[2].i2c_scl:0

tcpwm.line_compl[3]:2

tcpwm.line[4]:2

ctb1_pads[0]

csd[1].c_mod

scb[2].uart_rx:0

scb[2].uart_tx:0

scb[2].uart_cts:0

scb[2].uart_rts:0

scb[2].spi_mosi:0

scb[2].spi_miso:0

scb[2].spi_clk:0

P5.1

P5.2

P5.3

ctb1_pads[1]

csd[1].c_sh_tank

tcpwm.line_compl[4]:2

tcpwm.line[5]:2

scb[2].i2c_sda:0

lpcomp.comp[0]:1

lpcomp.comp[1]:1

ctb1_pads[2]

ctb1_oa0_out_10x

ctb1_pads[3]

ctb1_oa1_out_10x

tcpwm.line_compl[5]:2

scb[2].spi_select0:0

P5.4

P5.5

P5.6

P5.7

P1.0

ctb1_pads[4]

ctb1_pads[5]

ctb1_pads[6]

ctb1_pads[7]

ctb0_pads[0]

tcpwm.line[6]:2

tcpwm.line_compl[6]:2

tcpwm.line[7]:2

scb[2].spi_select1:0

scb[2].spi_select2:0

scb[2].spi_select3:0

tcpwm.line_compl[7]:2

tcpwm.line[2]:1

scb[0].uart_rx:1

scb[0].uart_tx:1

scb[0].uart_cts:1

scb[0].uart_rts:1

scb[0].i2c_scl:1

scb[0].i2c_sda:1

scb[0].spi_mosi:1

scb[0].spi_miso:1

scb[0].spi_clk:1

P1.1

P1.2

P1.3

P1.4

ctb0_pads[1]

tcpwm.line_compl[2]:1

tcpwm.line[3]:1

ctb0_pads[2]

ctb0_oa0_out_10x

ctb0_pads[3]

ctb0_oa1_out_10x

tcpwm.line_compl[3]:1

tcpwm.line[6]:1

scb[0].spi_select0:1

scb[0].spi_select1:1

ctb0_pads[4]

Document Number: 001-91686 Rev. *K

Page 13 of 47

PSoC^™4: PSoC 4200L Datasheet

Port/Pin

P1.5

Analog

USB

Alt. Function 1

tcpwm.line_compl[6]:1

tcpwm.line[7]:1

Alt. Function 2

Alt. Function 3

Alt. Function 4

Alt. Function 5

scb[0].spi_select2:1

scb[0].spi_select3:1

ctb0_pads[5]

ctb0_pads[6]

P1.6

P1.7

ctb0_pads[7],

sar_ext_vref

tcpwm.line_compl[7]:1

P2.0

P2.1

sarmux_pads[0]

sarmux_pads[1]

sarmux_pads[2]

sarmux_pads[3]

sarmux_pads[4]

sarmux_pads[5]

sarmux_pads[6]

sarmux_pads[7]

tcpwm.line[4]:1

tcpwm.line_compl[4]:1

tcpwm.line[5]:1

scb[1].uart_rx:1

scb[1].uart_tx:1

scb[1].uart_cts:1

scb[1].uart_rts:1

scb[1].i2c_scl:1

scb[1].i2c_sda:1

scb[1].spi_mosi:1

scb[1].spi_miso:1

scb[1].spi_clk:1

P2.2

P2.3

tcpwm.line_compl[5]:1

tcpwm.line[0]:1

scb[1].spi_select0:1

scb[1].spi_select1:0

scb[1].spi_select2:0

scb[1].spi_select3:0

P2.4

P2.5

tcpwm.line_compl[0]:1

tcpwm.line[1]:1

P2.6

P2.7

tcpwm.line_compl[1]:1

P10.0

P10.1

P10.2

P10.3

P10.4

P10.5

P10.6

P10.7

P6.0

scb[2].uart_rx:1

scb[2].uart_tx:1

scb[2].uart_cts:1

scb[2].uart_rts:1

scb[2].i2c_scl:1

scb[2].i2c_sda:1

scb[2].spi_mosi:1

scb[2].spi_miso:1

scb[2].spi_clk:1

scb[2].spi_select0:1

scb[2].spi_select1:1

scb[2].spi_select2:1

scb[2].spi_select3:1

tcpwm.line[4]:0

scb[3].uart_rx:1

can[0].can_tx-

_enb_n:0

scb[3].i2c_scl:1

scb[3].spi_mosi:1

P6.1

P6.2

tcpwm.line_compl[4]:0

tcpwm.line[5]:0

scb[3].uart_tx:1

scb[3].uart_cts:1

scb[3].uart_rts:1

can[0].can_rx:0

can[0].can_tx:0

scb[3].i2c_sda:1

scb[2].i2c_scl:3

scb[2].i2c_sda:3

scb[0].i2c_scl:3

scb[1].i2c_scl:3

scb[1].i2c_sda:3

scb[0].i2c_sda:3

scb[1].i2c_scl:2

scb[1].i2c_sda:2

cpuss.swd_data:0

cpuss.swd_clk:0

scb[3].spi_miso:1

scb[3].spi_clk:1

P6.3

tcpwm.line_compl[5]:0

tcpwm.line[6]:0

scb[3].spi_select0:1

scb[3].spi_select1:1

scb[3].spi_select3:1

P6.4

P12.0

P12.1

P6.5

tcpwm.line[7]:0

tcpwm.line_compl[7]:0

tcpwm.line_compl[6]:0

tcpwm.line[0]:0

scb[3].spi_select2:1

scb[1].spi_mosi:2

scb[1].spi_miso:2

scb[1].spi_clk:2

P3.0

scb[1].uart_rx:2

scb[1].uart_tx:2

scb[1].uart_cts:2

scb[1].uart_rts:2

P3.1

tcpwm.line_compl[0]:0

tcpwm.line[1]:0

P3.2

P3.3

tcpwm.line_compl[1]:0

tcpwm.line[2]:0

scb[1].spi_select0:2

scb[1].spi_select1:1

scb[1].spi_select2:1

scb[1].spi_select3:1

P3.4

P3.5

tcpwm.line_compl[2]:0

tcpwm.line[3]:0

P3.6

P3.7

tcpwm.line_compl[3]:0

tcpwm.line[4]:3

P11.0

P11.1

P11.2

P11.3

P11.4

P11.5

P11.6

P11.7

P4.0

scb[2].uart_rx:2

scb[2].uart_tx:2

scb[2].uart_cts:2

scb[2].uart_rts:2

scb[2].i2c_scl:2

scb[2].i2c_sda:2

cpuss.swd_data:1

cpuss.swd_clk:1

scb[2].spi_mosi:2

scb[2].spi_miso:2

scb[2].spi_clk:2

tcpwm.line_compl[4]:3

tcpwm.line[5]:3

tcpwm.line_compl[5]:3

tcpwm.line[6]:3

scb[2].spi_select0:2

scb[2].spi_select1:2

scb[2].spi_select2:2

scb[2].spi_select3:2

tcpwm.line_compl[6]:3

tcpwm.line[7]:3

tcpwm.line_compl[7]:3

scb[0].uart_rx:2

scb[0].uart_tx:2

can[0].can_rx:1

can[0].can_tx:1

scb[0].i2c_scl:2

scb[0].i2c_sda:2

scb[0].spi_mosi:2

scb[0].spi_miso:2

P4.1

Document Number: 001-91686 Rev. *K

Page 14 of 47

PSoC^™4: PSoC 4200L Datasheet

Port/Pin

Analog

USB

Alt. Function 1

Alt. Function 2

Alt. Function 3

Alt. Function 4

Alt. Function 5

P4.2

csd[0].c_mod

scb[0].uart_cts:2

can[0].can_tx-

_enb_n:1

lpcomp.comp[0]:2

scb[0].spi_clk:2

P4.3

P4.4

csd[0].c_sh_tank

scb[0].uart_rts:2

lpcomp.comp[1]:2

scb[0].spi_select0:2

scb[0].spi_select1:2

can[1].can_tx-

_enb_n:1

P4.5

P4.6

P4.7

P13.0

P13.1

P13.2

P7.0

P7.1

P7.2

P7.3

P7.4

P7.5

P7.6

P7.7

can[1].can_rx:1

can[1].can_tx:1

scb[0].spi_select2:2

scb[0].spi_select3:2

USBDP

USBDM

VBUS

srss.eco_in

tcpwm.line[0]:3

tcpwm.line_compl[0]:3

tcpwm.line[1]:3

scb[3].uart_rx:2

scb[3].uart_tx:2

scb[3].uart_cts:2

scb[3].uart_rts:2

scb[3].i2c_scl:2

scb[3].i2c_sda:2

scb[3].spi_mosi:2

scb[3].spi_miso:2

scb[3].spi_clk:2

srss.eco_out

tcpwm.line_compl[1]:3

tcpwm.line[2]:3

scb[3].spi_select0:2

scb[3].spi_select1:2

scb[3].spi_select2:2

scb[3].spi_select3:2

tcpwm.line_compl[2]:3

tcpwm.line[3]:3

tcpwm.line_compl[3]:3

Descriptions of the power pin functions are as follows:

range is also designed for battery-powered operation, for

instance, the chip can be powered from a battery system that

starts at 3.5 V and works down to 1.8 V. In this mode, the internal

regulator of the PSoC 4200L supplies the internal logic and the

VCCD output of the PSoC 4200L must be bypassed to ground

via an external Capacitor (in the range of 1 to 1.6 µF; X5R

ceramic or better).

VDDD: Power supply for both analog and digital sections (where

there is no V_DDApin)

VDDA: Analog V_DDpin where package pins allow; should be

present before or concurrently with VDDD and the value of

VDDA should be equal to or higher than VDDD and VDDIO

VDDIO: I/O pin power domain. It should not be present without

VDDD.

VDDAand VDDD must be shorted together on the PC board; the

grounds, VSSA and VSS must also be shorted together. Bypass

capacitors must be used from VDDD and VDDA to ground,

typical practice for systems in this frequency range is to use a

capacitor in the 1 µF range in parallel with a smaller capacitor

(0.1 µF, for example). Note that these are simply rules of thumb

and that, for critical applications, the PCB layout, lead induc-

tance, and the bypass capacitor parasitic should be simulated to

design and obtain optimal bypassing.

VSSA: Analog ground pin where package pins allow; shorted to

VSS otherwise

VSS: Ground pin

VCCD: Regulated digital supply (1.8 V ±5%)

VBUS: USB voltage. There is no constraint on VBUS with

respect to VDDD. However, since it comes from USB, it is

typically assumed to and ideally be 5 V (4.35 to 5.5 V is the

range).

Power Supply

Bypass Capacitors

VDDD–VSS and 0.1 µF ceramic at each pin plus bulk

GPIO and GPIO_OVT pins can be used as CSD sense and

shield pins (a total of 94). Up to 64 of the pins can be used for

LCD drive.

VDDIO-VSS

VDDA–VSSA

capacitor 1 to 10 µF.

0.1 µF ceramic at pin. Additional 1 µF to

10 µF bulk capacitor

The following packages are supported: 124-ball BGA, 64-pin

TQFP, 68-pin QFN, and 48-pin TQFP.

VCCD–VSS

1 µF ceramic capacitor at the VCCD pin

VREF–VSSA

(optional)

The internal bandgap may be bypassed

with a 1 µF to 10 µF capacitor for better

ADC performance.

Power

The supply voltage range is 1.71 V to 5.5 V with all functions and

circuits operating over that range.

Regulated External Supply

In this mode, the PSoC 4200L is powered by an external power

supply that must be within the range of 1.71 V to 1.89 V (1.8

±5%); note that this range needs to include power supply ripple.

In this mode, the VCCD and VDDD pins are shorted together and

bypassed. The internal regulator is disabled in firmware.

The PSoC 4200L family allows two distinct modes of power

supply operation: Unregulated External Supply and Regulated

External Supply modes.

Unregulated External Supply

In this mode, the PSoC 4200L is powered by an External Power

Supply that can be anywhere in the range of 1.8 V to 5.5 V. This

Document Number: 001-91686 Rev. *K

Page 15 of 47

PSoC^™4: PSoC 4200L Datasheet

Electrical Specifications

Absolute Maximum Ratings

Table 1. Absolute Maximum Ratings^[1]

Details/

Spec ID#

SID1

Parameter

Description

Min

Typ

Max

Units

Conditions

V_{DD_ABS}

Analog or digital supply relative to V_SS

–0.5

–

6

V

Absolute

(V_SSD= V_SSA

)

maximum

SID2

V_{CCD_ABS}

V_{GPIO_ABS}

I_{GPIO_ABS}

Direct digital core voltage input relative

to V_SSD

–0.5

–25

–

1.95

V

Absolute

maximum

SID3

GPIO voltage; V_DDDor V_DDA

V_DD+ 0.5

Absolute

maximum

SID4

Current per GPIO

25

0.5

–

mA

V

Absolute

maximum

SID5

I_{G-PIO_injection}GPIO injection current per pin

–0.5

2200

500

Absolute

maximum

BID44

BID45

BID46

ESD_HBM

ESD_CDM

LU

Electrostatic discharge human body

model

Electrostatic discharge charged device

model

–

V

Pin current for latch-up

–140

140

mA

Device Level Specifications

All specifications are valid for –40 °C  T_A 105 °C and T_J 125 °C, except where noted. Specifications are valid for 1.71 V to 5.5 V,

except where noted.

Table 2. DC Specifications

Details/

Spec ID#

SID53

Parameter

V_DDD

Description

Min

Typ

Max

Units

Conditions

Power Supply Input Voltage (V_DDA

=

1.8

–

5.5

V

With regulator

enabled

V_DDD= V_DD)

SID255

V_DDD

Power supply input voltage unregulated

1.71

1.8

1.89

V

Internally unregu-

lated Supply

SID54

SID55

V_CCD

C_EFC

Output voltage (for core logic)

–

1

1.8

1.3

–

V

External Regulator voltage (V_CCD

bypass

)

1.6

µF

X5R ceramic or

better

SID56

C_EXC

Power supply decoupling capacitor

–

1

–

µF

X5R ceramic or

better

Active Mode

SID6

I_DD1

I_DD2

I_DD3

I_DD4

Execute from flash; CPU at 6 MHz

Execute from flash; CPU at 12 MHz

Execute from flash; CPU at 24 MHz

Execute from flash; CPU at 48 MHz

–

2.2

3.7

3.1

4.8

mA

SID7

SID8

6.7

8.0

SID9

12.8

14.5

Sleep Mode

SID21

I_DD16

I_DD17

I²C wakeup, WDT, and Comparators on.

Regulator Off.

I²C wakeup, WDT, and Comparators on.

–

1.8

1.7

2.2

2.1

mA

V_DD= 1.71 to

1.89, 6 MHz

SID22

V_DD= 1.8 to 5.5,

6 MHz

Note

1. Usage above the absolute maximum conditions listed in Table 1 may cause permanent damage to the device. Exposure to absolute maximum conditions for extended

periods of time may affect device reliability. The maximum storage temperature is 150 °C in compliance with JEDEC Standard JESD22-A103, High Temperature

Storage Life. When used below absolute maximum conditions but above normal operating conditions, the device may not operate to specification.

Document Number: 001-91686 Rev. *K

Page 16 of 47

PSoC^™4: PSoC 4200L Datasheet

Table 2. DC Specifications

Details/

Spec ID#

SID23

Parameter

I_DD18

Description

Min

Typ

Max

Units

Conditions

I²C wakeup, WDT, and Comparators on.

Regulator Off.

–

2.4

2.9

mA

V_DD= 1.71 to

1.89, 12 MHz

SID24

I_DD19

I²C wakeup, WDT, and Comparators on.

–

2.3

2.8

mA

V_DD= 1.8 to 5.5,

12 MHz

Deep Sleep Mode, –40 °C to + 60 °C

SID30

SID31

SID32

I_DD25

I_DD26

I_DD27

I²C wakeup and WDT on. Regulator Off.

I²C wakeup and WDT on.

–

1.3

–

13.5

20.0

µA

V_DD= 1.71 to 1.89

V_DD= 1.8 to 3.6

V_DD= 3.6 to 5.5

Deep Sleep Mode, +85 °C

SID33

SID34

SID35

I_DD28

I_DD29

I_DD30

I²C wakeup and WDT on. Regulator Off.

I²C wakeup and WDT on.

–

15

–

45.0

60.0

45.0

µA

V_DD= 1.71 to 1.89

V_DD= 1.8 to 3.6

V_DD= 3.6 to 5.5

Hibernate Mode, –40 °C to + 60 °C

SID39

SID40

SID41

I_DD34

I_DD35

I_DD36

Regulator Off.

–

150

–

1123

1600

nA

V_DD= 1.71 to 1.89

V_DD= 1.8 to 3.6

V_DD= 3.6 to 5.5

Hibernate Mode, +85 °C

SID42

I_DD37

I_DD38

I_DD39

Regulator Off.

–

4142

9700

nA

V_DD= 1.71 to 1.89

V_DD= 1.8 to 3.6

V_DD= 3.6 to 5.5

SID43

SID44

10,400

Stop Mode

SID304

I_DD43A

I_DD43B

Stop Mode current; V_DD= 3.6 V

–

20

–

659

nA

T = –40 °C to +60

°C

SID304A

1810

T = +85 °C

XRES current

SID307

I_{DD_XR}

Supply current while XRES (Active Low)

asserted

–

2

5

mA

Table 3. AC Specifications

Details/

Spec ID#

SID48

Parameter

F_CPU

Description

CPU frequency

Min

DC

–

Typ

Max

Units

Conditions

–

0

48

–

MHz 1.71 V_DD5.5

SID49

T_SLEEP

Wakeup from sleep mode

µs

Guaranteed by

characterization

SID50

T_DEEPSLEEP

Wakeup from Deep Sleep mode

–

25

µs

24-MHz IMO.

Guaranteed by

characterization

SID51

SID51A

SID52

T_HIBERNATE

T_STOP

Wakeup from Hibernate mode

Wakeup from Stop mode

External reset pulse width

–

1

–

0.7

1.9

–

ms

µs

Guaranteed by

characterization

Guaranteed by

characterization

T_RESETWIDTH

Guaranteed by

characterization

Document Number: 001-91686 Rev. *K

Page 17 of 47

PSoC^™4: PSoC 4200L Datasheet

GPIO

Table 4. GPIO DC Specifications

Details/

Spec ID#

SID57

Parameter

Description

Min

Typ

Max

Units

Conditions

CMOS Input

Per I²C Spec

[2]

V_IH

Input voltage high threshold

0.7 × V_DDD

–

V

SID57A

I_IHS

V_IL

Input current when Pad > V_DDIOfor

OVT inputs

10

µA

SID58

Input voltage low threshold

–

0.3 ×

V_DDD

V

CMOS Input

[2]

SID241

SID242

V_IH

V_IL

LVTTL input, V_DDD< 2.7 V

0.7 × V_DDD

–

V

0.3 ×

V_DDD

[2]

SID243

SID244

SID59

V_IH

V_IL

LVTTL input, V_DDD 2.7 V

Output voltage high level

2.0

–

0.8

–

V

V_OH

V_OL

V_DDD– 0.6

I_OH= 4 mA,

V_DDD 3 V

SID60

SID61

SID62

SID62A

Output voltage high level

Output voltage low level

V_DDD– 0.5

–

V

I_OH= 1 mA at

1.8 V V_DDD

–

0.6

0.4

I_OL= 4 mA at

1.8 V V_DDD

I_OL= 8 mA,

V_DDD 3 V

I_OL= 3 mA,

V_DDD 3 V

SID63

SID64

SID65

R_PULLUP

R_PULLDOWN

I_IL

Pull-up resistor

3.5

–

5.6

–

8.5

2

kΩ

nA

Pull-down resistor

Input leakage current (absolute value)

25 °C, V_DDD

3.0 V

=

SID65A

SID66

I_{IL_CTBM}

C_IN

Input leakage current (absolute value)

for CTBM pins

–

4

7

nA

pF

Input capacitance

Not applicable

for P6.4, P6.5,

P12.0, P12.1,

and for USB

pins.

SID67

SID68

V_HYSTTL

Input hysteresis LVTTL

Input hysteresis CMOS

25

40

–

mV

V_DDD 2.7 V

V_HYSCMOS

0.05 ×

V_DDD

SID69

I_DIODE

Current through protection diode to

–

100

200

µA

Guaranteed by

characterization

V_DD/Vss

SID69A

I_{TOT_GPIO}

Maximum Total Source or Sink Chip

Current

–

mA

Guaranteed by

characterization

Note

2.

V

must not exceed V

+ 0.2 V.

IH

DDD

Document Number: 001-91686 Rev. *K

Page 18 of 47

PSoC^™4: PSoC 4200L Datasheet

Table 5. GPIO AC Specifications

(Guaranteed by Characterization)^[3]

Details/

Spec ID#

SID70

Parameter

T_RISEF

Description

Min

Typ

Max

Units

Conditions

Rise time in fast strong mode

2

–

12

ns

3.3 V V_DDD

,

Cload = 25 pF

SID71

SID72

SID73

SID74

T_FALLF

Fall time in fast strong mode

Rise time in slow strong mode

Fall time in slow strong mode

2

10

–

12

60

33

ns

3.3 V V_DDD

Cload = 25 pF

,

T_RISES

T_FALLS

F_GPIOUT1

3.3 V V_DDD

Cload = 25 pF

,

ns

3.3 V V_DDD,

Cload = 25 pF

GPIO Fout;3.3 V  V_DDD5.5 V. Fast

strong mode.

MHz

90/10%, 25 pF

load, 60/40 duty

cycle

SID75

SID76

SID245

F_GPIOUT2

F_GPIOUT3

F_GPIOUT4

F_GPIOIN

GPIO Fout;1.7 VV_DDD3.3 V. Fast

–

16.7

7

MHz

90/10%, 25 pF

load, 60/40 duty

cycle

strong mode.

GPIO Fout;3.3 V V_DDD5.5 V. Slow

strong mode.

90/10%, 25 pF

load, 60/40 duty

cycle

GPIO Fout;1.7 V V_DDD3.3 V. Slow

strong mode.

3.5

48

90/10%, 25 pF

load, 60/40 duty

cycle

SID246

GPIO input operating frequency;

90/10% V_IO

1.71 V V_DDD5.5 V

XRES

Table 6. XRES DC Specifications

Details/

Spec ID#

SID77

Parameter

V_IH

Description

Min

Typ

Max

Units

Conditions

Input voltage high threshold

0.7 ×

V_DDD

–

V

CMOS Input

SID78

V_IL

Input voltage low threshold

–

0.3 ×

V_DDD

V

SID79

SID80

SID81

R_PULLUP

C_IN

Pull-up resistor

3.5

–

5.6

3

8.5

–

kΩ

pF

Input capacitance

Input voltage hysteresis

V_HYSXRES

–

100

–

mV

Guaranteed by

characterization

SID82

I_DIODE

Current through protection diode to

–

100

µA

Guaranteed by

characterization

V_DDD/V_SS

Table 7. XRES AC Specifications

Details/

Spec ID#

SID83

Parameter

Description

Min

Typ

Max

Units

Conditions

T_RESETWIDTHReset pulse width

1

–

µs

Guaranteed by

characterization

Note

3. Simultaneous switching transitions on many fully-loaded GPIO pins may cause ground perturbations depending on several factors including PCB and decoupling

capacitor design. For applications that are very sensitive to ground perturbations, the slower GPIO slew rate setting may be used.

Document Number: 001-91686 Rev. *K

Page 19 of 47

PSoC^™4: PSoC 4200L Datasheet

Analog Peripherals

Opamp

Table 8. Opamp Specifications

(Guaranteed by Characterization)

Spec ID#

Parameter

I_DD

Description

Opamp block current. No load.

Power = high

Min

Typ

–

Max

Units

–

Details/Conditions

–

1850

950

350

–

SID269

SID270

SID271

I_{DD_HI}

1100

550

150

–

µA

–

I_{DD_MED}

Power = medium

–

I_{DD_LOW}

Power = low

–

GBW

Load = 20 pF, 0.1 mA. V_DDA= 2.7 V

Power = high

–

SID272

SID273

SID274

GBW_HI

GBW_MED

GBW_LO

I_{OUT_MAX}

I_{OUT_MAX_HI}

I_{OUT_MAX_MID}

I_{OUT_MAX_LO}

I_OUT

6

–

MHz

–

Power = medium

4

–

Power = low

–

1

–

V_DDA 2.7 V, 500 mV from rail

Power = high

–

SID275

SID276

SID277

10

–

mA

–

Power = medium

–

Power = low

5

–

V_DDA= 1.71 V, 500 mV from rail

Power = high

–

SID278

SID279

SID280

SID281

I_{OUT_MAX_HI}

I_{OUT_MAX_MID}

I_{OUT_MAX_LO}

V_IN

4

–

mA

V

Power = medium

4

–

Power = low

–

2

–

Input voltage range

–0.05

–

V_DDA

0.2

–

Charge-pump on, V_DDA

2.7 V

SID282

V_CM

Input common mode voltage

–0.05

–

VDDA

– 0.2

V

Charge-pump on, V_DDA

2.7 V

V_OUT

V_DDA 2.7 V

–

SID283

SID284

SID285

SID286

V_{OUT_1}

Power = high, I_load=10 mA

0.5

VDDA

– 0.5

V

V_{OUT_2}

V_{OUT_3}

V_{OUT_4}

Power = high, I_load=1 mA

Power = medium, I_load=1 mA

Power = low, I_load=0.1mA

0.2

–

VDDA

– 0.2

VDDA

– 0.2

VDDA

– 0.2

SID288

V_{OS_TR}

V_{OS_DR_TR}

CMRR

Offset voltage, trimmed

Offset voltage drift, trimmed

DC

1

–

±0.5

±1

1

–

mV

High mode

Medium mode

Low mode

SID288A

SID288B

SID290

–

±2

–

mV

–10

–

±3

10

–

µV/°C

dB

High mode

SID290A

SID290B

SID291

SID292

±10

70

Medium mode

Low mode

–

60

70

–

V

_DDD= 3.6 V

PSRR

At 1 kHz, 100 mV ripple

85

–

dB

VDDD = 3.6 V

Noise

–

SID293

SID294

V_N1

Input referred, 1 Hz - 1GHz, power =

high

–

94

–

µVrms

V_N2

Input referred, 1 kHz, power = high

–

72

–

nV/rtHz

Document Number: 001-91686 Rev. *K

Page 20 of 47

PSoC^™4: PSoC 4200L Datasheet

Table 8. Opamp Specifications

(Guaranteed by Characterization) (continued)

Spec ID#

SID295

Parameter

V_N3

Description

Min

–

Typ

28

15

–

Max

–

Units

nV/rtHz

pF

Details/Conditions

Input referred, 10kHz, power = high

Input referred, 100kHz, power = high

SID296

V_N4

–

SID297

Cload

Stable up to maximum load. Perfor-

mance specs at 50 pF.

–

125

SID298

SID299

SID299A

Slew_rate

Cload = 50 pF, Power = High, V_DDA

2.7 V



6

–

V/µs

µs

T_op_wake

From disable to enable, no external

RC dominating

25

OL_GAIN

Open Loop Gain

–

90

–

dB

Comp_mode

Comparator mode; 50 mV drive,

T_rise= T_fall(approx.)

SID300

SID301

SID302

SID303

T_PD1

Response time; power = high

Response time; power = medium

Response time; power = low

Hysteresis

–

150

400

2000

10

–

ns

T_PD2

T_PD3

ns

Vhyst_op

mV

Deep Sleep Mode

Mode 2 is lowest current range. Mode

1 has higher GBW.

Deep Sleep mode V_DDA

2.7 V.



SID_DS_1 IDD_HI_M1

Mode 1, High current

–

1400

700

200

120

60

–

µA

25 °C

SID_DS_2 IDD_MED_M1 Mode 1, Medium current

SID_DS_3 IDD_LOW_M1 Mode 1, Low current

SID_DS_4 IDD_HI_M2

Mode 2, High current

SID_DS_5 IDD_MED_M2 Mode 2, Medium current

SID_DS_6 IDD_LOW_M2 Mode 2, Low current

15

SID_DS_7 GBW_HI_M1

Mode 1, High current

4

MHz 20-pF load, no DC load

0.2 V to V_DDA– 1.5 V

SID_DS_8 GBW_MED_M1 Mode 1, Medium current

SID_DS_9 GBW_LOW_M1 Mode 1, Low current

–

2

0.5

0.2

0.1

5

–

MHz 20-pF load, no DC load

0.2 V to V_DDA– 1.5 V

MHz 20-pF load, no DC load

0.2 V to V_DDA– 1.5 V

SID_DS_10 GBW_HI_M2

Mode 2, High current

MHz 20-pF load, no DC load

0.2 V to V_DDA– 1.5 V

SID_DS_11 GBW_MED_M2 Mode 2, Medium current

SID_DS_12 GBW_LOW_M2 Mode 2, Low current

MHz 20-pF load, no DC load

0.2 V to V_DDA– 1.5 V

MHz 20-pF load, no DC load

0.2 V to V_DDA– 1.5 V

SID_DS_13 VOS_HI_M1

Mode 1, High current

mV

With trim 25 °C, 0.2 V to

V_DDA– 1.5 V

SID_DS_14 VOS_MED_M1 Mode 1, Medium current

SID_DS_15 VOS_LOW_M1 Mode 1, Low current

5

With trim 25 °C, 0.2 V to

V_DDA– 1.5 V

5

With trim 25 °C, 0.2 V to

V

_DDA– 1.5 V

With trim 25 °C, 0.2 V to

_DDA– 1.5 V

With trim 25 °C, 0.2 V to

_DDA– 1.5 V

SID_DS_16 VOS_HI_M2

Mode 2, High current

5

V

SID_DS_17 VOS_MED_M2 Mode 2, Medium current

5

V

Document Number: 001-91686 Rev. *K

Page 21 of 47

PSoC^™4: PSoC 4200L Datasheet

Table 8. Opamp Specifications

(Guaranteed by Characterization) (continued)

Spec ID#

Parameter

Description

Min

Typ

Max

Units

Details/Conditions

SID_DS_18 VOS_LOW_M2 Mode 2, Low current

–

5

–

mV

With trim 25 °C, 0.2 V to

V_DDA-1.5 V

SID_DS_19 IOUT_HI_M1

Mode 1, High current

–

10

4

–

mA

Output is 0.5 V to

V

_DDA-0.5 V

Output is 0.5 V to

_DDA-0.5 V

Output is 0.5 V to

_DDA-0.5 V

Output is 0.5 V to

_DDA-0.5 V

Output is 0.5 V to

_DDA-0.5 V

Output is 0.5 V to

SID_DS_20 IOUT_MED_M1 Mode 1, Medium current

SID_DS_21 IOUT_LOW_M1 Mode 1, Low current

V

SID_DS_22 IOUT_HI_M2

Mode 2, High current

1

V

SID_DS_23 IOUT_MED_M2 Mode 2, Medium current

SID_DS_24 IOUT_LOW_M2 Mode 2, Low current

1

V

0.5

V_DDA-0.5 V

Comparator

Table 9. Comparator DC Specifications

Spec ID#

Parameter

V_OFFSET2

Description

Min

Typ

Max

Units

Details/Conditions

SID85

Input offset voltage. Custom trim.

Common mode voltage range from 0

to V_DD-1.

–

±4

mV

SID85A

V_OFFSET3

Input offset voltage. Ultra low-power

mode.

–

±12

–

mV V_DDD≥ 2.2 V for Temp <

0 °C, V_DDD≥ 1.8 V for

Temp > 0 °C

SID86

V_HYST

V_ICM1

V_ICM2

Hysteresis when enabled. Common

mode voltage range from 0 to V_DD-1.

–

0

10

–

35

mV Guaranteed by characteri-

zation

SID87

Input common mode voltage in

normal mode

V_DDD

0.2

–

V

Modes 1 and 2.

SID247

SID247A

Input common mode voltage in low

power mode

–

V_DDD

Input common mode voltage in ultra

low power mode

–

V_DDD

1.15

–

V_DDD≥ 2.2 V for Temp <

0 °C, V_DDD≥ 1.8 V for

Temp > 0 °C

SID88

CMRR

I_CMP1

I_CMP2

I_CMP3

Common mode rejection ratio

Block current, normal mode

50

42

–

dB

µA

V_DDD 2.7 V. Guaranteed

by characterization

SID88A

SID89

V_DDD 2.7 V. Guaranteed

by characterization

280

50

6

400

100

28

Guaranteed by characteri-

zation

SID248

SID259

Block current, low power mode

Block current, ultra low power mode

–

Guaranteed by characteri-

zation

–

Guaranteed by characteri-

zation, V_DDD≥ 2.2 V for

Temp < 0 °C, V_DDD≥ 1.8 V

for Temp > 0 °

SID90

Z_CMP

DC input impedance of comparator

35

–

MΩ Guaranteed by characteri-

zation

Document Number: 001-91686 Rev. *K

Page 22 of 47

PSoC^™4: PSoC 4200L Datasheet

Table 10. Comparator AC Specifications

(Guaranteed by Characterization)

Spec ID#

SID91

Parameter

T_RESP1

T_RESP2

T_RESP3

Description

Min

–

Typ

38

Max

110

200

15

Units Details/Conditions

Response time, normal mode

Response time, low power mode

Response time, ultra low power mode

ns

µs

50-mV overdrive

200-mV overdrive.

SID258

SID92

–

70

–

2.3

V

_DDD≥ 2.2 V for

Temp < 0 °C, V_DDD

1.8 V for Temp > 0 °C

≥

Temperature Sensor

Table 11. Temperature Sensor Specifications

Spec ID#

Parameter

Description

Min

Typ

Max

Units Details/Conditions

°C –40 to +85 °C

SID93

T_SENSACC

Temperature sensor accuracy

–5

±1

+5

SAR ADC

Table 12. SAR ADC DC Specifications

Spec ID#

SID94

Parameter

A_RES

A_CHNIS_S

A-CHNKS_D Number of channels - differential

Description

Min

–

Typ

–

Max

Units Details/Conditions

Resolution

Number of channels - single ended

12

16

8

bits

SID95

–

SID96

–

Diff inputs use

neighboring I/O

SID97

SID98

SID99

A-MONO

Monotonicity

–

±0.1

2

Yes. Based on

characterization

A_GAINERR Gain error

%

With external

reference.

A_OFFSET

Input offset voltage

mV Measured with 1-V

V_REF.

SID100

SID101

A_ISAR

A_VINS

Current consumption

–

1

mA

Input voltage range - single ended

V_SS

V_DDA

V

Based on device

characterization

SID102

SID103

SID104

A_VIND

Input voltage range - differential

Input resistance

V_SS

–

V_DDA

2.2

V

Based on device

characterization

A_INRES

A_INCAP

kΩ

pF

Based on device

characterization

Input capacitance

–

10

Based on device

characterization

Table 13. SAR ADC AC Specifications

(Guaranteed by Characterization)

Spec ID#

SID106

SID107

SID108

Parameter

A_PSRR

Description

Power supply rejection ratio

Common mode rejection ratio

Min

70

66

–

Typ

–

Max

Units

dB

Details/Conditions

–

1

A_CMRR

–

dB

Measured at 1 V

A_SAMP_1

Sample rate with external reference

bypass cap

–

Msps

SID108A

A_SAMP_2

Sample rate with no bypass cap.

Reference = V_DD

–

500

ksps

Document Number: 001-91686 Rev. *K

Page 23 of 47

PSoC^™4: PSoC 4200L Datasheet

Table 13. SAR ADC AC Specifications

(Guaranteed by Characterization) (continued)

Spec ID#

Parameter

Description

Min

Typ

Max

Units

Details/Conditions

SID108B

A_SAMP_3

Sample rate with no bypass cap. Internal

reference

–

100

ksps

SID109

SID111

A_SNDR

A_INL

Signal-to-noise and distortion ratio

(SINAD)

65

–

dB

F_IN= 10 kHz

Integral non linearity

–1.7

+2

LSB

V

_DD= 1.71 to 5.5,

1 Msps, V_REF= 1 to

5.5.

SID111A

SID111B

A_INL

–1.5

–

+1.7

LSB

V

_DDD= 1.71 to 3.6,

1 Msps, V_REF= 1.71

to V_DDD

.

LSB V_DDD= 1.71 to 5.5,

500 ksps, V_REF= 1 to

5.5.

SID112

A_DNL

Differential non linearity

–1

–

+2.2

+2

LSB

V

_DDD= 1.71 to 5.5, 1

Msps, V_REF= 1 to 5.5.

SID112A

LSB V_DDD= 1.71 to 3.6, 1

Msps, V_REF= 1.71 to

V_DDD

.

SID112B

A_DNL

A_THD

Differential non linearity

Total harmonic distortion

–1

–

+2.2

–65

LSB V_DDD= 1.71 to 5.5,

500 ksps, V_REF= 1 to

5.5.

SID113

dB

F_IN= 10 kHz.

CSD

Table 14. CSD Block Specification

Spec ID# Parameter

CSD Specification

Description

Min

Typ

Max

Units

Details/Conditions

SID308

SID309

SID310

SID311

SID312

SID313

VCSD

IDAC1

IDAC2

SNR

Voltage range of operation

DNL for 8-bit resolution

INL for 8-bit resolution

DNL for 7-bit resolution

INL for 7-bit resolution

1.71

–1

–3

–1

–3

5

–

5.5

1

V

LSB

Ratio

3

1

3

Capacitance range of

9 to 35 pF, 0.1 pF

sensitivity

Ratio of counts of finger to noise.

Guaranteed by characterization

–

SID314

IDAC1_CRT1 Output current of Idac1 (8-bits) in High

range

–

612

306

–

µA

SID314A IDAC1_CRT2 Output current of Idac1(8-bits) in Low

range

SID315

IDAC2_CRT1 Output current of Idac2 (7-bits) in High

range

304.8

152.4

SID315A IDAC2_CRT2 Output current of Idac2 (7-bits) in Low

range

Document Number: 001-91686 Rev. *K

Page 24 of 47

PSoC^™4: PSoC 4200L Datasheet

Digital Peripherals

The following specifications apply to the Timer/Counter/PWM peripheral in timer mode.

Timer/Counter/PWM

Table 15. TCPWM Specifications

(Guaranteed by Characterization)

Spec ID#

Parameter

Description

Min

Typ

Max Units

Details/Conditions

All modes

(Timer/Counter/PWM)

All modes

(Timer/Counter/PWM)

All modes

(Timer/Counter/PWM)

Fc max = Fcpu.

Maximum = 48 MHz

–

SID.TCPWM.1 ITCPWM1

SID.TCPWM.2 ITCPWM2

SID.TCPWM.2A ITCPWM3

Block current consumption at 3 MHz

45

155

650

Fc

µA

Block current consumption at

12 MHz

Block current consumption at

48 MHz

–

µA

SID.TCPWM.3 TCPWMFREQ Operating frequency

MHz

Trigger Events can be

Stop, Start, Reload,

Count, Capture, or Kill

depending on which

mode of operation is

selected.

Input Trigger Pulse Width for all

–

SID.TCPWM.4 TPWMENEXT

SID.TCPWM.5 TPWMEXT

2/Fc

ns

Trigger Events

Minimum possible width

of Overflow, Underflow,

Output Trigger Pulse widths

ns and CC (Counter equals

Compare value) trigger

outputs

Minimum time between

successive counts

Minimum pulse width of

PWM Output

–

SID.TCPWM.5A TCRES

SID.TCPWM.5B PWMRES

Resolution of Counter

PWM Resolution

1/Fc

ns

Minimum pulse width

ns between Quadrature

phase inputs.

–

SID.TCPWM.5C QRES

Quadrature inputs resolution

1/Fc

I²C

Table 16. Fixed I²C DC Specifications

(Guaranteed by Characterization)

Spec ID#

SID149

Parameter

I_I2C1

Description

Min

Typ

Max

Units

Details/Conditions

Block current consumption at

100 kHz

–

10.5

55

µA

SID150

I_I2C2

Block current consumption at

400 kHz

–

135

µA

SID151

SID152

I_I2C3

I_I2C4

Block current consumption at 1 Mbps

I²C enabled in Deep Sleep mode

–

310

1.4

µA

Table 17. Fixed I²C AC Specifications

(Guaranteed by Characterization)

Spec ID#

SID153

Parameter

F_I2C1

Description

Min

Typ

Max

Units

Details/Conditions

Bit rate

–

1

Mbps

Document Number: 001-91686 Rev. *K

Page 25 of 47

PSoC^™4: PSoC 4200L Datasheet

LCD Direct Drive

Table 18. LCD Direct Drive DC Specifications

(Guaranteed by Characterization)

Spec ID#

Parameter

I_LCDLOW

Description

Min

Typ

Max

Units Details/Conditions

SID154

Operating current in low power mode

–

5

–

µA 16 × 4 small segment

disp. at 50 Hz

SID155

C_LCDCAP

LCD capacitance per segment/common

driver

–

500

5000

pF Guaranteed by Design

SID156

SID157

LCD_OFFSET

I_LCDOP1

Long-term segment offset

–

20

–

mV

PWM Mode current. 5-V bias.

24-MHz IMO

0.6

mA 32 × 4 segments.

50 Hz, 25 °C

SID158

I_LCDOP2

PWM Mode current. 3.3-V bias.

24-MHz IMO.

–

0.5

–

mA 32 × 4 segments.

50 Hz, 25 °C

Table 19. LCD Direct Drive AC Specifications

(Guaranteed by Characterization)

Spec ID#

Parameter

F_LCD

Description

Min

Typ

Max

Units

Details/Conditions

SID159

LCD frame rate

10

50

150

Hz

Table 20. Fixed UART DC Specifications

(Guaranteed by Characterization)

Spec ID#

Parameter

I_UART1

Description

Min

Typ

Max

Units

SID160

Block current consumption at

100 Kbits/sec

–

9

55

µA

SID161

I_UART2

Block current consumption at

1000 Kbits/sec

–

312

µA

Table 21. Fixed UART AC Specifications

(Guaranteed by Characterization)

Spec ID#

Parameter

F_UART

Description

Min

Typ

Max

Units

Details/Conditions

SID162

Bit rate

–

1

Mbps

Document Number: 001-91686 Rev. *K

Page 26 of 47

PSoC^™4: PSoC 4200L Datasheet

SPI Specifications

Table 22. Fixed SPI DC Specifications

(Guaranteed by Characterization)

Spec ID#

SID163

Parameter

Description

Min

–

Typ

–

Max

360

560

600

Units

µA

I_SPI1

I_SPI2

I_SPI3

Block current consumption at 1 Mbits/sec

Block current consumption at 4 Mbits/sec

Block current consumption at 8 Mbits/sec

SID164

SID165

–

µA

–

µA

Table 23. Fixed SPI AC Specifications

(Guaranteed by Characterization)

Spec ID#

SID166

Parameter

Description

Min

Typ

Max

Units

F_SPI

SPI operating frequency (master; 6X

oversampling)

–

8

MHz

Table 24. Fixed SPI Master Mode AC Specifications

(Guaranteed by Characterization)

Spec ID#

SID167

Parameter

Description

Min

–

Typ

–

Max

15

–

Units

ns

T_DMO

T_DSI

MOSI valid after Sclock driving edge

SID168

MISO valid before Sclock capturing edge.

Full clock, late MISO Sampling used

20

–

ns

SID169

T_HMO

Previous MOSI data hold time with respect

to capturing edge at Slave

0

–

ns

Table 25. Fixed SPI Slave mode AC Specifications

(Guaranteed by Characterization)

Spec ID#

SID170

Parameter

Description

Min

40

–

Typ

–

Max

Units

ns

T_DMI

MOSI valid before Sclock capturing edge

MISO valid after Sclock driving edge

–

SID171

T_DSO

–

42 + 3 ×

T_SCB

ns

SID171A

T_{DSO_ext}

MISO valid after Sclock driving edge in Ext.

Clock mode

–

48

ns

SID172

T_HSO

Previous MISO data hold time

0

–

ns

SID172A

T_SSELSCK

SSEL Valid to first SCK Valid edge

100

Document Number: 001-91686 Rev. *K

Page 27 of 47

PSoC^™4: PSoC 4200L Datasheet

Memory

Table 26. Flash DC Specifications

Spec ID#

Parameter

V_PE

Description

Min

Typ

Max

Units

Details/Conditions

SID173

Erase and program voltage

1.71

–

5.5

V

Table 27. Flash AC Specifications

Spec ID#

Parameter

Description

Min

Typ

Max

Units

Details/Conditions

SID174

T_ROWWRITE

Row (block) write time (erase and

program)

–

20

ms

Row (block) = 256 bytes

SID175

SID176

SID178

SID180

T_ROWERASE

T_ROWPROGRAM

T_BULKERASE

T_DEVPROG

Row erase time

–

13

7

ms

Row program time after erase

Bulk erase time (128 KB)

Total device program time

35

15

seconds Guaranteed by charac-

terization

SID181

SID182

SID182A

SID182B

F_END

F_RET

Flash endurance

100 k

20

–

cycles Guaranteed by charac-

terization

Flash retention. T_A 55 °C, 100 k

P/E cycles

years Guaranteed by charac-

terization

Flash retention. T_A 85 °C, 10 k

P/E cycles

10

–

years Guaranteed by charac-

terization

F_RETQ

Flash retention. T_A 105 °C, 10 k

P/E cycles,  three years at T_A≥

85 °C

10

20

years Guaranteed by charac-

terization.

Document Number: 001-91686 Rev. *K

Page 28 of 47

PSoC^™4: PSoC 4200L Datasheet

System Resources

Power-on-Reset (POR) with Brown Out

Table 28. Imprecise Power On Reset (PRES)

Spec ID#

Parameter

V_RISEIPOR

Description

Rising trip voltage

Min

Typ

Max

Units

Details/Conditions

SID185

0.80

–

1.45

V

Guaranteed by charac-

terization

SID186

SID187

V_FALLIPOR

V_IPORHYST

Falling trip voltage

Hysteresis

0.75

15

–

1.4

V

Guaranteed by charac-

terization

200

mV

Guaranteed by charac-

terization

Table 29. Precise Power On Reset (POR)

Spec ID#

Parameter

V_FALLPPOR

Description

Min

Typ

Max

Units

Details/Conditions

SID190

BOD trip voltage in active and

sleep modes

1.64

–

V

Guaranteed by charac-

terization

SID192

V_FALLDPSLP

BOD trip voltage in Deep Sleep

1.4

–

V

Guaranteed by charac-

terization

Voltage Monitors

Table 30. Voltage Monitors DC Specifications

Spec ID#

SID195

SID196

SID197

SID198

SID199

SID200

SID201

SID202

SID203

SID204

SID205

SID206

SID207

SID208

SID209

SID210

SID211

Parameter

V_LVI1

Description

Min

1.71

1.76

1.85

1.95

2.05

2.15

2.24

2.34

2.44

2.54

2.63

2.73

2.83

2.93

3.12

4.39

–

Typ

1.75

1.80

1.90

2.00

2.10

2.20

2.30

2.40

2.50

2.60

2.70

2.80

2.90

3.00

3.20

4.50

–

Max

1.79

1.85

1.95

2.05

2.15

2.26

2.36

2.46

2.56

2.67

2.77

2.87

2.97

3.08

3.28

4.61

100

Units

V

Details/Conditions

LVI_A/D_SEL[3:0] = 0000b

LVI_A/D_SEL[3:0] = 0001b

LVI_A/D_SEL[3:0] = 0010b

LVI_A/D_SEL[3:0] = 0011b

LVI_A/D_SEL[3:0] = 0100b

LVI_A/D_SEL[3:0] = 0101b

LVI_A/D_SEL[3:0] = 0110b

LVI_A/D_SEL[3:0] = 0111b

LVI_A/D_SEL[3:0] = 1000b

LVI_A/D_SEL[3:0] = 1001b

LVI_A/D_SEL[3:0] = 1010b

LVI_A/D_SEL[3:0] = 1011b

LVI_A/D_SEL[3:0] = 1100b

LVI_A/D_SEL[3:0] = 1101b

LVI_A/D_SEL[3:0] = 1110b

LVI_A/D_SEL[3:0] = 1111b

Block current

V_LVI2

V

V_LVI3

V

V_LVI4

V

V_LVI5

V

V_LVI6

V

V_LVI7

V

V_LVI8

V

V_LVI9

V

V_LVI10

V_LVI11

V_LVI12

V_LVI13

V_LVI14

V_LVI15

V_LVI16

LVI_IDD

V

µA

Guaranteed by charac-

terization

Table 31. Voltage Monitors AC Specifications

Spec ID#

Parameter

T_MONTRIP

Description

Min

Typ

Max

Units

Details/Conditions

SID212

Voltage monitor trip time

–

1

µs

Guaranteed by charac-

terization

Document Number: 001-91686 Rev. *K

Page 29 of 47

PSoC^™4: PSoC 4200L Datasheet

SWD Interface

Table 32. SWD Interface Specifications

Spec ID#

Parameter

Description

3.3 V  V_DD 5.5 V

Min

Typ

Max

Units

Details/Conditions

SID213

F_SWDCLK1

–

14

MHz

SWDCLK ≤ 1/3 CPU

clock frequency

SID214

SID215

SID216

SID217

F_SWDCLK2

1.71 V  V_DD 3.3 V

–

0.25 * T

–

7

MHz

ns

SWDCLK ≤ 1/3 CPU

clock frequency

T_SWDI_SETUP T = 1/f SWDCLK

T_SWDI_HOLD T = 1/f SWDCLK

T_SWDO_VALID T = 1/f SWDCLK

–

Guaranteed by

characterization

–

0.5 * T

–

ns

Guaranteed by

characterization

ns

Guaranteed by

characterization

SID217A T_SWDO_HOLD T = 1/f SWDCLK

1

ns

Guaranteed by

characterization

Internal Main Oscillator

Table 33. IMO DC Specifications

(Guaranteed by Design)

Spec ID#

SID218

SID219

SID220

SID221

SID222

Parameter

I_IMO1

Description

Min

–

Typ

–

Max

1000

325

225

180

150

Units

µA

Details/Conditions

IMO operating current at 48 MHz

IMO operating current at 24 MHz

IMO operating current at 12 MHz

IMO operating current at 6 MHz

IMO operating current at 3 MHz

I_IMO2

I_IMO3

I_IMO4

I_IMO5

–

µA

–

µA

–

µA

–

µA

Table 34. IMO AC Specifications

Spec ID#

Parameter

F_IMOTOL1

Description

Min

Typ

Max

Units

Details/Conditions

SID223

Frequency variation from 3 to

48 MHz

–

±2

%

SID226

SID227

SID228

SID229

T_STARTIMO

IMO startup time

–

12

–

µs

ps

T_JITRMSIMO1

T_JITRMSIMO2

T_JITRMSIMO3

RMS Jitter at 3 MHz

RMS Jitter at 24 MHz

RMS Jitter at 48 MHz

156

145

139

–

Internal Low-Speed Oscillator

Table 35. ILO DC Specifications

(Guaranteed by Design)

Spec ID#

Parameter

I_ILO1

Description

Min

Typ

Max

Units

Details/Conditions

SID231

ILO operating current at 32 kHz

–

0.3

1.05

µA

Guaranteed by

Characterization

SID233

I_ILOLEAK

ILO leakage current

–

2

15

nA

Guaranteed by

Design

Document Number: 001-91686 Rev. *K

Page 30 of 47

PSoC^™4: PSoC 4200L Datasheet

Table 36. ILO AC Specifications

Spec ID#

Parameter

T_STARTILO1

Description

ILO startup time

Min

Typ

Max

Units

Details/Conditions

SID234

–

2

ms

Guaranteed by charac-

terization

SID236

SID237

T_ILODUTY

F_ILOTRIM1

ILO duty cycle

40

15

50

32

60

50

%

Guaranteed by charac-

terization

32 kHz trimmed frequency

kHz

±60% with trim.

Table 37. PLL DC Specifications

Spec ID#

SID410

Parameter

IDD_PLL_48

IDD_PLL_24

Description

In = 3 MHz, Out = 48 MHz

In = 3 MHz, Out = 24 MHz

Min

–

Typ

530

300

Max

Units

µA

Details/Conditions

610

405

SID411

–

µA

Table 38. PLL AC Specifications

Spec ID#

SID412

Parameter

F_PLLIN

Description

PLL input frequency

Min

1

Typ

–

Max

48

3

Units

MHz

Details/Conditions

SID413

F_PLLINT

F_PLLVCO

D_IVVCO

PLL intermediate frequency;

prescaler out

1

–

SID414

SID415

VCO output frequency before

post-divide

22.5

1

–

104

8

MHz

–

VCO Output post-divider range;

PLL output frequency is

F

_PPLVCO/D_IVVCO

SID416

SID417

PLLlocktime

Jperiod_1

Lock time at startup

–

250

150

200

us

ps

Period jitter for VCO ≥ 67 MHz

Period jitter for VCO ≤ 67 MHz

Guaranteed By Design

SID416A Jperiod_2

Table 39. External Clock Specifications

Spec ID#

Parameter

ExtClkFreq

Description

Min

Typ

Max

Units

Details/Conditions

SID305

External Clock input Frequency

0

–

48

MHz Guaranteed by

characterization

SID306

ExtClkDuty

Duty cycle; Measured at V_DD/2

45

–

55

%

Guaranteed by

characterization

Table 40. Watch Crystal Oscillator (WCO) Specifications

Spec ID# Parameter Description

IMO WCO-PLL calibrated mode

Min

Typ

Max

Units

Details / Conditions

SID330

SID331

SID332

SID333

IMOWCO1

IMOWCO2

IMOWCO3

IMOWCO4

Frequency variation with IMO set to

3 MHz

–0.6

–0.4

–0.3

–0.2

–

0.6

0.4

0.3

0.2

%

Does not include WCO

tolerance

Frequency variation with IMO set to

5 MHZ

Does not include WCO

tolerance

Frequency variation with IMO set to

7 or 9 MHZ

Does not include WCO

tolerance

All other IMO frequency settings

Does not include WCO

tolerance

Document Number: 001-91686 Rev. *K

Page 31 of 47

PSoC^™4: PSoC 4200L Datasheet

Table 40. Watch Crystal Oscillator (WCO) Specifications

Spec ID# Parameter Description

WCO Specifications

Min

Typ

Max

Units

Details / Conditions

SID398

SID399

SID400

SID401

SID402

SID403

SID404

SID405

FWCO

FTOL

ESR

Crystal frequency

–

6

–

32.768

–

250

–

kHz

Frequency tolerance

Equivalent series resistance

Drive Level

50

–

ppm With 20-ppm crystal.

kΩ

µW

ms

pF

PD

1

TSTART

CL

Startup time

–

500

12.5

–

Crystal load capacitance

Crystal shunt capacitance

–

C0

1.35

–

pF

IWCO1

Operating current (high power

mode)

8

uA

Table 41. External Crystal Oscillator (ECO) Specifications

Spec ID#

Parameter

Description

Min

–

Typ

–

Max

1.5

33

Units

mA

Details/Conditions

SID316

SID317

IECO1

FECO

Block operating current

Crystal frequency range

4

–

MHz

Table 42. UDB AC Specifications

(Guaranteed by Characterization)

Spec ID#

Parameter

Description

Min

Typ

Max

Units Details/Conditions

Datapath performance

SID249

SID250

SID251

F_MAX-TIMER

F_MAX-ADDER

F_{MAX_CRC}

Max frequency of 16-bit timer in a

UDB pair

–

48

MHz

Max frequency of 16-bit adder in a

UDB pair

Max frequency of 16-bit CRC/PRS in

a UDB pair

PLD Performance in UDB

SID252 F_{MAX_PLD}

Max frequency of 2-pass PLD

function in a UDB pair

–

48

MHz

Clock to Output Performance

SID253

SID254

T_{CLK_OUT_UDB1}

T_{CLK_OUT_UDB2}

Prop. delay for clock in to data out at

25 °C, Typ.

–

15

25

–

ns

Prop. delay for clock in to data out,

Worst case.

Document Number: 001-91686 Rev. *K

Page 32 of 47

PSoC^™4: PSoC 4200L Datasheet

Table 43. Block Specs

Spec ID#

Parameter

Description

Min

Typ

Max

Units Details/Conditions

SID256

T_WS48

Number of wait states at 48 MHz

2

–

CPU execution from

Flash. Guaranteed

by characterization

SID257

SID260

T_WS24

Number of wait states at 24 MHz

Trimmed internal reference to SAR

1

–

CPU execution from

Flash. Guaranteed

by characterization

V_REFSAR

–1

+1

%

Percentage of Vbg

(1.024 V).

Guaranteed by

characterization

SID261

SID262

F_SARINTREF

SAR operating speed without

external reference bypass

–

3

500

–

4

ksps 12-bit resolution.

Guaranteed by

characterization

T_CLKSWITCH

Clock switching from clk1 to clk2 in

clk1 periods

Periods Guaranteed by

design

* Tws48 and Tws24 are guaranteed by Design

Table 44. UDB Port Adaptor Specifications

(Based on LPC Component Specs; all specs except TLCLKDO are guaranteed by design -10-pF load, 3-V V_DDIOand V_DDD

)

Spec ID#

SID263

Parameter

T_LCLKDO

Description

LCLK to output delay

Min

–

Typ

–

Max

18

7

Units Details/Conditions

ns

SID264

T_DINLCLK

Input setup time to LCLCK rising

edge

–

SID265

SID266

SID267

SID268

T_DINLCLKHLD

T_LCLKHIZ

Input hold time from LCLK rising edge

LCLK to output tristated

0

–

ns

28

33

60

T_FLCLK

LCLK frequency

–

MHz

%

T_LCLKDUTY

LCLK duty cycle (percentage high)

40

Table 45. USB Device Block Specifications (USB only)

Spec ID#

Parameter

Vusb_5

Description

Min

Typ

Max

Units Details / Conditions

SID321

Device supply for USB operation

4.5

–

5.5

V

USB Configured,

USB Reg. enabled

SID322

SID323

SID324

SID325

SID326

SID327

SID328

SID329

Vusb_3.3

Device supply for USB operation

3.15

–

3.6

–

USB Configured,

USB Reg. bypassed

Vusb_3

Device supply for USB operation

(Functional operation only)

2.85

–

USB Configured,

USB Reg. bypassed

Iusb_config

Isub_suspend

Device supply current in Active mode,

IMO = 24 MHz

10

8

mA V_DDD= 5 V

Device supply current in Active mode,

IMO = 24 MHz

–

mA

V

_DDD= 3.3 V

Device supply current in Sleep mode

–

0.5

0.3

0.5

0.3

–

V

_DDD= 5 V, PICU

wakeup

_DDD= 5 V, Device

disconnected

–

V

–

mA V_DDD= 3.3 V, PICU

wakeup

–

mA

V

_DDD= 3.3 V, Device

disconnected

Document Number: 001-91686 Rev. *K

Page 33 of 47

PSoC^™4: PSoC 4200L Datasheet

Table 46. SIO Specifications

Spec ID# Parameter

Description

Min

Typ

Max

Units

Details / Conditions

SIO DC Specifications

SID330 V_IH

Input voltage high threshold

Input voltage low threshold

0.7 * V_DD

–

0.3*VDD

–

V

CMOS input; with respect

to V_DDIO

SID331 V_IL

SID332 V_IH

SID333 V_IL

SID334 V_OH

SID335 V_OH

SID336 V_OH

–

Vr + 0.2

–

CMOS input; with respect

to V_DDIO

Differential input mode high

voltage; hysteresis disabled

Vr is the SIO reference

voltage

Differential input mode low

voltage, hysteresis disabled

Vr-0.2

–

Vr is the SIO reference

voltage

Output high voltage in unregu-

lated mode

V_DDIO– 0.4

I_OH= 4 mA, V_DD= 3.3 V

Output high voltage in regulated Vr – 0.65

mode

Vr + 0.2

I_OH= 1 mA

Output high voltage in regulated

mode

Vr – 0.3

I_OH= 0.1 mA

SID337 V_OL

SID338 V_OL

SID339 Vinref

SID340 Voutref

Output low voltage

Input voltage reference

–

0.8

0.4

V

V_DDIO= 3.3 V, I_OL= 25 mA

V_DDIO= 1.8 V, I_OL= 4 mA

0.48

1

0.52 * V_DDIO

Output voltage reference

(regulated mode)

V

_DDIO– 1

V_DDIO> 3.3

V_DDIO< 3.3

SID341 Voutref

Output voltage reference

(regulated mode)

1

–

V_DDIO– 0.5

V

SID342 R_PULLUP

SID343 R_PULLDOWN

SID344 I_IL

Pull-up resistor

3.5

–

5.6

–

8.5

14

kΩ

Pull-down resistor

Input leakage current (absolute

value)

nA V_IH≤ V_DDSIO; 25 °C

SID345 I_IL

Input leakage current (absolute

value)

–

10

nA V_IH> V_DDSIO; 25 °C

SID346 C_IN

Input capacitance

–

40

35

–

7

–

pF

mV

µA

SID347 VHYST-Single Hysteresis in single-ended mode

SID348 VHYST_Diff

SID349 I_DIODE

Hysteresis in differential mode

–

Current through protection diode

to V_DD/V_SS

100

SIO AC Specifications (Guaranteed By Design)

SID350 T_RISEF

SID351 T_FALLF

SID352 T_RISES

SID353 T_FALLS

SID354 F_SIOUT1

Rise time in Fast Strong mode

–

12

75

70

33

ns 3.3-V V_DD, Cload = 25 pF

Fall time in Fast Strong mode

Rise time in Slow Strong mode

Fall time in Slow Strong mode

SIO Fout; Unregulated, Fast

Strong mode

MHz 3.3-V ≤ V_DD≤ 5.5 V, 25 pF.

Guaranteed by design.

SID355 F_SIOUT2

SID356 F_SIOUT3

SID357 F_SIOUT4

SIO Fout; Unregulated, Fast

Strong mode

–

16

20

10

MHz 1.71-V ≤ V_DD≤ 3.3 V, 25 pF

MHz 3.3-V ≤ V_DD≤ 5.5 V, 25 pF

MHz 1.71 V ≤ V_DD≤ 3.3 V, 25 pF

SIOFout;Regulated,FastStrong

mode

SIOFout;Regulated,FastStrong

mode

Document Number: 001-91686 Rev. *K

Page 34 of 47

PSoC^™4: PSoC 4200L Datasheet

Table 46. SIO Specifications (continued)

Spec ID#

Parameter

Description

Min

Typ

Max

Units

Details / Conditions

SID358 F_SIOUT3

SID359 F_SIOUT4

SID360 F_SIOUT5

SID361 F_GPIOIN

SIO Fout; Unregulated, Slow

Strong mode.

–

5

MHz 3.3 V ≤ V_DD≤ 5.5 V, 25 pF

MHz 1.71 V ≤ V_DD≤ 3.3 V, 25 pF

MHz 1.7 V ≤ V_DD≤ 5.5 V, 25 pF

MHz 1.71 V ≤ V_DD≤ 5.5 V

SIO Fout, Unregulated, Slow

Strong mode.

–

3.5

2.5

48

SIO Fout, Regulated, Slow

Strong mode.

GPIO input operating

frequency;1.71 V ≤ V_DD≤ 5.5 V

Table 47. CAN Specifications

Spec ID# Parameter

Description

Min

Typ

Max

Units

Details / Conditions

SID420 IDD_CAN

SID421 CAN_bits

Block current consumption

CAN Bit rate (Min 8-MHz clock)

–

200

1

uA

Mbps

Document Number: 001-91686 Rev. *K

Page 35 of 47

PSoC^™4: PSoC 4200L Datasheet

Ordering Information

The PSoC 4200L family part numbers and features are listed in the following table.

Table 48. PSoC 4200L Ordering Information

Features

Package

CY8C4246AZI-L423

CY8C4246AZI-L433

CY8C4246AZI-L435

CY8C4246AZI-L445

CY8C4246LTI-L445

CY8C4247AZI-L423

CY8C4247AZI-L433

CY8C4247AZI-L445

CY8C4247LTI-L445

CY8C4247AZI-L475

CY8C4247LTI-L475

CY8C4247BZI-L479

CY8C4247AZI-L485

CY8C4247LTI-L485

48

64

8

2

4

1

–

2

1

–

2

–

2

✔

–

1000 ksps

2

8

3

4

3

4

–

✔

–

38

53

57

38

53

57

53

57

98

53

57

98

96

53

57

98

53

57

98

✔

–

✔

–

4246

–

✔

–

✔

–

✔

–

48 128 16

–

✔

–

✔

–

✔

–

✔

–

✔

–

4247

–

✔

–

✔

–

✔

–

✔

–

✔

–

✔

–

CY8C4247LTQ-L485 48 128 16

–

CY8C4247BZI-L489

CY8C4248BZI-L469

CY8C4248AZI-L475

CY8C4248LTI-L475

CY8C4248BZI-L479

CY8C4248AZI-L485

CY8C4248LTI-L485

48 128 16

48 256 32

–

✔

–

✔

–

✔

–

✔

–

✔

–

4248

✔

–

✔

–

CY8C4248LTQ-L485 48 256 32

CY8C4248BZI-L489 48 256 32

–

✔

Document Number: 001-91686 Rev. *K

Page 36 of 47

PSoC^™4: PSoC 4200L Datasheet

The nomenclature used in Table 48 is based on the following part numbering convention:

Table 49. MPN Nomenclature

Field

Description

Values

Meaning

CY8C

Cypress Prefix

Architecture

Family

4

A

B

4

PSoC 4

2

4200 Family

CPU Speed

4

48 MHz

6

64 KB

C

Flash Capacity

7

128 KB

8

256 KB

AX, AZ

TQFP

LT

QFN

BGA

DE

F

Package Code

BZ

FD

CSP

I

Industrial

Temperature Range

Q

Extended Industrial

PSoC 4 S-Series

PSoC 4 L-Series

PSoC 4 M-Series

Code of feature set in the specific family

S

Series Designator

Attributes Code

L

M

XYZ

000-999

Part Numbering Conventions

The part number fields are defined as follows.

CY8C 4 A B C D E F -

S

X Y Z

Cypress Prefix

Architecture

Family Group within Architecture

Speed Grade

Flash Capacity

Package Code

Temperature Range

Series Designator

Attributes Code

Document Number: 001-91686 Rev. *K

Page 37 of 47

PSoC^™4: PSoC 4200L Datasheet

Packaging

Table 50. Package Dimensions

SPEC ID#

Package

Description

Package DWG #

PKG_1 124-ball VFBGA 124-ball, 9 mm x 9 mm x 1.0 mm

height with 0.65 mm ball pitch

001-97718

51-85051

001-09618

51-85135

PKG_2

PKG_3

PKG_4

64-pin TQFP 64-pin TQFP, 10 mm x10 mm x

1,4 mm height with 0.5 mm pitch

68-pin QFN

68-pin QFN, 8 mm x 8 mm x

1.0 mm height with 0.4 mm pitch

48-pin TQFP 48-pin TQFP, 7 mm x 7 mm x

1.4 mm height with 0.5 mm pitch

Table 51. Package Characteristics

Parameter Description

T_A

Conditions

Min

Typ

Max

Units

Operating ambient temperature

Operating junction temperature

Package _JA(124-ball VFBGA)

Package _JA(64-pin TQFP)

Package _JA(68-pin QFN)

–40

25

105

°C

T_J

–40

–

125

–

°C

T_JA

35

54

17

67

°C/Watt

–

Package _JA(48-pin TQFP)

Table 52. Solder Reflow Peak Temperature

Package

Maximum Peak Temperature

Maximum Time at Peak Temperature

All packages

260 °C

30 seconds

Table 53. Package Moisture Sensitivity Level (MSL), IPC/JEDEC J-STD-2

Package

MSL

All packages

MSL 3

Document Number: 001-91686 Rev. *K

Page 38 of 47

PSoC^™4: PSoC 4200L Datasheet

Figure 8. 124-Ball VFBGA Package Outline

001-97718 *B

Document Number: 001-91686 Rev. *K

Page 39 of 47

PSoC^™4: PSoC 4200L Datasheet

Figure 9. 64-Pin TQFP Package Outline

51-85051 *D

Figure 10. 68-Pin QFN Package Outline

001-09618 *E

Document Number: 001-91686 Rev. *K

Page 40 of 47

PSoC^™4: PSoC 4200L Datasheet

Figure 11. 48-Pin TQFP Package Outline

51-85135 *C

Document Number: 001-91686 Rev. *K

Page 41 of 47

PSoC^™4: PSoC 4200L Datasheet

Acronyms

Table 54. Acronyms Used in this Document (continued)

Table 54. Acronyms Used in this Document

Acronym

ETM

Description

embedded trace macrocell

Acronym

abus

Description

analog local bus

FIR

finite impulse response, see also IIR

flash patch and breakpoint

full-speed

ADC

AG

analog-to-digital converter

analog global

FPB

FS

AHB

AMBA (advanced microcontroller bus archi-

tecture) high-performance bus, an Arm data

transfer bus

GPIO

general-purpose input/output, applies to a PSoC

HVI

high-voltage interrupt, see also LVI, LVD

integrated circuit

ALU

arithmetic logic unit

IC

AMUXBUS analog multiplexer bus

IDAC

current DAC, see also DAC, VDAC

integrated development environment

API

application programming interface

IDE

I²C, or IIC

APSR

Arm^®

ATM

BW

application program status register

advanced RISC machine, a CPU architecture

automatic thump mode

Inter-Integrated Circuit, a communications

protocol

IIR

infinite impulse response, see also FIR

internal low-speed oscillator, see also IMO

internal main oscillator, see also ILO

integral nonlinearity, see also DNL

input/output, see also GPIO, DIO, SIO, USBIO

initial power-on reset

bandwidth

ILO

IMO

INL

CAN

Controller Area Network, a communications

protocol

CMRR

CPU

common-mode rejection ratio

central processing unit

I/O

IPOR

IPSR

IRQ

ITM

LCD

LIN

CRC

cyclic redundancy check, an error-checking

protocol

interrupt program status register

interrupt request

DAC

DFB

DIO

digital-to-analog converter, see also IDAC, VDAC

digital filter block

instrumentation trace macrocell

liquid crystal display

digital input/output, GPIO with only digital

capabilities, no analog. See GPIO.

Local Interconnect Network, a communications

protocol.

DMIPS

DMA

DNL

Dhrystone million instructions per second

direct memory access, see also TD

differential nonlinearity, see also INL

do not use

LR

link register

LUT

LVD

lookup table

DNU

DR

low-voltage detect, see also LVI

low-voltage interrupt, see also HVI

low-voltage transistor-transistor logic

multiply-accumulate

port write data registers

LVI

DSI

digital system interconnect

data watchpoint and trace

error correcting code

LVTTL

MAC

MCU

MISO

NC

DWT

ECC

microcontroller unit

ECO

EEPROM

external crystal oscillator

master-in slave-out

electrically erasable programmable read-only

memory

no connect

NMI

nonmaskable interrupt

non-return-to-zero

EMI

electromagnetic interference

external memory interface

end of conversion

NRZ

NVIC

NVL

opamp

PAL

EMIF

EOC

EOF

EPSR

ESD

nested vectored interrupt controller

nonvolatile latch, see also WOL

operational amplifier

end of frame

execution program status register

electrostatic discharge

programmable array logic, see also PLD

Document Number: 001-91686 Rev. *K

Page 42 of 47

PSoC^™4: PSoC 4200L Datasheet

Table 54. Acronyms Used in this Document (continued)

Acronym Description

PC

Table 54. Acronyms Used in this Document (continued)

Acronym

SWV

Description

single-wire viewer

program counter

PCB

PGA

PHUB

PHY

PICU

PLA

printed circuit board

TD

transaction descriptor, see also DMA

total harmonic distortion

transimpedance amplifier

technical reference manual

transistor-transistor logic

transmit

programmable gain amplifier

peripheral hub

THD

TIA

physical layer

TRM

TTL

TX

port interrupt control unit

programmable logic array

programmable logic device, see also PAL

phase-locked loop

PLD

UART

Universal Asynchronous Transmitter Receiver, a

communications protocol

PLL

UDB

universal digital block

Universal Serial Bus

PMDD

POR

PRES

PRS

PS

PSoC^®

PSRR

PWM

RAM

RISC

RMS

RTC

RTL

package material declaration data sheet

power-on reset

USB

USBIO

USB input/output, PSoC pins used to connect to

a USB port

precise power-on reset

pseudo random sequence

port read data register

Programmable System-on-Chip™

power supply rejection ratio

pulse-width modulator

random-access memory

reduced-instruction-set computing

root-mean-square

VDAC

WDT

voltage DAC, see also DAC, IDAC

watchdog timer

WOL

write once latch, see also NVL

watchdog timer reset

external reset I/O pin

crystal

WRES

XRES

XTAL

real-time clock

register transfer language

remote transmission request

receive

RTR

RX

SAR

SC/CT

SCL

successive approximation register

switched capacitor/continuous time

I²C serial clock

SDA

S/H

I²C serial data

sample and hold

SINAD

SIO

signal to noise and distortion ratio

special input/output, GPIO with advanced

features. See GPIO.

SOC

SOF

SPI

start of conversion

start of frame

Serial Peripheral Interface, a communications

protocol

SR

slew rate

SRAM

SRES

SWD

static random access memory

software reset

serial wire debug, a test protocol

Document Number: 001-91686 Rev. *K

Page 43 of 47

PSoC^™4: PSoC 4200L Datasheet

Document Conventions

Units of Measure

Table 55. Units of Measure

Symbol

°C

Unit of Measure

degrees Celsius

decibel

dB

fF

femto farad

hertz

Hz

KB

kbps

Khr

kHz

k

1024 bytes

kilobits per second

kilohour

kilohertz

kilo ohm

ksps

LSB

Mbps

MHz

M

Msps

µA

kilosamples per second

least significant bit

megabits per second

megahertz

mega-ohm

megasamples per second

microampere

microfarad

µF

µH

microhenry

microsecond

microvolt

µs

µV

µW

mA

ms

mV

nA

microwatt

milliampere

millisecond

millivolt

nanoampere

nanosecond

nanovolt

ns

nV



ohm

pF

picofarad

ppm

ps

parts per million

picosecond

second

s

sps

sqrtHz

V

samples per second

square root of hertz

volt

Document Number: 001-91686 Rev. *K

Page 44 of 47

PSoC^™4: PSoC 4200L Datasheet

Revision History

Description Title: PSoC^™4: PSoC 4200L Datasheet Programmable System-on-Chip (PSoC^®)

Document Number: 001-91686

Submission

Revision

ECN

Description of Change

Date

**

4414601

4774497

02/06/2015 New datasheet for new device family.

*A

05/22/2015 Updated Pin List.

Added a footnote explaining ground perturbations in GPIO AC Specifications.

Updated values for SID269, SID270, SID271, and SID291.

Added Conditions for Deep Sleep Mode in Opamp Specifications.

Updated Conditions for SID_DS_10 through SID_DS_18.

Added Conditions for SID_DS_22 through SID_DS_24.

Updated description for SID85 and SID85A.

Updated values for SID89, SID248, SID259, SID91, SID258, and SID92.

Updated max value for SID.TCPWM.2A.

Updated typ and max values for SID149.

Added PLL DC Specifications and PLL AC Specifications.

Updated Watch Crystal Oscillator (WCO) Specifications.

Added CAN Specifications.

Changed µFBGA package to VFBGA package.

*B

4867142

08/03/2015 Changed datasheet status to Preliminary.

Updated Pinouts.

Removed typ value for SID43.

Updated Conditions for SID_DS_7, SID_DS_8, and SID_DS_9.

Updated max value for SID87.

Removed SID179.

Added External Crystal Oscillator (ECO) Specifications.

Updated max value for SID321, SID353, and SID359.

Added “Guaranteed by Design” note for SID354.

Updated Ordering Information.

*C

*D

5034067

5170871

12/03/2015 Updated Conditions for SID85A, SID247A, SID259, SID92, SID417, SID416A

Updated typ and max values for SID410.

Updated description for SID323.

Added “Guaranteed by Characterization” note for SIO AC Specs.

Updated Ordering Information.

03/11/2016 Removed VDDA and VDDIO pins in Regulated External Supply section.

Updated values for Deep Sleep Mode, Hibernate Mode and Stop Mode in DC Specifi-

cations.

Added SID299A.

Added a note in UDB Port Adaptor Specifications that all specs except TLCLKDO are

guaranteed by design.

Updated T_JAvalue for the 124-VFBGA package.

*E

5281150

05/23/2016 Changed datasheet status to Final.

Updated max values for SID6, SID7, SID8, SID9, SID31, SID32, SID34, SID35, SID40,

SID41, SID43, and SID44.

Updated the template.

*F

5516529

5559970

11/15/2016 Added CY8C4248BZI-L469 in Ordering Information.

*G

11/20/2016 Updated max values for SID33, SID34, and SID35.

Updated SID171.

*H

*I

5713202

6201292

04/27/2017 Updated the Cypress logo and copyright information.

Updated 124-ball VFBGA package diagram.

Corrected typo in the part numbering convention table.

06/08/2018 Updated title to “PSoC® 4: PSoC 4200L Datasheet”.

Corrected links in More Information.

Added SID182B in Flash AC Specifications.

Added CY8C4247LTQ-L485 and CY8C4248LTQ-L485 in Ordering Information.

Added Extended Industrial temperature range in the part numbering convention table.

Document Number: 001-91686 Rev. *K

Page 45 of 47

PSoC^™4: PSoC 4200L Datasheet

Description Title: PSoC^™4: PSoC 4200L Datasheet Programmable System-on-Chip (PSoC^®)

Document Number: 001-91686

*J

6604720

06/26/2019 Added reference to AN85951 in More Information.

Updated Universal Digital Blocks (UDBs) and Port Interfaces.

Updated Timer/Counter/PWM (TCPWM) Block.

Updated LCD Segment Drive.

Updated GPIO.

Updated Pinouts.

Updated description for SID55 and removed Conditions for SID95.

Updated SID323 parameter name.

*K

7121245

04/12/2021 Updated the max temperature range.

Document Number: 001-91686 Rev. *K

Page 46 of 47

PSoC^™4: PSoC 4200L Datasheet

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Document Number: 001-91686 Rev. *K

Revised April 12, 2021

Page 47 of 47


型号：	CY8C4247BZI-L489
厂家：	Infineon
描述：	32位PSoC™ 4 Arm® Cortex®-M0/M0+ 时钟外围集成电路
文件：	总48页 (文件大小：934K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

CY8C4247BZI-L489 [INFINEON]

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