CY8C4248LQI-BL563T [INFINEON]
32位PSoC™ 4 Arm® Cortex®-M0/M0+;
| 型号： | CY8C4248LQI-BL563T |
| 厂家： | 
Infineon |
| 描述： | 32位PSoC™ 4 Arm® Cortex®-M0/M0+ |
| 文件： | 总69页 (文件大小：1339K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY8C42xx-BL
PSoC™ 4 MCU with AIROC™ Bluetooth® LE
Based on Arm® Cortex®-M0
General description
PSoC™ 4 is a scalable and reconfigurable platform architecture for a family of programmable embedded system
Arm®
controllers with an
Cortex®-M0 CPU. It combines programmable and reconfigurable analog and digital
blocks with flexible automatic routing. The PSoC™ 4 CY8C42xx-BL MCU with AIROC™ Bluetooth® LE product
family, based on this platform, is a combination of a microcontroller with an integrated Bluetooth® Low Energy,
also known as Bluetooth® smart, radio and subsystem (BLESS). The other features include digital programmable
logic, high-performance analog-to-digital conversion (ADC), opamps with Comparator mode, and standard
communication and timing peripherals. The programmable analog and digital subsystems allow flexibility and
in-field tuning of the design.
Features
• 32-bit MCU subsystem
- 48-MHz Arm® Cortex®-M0 CPU with single-cycle multiply and DMA
- Up to 256 KB of flash with read accelerator
- Up to 32 KB of SRAM
• Bluetooth® LE radio and subsystem
- Bluetooth® LE 4.2 support
- 2.4-GHz RF transceiver with 50-Ω antenna drive
- Digital PHY
- Link-layer engine supporting master and slave modes
- RF output power: –18 dBm to +3 dBm
- RX sensitivity: –89 dBm
- RX current: 18.7 mA
- TX current: 15.6 mA at 0 dBm
- Received Signal Strength Indication (RSSI): 1-dB resolution
• Programmable analog
- Four opamps with reconfigurable high-drive external and high-bandwidth internal drive, Comparator modes,
and ADC input buffering capability. Can operate in Deep Sleep mode.
- 12-bit, 1-Msps SAR ADC with differential and single-ended modes; Channel Sequencer with signal averaging
- Two current DACs (IDACs) for general-purpose or capacitive sensing applications on any pin
- Two low-power comparators that operate in Deep Sleep mode
• Programmable digital
- Four programmable logic blocks called universal digital blocks, (UDBs), each with eight macrocells and data
path
- Infineon-provided peripheral component library, user-defined state machines, and Verilog input
• Power management
- Active mode: 1.7 mA at 3-MHz flash program execution
- Deep Sleep mode: 1.5 µA with watch crystal oscillator (WCO) on
- Hibernate mode: 150 nA with RAM retention
- Stop mode: 60 nA
• Capacitive sensing
- Capacitive sigma-delta (CSD) provides best-in-class SNR (>5:1) and liquid tolerance
- Infineon-supplied software component makes capacitive sensing design easy
- Automatic hardware tuning algorithm (SmartSense)
Datasheet
www.infineon.com
Please read the Important Notice and Warnings at the end of this document
page 1
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PSoC™ 4 MCU with AIROC™ Bluetooth® LE
Based on Arm® Cortex®-M0
Features
• Segment LCD drive
- LCD drive supported on all pins (common or segment)
- Operates in Deep Sleep mode with four bits per pin memory
• Serial communication
- Two independent run-time reconfigurable serial communication blocks (SCBs) with reconfigurable I2C, SPI,
or UART functionality
• Timing and pulse-width modulation
- Four 16-bit timer/counter pulse-width modulator (TCPWM) blocks
- Center-aligned, Edge, and Pseudo-random modes
- Comparator-based triggering of Kill signals for motor drive and other high-reliability digital logic applications
• Up to 36 programmable GPIOs
- 7 mm × 7 mm 56-pin QFN package
- 76-ball CSP package
- 68-ball CSP package
- Any GPIO pin can be CAPSENSE™, LCD, analog, or digital
- Two overvoltage-tolerant (OVT) pins; drive modes, strengths, and slew rates are programmable
• PSoC™ Creator design environment
- Integrated Design Environment (IDE) provides schematic design entry and build (with analog and digital
automatic routing)
- API components for all fixed-function and programmable peripherals
• Industry-standard tool compatibility
- After schematic entry, development can be done with Arm®-based industry-standard development tools
Datasheet
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PSoC™ 4 MCU with AIROC™ Bluetooth® LE
Based on Arm® Cortex®-M0
More information
More information
There is a wealth of data at www.infineon.com to help you to select the right PSoC™ device for your design, and
to help you to quickly and effectively integrate the device into your design. For a comprehensive list of resources,
see the introduction page for Bluetooth® Low Energy products. Following is an abbreviated list for PSoC™ 4
CY8C4xxx-BL MCU with AIROC™ Bluetooth® LE:
• Overview: PSoC™ portfolio
• Product selectors: PSoC™ 1, PSoC™ 3, PSoC™ 4, PSoC™ 4 CY8C4xxx-BL MCU with AIROC™ Bluetooth® LE,
PSoC™ 5LP. In addition, PSoC™ Creator includes a device selection tool.
• Application notes: There are a large number of PSoC™ application notes covering a broad range of topics, from
basic to advanced level. Recommended application notes for getting started with PSoC™ 4 CY8C4xxx-BL MCU
with AIROC™ Bluetooth® LE are:
- AN91267: Getting started with PSoC™ 4 CY8C4xxx-BL MCU with AIROC™ Bluetooth® LE
- AN97060: PSoC™ 4 CY8C4xxx-BL MCU with AIROC™ Bluetooth® LE and PRoC-BLE - Over-The-Air (OTA) Device
Firmware Upgrade (DFU) guide
- AN91184: PSoC™ 4 CY8C4xxx-BL MCU with AIROC™ Bluetooth® LE - Designing Bluetooth® LE applications
- AN91162: Creating a Bluetooth® LE Custom Profile
- AN91445: Antenna design and RF layout guidelines
- AN96841: Getting started With EZ-BLE module
- AN85951: PSoC™ 4 CAPSENSE™ design guide
- AN95089: PSoC™ 4/PRoC-Bluetooth® LE crystal oscillator selection and tuning techniques
- AN92584: Designing for low power and estimating battery life for Bluetooth® LE applications
• Technical reference manual (TRM) is in two documents:
- Architecture TRM details each PSoC™ 4 CY8C4xxx-BL MCU with AIROC™ Bluetooth® LE functional block.
- Registers TRM describes each of the PSoC™ 4 CY8C4xxx-BL MCU with AIROC™ Bluetooth® LE registers.
• Development kits:
- CY8CKIT-042-BLE-A Pioneer Kit, is a flexible, Arduino-compatible, Bluetooth® LE development kit for
PSoC™ 4 with AIROC™ Bluetooth® LE.
- CY8CKIT-142, PSoC™ 4 with AIROC™ Bluetooth® LE Module, features a PSoC™ 4 CY8C4xxx-BL MCU with AIROC™
Bluetooth® LE device, two crystals for the antenna matching network, a PCB antenna, and other passives,
while providing access to all GPIOs of the device.
- CY8CKIT-143, PSoC™ 4 with AIROC™ Bluetooth® LE 256 KB module, features a PSoC™ 4 CY8C4xxx-BL MCU with
AIROC™ Bluetooth® LE 256 KB device, two crystals for the antenna matching network, a PCB antenna, and
other passives, while providing access to all GPIOs of the device.
- The MiniProg3 device provides an interface for flash programming and debug.
Datasheet
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PSoC™ 4 MCU with AIROC™ Bluetooth® LE
Based on Arm® Cortex®-M0
PSoC™ Creator
PSoC™ Creator
PSoC™ Creator is a free Windows-based Integrated Design Environment (IDE). It enables concurrent hardware
and firmware design of PSoC™ 3, PSoC™ 4, and PSoC™ 5LP based systems. Create designs using classic, familiar
schematic capture supported by over 100 pre-verified, production-ready PSoC™ Components; see the list of
component datasheets. With PSoC™ Creator, you can
1. Drag and drop component icons to build your hardware system design in the main design workspace
2. Codesign your application firmware with the PSoC™ hardware, using the PSoC™ Creator IDE C compiler
3. Configure components using the configuration tools
4. Explore the library of 100+ components
5. Review component datasheets
1
4
2
5
3
Figure 1
Multiple-sensor example project in PSoC™ Creator contents
Datasheet
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PSoC™ 4 MCU with AIROC™ Bluetooth® LE
Based on Arm® Cortex®-M0
Table of contents
Table of contents
General description ...........................................................................................................................1
Features ...........................................................................................................................................1
More information ..............................................................................................................................3
PSoC™ Creator ..................................................................................................................................4
Table of contents...............................................................................................................................5
Block diagram...................................................................................................................................7
1 Functional definition.......................................................................................................................8
1.1 CPU and memory subsystem .................................................................................................................................8
1.1.1 CPU .......................................................................................................................................................................8
1.1.2 Flash .....................................................................................................................................................................8
1.1.3 SRAM.....................................................................................................................................................................8
1.1.4 SROM ....................................................................................................................................................................8
1.1.5 DMA.......................................................................................................................................................................8
1.2 System Resources...................................................................................................................................................8
1.2.1 Power System ......................................................................................................................................................8
1.2.2 Clock system ........................................................................................................................................................9
1.2.3 IMO clock source ..................................................................................................................................................9
1.2.4 ILO clock source...................................................................................................................................................9
1.2.5 External crystal oscillator (ECO)..........................................................................................................................9
1.2.6 Watch crystal oscillator (WCO)............................................................................................................................9
1.2.7 Watchdog timer....................................................................................................................................................9
1.2.8 Reset ...................................................................................................................................................................10
1.2.9 Voltage Reference ..............................................................................................................................................10
1.3 Bluetooth® LE radio and subsystem ....................................................................................................................11
1.4 Analog blocks ........................................................................................................................................................12
1.4.1 12-bit SAR ADC ...................................................................................................................................................12
1.4.2 Opamps (CTBm block).......................................................................................................................................12
1.4.3 Temperature sensor ..........................................................................................................................................13
1.4.4 Low-power comparators ...................................................................................................................................13
1.5 Programmable digital...........................................................................................................................................13
1.5.1 Universal digital blocks (UDBs) and port interfaces ........................................................................................13
1.6 Fixed-function digital............................................................................................................................................14
1.6.1 Timer/counter/PWM block ................................................................................................................................14
1.6.2 Serial Communication Blocks (SCB) .................................................................................................................14
1.7 GPIO.......................................................................................................................................................................15
1.8 Special-function peripherals................................................................................................................................16
1.8.1 LCD segment drive.............................................................................................................................................16
1.8.2 CAPSENSE™........................................................................................................................................................16
2 Pinouts ........................................................................................................................................17
3 Power ..........................................................................................................................................27
4 Development support ...................................................................................................................28
4.1 Documentation .....................................................................................................................................................28
4.2 Online ....................................................................................................................................................................28
4.3 Tools ......................................................................................................................................................................28
5 Electrical specifications.................................................................................................................29
5.1 Absolute maximum ratings .................................................................................................................................29
5.2 Device-level specifications ...................................................................................................................................30
5.2.1 GPIO....................................................................................................................................................................33
5.2.2 XRES ...................................................................................................................................................................35
5.3 Analog peripherals................................................................................................................................................36
5.3.1 Opamp................................................................................................................................................................36
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PSoC™ 4 MCU with AIROC™ Bluetooth® LE
Based on Arm® Cortex®-M0
Table of contents
5.3.2 Temperature sensor ..........................................................................................................................................38
5.3.3 SAR ADC..............................................................................................................................................................39
5.3.4 CSD .....................................................................................................................................................................40
5.4 Digital peripherals.................................................................................................................................................41
5.4.1 Timer ..................................................................................................................................................................41
5.4.2 Counter ..............................................................................................................................................................42
5.4.3 Pulse width modulation (PWM) ........................................................................................................................43
5.4.4 I2C .......................................................................................................................................................................43
5.4.5 LCD direct drive..................................................................................................................................................44
5.4.6 SPI specifications...............................................................................................................................................45
5.5 Memory..................................................................................................................................................................46
5.6 System resources..................................................................................................................................................47
5.6.1 Power-on reset (POR) ........................................................................................................................................47
5.6.2 Voltage monitors ...............................................................................................................................................48
5.6.3 SWD interface ....................................................................................................................................................48
5.6.4 Internal main oscillator .....................................................................................................................................49
5.6.5 Internal low-speed oscillator ............................................................................................................................49
6 Ordering information ....................................................................................................................55
6.1 Ordering code definitions.....................................................................................................................................56
7 Packaging ....................................................................................................................................57
7.1 WLCSP compatibility ............................................................................................................................................59
8 Acronyms.....................................................................................................................................63
9 Document conventions..................................................................................................................67
9.1 Units of measure ...................................................................................................................................................67
Revision history ..............................................................................................................................68
Datasheet
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PSoC™ 4 MCU with AIROC™ Bluetooth® LE
Based on Arm® Cortex®-M0
Block diagram
Block diagram
CPU Subsystem
PSoC™
4200
SWD/ TC
SPCIF
Cortex®
Flash
Up to 256 KB
SRAM
Up to 32 KB
ROM
8 KB
DataWire /
DMA
M0
32-bit
AHB- Lite
48 MHz
FAST MUL
Read Accelerator
SRAM Controller
ROM Controller
Initiator /MMIO
NVIC , IRQMUX
System Resources
System Interconnect (Multi Layer AHB )
Peripheral Interconnect (MMIO)
Power
Sleep Control
WIC
Peripherals
POR
REF
LVD
BOD
PCLK
PWRSYS
NVLatches
Programmable
Programmable
Digital
Bluetooth® Low
Energy Subsystem
Clock
Clock Control
WDT
Analog
SAR ADC
( 12-bit)
IMO
ILO
Bluetooth® LE Baseband
Peripheral
UDB
...
UDB
Reset
1
KB SRAM
Reset Control
XRES
GFSK Modem
x1
x4
2. 4 GHz
GFSK
Radio
Test
Digital DFT
Analog DFT
CTBm
x OpAmp
SARMUX
x2
2
Port Interface & Digital System Interconnect ( DSI)
I/O : Antenna/Power/Crystal
High Speed I / O Matrix
Power Modes
Active/Sleep
DeepSleep
36 x GPIOs , 2 x GPIO_ OVT
I/O Subsystem
Hibernate
The PSoC™ 4 CY8C42xx-BL MCU with AIROC™ Bluetooth® LE devices include extensive support for programming,
testing, debugging, and tracing both hardware and firmware.
The Arm® SWD interface supports all programming and debug features of the device.
Complete debug-on-chip functionality enables full-device debugging in the final system using the standard
production device. It does not require special interfaces, debugging pods, simulators, or emulators. Only the
standard programming connections are required to fully support debugging.
The PSoC™ Creator IDE provides fully integrated programming and debugging support for the PSoC™ 4
CY8C42xx-BL MCU with AIROC™ Bluetooth® LE devices. The SWD interface is fully compatible with
industry-standard third-party tools. With the ability to disable debug features, very robust flash protection, and
allowing customer-proprietary functionality to be implemented in on-chip programmable blocks, the PSoC™ 4
CY8C42xx-BL MCU with AIROC™ Bluetooth® LE family provides a level of security not possible with multi-chip
application solutions or with microcontrollers.
Debug circuits are enabled by default and can only be disabled in firmware. If not enabled, the only way to
re-enable them is to erase the entire device, clear flash protection, and reprogram the device with the new
firmware that enables debugging.
Additionally, all device interfaces can be permanently disabled (device security) for applications concerned
about phishing attacks due to a maliciously reprogrammed device or attempts to defeat security by starting and
interrupting flash programming sequences. Because all programming, debug, and test interfaces are disabled
when maximum device security is enabled, PSoC™ 4 CY8C42xx-BL MCU with AIROC™ Bluetooth® LE with device
security enabled may not be returned for failure analysis. This is a trade-off the PSoC™ 4 CY8C42xx-BL MCU with
AIROC™ Bluetooth® LE allows the customer to make.
Datasheet
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PSoC™ 4 MCU with AIROC™ Bluetooth® LE
Based on Arm® Cortex®-M0
Functional definition
1
Functional definition
CPU and memory subsystem
CPU
1.1
1.1.1
The Cortex®-M0 CPU in PSoC™ 4 CY8C42xx-BL MCU with AIROC™ Bluetooth® LE is part of the 32-bit MCU
subsystem, which is optimized for low-power operation with extensive clock gating. It mostly uses 16-bit
instructions and executes a subset of the Thumb-2 instruction set. This enables fully compatible binary upward
migration of the code to higher-performance processors such as Cortex®-M3 and M4. The implementation
includes a hardware multiplier that provides a 32-bit result in one cycle. It includes a nested vectored interrupt
controller (NVIC) block with 32 interrupt inputs and a wakeup interrupt controller (WIC). The WIC can wake the
processor up from the Deep Sleep mode, allowing power to the main processor to be switched off when the chip
is in the Deep Sleep mode. The Cortex®-M0 CPU provides a nonmaskable interrupt (NMI) input, which is made
available to the user when it is not in use for system functions requested by the user.
The CPU also includes an SWD interface, which is a 2-wire form of JTAG; the debug configuration used for PSoC™
4 CY8C42xx-BL MCU with AIROC™ Bluetooth® LE has four break-point (address) comparators and two watchpoint
(data) comparators.
1.1.2
Flash
The PSoC™ 4 CY8C42xx-BL MCU with AIROC™ Bluetooth® LE device has a flash module with 256 KB of flash
memory, tightly coupled to the CPU to improve average access times from the flash block. The flash block is
designed to deliver 2 wait-state (WS) access time at 48 MHz and with 1-WS access time at 24 MHz. The flash
accelerator delivers 85% of single-cycle SRAM access performance on average. Part of the flash module can be
used to emulate EEPROM operation if required. Maximum erase and program time is 20 ms per row (256 bytes).
This also applies to the emulated EEPROM.
1.1.3
SRAM
SRAM memory is retained during Hibernate.
1.1.4
SROM
The 8-KB supervisory ROM contains a library of executable functions for flash programming. These functions are
accessed through supervisory calls (SVC) and enable in-system programming of the flash memory.
1.1.5
DMA
A DMA engine, with eight channels, is provided that can do 32-bit transfers and has chainable ping-pong
descriptors.
1.2
System Resources
Power System
1.2.1
The power system is described in detail in the section “Power” on page 27. It provides an assurance that the
voltage levels are as required for the respective modes, and can either delay the mode entry (on power-on reset
(POR), for example) until voltage levels are as required or generate resets (brownout detect (BOD)) or interrupts
when the power supply reaches a particular programmable level between 1.8 and 4.5 V (low voltage detect
(LVD)). PSoC™ 4 CY8C42xx-BL MCU with AIROC™ Bluetooth® LE operates with a single external supply (1.71 to 5.5 V
without radio, and 1.9 V to 5.5 V with radio). The device has five different power modes; transitions between these
modes are managed by the power system. PSoC™ 4 CY8C42xx-BL MCU with AIROC™ Bluetooth® LE provides Sleep,
Deep Sleep, Hibernate, and Stop low-power modes. Refer to the Technical Reference Manual for more details.
Datasheet
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PSoC™ 4 MCU with AIROC™ Bluetooth® LE
Based on Arm® Cortex®-M0
Functional definition
1.2.2
Clock system
The PSoC™ 4 CY8C42xx-BL MCU with AIROC™ Bluetooth® LE clock system is responsible for providing clocks to all
subsystems that require clocks and for switching between different clock sources without glitching. In addition,
the clock system ensures that no metastable conditions occur.
The clock system for PSoC™ 4 CY8C42xx-BL MCU with AIROC™ Bluetooth® LE consists of the internal main
oscillator (IMO), the internal low-speed oscillator (ILO), the 24-MHz external crystal oscillator (ECO) and the
32-kHz watch crystal oscillator (WCO). In addition, an external clock may be supplied from a pin.
1.2.3
IMO clock source
The IMO is the primary source of internal clocking in PSoC™ 4 CY8C42xx-BL MCU with AIROC™ Bluetooth® LE. It is
trimmed during testing to achieve the specified accuracy. Trim values are stored in nonvolatile latches (NVL).
Additional trim settings from flash can be used to compensate for changes. The IMO default frequency is 24 MHz
and it can be adjusted between 3 to 48 MHz in steps of 1 MHz. The IMO tolerance with Infineon-provided
calibration settings is ±2%.
1.2.4
ILO clock source
The ILO is a very low-power oscillator, which is primarily used to generate clocks for the peripheral operation in
the Deep Sleep mode. ILO-driven counters can be calibrated to the IMO to improve accuracy. A software
component is provided, which does the calibration.
1.2.5
External crystal oscillator (ECO)
The ECO is used as the active clock for the Bluetooth® LE subsystem to meet the ±50-ppm clock accuracy of the
Bluetooth® 4.2 Specification. PSoC™ 4 CY8C42xx-BL MCU with AIROC™ Bluetooth® LE includes a tunable load
capacitor to tune the crystal clock frequency by measuring the actual clock frequency. The high-accuracy ECO
clock can also be used as a system clock.
1.2.6
Watch crystal oscillator (WCO)
The WCO is used as the sleep clock for the Bluetooth® LE subsystem to meet the ±500-ppm clock accuracy for the
Bluetooth® 4.2 Specification. The sleep clock provides an accurate sleep timing and enables wakeup at the
specified advertisement and connection intervals. The WCO output can be used to realize the real-time clock
(RTC) function in firmware.
1.2.7
Watchdog timer
A watchdog timer is implemented in the clock block running from the ILO or from the WCO; this allows the
watchdog operation during Deep Sleep and generates a watchdog reset if not serviced before the timeout occurs.
The watchdog reset is recorded in the Reset Cause register. With the WCO and firmware, an accurate real-time
clock (within the bounds of the 32-kHz crystal accuracy) can be realized.
Datasheet
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PSoC™ 4 MCU with AIROC™ Bluetooth® LE
Based on Arm® Cortex®-M0
Functional definition
HFCLK
ECO
Prescaler
SYSCLK
Divider
/2n (n=0..3)
Divider 0
(/16)
PER0_CLK
IMO
Divider 9
(/16)
EXTCLK
Fractional
Divider 0
(/16.5)
PER15_CLK
LFCLK
Fractional
Divider1
(/16.5)
WCO
ILO
Figure 2
PSoC™ 4 CY8C42xx-BL MCU with AIROC™ Bluetooth® LE MCU clocking architecture
The HFCLK signal can be divided down (see Figure 2) to generate synchronous clocks for the UDBs, and the
analog and digital peripherals. There are a total of 12 clock dividers for PSoC™ 4 CY8C42xx-BL MCU with AIROC™
Bluetooth® LE: ten with 16-bit divide capability and two with 16.5-bit divide capability. This allows the generation
of 16 divided clock signals, which can be used by peripheral blocks. The analog clock leads the digital clocks to
allow analog events to occur before the digital clock-related noise is generated. The 16-bit and 16.5-bit dividers
allow a lot of flexibility in generating fine-grained frequency values and are fully supported in PSoC™ Creator.
1.2.8
Reset
PSoC™ 4 CY8C42xx-BL MCU with AIROC™ Bluetooth® LE device can be reset from a variety of sources including a
software reset. Reset events are asynchronous and guarantee reversion to a known state. The reset cause is
recorded in a register, which is sticky through resets and allows the software to determine the cause of the reset.
An XRES pin is reserved for an external reset to avoid complications with the configuration and multiple pin
functions during power-on or reconfiguration. The XRES pin has an internal pull-up resistor that is always
enabled.
1.2.9
Voltage Reference
The PSoC™ 4 CY8C42xx-BL MCU with AIROC™ Bluetooth® LE reference system generates all internally required
references. A one-percent voltage reference spec is provided for the 12-bit ADC. To allow better signal-to-noise
ratios (SNR) and better absolute accuracy, it is possible to bypass the internal reference using a REF pin or use an
external reference for the SAR. See Table 21 for details.
Datasheet
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PSoC™ 4 MCU with AIROC™ Bluetooth® LE
Based on Arm® Cortex®-M0
Functional definition
1.3
Bluetooth® LE radio and subsystem
PSoC™ 4 CY8C42xx-BL MCU with AIROC™ Bluetooth® LE incorporates a Bluetooth® Smart subsystem that contains
the Physical Layer (PHY) and Link Layer (LL) engines with an embedded AES-128 security engine. The physical
layer consists of the digital PHY and the RF transceiver that transmits and receives GFSK packets at 1 Mbps over
a 2.4-GHz ISM band, which is compliant with Bluetooth® Smart Bluetooth® Specification 4.2. The baseband
controller is a composite hardware and firmware implementation that supports both master and slave modes.
Key protocol elements, such as HCI and link control, are implemented in firmware. Time-critical functional
blocks, such as encryption, CRC, data whitening, and access code correlation, are implemented in hardware (in
the LL engine).
The RF transceiver contains an integrated balun, which provides a single-ended RF port pin to drive a 50-Ω
antenna via a matching/filtering network. In the receive direction, this block converts the RF signal from the
antenna to a digital bit stream after performing GFSK demodulation. In the transmit direction, this block
performs GFSK modulation and then converts a digital baseband signal to a radio frequency before transmitting
it to air through the antenna.
The Bluetooth® smart radio and subsystem (BLESS) requires a 1.9-V minimum supply (the range varies from 1.9 V
to 5.5 V).
Key features of BLESS are as follows:
• Master and slave single-mode protocol stack with logical link control and adaptation protocol (L2CAP), attribute
(ATT), and security manager (SM) protocols
• API access to generic attribute profile (GATT), generic access profile (GAP), and L2CAP
• L2CAP connection-oriented channel
• GAP features
- Broadcaster, Observer, Peripheral, and Central roles
- Security mode 1: Level 1, 2, 3, and 4
- Security mode 2: Level 1 and 2
- User-defined advertising data
- Multiple bond support
• GATT features
- GATT client and server
- Supports GATT sub-procedures
- 32-bit universally unique identifier (UUID)
• Security Manager (SM)
- Pairing methods: Just works, Passkey Entry, Out of Band, and Numeric Comparison
- Authenticated man-in-the-middle (MITM) protection and data signing
- LE secure connections (Bluetooth® 4.2 feature)
• Link layer (LL)
- Master and Slave roles
- 128-bit AES engine
- Encryption
- Low-duty cycle advertising
- LE ping
- LE data packet length extension (Bluetooth® 4.2 feature)
- Link layer privacy (with extended scanning filter policy, Bluetooth® 4.2 feature)
• Supports all SIG-adopted Bluetooth® LE profiles
Datasheet
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PSoC™ 4 MCU with AIROC™ Bluetooth® LE
Based on Arm® Cortex®-M0
Functional definition
1.4
Analog blocks
12-bit SAR ADC
1.4.1
The 12-bit, 1-Msps SAR ADC can operate at a maximum clock rate of 18 MHz and requires a minimum of 18 clocks
at that frequency to do a 12-bit conversion.
The block functionality is augmented for the user by adding a reference buffer to it (trimmable to ±1%) and by
providing the choice of three internal voltage references, VDD, VDD/2, and VREF (nominally 1.024 V), as well as an
external reference through a REF pin. The sample-and-hold (S/H) aperture is programmable; it allows the gain
bandwidth requirements of the amplifier driving the SAR inputs, which determine its settling time, to be relaxed
if required. System performance will be 65 dB for true 12-bit precision provided appropriate references are used
and system noise levels permit it. To improve the performance in noisy conditions, it is possible to provide an
external bypass (through a fixed pin location) for the internal reference amplifier.
The SAR is connected to a fixed set of pins through an 8-input sequencer. The sequencer cycles through the
selected channels autonomously (sequencer scan) and does so with zero switching overhead (that is, the
aggregate sampling bandwidth is equal to 1 Msps whether it is for a single channel or distributed over several
channels). The sequencer switching is effected through a state machine or through firmware-driven switching. A
feature provided by the sequencer is the buffering of each channel to reduce CPU interrupt-service requirements.
To accommodate signals with varying source impedances and frequencies, it is possible to have different sample
times programmable for each channel. Also, the signal range specification through a pair of range registers (low
and high range values) is implemented with a corresponding out-of-range interrupt if the digitized value exceeds
the programmed range; this allows fast detection of out-of-range values without having to wait for a sequencer
scan to be completed and the CPU to read the values and check for out-of-range values in software.
The SAR is able to digitize the output of the on-chip temperature sensor for calibration and other
temperature-dependent functions. The SAR is not available in Deep Sleep and Hibernate modes as it requires a
high-speed clock (up to 18 MHz). The SAR operating range is 1.71 to 5.5 V.
AHB System Bus and Programmable Logic
Interconnect
SAR Sequencer
Sequencing
and Control
Data and
Status Flags
POS
SARADC
NEG
External
Reference
and Bypass
Reference
Selection
(optional)
VDDD
VREF
VDD/2
Inputs from other Ports
Figure 3
SAR ADC system diagram
1.4.2
Opamps (CTBm block)
PSoC™ CY8C42x8_BLE has four opamps with Comparator modes, which allow most common analog functions to
be performed on-chip, eliminating external components. PGAs, voltage buffers, filters, transimpedance
amplifiers, and other functions can be realized with external passives saving power, cost, and space. The on-chip
opamps are designed with enough bandwidth to drive the sample-and-hold circuit of the ADC without requiring
external buffering.
Datasheet
12
002-23053 Rev. *B
2023-03-29
PSoC™ 4 MCU with AIROC™ Bluetooth® LE
Based on Arm® Cortex®-M0
Functional definition
1.4.3
Temperature sensor
PSoC™ 4 CY8C42xx-BL MCU with AIROC™ Bluetooth® LE has an on-chip temperature sensor. This consists of a
diode, which is biased by a current source that can be disabled to save power. The temperature sensor is
connected to the ADC, which digitizes the reading and produces a temperature value by using a Infineon-supplied
software that includes calibration and linearization.
1.4.4
Low-power comparators
PSoC™ 4 CY8C42xx-BL MCU with AIROC™ Bluetooth® LE has a pair of low-power comparators, which can also
operate in Deep Sleep and Hibernate modes. This allows the analog system blocks to be disabled while retaining
the ability to monitor external voltage levels during low-power modes. The comparator outputs are normally
synchronized to avoid metastability unless operating in an asynchronous power mode (Hibernate) where the
system wake-up circuit is activated by a comparator-switch event.
1.5
Programmable digital
1.5.1
Universal digital blocks (UDBs) and port interfaces
The PSoC™ 4XX8 BLE 4.2 has four UDBs; the UDB array also provides a switched Digital System Interconnect (DSI)
fabric that allows signals from peripherals and ports to be routed to and through the UDBs for communication
and control.
System
Interconnect
CPU
Sub -system
Clocks
8 to 32
4 to8
UDBIF
BUS IF IRQ IF CLK IF
Port IF
DSI
DSI
UDB
UDB
Routing
Channels
UDB
UDB
DSI
DSI
Programmable Digital Subsystem
Figure 4
UDB array
UDBs can be clocked from a clock-divider block, from a port interface (required for peripherals such as SPI), and
from the DSI network directly or after synchronization.
A port interface is defined, which acts as a register that can be clocked with the same source as the PLDs inside
the UDB array. This allows a faster operation because the inputs and outputs can be registered at the port
interface close to the I/O pins and at the edge of the array. The port interface registers can be clocked by one of
the I/Os from the same port. This allows interfaces such as SPI to operate at higher clock speeds by eliminating
the delay for the port input to be routed over DSI and used to register other inputs (see Figure 5).
Datasheet
13
002-23053 Rev. *B
2023-03-29
PSoC™ 4 MCU with AIROC™ Bluetooth® LE
Based on Arm® Cortex®-M0
Functional definition
High Speed I/O Matrix
To Clock
Tree
8
4
8
8
Input Registers
Output Registers
Enables
7
6
. . .
0
7
6
. . .
0
3
2
1
0
Digital
GlobalClocks
9
4
[1]
[0]
[1]
Clock Selector
Block from
UD B
2
2
3
DSI Signals
1 I/O Signal
,
4
8
8
[1]
[0]
[1]
Reset Selector
Block from
UD B
From DSI
To DSI
From DSI
Figure 5
Port interface
UDBs can generate interrupts (one UDB at a time) to the interrupt controller. UDBs retain the ability to connect
to any pin on the chip through the DSI.
1.6
Fixed-function digital
1.6.1
Timer/counter/PWM block
The timer/counter/PWM block consists of four 16-bit counters with user-programmable period length. There is a
capture register to record the count value at the time of an event (which may be an I/O event), a period register
which is used to either stop or auto-reload the counter when its count is equal to the period register, and compare
registers to generate compare value signals which are used as PWM duty cycle outputs. The block also provides
true and complementary outputs with programmable offset between them to allow the use as deadband
programmable complementary PWM outputs. It also has a Kill input to force outputs to a predetermined state;
for example, this is used in motor-drive systems when an overcurrent state is indicated and the PWMs driving the
FETs need to be shut off immediately with no time for software intervention.
1.6.2
Serial Communication Blocks (SCB)
PSoC™ 4 CY8C42xx-BL MCU with AIROC™ Bluetooth® LE has two SCBs, each of which can implement an I2C, UART,
or SPI interface.
I2C mode: The hardware I2C block implements a full multi-master and slave interface (it is capable of multimaster
arbitration). This block is capable of operating at speeds of up to 1 Mbps (Fast Mode Plus) and has flexible
buffering options to reduce the interrupt overhead and latency for the CPU. It also supports EzI2C that creates a
mailbox address range in the memory of PSoC™ 4 CY8C42xx-BL MCU with AIROC™ Bluetooth® LE and effectively
reduces the I2C communication to reading from and writing to an array in the memory. In addition, the block
supports an 8-deep FIFO for receive and transmit, which, by increasing the time given for the CPU to read the
data, greatly reduces the need for clock stretching caused by the CPU not having read the data on time. The FIFO
mode is available in all channels and is very useful in the absence of DMA.
The I2C peripheral is compatible with I2C Standard-mode, Fast-mode, and Fast-Mode Plus devices as defined in
the NXP I2C-bus specification and user manual (UM10204). The I2C bus I/O is implemented with GPIO in
open-drain modes.
SCB1 is fully compliant with Standard mode (100 kHz), Fast mode (400 kHz), and Fast-Mode Plus (1 MHz) I2C
signaling specifications when routed to GPIO pins P5[0] and P5[1], except for hot-swap capability during I2C
active communication. The remaining GPIOs do not meet the hot-swap specification (VDD off; draw < 10-µA
current) for Fast mode and Fast-Mode Plus, IOL Spec (20 mA) for Fast-Mode Plus, hysteresis spec (0.05 VDD) for
Fast mode and Fast-Mode Plus, and minimum fall time spec for Fast mode and Fast-Mode Plus.
Datasheet
14
002-23053 Rev. *B
2023-03-29
PSoC™ 4 MCU with AIROC™ Bluetooth® LE
Based on Arm® Cortex®-M0
Functional definition
• GPIO cells, including P5.0 and P5.1, cannot be hot-swapped or powered up independent of the rest of the I2C
system.
• The GPIO pins P5.0 and P5.1 are over-voltage tolerant but cannot be hot-swapped or powered up independent
of the rest of the I2C system
• Fast-Mode Plus has an IOL specification of 20 mA at a VOL of 0.4 V. The GPIO cells can sink a maximum of 8 mA
IOL with a VOL maximum of 0.6 V.
• Fast-mode and Fast-Mode Plus specify minimum Fall times, which are not met with the GPIO cell; the
Slow-Strong mode can help meet this spec depending on the bus load.
UART mode: This is a full-feature UART operating at up to 1 Mbps. It supports automotive single-wire interface
(LIN), infrared interface (IrDA), and SmartCard (ISO7816) protocols, all of which are minor variants of the basic
UART protocol. In addition, it supports the 9-bit multiprocessor mode that allows the addressing of peripherals
connected over common RX and TX lines. Common UART functions such as parity error, break detect, and frame
error are supported. An 8-deep FIFO allows much greater CPU service latencies to be tolerated. Note that
hardware handshaking is not supported. This is not commonly used and can be implemented with a UDB-based
UART in the system, if required.
SPI mode: The SPI mode supports full Motorola SPI, TI Secure Simple Pairing (SSP) (essentially adds a start pulse
that is used to synchronize SPI Codecs), and National Microwire (half-duplex form of SPI). The SPI block can use
the FIFO for transmit and receive.
1.7
GPIO
PSoC™ 4 CY8C42xx-BL MCU with AIROC™ Bluetooth® LE has 36 GPIOs. The GPIO block implements the following:
• Eight drive strength modes:
- Analog input mode (input and output buffers disabled)
- Input only
- Weak pull-up with strong pull-down
- Strong pull-up with weak pull-down
- Open drain with strong pull-down
- Open drain with strong pull-up
- Strong pull-up with strong pull-down
- Weak pull-up with weak pull-down
• Input threshold select (CMOS or LVTTL)
• Pins 0 and 1 of Port 5 are overvoltage-tolerant pins
• Individual control of input and output buffer enabling/disabling in addition to drive-strength modes
• Hold mode for latching previous state (used for retaining the I/O state in Deep Sleep and Hibernate modes)
• Selectable slew rates for dV/dt-related noise control to improve EMI
The pins are organized in logical entities called ports, which are 8-bit in width. During power-on and reset, the
blocks are forced to the disable state so as not to crowbar any inputs and/or cause excess turn-on current. A
multiplexing network known as a high-speed I/O matrix (HSIOM) is used to multiplex between various signals that
may connect to an I/O pin. Pin locations for fixed-function peripherals are also fixed to reduce internal
multiplexing complexity (these signals do not go through the DSI network). DSI signals are not affected by this
and any pin may be routed to any UDB through the DSI network.
Data output and pin-state registers store, respectively, the values to be driven on the pins and the states of the
pins themselves.
Every I/O pin can generate an interrupt if so enabled and each I/O port has an interrupt request (IRQ) and interrupt
service routine (ISR) vector associated with it (5 for PSoC™ 4 CY8C42xx-BL MCU with AIROC™ Bluetooth® LE).
Datasheet
15
002-23053 Rev. *B
2023-03-29
PSoC™ 4 MCU with AIROC™ Bluetooth® LE
Based on Arm® Cortex®-M0
Functional definition
1.8
Special-function peripherals
LCD segment drive
1.8.1
PSoC™ 4 CY8C42xx-BL MCU with AIROC™ Bluetooth® LE has an LCD controller, which can drive up to four
commons and up to 32 segments. It uses full digital methods to drive the LCD segments requiring no generation
of internal LCD voltages. The two methods used are referred to as digital correlation and PWM.
The digital correlation method modulates the frequency and levels of the common and segment signals to
generate the highest RMS voltage across a segment to light it up or to keep the RMS signal zero. This method is
good for STN displays but may result in reduced contrast with TN (cheaper) displays.
The PWM method drives the panel with PWM signals to effectively use the capacitance of the panel to provide the
integration of the modulated pulse-width to generate the desired LCD voltage. This method results in higher
power consumption but can result in better results when driving TN displays. LCD operation is supported during
Deep Sleep mode, refreshing a small display buffer (four bits; one 32-bit register per port).
1.8.2
CAPSENSE™
CAPSENSE™ is supported on all pins in PSoC™ 4 CY8C42xx-BL MCU with AIROC™ Bluetooth® LE through a
CAPSENSE™ Sigma-Delta (CSD) block that can be connected to any pin through an analog mux bus that any GPIO
pin can be connected to via an Analog switch. CAPSENSE™ function can thus be provided on any pin or group of
pins in a system under software control. A Component is provided for the CAPSENSE™ block to make it easy for
the user.
The shield voltage can be driven on another mux bus to provide liquid-tolerance capability. Liquid tolerance is
provided by driving the shield electrode in phase with the sense electrode to keep the shield capacitance from
attenuating the sensed input.
The CAPSENSE™ block has two IDACs which can be used for general purposes if CAPSENSE™ is not being used
(both IDACs are available in that case) or if CAPSENSE™ is used without liquid tolerance (one IDAC is available).
Datasheet
16
002-23053 Rev. *B
2023-03-29
PSoC™ 4 MCU with AIROC™ Bluetooth® LE
Based on Arm® Cortex®-M0
Pinouts
2
Pinouts
Table 1, Table 2, and Table 3 show pin list for 56-pin QFN, 68-ball WLCSP, and 76-ball WLCSP packages of PSoC™
4 CY8C42xx-BL MCU with AIROC™ Bluetooth® LE respectively. Port 3 consists of the high-speed analog inputs for
the SAR mux. All pins support CSD CAPSENSE™ and analog mux bus connections.
Table 1
PSoC™ 4 CY8C42xx-BL MCU with AIROC™ Bluetooth® LE pin list
(56-pin QFN package)
Pin
1
2
3
4
Name
VDDD
XTAL32O/P6.0
XTAL32I/P6.1
XRES
P4.0
Type
POWER
CLOCK
CLOCK
RESET
GPIO
Description
1.71-V to 5.5-V digital supply
32.768-kHz crystal
32.768-kHz crystal or external clock input
Reset, active LOW
5
Port 4 Pin 0, lcd, csd
6
P4.1
GPIO
Port 4 Pin 1, lcd, csd
7
P5.0
GPIO
Port 5 Pin 0, lcd, csd
8
P5.1
GPIO
Port 5 Pin 1, lcd, csd
9
VSSD
VDDR
GANT1
ANT
GANT2
VDDR
VDDR
XTAL24I
XTAL24O
VDDR
P0.0
P0.1
P0.2
P0.3
VDDD
P0.4
GROUND
POWER
GROUND
ANTENNA
GROUND
POWER
POWER
CLOCK
CLOCK
POWER
GPIO
GPIO
GPIO
GPIO
POWER
GPIO
Digital ground
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
1.9-V to 5.5-V radio supply
Antenna shielding ground
Antenna pin
Antenna shielding ground
1.9-V to 5.5-V radio supply
1.9-V to 5.5-V radio supply
24-MHz crystal or external clock input
24-MHz crystal
1.9-V to 5.5-V radio supply
Port 0 Pin 0, lcd, csd
Port 0 Pin 1, lcd, csd
Port 0 Pin 2, lcd, csd
Port 0 Pin 3, lcd, csd
1.71-V to 5.5-V digital supply
Port 0 Pin 4, lcd, csd
Port 0 Pin 5, lcd, csd
Port 0 Pin 6, lcd, csd
Port 0 Pin 7, lcd, csd
Port 1 Pin 0, lcd, csd
Port 1 Pin 1, lcd, csd
Port 1 Pin 2, lcd, csd
Port 1 Pin 3, lcd, csd
P0.5
P0.6
P0.7
P1.0
P1.1
P1.2
P1.3
P1.4
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
Port 1 Pin 4, lcd, csd
Port 1 Pin 5, lcd, csd
Port 1 Pin 6, lcd, csd
Port 1 Pin 7, lcd, csd
P1.5
P1.6
P1.7
GPIO
GPIO
GPIO
Datasheet
17
002-23053 Rev. *B
2023-03-29
PSoC™ 4 MCU with AIROC™ Bluetooth® LE
Based on Arm® Cortex®-M0
Pinouts
Table 1
PSoC™ 4 CY8C42xx-BL MCU with AIROC™ Bluetooth® LE pin list
(56-pin QFN package) (continued)
Pin
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
Name
VDDA
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
VREF
VDDA
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
VSSA
VCCD
Type
POWER
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
REF
POWER
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
Description
1.71-V to 5.5-V analog supply
Port 2 Pin 0, lcd, csd
Port 2 Pin 1, lcd, csd
Port 2 Pin 2, lcd, csd
Port 2 Pin 3, lcd, csd
Port 2 Pin 4, lcd, csd
Port 2 Pin 5, lcd, csd
Port 2 Pin 6, lcd, csd
Port 2 Pin 7, lcd, csd
External reference input or bypass capacitor
1.71-V to 5.5-V analog supply
Port 3 Pin 0, lcd, csd
Port 3 Pin 1, lcd, csd
Port 3 Pin 2, lcd, csd
Port 3 Pin 3, lcd, csd
Port 3 Pin 4, lcd, csd
Port 3 Pin 5, lcd, csd
Port 3 Pin 6, lcd, csd
Port 3 Pin 7, lcd, csd
Analog ground
Regulated 1.8-V supply, connect to 1.3-µF
capacitor.
GPIO
GPIO
GROUND
POWER
57
EPAD
GROUND
Ground paddle for the QFN package
Table 2
PSoC™ 4 CY8C42xx-BL MCU with AIROC™ Bluetooth® LE pin list
(68-ball WLCSP package)
Pin
A1
A2
A3
A4
A5
A6
A7
A8
B1
B2
B3
B4
Name
VREF
VSSA
P3.3
Type
REF
GROUND
GPIO
Pin description
External reference input or bypass capacitor
Analog ground
Port 3 Pin 3, lcd, csd
Port 3 Pin 7, lcd, csd
Digital ground
Analog ground
Regulated 1.8-V supply, connect to 1-μF capacitor
1.71-V to 5.5-V radio supply
Port 2 Pin 3, lcd, csd
P3.7
GPIO
VSSD
VSSA
VCCD
VDDD
P2.3
GROUND
GROUND
POWER
POWER
GPI
VSSA
P2.7
P3.4
GROUND
GPIO
GPIO
Analog ground
Port 2 Pin 7, lcd, csd
Port 3 Pin 4, lcd, csd
Datasheet
18
002-23053 Rev. *B
2023-03-29
PSoC™ 4 MCU with AIROC™ Bluetooth® LE
Based on Arm® Cortex®-M0
Pinouts
Table 2
PSoC™ 4 CY8C42xx-BL MCU with AIROC™ Bluetooth® LE pin list
(68-ball WLCSP package) (continued)
Pin
B5
B6
B7
B8
C1
C2
C3
C4
C5
C6
C7
C8
D1
D2
D3
D4
D5
D6
D7
D8
E1
E2
E3
E4
E5
E6
E7
E8
F1
F2
F3
F4
F5
F6
F7
F8
G1
G2
G3
Name
P3.5
P3.6
Type
GPIO
GPIO
CLOCK
CLOCK
GROUND
GPIO
GPIO
GPIO
GPIO
GPIO
RESET
GPIO
GPIO
POWER
GPIO
GPIO
GPIO
GROUND
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GROUND
GROUND
GPIO
GPIO
GPIO
GPIO
GROUND
GROUND
POWER
GPIO
POWER
GPIO
Pin description
Port 3 Pin 5, lcd, csd
Port 3 Pin 6, lcd, csd
32.768-kHz crystal or external clock input
32.768-kHz crystal
XTAL32I/P6.1
XTAL32O/P6.0
VSSA
P2.2
Analog ground
Port 2 Pin 2, lcd, csd
Port 2 Pin 6, lcd, csd
Port 3 Pin 0, lcd, csd
Port 3 Pin 1, lcd, csd
Port 3 Pin 2, lcd, csd
Reset, active LOW
Port 4 Pin 0, lcd, csd
Port 1 Pin 7, lcd, csd
1.71-V to 5.5-V analog supply
Port 2 Pin 0, lcd, csd
Port 2 Pin 1, lcd, csd
Port 2 Pin 5, lcd, csd
Digital ground
Port 4 Pin 1, lcd, csd
Port 5 Pin 0, lcd, csd
Port 1 Pin 2, lcd, csd
Port 1 Pin 3, lcd, csd
Port 1 Pin 4, lcd, csd
Port 1 Pin 5, lcd, csd
Port 1 Pin 6, lcd, csd
Port 2 Pin 4, lcd, csd
Port 5 Pin 1, lcd, csd
Digital ground
P2.6
P3.0
P3.1
P3.2
XRES
P4.0
P1.7
VDDA
P2.0
P2.1
P2.5
VSSD
P4.1
P5.0
P1.2
P1.3
P1.4
P1.5
P1.6
P2.4
P5.1
VSSD
VSSD
P0.7
P0.3
P1.0
P1.1
VSSR
VSSR
VDDR
P0.6
VDDD
P0.2
Digital ground
Port 0 Pin 7, lcd, csd
Port 0 Pin 3, lcd, csd
Port 1 Pin 0, lcd, csd
Port 1 Pin 1, lcd, csd
Radio ground
Radio ground
1.9-V to 5.5-V radio supply
Port 0 Pin 6, lcd, csd
1.71-V to 5.5-V digital supply
Port 0 Pin 2, lcd, csd
Datasheet
19
002-23053 Rev. *B
2023-03-29
PSoC™ 4 MCU with AIROC™ Bluetooth® LE
Based on Arm® Cortex®-M0
Pinouts
Table 2
PSoC™ 4 CY8C42xx-BL MCU with AIROC™ Bluetooth® LE pin list
(68-ball WLCSP package) (continued)
Pin
G4
G5
G6
G7
G8
H1
H2
H3
H4
H5
H6
H7
J1
Name
VSSD
VSSR
VSSR
GANT
VSSR
P0.5
P0.1
XTAL24O
XTAL24I
VSSR
Type
GROUND
GROUND
GROUND
GROUND
GROUND
GPIO
Pin description
Digital ground
Radio ground
Radio ground
Antenna shielding ground
Radio ground
Port 0 Pin 5, lcd, csd
Port 0 Pin 1, lcd, csd
24-MHz crystal
GPIO
CLOCK
CLOCK
GROUND
GROUND
ANTENNA
GPIO
24-MHz crystal or external clock input
Radio ground
VSSR
ANT
P0.4
P0.0
Radio ground
Antenna pin
Port 0 Pin 4, lcd, csd
Port 0 Pin 0, lcd, csd
1.9-V to 5.5-V radio supply
1.9-V to 5.5-V radio supply
-
J2
J3
J6
J7
GPIO
VDDR
VDDR
No Connect
POWER
POWER
-
Table 3
PSoC™ 4 CY8C42xx-BL MCU with AIROC™ Bluetooth® LE pin list
(76-ball WLCSP package)
Pin
Name
NC
Type
NC
Description
A1
A2
A3
A4
A5
A6
A7
A8
A9
B1
B2
B3
B4
B5
B6
B7
B8
B9
Do not connect
VREF
VSSA
P3.3
P3.7
VSSD
VSSA
VCCD
VDDD
NB
P2.3
VSSA
P2.7
P3.4
REF
GROUND
GPIO
External reference input or bypass capacitor
Analog ground
Port 3 Pin 3, analog/digital/lcd/csd
Port 3 Pin 7, analog/digital/lcd/csd
Digital ground
GPIO
GROUND
GROUND
POWER
POWER
NO BALL
GPIO
GROUND
GPIO
GPIO
Analog ground
Regulated 1.8-V supply, connect to 1-μF capacitor
1.71-V to 5.5-V digital supply
No Ball
Port 2 Pin 3, analog/digital/lcd/csd
Analog ground
Port 2 Pin 7, analog/digital/lcd/csd
Port 3 Pin 4, analog/digital/lcd/csd
Port 3 Pin 5, analog/digital/lcd/csd
Port 3 Pin 6, analog/digital/lcd/csd
32.768-kHz crystal or external clock input
32.768-kHz crystal
P3.5
GPIO
P3.6
XTAL32I/P6.1
XTAL32O/P6.0
GPIO
CLOCK
CLOCK
Datasheet
20
002-23053 Rev. *B
2023-03-29
PSoC™ 4 MCU with AIROC™ Bluetooth® LE
Based on Arm® Cortex®-M0
Pinouts
Table 3
Pin
PSoC™ 4 CY8C42xx-BL MCU with AIROC™ Bluetooth® LE pin list
(76-ball WLCSP package) (continued)
Name
NC
Type
NC
GROUND
GPIO
GPIO
GPIO
GPIO
GPIO
RESET
GPIO
NC
Description
C1
C2
C3
C4
C5
C6
C7
C8
C9
D1
D2
D3
D4
D5
D6
D7
D8
D9
E1
E2
E3
E4
E5
E6
E7
E8
E9
F1
F2
F3
F4
F5
F6
F7
F8
F9
G1
G2
G3
Do not connect
Analog ground
VSSA
P2.2
P2.6
P3.0
P3.1
P3.2
XRES
P4.0
NC
Port 2 Pin 2, analog/digital/lcd/csd
Port 2 Pin 6, analog/digital/lcd/csd
Port 3 Pin 0, analog/digital/lcd/csd
Port 3 Pin 1, analog/digital/lcd/csd
Port 3 Pin 2, analog/digital/lcd/csd
Reset, active LOW
Port 4 Pin 0, analog/digital/lcd/csd
Do not connect
P1.7
VDDA
P2.0
P2.1
P2.5
VSSD
P4.1
P5.0
NC
GPIO
POWER
GPIO
GPIO
GPIO
GROUND
GPIO
GPIO
Port 1 Pin 7, analog/digital/lcd/csd
1.71-V to 5.5-V analog supply
Port 2 Pin 0, analog/digital/lcd/csd
Port 2 Pin 1, analog/digital/lcd/csd
Port 2 Pin 5, analog/digital/lcd/csd
Digital ground
Port 4 Pin 1, analog/digital/lcd/csd
Port 5 Pin 0, analog/digital/lcd/csd
Do not connect
NC
P1.2
P1.3
P1.4
P1.5
P1.6
P2.4
P5.1
VSSD
NC
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GROUND
NC
Port 1 Pin 2, analog/digital/lcd/csd
Port 1 Pin 3, analog/digital/lcd/csd
Port 1 Pin 4, analog/digital/lcd/csd
Port 1 Pin 5, analog/digital/lcd/csd
Port 1 Pin 6, analog/digital/lcd/csd
Port 2 Pin 4, analog/digital/lcd/csd
Port 5 Pin 1, analog/digital/lcd/csd
Digital ground
Do not connect
VSSD
P0.7
P0.3
P1.0
P1.1
VSSR
VSSR
VDDR
NC
GROUND
GPIO
GPIO
GPIO
GPIO
GROUND
GROUND
POWER
NC
Digital ground
Port 0 Pin 7, analog/digital/lcd/csd
Port 0 Pin 3, analog/digital/lcd/csd
Port 1 Pin 0, analog/digital/lcd/csd
Port 1 Pin 1, analog/digital/lcd/csd
Radio ground
Radio ground
1.9-V to 5.5-V radio supply
Do not connect
P0.6
VDDD
GPIO
POWER
Port 0 Pin 6, analog/digital/lcd/csd
1.71-V to 5.5-V digital supply
Datasheet
21
002-23053 Rev. *B
2023-03-29
PSoC™ 4 MCU with AIROC™ Bluetooth® LE
Based on Arm® Cortex®-M0
Pinouts
Table 3
Pin
PSoC™ 4 CY8C42xx-BL MCU with AIROC™ Bluetooth® LE pin list
(76-ball WLCSP package) (continued)
Name
P0.2
VSSD
VSSR
VSSR
GANT
VSSR
Type
GPIO
Description
Port 0 Pin 2, analog/digital/lcd/csd
Digital ground
Radio ground
Radio ground
Antenna shielding ground
Radio ground
Do not connect
G4
G5
G6
G7
G8
G9
H1
H2
H3
H4
H5
H6
H7
H8
J1
GROUND
GROUND
GROUND
GROUND
GROUND
NC
NC
P0.5
P0.1
XTAL24O
XTAL24I
VSSR
GPIO
GPIO
CLOCK
CLOCK
GROUND
GROUND
Port 0 Pin 5, analog/digital/lcd/csd
Port 0 Pin 1, analog/digital/lcd/csd
24-MHz crystal
24-MHz crystal or external clock input
Radio ground
VSSR
Radio ground
ANT
ANTENNA Antenna pin
NC
P0.4
P0.0
NC
GPIO
GPIO
POWER
POWER
–
Do not connect
J2
J3
J4
J7
Port 0 Pin 4, analog/digital/lcd/csd
Port 0 Pin 0, analog/digital/lcd/csd
1.9-V to 5.5-V radio supply
1.9-V to 5.5-V radio supply
–
VDDR
VDDR
NO CONNECT
J8
Datasheet
22
002-23053 Rev. *B
2023-03-29
PSoC™ 4 MCU with AIROC™ Bluetooth® LE
Based on Arm® Cortex®-M0
Pinouts
High-speed I/O matrix (HSIOM) is a group of high-speed switches that routes GPIOs to the resources inside the
device. These resources include CAPSENSE™, TCPWMs, I2C, SPI, UART, and LCD. HSIOM_PORT_SELx are
32-bit-wide registers that control the routing of GPIOs. Each register controls one port; four dedicated bits are
assigned to each GPIO in the port. This provides up to 16 different options for GPIO routing as shown in Table 4.
Table 4
Value
HSIOM port settings
Description
0
Firmware-controlled GPIO
1
Output is firmware-controlled, but Output Enable (OE) is controlled from DSI.
Both output and OE are controlled from DSI.
Output is controlled from DSI, but OE is firmware-controlled.
Pin is a CSD sense pin
2
3
4
5
Pin is a CSD shield pin
6
Pin is connected to AMUXA
7
Pin is connected to AMUXB
8
Pin-specific Active function #0
9
Pin-specific Active function #1
10
11
12
13
14
15
Pin-specific Active function #2
Reserved
Pin is an LCD common pin
Pin is an LCD segment pin
Pin-specific Deep-Sleep function #0
Pin-specific Deep-Sleep function #1
Datasheet
23
002-23053 Rev. *B
2023-03-29
The selection of peripheral function for different GPIO pins is given in Table 5.
Table 5
Port pin connections
Digital
Name
Analog
GPIO
Active #0
TCPWM0_P[3]
TCPWM0_N[3]
TCPWM1_P[3]
TCPWM1_N[3]
TCPWM1_P[0]
Active #1
Active #2
Deep Sleep #0
SCB1_I2C_SDA[1]
SCB1_I2C_SCL[1]
COMP0_OUT[0]
Deep Sleep #1
SCB1_SPI_MOSI[1]
SCB1_SPI_MISO[1]
SCB1_SPI_SS0[1]
SCB1_SPI_SCLK[1]
SCB0_SPI_MOSI[1]
P0.0
P0.1
P0.2
P0.3
P0.4
COMP0_INP
GPIO
GPIO
GPIO
GPIO
GPIO
SCB1_UART_RX[1]
SCB1_UART_TX[1]
SCB1_UART_RTS[1]
SCB1_UART_CTS[1]
SCB0_UART_RX[1]
–
–
–
–
COMP0_INN
–
–
COMP1_OUT[0]
COMP1_INP
EXT_CLK[0]/
ECO_OUT[0]
SCB0_I2C_SDA[1]
P0.5
P0.6
P0.7
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
P3.0
P3.1
P3.2
P3.3
COMP1_INN
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
TCPWM1_N[0]
TCPWM2_P[0]
TCPWM2_N[0]
TCPWM0_P[1]
TCPWM0_N[1]
TCPWM1_P[1]
TCPWM1_N[1]
TCPWM2_P[1]
TCPWM2_N[1]
TCPWM3_P[1]
TCPWM3_N[1]
–
SCB0_UART_TX[1]
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
SCB0_I2C_SCL[1]
SCB0_SPI_MISO[1]
–
SCB0_UART_RTS[1]
SWDIO[0]
SCB0_SPI_SS0[1]
–
SCB0_UART_CTS[1]
SWDCLK[0]
SCB0_SPI_SCLK[1]
CTBm1_OA0_INP
CTBm1_OA0_INN
CTBm1_OA0_OUT
CTBm1_OA1_OUT
CTBm1_OA1_INN
CTBm1_OA1_INP
CTBm1_OA0_INP
CTBm1_OA1_INP
CTBm0_OA0_INP
CTBm0_OA0_INN
CTBm0_OA0_OUT
CTBm0_OA1_OUT
CTBm0_OA1_INN
CTBm0_OA1_INP
CTBm0_OA0_INP
CTBm0_OA1_INP
SARMUX_0
–
COMP0_OUT[1]
WCO_OUT[2]
–
COMP1_OUT[1]
SCB1_SPI_SS1
–
–
SCB1_SPI_SS2
–
–
SCB1_SPI_SS3
SCB0_UART_RX[0]
SCB0_I2C_SDA[0]
SCB0_SPI_MOSI[1]
SCB0_UART_TX[0]
SCB0_I2C_SCL[0]
SCB0_SPI_MISO[1]
SCB0_UART_RTS[0]
–
SCB0_SPI_SS0[1]
SCB0_UART_CTS[0]
–
SCB0_SPI_SCLK[1]
–
–
SCB0_SPI_SS1
–
–
–
SCB0_SPI_SS2
–
–
WAKEUP
SCB0_SPI_SS3
–
–
–
–
–
–
WCO_OUT[1]
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
EXT_CLK[1]/ECO_OUT[1] –
TCPWM0_P[2]
TCPWM0_N[2]
TCPWM1_P[2]
TCPWM1_N[2]
SCB0_UART_RX[2]
SCB0_UART_TX[2]
SCB0_UART_RTS[2]
SCB0_UART_CTS[2]
–
–
–
–
SCB0_I2C_SDA[2]
SARMUX_1
SCB0_I2C_SCL[2]
SARMUX_2
–
–
SARMUX_3
Table 5
Port pin connections (continued)
Digital
Name
Analog
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
Active #0
Active #1
SCB1_UART_RX[2]
SCB1_UART_TX[2]
SCB1_UART_RTS[2]
SCB1_UART_CTS[2]
SCB1_UART_RTS[0]
SCB1_UART_CTS[0]
SCB1_UART_RX[0]
SCB1_UART_TX[0]
–
Active #2
Deep Sleep #0
Deep Sleep #1
P3.4
P3.5
P3.6
P3.7
P4.0
P4.1
P5.0
P5.1
SARMUX_4
SARMUX_5
SARMUX_6
SARMUX_7
CMOD
CTANK
–
TCPWM2_P[2]
TCPWM2_N[2]
TCPWM3_P[2]
TCPWM3_N[2]
TCPWM0_P[0]
TCPWM0_N[0]
TCPWM3_P[0]
TCPWM3_N[0]
–
–
–
–
–
–
–
SCB1_I2C_SDA[2]
–
–
–
SCB1_I2C_SCL[2]
–
–
WCO_OUT[0]
–
SCB1_SPI_MOSI[0]
SCB1_SPI_MISO[0]
SCB1_SPI_SS0[0]
SCB1_SPI_SCLK[0]
–
–
EXTPA_EN
SCB1_I2C_SDA[0]
–
EXT_CLK[2]/ECO_OUT[2] SCB1_I2C_SCL[0]
P6.0_XTAL32
O
–
–
–
P6.1_XTAL32I
–
GPIO
–
–
–
–
–
PSoC™ 4 MCU with AIROC™ Bluetooth® LE
Based on Arm® Cortex®-M0
Pinouts
The possible pin connections are shown for all analog and digital peripherals (except the radio, LCD, and CSD
blocks, which were shown in Table 1). A typical system application connection diagram is shown in Figure 6.
VDDA
C1
1.3
uF
C2
1.0 uF
C3
47 pF
C4
24 pF
1
U1
Y2
2
1
VDDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
42
41
40
39
38
37
36
35
34
33
32
31
30
29
32.768KHz
VDDD
XTAL32O/P6.0
XTAL32I/P6.1
XRES
P4.0
P4.1
P5.0
P5.1
VSS
VDDR
GANT1
ANT
P2.5
P2.4
P2.3
P2.2
P2.1
P2.0
VDDA
P1.7
P1.6
P1.5
P1.4
P1.3
P1.2
P1.1
ANTENNA
VDDA
PSoC™ 4XXX-BLE
56-QFN
VDDR
C6
GANT2
VDDR
C5
L1
VDDR
VDDR
Y1
24MHz
4
VDDD
2
Figure 6
System application connection diagram
Datasheet
26
002-23053 Rev. *B
2023-03-29
PSoC™ 4 MCU with AIROC™ Bluetooth® LE
Based on Arm® Cortex®-M0
Power
3
Power
The PSoC™ 4 CY8C42xx-BL MCU with AIROC™ Bluetooth® LE device can be supplied from batteries with a voltage
range of 1.9 V to 5.5 V by directly connecting to the digital supply (VDDD), analog supply (VDDA), and radio supply
(VDDR) pins. Internal LDOs in the device regulate the supply voltage to the required levels for different blocks.
The device has one regulator for the digital circuitry and separate regulators for radio circuitry for noise isolation.
Analog circuits run directly from the analog supply (VDDA) input. The device uses separate regulators for Deep
Sleep and Hibernate (lowered power supply and retention) modes to minimize the power consumption. The
radio stops working below 1.9 V, but the device continues to function down to 1.71 V without RF.
Bypass capacitors must be used from VDDx (x = A, D, or R) to ground. The typical practice for systems in this
frequency range is to use a capacitor in the 1-µF range in parallel with a smaller capacitor (for example, 0.1 µF).
Note that these are simply rules of thumb and that, for critical applications, the PCB layout, lead inductance, and
the bypass capacitor parasitic should be simulated to design and obtain optimal bypassing.
Table 6
Power supply
Power supply
Bypass capacitors
VDDD
VDDA
VDDR
VCCD
The internal bandgap may be bypassed with a 1-µF to 10-µF.
0.1-µF ceramic at each pin plus bulk capacitor 1-µF to 10-µF.
0.1-µF ceramic at each pin plus bulk capacitor 1-µF to 10-µF.
1.3-µF ceramic capacitor at the VCCD pin.
VREF (optional)
The internal bandgap may be bypassed with a 1-µF to 10-µF capacitor.
Datasheet
27
002-23053 Rev. *B
2023-03-29
PSoC™ 4 MCU with AIROC™ Bluetooth® LE
Based on Arm® Cortex®-M0
Development support
4
Development support
The PSoC™ 4 CY8C42xx-BL MCU with AIROC™ Bluetooth® LE family has a rich set of documentation, development
tools, and online resources to assist you during your development process. See PSoC™ 4 MCU with AIROC™
Bluetooth® LE to find out more.
4.1
Documentation
A suite of documentation supports the PSoC™ 4 CY8C42xx-BL MCU with AIROC™ Bluetooth® LE family to ensure
that you can find answers to your questions quickly. This section contains a list of some of the key documents.
Software user guide: A step-by-step guide for using PSoC™ Creator. The software user guide shows you how the
PSoC™ Creator build process works in detail, how to use source control with PSoC™ Creator, and much more.
Component datasheets: The flexibility of PSoC™ allows the creation of new peripherals (Components) long after
the device has gone into production. Component datasheets provide all of the information needed to select and
use a particular Component, including a functional description, API documentation, example code, and AC/DC
specifications.
Application notes: PSoC™ application notes discuss a particular application of PSoC™ in depth; examples
include creating standard and custom Bluetooth® LE profiles. Application notes often include example projects
in addition to the application note document.
Technical reference manual (TRM): The TRM contains all the technical detail you need to use a PSoC™ device,
including a complete description of all PSoC™ registers. The TRM is available in the Documentation section at
PSoC™ 4 MCU.
4.2
Online
In addition to print documentation, the PSoC™ forums connect you with fellow PSoC™ users and experts in
PSoC™ from around the world, 24 hours a day, 7 days a week.
4.3
Tools
With industry standard cores, programming, and debugging interfaces, the PSoC™ 4 CY8C42xx-BL MCU with
AIROC™ Bluetooth® LE family is part of a development tool ecosystem. See the PSoC™ Creator for the latest
information on the revolutionary, easy to use PSoC™ Creator IDE, supported third party compilers, programmers,
debuggers, and development kits.
Datasheet
28
002-23053 Rev. *B
2023-03-29
PSoC™ 4 MCU with AIROC™ Bluetooth® LE
Based on Arm® Cortex®-M0
Electrical specifications
5
Electrical specifications
5.1
Table 7
Absolute maximum ratings
Absolute maximum ratings[1]
Details/
Spec ID#
Parameter
VDDD_ABS
Description
Min
–0.5
–0.5
Typ
–
Max
6
Unit
conditions
Analog, digital, or radio supply
relative to VSS (VSSD = VSSA
Direct digital core voltage
input relative to VSSD
SID1
SID2
V
V
V
Absolute max
Absolute max
Absolute max
)
VCCD_ABS
–
1.95
VDD
+0.5
25
SID3
SID4
VGPIO_ABS
IGPIO_ABS
GPIO voltage
–0.5
–25
–
–
Maximum current per GPIO
mA Absolute max
Absolute max,
mA current injected
per pin
GPIO injection current, Max for
VIH > VDDD, and Min for VIL < VSS
SID5
IGPIO_injection
ESD_HBM
–0.5
–
–
0.5
Electrostatic discharge human
body model
Electrostatic discharge
charged device model
BID57
BID58
2200
–
V
–
ESD_CDM
LU
500
–
–
–
V
–
–
BID61
Pin current for latch-up
–200
200
mA
Note
1. Usage above the absolute maximum conditions listed in Table 7 may cause permanent damage to the de-
vice. Exposure to absolute maximum conditions for extended periods of time may affect device reliability.
The maximum storage temperature is 150°C in compliance with JEDEC Standard JESD22-A103, High Tem-
perature Storage Life. When used below absolute maximum conditions but above normal operating condi-
tions, the device may not operate to specification.
Datasheet
29
002-23053 Rev. *B
2023-03-29
PSoC™ 4 MCU with AIROC™ Bluetooth® LE
Based on Arm® Cortex®-M0
Electrical specifications
5.2
Device-level specifications
All specifications are valid for –40°C TA 85°C and TJ 100°C, except where noted. Specifications are valid for
1.71 V to 5.5 V, except where noted.
Table 8
DC specifications
Details/
Spec ID# Parameter
Description
Min
Typ
Max
Unit
conditions
Power supply input voltage (VDDA
With regulator
enabled
SID6
SID7
VDD
VDD
1.8
–
5.5
V
= VDDD = VDD
)
Internally
unregulated
Supply
Power supply input voltage
unregulated (VDDA = VDDD = VDD
1.71
1.9
1.8
1.89
V
)
SID8
SID8A
VDDR
VDDR
Radio supply voltage (Radio ON)
Radio supply voltage (Radio OFF) 1.71
–
–
5.5
5.5
V
V
–
–
Digital regulator output voltage
SID9
VCCD
–
1.8
1.3
–
V
–
(for core logic)
Digital regulator output bypass
capacitor
X5R ceramic or
better
SID10
CVCCD
1
1.6
µF
Active mode, VDD = 1.71 V to 5.5 V
T = 25°C,
SID13
SID14
SID15
SID16
SID17
SID18
SID19
SID20
SID21
SID22
IDD3
IDD4
IDD5
IDD6
IDD7
IDD8
IDD9
IDD10
IDD11
IDD12
Execute from flash; CPU at 3 MHz
Execute from flash; CPU at 3 MHz
Execute from flash; CPU at 6 MHz
Execute from flash; CPU at 6 MHz
Execute from flash; CPU at 12 MHz
Execute from flash; CPU at 12 MHz
Execute from flash; CPU at 24 MHz
Execute from flash; CPU at 24 MHz
Execute from flash; CPU at 48 MHz
Execute from flash; CPU at 48 MHz
–
–
–
–
–
–
–
–
–
–
2.1
–
–
–
–
–
–
–
–
–
–
–
mA
VDD = 3.3 V
mA T = –40°C to 85°C
T = 25°C,
VDD = 3.3 V
mA T = –40°C to 85°C
T = 25°C,
VDD = 3.3 V
mA T = –40°C to 85°C
T = 25°C,
VDD = 3.3 V
mA T = –40°C to 85°C
T = 25°C,
VDD = 3.3 V
mA T = –40°C to 85°C
2.5
–
mA
4
mA
–
7.1
–
mA
13.4
–
mA
Sleep mode, VDD = 1.8 to 5.5 V
SID23 IDD13 IMO on
Sleep mode, VDD and VDDR = 1.9 to 5.5 V
SID24 IDD14 ECO on
Deep Sleep mode, VDD = 1.8 to 3.6 V
T = 25°C,
mA VDD = 3.3 V,
SYSCLK = 3 MHz
–
–
–
–
–
–
T = 25°C,
mA VDD = 3.3 V,
SYSCLK = 3 MHz
T = 25°C,
µA
SID25
SID26
IDD15
IDD16
WDT with WCO on
WDT with WCO on
–
–
1.5
–
–
–
VDD = 3.3 V
µA
T = –40°C to 85°C
Datasheet
30
002-23053 Rev. *B
2023-03-29
PSoC™ 4 MCU with AIROC™ Bluetooth® LE
Based on Arm® Cortex®-M0
Electrical specifications
Table 8
Spec ID# Parameter
Deep Sleep mode, VDD = 3.6 to 5.5 V
DC specifications (continued)
Details/
Description
Min
Typ
Max
Unit
conditions
T = 25°C,
SID27
SID28
IDD17
IDD18
WDT with WCO on
WDT with WCO on
–
–
–
–
–
–
µA
µA
VDD = 5 V
T = –40°C to 85°C
Deep Sleep mode, VDD = 1.71 to 1.89 V (Regulator bypassed)
SID29
SID30
IDD19
IDD20
WDT with WCO on
WDT with WCO on
–
–
–
–
–
–
µA
µA
T = 25°C
T = –40°C to 85°C
Deep Sleep mode, VDD = 1.8 to 3.6 V
T = 25°C,
SID31
SID32
IDD21
IDD22
Opamp on
Opamp on
–
–
–
–
–
–
µA
µA
VDD = 3.3 V
T = –40°C to 85°C
Deep Sleep mode, VDD = 3.6 to 5.5 V
T = 25°C,
VDD = 5 V
T = –40°C to 85°C
SID33
SID34
IDD23
IDD24
Opamp on
Opamp on
–
–
–
–
–
–
µA
µA
Deep Sleep mode, VDD = 1.71 to 1.89 V (Regulator bypassed)
SID35
SID36
IDD25
IDD26
Opamp on
Opamp on
–
–
–
–
–
–
µA
µA
T = 25°C
T = –40°C to 85°C
Hibernate mode, VDD = 1.8 to 3.6 V
T = 25°C,
SID37
SID38
IDD27
IDD28
GPIO and reset active
–
–
150
–
–
–
nA
nA
VDD = 3.3V
GPIO and reset active
T = –40°C to 85°C
Hibernate mode, VDD = 3.6 to 5.5 V
T = 25°C,
VDD = 5 V
T = –40°C to 85°C
SID39
SID40
IDD29
IDD30
GPIO and reset active
–
–
–
–
–
–
nA
nA
GPIO and reset active
Hibernate mode, VDD = 1.71 to 1.89 V (Regulator bypassed)
SID41
SID42
IDD31
IDD32
GPIO and reset active
GPIO and reset active
–
–
–
–
–
–
nA
nA
T = 25°C
T = –40°C to 85°C
Stop mode, VDD = 1.8 to 3.6 V
T = 25°C,
VDD = 3.3 V
SID43
IDD33
Stop mode current (VDD
)
–
20
–
nA
T = 25°C,
SID44
SID45
IDD34
IDD35
Stop mode current (VDDR
)
)
–
–
40
–
–-
–
nA
nA
VDDR = 3.3 V
Stop mode current (VDD
)
T = –40°C to 85°C
T = –40°C to
85°C,
VDDR = 1.9 V to
3.6 V
SID46
IDD36
Stop mode current (VDDR
–
–
–
nA
Datasheet
31
002-23053 Rev. *B
2023-03-29
PSoC™ 4 MCU with AIROC™ Bluetooth® LE
Based on Arm® Cortex®-M0
Electrical specifications
Table 8
DC specifications (continued)
Details/
Spec ID# Parameter
Description
Min
Typ
Max
Unit
conditions
Stop mode, VDD = 3.6 to 5.5 V
T = 25°C,
SID47
SID48
IDD37
Stop mode current (VDD
)
–
–
–
–
–
–
nA
nA
VDD = 5 V
T = 25°C,
IDD38
IDD39
IDD40
Stop mode current (VDDR
Stop mode current (VDD
Stop mode current (VDDR
)
VDDR = 5 V
SID49
SID50
)
–
–
–
–
–
–
nA
nA
T = –40°C to 85°C
T = –40°C to 85°C
)
Stop mode, VDD = 1.71 to 1.89 V (Regulator bypassed)
SID51
SID52
IDD41
IDD42
Stop mode current (VDD
Stop mode current (VDD
)
)
–
–
–
–
–
–
nA
nA
T = 25°C
T = –40°C to 85°C
Table 9
AC specifications
Details/
Spec ID# Parameter
Description
Min
DC
–
Typ
Max
Unit
conditions
SID53
SID54
FCPU
CPU frequency
–
0
48
–
MHz 1.71 V VDD 5.5 V
Guaranteed by
characterization
TSLEEP
Wakeup from Sleep mode
µs
24-MHz IMO.
Wakeup from Deep Sleep
mode
SID55
TDEEPSLEEP
–
–
25
µs
Guaranteed by
characterization.
Wakeup from Hibernate
mode
Guaranteed by
SID56
SID57
THIBERNATE
TSTOP
–
–
–
–
0.7
2.2
ms
ms
characterization
Guaranteed by
characterization
Wakeup from Stop mode
Datasheet
32
002-23053 Rev. *B
2023-03-29
PSoC™ 4 MCU with AIROC™ Bluetooth® LE
Based on Arm® Cortex®-M0
Electrical specifications
5.2.1
GPIO
Table 10
GPIO DC specifications
Details/
Spec ID# Parameter
Description
Min
0.7 × VDD
–
Typ
–
Max
Unit
conditions
SID58
SID59
VIH
VIL
Input voltage HIGH threshold
Input voltage LOW threshold
–
V
V
CMOS input
0.3
× VDD
–
CMOS input
SID60
SID61
SID62
SID63
VIH
VIL
VIH
VIL
LVTTL input, VDD < 2.7 V
LVTTL input, VDD < 2.7 V
LVTTL input, VDD >= 2.7 V
LVTTL input, VDD >= 2.7 V
0.7 × VDD
–
–
–
–
-
V
V
V
V
–
–
–
–
–
2.0
–
0.3× VDD
-
0.8
Ioh = 4-mA at
3.3-V VDD
Ioh = 1-mA at
1.8-V VDD
Iol = 8-mA at
3.3-V VDD
Iol = 4-mA at
1.8-V VDD
SID64
SID65
SID66
SID67
SID68
VOH
VOH
VOL
VOL
VOL
Output voltage HIGH level
Output voltage HIGH level
Output voltage LOW level
Output voltage LOW level
Output voltage LOW level
VDD –0.6
–
–
–
–
–
–
V
V
V
V
V
VDD –0.5
–
–
–
–
0.6
0.6
0.4
Iol = 3-mA at
3.3-V VDD
SID69
SID70
Rpullup
Rpulldown
Pull-up resistor
Pull-down resistor
3.5
3.5
5.6
5.6
8.5
8.5
kΩ
kΩ
–
–
Input leakage current (absolute
value)
Input leakage on CTBm input
pins
Input capacitance
Input hysteresis LVTTL
Input hysteresis CMOS
25°C,
SID71
SID72
IIL
–
–
–
–
2
nA
nA
VDD = 3.3 V
IIL_CTBM
4
7
–
–
SID73
SID74
SID75
CIN
Vhysttl
Vhyscmos
–
25
–
40
–
pF
mV
mV
V
DD > 2.7 V
–
0.05 × VDD
–
Current through protection
diode to VDD/VSS
Maximum total source or sink
chip current
SID76
Idiode
–
–
–
–
100
µA
–
–
SID77
ITOT_GPIO
200
mA
Note
2. VIH must not exceed VDDD + 0.2 V.
Datasheet
33
002-23053 Rev. *B
2023-03-29
PSoC™ 4 MCU with AIROC™ Bluetooth® LE
Based on Arm® Cortex®-M0
Electrical specifications
Table 11
GPIO AC specifications
Details/
Spec ID# Parameter
Description
Min
2
Typ Max Unit
conditions
Rise time in Fast-Strong
mode
Fall time in Fast-Strong
mode
Rise time in Slow-Strong
mode
Fall time in Slow-Strong
mode
GPIO Fout; 3.3 V VDD
5.5 V. Fast-Strong mode
GPIO Fout; 1.7 VVDD 3.3 V.
Fast-Strong mode
3.3-V VDDD
,
SID78
SID79
SID80
SID81
SID82
SID83
SID84
SID85
TRISEF
–
–
–
–
–
–
–
–
12
12
60
60
33
ns
ns
–
CLOAD = 25-pF
3.3-V VDDD
,
TFALLF
2
CLOAD = 25-pF
3.3-V VDDD
,
TRISES
10
10
–
CLOAD = 25-pF
3.3-V VDDD,
CLOAD = 25-pF
90/10%, 25-pF load,
60/40 duty cycle
90/10%, 25-pF load,
60/40 duty cycle
90/10%, 25-pF load,
60/40 duty cycle
90/10%, 25-pF load,
60/40 duty cycle
TFALLS
–
FGPIOUT1
FGPIOUT2
FGPIOUT3
FGPIOUT4
MHz
–
16.7 MHz
GPIO Fout; 3.3 V VDD
5.5 V. Slow-Strong mode
GPIO Fout; 1.7 V VDD
3.3 V. Slow-Strong mode
–
7
MHz
MHz
–
3.5
GPIO input operating
frequency;
1.71 V VDD 5.5 V
SID86
FGPIOIN
–
–
48
MHz 90/10% VIO
Table 12
OVT GPIO DC specifications (P5_0 and P5_1 Only)
Details/
Spec ID# Parameter
Description
Min
–
Typ Max Unit
conditions
Input leakage current (absolute
value), VIH > VDD
25°C,
VDD = 0 V, VIH= 3.0 V
IOL = 20-mA, VDD
2.9-V
SID71A
SID66A
IIL
–
–
10
µA
V
>
VOL
Output voltage LOW level
–
0.4
Table 13
OVT GPIO AC specifications (P5_0 and P5_1 only)
Details/
Spec ID# Parameter
Description
Min
1.5
1.5
10
Typ
–
Max
12
Unit
conditions
Output rise time in Fast-Strong
mode
Output fall time in Fast-Strong
mode
Output rise time in Slow-Strong
mode
Output fall time in Slow-Strong
mode
25-pF load, 10%–
90%, VDD=3.3-V
25-pF load, 10%–
90%, VDD=3.3-V
25-pF load, 10%–
90%, VDD=3.3-V
25-pF load, 10%–
90%, VDD=3.3-V
SID78A
SID79A
SID80A
SID81A
TRISE_OVFS
TFALL_OVFS
TRISSS
ns
ns
ns
ns
–
12
–
60
TFALLSS
10
–
60
Datasheet
34
002-23053 Rev. *B
2023-03-29
PSoC™ 4 MCU with AIROC™ Bluetooth® LE
Based on Arm® Cortex®-M0
Electrical specifications
Table 13
OVT GPIO AC specifications (P5_0 and P5_1 only) (continued)
Details/
Spec ID# Parameter
Description
Min
Typ
Max
Unit
conditions
90/10%, 25-pF
GPIO FOUT; 3.3 V ≤ VDD ≤ 5.5 V
SID82A
SID83A
FGPIOUT1
–
–
24
MHz load, 60/40 duty
cycle
Fast-Strong mode
90/10%, 25-pF
MHz load, 60/40 duty
cycle
GPIO FOUT; 1.71 V ≤ VDD ≤ 3.3 V
Fast-Strong mode
FGPIOUT2
–
–
16
5.2.2
XRES
Table 14
XRES DC specifications
Details/
Unit
Spec ID# Parameter
Description
Min
Typ
Max
conditions
0.7 ×
VDDD
SID87
VIH
Input voltage HIGH threshold
–
–
V
CMOS input
SID88
SID89
SID90
SID91
VIL
Rpullup
CIN
Input voltage LOW threshold
Pull-up resistor
Input capacitance
–
3.5
–
–
5.6
3
0.3 × VDDD
V
CMOS input
8.5
–
–
kΩ
pF
mV
–
–
–
VHYSXRES
Input voltage hysteresis
–
100
Current through protection
diode to VDDD/VSS
SID92
IDIODE
–
–
100
µA
–
Table 15
XRES AC specifications
Description
TRESETWIDTH Reset pulse width
Spec ID# Parameter
SID93
Min
Typ
Max
Unit Details/conditions
1
–
–
µs
–
Datasheet
35
002-23053 Rev. *B
2023-03-29
PSoC™ 4 MCU with AIROC™ Bluetooth® LE
Based on Arm® Cortex®-M0
Electrical specifications
5.3
Analog peripherals
5.3.1
Opamp
Table 16
Opamp specifications
Details/
Spec ID# Parameter
Description
Min
Typ
Max
Unit
conditions
IDD (Opamp block current. VDD = 1.8 V. No load)
SID94
SID95
SID96
IDD_HI
IDD_MED
IDD_LOW
Power = high
Power = medium
Power = low
–
–
–
1000
500
250
1850
950
350
µA
µA
µA
–
–
–
GBW (Load = 20 pF, 0.1 mA. VDDA = 2.7 V)
SID97
SID98
SID99
GBW_HI
GBW_MED
GBW_LO
Power = high
Power = medium
Power = low
6
4
–
–
–
1
–
–
–
MHz
MHz
MHz
–
–
–
IOUT_MAX (VDDA 2.7 V, 500 mV from rail)
SID100
SID101
SID102
IOUT_MAX_HI
IOUT_MAX_MID Power = medium
IOUT_MAX_LO Power = low
Power = high
10
10
–
–
–
5
–
–
–
mA
mA
mA
–
–
–
IOUT (VDDA = 1.71 V, 500 mV from rail)
SID103
SID104
SID105
SID106
SID107
IOUT_MAX_HI
IOUT_MAX_MID Power = medium
IOUT_MAX_LO Power = low
VIN
VCM
Power = high
4
4
–
–
–
2
–
–
–
–
–
mA
mA
mA
V
–
–
–
–
–
Charge pump on, VDDA 2.7 V
Charge pump on, VDDA 2.7 V
–0.05
–0.05
VDDA – 0.2
VDDA – 0.2
V
V
OUT (VDDA 2.7 V)
SID108
SID109
SID110
SID111
SID112
VOUT_1
VOUT_2
VOUT_3
VOUT_4
VOS_TR
Power = high, ILOAD=10 mA
Power = high, ILOAD=1 mA
Power = medium, ILOAD=1 mA
Power = low, ILOAD=0.1 mA
Offset voltage, trimmed
0.5
0.2
0.2
0.2
1
–
–
–
–
±0.5
VDDA – 0.5
VDDA – 0.2
VDDA – 0.2
VDDA – 0.2
1
V
V
V
V
mV
–
–
–
–
High mode
Medium
mode
SID113
VOS_TR
Offset voltage, trimmed
–
±1
–
mV
SID114
SID115
VOS_TR
VOS_DR_TR
Offset voltage, trimmed
Offset voltage drift, trimmed
–
–10
±2
±3
–
10
mV
µV/C
Low mode
High mode
Medium
mode
SID116
VOS_DR_TR
Offset voltage drift, trimmed
–
±10
–
µV/C
SID117
SID118
SID119
VOS_DR_TR
CMRR
PSRR
Offset voltage drift, trimmed
DC
At 1 kHz, 100-mV ripple
–
70
70
±10
80
85
–
–
–
µV/C
dB
dB
Low mode
V
DDD = 3.6-V
VDDD = 3.6-V
Datasheet
36
002-23053 Rev. *B
2023-03-29
PSoC™ 4 MCU with AIROC™ Bluetooth® LE
Based on Arm® Cortex®-M0
Electrical specifications
Table 16
Opamp specifications (continued)
Details/
Spec ID# Parameter
Noise
Description
Min
Typ
Max
Unit
conditions
Input referred, 1 Hz–1 GHz,
power = high
Input referred, 1-kHz, power =
high
SID120
SID121
SID122
SID123
SID124
SID125
SID126
VN1
–
–
–
–
–
6
–
94
72
28
15
–
–
–
µVrms
nV/rtHz
nV/rtHz
nV/rtHz
pF
–
–
–
–
–
–
–
VN2
Input referred, 10-kHz, power =
high
Input referred, 100-kHz, power =
high
Stable up to maximum load.
Performance specs at 50 pF
VN3
–
VN4
–
CLOAD
Slew_rate
T_op_wake
125
–
Cload = 50 pF, Power = High,
–
V/µsec
µsec
VDDA 2.7 V
From disable to enable, no
external RC dominating
300
–
Comp_mode (Comparator mode; 50-mV drive, TRISE = TFALL (approx.)
SID127
SID128
SID129
SID130
TPD1
TPD2
TPD3
Vhyst_op
Response time; power = high
Response time; power = medium
Response time; power = low
Hysteresis
–
–
–
–
150
400
2000
10
–
–
–
–
nsec
nsec
nsec
mV
–
–
–
–
Deep Sleep (Deep Sleep mode operation is only guaranteed for VDDA > 2.5 V)
SID131
SID132
SID133
SID134
SID135
SID136
GBW_DS
IDD_DS
Vos_DS
Vos_dr_DS
Vout_DS
Vcm_DS
Gain bandwidth product
Current
Offset voltage
Offset voltage drift
Output voltage
Common mode voltage
–
–
–
–
0.2
0.2
50
15
5
20
–
–
–
–
–
kHz
µA
mV
µV/°C
V
–
–
–
–
–
–
V
V
DD–0.2
DD–1.8
–
V
Table 17
Comparator DC specifications[3]
Details/
Spec ID# Parameter
Description
Min Typ Max
Unit
conditions
SID140 VOFFSET1
SID141 VOFFSET2
Input offset voltage, Factory trim
Input offset voltage, Custom trim
–
–
–
–
±10
±6
mV
mV
–
–
VDDD ≥ 2.6 V for
Temp < 0°C,
Input offset voltage,
SID141A VOFFSET3
–
–
±12
10
–
mV
mV
ultra-low-power mode
VDDD ≥ 1.8 V for
Temp > 0°C
Hysteresis when enabled. Common
Mode voltage range from 0 to VDD –1
SID142 VHYST
35
–
Note
3. ULP LCOMP operating conditions:
- VDDD 2.6 V-5.5 V for datasheet temp range < 0°C
- VDDD 1.8 V-5.5 V for datasheet temp range ≥ 0°C
Datasheet
37
002-23053 Rev. *B
2023-03-29
PSoC™ 4 MCU with AIROC™ Bluetooth® LE
Based on Arm® Cortex®-M0
Electrical specifications
Table 17
Comparator DC specifications[3] (continued)
Details/
Spec ID# Parameter
SID143 VICM1
Description
Min Typ Max
Unit
conditions
Input common mode voltage in
normal mode
Input common mode voltage in low
power mode
VDDD
0.1
–
0
0
–
–
V
V
Modes 1 and 2
–
SID144 VICM2
VDDD
VDDD ≥ 2.6 V for
Temp < 0°C,
VDDD ≥ 1.8 V for
Temp > 0°C
Input common mode voltage in ultra
low power mode
VDDD
–
SID145 VICM3
0
–
V
1.15
SID146 CMRR
SID147 CMRR
SID148 ICMP1
SID149 ICMP2
Common mode rejection ratio
Common mode rejection ratio
Block current, normal mode
Block current, low power mode
50
42
–
–
–
–
–
–
–
400
100
dB
dB
µA
µA
V
V
DDD ≥ 2.7 V
DDD ≤ 2.7 V
–
–
–
VDDD ≥ 2.6 V for
Temp < 0°C,
Block current in ultra low-power
mode
SID150 ICMP3
–
6
–
–
–
µA
VDDD ≥ 1.8 V for
Temp > 0°C
SID151 ZCMP
DC input impedance of comparator
35
MΩ
–
Note
3. ULP LCOMP operating conditions:
- VDDD 2.6 V-5.5 V for datasheet temp range < 0°C
- VDDD 1.8 V-5.5 V for datasheet temp range ≥ 0°C
Table 18
Comparator AC specifications[3]
Details/
Spec ID# Parameter
SID152 TRESP1
Description
Min
–
Typ
38
Max
Unit
conditions
Response time, normal mode,
50-mV overdrive
Response time, low power mode,
50-mV overdrive
50-mV
overdrive
50-mV
overdrive
–
–
ns
ns
SID153 TRESP2
–
70
200-mV
overdrive.VDDD
≥ 2.6 V for
Temp < 0°C,
VDDD ≥ 1.8 V for
Temp > 0°C
Response time, ultra-low-power
mode, 50-mV overdrive
SID154 TRESP3
–
2.3
–
µs
5.3.2
Temperature sensor
Table 19
Temperature sensor specifications
Details/
Spec ID# Parameter
Description
Min
Typ
Max
Unit
conditions
SID155
TSENSACC
Temperature sensor accuracy
–5
±1
5
°C –40 to +85°C
Datasheet
38
002-23053 Rev. *B
2023-03-29
PSoC™ 4 MCU with AIROC™ Bluetooth® LE
Based on Arm® Cortex®-M0
Electrical specifications
5.3.3
SAR ADC
Table 20
SAR ADC DC specifications
Details/
Spec ID# Parameter
Description
Resolution
Number of channels -
single-ended
Min Typ
Max
12
Unit
bits
–
conditions
SID156
SID157
A_RES
–
–
–
–
–
A_CHNIS_S
16
8 full-speed
Diff inputs use
neighboring I/O
Yes
With external
reference.
SID158
SID159
SID160
A-CHNKS_D Number of channels - differential
A-MONO Monotonicity
–
–
–
–
–
–
8
–
–
–
A_GAINERR Gain error
±0.1
%
Measured with 1-V
VREF
SID161
SID162
SID163
A_OFFSET Input offset voltage
–
–
–
–
–
2
1
mV
mA
V
A_ISAR
A_VINS
Current consumption
Input voltage range -
single-ended
–
VSS
VDDA
–
SID164
SID165
SID166
A_VIND
A_INRES
A_INCAP
Input voltage range - differential
Input resistance
Input capacitance
VSS
–
–
–
–
–
VDDA
2.2
10
V
kΩ
pF
–
–
–
Trimmed internal reference to
SAR
Percentage of Vbg
(1.024-V)
SID312
VREFSAR
–1
–
1
%
Table 21
SAR ADC AC specifications
Details/
Spec ID# Parameter
Description
Min
Typ
Max
Unit
conditions
Measured at 1-V
reference
SID167
A_psrr
Power supply rejection ratio
70
–
–
dB
SID168
SID169
A_cmrr
A_samp
Common mode rejection ratio
Sample rate
66
–
–
–
–
1
dB
Msps
–
SAR operating speed without
external ref. bypass
Signal-to-noise ratio (SNR)
SID313
SID170
SID171
Fsarintref
A_snr
–
65
–
–
–
–
100
–
A_samp/
2
Ksps 12-bit resolution
dB Fin = 10 kHz
A_bw
Input bandwidth without aliasing
kHz
–
Integral non linearity. VDD = 1.71 to
5.5 V, 1 Msps
Integral non linearity. VDDD = 1.71
to 3.6 V, 1 Msps
Integral non linearity. VDD = 1.71 to
5.5 V, 500 Ksps
SID172
SID173
SID174
SID175
SID176
A_inl
–1.7
–1.5
–1.5
–1
–
–
–
–
–
2
LSB Vref = 1 V to VDD
Vref = 1.71 V to
A_INL
A_INL
A_dnl
A_DNL
1.7
1.7
2.2
2
LSB
VDD
LSB Vref = 1 V to VDD
LSB Vref = 1 V to VDD
Differential non linearity. VDD
1.71 to 5.5 V, 1 Msps
=
Differential non linearity. VDD
1.71 to 3.6 V, 1 Msps
=
Vref = 1.71 V to
–1
LSB
VDD
Datasheet
39
002-23053 Rev. *B
2023-03-29
PSoC™ 4 MCU with AIROC™ Bluetooth® LE
Based on Arm® Cortex®-M0
Electrical specifications
Table 21
SAR ADC AC specifications (continued)
Details/
Spec ID# Parameter
Description
Min
Typ
Max
Unit
conditions
Differential non linearity. VDD
1.71 to 5.5 V, 500 Ksps
Total harmonic distortion
=
SID177
SID178
A_DNL
A_thd
–1
–
–
–
2.2
LSB Vref = 1 V to VDD
dB Fin = 10 kHz
–65
5.3.4
CSD
Table 22
CSD block specifications
Details/
Spec ID# Parameter
Description
Min
Typ
Max
Unit
conditions
SID179
SID180
SID181
SID182
SID183
SID184
VCSD
Voltage range of operation
DNL for 8-bit resolution
INL for 8-bit resolution
DNL for 7-bit resolution
INL for 7-bit resolution
1.71
–1
–3
–1
–3
5
–
–
–
–
–
–
5.5
1
3
1
3
V
–
–
–
–
–
IDAC1
IDAC1
IDAC2
IDAC2
SNR
LSB
LSB
LSB
LSB
Ratio of counts of finger to
noise
–
Ratio Capacitance range
of 9 to 35 pF, 0.1 pF
sensitivity. Radio is
not operating
during the scan
SID185
SID186
SID187
SID188
IDAC1_CRT1 Output current of IDAC1 (8 bits)
in High range
IDAC1_CRT2 Output current of IDAC1 (8 bits)
in Low range
IDAC2_CRT1 Output current of IDAC2 (7 bits)
in High range
IDAC2_CRT2 Output current of IDAC2 (7 bits)
in Low range
–
–
–
–
612
306
305
153
–
–
–
–
µA
µA
µA
µA
–
–
–
–
Datasheet
40
002-23053 Rev. *B
2023-03-29
PSoC™ 4 MCU with AIROC™ Bluetooth® LE
Based on Arm® Cortex®-M0
Electrical specifications
5.4
Digital peripherals
5.4.1
Timer
Table 23
Timer DC specifications
Details/
Spec ID Parameter
Description
Min
–
Typ
–
Max Unit
conditions
Block current consumption at
3 MHz
Block current consumption at
12 MHz
Block current consumption at
48 MHz
SID189
SID190
SID191
ITIM1
ITIM2
ITIM3
50
µA 16-bit timer
µA 16-bit timer
–
–
175
712
–
–
µA 16-bit timer
Table 24
Timer AC specifications
Details/
Spec ID Parameter
SID192 TTIMFREQ
SID193 TCAPWINT
Description
Operating frequency
Min
Typ
–
Max Unit
conditions
FCLK
2 ×
TCLK
48
–
MHz
ns
–
Capture pulse width (internal)
–
–
2 ×
SID194 TCAPWEXT
SID195 TTIMRES
SID196 TTENWIDINT
Capture pulse width (external)
Timer resolution
–
–
–
–
–
–
ns
ns
ns
–
–
–
TCLK
TCLK
2 ×
TCLK
Enable pulse width (internal)
2 ×
SID197 TTENWIDEXT
Enable pulse width (external)
–
–
–
–
–
–
ns
ns
ns
–
–
–
TCLK
2 ×
TCLK
2 ×
TCLK
SID198 TTIMRESWINT Reset pulse width (internal)
SID199 TTIMRESEXT
Reset pulse width (external)
Datasheet
41
002-23053 Rev. *B
2023-03-29
PSoC™ 4 MCU with AIROC™ Bluetooth® LE
Based on Arm® Cortex®-M0
Electrical specifications
5.4.2
Counter
Table 25
Counter DC specifications
Spec ID Parameter
Description
Min
Typ Max Unit Details/conditions
Block current consumption at
3 MHz
Block current consumption at
12 MHz
Block current consumption at
48 MHz
SID200
SID201
SID202
ICTR1
ICTR2
ICTR3
–
–
–
–
50
µA 16-bit counter
µA 16-bit counter
µA 16-bit counter
–
–
175
712
Table 26
Counter AC specifications
Spec ID Parameter
Description
Operating frequency
Min
FCLK
Typ
–
–
–
–
Max Unit Details/conditions
SID203
SID204
SID205
SID206
SID207
SID208
TCTRFREQ
48
–
MHz
ns
–
–
–
–
–
–
TCTRPWINT Capture pulse width (internal) 2 × TCLK
TCTRPWEXT Capture pulse width (external) 2 × TCLK
TCTRES
TCENWIDINT Enable pulse width (internal)
TCENWIDEXT Enable pulse width (external)
–
ns
Counter Resolution
TCLK
2 × TCLK
2 × TCLK
–
ns
–
–
–
ns
–
ns
TCTRRE-
SWINT
SID209
SID210
Reset pulse width (internal)
2 × TCLK
2 × TCLK
–
–
–
–
ns
ns
–
–
TCTRRE-
SWEXT
Reset pulse width (external)
Datasheet
42
002-23053 Rev. *B
2023-03-29
PSoC™ 4 MCU with AIROC™ Bluetooth® LE
Based on Arm® Cortex®-M0
Electrical specifications
5.4.3
Pulse width modulation (PWM)
Table 27
PWM DC specifications
Details/
Spec ID Parameter
Description
Min
–
Typ Max Unit
conditions
Block current consumption at
3 MHz
Block current consumption at
12 MHz
Block current consumption at
48 MHz
SID211
SID212
SID213
IPWM1
IPWM2
IPWM3
–
–
–
50
µA 16-bit PWM
–
175
741
µA 16-bit PWM
µA 16-bit PWM
–
Table 28
Spec ID
PWM AC specifications
Details/
Parameter
Description
Min
Typ
Max Unit
conditions
SID214
SID215
SID216
SID217
SID218
SID219
SID220
SID221
SID222
TPWMFREQ
TPWMPWINT
TPWMEXT
TPWMKILLINT Kill pulse width (internal)
TPWMKILLEXT Kill pulse width (external)
TPWMEINT
TPWMENEXT
TPWMRESWINT Reset pulse width (internal)
TPWMRESWEXT Reset pulse width (external)
Operating frequency
Pulse width (internal)
Pulse width (external)
FCLK
–
–
–
–
–
–
–
–
–
48
–
–
–
–
–
–
–
–
MHz
ns
ns
ns
ns
ns
ns
ns
ns
–
–
–
–
–
–
–
–
–
2 × TCLK
2 × TCLK
2 × TCLK
2 × TCLK
2 × TCLK
2 × TCLK
2 × TCLK
2 × TCLK
Enable pulse width (internal)
Enable pulse width (external)
5.4.4
Table 29
I2C
Fixed I2C DC specifications
Details/
Spec ID
SID223
Parameter
II2C1
Description
Min
–
Typ
–
Max Unit
conditions
Block current consumption at
100 kHz
Block current consumption at
400 kHz
50
µA
µA
–
–
SID224
II2C2
–
–
155
Block current consumption at
1 Mbps
I2C enabled in Deep Sleep mode
SID225
SID226
II2C3
II2C4
–
–
–
–
390
1.4
µA
µA
–
–
Table 30
Fixed I2C AC specifications
Description
Details/
Spec ID Parameter
Min
Typ
Max Unit
Mbps
conditions
SID227
FI2C1
Bit rate
–
–
1
–
Datasheet
43
002-23053 Rev. *B
2023-03-29
PSoC™ 4 MCU with AIROC™ Bluetooth® LE
Based on Arm® Cortex®-M0
Electrical specifications
5.4.5
LCD direct drive
Table 31
LCD direct drive DC specifications
Details/
Spec ID
Parameter
Description
Min
Typ Max Unit
conditions
16 × 4 small
µA segmentdisplayat
50 Hz
Operating current in low-power
mode
SID228
ILCDLOW
–
17.5
–
LCD capacitance per
SID229
SID230
SID231
CLCDCAP
LCDOFFSET
ILCDOP1
–
–
–
500 5000
pF
mV
mA
–
–
segment/common driver
Long-term segment offset
LCD system operating current
VBIAS = 5 V.
20
2
–
–
32 × 4 segments.
50 Hz at 25°C
LCD system operating current.
VBIAS = 3.3 V
32 × 4 segments
50 Hz at 25°C
SID232
ILCDOP2
–
2
–
mA
Table 32
Spec ID
SID233
LCD direct drive AC specifications
Details/
Parameter
Description
Min
Typ Max Unit
conditions
FLCD
LCD frame rate
10
50
150
Hz
–
Table 33
Spec ID
Fixed UART DC specifications
Parameter Description
Details/
Min Typ Max
Unit
µA
conditions
Block current consumption at
100 kbps
SID234
SID235
IUART1
–
–
–
–
55
–
–
Block current consumption at
1000 kbps
IUART2
360
µA
Table 34
Spec ID
SID236
Fixed UART AC specifications
Details/
Parameter
Description
Min Typ Max
Unit
conditions
FUART
Bit rate
–
–
1
Mbps
–
Datasheet
44
002-23053 Rev. *B
2023-03-29
PSoC™ 4 MCU with AIROC™ Bluetooth® LE
Based on Arm® Cortex®-M0
Electrical specifications
5.4.6
SPI specifications
Table 35
Fixed SPI DC specifications
Details/
Spec ID
Parameter
ISPI1
Description
Min Typ Max Unit
conditions
SID237
Block current consumption at
1 Mbps
Block current consumption at
4 Mbps
Block current consumption at
8 Mbps
–
–
–
–
–
–
360
560
600
µA
µA
µA
–
–
–
SID238
SID239
ISPI2
ISPI3
Table 36
Spec ID
Fixed SPI AC specifications
Details/
Parameter
Description
Min Typ Max Unit
MHz
conditions
SPI operating frequency (master; 6X
oversampling)
SID240
FSPI
–
–
8
–
Table 37
Fixed SPI Master mode AC specifications
Details/
Spec ID Parameter
Description
Min Typ Max Unit
conditions
SID241
SID242
TDMO
TDSI
MOSI valid after Sclock driving edge
MISO valid before Sclock capturing
–
–
–
18
–
ns
ns
–
Full clock, late
MISO sampling
edge. Full clock, late MISO sampling 20
used
Referred to Slave
capturing edge
SID243
THMO
Previous MOSI data hold time
0
–
–
ns
Table 38
Fixed SPI Slave mode AC specifications
Details/
Spec ID Parameter
Description
Min Typ
Max
Unit
ns
conditions
MOSI valid before Sclock capturing
edge
SID244
SID245
SID246
TDMI
40
–
–
–
–
–
–
–
42 + 3 ×
TCPU
TDSO
MISO valid after Sclock driving edge
ns
MISO valid after Sclock driving edge
in external clock mode
TDSO_ext
–
53
ns VDD < 3.0 V
SID247
SID248
THSO
TSSELSCK
Previous MISO data hold time
SSEL valid to first SCK valid edge
0
100
–
–
–
–
ns
ns
–
–
Datasheet
45
002-23053 Rev. *B
2023-03-29
PSoC™ 4 MCU with AIROC™ Bluetooth® LE
Based on Arm® Cortex®-M0
Electrical specifications
5.5
Memory
Table 39
Spec ID
SID249
SID309
Flash DC specifications
Details/
Parameter
VPE
Description
Min
1.71
2
Typ
–
Max
5.5
–
Unit
conditions
Erase and program voltage
V
–
Number of Wait states at
32–48 MHz
Number of Wait states at
16–32 MHz
Number of Wait states for
0–16 MHz
CPU execution
from flash
CPU execution
from flash
CPU execution
from flash
TWS48
TWS32
TWS16
–
SID310
SID311
1
0
–
–
–
–
Table 40
Spec ID
Flash AC specifications
Details/
Parameter
Description
Min
Typ
Max
Unit
conditions
Row (block) = 128
bytes for 128 KB
flash devices
Row (block) = 256
bytes for 256 KB
flash devices
Row (block) write time
(erase and program)
[4]
[4]
SID250
TROWWRITE
–
–
20
ms
SID251
SID252
TROWERASE
Row erase time
Row program time after
erase
Bulk erase time (256 KB)
Total device program time
Flash endurance
Flash retention. TA 55°C,
100 K P/E cycles
Flash retention. TA 85°C,
10 K P/E cycles
–
–
–
–
13
7
ms
ms
ms
–
[4]
TROWPROGRAM
–
[4]
SID253
SID254
SID254A
SID255
TBULKERASE
–
–
–
–
–
–
–
35
50
25
–
–
256 KB
128 KB
–
[4]
TDEVPROG
seconds
FEND
FRET
100 K
cycles
years
SID256
20
10
–
–
–
–
–
–
SID257
FRET2
years
Note
4. It can take as much as 20 milliseconds to write to flash. During this time, the device should not be reset, or
flash operations will be interrupted and cannot be relied on to have completed. Reset sources include the
XRES pin, software resets, CPU lockup states and privilege violations, improper power supply levels, and
watchdogs. Make certain that these are not inadvertently activated.
Datasheet
46
002-23053 Rev. *B
2023-03-29
PSoC™ 4 MCU with AIROC™ Bluetooth® LE
Based on Arm® Cortex®-M0
Electrical specifications
5.6
System resources
5.6.1
Power-on reset (POR)
Table 41
Spec ID
SID258
SID259
SID260
POR DC specifications
Parameter
VRISEIPOR
Description
Min
0.80
0.75
15
Typ
–
–
Max
1.45
1.40
200
Unit Details/conditions
Rising trip voltage
Falling trip voltage
Hysteresis
V
V
–
–
–
VFALLIPOR
VIPORHYST
–
mV
Table 42
Spec ID
POR AC specifications
Parameter
Description
Min
Typ
Max
Unit Details/conditions
µs
PPOR response time in
Active and Sleep modes
SID264
TPPOR_TR
–
–
1
–
Table 43
Spec ID#
Brown-out detect
Parameter
Description
Min
Typ Max
Unit Details/conditions
BOD trip voltage in Active
and Sleep modes
BOD trip voltage in Deep
Sleep mode
SID261 VFALLPPOR
SID262 VFALLDPSLP
1.64
1.4
–
–
–
–
V
V
–
–
Table 44
Hibernate reset
Spec ID# Parameter
Description
Min
Typ
Max
Unit Details/conditions
BOD trip voltage in
Hibernate mode
SID263 VHBRTRIP
1.1
–
–
V
–
Datasheet
47
002-23053 Rev. *B
2023-03-29
PSoC™ 4 MCU with AIROC™ Bluetooth® LE
Based on Arm® Cortex®-M0
Electrical specifications
5.6.2
Voltage monitors
Table 45
Voltage monitor DC specifications
Details/
Spec ID Parameter
Description
Min
Typ
Max
Unit
conditions
SID265 VLVI1
SID266 VLVI2
SID267 VLVI3
SID268 VLVI4
SID269 VLVI5
SID270 VLVI6
SID271 VLVI7
SID272 VLVI8
SID273 VLVI9
SID274 VLVI10
SID2705 VLVI11
SID276 VLVI12
SID277 VLVI13
SID278 VLVI14
SID279 VLVI15
SID280 VLVI16
SID281 LVI_IDD
LVI_A/D_SEL[3:0] = 0000b
LVI_A/D_SEL[3:0] = 0001b
LVI_A/D_SEL[3:0] = 0010b
LVI_A/D_SEL[3:0] = 0011b
LVI_A/D_SEL[3:0] = 0100b
LVI_A/D_SEL[3:0] = 0101b
LVI_A/D_SEL[3:0] = 0110b
LVI_A/D_SEL[3:0] = 0111b
LVI_A/D_SEL[3:0] = 1000b
LVI_A/D_SEL[3:0] = 1001b
LVI_A/D_SEL[3:0] = 1010b
LVI_A/D_SEL[3:0] = 1011b
LVI_A/D_SEL[3:0] = 1100b
LVI_A/D_SEL[3:0] = 1101b
LVI_A/D_SEL[3:0] = 1110b
LVI_A/D_SEL[3:0] = 1111b
Block current
1.71
1.76
1.85
1.95
2.05
2.15
2.24
2.34
2.44
2.54
2.63
2.73
2.83
2.93
3.12
4.39
–
1.75
1.80
1.90
2.00
2.10
2.20
2.30
2.40
2.50
2.60
2.70
2.80
2.90
3.00
3.20
4.50
–
1.79
1.85
1.95
2.05
2.15
2.26
2.36
2.46
2.56
2.67
2.77
2.87
2.97
3.08
3.28
4.61
100
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
µA
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Table 46
Voltage monitor AC specifications
Details/
Spec ID Parameter
Description
Min
Typ
Max
Unit
conditions
SID282 TMONTRIP
Voltage monitor trip time
–
–
1
µs
–
5.6.3
SWD interface
Table 47
SWD interface specifications
Details/
Spec ID
Parameter
Description
3.3 V VDD 5.5 V
1.71 V VDD 3.3 V
Min
–
Typ
–
Max
Unit
conditions
SWDCLK≤1/3CPU
clock frequency
SWDCLK≤1/3CPU
clock frequency
SID283 F_SWDCLK1
SID284 F_SWDCLK2
14
7
MHz
MHz
–
–
SID285 T_SWDI_SETUP T = 1/f SWDCLK
SID286 T_SWDI_HOLD T = 1/f SWDCLK
SID287 T_SWDO_VALID T = 1/f SWDCLK
SID288 T_SWDO_HOLD T = 1/f SWDCLK
0.25 × T
0.25 × T
–
–
–
–
–
ns
ns
ns
ns
–
–
–
–
–
0.5 × T
–
–
1
Datasheet
48
002-23053 Rev. *B
2023-03-29
PSoC™ 4 MCU with AIROC™ Bluetooth® LE
Based on Arm® Cortex®-M0
Electrical specifications
5.6.4
Internal main oscillator
Table 48
IMO DC specifications
Details/
Spec ID
Parameter
Description
Min
Typ
Max
Unit
conditions
SID289 IIMO1
SID290 IIMO2
SID291 IIMO3
SID292 IIMO4
SID293 IIMO5
IMO operating current at
48 MHz
IMO operating current at
24 MHz
IMO operating current at
12 MHz
IMO operating current at
6 MHz
–
–
1000
µA
–
–
–
–
–
–
–
–
–
–
–
–
–
325
225
180
150
µA
µA
µA
µA
IMO operating current at
3 MHz
Table 49
IMO AC specifications
Details/
Spec ID
Parameter
Description
Min
Typ
Max
Unit
conditions
Frequency variation from 3 to
48 MHz
IMO startup time
With API-called
calibration
SID296
SID297
FIMOTOL3
FIMOTOL3
–
–
–
–
±2
12
%
µs
–
5.6.5
Internal low-speed oscillator
Table 50
ILO DC specifications
Details/
Spec ID
Parameter
Description
Min
Typ
0.3
Max
1.05
Unit
µA
conditions
SID298 IILO2
ILO operating current at
32 kHz
–
–
Table 51
ILO AC specifications
Parameter Description
TSTARTILO1 ILO startup time
FILOTRIM1
Details/
Spec ID
Min
Typ
Max
Unit
conditions
SID299
SID300
–
15
–
32
2
50
ms
kHz
–
–
32-kHz trimmed frequency
Table 52
Spec ID
External clock specifications
Details/
Parameter
Description
Min
Typ
Max
Unit
conditions
SID301 ExtClkFreq
SID302 ExtClkDuty
External clock input
frequency
Duty cycle; Measured at VDD/2
0
–
48
MHz CMOS input level
only
45
–
55
%
CMOS input level
only
Datasheet
49
002-23053 Rev. *B
2023-03-29
PSoC™ 4 MCU with AIROC™ Bluetooth® LE
Based on Arm® Cortex®-M0
Electrical specifications
Table 53
Spec ID
UDB AC specifications
Parameter
Details/
Description
Min Typ
Max
Unit
conditions
Data path performance
Max frequency of 16-bit timer in
a UDB pair
Max frequency of 16-bit adder in
a UDB pair
Max frequency of 16-bit
CRC/PRS in a UDB pair
SID303
SID304
SID305
FMAX-TIMER
FMAX-ADDER
FMAX_CRC
–
–
–
–
–
–
48
48
48
MHz
MHz
MHz
–
–
–
PLD performance in UDB
SID306 FMAX_PLD
Clock to output performance
Max frequency of 2-pass PLD
function in a UDB pair
–
–
48
MHz
–
Prop. delay for clock in to data
out at 25°C, Typical
Prop. delay for clock in to data
out, Worst case
SID307
SID308
TCLK_OUT_UDB1
TCLK_OUT_UDB2
–
–
15
25
–
–
ns
ns
–
–
Datasheet
50
002-23053 Rev. *B
2023-03-29
PSoC™ 4 MCU with AIROC™ Bluetooth® LE
Based on Arm® Cortex®-M0
Electrical specifications
Table 54
Bluetooth® LE subsystem
Details/
Spec ID# Parameter
RF receiver specification
Description
Min Typ Max
Unit
conditions
RX sensitivity with idle trans-
mitter
RX sensitivity with idle trans-
mitter excluding Balun loss
SID340
RXS, IDLE
SID340A
–
–
–89
–91
–
–
dBm
dBm
–
Guaranteed by
design simulation
RF-PHY
RX sensitivity with dirty trans-
mitter
SID341
SID342
SID343
RXS, DIRTY
–
–
–87 –70
dBm Specification
(RCV-LE/CA/01/C)
RXS,
HIGHGAIN
RX sensitivity in high-gain mode
with idle transmitter
–91
–1
–
–
dBm
–
RF-PHY
dBm Specification
(RCV-LE/CA/06/C)
PRXMAX
CI1
Maximum input power
–10
Co-channel interference,
Wanted signal at –67 dBm and
Interferer at FRX
Adjacent channel interference
Wanted signal at –67 dBm and
Interferer at FRX ±1 MHz
Adjacent channel interference
Wanted signal at –67 dBm and
Interferer at FRX ±2 MHz
Adjacent channel interference
Wanted signal at –67 dBm and
Interferer at ≥FRX ±3 MHz
RF-PHY
Specification
(RCV-LE/CA/03/C)
RF-PHY
Specification
(RCV-LE/CA/03/C)
RF-PHY
Specification
(RCV-LE/CA/03/C)
RF-PHY
Specification
(RCV-LE/CA/03/C)
SID344
SID345
SID346
SID347
–
–
–
–
9
21
15
–
dB
dB
dB
dB
CI2
3
CI3
–29
–39
CI4
–
Adjacent channel interference
Wanted Signal at –67 dBm and
Interferer at Image frequency
RF-PHY
SID348
SID349
CI5
CI6
–
–
–20
–30
–
–
dB
dB
Specification
(RCV-LE/CA/03/C)
(FIMAGE
)
Adjacent channel interference
Wanted signal at –67 dBm and
Interferer at Image frequency
(FIMAGE ± 1 MHz)
RF-PHY
Specification
(RCV-LE/CA/03/C)
Out-of-band blocking,
RF-PHY
SID350
SID351
SID352
SID353
OBB1
OBB2
OBB3
OBB4
Wanted signal at –67 dBm and
Interferer at F = 30–2000 MHz
–30 –27
–35 –27
–35 –27
–30 –27
–
–
–
–
dBm Specification
(RCV-LE/CA/04/C)
Out-of-band blocking,
Wanted signal at –67 dBm and
Interferer at F = 2003–2399 MHz
Out-of-band blocking,
Wanted signal at –67 dBm and
Interferer at F = 2484–2997 MHz
Out-of-band blocking,
Wanted signal a –67 dBm and
Interferer at F = 3000–12750 MHz
RF-PHY
dBm Specification
(RCV-LE/CA/04/C)
RF-PHY
dBm Specification
(RCV-LE/CA/04/C)
RF-PHY
dBm Specification
(RCV-LE/CA/04/C)
Datasheet
51
002-23053 Rev. *B
2023-03-29
PSoC™ 4 MCU with AIROC™ Bluetooth® LE
Based on Arm® Cortex®-M0
Electrical specifications
Table 54
Bluetooth® LE subsystem (continued)
Details/
Spec ID# Parameter
Description
Min Typ Max
Unit
conditions
Intermodulation performance
Wanted signal at –64 dBm and
1-Mbps Bluetooth® LE, third,
fourth, and fifth offset channel
RF-PHY
dBm Specification
(RCV-LE/CA/05/C)
SID354
SID355
IMD
–50
–
–
–
–
100-kHz
measurement
dBm bandwidth
ETSI EN300 328
V1.8.1
Receiver spurious emission
30 MHz to 1.0 GHz
RXSE1
–57
1-MHz
measurement
dBm bandwidth
ETSI EN300 328
V1.8.1
Receiver spurious emission
1.0 GHz to 12.75 GHz
SID356
RXSE2
–
–
–47
RF transmitter specifications
SID357
SID358
TXP, ACC
TXP, RANGE
RF power accuracy
RF power control range
–
–
±1
20
–
–
dB
dB
–
–
Output power, 0-dB Gain setting
(PA7)
Output power, maximum power
setting (PA10)
Output power, minimum power
setting (PA1)
SID359
SID360
SID361
TXP, 0dBm
TXP, MAX
TXP, MIN
–
–
–
0
3
–
–
–
dBm
dBm
dBm
–
–
–
–18
RF-PHY
kHz Specification
(TRM-LE/CA/05/C)
Average frequency deviation for
10101010 pattern
SID362
SID363
SID364
SID365
SID366
SID367
SID368
SID369
F2AVG
185
–
–
RF-PHY
Average frequency deviation for
11110000 pattern
F1AVG
225 250 275
kHz Specification
(TRM-LE/CA/05/C)
RF-PHY
Specification
(TRM-LE/CA/05/C)
EO
Eye opening = ∆F2AVG/∆F1AVG
Frequency accuracy
0.8
–150
–50
–20
–20
–
–
–
–
–
–
–
–
RF-PHY
FTX, ACC
FTX, MAXDR
FTX, INITDR
FTX, DR
IBSE1
150
50
kHz Specification
(TRM-LE/CA/06/C)
RF-PHY
Maximum frequency drift
Initial frequency drift
kHz Specification
(TRM-LE/CA/06/C)
RF-PHY
20
kHz Specification
(TRM-LE/CA/06/C)
RF-PHY
Specification
(TRM-LE/CA/06/C)
kHz/
50 µs
Maximum drift rate
20
RF-PHY
In-band spurious emission at
2-MHz offset
–20
dBm Specification
(TRM-LE/CA/03/C)
Datasheet
52
002-23053 Rev. *B
2023-03-29
PSoC™ 4 MCU with AIROC™ Bluetooth® LE
Based on Arm® Cortex®-M0
Electrical specifications
Table 54
Bluetooth® LE subsystem (continued)
Details/
Spec ID# Parameter
Description
Min Typ Max
Unit
conditions
RF-PHY
dBm Specification
(TRM-LE/CA/03/C)
In-band spurious emission at
≥3-MHz offset
SID370
IBSE2
–
–
-30
Transmitter spurious emissions
(average), <1.0 GHz
SID371
SID372
TXSE1
TXSE2
–
–
–
–
-55.5 dBm FCC-15.247
-41.5 dBm FCC-15.247
Transmitter spurious emissions
(average), >1.0 GHz
RF current specifications
SID373 IRX
Receive current in normal mode
Radio receive current in normal
mode
–
–
18.7
16.4
–
–
mA
mA
–
SID373A IRX_RF
Measured at VDDR
Receive current in high-gain
mode
TX current at 3-dBm setting
(PA10)
TX current at 0-dBm setting
(PA7)
Radio TX current at 0 dBm
setting (PA7)
Radio TX current at 0 dBm
excluding Balun loss
TX current at –3-dBm setting
(PA4)
TX current at –6-dBm setting
(PA3)
TX current at –12-dBm setting
(PA2)
SID374
SID375
SID376
IRX, HIGHGAIN
–
–
–
–
–
–
–
–
–
21.5
20
–
–
–
–
–
–
–
–
–
mA
mA
mA
mA
mA
mA
mA
mA
mA
–
ITX, 3dBm
ITX, 0dBm
–
16.5
15.6
14.2
15.5
14.5
13.2
12.5
–
SID376A ITX_RF, 0dBm
SID376B ITX_RF, 0dBm
Measured at VDDR
Guaranteed by
design simulation
SID377
SID378
SID379
SID380
ITX,-3dBm
ITX,-6dBm
ITX,-12dBm
ITX,-18dBm
–
–
–
–
TX current at –18-dBm setting
(PA1)
TXP: 0 dBm;
Average current at 1-second
Bluetooth® LE connection
interval
Iavg_1sec,
0dBm
±20-ppm master
and slave clock
accuracy.
SID380A
SID380B
–
–
17.1
6.1
–
–
µA
µA
TXP: 0 dBm;
Average current at 4-second
Bluetooth® LE connection
interval
Iavg_4sec,
0dBm
±20-ppm master
and slave clock
accuracy.
General RF specifications
SID381
SID382
SID383
FREQ
CHBW
DR
RF operating frequency
Channel spacing
On-air data rate
2400
–
–
–
2
1000
2482
–
–
MHz
MHz
kbps
–
–
–
Bluetooth® LE.IDLE to
Bluetooth® LE. TX transition
time
SID384
IDLE2TX
–
120 140
µs
–
Datasheet
53
002-23053 Rev. *B
2023-03-29
PSoC™ 4 MCU with AIROC™ Bluetooth® LE
Based on Arm® Cortex®-M0
Electrical specifications
Table 54
Bluetooth® LE subsystem (continued)
Details/
Spec ID# Parameter
Description
Min Typ Max
Unit
conditions
Bluetooth® LE.IDLE to
Bluetooth® LE. RX transition
time
SID385
IDLE2RX
–
75
120
µs
–
RSSI specifications
SID386
SID387
SID388
RSSI, ACC
RSSI, RES
RSSI, PER
RSSI accuracy
–
–
–
±5
1
6
–
–
–
dB
dB
µs
–
–
–
RSSI resolution
RSSI sample period
Table 55
ECO specifications
Details/
Spec ID# Parameter
Description
Crystal frequency
Frequency tolerance
Equivalent series resistance
Drive level
Startup time (Fast Charge on)
Startup time (Fast Charge off)
Load capacitance
Min Typ
Max Unit
conditions
SID389
SID390
SID391
SID392
SID393
SID394
SID395
SID396
SID397
FECO
FTOL
ESR
–
–50
–
24
–
–
–
50
60
100
850
3
MHz
ppm
Ω
µW
µs
–
–
–
–
–
–
–
–
–
PD
–
–
TSTART1
TSTART2
CL
C0
IECO
–
–
–
–
ms
pF
–
8
–
Shunt capacitance
Operating current
–
–
1.1
1400
–
pF
–
µA
Table 56
Spec ID#
WCO specifications
Parameter
FWCO
Details/
Description
Min
Typ
Max
Unit
conditions
SID398
SID399
SID400
SID401
SID402
SID403
SID404
Crystal frequency
–
–
–
–
–
6
–
32.768
–
–
–
kHz
ppm
kΩ
µW
ms
pF
–
–
–
–
–
–
–
FTOL
ESR
PD
Frequency tolerance
Equivalent series resistance
Drive level
50
50
–
–
–
1
TSTART
CL
C0
Startup time
Crystal load capacitance
Crystal shunt capacitance
500
12.5
–
1.35
pF
Operating current
(High-Power mode)
Operating current(Low-Power
mode)
SID405
SID406
IWCO1
IWCO2
–
–
–
–
8
µA
µA
–
–
2.6
Datasheet
54
002-23053 Rev. *B
2023-03-29
PSoC™ 4 MCU with AIROC™ Bluetooth® LE
Based on Arm® Cortex®-M0
Ordering information
6
Ordering information
The PSoC™ 4 CY8C42xx-BL MCU with AIROC™ Bluetooth® LE part numbers and features are listed in Table 57.
Table 57 CY8C42xx-BL MCU with AIROC™ Bluetooth® LE part numbers
CY8C4247LQI-BL473
48 4.1 128 16
48 4.1 128 16
48 4.1 128 16
48 4.1 128 16
48 4.1 128 16
48 4.1 128 16
48 4.1 128 16
48 4.1 128 16
48 4.1 128 16
48 4.1 128 16
48 4.1 128 16
48 4.1 256 32
48 4.1 256 32
48 4.1 256 32
48 4.2 256 32
48 4.2 256 32
48 4.2 256 32
48 4.2 256 32
48 4.2 256 32
48 4.2 256 32
48 4.2 256 32
48 4.2 256 32
48 4.2 256 32
48 4.2 256 32
4
4
4
4
4
4
4
4
4
4
4
4
4
4
–
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
2
4
4
4
4
4
4
4
4
4
–
–
1
–
1
1
1
1
1
1
1
1
1
1
–
–
–
1
1
–
1
1
1
1
–
–
–
–
–
1
–
1
–
–
1
–
–
–
–
–
–
–
–
–
–
–
–
1
–
–
–
1
1
1
1
1
1
1
1
–
1
1
–
–
–
–
–
1
1
1
1
1
1 Msps
1 Msps
1 Msps
1 Msps
1 Msps
1 Msps
1 Msps
1 Msps
1 Msps
1 Msps
1 Msps
1 Msps
1 Msps
1 Msps
1 Msps
1 Msps
1 Msps
1 Msps
1 Msps
1 Msps
1 Msps
1 Msps
1 Msps
1 Msps
–
–
–
–
–
–
–
–
–
–
–
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
–
2
2
2
2
2
2
2
2
2
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
36
36
36
36
36
36
36
36
36
36
QFN
68-CSP
QFN
85°C
85°C
85°C
85°C
85°C
85°C
85°C
85°C
105°C
105°C
CY8C4247FNI-BL473
CY8C4247LQI-BL453
CY8C4247LQI-BL463
CY8C4247LQI-BL483
CY8C4247LQI-BL493
CY8C4247FNI-BL483
CY8C4247FNI-BL493
CY8C4247FNQ-BL483
CY8C4247LQQ-BL483
CY8C4247FLI-BL493
CY8C4248LQI-BL453
CY8C4248LQI-BL483
CY8C4248FNI-BL483
CY8C4248LQI-BL543
CY8C4248LQI-BL573
CY8C4248FNI-BL573
CY8C4248LQI-BL553
CY8C4248FNI-BL553
CY8C4248LQI-BL563
CY8C4248LQI-BL583
CY8C4248FNI-BL583
CY8C4248LQQ-BL583
CY8C4248LQI-BL593
QFN
QFN
QFN
68-CSP
68-CSP
68-CSP
QFN
36 Thin 68-CSP 85°C
36
36
36
36
36
36
36
36
36
36
36
36
36
QFN
QFN
85°C
85°C
85°C
85°C
85°C
85°C
85°C
85°C
85°C
85°C
85°C
105°C
85°C
76-CSP
QFN
QFN
76-CSP
QFN
76-CSP
QFN
QFN
76-CSP
QFN
QFN
PSoC™ 4 devices follow the part numbering convention described in the following table. All fields are
single-character alphanumeric (0, 1, 2, …, 9, A,B, …, Z) unless stated otherwise.
Datasheet
55
002-23053 Rev. *B
2023-03-29
PSoC™ 4 MCU with AIROC™ Bluetooth® LE
Based on Arm® Cortex®-M0
Ordering information
6.1
Ordering code definitions
CY 8 C
4
A
B
C
D
E
F
-
BLXYZ
Example
Cypress prefix
CY8 C
4 : PSoC™ 4
Architecture
Family within architecture
Speed grade
2 : 4200 family
4 : 48MHz
Flash capacity
8 : 256KB
Package code
LQ : QFN
Temperature range
Attributes code
I : Industrial
BLXYZ : Attributes
The field values are listed in the following table:
Field
CY8C
4
Description
Cypress prefix
Architecture
Family within
architecture
Values
Meaning
4
2
PSoC™ 4
PSoC™ 4 CY8C42xx-BL MCU with AIROC™ Bluetooth® LE
family
A
B
C
CPU speed
Flash capacity
4
8, 7
FN
LQ
FL
I
48 MHz
256, 128 KB respectively
WLCSP
QFN
Thin CSP
DE
F
Package code
Temperature range
Industrial
BL400-BL499 Bluetooth® 4.1 compliant
BL500-BL599 Bluetooth® 4.2 compliant
BLXYZ Attributes code
Datasheet
56
002-23053 Rev. *B
2023-03-29
PSoC™ 4 MCU with AIROC™ Bluetooth® LE
Based on Arm® Cortex®-M0
Packaging
7
Packaging
Table 58
Package characteristics
Description
Parameter
Conditions
Min
Typ
Max
Unit
Operating ambient
temperature
Operating junction
temperature
TA
TJ
–
–40
25.00
105
°C
–
–40
–
125
°C
TJA
TJC
TJA
TJC
Package JA (56-pin QFN)
Package JC (56-pin QFN)
Package JA (76-ball WLCSP)
Package JC (76-ball WLCSP)
–
–
–
–
–
–
–
–
16.9
9.7
20.1
0.19
–
–
–
–
°C/watt
°C/watt
°C/watt
°C/watt
Package JA (76-ball thin
TJA
TJC
–
–
–
–
20.9
0.17
–
–
°C/watt
°C/watt
WLCSP)
Package JC (76-ball thin
WLCSP)
TJA
TJC
TJA
Package JA (68-ball WLCSP)
Package JC (68-ball WLCSP)
Package JA (68-ball thin
WLCSP)
Package JC (68-ball thin
WLCSP)
–
–
–
–
–
16.6
0.19
16.6
–
–
–
°C/watt
°C/watt
°C/watt
–
–
TJC
–
0.19
–
°C/watt
Table 59
Solder reflow peak temperature
Package
Maximum peak
temperature
Maximum time at peak
temperature
All packages
260°C
30 seconds
Table 60
Table 61
Package moisture sensitivity level (MSL), IPC/JEDEC J-STD-2
Package
56-pin QFN
All WLCSP packages
MSL
MSL 3
MSL 1
Package details
Spec ID
Package
Description
001-58740 Rev. *C
001-96603 Rev. *B
002-10658 Rev. **
001-92343 Rev. *A
001-99408 Rev. **
56-pin QFN
7.0 mm × 7.0 mm × 0.6 mm
4.04 mm × 3.87 mm × 0.55 mm
4.04 mm × 3.87 mm × 0.4 mm
3.52 mm × 3.91 mm × 0.55 mm
52 mm × 3.91 mm × 0.4 mm
76-ball WLCSP
76-ball thin WLCSP
68-ball WLCSP
68-ball thin WLCSP
Datasheet
57
002-23053 Rev. *B
2023-03-29
PSoC™ 4 MCU with AIROC™ Bluetooth® LE
Based on Arm® Cortex®-M0
Packaging
TOP VIEW
SIDE VIEW
BOTTOM VIEW
NOTES:
1. HATCH AREA IS SOLDERABLE EXPOSED PAD
2. BASED ON REF JEDEC # MO-248
3. ALL DIMENSIONS ARE IN MILLIMETERS
001-58740 *C
Figure 7
56-pin QFN 7 × 7 × 0.6 mm
The center pad on the QFN package should be connected to ground (VSS) for best mechanical, thermal, and
electrical performance.
Datasheet
58
002-23053 Rev. *B
2023-03-29
PSoC™ 4 MCU with AIROC™ Bluetooth® LE
Based on Arm® Cortex®-M0
Packaging
7.1
WLCSP compatibility
The PSoC™ 4XXX-BLE family has products with 128 KB (16KB SRAM) and 256 KB (32KB SRAM) Flash. Package
pin-outs and sizes are identical for the 56-pin QFN package but are different in one dimension for the 68-ball
WLCSP.
The 256KB Flash product has an extra column of balls which are required for mechanical integrity purposes in
the Chip-Scale package. With consideration for this difference, the land pattern on the PCB may be designed such
that either product may be used with no change to the PCB design.
Figure 8 shows the 128KB and 256 KB Flash CSP packages.
128-K Bluetooth® LE
256-K Bluetooth® LE
CONNECTED PADS
NC PADS
PACKAGE CENTER
PACK BOUNDARY
FIDUCIAL FOR128K
FIDUCIAL FOR256K
Figure 8
128KB and 256 KB Flash CSP packages
The rightmost column of (all NC, No Connect) balls in the 256K Bluetooth® LE WLCSP is for mechanical integrity
purposes. The package is thus wider (3.2 mm versus 2.8 mm). All other dimensions are identical. Infineon will
provide layout symbols for printed circuit board (PCB) layout.
The scheme in Figure 8 is implemented to design the PCB for the 256K Bluetooth® LE package with the
appropriate space requirements thus allowing use of either package at a later time without redesigning the PCB.
Datasheet
59
002-23053 Rev. *B
2023-03-29
PSoC™ 4 MCU with AIROC™ Bluetooth® LE
Based on Arm® Cortex®-M0
Packaging
001-92343 *A
Figure 9
68-ball WLCSP package outline
SIDE VIEW
BOTTOM VIEW
TOP VIEW
1
2
3
4
5
6
7
8
8
7
6
5
4
3
2
1
A
B
C
D
E
F
A
B
C
D
E
F
G
H
G
H
J
J
NOTES:
1. REFERENCE JEDEC PUBLICATION 95, DESIGN GUIDE 4.18
2. ALL DIMENSIONS ARE IN MILLIMETERS
001-99408 **
Figure 10
68-ball thin WLCSP
Datasheet
60
002-23053 Rev. *B
2023-03-29
PSoC™ 4 MCU with AIROC™ Bluetooth® LE
Based on Arm® Cortex®-M0
Packaging
PIN #1 MARK
B
1
2
3
4
5
6
7
8
9
9
8
7
6
5
4
3
2
1
7
A
B
C
D
E
F
A
B
C
D
E
F
6
SD
D1
D
G
H
J
G
H
J
eD
SE
A
E
eE
6
E1
TOP VIEW
BOTTOM VIEW
0.10 C
5
DETAIL A
A1
0.05 C
C
76XØb
Ø0.06 M C A B
Ø0.03 M C
A
DETAIL A
SIDE VIEW
NOTES:
1. ALL DIMENSIONS ARE IN MILLIMETERS.
DIMENSIONS
NOM.
SYMBOL
2. SOLDER BALL POSITION DESIGNATION PER JEP95, SECTION 3, SPP-020.
3. "e" REPRESENTS THE SOLDER BALL GRID PITCH.
MIN.
MAX.
0.55
0.24
A
-
-
0.21
4. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D" DIRECTION.
SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION.
N IS THE NUMBER OF POPULATED SOLDER BALL POSITIONS FOR MATRIX
SIZE MD X ME.
A1
D
0.18
3.87 BSC
E
4.04 BSC
3.20 BSC
3.20 BSC
9
D1
E1
MD
ME
N
5.
DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A
PLANE PARALLEL TO DATUM C.
6.
"SD" AND "SE" ARE MEASURED WITH RESPECT TO DATUMS A AND B AND
DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW.
9
76
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW,
"SD" OR "SE" = 0.
0.26
b
0.23
0.29
eD
eE
SD
SE
0.40 BSC
0.40 BSC
0.381 BSC
0.321 BSC
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW,
"SD" = eD/2 AND "SE" = eE/2.
A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK
METALIZED MARK, INDENTATION OR OTHER MEANS.
7.
8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED SOLDER
BALLS.
9. JEDEC SPECIFICATION NO. REF : N/A
001-96603 *B
Figure 11
76-ball WLCSP package outline
Datasheet
61
002-23053 Rev. *B
2023-03-29
PSoC™ 4 MCU with AIROC™ Bluetooth® LE
Based on Arm® Cortex®-M0
Packaging
PIN #1 MARK
B
1
2
3
4
5
6
7
8
9
9
8
7
6
5
4
3
2
1
7
A
B
C
D
E
F
A
B
C
D
E
F
6
SD
D1
D
G
H
J
G
H
J
eD
SE
A
E
eE
6
E1
TOP VIEW
BOTTOM VIEW
0.10 C
5
DETAIL A
A1
0.05 C
C
76XØb
Ø0.06 M C A B
Ø0.03 M C
A
SIDE VIEW
NOTES:
1. ALL DIMENSIONS ARE IN MILLIMETERS.
DIMENSIONS
NOM.
SYMBOL
2. SOLDER BALL POSITION DESIGNATION PER JEP95, SECTION 3, SPP-020.
3. "e" REPRESENTS THE SOLDER BALL GRID PITCH.
MIN.
MAX.
0.40
A
-
-
0.08
4. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D" DIRECTION.
SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION.
N IS THE NUMBER OF POPULATED SOLDER BALL POSITIONS FOR MATRIX
SIZE MD X ME.
0.088
A1
D
0.072
3.87 BSC
E
4.04 BSC
3.20 BSC
3.20 BSC
9
D1
E1
MD
ME
N
5.
DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A
PLANE PARALLEL TO DATUM C.
6.
"SD" AND "SE" ARE MEASURED WITH RESPECT TO DATUMS A AND B AND
DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW.
9
76
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW,
"SD" OR "SE" = 0.
0.25
b
0.22
0.28
eD
eE
SD
SE
0.40 BSC
0.40 BSC
0.381
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW,
"SD" = eD/2 AND "SE" = eE/2.
A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK
METALIZED MARK, INDENTATION OR OTHER MEANS.
7.
0.321
8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED SOLDER
BALLS.
002-10658 **
Figure 12
76-ball thin WLCSP package outline
Datasheet
62
002-23053 Rev. *B
2023-03-29
PSoC™ 4 MCU with AIROC™ Bluetooth® LE
Based on Arm® Cortex®-M0
Acronyms
8
Acronyms
Table 62
Acronym
ABUS
ADC
Acronyms used in this document
Description
analog local bus
analog-to-digital converter
analog global
AG
AHB
AMBA (advanced microcontroller bus architecture) high-performance bus, an Arm® data transfer
bus
ALU
arithmetic logic unit
AMUXBUS
API
APSR
Arm®®
ATM
BW
analog multiplexer bus
application programming interface
application program status register
advanced RISC machine, a CPU architecture
automatic thump mode
bandwidth
CAN
CMRR
CPU
CRC
DAC
DFB
Controller Area Network, a communications protocol
common-mode rejection ratio
central processing unit
cyclic redundancy check, an error-checking protocol
digital-to-analog converter, see also IDAC, VDAC
digital filter block
DIO
digital input/output, GPIO with only digital capabilities, no analog. See GPIO.
Dhrystone million instructions per second
direct memory access, see also TD
differential nonlinearity, see also INL
do not use
DMIPS
DMA
DNL
DNU
DR
port write data registers
DSI
digital system interconnect
DWT
ECC
data watchpoint and trace
error correcting code
ECO
EEPROM
EMI
EMIF
EOC
EOF
external crystal oscillator
electrically erasable programmable read-only memory
electromagnetic interference
external memory interface
end of conversion
end of frame
EPSR
ESD
execution program status register
electrostatic discharge
ETM
FET
embedded trace macrocell
field-effect transistor
FIR
finite impulse response, see also IIR
Datasheet
63
002-23053 Rev. *B
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PSoC™ 4 MCU with AIROC™ Bluetooth® LE
Based on Arm® Cortex®-M0
Acronyms
Table 62
Acronym
FPB
FS
Acronyms used in this document (continued)
Description
flash patch and breakpoint
full-speed
GPIO
HCI
general-purpose input/output, applies to a PSoC™ pin
host controller interface
HVI
IC
high-voltage interrupt, see also LVI, LVD
integrated circuit
IDAC
IDE
I2C, or IIC
IIR
ILO
IMO
INL
current DAC, see also DAC, VDAC
integrated development environment
Inter-Integrated Circuit, a communications protocol
infinite impulse response, see also FIR
internal low-speed oscillator, see also IMO
internal main oscillator, see also ILO
integral nonlinearity, see also DNL
input/output, see also GPIO, DIO, SIO, USBIO
initial power-on reset
I/O
IPOR
IPSR
IRQ
interrupt program status register
interrupt request
ITM
LCD
LIN
instrumentation trace macrocell
liquid crystal display
Local Interconnect Network, a communications protocol.
link register
LR
LUT
LVD
LVI
LVTTL
MAC
MCU
MISO
NC
lookup table
low-voltage detect, see also LVI
low-voltage interrupt, see also HVI
low-voltage transistor-transistor logic
multiply-accumulate
microcontroller unit
master-in slave-out
no connect
NMI
nonmaskable interrupt
NRZ
NVIC
NVL
Opamp
PAL
non-return-to-zero
nested vectored interrupt controller
nonvolatile latch, see also WOL
operational amplifier
programmable array logic, see also PLD
program counter
PC
PCB
PGA
PHUB
PHY
printed circuit board
programmable gain amplifier
peripheral hub
physical layer
Datasheet
64
002-23053 Rev. *B
2023-03-29
PSoC™ 4 MCU with AIROC™ Bluetooth® LE
Based on Arm® Cortex®-M0
Acronyms
Table 62
Acronym
PICU
PLA
PLD
PLL
Acronyms used in this document (continued)
Description
port interrupt control unit
programmable logic array
programmable logic device, see also PAL
phase-locked loop
PMDD
POR
PRES
PRS
package material declaration data sheet
power-on reset
precise power-on reset
pseudo random sequence
port read data register
PS
PSoC™
UDB
USB
Programmable system on chip
universal digital block
Universal Serial Bus
USBIO
VDAC
WDT
PSRR
PWM
RAM
RISC
RMS
RTC
USB input/output, PSoC™ pins used to connect to a USB port
voltage DAC, see also DAC, IDAC
watchdog timer
power supply rejection ratio
pulse-width modulator
random-access memory
reduced-instruction-set computing
root-mean-square
real-time clock
RTL
RTR
RX
register transfer language
remote transmission request
receive
SAR
SC/CT
SCL
successive approximation register
switched capacitor/continuous time
I2C serial clock
SDA
I2C serial data
S/H
sample and hold
SINAD
SIO
SOC
signal to noise and distortion ratio
special input/output, GPIO with advanced features. See GPIO.
start of conversion
SOF
start of frame
SPI
SR
Serial Peripheral Interface, a communications protocol
slew rate
SRAM
SRES
STN
static random access memory
software reset
super twisted nematic
SWD
SWV
serial wire debug, a test protocol
single-wire viewer
Datasheet
65
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PSoC™ 4 MCU with AIROC™ Bluetooth® LE
Based on Arm® Cortex®-M0
Acronyms
Table 62
Acronym
TD
THD
TIA
Acronyms used in this document (continued)
Description
transaction descriptor, see also DMA
total harmonic distortion
transimpedance amplifier
twisted nematic
TN
TRM
TTL
TX
technical reference manual
transistor-transistor logic
transmit
UART
WOL
WRES
XRES
XTAL
Universal Asynchronous Transmitter Receiver, a communications protocol
write once latch, see also NVL
watchdog timer reset
external reset I/O pin
crystal
Datasheet
66
002-23053 Rev. *B
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PSoC™ 4 MCU with AIROC™ Bluetooth® LE
Based on Arm® Cortex®-M0
Document conventions
9
Document conventions
9.1
Units of measure
Table 63
Units of measure
Symbol
Units of measure
°C
dB
degrees Celsius
decibel
dBm
fF
Hz
decibel-milliwatts
femtofarads
hertz
KB
1024 bytes
kbps
Khr
kHz
k
ksps
LSB
Mbps
MHz
M
Msps
µA
kilobits per second
kilohour
kilohertz
kilo ohm
kilosamples per second
least significant bit
megabits per second
megahertz
mega-ohm
megasamples per second
microampere
microfarad
µF
µH
µs
µV
microhenry
microsecond
microvolt
µW
mA
ms
mV
nA
microwatt
milliampere
millisecond
millivolt
nanoampere
nanosecond
nanovolt
ns
nV
ohm
pF
picofarad
ppm
ps
s
parts per million
picosecond
second
sps
sqrtHz
V
samples per second
square root of hertz
volt
Datasheet
67
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2023-03-29
PSoC™ 4 MCU with AIROC™ Bluetooth® LE
Based on Arm® Cortex®-M0
Revision history
Revision history
Document
Date
Description of changes
revision
**
2018-02-22
New datasheet
Updated datasheet to IFX template.
*A
*B
2021-06-16
2023-03-29
Changed title to “PSoC™ 4 CY8C42xx-BL MCU with AIROC™ Bluetooth® LE
Family Datasheet”
Updated to the latest template
Added Table 2 for 68-ball WLCSP package
Removed the following part numbers from Table 57:
CY8C4248LQI-BL473, CY8C4248FLI-BL483, CY8C4248FNI-BL543,
CY8C4248FNI-BL563, CY8C4248FLI-BL583, CY8C4248FNQ-BL583, and
CY8C4248FNI-BL593
Datasheet
68
002-23053 Rev. *B
2023-03-29
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Edition 2023-03-29
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in question please contact your nearest Infineon
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