CY9AF112KPMC-G-JNCGE1

The following document contains information on Cypress products. The document has the series

name, product name, and ordering part numbering with the prefix “MB”. However, Cypress will

offer these products to new and existing customers with the series name, product name, and

ordering part number with the prefix “CY”.

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About Cypress

Cypress is the leader in advanced embedded system solutions for the world's most innovative

automotive, industrial, smart home appliances, consumer electronics and medical products.

Cypress' microcontrollers, analog ICs, wireless and USB-based connectivity solutions and reliable,

high-performance memories help engineers design differentiated products and get them to market

first. Cypress is committed to providing customers with the best support and development

resources on the planet enabling them to disrupt markets by creating new product categories in

record time. To learn more, go to www.cypress.com.

MB9A110K Series

32-bit ARM^®Cortex^®-M3

FM3 Microcontroller

The MB9A110K Series are a highly integrated 32-bit microcontrollers dedicated for embedded controllers with high-performance and

low cost.

These series are based on the ARM^®Cortex^®-M3 Processor with on-chip Flash memory and SRAM, and has peripheral functions

such as Motor Control Timers, ADCs and Communication Interfaces (UART, CSIO, I²C, LIN).

The products which are described in this datasheet are placed into TYPE5 product categories in "FM3 Family Peripheral Manual".

Features

32-bit ARM^®Cortex^®-M3 Core

Processor version: r2p1

Multi-function Serial Interface (Max 4 channels)

2 channels with 16-steps × 9-bits FIFO (ch.0, ch.1),

2 channels without FIFO (ch.3, ch.5)

Up to 40 MHz Frequency Operation

Operation mode is selectable from the followings for each

channel.

(In ch.5, only UART and LIN are available.)

 UART

 CSIO

 LIN

 I²C

Integrated Nested Vectored Interrupt Controller (NVIC): 1

NMI (non-maskable interrupt) and 48 peripheral interrupts

and 16 priority levels

24-bit System timer (Sys Tick): System timer for OS task

management

On-chip Memories

[UART]

[Flash memory]

This Series are based on two independent on-chip Flash

memories.

Full-duplex double buffer

Selection with or without parity supported

Built-in dedicated baud rate generator

External clock available as a serial clock

MainFlash

 Up to 128 KB

 Read cycle: 0 wait-cycle

 Security function for code protection

Hardware Flow control: Automatically control the

transmission by CTS/RTS (only ch.4)

WorkFlash

 32 KB

 Read cycle: 0 wait-cycle

 Security function is shared with code protection

Various error detect functions available (parity errors,

framing errors, and overrun errors)

[CSIO]

[SRAM]

Full-duplex double buffer

Built-in dedicated baud rate generator

Overrun error detect function available

This Series contain a total of up to 16 KB on-chip SRAM. This

is composed of two independent SRAM (SRAM0, SRAM1).

SRAM0 is connected to I-code bus and D-code bus of Cortex-

M3 core. SRAM1 is connected to System bus.

SRAM0: 8 KB

SRAM1: 8 KB

Cypress Semiconductor Corporation

Document Number: 002-05627 Rev. *B

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised March 22, 2017

MB9A110K Series

[LIN]

General Purpose I/O Port

This series can use its pins as General Purpose I/O ports

when they are not used for external bus or peripherals.

Moreover, the port relocate function is built in. It can set which

I/O port the peripheral function can be allocated.

LIN protocol Rev.2.1 supported

Full-duplex double buffer

Master/Slave mode supported

Capable of pull-up control per pin

Capable of reading pin level directly

Built-in the port relocate function

Up 36 fast General Purpose I/O Ports

LIN break field generate (can be changed 13 to 16-bit

length)

LIN break delimiter generate (can be changed 1 to 4-bit

length)

Various error detect functions available (parity errors,

framing errors, and overrun errors)

Some pin is 5 V tolerant I/O.

See "Pin Description" to confirm the corresponding pins.

[I²C]

Standard mode (Max 100 kbps) / Fast-mode (Max 400 kbps)

supported

Multi-function Timer

The Multi-function timer is composed of the following blocks.

16-bit free-run timer × 3 ch.

Input capture × 4 ch.

DMA Controller (4 channels)

DMA Controller has an independent bus for CPU, so CPU and

DMA Controller can process simultaneously.

Output compare × 6 ch.

A/D activating compare × 3 ch.

Waveform generator × 3 ch.

16-bit PPG timer × 3 ch.

8 independently configured and operated channels

Transfer can be started by software or request from the built-

in peripherals

Transfer address area: 32-bit (4 GB)

Transfer mode: Block transfer/Burst transfer/Demand

transfer

The following function can be used to achieve the motor

control.

Transfer data type: byte/half-word/word

Transfer block count: 1 to 16

PWM signal output function

DC chopper waveform output function

Dead time function

Number of transfers: 1 to 65536

Input capture function

A/D Converter (Max 8 channels)

[12-bit A/D Converter]

A/D convertor activate function

DTIF (Motor emergency stop) interrupt function

Successive Approximation Register type

Built-in 2 unit

Real-time clock (RTC)

The Real-time clock can count

Year/Month/Day/Hour/Minute/Second/A day of the week from

00 to 99.

Conversion time: 1.0 μs @ 5 V

Priority conversion available (priority at 2 levels)

Scanning conversion mode

Interrupt function with specifying date and time

(Year/Month/Day/Hour/Minute) is available. This function is

also available by specifying only Year, Month, Day, Hour or

Minute.

Built-in FIFO for conversion data storage

(for SCAN conversion: 16 steps, for Priority conversion:

4 steps)

Timer interrupt function after set time or each set time.

Capable of rewriting the time with continuing the time count.

Leap year automatic count is available.

Base Timer (Max 8 channels)

Operation mode is selectable from the followings for each

channel.

16-bit PWM timer

16-bit PPG timer

16-/32-bit reload timer

16-/32-bit PWC timer

Document Number: 002-05627 Rev. *B

Page 2 of 81

MB9A110K Series

Quadrature Position/Revolution Counter (QPRC)

The Quadrature Position/Revolution Counter (QPRC) is used

to measure the position of the position encoder. Moreover, it is

possible to use up/down counter.

Clock and Reset

[Clocks]

Five clock sources (2 external oscillators, 2 internal CR

oscillator, and Main PLL) that are dynamically selectable.

The detection edge of the three external event input pins

Main Clock:

Sub Clock:

4 MHz to 48 MHz

32.768 kHz

AIN, BIN and ZIN is configurable.

16-bit position counter

High-speed internal CR Clock:4 MHz

Low-speed internal CR Clock: 100 kHz

Main PLL Clock

16-bit revolution counter

Two 16-bit compare registers

Dual Timer (32/16-bit Down Counter)

The Dual Timer consists of two programmable 32/16-bit down

counters.

Operation mode is selectable from the followings for each

channel.

[Resets]

Reset requests from INITX pin

Power on reset

Software reset

Free-running

Periodic (=Reload)

One-shot

Watchdog timers reset

Low-voltage detector reset

Clock supervisor reset

Watch Counter

The Watch counter is used for wake up from Low Power

Consumption mode.

Clock Super Visor (CSV)

Clocks generated by internal CR oscillators are used to

supervise abnormality of the external clocks.

Interval timer: up to 64 s (Max) @ Sub Clock: 32.768 kHz

External OSC clock failure (clock stop) is detected, reset is

External Interrupt Controller Unit

Up to 6 external interrupt input pin

Include one non-maskable interrupt (NMI)

asserted.

External OSC frequency anomaly is detected, interrupt or

reset is asserted.

Low-Voltage Detector (LVD)

Watchdog Timer (2 channels)

A watchdog timer can generate interrupts or a reset when a

time-out value is reached.

This Series include 2-stage monitoring of voltage on the VCC

pins. When the voltage falls below the voltage has been set,

Low-Voltage Detector generates an interrupt or reset.

This series consists of two different watchdogs, a "Hardware"

watchdog and a "Software" watchdog.

LVD1: error reporting via interrupt

LVD2: auto-reset operation

"Hardware" watchdog timer is clocked by low-speed internal

CR oscillator. Therefore, ”Hardware" watchdog is active in any

power saving mode except RTC and STOP and Deep stand-

by RTC and Deep stand-by STOP.

Low Power Consumption Mode

Six Low Power Consumption modes supported.

SLEEP

CRC (Cyclic Redundancy Check) Accelerator

The CRC accelerator helps a verify data transmission or

storage integrity.

TIMER

RTC

CCITT CRC16 and IEEE-802.3 CRC32 are supported.

CCITT CRC16 Generator Polynomial: 0x1021

STOP

Deep stand-by RTC

Deep stand-by STOP

IEEE-802.3 CRC32 Generator Polynomial: 0x04C11DB7

Debug

Serial Wire JTAG Debug Port (SWJ-DP)

Power Supply

Wide range voltage: VCC = 2.7 V to 5.5 V

Document Number: 002-05627 Rev. *B

Page 3 of 81

MB9A110K Series

Contents

1. Product Lineup.................................................................................................................................................................. 6

2. Packages ........................................................................................................................................................................... 7

3. Pin Assignment................................................................................................................................................................. 8

4. List of Pin Functions....................................................................................................................................................... 11

5. I/O Circuit Type................................................................................................................................................................ 21

6. Handling Precautions ..................................................................................................................................................... 26

6.1

6.2

6.3

Precautions for Product Design................................................................................................................................... 26

Precautions for Package Mounting.............................................................................................................................. 27

Precautions for Use Environment................................................................................................................................ 28

7. Handling Devices ............................................................................................................................................................ 29

8. Block Diagram................................................................................................................................................................. 31

9. Memory Size.................................................................................................................................................................... 31

10. Memory Map .................................................................................................................................................................... 32

11. Pin Status in Each CPU State ........................................................................................................................................ 35

12. Electrical Characteristics ............................................................................................................................................... 40

12.1 Absolute Maximum Ratings......................................................................................................................................... 40

12.2 Recommended Operating Conditions.......................................................................................................................... 42

12.3 DC Characteristics....................................................................................................................................................... 43

12.3.1Current Rating.............................................................................................................................................................. 43

12.3.2 Pin Characteristics ....................................................................................................................................................... 46

12.4 AC Characteristics....................................................................................................................................................... 47

12.4.1 Main Clock Input Characteristics.................................................................................................................................. 47

12.4.2 Sub Clock Input Characteristics ................................................................................................................................... 48

12.4.3 Internal CR Oscillation Characteristics......................................................................................................................... 48

12.4.4 Operating Conditions of Main PLL (In the case of using main clock for input of PLL).................................................. 49

12.4.5 Operating Conditions of Main PLL (In the case of using high-speed internal CR)........................................................ 49

12.4.6 Reset Input Characteristics .......................................................................................................................................... 50

12.4.7 Power-on Reset Timing................................................................................................................................................ 50

12.4.8 Base Timer Input Timing.............................................................................................................................................. 51

12.4.9 CSIO/UART Timing...................................................................................................................................................... 52

12.4.10 External Input Timing................................................................................................................................................ 60

12.4.11 Quadrature Position/Revolution Counter timing........................................................................................................ 61

12.4.12 I²C Timing................................................................................................................................................................. 63

12.4.13 JTAG Timing............................................................................................................................................................. 64

12.5 12-bit A/D Converter.................................................................................................................................................... 65

12.6 Low-Voltage Detection Characteristics........................................................................................................................ 68

12.6.1 Low-Voltage Detection Reset....................................................................................................................................... 68

12.6.2 Interrupt of Low-voltage Detection ............................................................................................................................... 68

12.7 MainFlash Memory Write/Erase Characteristics.......................................................................................................... 69

12.7.1 Write / Erase time......................................................................................................................................................... 69

12.7.2 Erase/write cycles and data hold time.......................................................................................................................... 69

12.8 WorkFlash Memory Write/Erase Characteristics......................................................................................................... 69

12.8.1 Write / Erase time......................................................................................................................................................... 69

12.8.2 Erase/write cycles and data hold time.......................................................................................................................... 69

12.9 Return Time from Low-Power Consumption Mode...................................................................................................... 70

12.9.1 Return Factor: Interrupt/WKUP .................................................................................................................................... 70

12.9.2 Return Factor: Reset.................................................................................................................................................... 72

Document Number: 002-05627 Rev. *B

Page 4 of 81

MB9A110K Series

13. Ordering Information ...................................................................................................................................................... 74

14. Package Dimensions ...................................................................................................................................................... 75

15. Major Changes ................................................................................................................................................................ 78

Document History................................................................................................................................................................. 80

Sales, Solutions, and Legal Information............................................................................................................................. 81

Document Number: 002-05627 Rev. *B

Page 5 of 81

MB9A110K Series

1. Product Lineup

Memory Size

Product name

MB9AF111K

64 KB

MB9AF112K

128 KB

32 KB

MainFlash

WorkFlash

SRAM0

SRAM1

Total

On-chip

Flash memory

32 KB

8 KB

On-chip SRAM

8 KB

16 KB

Function

MB9AF111K

MB9AF112K

Product name

Pin count

CPU

48/52

Cortex-M3

40 MHz

Freq.

Power supply voltage range

DMAC

2.7 V to 5.5 V

4 ch. (Max)

Multi-function Serial Interface

(UART/CSIO/LIN/I²C)

with 16-steps × 9-bits FIFO: ch.0, ch.1

without FIFO: ch.3, ch.5 (In ch.5, only UART and LIN are available.)

Base Timer

(PWC/ Reload timer/PWM/PPG)

8 ch. (Max)

A/D activation

compare

3 ch.

Input capture

Free-run timer

Output

compare

Waveform

generator

PPG

4 ch.

3 ch.

MF-

Timer

1 unit (Max)

6 ch.

3 ch.

QPRC

1 ch. (Max)

Dual Timer

Real-time clock

1 unit

Watch Counter

1 unit

CRC Accelerator

Yes

Watchdog timer

1 ch. (SW) + 1 ch. (HW)

6 pins (Max) + NMI × 1

36 pins (Max)

8 ch. (2 units)

Yes

External Interrupts

General Purpose I/O ports

12-bit A/D converter

CSV (Clock Super Visor)

LVD (Low-Voltage Detector)

2 ch.

High-speed

Built-in OSC

4 MHz

100 kHz

Low-speed

Debug Function

SWJ-DP

Note:

−

All signals of the peripheral function in each product cannot be allocated by limiting the pins of package.

It is necessary to use the port relocate function of the General I/O port according to your function use.

See “12. Electrical Characteristics 12.4. AC Characteristics 12.4.3. Internal CR Oscillation Characteristics” for accuracy of

built-in CR.

Document Number: 002-05627 Rev. *B

Page 6 of 81

MB9A110K Series

2. Packages

Product name

MB9AF111K

MB9AF112K

Package

LQFP: LQA048 (0.5 mm pitch)

QFN: VNA048 (0.5 mm pitch)

LQFP: LQC052 (0.65 mm pitch)



: Supported

Note:

−

See “14. Package Dimensions” for detailed information on each package.

Document Number: 002-05627 Rev. *B

Page 7 of 81

MB9A110K Series

3. Pin Assignment

LQA048

(TOP VIEW)

VCC

1

2

3

4

5

6

7

8

9

36 P21/SIN0_0/INT06_1/WKUP2

P50/INT00_0/AIN0_2/SIN3_1

P51/INT01_0/BIN0_2/SOT3_1

P52/INT02_0/ZIN0_2/SCK3_1

P39/DTTI0X_0/ADTG_2

35 P22/AN07/SOT0_0/TIOB7_1

34 P23/AN06/SCK0_0/TIOA7_1

33 AVSS

32 AVRH

P3A/RTO00_0/TIOA0_1/RTCCO_2/SUBOUT_2

P3B/RTO01_0/TIOA1_1

31 AVCC

LQFP - 48

30 P15/AN05/SOT0_1/IC03_2

29 P14/AN04/SIN0_1/INT03_1/IC02_2

28 P13/AN03/SCK1_1/IC01_2/RTCCO_1/SUBOUT_1

27 P12/AN02/SOT1_1/IC00_2

26 P11/AN01/SIN1_1/INT02_1/FRCK0_2/IC02_0/WKUP1

25 P10/AN00

P3C/RTO02_0/TIOA2_1

P3D/RTO03_0/TIOA3_1

P3E/RTO04_0/TIOA4_1 10

P3F/RTO05_0/TIOA5_1 11

VSS 12

Note:

−

The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For

these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function

register (EPFR) to select the pin.

Document Number: 002-05627 Rev. *B

Page 8 of 81

MB9A110K Series

VNA048

(TOP VIEW)

VCC

P50/INT00_0/AIN0_2/SIN3_1

P51/INT01_0/BIN0_2/SOT3_1

P52/INT02_0/ZIN0_2/SCK3_1

P39/DTTI0X_0/ADTG_2

1

2

3

4

5

6

7

8

9

36 P21/SIN0_0/INT06_1/WKUP2

35 P22/AN07/SOT0_0/TIOB7_1

34 P23/AN06/SCK0_0/TIOA7_1

33 AVSS

32 AVRH

P3A/RTO00_0/TIOA0_1/RTCCO_2/SUBOUT_2

P3B/RTO01_0/TIOA1_1

31 AVCC

QFN - 48

30 P15/AN05/SOT0_1/IC03_2

29 P14/AN04/SIN0_1/INT03_1/IC02_2

28 P13/AN03/SCK1_1/IC01_2/RTCCO_1/SUBOUT_1

27 P12/AN02/SOT1_1/IC00_2

26 P11/AN01/SIN1_1/INT02_1/FRCK0_2/IC02_0/WKUP1

25 P10/AN00

P3C/RTO02_0/TIOA2_1

P3D/RTO03_0/TIOA3_1

P3E/RTO04_0/TIOA4_1 10

P3F/RTO05_0/TIOA5_1 11

VSS 12

Note:

−

The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For

these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function

register (EPFR) to select the pin.

Document Number: 002-05627 Rev. *B

Page 9 of 81

MB9A110K Series

LQC052

(TOP VIEW)

VCC

P50/INT00_0/AIN0_2/SIN3_1

P51/INT01_0/BIN0_2/SOT3_1

P52/INT02_0/ZIN0_2/SCK3_1

NC

1

2

3

4

5

6

7

8

9

39 P21/SIN0_0/INT06_1/WKUP2

38 P22/AN07/SOT0_0/TIOB7_1

37 P23/AN06/SCK0_0/TIOA7_1

36 NC

35 AVSS

P39/DTTI0X_0/ADTG_2

34 AVRH

P3A/RTO00_0/TIOA0_1/RTCCO_2/SUBOUT_2

P3B/RTO01_0/TIOA1_1

33 AVCC

LQFP - 52

32 P15/AN05/SOT0_1/IC03_2

31 P14/AN04/SIN0_1/INT03_1/IC02_2

30 P13/AN03/SCK1_1/IC01_2/RTCCO_1/SUBOUT_1

29 P12/AN02/SOT1_1/IC00_2

28 P11/AN01/SIN1_1/INT02_1/FRCK0_2/IC02_0/WKUP1

27 P10/AN00

P3C/RTO02_0/TIOA2_1

P3D/RTO03_0/TIOA3_1 10

P3E/RTO04_0/TIOA4_1 11

P3F/RTO05_0/TIOA5_1 12

VSS 13

Note:

−

The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For

these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function

register (EPFR) to select the pin.

Document Number: 002-05627 Rev. *B

Page 10 of 81

MB9A110K Series

4. List of Pin Functions

List of pin numbers

The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these

pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR)

to select the pin.

Pin No

I/O circuit

type

Pin state

type

Pin Name

LQFP-48

QFN-48

LQFP-52

1

VCC

-

P50

INT00_0

AIN0_2

SIN3_1

P51

I^*1

2

3

4

H

INT01_0

BIN0_2

SOT3_1

P52

3

4

INT02_0

ZIN0_2

SCK3_1

NC

-

5

6

-

P39

5

DTTI0X_0

ADTG_2

P3A

E

I

RTO00_0

TIOA0_1

RTCCO_2

SUBOUT_2

P3B

6

7

G

7

8

9

RTO01_0

TIOA1_1

P3C

G

I

RTO02_0

TIOA2_1

P3D

9

10

11

RTO03_0

TIOA3_1

P3E

10

RTO04_0

TIOA4_1

Document Number: 002-05627 Rev. *B

Page 11 of 81

MB9A110K Series

Pin No

I/O circuit

type

Pin state

type

Pin Name

LQFP-48

QFN-48

LQFP-52

P3F

11

12

RTO05_0

TIOA5_1

VSS

G

I

12

13

14

13

14

15

-

C

VCC

P46

15

16

D

M

X0A

P47

16

17

18

17

18

19

D

B

E

N

C

I

X1A

INITX

P49

TIOB0_0

P4A

19

-

20

21

22

23

24

E

I

TIOB1_0

NC

-

PE0

20

21

22

C

J

P

D

A

MD1

MD0

PE2

A

X0

PE3

23

24

25

26

27

A

F

B

K

X1

VSS

-

P10

AN00

P11

AN01

SIN1_1

INT02_1

FRCK0_2

IC02_0

WKUP1

P12

26

27

28

29

F

K

AN02

SOT1_1

IC00_2

Document Number: 002-05627 Rev. *B

Page 12 of 81

MB9A110K Series

Pin No

I/O circuit

type

Pin state

type

Pin Name

LQFP-48

QFN-48

LQFP-52

P13

AN03

SCK1_1

IC01_2

RTCCO_1

SUBOUT_1

P14

28

30

F

K

AN04

29

30

31

32

SIN0_1

INT03_1

IC02_2

F

L

P15

AN05

SOT0_1

IC03_2

AVCC

AVRH

AVSS

NC

K

31

32

33

-

33

34

35

36

-

P23

AN06

SCK0_0

TIOA7_1

P22

34

35

36

37

38

39

F

E

K

G

AN07

SOT0_0

TIOB7_1

P21

SIN0_0

INT06_1

WKUP2

NC

-

40

41

-

P00

37

E

TRSTX

P01

38

39

40

42

43

44

TCK

SWCLK

P02

E

TDI

P03

TMS

SWDIO

P04

41

45

TDO

SWO

E

Document Number: 002-05627 Rev. *B

Page 13 of 81

MB9A110K Series

Pin No

I/O circuit

type

Pin state

type

Pin Name

LQFP-48

QFN-48

LQFP-52

P0F

NMIX

CROUT_1

RTCCO_0

SUBOUT_0

WKUP0

P61

42

43

44

46

E

J

I

SOT5_0

TIOB2_2

UHCONX

DTTI0X_2

P60

47

48

SIN5_0

TIOA2_2

INT15_1

IC00_0

WKUP3

VCC

I^[1]

G

45

46

47

48

49

50

51

52

-

P80

H

O

P81

VSS

*1: 5 V tolerant I/O

Document Number: 002-05627 Rev. *B

Page 14 of 81

MB9A110K Series

List of pin functions

The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these

pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR)

to select the pin.

Pin No

Module

Pin name

ADTG_2

Function

LQFP-48

QFN-48

LQFP-52

ADC

A/D converter external trigger input pin

5

6

AN00

25

26

27

28

29

30

34

35

6

18

7

19

8

27

28

29

30

31

32

37

38

7

19

8

20

9

AN01

AN02

AN03

A/D converter analog input pin.

ANxx describes ADC ch.xx.

AN04

AN05

AN06

AN07

Base Timer

0

TIOA0_1

TIOB0_0

TIOA1_1

TIOB1_0

TIOA2_1

TIOA2_2

TIOB2_2

Base timer ch.0 TIOA pin

Base timer ch.0 TIOB pin

Base timer ch.1 TIOA pin

Base timer ch.1 TIOB pin

Base Timer

1

Base Timer

2

Base timer ch.2 TIOA pin

Base timer ch.2 TIOB pin

Base timer ch.3 TIOA pin

44

43

48

47

Base Timer

3

TIOA3_1

TIOA4_1

TIOA5_1

9

10

11

12

Base Timer

4

Base timer ch.4 TIOA pin

Base timer ch.5 TIOA pin

10

11

Base Timer

5

Base Timer

7

TIOA7_1

TIOB7_1

SWCLK

SWDIO

SWO

Base timer ch.7 TIOA pin

34

35

38

40

41

38

39

41

40

37

2

37

38

42

44

45

42

43

45

44

41

2

Base timer ch.7 TIOB pin

Debugger

Serial wire debug interface clock input pin

Serial wire debug interface data input/output pin

Serial wire viewer output pin

TCK

JTAG test clock input pin

TDI

JTAG test data input pin

TDO

JTAG debug data output pin

TMS

JTAG test mode state input/output pin

JTAG test reset Input pin

TRSTX

INT00_0

INT01_0

INT02_0

INT02_1

INT03_1

INT06_1

INT15_1

NMIX

External

Interrupt

External interrupt request 00 input pin

External interrupt request 01 input pin

3

4

3

4

External interrupt request 02 input pin

26

29

36

44

42

28

31

39

48

46

External interrupt request 03 input pin

External interrupt request 06 input pin

External interrupt request 15 input pin

Non-Maskable Interrupt input pin

Document Number: 002-05627 Rev. *B

Page 15 of 81

MB9A110K Series

Pin No

Module

GPIO

Pin name

Function

LQFP-48

LQFP-52

QFN-48

37

38

39

40

41

42

25

26

27

28

29

30

36

35

34

5

P00

P01

P02

P03

P04

P0F

P10

P11

P12

P13

P14

P15

P21

P22

P23

P39

P3A

P3B

P3C

P3D

P3E

P3F

P46

P47

P49

P4A

P50

P51

P52

P60

P61

P80

P81

PE0

PE2

PE3

41

42

43

44

45

46

27

28

29

30

31

32

39

38

37

6

General-purpose I/O port 0

General-purpose I/O port 1

General-purpose I/O port 2

6

7

8

9

10

11

15

16

18

19

2

7

8

9

General-purpose I/O port 3

10

11

12

16

17

19

20

2

General-purpose I/O port 4

General-purpose I/O port 5

3

4

3

4

44

43

46

47

20

22

23

48

47

50

51

22

24

25

General-purpose I/O port 6

General-purpose I/O port 8

General-purpose I/O port E

Document Number: 002-05627 Rev. *B

Page 16 of 81

MB9A110K Series

Pin No.

Module

Pin name

Function

LQFP-48

QFN-48

LQFP-52

Multi- function

Serial

0

SIN0_0

SIN0_1

36

29

39

31

Multi-function serial interface ch.0 input pin

SOT0_0

(SDA0_0)

Multi-function serial interface ch.0 output pin.

This pin operates as SOT0 when it is used in a

UART/CSIO/LIN (operation modes

35

30

38

32

0 to 3) and as SDA0 when it is used in an I²C (operation

mode 4).

SOT0_1

(SDA0_1)

Multi-function serial interface ch.0 clock I/O pin.

This pin operates as SCK0 when it is used in a CSIO

(operation modes 2) and as SCL0 when it is used in an

I²C (operation mode 4).

SCK0_0

(SCL0_0)

34

26

37

28

Multi- function

Serial

1

SIN1_1

Multi-function serial interface ch.1 input pin

Multi-function serial interface ch.1 output pin.

This pin operates as SOT1 when it is used in a

UART/CSIO/LIN (operation modes

SOT1_1

(SDA1_1)

27

29

0 to 3) and as SDA1 when it is used in an I²C (operation

mode 4).

Multi-function serial interface ch.1 clock I/O pin.

This pin operates as SCK1 when it is used in a CSIO

(operation modes 2) and as SCL1 when it is used in an

I²C (operation mode 4).

SCK1_1

(SCL1_1)

28

2

30

2

Multi- function

Serial

3

SIN3_1

Multi-function serial interface ch.3 input pin

Multi-function serial interface ch.3 output pin.

This pin operates as SOT3 when it is used in a

UART/CSIO/LIN (operation modes

SOT3_1

(SDA3_1)

3

0 to 3) and as SDA3 when it is used in an I²C (operation

mode 4).

Multi-function serial interface ch.3 clock I/O pin.

This pin operates as SCK3 when it is used in a CSIO

(operation modes 2) and as SCL3 when it is used in an

I²C (operation mode 4).

SCK3_1

(SCL3_1)

4

Multi- function

Serial

5

SIN5_0

Multi-function serial interface ch.5 input pin

Multi-function serial interface ch.5 output pin.

This pin operates as SOT5 when it is used in a

UART/LIN (operation modes 0, 1, 3).

44

43

48

47

SOT5_0

Document Number: 002-05627 Rev. *B

Page 17 of 81

MB9A110K Series

Pin No

Module

Pin name

DTTI0X_0

Function

LQFP-48

QFN-48

LQFP-52

Multi- function

Timer

0

5

6

Input signal controlling wave form generator outputs

RTO00 to RTO05 of multi-function timer 0.

DTTI0X_2

FRCK0_2

IC00_0

43

26

44

27

28

26

29

30

47

28

48

29

30

28

31

32

16-bit free-run timer ch.0 external clock input pin

IC00_2

IC01_2

IC02_0

IC02_2

IC03_2

16-bit input capture ch.0 input pin of multi-function

timer 0.

ICxx describes channel number.

Wave form generator output pin of multi-function timer

RTO00_0

(PPG00_0)

0.

6

7

8

This pin operates as PPG00 when it is used in PPG0

output modes.

Wave form generator output pin of multi-function timer

0.

RTO01_0

(PPG00_0)

This pin operates as PPG00 when it is used in PPG0

output modes.

Wave form generator output pin of multi-function timer

RTO02_0

(PPG02_0)

0.

8

9

This pin operates as PPG02 when it is used in PPG0

output modes.

Wave form generator output pin of multi-function timer

RTO03_0

(PPG02_0)

0.

9

10

11

12

This pin operates as PPG02 when it is used in PPG0

output modes.

Wave form generator output pin of multi-function timer

0.

This pin operates as PPG04 when it is used in PPG0

output modes.

Wave form generator output pin of multi-function timer

0.

RTO04_0

(PPG04_0)

10

11

RTO05_0

(PPG04_0)

This pin operates as PPG04 when it is used in PPG0

output modes.

Document Number: 002-05627 Rev. *B

Page 18 of 81

MB9A110K Series

Pin No

Module

Quadrature

Position/

Revolution

Counter

0

Pin name

Function

QPRC ch.0 AIN input pin

LQFP-48

QFN-48

LQFP-52

AIN0_2

BIN0_2

ZIN0_2

2

3

4

QPRC ch.0 BIN input pin

QPRC ch.0 ZIN input pin

3

4

Real-time clock

RTCCO_0

RTCCO_1

RTCCO_2

SUBOUT_0

SUBOUT_1

SUBOUT_2

WKUP0

42

28

6

46

30

7

0.5 seconds pulse output pin of Real-time clock pin

Sub clock output pin

42

28

6

46

30

7

Low Power

Consumption

Mode

Deep stand-by mode return signal input pin 0

Deep stand-by mode return signal input pin 1

Deep stand-by mode return signal input pin 2

Deep stand-by mode return signal input pin 3

42

26

36

44

46

28

39

48

WKUP1

WKUP2

WKUP3

Document Number: 002-05627 Rev. *B

Page 19 of 81

MB9A110K Series

Pin No

Module

Reset

Pin name

Function

LQFP-48

QFN-48

LQFP-52

External Reset Input.

INITX

MD0

17

18

23

A reset is valid when INITX="L".

Mode 0 pin.

During normal operation, MD0="L" must be input.

During serial programming to Flash memory, MD0="H"

must be input.

Mode

21

20

Mode 1 pin.

MD1

During serial programming to Flash memory, MD1="L"

must be input.

22

Power

GND

VCC

VSS

X0

X0A

X1

X1A

Power supply Pin

GND Pin

Main clock (oscillation) input pin

Sub clock (oscillation) input pin

Main clock (oscillation) I/O pin

Sub clock (oscillation) I/O pin

1

14

45

12

24

48

22

15

23

16

15

49

13

26

52

24

16

25

17

Clock

CROUT_1

Built-in high-speed CR-osc clock output port

42

46

Analog

Power

AVCC

A/D converter analog power pin

31

33

AVRH

A/D converter analog reference voltage input pin

32

34

Analog

GND

C pin

AVSS

C

A/D converter GND pin

33

13

35

14

Power stabilization capacity pin

NC pin

NC pin.

NC pin should be kept open.

NC

-

5

NC pin.

NC pin should be kept open.

21

36

40

NC pin.

NC pin should be kept open.

NC pin.

NC pin should be kept open.

Note:

−

While this device contains a Test Access Port (TAP) based on the IEEE 1149.1-2001 JTAG standard, it is not fully compliant

to all requirements of that standard. This device may contain a 32-bit device ID that is the same as the 32-bit device ID in

other devices with different functionality. The TAP pins may also be configurable for purposes other than access to the TAP

controller.

Document Number: 002-05627 Rev. *B

Page 20 of 81

MB9A110K Series

5. I/O Circuit Type

Type

Circuit

Remarks

A

It is possible to select the main

oscillation / GPIO function

Pull-up

resistor

When the main oscillation is

selected.

P-ch

Digital output

−

Oscillation feedback resistor

: Approximately 1 MΩ

X1

−

With Standby mode control

When the GPIO is selected.

N-ch

−

CMOS level output.

R

CMOS level hysteresis input

With pull-up resistor control

With standby mode control

Pull-up resistor

Pull-up resistor control

Digital input

: Approximately 50 kΩ

I_OH= -4 mA, I_OL= 4 mA

−

Standby mode Control

Clock input

Feedback

resistor

Standby mode Control

Digital input

Standby mode Control

Pull-up

resistor

R

Digital output

P-ch

N-ch

P-ch

X0

Digital output

Pull-up resistor control

B

−

CMOS level hysteresis input

Pull-up resistor

: Approximately 50 kΩ

Pull-up resistor

Digital input

Document Number: 002-05627 Rev. *B

Page 21 of 81

MB9A110K Series

Type

Circuit

Remarks

C

−

Open drain output

−

CMOS level hysteresis input

Digital input

Digital output

N-ch

D

It is possible to select the sub

oscillation / GPIO function

Pull-up

resistor

When the sub oscillation is

selected.

P-ch

Digital output

−

Oscillation feedback resistor

: Approximately 5 MΩ

X1A

−

With Standby mode control

When the GPIO is selected.

N-ch

Digital output

−

CMOS level output.

R

CMOS level hysteresis input

With pull-up resistor control

With standby mode control

Pull-up resistor

Pull-up resistor control

Digital input

: Approximately 50 kΩ

I_OH= -4 mA, I_OL= 4 mA

−

Standby mode Control

Clock input

Feedback

resistor

Standby mode Control

Digital input

Standby mode Control

Pull-up

resistor

R

Digital output

P-ch

N-ch

X0A

Digital output

Pull-up resistor control

Document Number: 002-05627 Rev. *B

Page 22 of 81

MB9A110K Series

Type

Circuit

Remarks

E

−

CMOS level output

−

CMOS level hysteresis input

With pull-up resistor control

With standby mode control

Pull-up resistor

P-ch

Digital output

: Approximately 50 kΩ

I_OH= -4 mA, I_OL= 4 mA

When this pin is used as an I²C

pin, the digital output

−

P-ch transistor is always off

+B input is available

N-ch

−

R

Pull-up resistor control

Digital input

Standby mode Control

F

−

CMOS level output

CMOS level hysteresis input

With input control

Analog input

With pull-up resistor control

With standby mode control

Pull-up resistor

Digital output

P-ch

: Approximately 50 kΩ

I_OH= -4 mA, I_OL= 4 mA

When this pin is used as an I²C

pin, the digital output

P-ch transistor is always off

+B input is available

−

N-ch

−

Pull-up resistor control

Digital input

R

Standby mode Control

Analog input

Input control

Document Number: 002-05627 Rev. *B

Page 23 of 81

MB9A110K Series

Type

Circuit

Remarks

G

−

CMOS level output

−

CMOS level hysteresis input

With pull-up resistor control

With standby mode control

Pull-up resistor

: Approximately 50 kΩ

I_OH= -12 mA, I_OL= 12 mA

+B input is available

P-ch

Digital output

−

N-ch

R

Pull-up resistor control

Digital input

Standby mode Control

H

−

CMOS level output

CMOS level hysteresis input

With standby mode control

I_OH= -20.5 mA, I_OL= 18.5 mA

P-ch

Digital output

N-ch

R

Digital input

Standby mode Control

Document Number: 002-05627 Rev. *B

Page 24 of 81

MB9A110K Series

Type

Circuit

Remarks

I

−

CMOS level output

−

CMOS level hysteresis input

5 V tolerant

With pull-up resistor control

With standby mode control

Pull-up resistor

P-ch

Digital output

: Approximately 50 kΩ

I_OH= -4 mA, I_OL= 4 mA

Available to control of PZR registers.

−

N-ch

R

Pull-up resistor control

Digital input

Standby mode Control

J

CMOS level hysteresis input

Mode input

Document Number: 002-05627 Rev. *B

Page 25 of 81

MB9A110K Series

6. Handling Precautions

Any semiconductor devices have inherently a certain rate of failure. The possibility of failure is greatly affected by the conditions in

which they are used (circuit conditions, environmental conditions, etc.). This page describes precautions that must be observed to

minimize the chance of failure and to obtain higher reliability from your Cypress semiconductor devices.

6.1 Precautions for Product Design

This section describes precautions when designing electronic equipment using semiconductor devices.

Absolute maximum ratings

Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of

certain established limits, called absolute maximum ratings. Do not exceed these ratings.

Recommended operating conditions

Recommended operating conditions are normal operating ranges for the semiconductor device. All the device's electrical

characteristics are warranted when operated within these ranges.

Always use semiconductor devices within the recommended operating conditions. Operation outside these ranges may adversely

affect reliability and could result in device failure.

No warranty is made with respect to uses, operating conditions, or combinations not represented on the datasheet. Users

considering application outside the listed conditions are advised to contact their sales representative beforehand.

Processing and protection of pins

These precautions must be followed when handling the pins which connect semiconductor devices to power supply and

input/output functions.

1. Preventing Over-Voltage and Over-Current Conditions

Exposure to voltage or current levels in excess of maximum ratings at any pin is likely to cause deterioration within the device,

and in extreme cases leads to permanent damage of the device. Try to prevent such overvoltage or over-current conditions at

the design stage.

2. Protection of Output Pins

Shorting of output pins to supply pins or other output pins, or connection to large capacitance can cause large current flows.

Such conditions if present for extended periods of time can damage the device.

Therefore, avoid this type of connection.

3. Handling of Unused Input Pins

Unconnected input pins with very high impedance levels can adversely affect stability of operation. Such pins should be

connected through an appropriate resistance to a power supply pin or ground pin.

Latch-up

Semiconductor devices are constructed by the formation of P-type and N-type areas on a substrate. When subjected to abnormally

high voltages, internal parasitic PNPN junctions (called thyristor structures) may be formed, causing large current levels in excess

of several hundred mA to flow continuously at the power supply pin. This condition is called latch-up.

CAUTION: The occurrence of latch-up not only causes loss of reliability in the semiconductor device, but can cause injury or

damage from high heat, smoke or flame. To prevent this from happening, do the following:

1. Be sure that voltages applied to pins do not exceed the absolute maximum ratings. This should include attention to abnormal

noise, surge levels, etc.

2. Be sure that abnormal current flows do not occur during the power-on sequence.

Observance of safety regulations and standards

Most countries in the world have established standards and regulations regarding safety, protection from electromagnetic

interference, etc. Customers are requested to observe applicable regulations and standards in the design of products.

Fail-safe design

Any semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage or loss from such

failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and

prevention of over-current levels and other abnormal operating conditions.

Document Number: 002-05627 Rev. *B

Page 26 of 81

MB9A110K Series

Precautions related to usage of devices

Cypress semiconductor devices are intended for use in standard applications (computers, office automation and other office

equipment, industrial, communications, and measurement equipment, personal or household devices, etc.).

CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly

affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as

aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.)

are requested to consult with sales representatives before such use. The company will not be responsible for damages arising

from such use without prior approval.

6.2 Precautions for Package Mounting

Package mounting may be either lead insertion type or surface mount type. In either case, for heat resistance during soldering, you

should only mount under Cypress recommended conditions. For detailed information about mount conditions, contact your sales

representative.

Lead insertion type

Mounting of lead insertion type packages onto printed circuit boards may be done by two methods: direct soldering on the board,

or mounting by using a socket.

Direct mounting onto boards normally involves processes for inserting leads into through-holes on the board and using the flow

soldering (wave soldering) method of applying liquid solder. In this case, the soldering process usually causes leads to be

subjected to thermal stress in excess of the absolute ratings for storage temperature. Mounting processes should conform to

Cypress recommended mounting conditions.

If socket mounting is used, differences in surface treatment of the socket contacts and IC lead surfaces can lead to contact

deterioration after long periods. For this reason it is recommended that the surface treatment of socket contacts and IC leads be

verified before mounting.

Surface mount type

Surface mount packaging has longer and thinner leads than lead-insertion packaging, and therefore leads are more easily

deformed or bent. The use of packages with higher pin counts and narrower pin pitch results in increased susceptibility to open

connections caused by deformed pins, or shorting due to solder bridges.

You must use appropriate mounting techniques. Cypress recommends the solder reflow method, and has established a ranking of

mounting conditions for each product. Users are advised to mount packages in accordance with Cypress ranking of recommended

conditions.

Lead-free packaging

CAUTION: When ball grid array (BGA) packages with Sn-Ag-Cu balls are mounted using Sn-Pb eutectic soldering, junction

strength may be reduced under some conditions of use.

Storage of semiconductor devices

Because plastic chip packages are formed from plastic resins, exposure to natural environmental conditions will cause absorption

of moisture. During mounting, the application of heat to a package that has absorbed moisture can cause surfaces to peel,

reducing moisture resistance and causing packages to crack. To prevent, do the following:

1. Avoid exposure to rapid temperature changes, which cause moisture to condense inside the product. Store products in

locations where temperature changes are slight.

2. Use dry boxes for product storage. Products should be stored below 70% relative humidity, and at temperatures between 5°C

and 30°C.

When you open Dry Package that recommends humidity 40% to 70% relative humidity.

3. When necessary, Cypress packages semiconductor devices in highly moisture-resistant aluminum laminate bags, with a silica

gel desiccant. Devices should be sealed in their aluminum laminate bags for storage.

4. Avoid storing packages where they are exposed to corrosive gases or high levels of dust.

Baking

Packages that have absorbed moisture may be de-moisturized by baking (heat drying). Follow the Cypress recommended

conditions for baking.

Condition: 125°C/24 h

Document Number: 002-05627 Rev. *B

Page 27 of 81

MB9A110K Series

Static electricity

Because semiconductor devices are particularly susceptible to damage by static electricity, you must take the following

precautions:

1. Maintain relative humidity in the working environment between 40% and 70%. Use of an apparatus for ion generation may be

needed to remove electricity.

2. Electrically ground all conveyors, solder vessels, soldering irons and peripheral equipment.

3. Eliminate static body electricity by the use of rings or bracelets connected to ground through high resistance (on the level

of 1 MΩ).

Wearing of conductive clothing and shoes, use of conductive floor mats and other measures to minimize shock loads is

recommended.

4. Ground all fixtures and instruments, or protect with anti-static measures.

5. Avoid the use of styrofoam or other highly static-prone materials for storage of completed board assemblies.

6.3 Precautions for Use Environment

Reliability of semiconductor devices depends on ambient temperature and other conditions as described above.

For reliable performance, do the following:

1. Humidity

Prolonged use in high humidity can lead to leakage in devices as well as printed circuit boards. If high humidity levels are

anticipated, consider anti-humidity processing.

2. Discharge of Static Electricity

When high-voltage charges exist close to semiconductor devices, discharges can cause abnormal operation. In such cases,

use anti-static measures or processing to prevent discharges.

3. Corrosive Gases, Dust, or Oil

Exposure to corrosive gases or contact with dust or oil may lead to chemical reactions that will adversely affect the device. If

you use devices in such conditions, consider ways to prevent such exposure or to protect the devices.

4. Radiation, Including Cosmic Radiation

Most devices are not designed for environments involving exposure to radiation or cosmic radiation. Users should provide

shielding as appropriate.

5. Smoke, Flame

CAUTION: Plastic molded devices are flammable, and therefore should not be used near combustible substances. If devices

begin to smoke or burn, there is danger of the release of toxic gases.

Customers considering the use of Cypress products in other special environmental conditions should consult with sales

representatives.

Document Number: 002-05627 Rev. *B

Page 28 of 81

MB9A110K Series

7. Handling Devices

Power supply pins

In products with multiple VCC and VSS pins, respective pins at the same potential are interconnected within the device in order to

prevent malfunctions such as latch-up. However, all of these pins should be connected externally to the power supply or ground

lines in order to reduce electromagnetic emission levels, to prevent abnormal operation of strobe signals caused by the rise in the

ground level, and to conform to the total output current rating.

Moreover, connect the current supply source with each Power supply pins and GND pins of this device at low impedance. It is also

advisable that a ceramic capacitor of approximately 0.1 µF be connected as a bypass capacitor between each Power supply pins

and GND pins, between AVCC pin and AVSS pin near this device.

Stabilizing power supply voltage

A malfunction may occur when the power supply voltage fluctuates rapidly even though the fluctuation is within the recommended

operating conditions of the VCC power supply voltage. As a rule, with voltage stabilization, suppress the voltage fluctuation so that

the fluctuation in VCC ripple (peak-to-peak value) at the commercial frequency (50 Hz/60 Hz) does not exceed 10% of the VCC

value in the recommended operating conditions, and the transient fluctuation rate does not exceed 0.1 V/μs when there is a

momentary fluctuation on switching the power supply.

Crystal oscillator circuit

Noise near the X0/X1 and X0A/X1A pins may cause the device to malfunction. Design the printed circuit board so that X0/X1,

X0A/X1A pins, the crystal oscillator (or ceramic oscillator), and the bypass capacitor to ground are located as close to the device as

possible.

It is strongly recommended that the PC board artwork be designed such that the X0/X1 and X0A/X1A pins are surrounded by

ground plane as this is expected to produce stable operation.

Evaluate oscillation of your using crystal oscillator by your mount board.

Using an external clock

When using an external clock, the clock signal should be input to the X0, X0A pin only and the X1, X1A pin should be kept open.

 Example of Using an External Clock

Device

X0(X0A)

Open

X1(X1A)

Handling when using Multi-function serial pin as I²C pin

If it is using Multi-function serial pin as I²C pins, P-ch transistor of digital output is always disable. However, I²C pins need to keep

the electrical characteristic like other pins and not to connect to external I²C bus system with power OFF.

Document Number: 002-05627 Rev. *B

Page 29 of 81

MB9A110K Series

C pin

This series contains the regulator. Be sure to connect a smoothing capacitor (C_S) for the regulator between the C pin and the GND

pin. Please use a ceramic capacitor or a capacitor of equivalent frequency characteristics as a smoothing capacitor.

However, some laminated ceramic capacitors have the characteristics of capacitance variation due to thermal fluctuation

(F characteristics and Y5V characteristics). Please select the capacitor that meets the specifications in the operating conditions to

use by evaluating the temperature characteristics of a capacitor.

A smoothing capacitor of about 4.7 μF would be recommended for this series.

C

Device

C_S

VSS

GND

Mode pins (MD0)

Connect the MD pin (MD0) directly to VCC or VSS pins. Design the printed circuit board such that the pull-up/down resistance

stays low, as well as the distance between the mode pins and VCC pins or VSS pins is as short as possible and the connection

impedance is low, when the pins are pulled-up/down such as for switching the pin level and rewriting the Flash memory data. It is

because of preventing the device erroneously switching to test mode due to noise.

NC pins

NC pin should be kept open.

Notes on power-on

Turn power on/off in the following order or at the same time.

If not using the A/D converter, connect AVCC =VCC and AVSS = VSS.

Turning on: VCC → AVCC → AVRH

Turning off: AVRH → AVCC → VCC

Serial communication

There is a possibility to receive wrong data due to the noise or other causes on the serial communication.

Therefore, design a printed circuit board so as to avoid noise.

Consider the case of receiving wrong data due to noise, perform error detection such as by applying a checksum of data at the

end. If an error is detected, retransmit the data.

Differences in features among the products with different memory sizes and between Flash products and

MASK products

The electric characteristics including power consumption, ESD, latch-up, noise characteristics, and oscillation characteristics

among the products with different memory sizes and between Flash products and MASK products are different because chip

layout and memory structures are different.

If you are switching to use a different product of the same series, please make sure to evaluate the electric characteristics.

Pull-up function of 5 V tolerant I/O

Please do not input the signal more than VCC voltage at the time of Pull-Up function use of 5 V tolerant I/O.

Document Number: 002-05627 Rev. *B

Page 30 of 81

MB9A110K Series

8. Block Diagram

MB9AF111K, F112K

TRSTX,TCK,

TDI,TMS

TDO

SRAM0

8 Kbyte

SWJ-DP

ROM

Table

SRAM1

8 Kbyte

I

Cortex-M3ꢀCore

@40 MHz(Max)

MainFlash I/F

Security

MainFlash

64 Kbyte/

128 Kbyte

D

NVIC

Sys

WorkFlash

32 Kbyte

Dual-Timer

WorkFlash I/F

Watchdog Timer

(Software)

Clock Reset

Generator

INITX

Watchdog Timer

(Hardware)

DMAC

4ch.

CSV

CLK

Main

Source Clock

X0

PLL

Osc

Sub

Osc

X1

CR

4MHz

CR

100kHz

X0A

CROUT

AVCC,

AVSS,

AVRH

12-bit A/D Converter

Unit 0

Power-On

Reset

AN[07:00]

Unit 1

ADTG_2

LVD

LVD Ctrl

Regulator

C

TIOAx

TIOBx

Base Timer

16-bit 8ch./

32-bit 4ch.

WKUP[3:0]

Deep Standby Ctrl

AIN0

BIN0

ZIN0

RTCCO,

SUBOUT

QPRC

1ch.

Real-Time Clock

IRQ-Monitor

A/D Activation Compare

3ch.

CRC

Accelerator

16-bit Input Capture

4ch.

Watch Counter

IC0x

External Interrupt

Controller

6-pin + NMI

INTx

16-bit Free-Run Timer

3ch.

FRCKx

NMIX

16-bit Output Compare

6ch.

MD[1:0]

MODE-Ctrl

GPIO

P0x,

P1x,

.

DTTI0X

RTOx

Waveform Generator

3ch.

PIN-Function-Ctrl

.

PFx

16-bit PPG

3ch.

SCKx

SINx

Multi-Function Serial I/F

4ch.

(with FIFO ch.0 - ch.1)

SOTx

Multi-Function Timer

9. Memory Size

See “Memory size” in “1. Product Lineup” to confirm the memory size.

Document Number: 002-05627 Rev. *B

Page 31 of 81

MB9A110K Series

10.Memory Map

Memory Map (1)

Peripherals Area

Reserved

0x41FF_FFFF

0x4006_1000

0x4006_0000

DMAC

0xFFFF_FFFF

Reserved

0xE010_0000

0xE000_0000

Cortex-M3 Private

Peripherals

0x4003_C000

0x4003_B000

0x4003_A000

0x4003_9000

0x4003_8000

RTC

Watch Counter

CRC

Reserved

MFS

0x7000_0000

0x6000_0000

Reserved

External Device

Area

0x4003_6000

0x4003_5000

0x4003_4000

0x4003_3000

0x4003_2000

0x4003_1000

0x4003_0000

0x4002_F000

0x4002_E000

0x4002_8000

0x4002_7000

0x4002_6000

0x4002_5000

0x4002_4000

LVD/DS mode

Reserved

GPIO

Reserved

0x4400_0000

0x4200_0000

0x4000_0000

Reserved

Int-Req. Read

EXTI

32Mbyte

Bit band alias

Peripherals

Reserved

CR Trim

Reserved

A/DC

0x2400_0000

0x2200_0000

32Mbyte

Bit band alias

QPRC

Base Timer

PPG

Reserved

0x200E_1000

0x200E_0000

0x200C_0000

WorkFlash I/F

WorkFlash

Reserved

MFT unit0

0x2008_0000

0x2000_0000

0x1FFF_0000

SRAM1

SRAM0

0x4002_1000

0x4002_0000

0x4001_6000

0x4001_5000

0x4001_3000

0x4001_2000

0x4001_1000

0x4001_0000

0x4000_1000

0x4000_0000

See the next page

"Memory Map (2)" for

the memory size

details.

Reserved

Dual Timer

0x0010_2000

0x0010_0000

Security/CR Trim

Reserved

SW WDT

MainFlash

HW WDT

0x0000_0000

Clock/Reset

Reserved

MainFlash I/F

Document Number: 002-05627 Rev. *B

Page 32 of 81

MB9A110K Series

Memory Map (2)

MB9AF112K

MB9AF111K

0x200E_0000

Reserved

0x200C_8000

0x200C_0000

0x200C_8000

0x200C_0000

SA0-3 (8KBx4)

Reserved

SA0-3 (8KBx4)

Reserved

0x2000_2000

SRAM1

8Kbyte

SRAM1

8Kbyte

0x2000_0000

0x1FFF_E000

0x2000_0000

0x1FFF_E000

SRAM0

8Kbyte

SRAM0

8Kbyte

Reserved

0x0010_2000

0x0010_1000

0x0010_0000

0x0010_2000

0x0010_1000

0x0010_0000

CR trimming

Security

CR trimming

Security

Reserved

0x0002_0000

0x0000_0000

0x0001_0000

0x0000_0000

SA8-9 (48KBx2)

SA4-7 (8KBx4)

SA8-9 (16KBx2)

SA4-7 (8KBx4)

See "MB9A310K/110K Series Flash programming Manual" for sector structure of Flash.

Document Number: 002-05627 Rev. *B

Page 33 of 81

MB9A110K Series

Peripheral Address Map

Start address

End address

Bus

AHB

Peripherals

0x4000_0000

0x4000_1000

0x4001_0000

0x4001_1000

0x4001_2000

0x4001_3000

0x4001_5000

0x4001_6000

0x4002_0000

0x4002_1000

0x4002_4000

0x4002_5000

0x4002_6000

0x4002_7000

0x4002_8000

0x4002_E000

0x4002_F000

0x4003_0000

0x4003_1000

0x4003_2000

0x4003_3000

0x4003_4000

0x4003_5000

0x4003_5800

0x4003_6000

0x4003_8000

0x4003_9000

0x4003_A000

0x4003_B000

0x4003_C000

0x4004_0000

0x4006_0000

0x4006_1000

0x200E_0000

0x4000_0FFF

0x4000_FFFF

MainFlash I/F register

Reserved

0x4001_0FFF

0x4001_1FFF

0x4001_2FFF

0x4001_4FFF

0x4001_5FFF

0x4001_FFFF

0x4002_0FFF

0x4002_3FFF

0x4002_4FFF

0x4002_5FFF

0x4002_6FFF

0x4002_7FFF

0x4002_DFFF

0x4002_EFFF

0x4002_FFFF

0x4003_0FFF

0x4003_1FFF

0x4003_2FFF

0x4003_3FFF

0x4003_4FFF

0x4003_57FF

0x4003_5FFF

0x4003_7FFF

0x4003_8FFF

0x4003_9FFF

0x4003_AFFF

0x4003_BFFF

0x4003_FFFF

0x4005_FFFF

0x4006_0FFF

0x41FF_FFFF

0x200E_FFFF

Clock/Reset Control

Hardware Watchdog timer

Software Watchdog timer

Reserved

APB0

Dual-Timer

Reserved

Multi-function timer unit0

Reserved

PPG

Base Timer

APB1

Quadrature Position/Revolution Counter

A/D Converter

Reserved

Internal CR trimming

Reserved

External Interrupt Controller

Interrupt Request Batch-Read Function

Reserved

GPIO

Reserved

Low Voltage Detector

Deep stand-by mode Controller

Reserved

APB2

Multi-function serial Interface

CRC

Watch Counter

Real-time clock

Reserved

DMAC register

AHB

Reserved

WorkFlash I/F register

Document Number: 002-05627 Rev. *B

Page 34 of 81

MB9A110K Series

11.Pin Status in Each CPU State

The terms used for pin status have the following meanings.

INITX=0

This is the period when the INITX pin is the "L" level.

INITX=1

This is the period when the INITX pin is the "H" level.

SPL=0

This is the status that standby pin level setting bit (SPL) in standby mode control register (STB_CTL) is set to "0".

SPL=1

This is the status that standby pin level setting bit (SPL) in standby mode control register (STB_CTL) is set to "1".

Input enabled

Indicates that the input function can be used.

Internal input fixed at "0"

This is the status that the input function cannot be used. Internal input is fixed at "L".

Hi-Z

Indicates that the output drive transistor is disabled and the pin is put in the Hi-Z state.

Setting disabled

Indicates that the setting is disabled.

Maintain previous state

Maintains the state that was immediately prior to entering the current mode.

If a built-in peripheral function is operating, the output follows the peripheral function.

If the pin is being used as a port, that output is maintained.

Analog input is enabled

Indicates that the analog input is enabled.

GPIO selected

In Deep stand-by mode, pins switch to the general-purpose I/O port.

Document Number: 002-05627 Rev. *B

Page 35 of 81

MB9A110K Series

List of Pin Status

Return

Power-on

reset or

low-voltage

detection

state

Run

mode or

sleep

mode

state

Device

internal

reset

Deep stand-by

RTC mode or Deep

stand-by STOP

mode state

from

Deep

INITX

input

state

Timer mode,

RTC mode, or

sleep mode state

stand-by

mode

state

Function

group

Power

supply

unstable

Power

supply

stable

Power

supply

stable

Power supply

stable

Power supply

stable

Power supply stable

-

INITX = 0 INITX = 1 INITX = 1

INITX = 1

-

SPL = 0

SPL = 1

SPL = 0

SPL = 1

Hi-Z /

Internal

input

fixed at

"0"

Hi-Z /

Internal

input

fixed at

"0"

Maintain

GPIO

selected

Setting

disabled

Setting

disabled

Setting

disabled

A

Main crystal

oscillator

input pin

Input

enabled

Input

enabled

Input

enabled

Input

enabled

Input

enabled

Input

enabled

Input

enabled

Input

enabled

Input

enabled

Hi-Z /

Internal

input

fixed at

"0"

Hi-Z /

Internal

input

fixed at

"0"

Maintain

GPIO

selected

Setting

disabled

Setting

disabled

Setting

disabled

Maintain

When

oscillation

stop^*1,

Maintain

When

oscillation

stop^*1,

B

Hi-Z/

When

Hi-Z /

oscillation oscillation oscillation

stop^*1,

Hi-Z/

Internal

input

fixed

Main crystal Internal input

Maintain

Internal

input fixed

at "0"

Internal

input fixed

at "0"

oscillator

output pin

fixed at "0"/

or Input

enable

stop^*1,

Hi-Z/

Internal

input

fixed

at "0"

stop^*1,

Hi-

Z/Internal

input

fixed

at "0"

Hi-Z/

Internal

input fixed

at "0"

Internal

input fixed

at "0"

Pull-up /

Input

enabled

Pull-up /

Input

enabled

Pull-up /

Input

enabled

Pull-up /

Input

enabled

Pull-up /

Input

enabled

Pull-up /

Input

enabled

Pull-up /

Input

enabled

Pull-up /

Input

enabled

INITX

input pin

Pull-up / Input

enabled

C

D

Mode

input pin

Input

enabled

Input

enabled

Input

enabled

Input

enabled

Input

enabled

Input

enabled

Input

enabled

Input

enabled

Input enabled

Hi-Z

Pull-up /

Input

enabled

Pull-up /

Input

enabled

Maintain

JTAG

selected

Maintain

E

Hi-Z /

Internal

input

fixed at

"0"

Hi-Z /

Internal

input

fixed at

"0"

Maintain

GPIO

selected

Setting

disabled

Setting

disabled

Setting

disabled

Document Number: 002-05627 Rev. *B

Page 36 of 81

MB9A110K Series

Return

Power-on

reset or

low-voltage

detection

state

Run

mode or

sleep

mode

state

Device

internal

reset

Deep stand-by

RTC mode or Deep

stand-by STOP

mode state

from

Deep

INITX

input

state

Timer mode,

RTC mode, or

sleep mode state

stand-by

mode

state

Function

group

Power

supply

unstable

Power

supply

stable

Power

supply

stable

Power supply

stable

Power supply

stable

Power supply stable

-

INITX = 0 INITX = 1 INITX = 1

INITX = 1

-

SPL = 0

SPL = 1

SPL = 0

SPL = 1

Hi-Z /

WKUP

input

enabled

Hi-Z /

Internal

input

fixed at

"0" /

Analog

input

Maintain

WKUP

input

enabled

WKUP

Setting

GPIO

enabled

disabled

selected

Hi-Z /

Internal

input

fixed at

"0" /

Analog

input

Hi-Z /

Internal

input

fixed at

"0" /

Analog

input

Hi-Z /

Internal

input fixed

at "0" /

Analog

input

Internal

input fixed

at "0" /

Analog

input

Internal

input fixed

at "0" /

Analog

input

Internal

input fixed

at "0" /

Analog

input

Internal

input fixed

at "0" /

Analog

input

Analog

input

selected

Hi-Z

enabled

F

External

interrupt

enabled

selected

Resource

other than

above

Maintain

GPIO

selected

GPIO

selected

Hi-Z /

Internal

input

fixed at

"0"

Maintain

Setting

disabled

Setting

disabled

Setting

disabled

Hi-Z /

Internal

input

selected

fixed at

"0"

Maintain

GPIO

selected

Hi-Z /

WKUP

input

Maintain

WKUP

input

enabled

WKUP

Setting

GPIO

enabled

disabled

selected

enabled

External

interrupt

enabled

selected

Resource

other than

above

Maintain

Setting

disabled

Setting

disabled

Setting

disabled

G

GPIO

selected

GPIO

selected

Hi-Z /

Internal

input

fixed at

"0"

Maintain

Hi-Z /

Internal

input

Hi-Z /

Input

Hi-Z /

Input

selected

Hi-Z

enabled

fixed at

"0"

Maintain

GPIO

selected

External

interrupt

enabled

selected

Resource

other than

above

Maintain

Setting

disabled

Setting

disabled

Setting

disabled

GPIO

selected

GPIO

selected

Hi-Z /

Internal

input

fixed

at "0"

Maintain

H

Hi-Z /

Internal

input

Hi-Z /

Input

Hi-Z /

Input

selected

Hi-Z

enabled

fixed

at "0"

Maintain

GPIO

selected

Document Number: 002-05627 Rev. *B

Page 37 of 81

MB9A110K Series

Return

Power-on

reset or

low-voltage

detection

state

Run

mode or

sleep

mode

state

Device

internal

reset

Deep stand-by

RTC mode or Deep

stand-by STOP

mode state

from

Deep

INITX

input

state

Timer mode,

RTC mode, or

sleep mode state

stand-by

mode

state

Function

group

Power

supply

unstable

Power

supply

stable

Power

supply

stable

Power supply

stable

Power supply

stable

Power supply stable

-

INITX = 0 INITX = 1 INITX = 1

INITX = 1

-

SPL = 0

SPL = 1

SPL = 0

SPL = 1

Resource

selected

GPIO

Hi-Z /

Internal

input

fixed at

"0"

Hi-Z /

Internal

input

fixed at

"0"

selected

Maintain

selected

Maintain

Hi-Z /

Input

enabled

Hi-Z /

Input

enabled

Maintain

I

Hi-Z

GPIO

selected

Maintain

NMIX

selected

Setting

disabled

Setting

disabled

Setting

disabled

GPIO

selected

Resource

other than

above

Hi-Z /

WKUP

input

Maintain

WKUP

input

enabled

Hi-Z /

Internal

input

fixed at

"0"

J

Hi-Z /

Input

enabled

Hi-Z /

Input

enabled

selected

enabled

Hi-Z

Maintain

GPIO

selected

Hi-Z /

Internal

input

fixed at

"0" /

Analog

input

Hi-Z /

Internal

input

fixed at

"0" /

Analog

input

Hi-Z /

Internal

input

fixed at

"0" /

Analog

input

Hi-Z /

Internal

input fixed

at "0" /

Analog

input

Internal

input fixed

at "0" /

Analog

input

Internal

input fixed

at "0" /

Analog

input

Internal

input fixed

at "0" /

Analog

input

Internal

input fixed

at "0" /

Analog

input

Analog

input

selected

enabled

K

Resource

other than

above

GPIO

selected

GPIO

selected

Hi-Z /

Internal

input

fixed at

"0"

Hi-Z /

Internal

input

fixed at

"0"

Maintain

Setting

disabled

Setting

disabled

Setting

disabled

selected

Maintain

GPIO

selected

Hi-Z /

Internal

input

fixed at

"0" /

Analog

input

Hi-Z /

Internal

input

fixed at

"0" /

Analog

input

Hi-Z /

Internal

input

fixed at

"0" /

Analog

input

Hi-Z /

Internal

input fixed

at "0" /

Analog

input

Internal

input fixed

at "0" /

Analog

input

Internal

input fixed

at "0" /

Analog

input

Internal

input fixed

at "0" /

Analog

input

Internal

input fixed

at "0" /

Analog

input

Analog

input

Hi-Z

selected

enabled

External

interrupt

enabled

selected

Resource

other than

above

Maintain

L

GPIO

selected

GPIO

selected

Hi-Z /

Internal

input

fixed at

"0"

Maintain

Setting

disabled

Setting

disabled

Setting

disabled

Hi-Z /

Internal

input

selected

fixed at

"0"

Maintain

GPIO

selected

Document Number: 002-05627 Rev. *B

Page 38 of 81

MB9A110K Series

Return

Power-on

reset or

low-voltage

detection

state

Run

mode or

sleep

mode

state

Device

internal

reset

Deep stand-by

RTC mode or Deep

stand-by STOP

mode state

from

Deep

INITX

input

state

Timer mode,

RTC mode, or

sleep mode state

stand-by

mode

state

Function

group

Power

supply

unstable

Power

supply

stable

Power

supply

stable

Power supply

stable

Power supply

stable

Power supply stable

-

INITX = 0 INITX = 1 INITX = 1

INITX = 1

-

SPL = 0

SPL = 1

SPL = 0

SPL = 1

Hi-Z /

Internal

input

fixed at

"0"

Hi-Z /

Internal

input

fixed at

"0"

Maintain

GPIO

selected

Setting

disabled

Setting

disabled

Setting

disabled

M

Sub crystal

oscillator

input pin

Input

enabled

Input

enabled

Input

enabled

Input

enabled

Input

enabled

Input

enabled

Input

enabled

Input

enabled

Input enabled

Hi-Z /

Maintain

Internal

input

fixed at

"0"

Maintain

Internal

input

fixed at

"0"

Maintain

GPIO

selected

Setting

disabled

Setting

disabled

Setting

disabled

Maintain

N

Hi-Z/

/When

Hi-Z /

Sub crystal

oscillator

output pin

Internal input

fixed at "0"/

or Input

Maintain

/When

oscillation

stop^*2, Hi-

Z/

Internal

input fixed

at "0"

oscillation oscillation oscillation

stop^*2, Hi- stop^*2, Hi- stop^*2, Hi-

Z/ Internal Z/ Internal Z/ Internal

input

fixed

at "0"

Hi-Z /

Internal

input

fixed

at "0"

Input

Internal

input fixed

at "0"

Internal

input fixed

at "0"

oscillation

stop^*2, Hi-

Z/ Internal

input fixed

at "0"

enable

input

fixed

at "0"

input

fixed

at "0"

Hi-Z /

Internal

input

fixed

at "0"

Input

enabled

Hi-Z /

Input

Hi-Z /

Input

enabled

Hi-Z /

Input

enabled

Maintain

GPIO

selected

O

P

Hi-Z

Mode

input pin

Input

enabled

Input

enabled

Input

Input enabled

enabled

Maintain

enabled

Maintain

enabled

Hi-Z /

Input

enabled

Maintain

enabled

Maintain

GPIO

selected

Setting

disabled

Setting

disabled

Setting

disabled

enabled

*1: Oscillation is stopped at sub timer mode, low-speed CR timer mode, RTC mode, stop mode, deep stand-by RTC mode, and

deep stand-by stop mode.

*2: Oscillation is stopped at stop mode and deep stand-by stop mode

Document Number: 002-05627 Rev. *B

Page 39 of 81

MB9A110K Series

12.Electrical Characteristics

12.1 Absolute Maximum Ratings

Parameter

Rating

Symbol

Unit

Remarks

Min

Max

Power supply voltage^{*1, *2}

Vcc

Vss - 0.5

Vss + 6.5

V

Analog power supply voltage^{*1, *3}

Analog reference voltage^{*1, *3}

AVcc

AVRH

Vcc + 0.5

(≤ 6.5 V)

Vss - 0.5

V

Input voltage

V_I

Vss + 6.5

5 V tolerant

AVcc + 0.5

Analog pin input voltage

Output voltage

V_IA

(≤ 6.5 V)

Vcc + 0.5

(≤ 6.5 V)

+2

V_O

Vss - 0.5

-2

V

Clamp maximum current

I_CLAMP

mA

*7

Σ[I_CLAMP

]

Clamp total maximum current

+20

10

20

39

4

12

18.5

100

50

*7

4 mA type

12 mA type

P80, P81

4 mA type

12 mA type

P80, P81

"L" level maximum output current^*4

I_OL

-

"L" level average output current^*5

I_OLAV

"L" level total maximum output current

"L" level total average output current^*6

∑I_OL

-

∑I_OLAV

- 10

mA

4 mA type

"H" level maximum output current^*4

"H" level average output current^*5

I_OH

-

- 20

- 39

- 4

mA

mW

°C

12 mA type

P80, P81

4 mA type

12 mA type

P80, P81

- 12

I_OHAV

- 20.5

- 100

- 50

300

+ 150

"H" level total maximum output current

"H" level total average output current^*6

Power consumption

∑I_OH

∑I_OHAV

P_D

-

Storage temperature

T_STG

- 55

*1: These parameters are based on the condition that V_SS= AV_SS= 0.0 V.

*2: Vcc must not drop below V_SS- 0.5 V.

*3: Ensure that the voltage does not to exceed Vcc + 0.5 V, for example, when the power is turned on.

*4: The maximum output current is the peak value for a single pin.

*5: The average output is the average current for a single pin over a period of 100 ms.

*6: The total average output current is the average current for all pins over a period of 100 ms.

Document Number: 002-05627 Rev. *B

Page 40 of 81

MB9A110K Series

*7:

•

See "4. List of Pin Functions" and "5. I/O Circuit Type" about +B input available pin.

Use within recommended operating conditions.

Use at DC voltage (current) the +B input.

The +B signal should always be applied a limiting resistance placed between the +B signal and the device.

The value of the limiting resistance should be set so that when the +B signal is applied the input current to the device pin

does not exceed rated values, either instantaneously or for prolonged periods.

•

Note that when the device drive current is low, such as in the low-power consumption modes, the +B input potential may

pass through the protective diode and increase the potential at the VCC and AVCC pin, and this may affect other devices.

Note that if a +B signal is input when the device power supply is off (not fixed at 0 V), the power supply is provided from the

pins, so that incomplete operation may result.

The following is a recommended circuit example (I/O equivalent circuit).

Protection Diode

V_CC

P-ch

Limiting

resistor

+B input (0V to 16V)

Digital output

Digital input

N-ch

R

AV_CC

Analog input

WARNING:

−

Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess

of absolute maximum ratings. Do not exceed these ratings.

Document Number: 002-05627 Rev. *B

Page 41 of 81

MB9A110K Series

12.2 Recommended Operating Conditions

(Vss = AVss = 0.0 V)

Value

Parameter

Power supply voltage

Symbol

Vcc

Conditions

Unit

Remarks

Min

Max

-

2.7^*2

5.5

V

Analog power supply voltage

Analog reference voltage

AVcc

-

2.7

5.5

V

AVcc=Vcc

AVRH

AVcc

For built-in

regulator^*1

Smoothing capacitor

C_S

T_A

-

1

10

μF

Operating temperature

- 40

+ 105

°C

*1: See "C Pin" in "7. Handling Devices" for the connection of the smoothing capacitor.

*2: In between less than the minimum power supply voltage and low voltage reset/interrupt detection voltage

or more, instruction execution and low voltage detection function by built-in High-speed CR (including Main PLL is used)

or built-in Low-speed CR is possible to operate only.

WARNING:

−

The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All

of the device's electrical characteristics are warranted when the device is operated within these ranges.

Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges

may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating

conditions, or combinations not represented on the datasheet. Users considering application outside the listed conditions are

advised to contact their representatives beforehand.

Document Number: 002-05627 Rev. *B

Page 42 of 81

MB9A110K Series

12.3 DC Characteristics

12.3.1 Current Rating

(Vcc = AVcc = 2.7 V to 5.5 V, Vss = AVss = 0 V, T_A= - 40°C to + 105°C)

Value

name

Parameter

Symbol

Conditions

Unit

Remarks

Typ^*3

Max^*4

CPU: 40 MHz,

Peripheral: 40 MHz,

MainFlash 0 Wait

FRWTR.RWT = 00

FSYNDN.SD = 000

CPU: 40 MHz,

32

41

mA

*1, *5

PLL

RUN mode

Peripheral: 40 MHz,

MainFlash 3 Wait

FRWTR.RWT = 00

FSYNDN.SD = 011

21

28

mA

*1, *5

RUN

CPU/ Peripheral: 4 MHz^*2

MainFlash 0 Wait

FRWTR.RWT = 00

FSYNDN.SD = 000

mode

current

Icc

High-speed

CR

3.9

7.7

*1

RUN mode

CPU/ Peripheral: 32 kHz

MainFlash 0 Wait

FRWTR.RWT = 00

FSYNDN.SD = 000

CPU/ Peripheral: 100 kHz

MainFlash 0 Wait

Sub

RUN mode

VCC

0.15

0.2

3.2

3.3

mA

*1, *6

*1

Low-speed

CR

RUN mode

FRWTR.RWT = 00

FSYNDN.SD = 000

PLL

Peripheral: 40 MHz

Peripheral: 4 MHz^*2

Peripheral: 32 kHz

Peripheral: 100 kHz

10

1.2

0.1

15

4.4

3.1

mA

*1, *5

*1

SLEEP mode

High-speed

CR

SLEEP mode

Sub

SLEEP mode

Low-speed

CR

SLEEP

mode

Iccs

current

*1, *6

*1

SLEEP mode

*1: When all ports are input and are fixed at "0".

*2: When setting it to 4 MHz by trimming.

*3: T_A=+25°C, V_CC=5.5 V

*4: T_A=+105°C, V_CC=5.5 V

*5: When using the crystal oscillator of 4 MHz (Including the current consumption of the oscillation circuit)

*6: When using the crystal oscillator of 32 kHz (Including the current consumption of the oscillation circuit)

Document Number: 002-05627 Rev. *B

Page 43 of 81

MB9A110K Series

(Vcc = AVcc = 2.7 V to 5.5 V, USBVcc = 3.0 V to 3.6 V, Vss = AVss = 0 V, T_A= - 40°C to + 105°C)

Value

name

Parameter

Symbol

Conditions

Unit

Remarks

Typ^*2

Max^*2

T_A= + 25°C,

5.2

-

6

mA

μA

*1, *3

*1, *4

*1

Main

TIMER

mode

When LVD is off

T_A= + 105°C,

When LVD is off

T_A= + 25°C,

When LVD is off

T_A= + 105°C,

When LVD is off

T_A= + 25°C,

When LVD is off

T_A= + 105°C,

When LVD is off

T_A= + 25°C,

When LVD is off

T_A= + 105°C,

When LVD is off

T_A= + 25°C,

9

TIMER

mode

I_CCT

current

Sub

TIMER

mode

60

-

230

3.1

210

3.1

200

3

mA

μA

RTC

50

-

mode

current

I_CCR

RTC mode

mA

μA

35

-

STOP

mode

I_CCH

STOP mode

current

mA

*1

When LVD is off

RAM hold off

T_A= + 25°C,

30

33

-

160

600

610

150

600

610

μA

mA

μA

*1, *4

*1

VCC

When LVD is off

RAM hold on

T_A= + 105°C,

When LVD is off

RAM hold off

T_A= + 105°C,

When LVD is off

RAM hold on

T_A= + 25°C,

Deep

I_CCRD

stand-by

RTC mode

-

mA

μA

*1

Deep

stand-by

mode

current

When LVD is off

RAM hold off

T_A= + 25°C,

20

23

-

*1, *4

*1

When LVD is off

RAM hold on

T_A= + 105°C,

When LVD is off

RAM hold off

T_A= + 105°C,

When LVD is off

RAM hold on

mA

μA

Deep

I_CCHD

stand-by

STOP mode

-

mA

*1

*1: When all ports are input and are fixed at "0".

*2: V_CC=5.5 V

*3: When using the crystal oscillator of 4 MHz (Including the current consumption of the oscillation circuit)

*4: When using the crystal oscillator of 32 kHz (Including the current consumption of the oscillation circuit)

Document Number: 002-05627 Rev. *B

Page 44 of 81

MB9A110K Series

Low-voltage detection current

(V_CC= 2.7 V to 5.5 V, V_SS= 0 V, T_A= - 40°C to + 105°C)

Value

name

Parameter

Symbol

Conditions

At operation

for interrupt

Vcc = 5.5 V

Unit

Remarks

Typ

Max

Low-voltage detection

circuit (LVD) power

supply current

I_CCLVD

VCC

4

7

μA

At not detect

Flash memory current

Parameter

(V_CC= 2.7 V to 5.5 V, V_SS= 0 V, T_A= - 40°C to + 105°C)

Value

name

Symbol

Conditions

Unit

Remarks

Typ

Max

MainFlash

At Write/Erase

WorkFlash

Flash memory

write/erase

Current

11.4

13.1

mA

I_CCFLASH

VCC

11.4

13.1

At Write/Erase

A/D converter current

Parameter

(V_CC= AV_CC= 2.7 V to 5.5 V, V_SS= AV_SS= AVRL = 0 V, T_A= - 40°C to + 105°C)

Value

name

Symbol

Conditions

At 1 unit operation

At stop

Unit

mA

μA

Remarks

Typ

Max

0.57

0.72

Power supply current

I_CCAD

AVCC

0.06

1.1

20

1.96

4

At 1 unit operation

AVRH=5.5 V

mA

Reference power

supply current

I_CCAVRH

AVRH

At stop

0.06

μA

Document Number: 002-05627 Rev. *B

Page 45 of 81

MB9A110K Series

12.3.2 Pin Characteristics

(Vcc = AVcc = 2.7 V to 5.5 V, Vss = AVss = 0 V, T_A= - 40°C to + 105°C)

Value

Parameter

Symbol

Pin name

CMOS

Conditions

Unit Remarks

Min

Typ

Max

hysteresis

input pin,

MD0, MD1

5V tolerant

input pin

"H" level input

voltage

(hysteresis

input)

-

Vcc × 0.8

-

Vcc + 0.3

V

V_IHS

Vcc × 0.8

Vss - 0.3

-

Vss + 5.5

Vcc × 0.2

CMOS

"L" level

input

voltage

(hysteresis

input)

hysteresis

input pin,

MD0, MD1

5V tolerant

input pin

V_ILS

Vcc ≥ 4.5 V

I_OH= - 4 mA

4mA

type

Vcc - 0.5

-

Vcc

V

Vcc < 4.5 V

I_OH= - 2 mA

Vcc ≥ 4.5 V

I_OH= - 12 mA

"H" level

output voltage

12mA

type

V_OH

Vcc < 4.5 V

I_OH= - 8 mA

Vcc ≥ 4.5 V

I_OH= - 20.5 mA

Vcc < 4.5 V

I_OH= - 13.0 mA

P80/P81

4mA type

Vcc - 0.4

Vss

-

Vcc

0.4

V

Vcc ≥ 4.5 V

I_OL= 4 mA

Vcc < 4.5 V

I_OL= 2 mA

Vcc ≥ 4.5 V

I_OL= 12 mA

"L" level

output voltage

V_OL

12mA type

P80/P81

Vss

V

Vcc < 4.5 V

I_OL= 8 mA

Vcc ≥ 4.5 V

I_OL= 18.5 mA

Vcc< 4.5 V

I_OL= 10.5 mA

Vss

- 5

-

0.4

+5

Input leak current

I_IL

-

μA

kΩ

Vcc ≥ 4.5 V

25

30

50

80

100

200

Pull-up resistance

value

R_PU

Pull-up pin

Vcc < 4.5 V

Other than

VCC,

Input capacitance

C_IN

VSS,

-

5

15

pF

AVCC,

AVSS, AVRH

Document Number: 002-05627 Rev. *B

Page 46 of 81

MB9A110K Series

12.4 AC Characteristics

12.4.1 Main Clock Input Characteristics

(Vcc = 2.7 V to 5.5 V, Vss = 0 V, T_A= - 40°C to + 105°C)

Value

name

Parameter

Symbol

Conditions

Unit

Remarks

Min

Max

Vcc ≥ 4.5 V

Vcc < 4.5 V

Vcc ≥ 4.5 V

Vcc < 4.5 V

Vcc ≥ 4.5 V

4

48

20

48

20

250

When crystal oscillator is

connected

MHz

ns

Input frequency

F_CH

When using external clock

4

X0

X1

20.83

50

Input clock cycle

t_CYLH

-

Vcc < 4.5 V

PWH/tCYLH

PWL/tCYLH

Input clock pulse width

45

-

55

5

%

When using external clock

Input clock rise time and

fall time

t_CF,

t_CR

-

ns

F_CM

-

42

-

MHz

ns

Master clock

F_CC

-

Base clock (HCLK/FCLK)

APB0 bus clock^*2

APB1 bus clock^*2

APB2 bus clock^*2

Base clock (HCLK/FCLK)

APB0 bus clock^*2

APB1 bus clock^*2

APB2 bus clock^*2

Internal operating

clock frequency^*1

F_CP0

F_CP1

F_CP2

t_CYCC

t_CYCP0

t_CYCP1

t_CYCP2

-

23.8

-

ns

Internal operating

clock cycle time^*1

-

ns

-

ns

*1: For more information about each internal operating clock, see "Chapter 2-1: Clock" in "FM3 Family Peripheral Manual".

*2: For about each APB bus which each peripheral is connected to, see "8. Block Diagram" in this datasheet.

X0

Document Number: 002-05627 Rev. *B

Page 47 of 81

MB9A110K Series

12.4.2 Sub Clock Input Characteristics

(Vcc = 2.7 V to 5.5 V, Vss = 0 V, T_A= - 40°C to + 105°C)

Value

name

Parameter

Symbol

Conditions

Unit

Remarks

Min

Typ

Max

When crystal oscillator is

connected

-

32.768

-

kHz

Input frequency

1/ t_CYLL

-

32

10

-

100

kHz

When using external clock

X0A

X1A

Input clock cycle

t_CYLL

-

31.25

μs

PWH/tCYLL

PWL/tCYLL

Input clock pulse width

45

-

55

%

When using external clock

X0A

12.4.3 Internal CR Oscillation Characteristics

High-speed internal CR

(Vcc = 2.7 V to 5.5 V, Vss = 0 V, T_A= - 40°C to + 105°C)

Value

Parameter

Symbol

Conditions

Unit

Remarks

Min

Typ

Max

T_A= + 25°C

3.96

3.84

4

4.04

When trimming^*1

Clock frequency

F_CRH

T_A= 0°C to + 70°C

4

4.16

MHz

T_A= - 40°C to + 85°C

3.8

3

4

-

4.2

5

T_A= - 40°C to + 85°C

-

When not trimming

*2

Frequency stability time

t_CRWT

-

90

μs

*1: In the case of using the values in CR trimming area of Flash memory at shipment for frequency trimming.

*2: Frequency stable time is time to stable of the frequency of the High-speed CR clock after the trim value is set. After setting the

trim value, the period when the frequency stability time passes can use the High-speed CR clock as a source clock.

Low-speed internal CR

(Vcc = 2.7 V to 5.5 V, Vss = 0 V, T_A= - 40°C to + 105°C)

Value

Parameter

Symbol

Conditions

Unit

Remarks

Min

Typ

Max

Clock frequency

F_CRL

-

50

100

150

kHz

Document Number: 002-05627 Rev. *B

Page 48 of 81

MB9A110K Series

12.4.4 Operating Conditions of Main PLL (In the case of using main clock for input of PLL)

(Vcc = 2.7 V to 5.5 V, Vss = 0 V, T_A= - 40°C to + 105°C)

Value

Parameter

Symbol

Unit

Remarks

Min Typ Max

PLL oscillation stabilization wait time^*1

(LOCK UP time)

t_LOCK

100

-

μs

PLL input clock frequency

PLL multiple rate

F_PLLI

-

4

13

200

-

16

75

300

40

MHz

multiple

MHz

PLL macro oscillation clock frequency

Main PLL clock frequency^*2

F_PLLO

F_CLKPLL

MHz

*1: Time from when the PLL starts operating until the oscillation stabilizes.

*2: For more information about Main PLL clock (CLKPLL), see "Chapter 2-1: Clock" in "FM3 Family Peripheral Manual".

12.4.5 Operating Conditions of Main PLL (In the case of using high-speed internal CR)

(Vcc = 2.7 V to 5.5 V, Vss = 0 V, T_A= - 40°C to + 105°C)

Value

Parameter

Symbol

Unit

Remarks

Min Typ Max

PLL oscillation stabilization wait time^*1

(LOCK UP time)

t_LOCK

100

-

μs

PLL input clock frequency

PLL multiple rate

F_PLLI

-

3.8

50

190

-

4

-

4.2

71

300

42

MHz

multiple

MHz

PLL macro oscillation clock frequency

Main PLL clock frequency^*2

F_PLLO

F_CLKPLL

-

MHz

*1: Time from when the PLL starts operating until the oscillation stabilizes.

*2: For more information about Main PLL clock (CLKPLL), see "Chapter 2-1: Clock" in "FM3 Family Peripheral Manual".

When setting PLL multiple rate, please take the accuracy of the built-in high-speed CR clock into account and prevent the

master clock from exceeding the maximum frequency.

Main PLL connection

Main PLL

Main clock (CLKMO)

PLL input

clock

PLL macro

oscillation clock

clock

(CLKPLL)

K

M

divider

Main

PLL

High-speed CR clock (CLKHC)

divider

N

divider

Document Number: 002-05627 Rev. *B

Page 49 of 81

MB9A110K Series

12.4.6 Reset Input Characteristics

(Vcc = 2.7 V to 5.5 V, Vss = 0 V, T_A= - 40°C to + 105°C)

Value

Parameter

Reset input time

Symbol

t_INITX

Pin name

Conditions

Unit

Remarks

Min

Max

INITX

-

500

-

ns

12.4.7 Power-on Reset Timing

(Vss = 0 V, T_A= - 40°C to + 85°C)

Value

Parameter

Symbol

Conditions

Unit

Remarks

Name

Min

Typ

Max

-

Power supply shut down time

Power ramp rate

t_OFF

dV/dt

t_PRT

-

50

0.7

-

ms

mV/µs

ms

*1

*2

VCC

V_CC: 0.2 V to 2.70 V

-

1000

0.89

Time until releasing Power-on reset

0.66

*1: V_CCmust be held below 0.2 V for a minimum period of t_OFF. Improper initialization may occur if this condition is not met.

*2: This dV/dt characteristic is applied at the power-on of cold start (t_OFF>50 ms).

Note:

−

t_OFFmust be satisfied. When t_OFFcannot be satisfied, assert external reset (INITX) at power-up and at any brownout event.

2.7V

V_CC

V_DH

0.2V

dV/dt

tPRT

tOFF

Internal RST

release

start

RST Active

CPU Operation

Glossary

 VDH: detection voltage of Low-Voltage detection reset. See 12.6 Low-voltage Detection Characteristics.

Document Number: 002-05627 Rev. *B

Page 50 of 81

MB9A110K Series

12.4.8 Base Timer Input Timing

Timer input timing

(Vcc = 2.7 V to 5.5 V, Vss = 0 V, T_A= - 40°C to + 105°C)

Value

Parameter

Symbol

Pin name

TIOAn/TIOBn

(when using as ECK,

TIN)

Conditions

Unit

Remarks

Min

Max

t_TIWH

t_TIWL

Input pulse width

-

2t_CYCP

-

ns

t_TIWH

t_TIWL

ECK

TIN

V_IHS

V_ILS

Trigger input timing

(Vcc = 2.7 V to 5.5 V, Vss = 0 V, T_A= - 40°C to + 105°C)

Value

Parameter

Symbol

Pin name

Conditions

Unit

Remarks

Min

Max

TIOAn/TIOBn

(when using as

TGIN)

t_TRGH

t_TRGL

Input pulse width

-

2t_CYCP

-

ns

t_TRGH

t_TRGL

V_IHS

TGIN

V_ILS

Note:

−

t_CYCPindicates the APB bus clock cycle time.

About the APB bus number which Base Timer is connected to, see “8. Block Diagram" in this datasheet.

Document Number: 002-05627 Rev. *B

Page 51 of 81

MB9A110K Series

12.4.9 CSIO/UART Timing

CSIO (SPI = 0, SCINV = 0)

(Vcc = 2.7V to 5.5V, Vss = 0V, T_A= - 40°C to + 105°C)

Vcc < 4.5 V

Min Max

Vcc ≥ 4.5 V

Parameter

Symbol

Conditions

Unit

name

Min

-

Max

Baud rate

-

8

-

8

-

Mbps

ns

Serial clock cycle time

t_SCYC

SCKx

4t_CYCP

SCKx

SOTx

SCKx

SINx

SCKx

SINx

SCK ↓ → SOT delay time

SIN → SCK ↑ setup time

SCK ↑ → SIN hold time

t_SLOVI

t_IVSHI

t_SHIXI

-30

50

0

+30

- 20

30

0

+ 20

ns

Master mode

-

Serial clock "L" pulse width

Serial clock "H" pulse width

t_SLSH

t_SHSL

SCKx

SOTx

SCKx

SINx

2t_CYCP- 10

t_CYCP+ 10

-

2t_CYCP- 10

t_CYCP+ 10

-

ns

SCK ↓ → SOT delay time

SIN → SCK ↑ setup time

SCK ↑ → SIN hold time

t_SLOVE

t_IVSHE

t_SHIXE

-

50

-

30

-

ns

Slave mode

10

20

10

20

SCKx

SINx

-

SCK fall time

SCK rise time

tF

tR

SCKx

-

5

-

5

ns

Notes:

−

The above characteristics apply to CLK synchronous mode.

−

t_CYCPindicates the APB bus clock cycle time.

About the APB bus number which Multi-function Serial is connected to, see "8. Block Diagram" in this datasheet.

−

These characteristics only guarantee the same relocate port number.

For example, the combination of SCKx_0 and SOTx_1 is not guaranteed.

When the external load capacitance = 30 pF.

Document Number: 002-05627 Rev. *B

Page 52 of 81

MB9A110K Series

t_SCYC

V_OH

SCK

SOT

SIN

V_OL

t_SLOVI

V_OH

V_OL

t_IVSHI

V_IH

V_IL

t_SHIXI

V_IH

V_IL

Master mode

t_SLSH

t_SHSL

V_IH

tR

V_IH

SCK

V_IL

F

t

t_SLOVE

V_OH

V_OL

SOT

SIN

t_IVSHE

V_IH

V_IL

t_SHIXE

V_IH

V_IL

Slave mode

Document Number: 002-05627 Rev. *B

Page 53 of 81

MB9A110K Series

CSIO (SPI = 0, SCINV = 1)

Parameter

(Vcc = 2.7 V to 5.5 V, Vss = 0 V, T_A= - 40°C to + 105°C)

Vcc < 4.5 V

Vcc ≥ 4.5 V

name

Symbol

Conditions

Unit

Min

Max

Min

Max

Mbp

s

ns

Baud rate

-

8

-

8

-

Serial clock cycle time

SCK ↑ → SOT delay time

t_SCYC

SCKx

4t_CYCP

SCKx

SOTx

t_SHOVI

-30

+30

- 20

+ 20

ns

Master mode

SCKx

SINx

SCKx

SINx

SCKx

SOTx

SCKx

SINx

SIN → SCK ↓ setup time

SCK ↓ → SIN hold time

t_IVSLI

50

0

-

30

0

-

ns

t_SLIXI

t_SLSH

t_SHSL

Serial clock "L" pulse width

Serial clock "H" pulse width

2t_CYCP- 10

t_CYCP+ 10

-

2t_CYCP- 10

t_CYCP+ 10

-

ns

SCK ↑ → SOT delay time

SIN → SCK ↓ setup time

SCK ↓ → SIN hold time

t_SHOVE

t_IVSLE

t_SLIXE

-

50

-

30

-

ns

Slave mode

10

20

10

20

SCKx

SINx

-

SCK fall time

SCK rise time

tF

tR

SCKx

-

5

-

5

ns

Notes:

−

The above characteristics apply to CLK synchronous mode.

−

t_CYCPindicates the APB bus clock cycle time.

About the APB bus number which Multi-function Serial is connected to, see “8. Block Diagram" in this datasheet.

−

These characteristics only guarantee the same relocate port number.

For example, the combination of SCKx_0 and SOTx_1 is not guaranteed.

When the external load capacitance = 30 pF.

Document Number: 002-05627 Rev. *B

Page 54 of 81

MB9A110K Series

t_SCYC

V_OH

SCK

V_OL

t_SHOVI

V_OH

V_OL

SOT

SIN

t_IVSLI

V_IH

V_IL

t_SLIXI

V_IH

V_IL

Master mode

t_SHSL

t_SLSH

V_IH

tF

SCK

V_IL

tR

V_IL

t_SHOVE

V_OH

V_OL

SOT

SIN

t_IVSLE

t_SLIXE

V_IH

V_IL

V_IH

V_IL

Slave mode

Document Number: 002-05627 Rev. *B

Page 55 of 81

MB9A110K Series

CSIO (SPI = 1, SCINV = 0)

Parameter

(Vcc = 2.7 V to 5.5 V, Vss = 0 V, T_A= - 40°C to + 105°C)

Vcc < 4.5 V

Vcc ≥ 4.5 V

Symbol

Conditions

Unit

name

Min

-

Max

Min

-

Max

Baud rate

Serial clock cycle time

-

8

-

8

-

Mbps

ns

t_SCYC

SCKx

4t_CYCP

SCKx

SOTx

SCK ↑ → SOT delay time

t_SHOVI

-30

+30

- 20

+ 20

ns

SCKx

SINx

SCKx

SINx

SCKx

SOTx

SCKx

SOTx

SCKx

SINx

SIN → SCK ↓ setup time

SCK ↓ → SIN hold time

SOT → SCK ↓ delay time

t_IVSLI

t_SLIXI

t_SOVLI

50

0

-

30

0

-

ns

Master mode

2t_CYCP- 30

Serial clock "L" pulse width

Serial clock "H" pulse width

t_SLSH

t_SHSL

2t_CYCP- 10

t_CYCP+ 10

-

2t_CYCP- 10

t_CYCP+ 10

-

ns

SCK ↑ → SOT delay time

SIN → SCK ↓ setup time

SCK ↓ → SIN hold time

t_SHOVE

t_IVSLE

t_SLIXE

-

50

-

30

-

ns

Slave mode

10

20

10

20

SCKx

SINx

-

SCK fall time

SCK rise time

tF

tR

SCKx

-

5

-

5

ns

Notes:

−

The above characteristics apply to CLK synchronous mode.

−

t_CYCPindicates the APB bus clock cycle time.

About the APB bus number which Multi-function Serial is connected to, see “8. Block Diagram” in this datasheet.

−

These characteristics only guarantee the same relocate port number.

For example, the combination of SCKx_0 and SOTx_1 is not guaranteed.

When the external load capacitance = 30 pF.

Document Number: 002-05627 Rev. *B

Page 56 of 81

MB9A110K Series

t_SCYC

V_OH

V_OL

SCK

SOT

t_SHOVI

t_SOVLI

V_OH

V_OL

V_OH

V_OL

t_IVSLI

t_SLIXI

V_IH

V_IL

V_IH

V_IL

SIN

Master mode

t_SLSH

t_SHSL

SCK

V_IH

tF

V_IH

V_IL

V_IH

V_IL

t_SHOVE

tR

*

V_OH

V_OL

V_OH

V_OL

SOT

SIN

t_IVSLE

t_SLIXE

V_IH

V_IL

V_IH

V_IL

Slave mode

*: Changes when writing to TDR register

Document Number: 002-05627 Rev. *B

Page 57 of 81

MB9A110K Series

CSIO (SPI = 1, SCINV = 1)

Parameter

(Vcc = 2.7 V to 5.5 V, Vss = 0 V, T_A= - 40°C to + 105°C)

Vcc < 4.5 V

Vcc ≥ 4.5 V

Symbol

Conditions

Unit

name

Min

-

Max

Min

-

Max

Baud rate

Serial clock cycle time

-

8

-

8

-

Mbps

ns

t_SCYC

SCKx

4t_CYCP

SCKx

SOTx

SCK ↓ → SOT delay time

t_SLOVI

-30

+30

- 20

+ 20

ns

SCKx

SINx

SCKx

SINx

SCKx

SOTx

SCKx

SOTx

SCKx

SINx

Master mode

SIN → SCK ↑ setup time

SCK ↑ → SIN hold time

SOT → SCK ↑ delay time

t_IVSHI

t_SHIXI

t_SOVHI

50

0

-

30

0

-

ns

2t_CYCP- 30

Serial clock "L" pulse width

Serial clock "H" pulse width

t_SLSH

t_SHSL

2t_CYCP- 10

t_CYCP+ 10

-

2t_CYCP- 10

t_CYCP+ 10

-

ns

SCK ↓→ SOT delay time

SIN → SCK ↑ setup time

SCK ↑ → SIN hold time

t_SLOVE

t_IVSHE

t_SHIXE

-

50

-

30

-

ns

Slave mode

10

20

10

20

SCKx

SINx

-

SCK fall time

SCK rise time

tF

tR

SCKx

-

5

-

5

ns

Notes:

−

The above characteristics apply to CLK synchronous mode.

−

t_CYCPindicates the APB bus clock cycle time.

About the APB bus number which Multi-function Serial is connected to, see “8. Block Diagram” in this datasheet.

−

These characteristics only guarantee the same relocate port number.

For example, the combination of SCKx_0 and SOTx_1 is not guaranteed.

When the external load capacitance = 30 pF.

Document Number: 002-05627 Rev. *B

Page 58 of 81

MB9A110K Series

t_SCYC

V_OL

V_OH

SCK

t_SOVHI

t_SLOVI

V_OH

V_OL

V_OH

V_OL

SOT

SIN

t_SHIXI

t_IVSHI

V_IH

V_IL

V_IH

V_IL

Master mode

t_SHSL

t_SLSH

tR

tF

SCK

V_IH

V_IL

t_SLOVE

V_OH

V_OL

V_OH

V_OL

SOT

SIN

t_IVSHE

t_SHIXE

V_IH

V_IL

V_IH

V_IL

Slave mode

UART external clock input (EXT = 1)

Parameter

(Vcc = 2.7 V to 5.5 V, Vss = 0 V, T_A= - 40°C to + 105°C)

Symbol

Conditions

Min

Max

Unit

Remarks

Serial clock "L" pulse width

Serial clock "H" pulse width

SCK fall time

t_SLSH

t_SHSL

tF

t_CYCP+ 10

-

5

ns

C_L= 30 pF

-

SCK rise time

tR

tF

V_IH

t_SHSL

t_SLSH

SCK

V_IH

V_IL

Document Number: 002-05627 Rev. *B

Page 59 of 81

MB9A110K Series

12.4.10 External Input Timing

(Vcc = 2.7 V to 5.5 V, Vss = 0 V, T_A= - 40°C to + 105°C)

Value

Parameter

Symbol

Pin name

ADTG

Conditions

Unit

Remarks

Min

2t_CYCP

Max

A/D converter trigger input

*1

-

ns

FRCKx

ICxx

Free-run timer input clock

Input capture

t_INH,

t_INL

*1

Input pulse width

DTTIxX

-

ns

Wave form generator

2t_CYCP+ 100^*1

INTxx

NMIX

External interrupt

NMI

*2

500

820

-

ns

*3

*4

WKUPx

Deep stand-by wake up

*1: t_CYCPindicates the APB bus clock cycle time.

About the APB bus number which A/D converter, Multi-function Timer, External interrupt are connected to, see

"8. Block Diagram" in this datasheet.

*2: When in Run mode, in Sleep mode.

*3: When in Stop mode, in RTC mode, in Timer mode.

*4: When in deep stand-by Stop mode, in deep stand-by RTC mode.

Document Number: 002-05627 Rev. *B

Page 60 of 81

MB9A110K Series

12.4.11 Quadrature Position/Revolution Counter timing

(Vcc = 2.7 V to 5.5 V, Vss = 0 V, T_A= - 40°C to + 105°C)

Value

Unit

Parameter

AIN pin "H" width

AIN pin "L" width

BIN pin "H" width

BIN pin "L" width

BIN rise time from

AIN pin "H" level

AIN fall time from

BIN pin "H" level

BIN fall time from

AIN pin "L" level

AIN rise time from

BIN pin "L" level

AIN rise time from

BIN pin "H" level

BIN fall time from

AIN pin "H" level

AIN fall time from

BIN pin "L" level

Symbol

t_AHL

t_ALL

t_BHL

t_BLL

Conditions

Min

Max

-

t_AUBU

t_BUAD

t_ADBD

t_BDAU

t_BUAU

t_AUBD

t_BDAD

t_ADBU

PC_Mode2 or PC_Mode3

*1

2t_CYCP

-

ns

BIN rise time from

AIN pin "L" level

ZIN pin "H" width

ZIN pin "L" width

t_ZHL

t_ZLL

QCR:CGSC="0"

AIN/BIN rise and fall time from

determined ZIN level

Determined ZIN level from AIN/BIN

rise and fall time

t_ZABE

t_ABEZ

QCR:CGSC="1"

*1: t_CYCPindicates the APB bus clock cycle time.

About the APB bus number which Quadrature Position/Revolution Counter is connected to, see “8. Block Diagram" in this

datasheet.

tALL

tAHL

AIN

BIN

tADBD

tAUBU

tBUAD

tBDAU

tBHL

tBLL

Document Number: 002-05627 Rev. *B

Page 61 of 81

MB9A110K Series

tBLL

tBHL

BIN

AIN

tBDAD

tBUAU

tAUBD

tADBU

tAHL

tALL

ZIN

AIN/BIN

Document Number: 002-05627 Rev. *B

Page 62 of 81

MB9A110K Series

12.4.12 I²C Timing

(Vcc = 2.7 V to 5.5 V, Vss = 0 V, T_A= - 40°C to + 105°C)

Standard-mode

Fast-mode

Parameter

Symbol

Conditions

Unit Remarks

Min

Max

Min

Max

SCL clock frequency

(Repeated) START condition hold time

SDA ↓→ SCL ↓

F_SCL

0

100

0

400

kHz

t_HDSTA

4.0

-

0.6

-

μs

SCLclock "L" width

SCLclock "H" width

(Repeated) START setup time

SCL ↑→ SDA ↓

Data hold time

SCL ↓→ SDA ↓ ↑

Data setup time

SDA ↓ ↑ → SCL ↑

STOP condition setup time

SCL ↑→ SDA ↑

t_LOW

t_HIGH

4.7

4.0

-

1.3

0.6

-

μs

t_SUSTA

t_HDDAT

t_SUDAT

t_SUSTO

4.7

0

-

0.6

0

-

μs

ns

μs

C_L= 30 pF,

3.45^*2

0.9^*3

*1

R = (Vp/I_OL

)

250

4.0

-

100

0.6

-

Bus free time between

"STOP condition" and

"START condition"

Noise filter

t_BUF

t_SP

4.7

-

1.3

-

μs

*4

-

2 t_CYCP

ns

*1: R and C represent the pull-up resistance and load capacitance of the SCL and SDA lines, respectively.

Vp indicates the power supply voltage of the pull-up resistance and I_OLindicates V_OLguaranteed current.

*2: The maximum t_HDDATmust satisfy that it doesn't extend at least "L" period (t_LOW) of device's SCL signal.

*3: Fast-mode I²C bus device can be used on Standard-mode I²C bus system as long as the device satisfies the requirement

of "t_SUDAT≥ 250 ns".

*4: t_CYCPis the APB bus clock cycle time.

About the APB bus number that I2C is connected to, see “8. Block Diagram" in this datasheet.

To use Standard-mode, set the APB bus clock at 2 MHz or more.

To use Fast-mode, set the APB bus clock at 8 MHz or more.

SDA

SCL

Document Number: 002-05627 Rev. *B

Page 63 of 81

MB9A110K Series

12.4.13 JTAG Timing

(Vcc = 2.7 V to 5.5 V, Vss = 0 V, T_A= - 40°C to + 105°C)

Value

Parameter

TMS, TDI setup time

TMS, TDI hold time

Symbol

t_JTAGS

Pin name

TCK,

Conditions

Vcc ≥ 4.5 V

Unit

ns

Remarks

Min

Max

15

-

TMS, TDI

Vcc < 4.5 V

Vcc ≥ 4.5 V

TCK,

TMS, TDI

t_JTAGH

15

-

ns

Vcc < 4.5 V

Vcc ≥ 4.5 V

-

25

45

TCK,

TDO

TDO delay time

t_JTAGD

ns

Vcc < 4.5 V

Note:

−

When the external load capacitance = 30 pF.

TCK

TMS/TDI

TDO

Document Number: 002-05627 Rev. *B

Page 64 of 81

MB9A110K Series

12.5 12-bit A/D Converter

Electrical characteristics for the A/D converter

(Vcc = AVcc = 2.7 V to 5.5 V, Vss = AVss = 0 V, T_A= - 40°C to + 105°C)

Value

Typ

-

Parameter

Resolution

Integral nonlinearity

Differential nonlinearity

Zero transition voltage

Symbol

Unit

Remarks

name

Min

Max

12

+ 4.5

+ 2.5

+ 20

-

- 4.5

-2.5

bit

LSB

mV

AVRH = 2.7 V to 5.5 V

V_ZT

ANxx

- 20

AVRH -

20

1.0^*1

1.2^*1

Full-scale transition voltage

Conversion time

V_FST

ANxx

-

AVRH + 20

mV

-

AVcc ≥ 4.5 V

AVcc < 4.5 V

-

μs

*2

-

AVcc ≥ 4.5 V

Sampling time

Ts

-

ns

AVcc < 4.5 V

Compare clock cycle^*3

Tcck

50

-

2000

State transition time to

operation permission

Tstt

-

1.0

μs

Analog input capacity

Analog input resistance

C_AIN

12.9

pF

2

3.8

4

AVcc ≥ 4.5 V

R_AIN

-

kΩ

AVcc < 4.5 V

Interchannel disparity

Analog port input leak current

Analog input voltage

Reference voltage

-

LSB

μA

V

ANxx

AVRH

5

AVSS

2.7

AVRH

AVCC

V

*1: Conversion time is the value of sampling time (Ts) + compare time (Tc).

The condition of the minimum conversion time is the following.

AVcc ≥ 4.5 V, HCLK=40 MHz sampling time: 300 ns, compare time: 700 ns

AVcc < 4.5 V, HCLK=40 MHz sampling time: 500 ns, compare time: 700 ns

Ensure that it satisfies the value of sampling time (Ts) and compare clock cycle (Tcck).

For setting of sampling time and compare clock cycle, see "Chapter 1-1: A/D Converter" in "FM3 Family Peripheral Manual

Analog Macro Part".

The A/D Converter register is set at APB bus clock timing. The sampling clock and compare clock are set at Base clock

(HCLK).

About the APB bus number which the A/D Converter is connected to, see "8. Block Diagram" in this datasheet.

*2: A necessary sampling time changes by external impedance.

Ensure that it set the sampling time to satisfy (Equation 1).

*3: Compare time (Tc) is the value of (Equation 2).

Document Number: 002-05627 Rev. *B

Page 65 of 81

MB9A110K Series

Comparator

ANxx

Rext

R_AIN

Analog input pin

Analog

signal source

C_AIN

(Equation 1) Ts ≥ ( R_AIN+ Rext ) × C_AIN× 9

Ts:

Sampling time

R_AIN: Input resistance of A/D = 2 kΩ at 4.5 V < AV_CC< 5.5 V

Input resistance of A/D = 3.8 kΩ at 2.7 V < AV_CC< 4.5 V

C_AIN: Input capacity of A/D = 12.9 pF at 2.7 V < AV_CC< 5.5 V

Rext: Output impedance of external circuit

(Equation 2) Tc = Tcck × 14

Tc:

Compare time

Tcck: Compare clock cycle

Document Number: 002-05627 Rev. *B

Page 66 of 81

MB9A110K Series

Definition of 12-bit A/D converter terms

Resolution:

Analog variation that is recognized by an A/D converter.

Deviation of the line between the zero-transition point

Integral Nonlinearity:

(0b000000000000←→0b000000000001) and the full-scale transition point

(0b111111111110←→0b111111111111) from the actual conversion characteristics.

Differential Nonlinearity: Deviation from the ideal value of the input voltage that is required to change the output code by 1 LSB.

Integral nonlinearity

Differential nonlinearity

0xFFF

Actual conversion

characteristics

0xFFE

0xFFD

0x(N+1)

0xN

characteristics

{1 LSB(N-1) + V_ZT}

V_FST

Ideal characteristics

(Actually-

measured

value)

V_NT

0x004

(Actually-measured

value)

V_(N+1)T

(Actually-measured

value)

0x(N-1)

0x(N-2)

0x003

0x002

Actual conversion

characteristics

V_NT

(Actually-measured

value)

Ideal characteristics

0x001

(Actually-measured value)

Analog input

V_ZT

Actual conversion characteristics

AVss

AVRH

AVss

AVRH

Analog input

V_NT- {1LSB × (N - 1) + V_ZT}

1LSB

Integral nonlinearity of digital output N =

Differential nonlinearity of digital output N =

[LSB]

V_{(N + 1) T}- V_NT

- 1 [LSB]

1LSB

V_FST- V_ZT

1LSB =

4094

N:

A/D converter digital output value.

V_ZT:

V_FST

V_NT:

Voltage at which the digital output changes from 0x000 to 0x001.

Voltage at which the digital output changes from 0xFFE to 0xFFF.

Voltage at which the digital output changes from 0x(N − 1) to 0xN.

:

Document Number: 002-05627 Rev. *B

Page 67 of 81

MB9A110K Series

12.6 Low-Voltage Detection Characteristics

12.6.1 Low-Voltage Detection Reset

(T_A= - 40°C to + 105°C)

Value

Typ

2.45

2.50

Parameter

Symbol

VDL

Conditions

Unit

Remarks

When voltage drops

Min

2.25

2.30

Max

2.65

2.70

Detected voltage

Released voltage

-

V

VDH

When voltage rises

12.6.2 Interrupt of Low-voltage Detection

(T_A= - 40°C to + 105°C)

Value

Parameter

Symbol

Conditions

SVHI = 0000

SVHI = 0001

Unit

Remarks

Min

Typ

2.8

2.9

3.0

Max

Detected voltage

Released voltage

Detected voltage

VDL

VDH

VDL

2.58

2.67

2.76

3.02

3.13

3.24

V

When voltage drops

When voltage rises

When voltage drops

Released voltage

Detected voltage

Released voltage

Detected voltage

Released voltage

Detected voltage

Released voltage

Detected voltage

Released voltage

Detected voltage

Released voltage

Detected voltage

Released voltage

VDH

VDL

VDH

VDL

VDH

VDL

VDH

VDL

VDH

VDL

VDH

VDL

VDH

2.85

2.94

3.04

3.31

3.40

3.50

3.68

3.77

3.86

3.96

3.1

3.2

3.3

3.6

3.7

3.8

4.0

4.1

4.2

4.3

3.34

3.45

3.56

3.88

3.99

4.10

4.32

4.42

4.53

4.64

V

When voltage rises

When voltage drops

When voltage rises

When voltage drops

When voltage rises

When voltage drops

When voltage rises

When voltage drops

When voltage rises

When voltage drops

When voltage rises

When voltage drops

When voltage rises

SVHI = 0010

SVHI = 0011

SVHI = 0100

SVHI = 0111

SVHI = 1000

SVHI = 1001

*1

LVD stabilization wait time

T_LVDW

-

μs

2240 × t_CYCP

*1: t_CYCPindicates the APB2 bus clock cycle time.

Document Number: 002-05627 Rev. *B

Page 68 of 81

MB9A110K Series

12.7 MainFlash Memory Write/Erase Characteristics

12.7.1 Write / Erase time

(Vcc = 2.7 V to 5.5 V, T_A= - 40°C to + 105°C)

Value

Parameter

Typ^*1

Unit

Remarks

Max^*1

3.7

Large Sector

Small Sector

0.7

0.3

Sector erase time

s

Includes write time prior to internal erase

1.1

Half word (16-bit)

write time

12

384

μs

Not including system-level overhead time

Includes write time prior to internal erase

Chip erase time

3.8

16.2

s

*1: The typical value is immediately after shipment, the maximum value is guarantee value under 100,000 cycle of erase/write.

12.7.2 Erase/write cycles and data hold time

Erase/write cycles (cycle)

Data hold time (year)

1,000

20^*1

10^*1

5^*1

10,000

100,000

*1: At average + 85°C

12.8 WorkFlash Memory Write/Erase Characteristics

12.8.1 Write / Erase time

(Vcc = 2.7 V to 5.5 V, T_A= - 40°C to + 105°C)

Value

Parameter

Unit

Remarks

Typ^*1

Max^*1

Sector erase time

0.3

1.5

s

Includes write time prior to internal erase

Half word (16-bit)

write time

20

384

6

μs

Not including system-level overhead time

Includes write time prior to internal erase

Chip erase time

1.2

s

*1: The typical value is immediately after shipment, the maximum value is guarantee value under 10,000 cycle of erase/write.

12.8.2 Erase/write cycles and data hold time

Erase/write cycles (cycle)

Data hold time (year)

1,000

20^*1

10^*1

10,000

*1: At average + 85C

Document Number: 002-05627 Rev. *B

Page 69 of 81

MB9A110K Series

12.9 Return Time from Low-Power Consumption Mode

12.9.1 Return Factor: Interrupt/WKUP

The return time from Low-Power consumption mode is indicated as follows. It is from receiving the return factor to starting the

program operation.

Return count time

(V_CC= 2.7 V to 5.5 V, T_A= - 40°C to + 105°C)

Value

Parameter

Symbol

Unit

ns

Remarks

Typ

Max^*1

SLEEP mode

t_CYCC

High-speed CR TIMER mode,

Main TIMER mode,

40

80

μs

PLL TIMER mode

Ticnt

Low-speed CR TIMER mode

Sub TIMER mode

370

699

505

740

929

834

μs

STOP mode

*1: The maximum value depends on the accuracy of built-in CR.

Operation example of return from Low-Power consumption mode (by external interrupt^*1)

Ext.INT

Interrupt factor

Active

accept

Ticnt

Interrupt factor

clear by CPU

CPU

Operation

Start

*1: External interrupt is set to detecting fall edge.

Document Number: 002-05627 Rev. *B

Page 70 of 81

MB9A110K Series

Operation example of return from Low-Power consumption mode (by internal resource interrupt^*1)

Internal

Resource INT

Interrupt factor

accept

Active

Ticnt

Interrupt factor

clear by CPU

CPU

Operation

Start

*1: Internal resource interrupt is not included in return factor by the kind of Low-Power consumption mode.

Notes:

−

The return factor is different in each Low-Power consumption modes.

See "Chapter 6: Low Power Consumption Mode" and "Operations of Standby Modes" in FM3 Family Peripheral Manual about

the return factor from Low-Power consumption mode.

−

When interrupt recoveries, the operation mode that CPU recoveries depends on the state before the Low-Power consumption

mode transition. See "Chapter 6: Low Power Consumption Mode" in "FM3 Family Peripheral Manual".

Document Number: 002-05627 Rev. *B

Page 71 of 81

MB9A110K Series

12.9.2 Return Factor: Reset

The return time from Low-Power consumption mode is indicated as follows. It is from releasing reset to starting the program

operation.

Return count time

(V_CC= 2.7 V to 5.5 V, T_A= - 40°C to + 105°C)

Value

Parameter

Symbol

Unit

μs

Remarks

Typ

Max^*1

SLEEP mode

365

554

High-speed CR TIMER mode,

Main TIMER mode,

365

554

μs

PLL TIMER mode

Trcnt

Low-speed CR TIMER mode

Sub TIMER mode

555

608

475

934

976

774

μs

STOP mode

*1: The maximum value depends on the accuracy of built-in CR.

Operation example of return from Low-Power consumption mode (by INITX)

INITX

Internal RST

RST Active

Release

Trcnt

CPU

Operation

Start

Document Number: 002-05627 Rev. *B

Page 72 of 81

MB9A110K Series

Operation example of return from low power consumption mode (by internal resource reset^*1)

Internal

Resource RST

Internal RST

RST Active

Release

Trcnt

CPU

Operation

Start

*1: Internal resource reset is not included in return factor by the kind of Low-Power consumption mode.

Notes:

−

The return factor is different in each Low-Power consumption modes.

See "Chapter 6: Low Power Consumption Mode" and "Operations of Standby Modes" in FM3 Family Peripheral Manual.

When interrupt recoveries, the operation mode that CPU recoveries depends on the state before the Low-Power consumption

mode transition. See "Chapter 6: Low Power Consumption Mode" in "FM3 Family Peripheral Manual".

The time during the power-on reset/low-voltage detection reset is excluded. See "12.4.7. Power-on Reset Timing in 12.4. AC

Characteristics in 12. Electrical Characteristics" for the detail on the time during the power-on reset/low -voltage detection

reset.

−

When in recovery from reset, CPU changes to the high-speed CR run mode. When using the main clock or the PLL clock, it is

necessary to add the main clock oscillation stabilization wait time or the main PLL clock stabilization wait time.

The internal resource reset means the watchdog reset and the CSV reset.

Document Number: 002-05627 Rev. *B

Page 73 of 81

MB9A110K Series

13.Ordering Information

On-chip

Flash

memory

On-chip

SRAM

Part number

Package

Packing

Main: 64 KB

Work: 32 KB

MB9AF111KPMC-G-JNE2

MB9AF112KPMC-G-JNE2

MB9AF111KPMC1-G-JNE2

MB9AF112KPMC1-G-JNE2

MB9AF111KQN-G-AVE2

MB9AF112KQN-G-AVE2

16 KB

Plastic  LQFP

48-pin (0.5 mm pitch),

(LQA048)

Main: 128 KB

Work: 32 KB

16 KB

Main: 64 KB

Work: 32 KB

Plastic  LQFP

52-pin (0.65 mm pitch),

(LQC052)

Tray

Main: 128 KB

Work: 32 KB

Main: 64 KB

Work: 32 KB

Plastic  QFN

48-pin (0.5 mm pitch),

(VNA048)

Main: 128 KB

Work: 32 KB

Document Number: 002-05627 Rev. *B

Page 74 of 81

MB9A110K Series

14.Package Dimensions

Package Type

Package Code

LQFP 48pin (0.5mm pitch)

LQA048

4

D

5

7

D1

36

25

37

24

37

E1

E

5

7

4

3

6

48

13

48

1

12

2

A-B

5

D

7

e

0.10

C

3

0.20

C A-B D

0.80

C

A-B

D

b

8

2

A

9

A

SEATING

PLANE

c

A'

0.25

A1

10

b

0.80

C

L1

L

SECTION A-A'

DIMENSIONS

MIN. NOM. MAX.

1.70

SYMBOL

A

A1

b

0.00

0.15

0.09

0.20

0.27

0.20

c

D

9.00 BSC

7.00 BSC

0.50 BSC

9.00 BSC

7.00 BSC

0.60

D1

e

E

E1

L

0.45

0.30

0

0.75

0.70

8

L1

0.50

PACKAGE OUTLINE, 48 LEAD LQFP

7.0X7.0X1.7 MM LQA048 REV**

002-13731 **

Document Number: 002-05627 Rev. *B

Page 75 of 81

MB9A110K Series

Package Type

Package Code

QFN 48pin (0.5mm pitch)

VNA048

0.10

C

A

B

D

D2

A

25

36

0.10

2X

C

0.10

C A B

24

37

(ND-1)

5

e

E

E2

13

48

12

1

R

9

INDEX MARK

8

L

0.10

0.05

C

A

B

e

b

TOP VIEW

C

4

0.10

2X

C

BOTTOM VIEW

0.10

C

A

SEATING PLANE

C

0.05

A1

9

C

SIDE VIEW

NOTE

1. ALL DIMENSIONS ARE IN MILLIMETERS.

DIMENSIONS

SYMBOL

A

2. DIMENSIONING AND TOLERANCINC CONFORMS TO ASME Y14.5-1994.

3. N IS THE TOTAL NUMBER OF TERMINALS.

MIN. NOM. MAX.

0.90

4. DIMENSION "b" APPLIES TO METALLIZED TERMINAL AND IS MEASURED

BETWEEN 0.15 AND 0.30mm FROM TERMINAL TIP.IF THE TERMINALHAS

THE OPTIONAL RADIUS ON THE OTHER END OF THE TERMINAL.THE

DIMENSION "b"SHOULD NOT BE MEASURED IN THAT RADIUS AREA.

A

0.00

0.05

1

D

E

7.00 BSC

0.25

5. ND REFER TO THE NUMBER OF TERMINALS ON D OR E SIDE.

6. MAX. PACKAGE WARPAGE IS 0.05mm.

0.20

0.30

b

D

5.50 BSC

0.50 BSC

0.20 REF

0.40

2

7. MAXIMUM ALLOWABLE BURRS IS 0.076mm IN ALL DIRECTIONS.

8. PIN #1 ID ON TOP WILL BE LOCATED WITHIN INDICATED ZONE.

E

e

2

9. BILATERAL COPLANARITY ZONE APPLIES TO THE EXPOSEDHEAT

SINK SLUG AS WELL AS THE TERMINALS.

R

L

0.35

0.45

10. JEDEC SPEC IFICATIONNO . REF: N/A

PACKAGE OUTLINE, 48 LEADQFN

7.0X7.0X0.9 MMVNA048 5.5X5.5 MMEPAD(SAWN) REV**

002-15528 **

Document Number: 002-05627 Rev. *B

Page 76 of 81

MB9A110K Series

Package Type

Package Code

LQFP 52pin (0.65mm pitch)

LQC052

4

D

5

7

D1

39

27

39

40

26

40

E1

E

4

5

7

3

6

52

14

52

1

13

1

2

5 7

0.10

C

A-B

D

BOTTOMVIEW

e

3

0.13

C

A-B

D

0.20

C

A-B D

b

8

TOP VIEW

A

2

⁹c

A

A1

0.25

SEATING

PLANE

10

L1

b

A'

SECTION A-A'

0.10

C

L

SIDE VIEW

DIMENSION

SYMBOL

MIN. NOM. MAX.

1.70

A

A1

b

0.00

0.265 0.30 0.365

0.09 0.20

0.20

c

D

D1

e

12.00 BSC

10.00 BSC

0.65 BSC

E

12.00 BSC

10.00 BSC

E1

L

0.45 0.60 0.75

0.30 0.50 0.70

0

L1

PACKAGE OUTLINE, 52 LEAD LQFP

10.0X10.0X1.7 MM LQC052 REV**

002-13880 **

Document Number: 002-05627 Rev. *B

Page 77 of 81

MB9A110K Series

15.Major Changes

Spansion Publication Number: DS706-00030

Page

Section

Change Results

Revision 1.0

PRELIMINARY → Datasheet

-

PRODUCT LINEUP

Function

Added the pin count.

7

PACKAGES

Revised from "Planning".

8

I/O CIRCUIT TYPE

Corrected the following description to "TypeB".

Digital output → Digital input

23

BLOCK DIAGRAM

Corrected the following description.

 AHB (Max 40MHz) → AHB (Max 42MHz)

 APB0 (Max 40MHz) → APB0 (Max 42MHz)

 APB1 (Max 40MHz) → APB1 (Max 42MHz)

 APB2 (Max 40MHz) → APB2 (Max 42MHz)

Deleted the description for "USB Clock Ctrl / PLL".

Revised the value of "TBD".

34

ELECTRICAL CHARACTERISTICS

3. DC Characteristics

Corrected the value.

(1) Current Rating

- Power supply current (I_CCR)

Typ: 60 → 50

- Power supply current (I_CCRD) (RAM hold off)

Typ: 45 → 30

45, 46

- Power supply current (I_CCRD) (RAM hold on)

Typ: 48 → 33

(9) External Input Timing

5. 12-bit A/D Converter

Electrical characteristics for the A/D converter Corrected the value of "Compare clock cycle".

Revised the value of "TBD".

61

66

Deleted "(Preliminary value)".

Max: 10000 → 2000

7. MainFlash Memory Write/Erase

Characteristics

Deleted"(targeted value)".

Erase/write cycles and data hold time

8. WorkFlash Memory Write/Erase

Characteristics

70

Erase/write cycles and data hold time

Revision 1.1

-

Company name and layout design change

Revision 2.0

25

I/O Circuit Type

Added the description of I²C to the type of E and F

Added about +B input

Added "Stabilizing power supply voltage"

Added the following description

25, 26

32

I/O Circuit Type

Handling Devices

Crystal oscillator circuit

Handling Devices

C Pin

Block Diagram

Memory Map

Memory map(1)

Memory Map

32

"Evaluate oscillation of your using crystal oscillator by your mount board."

33

34

35

Changed the description

Modified the block diagram

Modified the area of "External Device Area"

36

Added the summary of Flash memory sector and the note

Memory map(2)

Added the Clamp maximum current

Added the output current of P80 and P81

Added about +B input

Electrical Characteristics

1. Absolute Maximum Ratings

43, 44

Modified the minimum value of Analog reference voltage

Added Smoothing capacitor

Added the note about less than the minimum power supply voltage

Changed the table format

Added Main TIMER mode current

Added Flash Memory Current

Moved A/D Converter Current

Electrical Characteristics

2. Recommended Operation Conditions

45

Electrical Characteristics

3. DC Characteristics

(1) Current rating

46-48

Document Number: 002-05627 Rev. *B

Page 78 of 81

MB9A110K Series

Page

Section

Electrical Characteristics

Change Results

51

4. AC Characteristics

(1) Main Clock Input Characteristics

Electrical Characteristics

4. AC Characteristics

(3) Built-in CR Oscillation Characteristics

Electrical Characteristics

Added Master clock at Internal operating clock frequency

Added Frequency stability time at Built-in high-speed CR

52

53

4. AC Characteristics

Added Main PLL clock frequency

Added the figure of Main PLL connection

(4-1) Operating Conditions of Main PLL

(4-2) Operating Conditions of Main PLL

Electrical Characteristics

4. AC Characteristics

(6) Power-on Reset Timing

Electrical Characteristics

Added Time until releasing Power-on reset

Changed the figure of timing

54

Modified from UART Timing to CSIO/UART Timing

Changed from Internal shift clock operation to Master mode

Changed from External shift clock operation to Slave mode

Added the typical value of Integral Nonlinearity, Differential Nonlinearity, Zero

transition voltage and Full-scale transition voltage

Added Conversion time at AVcc < 4.5 V

Modified Stage transition time to operation permission

Modified the minimum value of Reference voltage

56-63

4. AC Characteristics

(7) CSIO/UART Timing

Electrical Characteristics

5. 12bit A/D Converter

69

Electrical Characteristics

9. Return Time from Low-Power Consumption

Mode

74-77

78

Added Return Time from Low-Power Consumption Mode

Changed the description of part number

Ordering Information

Note: Please see “Document History” about later revised information.

Document Number: 002-05627 Rev. *B

Page 79 of 81

MB9A110K Series

Document History

Document Title: MB9A110K Series 32-bit ARM^®Cortex^®-M3, FM3 Microcontroller

Document Number: 002-05627

Orig. of

Change

Submission

Date

Revision

ECN

Description of Change

Migrated to Cypress and assigned document number 002-05627.

No change to document contents or format.

**

TOYO

02/20/2015

–

*A

5226072

04/18/2016 Updated to Cypress format.

Changed an explanation from “from 01 to 99” to “from 00 to 99” in Real-Time Clock

(RTC) (Page 2) of Features, and Deleted “Second/A day of the week” of interrupt

function.

Changed package code as the following in chapter :

2. Packages

3. Pin Assignment

13. Ordering Information

14. Package Dimensions.

FTP-48P-M49 -> LQA048, LCC-48P-M73 -> VNA048,

FPT-52P-M02 -> LQC052

*B

5561750

YSKA

03/22/2017

Corrected “J-TAG" to “JTAG" in 4. List of Pin Functions.

Added Note for JTAG pin in 4. List of Pin Functions.

Changed remark [1] to "When all ports are input and are fixed at "0"." in 12.3.1 Current

Rating.

Changed Parameter “Power supply rising time (t_VCCR)” to “Power ramp rate (dV/dt)” in

12.4.7 Power-on Reset Timing, Changed the minimum to 0.7mV/μs, Changed the

maximum to 1000mV/μs, and Added remarks and note.

Corrected "Analog port input current" to "Analog port input leak current" in 12.5 12-bit

A/D Converter.

Added the Baud rate spec in “12.4.9 CSIO/UART Timing”(Page 52, 54, 56, 58)

Document Number: 002-05627 Rev. *B

Page 80 of 81

MB9A110K Series

Sales, Solutions, and Legal Information

Worldwide Sales and Design Support

Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the

office closest to you, visit us at Cypress Locations.

Products

PSoC^®Solutions

ARM^®Cortex^®Microcontrollers

cypress.com/arm

cypress.com/automotive

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cypress.com/interface

cypress.com/iot

PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP

Automotive

Cypress Developer Community

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Training | Components

Internet of Things

Memory

Technical Support

cypress.com/memory

cypress.com/mcu

cypress.com/support

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cypress.com/psoc

cypress.com/pmic

cypress.com/touch

cypress.com/usb

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cypress.com/wireless

ARM and Cortex are the registered trademarks of ARM Limited in the EU and other countries.

All other trademarks or registered trademarks referenced herein are the property of their respective owners.

including any software or firmware included or referenced in this document (“Software”), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries

worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other

intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then

Cypress hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code

form, to modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to

end users (either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress’s patents that are infringed by the

Software (as provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation,

or compilation of the Software is prohibited.

TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE

OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. To the extent

permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any

product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It

is the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress

products are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support

devices or systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the

failure of the device or system could cause personal injury, death, or property damage (“Unintended Uses”). A critical component is any component of a device or system whose failure to perform

can be reasonably expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress

from any claim, damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs,

damages, and other liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products.

Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in

the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.

Document Number: 002-05627 Rev. *B

March 22, 2017

Page 81 of 81


型号：	CY9AF112KPMC-G-JNCGE1
厂家：	Infineon
描述：	FM3 CY9AFx1xK-Series Low Power Arm® Cortex®-M3 Microcontroller (MCU) Family 微控制器
文件：	总82页 (文件大小：1376K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

CY9AF112KPMC-G-JNCGE1 [INFINEON]

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