CY9AF156NBBGL-GK9E1 [INFINEON]
FM3 CY9AFx5xM/N/R-Series Low Power Arm® Cortex®-M3 Microcontroller (MCU) Family;
| 型号： | CY9AF156NBBGL-GK9E1 |
| 厂家： | 
Infineon |
| 描述： | FM3 CY9AFx5xM/N/R-Series Low Power Arm® Cortex®-M3 Microcontroller (MCU) Family 微控制器 |
| 文件： | 总150页 (文件大小：2743K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Please note that Cypress is an Infineon Technologies Company.
The document following this cover page is marked as “Cypress” document as this is the
company that originally developed the product. Please note that Infineon will continue
to offer the product to new and existing customers as part of the Infineon product
portfolio.
Continuity of document content
The fact that Infineon offers the following product as part of the Infineon product
portfolio does not lead to any changes to this document. Future revisions will occur
when appropriate, and any changes will be set out on the document history page.
Continuity of ordering part numbers
Infineon continues to support existing part numbers. Please continue to use the
ordering part numbers listed in the datasheet for ordering.
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CY9A150RB Series
32-bit Arm® Cortex®-M3
FM3 Microcontroller
The CY9A150RB Series are highly integrated 32-bit microcontrollers dedicated for embedded controllers with low-power
consumption mode and competitive cost.
These series are based on the Arm Cortex-M3 Processor with on-chip Flash memory and SRAM, and have peripheral functions
such as various timers, ADCs, and Communication Interfaces (UART, CSIO, I2C).
The products which are described in this data sheet are placed into TYPE8 product categories in FM3 Family Peripheral Manual.
Features
32-bit Arm Cortex-M3 Core
◼Processor version: r2p1
Multi-function Serial Interface (Max 16 channels)
◼16 channels with 16 steps×9-bit FIFO
◼Up to 40 MHz Frequency Operation
◼Operation mode is selectable from the followings for each
channel.
◼Integrated Nested Vectored Interrupt Controller (NVIC): 1
NMI (non-maskable interrupt) and
UART
CSIO
I2C
48 peripheral interrupts and 16 priority levels
◼24-bit System timer (Sys Tick): System timer for OS task
management
[UART]
On-chip Memories
◼Full-duplex double buffer
◼Selection with or without parity supported
◼Built-in dedicated baud rate generator
◼External clock available as a serial clock
[Flash memory]
◼Dual operation Flash memory
Dual Operation Flash memory has the upper bank and
the lower bank.
◼Hardware Flow control: Automatically control the
So, this series could implement erase, write and read
operations
transmission/reception by CTS/RTS (only ch.4)
◼Various error detection functions available (parity errors,
for each bank simultaneously.
framing errors, and overrun errors)
◼Main area: Up to 512 Kbytes (Up to 496 Kbytes upper bank
+ 16 Kbytes lower bank)
[CSIO]
◼Work area: 32 Kbytes (lower bank)
◼Read cycle: 0 wait-cycle
◼Full-duplex double buffer
◼Built-in dedicated baud rate generator
◼Overrun error detection function available
◼Security function for code protection
[SRAM]
[I2C]
This Series on-chip SRAM is composed of two independent
SRAM (SRAM0, SRAM1). SRAM0 is connected to I-code bus
and D-code bus of Cortex-M3 core. SRAM1 is connected to
System bus.
Standard-mode (Max 100 kbps) / Fast-mode (Max 400 kbps)
supported
DMA Controller (8channels)
◼SRAM0: Up to 32 Kbytes
◼SRAM1: Up to 32 Kbytes
The DMA Controller has an independent bus from the CPU, so
CPU and DMA Controller can process simultaneously.
◼8 independently configured and operated channels
External Bus Interface
◼Transfer can be started by software or request from the
◼Supports SRAM, NOR NAND Flash memory device
◼Up to 8 chip selects
built-in peripherals
◼Transfer address area: 32-bit (4 Gbytes)
◼8-/16-bit Data width
◼Transfer mode: Block transfer/Burst transfer/Demand
transfer
◼Up to 25-bit Address bit
◼Transfer data type: byte/half-word/word
◼Transfer block count: 1 to 16
◼Maximum area size: Up to 256 Mbytes
◼Supports Address/Data multiplex
◼Supports external RDY function
◼Number of transfers: 1 to 65536
Cypress Semiconductor Corporation
Document Number: 002-05646 Rev. *E
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised June 15, 2021
CY9A150RB Series
A/D Converter (Max 24 channels)
[12-bit A/D Converter]
The following function can be used to achieve the motor
control.
◼Successive Approximation type
◼Built-in 2 units
◼PWM signal output function
◼DC chopper waveform output function
◼Dead time function
◼Conversion time: 2.0 μs @ 2.7 V to 3.6 V
◼Priority conversion available (priority at 2 levels)
◼Scanning conversion mode
◼Input capture function
◼A/D convertor activate function
◼DTIF (Motor emergency stop) interrupt function
◼Built-in FIFO for conversion data storage (for SCAN
conversion: 16 steps, for Priority conversion: 4 steps)
Quadrature Position/Revolution Counter (QPRC)
The Quadrature Position/Revolution Counter (QPRC) is used
to measure the position of the position encoder. Moreover, it is
possible to use as the up/down counter.
Base Timer (Max 16channels)
Operation mode is selectable from the followings for each
channel.
◼16-bit PWM timer
◼16-bit PPG timer
◼The detection edge of the three external event input pins
AIN, BIN and ZIN is configurable.
◼16-/32-bit reload timer
◼16-/32-bit PWC timer
◼16-bit position counter
◼16-bit revolution counter
◼Two 16-bit compare registers
General-Purpose I/O Port
This series can use its pins as general-purpose I/O ports when
they are not used for external bus or peripherals. Moreover,
the port relocate function is built in. It can set which I/O port
the peripheral function can be allocated to.
HDMI-CEC/Remote Control Reception (Up to
2 channels)
HDMI-CEC transmission
◼Capable of pull-up control per pin
◼Capable of reading pin level directly
◼Built-in the port relocate function
◼Header block automatic transmission by judging Signal free
◼Generating status interrupt by detecting Arbitration lost
◼Generating START, EOM, ACK automatically to output CEC
◼Up to 103 high-speed general-purpose I/O Ports@120 pin
transmission by setting 1 byte data
Package
◼Generating transmission status interrupt when transmitting
◼Some ports are 5 V tolerant I/O
1 block (1 byte data and EOM/ACK)
See List of Pin Function and I/O Circuit Type to confirm the
corresponding pins.
HDMI-CEC reception
◼Automatic ACK reply function available
◼Line error detection function available
Dual Timer (32-/16-bit Down Counter)
The Dual Timer consists of two programmable 32-/16-bit down
counters.
Remote control reception
Operation mode is selectable from the followings for each
channel.
◼4 bytes reception buffer
◼Repeat code detection function available
◼Free-running
◼Periodic (=Reload)
◼One-shot
Real-time clock (RTC)
The Real-time clock can count
Year/Month/Day/Hour/Minute/Second/A day of the week from
00 to 99.
Multi-function Timer
The Multi-function timer is composed of the following blocks.
◼The interrupt function with specifying date and time
(Year/Month/Day/Hour/Minute) is available. This function is
also available by specifying only Year, Month, Day, Hour or
Minute.
◼16-bit free-run timer × 3ch.
◼Input capture × 4ch.
◼Output compare × 6ch.
◼A/D activation compare × 2ch.
◼Waveform generator × 3ch.
◼16-bit PPG timer × 3ch.
◼Timer interrupt function after set time or each set time.
◼Capable of rewriting the time with continuing the time count.
◼Leap year automatic count is available.
Document Number: 002-05646 Rev. *E
Page 2 of 149
CY9A150RB Series
Watch Counter
Clock Super Visor (CSV)
The Watch counter is used for wake up from sleep and timer
Clocks generated by built-in CR oscillators are used to
mode.
supervise abnormality of the external clocks.
◼If external clock failure (clock stop) is detected, reset is
Interval timer: up to 64 s (Max) @ Sub Clock : 32.768 kHz
asserted.
◼If external frequency anomaly is detected, interrupt or reset
External Interrupt Controller Unit
is asserted.
◼Up to 24 external interrupt input pins
◼Include one non-maskable interrupt (NMI) input pin
Low-Voltage Detector (LVD)
This Series includes 2-stage monitoring of voltage on the VCC
pins. When the voltage falls below the voltage that has been
set, Low-Voltage Detector generates an interrupt or reset.
Watchdog Timer (Two channels)
A watchdog timer can generate interrupts or a reset when a
time-out value is reached.
◼LVD1: error reporting via interrupt
◼LVD2: auto-reset operation
This series consists of two different watchdogs, a "Hardware"
watchdog and a "Software" watchdog.
Low-Power Consumption Mode
Six low-power consumption modes supported.
The Hardware watchdog timer is clocked by the built-in Low-
speed CR oscillator. Therefore, the Hardware watchdog is
active in any low-power consumption modes except RTC,
Stop, Deep Standby RTC and Deep Standby Stop modes.
◼Sleep
◼Timer
◼RTC
◼Stop
CRC (Cyclic Redundancy Check) Accelerator
The CRC accelerator calculates the CRC which has a heavy
software processing load, and achieves a reduction of the
integrity check processing load for reception data and storage.
◼Deep Standby RTC (selectable between keeping the value
of RAM and not)
◼Deep Standby Stop (selectable between keeping the value
of RAM and not)
CCITT CRC16 and IEEE-802.3 CRC32 are supported.
◼CCITT CRC16 Generator Polynomial: 0x1021
Debug
◼IEEE-802.3 CRC32 Generator Polynomial: 0x04C11DB7
◼Serial Wire JTAG Debug Port (SWJ-DP)
◼Embedded Trace Macrocells (ETM).*
Clock and Reset
*: CY9AF154MB, F155MB and F156MB support only SWJ-DP.
[Clocks]
Unique ID
Selectable from five clock sources (2 external oscillators, 2
built-in CR oscillators, and Main PLL).
Unique value of the device (41-bit) is set.
◼Main Clock: 4 MHz to 48 MHz
◼Sub Clock: 32.768 kHz
Power Supply
Wide range voltage: VCC = 1.65 V to 3.6 V
◼Built-in High-speed CR Clock: 4 MHz
◼Built-in Low-speed CR Clock: 100 kHz
◼Main PLL Clock
[Resets]
◼Reset requests from INITX pin
◼Power-on reset
◼Software reset
◼Watchdog timers reset
◼Low-voltage detection reset
◼Clock Super Visor reset
Document Number: 002-05646 Rev. *E
Page 3 of 149
CY9A150RB Series
Contents
Features................................................................................................................................................................................... 1
1.
Product Lineup .............................................................................................................................................................. 6
Memory size................................................................................................................................................................... 6
Function......................................................................................................................................................................... 6
Packages........................................................................................................................................................................ 8
Pin Assignment.............................................................................................................................................................. 9
LQM120 ......................................................................................................................................................................... 9
LQI100......................................................................................................................................................................... 10
LQH080........................................................................................................................................................................ 11
LBC112........................................................................................................................................................................ 12
FDG096 ....................................................................................................................................................................... 13
List of Pin Function ..................................................................................................................................................... 14
List of Pin Numbers...................................................................................................................................................... 14
List of Pin Functions..................................................................................................................................................... 36
I/O Circuit Type ............................................................................................................................................................ 60
Handling Precautions.................................................................................................................................................. 65
Precautions for Product Design ................................................................................................................................... 65
Precautions for Package Mounting .............................................................................................................................. 66
Precautions for Use Environment ................................................................................................................................ 68
Handling Devices......................................................................................................................................................... 69
Power Supply Pins....................................................................................................................................................... 69
Stabilizing Power Supply Voltage ................................................................................................................................ 69
Crystal Oscillator Circuit............................................................................................................................................... 69
Sub Crystal Oscillator .................................................................................................................................................. 69
Using an external clock................................................................................................................................................ 70
Handling when using Multi-function serial pin as I2C pin.............................................................................................. 70
C pin ............................................................................................................................................................................ 70
Mode pins (MD0) ......................................................................................................................................................... 70
Notes on power-on....................................................................................................................................................... 71
1.1
1.2
2.
3.
3.1
3.2
3.3
3.4
3.5
4.
4.1
4.2
5.
6.
6.1
6.2
6.3
7.
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
7.10 Serial Communication.................................................................................................................................................. 71
7.11 Differences in features among the products with different memory sizes and between Flash memory products
and MASK products..................................................................................................................................................... 71
7.12 Pull-Up function of 5 V tolerant I/O............................................................................................................................... 71
8.
9.
Block Diagram.............................................................................................................................................................. 72
Memory Size............................................................................................................................................................... 72
10. Memory Map................................................................................................................................................................. 73
10.1 Memory Map (1)........................................................................................................................................................... 73
10.2 Memory Map (2)........................................................................................................................................................... 74
10.3 Peripheral Address Map .............................................................................................................................................. 75
11. Pin Status in Each CPU State ..................................................................................................................................... 76
11.1 List of Pin Status.......................................................................................................................................................... 77
12. Electrical Characteristics............................................................................................................................................ 86
12.1 Absolute Maximum Ratings ......................................................................................................................................... 86
12.2 Recommended Operating Conditions.......................................................................................................................... 87
12.3 DC Characteristics....................................................................................................................................................... 88
12.3.1 Current rating............................................................................................................................................................... 88
Document Number: 002-05646 Rev. *E
Page 4 of 149
CY9A150RB Series
12.3.2 Pin Characteristics ....................................................................................................................................................... 91
12.4 AC Characteristics ....................................................................................................................................................... 92
12.4.1 Main Clock Input Characteristics.................................................................................................................................. 92
12.4.2 Sub Clock Input Characteristics ................................................................................................................................... 93
12.4.3 Built-in CR Oscillation Characteristics.......................................................................................................................... 94
12.4.4 Operating Conditions of Main PLL ............................................................................................................................... 95
12.4.5 Reset Input Characteristics.......................................................................................................................................... 96
12.4.6 Power-on Reset Timing................................................................................................................................................ 96
12.4.7 External Bus Timing..................................................................................................................................................... 97
12.4.8 Base Timer Input Timing............................................................................................................................................ 108
12.4.9 CSIO/UART Timing.................................................................................................................................................... 109
12.4.10 External Input Timing ............................................................................................................................................... 117
12.4.11 Quadrature Position/Revolution Counter timing ....................................................................................................... 118
12.4.12 I2C Timing ................................................................................................................................................................ 121
12.4.13 ETM Timing.............................................................................................................................................................. 122
12.4.14 JTAG Timing ............................................................................................................................................................ 123
12.5 12-bit A/D Converter .................................................................................................................................................. 124
12.5.1 Electrical Characteristics for the A/D Converter......................................................................................................... 124
12.5.2 Definition of 12-bit A/D Converter Terms ................................................................................................................... 126
12.6 Low-Voltage Detection Characteristics ...................................................................................................................... 127
12.6.1 Low-Voltage Detection Reset..................................................................................................................................... 127
12.6.2 Interrupt of Low-Voltage Detection............................................................................................................................. 129
12.7 Flash Memory Write/Erase Characteristics................................................................................................................ 130
12.7.1 Write / Erase time....................................................................................................................................................... 130
12.7.2 Write cycles and data hold time ................................................................................................................................. 130
12.8 Return Time from Low-Power Consumption Mode .................................................................................................... 131
12.8.1 Return Factor: Interrupt/WKUP .................................................................................................................................. 131
12.8.2 Return Factor: Reset.................................................................................................................................................. 133
13. Ordering Information................................................................................................................................................. 135
14. Package Dimensions................................................................................................................................................. 136
15. Errata .......................................................................................................................................................................... 141
15.1 Part Numbers Affected............................................................................................................................................... 141
15.2 Qualification Status.................................................................................................................................................... 141
15.3 Errata Summary......................................................................................................................................................... 141
16. Major Changes........................................................................................................................................................... 144
Document History............................................................................................................................................................... 147
Sales, Solutions, and Legal Information........................................................................................................................... 149
Document Number: 002-05646 Rev. *E
Page 5 of 149
CY9A150RB Series
1. Product Lineup
1.1 Memory size
Product name
CY9AF154MB/NB/RB
256 Kbytes
CY9AF155MB/NB/RB
CY9AF156MB/NB/RB
Main area
384 Kbytes
512 Kbytes
On-chip
Flash memory
Work area
SRAM0
SRAM1
Total
32 Kbytes
16 Kbytes
16 Kbytes
32 Kbytes
32 Kbytes
24 Kbytes
24 Kbytes
48 Kbytes
32 Kbytes
32 Kbytes
32 Kbytes
64 Kbytes
On-chip SRAM
1.2 Function
CY9AF154MB
CY9AF154NB
CY9AF155NB
CY9AF156NB
100/112
CY9AF154RB
CY9AF155RB
CY9AF156RB
120
Product name
CY9AF155MB
CY9AF156MB
Pin count
CPU
80/96
Cortex-M3
Freq.
40 MHz
Power supply voltage range
DMAC
1.65V to 3.6V
8ch.
Addr: 21-bit (Max)
R/W Data: 8-bit (Max)
CS: 4 (Max)
Addr: 25-bit (Max)
R/W Data: 8-/16-bit (Max)
CS: 8 (Max)
Addr: 25-bit (Max)
R/W Data: 8-/16-bit (Max)
CS: 8 (Max)
External Bus Interface
Support: SRAM, NOR Flash
memory
Support: SRAM,
Support: SRAM,
NOR Flash memory,
NAND Flash memory
16ch. (Max)
NOR Flash memory
14ch. (Max)
10ch. (Max)
Multi-function Serial Interface
(UART/CSIO/I2C)
Enabled channels :
ch.0 to ch.13
Enabled channels : ch.0 to
ch.15
Enabled channels :
ch.0 to ch.7, ch.10, ch.11
Base Timer
16ch. (Max)
(PWC/Reload timer/PWM/PPG)
A/D activation
2ch
compare
.
4ch
Input capture
.
3ch
Free-run timer
MF-
.
1 unit (Max)
Timer
6ch
Output compare
.
3ch
Waveform generator
PPG
.
3ch
.
QPRC
2ch. (Max)
1 unit
Dual Timer
HDMI-CEC/ Remote Control
Reception
2ch. (Max)
Document Number: 002-05646 Rev. *E
Page 6 of 149
CY9A150RB Series
CY9AF154MB
CY9AF155MB
CY9AF156MB
CY9AF154NB
CY9AF155NB
CY9AF156NB
CY9AF154RB
CY9AF155RB
CY9AF156RB
Product name
Real-Time Clock
1 unit
1 unit
Yes
Watch Counter
CRC Accelerator
Watchdog timer
1ch. (SW) + 1ch. (HW)
23 pins (Max) + NMI × 1
External Interrupts
I/O ports
24 pins (Max) + NMI × 1
83 pins (Max)
66 pins (Max)
17ch. (2 units)
Yes
103 pins (Max)
12-bit A/D converter
CSV (Clock Super Visor)
LVD (Low-Voltage Detector)
24ch. (2 units)
2ch.
High-speed
Built-in CR
4 MHz
Low-speed
100 kHz
SWJ-DP
Yes
Debug Function
Unique ID
SWJ-DP/ETM
Note:
−
All signals of the peripheral function in each product cannot be allocated by limiting the pins of package. It is necessary to
use the port relocate function of the I/O port according to your function use.
−
See Electrical Characteristics0 AC Characteristics 12.4.3 Built-in CR Oscillation Characteristics for accuracy of built-in CR.
Document Number: 002-05646 Rev. *E
Page 7 of 149
CY9A150RB Series
2. Packages
CY9AF154MB
CY9AF155MB
CY9AF156MB
CY9AF154NB
CY9AF155NB
CY9AF156NB
CY9AF154RB
CY9AF155RB
CY9AF156RB
Product name
Package
-
LQFP: LQH080 (0.5 mm pitch)
BGA: FDG096 (0.5 mm pitch)
LQFP: LQI100 (0.5 mm pitch)
BGA: LBC112 (0.8 mm pitch)
LQFP: LQM120 (0.5 mm pitch)
-
-
-
-
-
-
-
-
-
: Supported
Note:
−
See Package Dimensions for detailed information on each package.
Document Number: 002-05646 Rev. *E
Page 8 of 149
CY9A150RB Series
3. Pin Assignment
3.1 LQM120
(TOP VIEW)
VCC
1
2
3
4
5
6
7
8
9
90 VSS
P50/SIN3_1/AIN0_2/TIOB8_0/INT00_0/MADATA00_0
P51/SOT3_1/BIN0_2/TIOB9_0/INT01_0/MADATA01_0
P52/SCK3_1/ZIN0_2/TIOB10_0/INT02_0/MADATA02_0
P53/SIN6_0/TIOB11_0/TIOA1_2/INT07_2/MADATA03_0
P54/SOT6_0/TIOB12_0/TIOB1_2/INT18_1/MADATA04_0
P55/ADTG_1/SCK6_0/TIOB13_0/INT19_1/MADATA05_0
P56/SIN1_0/TIOA8_0/INT08_2/CEC1_1/MADATA06_0
P57/SOT1_0/TIOA9_0/MADATA07_0
89 P20/AN19/CROUT_0/AIN1_1/TIOA10_2/INT05_0/MAD24_0
88 P21/AN18/SIN0_0/BIN1_1/TIOB10_2/INT06_1/WKUP2
87 P22/AN17/SOT0_0/ZIN1_1/TIOB7_1
86 P23/AN16/SCK0_0/RTO00_1/TIOA7_1
85 P24/SIN2_1/RTO01_1/TIOB14_1/INT01_2
84 P25/SOT2_1/RTO02_1/TIOA14_1/TIOB11_2
83 P26/SCK2_1/RTO03_1/TIOA11_2
82 P27/SIN15_0/RTO04_1/TIOA6_2/INT02_2
81 P28/ADTG_4/SOT15_0/RTO05_1/TIOB6_2
80 P1F/AN15/ADTG_5/SCK15_0/FRCK0_1/TIOB9_2/MAD23_0
79 P1E/AN14/RTS4_1/DTTI0X_1/TIOA9_2/INT23_2/MAD22_0
78 P1D/AN13/CTS4_1/IC03_1/TIOA13_1/INT22_2/MAD21_0
77 P1C/AN12/SCK4_1/IC02_1/TIOA12_1/INT21_2/MAD20_0
76 P1B/AN11/SOT4_1/IC01_1/TIOA11_1/INT20_2/MAD19_0
75 P1A/AN10/SIN4_1/IC00_1/TIOA10_1/INT05_1/MAD18_0
74 P19/AN09/SCK2_2/TIOA9_1/MAD17_0
73 P18/AN08/SOT2_2/TIOA8_1/MAD16_0
72 AVSS
P58/SCK1_0/TIOA10_0/MADATA08_0 10
P59/SIN7_0/TIOA11_0/INT09_2/MADATA09_0 11
P5A/SOT7_0/TIOA12_0/INT16_2/MADATA10_0 12
P5B/SCK7_0/TIOA13_0/INT17_2/MADATA11_0 13
P30/AIN0_0/TIOB0_1/TIOA13_2/INT03_2/WKUP4/MADATA12_0 14
P31/SCK6_1/BIN0_0/TIOB1_1/TIOB13_2/INT04_2/MADATA13_0 15
P32/SOT6_1/ZIN0_0/TIOB2_1/INT05_2/MADATA14_0 16
P33/ADTG_6/SIN9_0/SIN6_1/TIOB3_1/INT04_0/MADATA15_0 17
P34/SOT9_0/FRCK0_0/TIOB4_1/TIOA15_2/MNALE_0 18
P35/SCK9_0/IC03_0/TIOB5_1/TIOB15_2/INT08_1/MNCLE_0 19
P36/SIN5_2/IC02_0/TIOB14_0/INT09_1/MNWEX_0 20
P37/SOT5_2/IC01_0/TIOA14_0/INT10_1/MNREX_0 21
P38/SCK5_2/IC00_0/TIOA8_2/INT11_1 22
LQFP - 120
71 AVRH
70 AVCC
69 P17/AN07/SIN2_2/INT04_1/MAD15_0
P39/ADTG_2/SIN10_0/DTTI0X_0/TIOB8_2/INT06_0 23
P3A/SOT10_0/RTO00_0/TIOA0_1/INT07_0/RTCCO_2/SUBOUT_2 24
P3B/SCK10_0/RTO01_0/TIOA1_1 25
68 P16/AN06/SCK0_1/TIOB13_1/INT15_0/MAD14_0
67 P15/AN05/SOT0_1/IC03_2/TIOB12_1/INT14_0/MAD13_0
66 P14/AN04/SIN0_1/IC02_2/TIOB11_1/INT03_1/MAD12_0
65 P13/AN03/SCK1_1/IC01_2/TIOB10_1/RTCCO_1/SUBOUT_1/MAD11_0
64 P12/AN02/SOT1_1/IC00_2/TIOB9_1/MAD10_0
63 P11/AN01/SIN1_1/FRCK0_2/TIOB8_1/INT02_1/WKUP1/MAD09_0
62 P10/AN00
P3C/SIN11_0/RTO02_0/TIOA2_1/INT18_2 26
P3D/SOT11_0/RTO03_0/TIOA3_1 27
P3E/SCK11_0/RTO04_0/TIOA4_1/INT19_2 28
P3F/RTO05_0/TIOA5_1 29
VSS 30
61 VCC
Note:
−
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For
these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function
register (EPFR) to select the pin.
Document Number: 002-05646 Rev. *E
Page 9 of 149
CY9A150RB Series
3.2 LQI100
(TOP VIEW)
VCC
P50/SIN3_1/AIN0_2/TIOB8_0/INT00_0/MADATA00_0
P51/SOT3_1/BIN0_2/TIOB9_0/INT01_0/MADATA01_0
P52/SCK3_1/ZIN0_2/TIOB10_0/INT02_0/MADATA02_0
P53/SIN6_0/TIOB11_0/TIOA1_2/INT07_2/MADATA03_0
P54/SOT6_0/TIOB12_0/TIOB1_2/INT18_1/MADATA04_0
P55/ADTG_1/SCK6_0/TIOB13_0/INT19_1/MADATA05_0
P56/INT08_2/CEC1_1/MADATA06_0
1
2
3
4
5
6
7
8
9
75 VSS
74 P20/AN19/CROUT_0/AIN1_1/TIOA10_2/INT05_0/MAD24_0
73 P21/AN18/SIN0_0/BIN1_1/TIOB10_2/INT06_1/WKUP2
72 P22/AN17/SOT0_0/ZIN1_1/TIOB7_1
71 P23/AN16/SCK0_0/TIOA7_1
70 P1F/AN15/ADTG_5/FRCK0_1/TIOB9_2/MAD23_0
69 P1E/AN14/RTS4_1/DTTI0X_1/TIOA9_2/INT23_2/MAD22_0
68 P1D/AN13/CTS4_1/IC03_1/TIOA13_1/INT22_2/MAD21_0
67 P1C/AN12/SCK4_1/IC02_1/TIOA12_1/INT21_2/MAD20_0
66 P1B/AN11/SOT4_1/IC01_1/TIOA11_1/INT20_2/MAD19_0
65 P1A/AN10/SIN4_1/IC00_1/TIOA10_1/INT05_1/MAD18_0
64 P19/AN09/SCK2_2/TIOA9_1/MAD17_0
63 P18/AN08/SOT2_2/TIOA8_1/MAD16_0
62 AVSS
P30/AIN0_0/TIOB0_1/TIOA13_2/INT03_2/WKUP4/MADATA07_0
P31/SCK6_1/BIN0_0/TIOB1_1/TIOB13_2/INT04_2/MADATA08_0 10
P32/SOT6_1/ZIN0_0/TIOB2_1/INT05_2/MADATA09_0 11
P33/ADTG_6/SIN9_0/SIN6_1/TIOB3_1/INT04_0/MADATA10_0 12
P34/SOT9_0/FRCK0_0/TIOB4_1/TIOA15_2/MADATA11_0 13
P35/SCK9_0/IC03_0/TIOB5_1/TIOB15_2/INT08_1/MADATA12_0 14
P36/SIN5_2/IC02_0/TIOB14_0/INT09_1/MADATA13_0 15
P37/SOT5_2/IC01_0/TIOA14_0/INT10_1/MADATA14_0 16
P38/SCK5_2/IC00_0/TIOA8_2/INT11_1/MADATA15_0 17
P39/ADTG_2/SIN10_0/DTTI0X_0/TIOB8_2/INT06_0 18
P3A/SOT10_0/RTO00_0/TIOA0_1/INT07_0/RTCCO_2/SUBOUT_2 19
P3B/SCK10_0/RTO01_0/TIOA1_1 20
LQFP - 100
61 AVRH
60 AVCC
59 P17/AN07/SIN2_2/INT04_1/MAD15_0
58 P16/AN06/SCK0_1/TIOB13_1/INT15_0/MAD14_0
57 P15/AN05/SOT0_1/IC03_2/TIOB12_1/INT14_0/MAD13_0
56 P14/AN04/SIN0_1/IC02_2/TIOB11_1/INT03_1/MAD12_0
55 P13/AN03/SCK1_1/IC01_2/TIOB10_1/RTCCO_1/SUBOUT_1/MAD11_0
54 P12/AN02/SOT1_1/IC00_2/TIOB9_1/MAD10_0
53 P11/AN01/SIN1_1/FRCK0_2/TIOB8_1/INT02_1/WKUP1/MAD09_0
52 P10/AN00
P3C/SIN11_0/RTO02_0/TIOA2_1/INT18_2 21
P3D/SOT11_0/RTO03_0/TIOA3_1 22
P3E/SCK11_0/RTO04_0/TIOA4_1/INT19_2 23
P3F/RTO05_0/TIOA5_1 24
VSS 25
51 VCC
Note:
−
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For
these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function
register (EPFR) to select the pin.
Document Number: 002-05646 Rev. *E
Page 10 of 149
CY9A150RB Series
3.3 LQH080
(TOP VIEW)
VCC
P50/SIN3_1/AIN0_2/TIOB8_0/INT00_0/MADATA00_0
P51/SOT3_1/BIN0_2/TIOB9_0/INT01_0/MADATA01_0
P52/SCK3_1/ZIN0_2/TIOB10_0/INT02_0/MADATA02_0
P53/SIN6_0/TIOB11_0/TIOA1_2/INT07_2/MADATA03_0
P54/SOT6_0/TIOB12_0/TIOB1_2/INT18_1/MADATA04_0
P55/ADTG_1/SCK6_0/TIOB13_0/INT19_1/MADATA05_0
P56/INT08_2/CEC1_1/MADATA06_0
1
2
3
4
5
6
7
8
9
60 P20/AN19/CROUT_0/AIN1_1/TIOA10_2/INT05_0/MAD24_0
59 P21/AN18/SIN0_0/BIN1_1/TIOB10_2/INT06_1/WKUP2
58 P22/AN17/SOT0_0/ZIN1_1/TIOB7_1
57 P23/AN16/SCK0_0/TIOA7_1
56 P1B/AN11/SOT4_1/IC01_1/TIOA11_1/INT20_2/MAD19_0
55 P1A/AN10/SIN4_1/IC00_1/TIOA10_1/INT05_1/MAD18_0
54 P19/AN09/SCK2_2/TIOA9_1/MAD17_0
53 P18/AN08/SOT2_2/TIOA8_1/MAD16_0
52 AVSS
P30/AIN0_0/TIOB0_1/TIOA13_2/INT03_2/WKUP4/MADATA07_0
P31/SCK6_1/BIN0_0/TIOB1_1/TIOB13_2/INT04_2/MADATA08_0 10
P32/SOT6_1/ZIN0_0/TIOB2_1/INT05_2/MADATA09_0 11
P33/ADTG_6/SIN6_1/TIOB3_1/INT04_0/MADATA10_0 12
P39/ADTG_2/SIN10_0/DTTI0X_0/INT06_0 13
P3A/SOT10_0/RTO00_0/TIOA0_1/INT07_0/RTCCO_2/SUBOUT_2 14
P3B/SCK10_0/RTO01_0/TIOA1_1 15
51 AVRH
LQFP - 80
50 AVCC
49 P17/AN07/SIN2_2/INT04_1/MAD15_0
48 P16/AN06/SCK0_1/TIOB13_1/INT15_0/MAD14_0
47 P15/AN05/SOT0_1/IC03_2/TIOB12_1/INT14_0/MAD13_0
46 P14/AN04/SIN0_1/IC02_2/TIOB11_1/INT03_1/MAD12_0
45 P13/AN03/SCK1_1/IC01_2/TIOB10_1/RTCCO_1/SUBOUT_1/MAD11_0
44 P12/AN02/SOT1_1/IC00_2/TIOB9_1/MAD10_0
43 P11/AN01/SIN1_1/FRCK0_2/TIOB8_1/INT02_1/WKUP1/MAD09_0
42 P10/AN00
P3C/SIN11_0/RTO02_0/TIOA2_1/INT18_2 16
P3D/SOT11_0/RTO03_0/TIOA3_1 17
P3E/SCK11_0/RTO04_0/TIOA4_1/INT19_2 18
P3F/RTO05_0/TIOA5_1 19
VSS 20
41 VCC
Note:
−
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For
these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function
register (EPFR) to select the pin.
Document Number: 002-05646 Rev. *E
Page 11 of 149
CY9A150RB Series
3.4 LBC112
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
TMS/
SWDIO
A
B
C
D
E
F
VSS
VCC
P50
P53
P30
P34
P37
P3B
VCC
VCC
VSS
P81
VSS
P51
P54
P31
P35
P38
P3C
P3F
VSS
C
P80
P52
VSS
P55
P32
P36
P3A
P3E
VSS
X1A
X0A
VCC
P61
P60
VSS
P33
P39
P3D
VSS
P40
INITX
VSS
P0E
P0F
P62
P56
P0B
P0C
P0D
P63
P07
P08
P09
P0A
TRSTX
VCC
VSS
P20
VSS
TDI
TDO/
SWO
TCK/
SWCLK
P05
VSS
P22
VSS
P06
P21
P23
AN15
AN11
AVRH
AVSS
AVCC
AN00
VCC
Index
AN14
AN10
AN07
AN04
VSS
MD1
X0
AN12
AN09
AN06
AN03
AN01
VSS
X1
AN13
AN08
VSS
AN02
P4E
G
H
J
P44
P43
P42
P41
P4C
P49
P48
P45
AN05
P4D
P4B
P4A
K
L
MD0
VSS
Note:
−
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For
these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function
register (EPFR) to select the pin.
Document Number: 002-05646 Rev. *E
Page 12 of 149
CY9A150RB Series
3.5 FDG096
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
TMS/
SWDIO
A
B
C
D
E
F
VSS
VCC
P50
P53
P56
VSS
P32
P3A
P3D
VCC
VSS
P81
VSS
P51
P54
P30
VSS
P33
P3B
P3E
VSS
C
P80
P52
VSS
P55
P31
VSS
P39
P3C
VSS
X1A
X0A
VCC
P61
VSS
P63
P62
P0F
P0D
P0E
VSS
P0C
P0B
P07
TRSTX
VSS
P20
VSS
TDI
TDO/
SWO
TCK/
SWCLK
P60
P0A
VSS
P22
P21
Index
P23
VSS
AN11
AN08
AN06
AN04
VSS
MD1
X0
AN10
AN07
AN05
AN03
AN01
VSS
X1
AN09
AVRH
AVSS
AVCC
AN00
VCC
VSS
G
H
J
P3F
INITX
VSS
P48
P45
P44
P4A
P49
VSS
P4D
P4C
P4B
AN02
P4E
K
L
MD0
Note:
−
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For
these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function
register (EPFR) to select the pin.
Document Number: 002-05646 Rev. *E
Page 13 of 149
CY9A150RB Series
4. List of Pin Function
4.1 List of Pin Numbers
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these
pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR)
to select the pin.
Pin No
I/O
Pin State
Type
Circuit
Pin Name
LQFP-120 LQFP-100 BGA-112 LQFP-80
BGA-96
Type
1
2
1
2
B1
C1
1
2
B1
VCC
P50
-
SIN3_1
AIN0_2
TIOB8_0
INT00_0
MADATA00_0
P51
C1
E
K
SOT3_1
(SDA3_1)
BIN0_2
TIOB9_0
INT01_0
MADATA01_0
P52
3
4
5
3
4
5
C2
B3
D1
3
4
5
C2
E
E
E
K
SCK3_1
(SCL3_1)
ZIN0_2
TIOB10_0
INT02_0
B3
K
MADATA02_0
P53
SIN6_0
TIOB11_0
TIOA1_2
INT07_2
D1
K
MADATA03_0
Document Number: 002-05646 Rev. *E
Page 14 of 149
CY9A150RB Series
Pin No
I/O
Pin State
Circuit
Pin Name
Type
LQFP-120 LQFP-100 BGA-112 LQFP-80
BGA-96
Type
P54
SOT6_0
(SDA6_0)
TIOB12_0
TIOB1_2
INT18_1
6
6
D2
6
D2
E
K
MADATA04_0
P55
ADTG_1
SCK6_0
(SCL6_0)
7
7
D3
7
D3
E
K
TIOB13_0
INT19_1
MADATA05_0
P56
INT08_2
CEC1_1
MADATA06_0
SIN1_0
8
-
D5
8
-
E1
8
H[1]
R
-
-
TIOA8_0
P57
SOT1_0
H[1]
J
(SDA1_0)
9
-
-
-
-
TIOA9_0
MADATA07_0
P58
SCK1_0
H[1]
J
(SCL1_0)
10
-
-
-
-
TIOA10_0
MADATA08_0
Document Number: 002-05646 Rev. *E
Page 15 of 149
CY9A150RB Series
Pin No
I/O
Pin State
Circuit
Pin Name
Type
LQFP-120 LQFP-100 BGA-112 LQFP-80
BGA-96
Type
P59
SIN7_0
11
-
-
-
-
TIOA11_0
INT09_2
MADATA09_0
P5A
E
K
SOT7_0
(SDA7_0)
12
-
-
-
-
E
K
TIOA12_0
INT16_2
MADATA10_0
P5B
SCK7_0
(SCL7_0)
13
-
-
-
-
E
K
TIOA13_0
INT17_2
MADATA11_0
P30
AIN0_0
TIOB0_1
TIOA13_2
INT03_2
WKUP4
14
-
-
-
-
E
S
MADATA12_0
P30
AIN0_0
TIOB0_1
TIOA13_2
INT03_2
WKUP4
-
9
E1
9
E2
E
S
MADATA07_0
Document Number: 002-05646 Rev. *E
Page 16 of 149
CY9A150RB Series
Pin No
I/O Circuit
Pin State
Type
Pin Name
Type
LQFP-120 LQFP-100 BGA-112 LQFP-80
BGA-96
P31
SCK6_1
(SCL6_1)
BIN0_0
TIOB1_1
TIOB13_2
INT04_2
15
-
-
-
-
E
K
MADATA13_0
P31
SCK6_1
(SCL6_1)
BIN0_0
TIOB1_1
TIOB13_2
INT04_2
10
E2
10
E3
E
K
-
MADATA08_0
P32
SOT6_1
(SDA6_1)
ZIN0_0
TIOB2_1
INT05_2
MADATA14_0
P32
16
-
-
-
-
E
K
SOT6_1
(SDA6_1)
ZIN0_0
TIOB2_1
11
E3
11
G1
E
K
-
INT05_2
MADATA09_0
P33
ADTG_6
SIN9_0
17
-
-
-
-
SIN6_1
E
K
TIOB3_1
INT04_0
MADATA15_0
Document Number: 002-05646 Rev. *E
Page 17 of 149
CY9A150RB Series
Pin No
I/O Circuit
Pin State
Type
Pin Name
Type
LQFP-120 LQFP-100 BGA-112 LQFP-80
BGA-96
P33
ADTG_6
SIN6_1
12
G2
-
12
E4
TIOB3_1
INT04_0
MADATA10_0
SIN9_0
E
K
-
-
-
-
P34
SOT9_0
(SDA9_0)
FRCK0_0
TIOB4_1
TIOA15_2
MNALE_0
P34
18
-
-
E
J
SOT9_0
(SDA9_0)
FRCK0_0
TIOB4_1
TIOA15_2
-
13
F1
-
-
E
J
MADATA11_0
P35
SCK9_0
(SCL9_0)
IC03_0
TIOB5_1
TIOB15_2
INT08_1
MNCLE_0
19
-
-
-
-
E
K
P35
SCK9_0
(SCL9_0)
IC03_0
TIOB5_1
-
14
F2
-
-
E
K
TIOB15_2
INT08_1
MADATA12_0
Document Number: 002-05646 Rev. *E
Page 18 of 149
CY9A150RB Series
Pin No
I/O Circuit
Pin State
Type
Pin Name
Type
LQFP-120 LQFP-100 BGA-112 LQFP-80
BGA-96
P36
SIN5_2
IC02_0
TIOB14_0
INT09_1
MNWEX_0
P36
20
-
-
-
-
E
K
SIN5_2
IC02_0
TIOB14_0
INT09_1
MADATA13_0
VSS
-
15
F3
-
-
E
K
-
-
-
-
-
-
-
-
-
-
-
-
F1
F2
F3
-
-
-
VSS
VSS
P37
SOT5_2
(SDA5_2)
IC01_0
TIOA14_0
INT10_1
MNREX_0
P37
21
-
-
-
-
E
K
SOT5_2
(SDA5_2)
IC01_0
TIOA14_0
INT10_1
-
16
G1
-
-
E
K
MADATA14_0
Document Number: 002-05646 Rev. *E
Page 19 of 149
CY9A150RB Series
Pin No
I/O Circuit
Pin State
Type
Pin Name
Type
LQFP-120 LQFP-100 BGA-112 LQFP-80
BGA-96
P38
SCK5_2
(SCL5_2)
22
IC00_0
TIOA08_2
INT11_1
MADATA15_0
P39
17
G2
-
-
E
K
-
ADTG_2
SIN10_0
DTTI0X_0
INT06_0
TIOB8_2
P3A
13
G3
23
18
F4
E
K
-
-
SOT10_0
(SDA10_0)
RTO00_0
TIOA0_1
INT07_0
RTCCO_2
SUBOUT_2
P3B
24
19
G3
14
H1
E
K
SCK10_0
(SCL10_0)
25
20
H1
15
H2
E
J
RTO01_0
TIOA1_1
P3C
SIN11_0
RTO02_0
TIOA2_1
INT18_2
26
21
H2
16
H3
E
K
Document Number: 002-05646 Rev. *E
Page 20 of 149
CY9A150RB Series
Pin No
I/O Circuit
Pin State
Type
Pin Name
Type
LQFP-120 LQFP-100 BGA-112
LQFP-80
BGA-96
P3D
SOT11_0
(SDA11_0)
27
22
G4
B2
17
J1
E
J
RTO03_0
TIOA3_1
VSS
-
-
-
B2
-
P3E
SCK11_0
(SCL11_0)
28
23
H3
18
J2
E
K
RTO04_0
TIOA4_1
INT19_2
P3F
29
24
J2
19
J4
RTO05_0
TIOA5_1
VSS
E
J
30
31
25
26
L1
J1
20
-
L1
-
-
-
VCC
P40
SIN12_0
TIOA0_0
INT12_1
P41
32
27
J4
-
-
E
K
SOT12_0
(SDA12_0)
33
28
L5
-
-
E
K
TIOA1_0
INT13_1
P42
SCK12_0
(SCL12_0)
34
29
K5
-
-
E
K
TIOA2_0
INT08_0
Document Number: 002-05646 Rev. *E
Page 21 of 149
CY9A150RB Series
Pin No
I/O Circuit
Pin State
Type
Pin Name
Type
LQFP-120 LQFP-100 BGA-112
LQFP-80
BGA-96
P43
ADTG_7
SIN13_0
TIOA3_0
INT09_0
P44
35
30
J5
-
-
E
K
21
-
L5
-
SOT13_0
(SDA13_0)
36
31
H5
E
K
TIOA4_0
INT10_0
MAD00_0
P45
21
L5
22
-
K5
-
SCK13_0
TIOA5_0
INT11_0
MAD01_0
VSS
37
32
L6
E
K
22
K5
-
-
-
-
K2
J3
H4
-
-
-
K2
J3
-
-
-
-
-
-
-
-
VSS
VSS
-
-
-
-
-
-
L6
L2
L4
K1
VSS
38
39
40
33
34
35
L2
L4
K1
23
24
25
C
VSS
VCC
P46
41
36
L3
26
L3
D
F
X0A
P47
42
43
37
38
K3
K4
27
28
K3
K4
D
B
G
C
X1A
INITX
P48
SIN3_2
INT14_1
MAD02_0
44
39
K6
29
J5
E
K
Document Number: 002-05646 Rev. *E
Page 22 of 149
CY9A150RB Series
Pin No
I/O Circuit
Pin State
Type
Pin Name
Type
LQFP-120 LQFP-100 BGA-112
LQFP-80
BGA-96
P49
SOT3_2
(SDA3_2)
AIN0_1
TIOB0_0
INT20_1
MAD03_0
P4A
45
40
J6
30
K6
E
K
SCK3_2
(SCL3_2)
BIN0_1
TIOB1_0
INT21_1
MAD04_0
P4B
46
41
L7
31
J6
E
K
IGTRG_0
ZIN0_1
47
42
K7
32
L7
E
K
TIOB2_0
INT22_1
MAD05_0
P4C
SCK7_1
(SCL7_1)
AIN1_2
TIOB3_0
INT12_0
CEC0_0
MAD06_0
48
43
H6
33
K7
H[1]
R
Document Number: 002-05646 Rev. *E
Page 23 of 149
CY9A150RB Series
Pin No
I/O Circuit
Pin State
Type
Pin Name
Type
LQFP-120 LQFP-100 BGA-112 LQFP-80
BGA-96
P4D
SOT7_1
(SDA7_1)
H[1]
K
BIN1_2
TIOB4_0
INT13_0
MAD07_0
P4E
49
44
J7
34
J7
SIN7_1
ZIN1_2
TIOB5_0
INT06_2
MAD08_0
SIN14_0
P70
45
K8
35
K8
50
H[1]
K
-
-
-
-
-
-
-
-
SOT14_0
51
E
J
(SDA14_0)
TIOA4_2
P71
SCK14_0
(SCL14_0)
52
-
-
-
-
-
-
-
-
-
-
-
-
E
K
TIOB4_2
INT13_2
P72
SIN2_0
TIOA6_0
INT14_2
P73
53
E
K
SOT2_0
(SDA2_0)
54
E
K
TIOB6_0
INT15_2
Document Number: 002-05646 Rev. *E
Page 24 of 149
CY9A150RB Series
Pin No
I/O Circuit
Pin State
Type
Pin Name
Type
LQFP-120 LQFP-100 BGA-112 LQFP-80
BGA-96
P74
55
-
-
-
-
E
J
SCK2_0
(SCL2_0)
MD1
PE0
56
57
58
46
47
48
K9
L8
L9
36
37
38
K9
L8
L9
C
G
A
E
D
A
MD0
X0
PE2
X1
59
49
L10
39
L10
A
B
PE3
60
61
50
51
L11
K11
40
41
L11
K11
VSS
-
-
VCC
P10
62
52
J11
42
J11
F
L
AN00
P11
AN01
SIN1_1
FRCK0_2
TIOB8_1
INT02_1
WKUP1
MAD09_0
P12
63
53
J10
43
J10
F
P
AN02
SOT1_1
(SDA1_1)
64
54
J8
44
J8
F
L
IC00_2
TIOB9_1
MAD10_0
VSS
-
-
-
-
K10
J9
-
-
K10
J9
-
-
VSS
Document Number: 002-05646 Rev. *E
Page 25 of 149
CY9A150RB Series
Pin No
I/O Circuit
Pin State
Type
Pin Name
Type
LQFP-120 LQFP-100 BGA-112 LQFP-80
BGA-96
P13
AN03
SCK1_1
(SCL1_1)
IC01_2
TIOB10_1
RTCCO_1
SUBOUT_1
MAD11_0
P14
65
55
H10
45
H10
F
L
AN04
SIN0_1
IC02_2
66
56
H9
46
H9
F
M
TIOB11_1
INT03_1
MAD12_0
P15
AN05
SOT0_1
(SDA0_1)
67
57
H7
47
G10
F
M
IC03_2
TIOB12_1
INT14_0
MAD13_0
Document Number: 002-05646 Rev. *E
Page 26 of 149
CY9A150RB Series
Pin No
I/O Circuit
Pin State
Type
Pin Name
Type
LQFP-120
LQFP-100
BGA-112
LQFP-80
BGA-96
P16
AN06
SCK0_1
(SCL0_1)
68
58
G10
48
G9
F
M
TIOB13_1
INT15_0
MAD14_0
P17
AN07
69
59
G9
49
F10
SIN2_2
INT04_1
MAD15_0
AVCC
AVRH
AVSS
F
M
70
71
72
60
61
62
H11
F11
G11
50
51
52
H11
F11
G11
-
-
-
P18
AN08
SOT2_2
73
63
G8
53
F9
F
L
(SDA2_2)
TIOA8_1
MAD16_0
P19
AN09
SCK2_2
74
64
F10
H8
54
E11
F
L
(SCL2_2)
TIOA9_1
MAD17_0
-
-
-
-
VSS
P1A
-
AN10
SIN4_1
IC00_1
TIOA10_1
INT05_1
MAD18_0
75
65
F9
55
E10
F
M
Document Number: 002-05646 Rev. *E
Page 27 of 149
CY9A150RB Series
Pin No
I/O Circuit
Pin State
Type
Pin Name
Type
LQFP-120
LQFP-100
BGA-112
LQFP-80
BGA-96
P1B
AN11
SOT4_1
(SDA4_1)
76
66
E11
56
E9
F
M
IC01_1
TIOA11_1
INT20_2
MAD19_0
P1C
AN12
SCK4_1
(SCL4_1)
77
67
E10
-
-
F
M
IC02_1
TIOA12_1
INT21_2
MAD20_0
P1D
AN13
CTS4_1
IC03_1
TIOA13_1
INT22_2
MAD21_0
P1E
78
68
69
70
F8
-
-
-
-
-
-
F
M
AN14
RTS4_1
DTTI0X_1
TIOA9_2
INT23_2
MAD22_0
P1F
79
E9
F
M
AN15
ADTG_5
FRCK0_1
TIOB9_2
MAD23_0
D11
80
F
L
SCK15_0
-
-
-
-
-
-
(SCL15_0)
-
B10
B10
VSS
-
Document Number: 002-05646 Rev. *E
Page 28 of 149
CY9A150RB Series
Pin No
I/O Circuit
Pin State
Type
Pin Name
Type
LQFP-120
LQFP-100
BGA-112
LQFP-80
BGA-96
-
-
-
-
C9
-
-
-
C9
VSS
VSS
-
-
D11
P28
ADTG_4
SOT15_0
81
-
-
-
-
E
J
(SDA15_0)
RTO05_1
TIOB6_2
P27
SIN15_0
RTO04_1
TIOA6_2
INT02_2
P26
82
-
-
-
-
E
K
SCK2_1
(SCL2_1)
83
-
-
-
-
E
J
RTO03_1
TIOA11_2
P25
SOT2_1
(SDA2_1)
84
-
-
-
-
E
J
RTO02_1
TIOA14_1
TIOB11_2
P24
SIN2_1
RTO01_1
TIOB14_1
85
-
-
-
-
E
K
INT01_2
P23
AN16
71
D10
57
D10
SCK0_0
86
F
L
(SCL0_0)
TIOA7_1
RTO00_1
-
-
-
-
Document Number: 002-05646 Rev. *E
Page 29 of 149
CY9A150RB Series
Pin No
I/O Circuit
Pin State
Type
Pin Name
Type
LQFP-120
LQFP-100
BGA-112
LQFP-80
BGA-96
P22
AN17
SOT0_0
87
72
E8
58
D9
F
L
(SDA0_0)
ZIN1_1
TIOB7_1
P21
AN18
SIN0_0
BIN1_1
TIOB10_2
INT06_1
WKUP2
P20
88
73
C11
59
C11
F
P
AN19
CROUT_0
AIN1_1
TIOA10_2
INT05_0
MAD24_0
VSS
89
74
C10
60
C10
F
M
90
91
75
76
A11
A10
-
-
A11
-
-
-
VCC
P00
TRSTX
TIOA14_2
MCSX7_0
61
A10
92
77
A9
E
I
SCK8_0
-
-
(SCL8_0)
P01
TCK
93
94
78
79
B9
62
B9
E
E
I
I
SWCLK
P02
TDI
63
-
B11
-
TIOB14_2
MCSX6_0
B11
SOT8_0
Document Number: 002-05646 Rev. *E
Page 30 of 149
CY9A150RB Series
Pin No
I/O Circuit
Pin State
Type
Pin Name
Type
LQFP-120
LQFP-100
BGA-112
LQFP-80
BGA-96
P03
TMS
95
80
A8
B8
64
A9
E
I
I
SWDIO
P04
96
81
65
B8
TDO
E
SWO
P05
AN20
TRACED0
SIN8_0
SIN4_2
TIOA5_2
INT00_1
MCSX5_0
97
82
C8
-
-
F
O
-
-
D8
D9
-
-
-
-
VSS
P06
-
AN21
TRACED1
SOT4_2
98
83
F
O
(SDA4_2)
TIOB5_2
INT01_1
MCSX4_0
P07
AN22
66
A8
ADTG_0
MCLKOUT_0
INT23_1
TRACED2
99
84
A7
F
O
-
-
-
SCK4_2
(SCL4_2)
-
-
-
A7
VSS
-
Document Number: 002-05646 Rev. *E
Page 31 of 149
CY9A150RB Series
Pin No
I/O Circuit
Pin State
Type
Pin Name
Type
LQFP-120
LQFP-100
BGA-112
LQFP-80
BGA-96
P08
AN23
TRACED3
CTS4_2
TIOA0_2
INT16_0
MCSX3_0
P09
100
85
B7
-
-
F
O
TRACECLK
RTS4_2
TIOB0_2
INT17_0
MCSX2_0
P0A
101
86
C7
-
-
E
N
SIN4_0
INT00_2
WKUP5
MCSX1_0
P0B
102
87
D7
67
C8
H[1]
S
SOT4_0
(SDA4_0)
H[1]
R
TIOB6_1
INT18_0
CEC0_1
MCSX0_0
P0C
103
88
A6
68
C7
SCK4_0
(SCL4_0)
104
89
B6
D4
69
B7
H[1]
K
TIOA6_1
INT19_0
MALE_0
VSS
-
-
-
-
-
Document Number: 002-05646 Rev. *E
Page 32 of 149
CY9A150RB Series
Pin No
I/O Circuit
Pin State
Type
Pin Name
Type
LQFP-120
LQFP-100
BGA-112
LQFP-80
BGA-96
-
-
C3
-
C3
VSS
P0D
-
RTS4_0
TIOA3_2
INT20_0
MDQM0_0
P0E
105
90
C6
70
B6
E
K
CTS4_0
TIOB3_2
INT21_0
MDQM1_0
VSS
106
91
A5
71
C6
A5
E
K
-
-
-
-
-
P0F
NMIX
CROUT_1
107
92
B5
72
A6
E
H
RTCCO_0
SUBOUT_0
WKUP0
P68
SCK3_0
108
-
-
-
-
E
K
(SCL3_0)
TIOB7_2
INT12_2
P67
SOT3_0
(SDA3_0)
109
-
-
-
-
E
K
TIOA7_2
INT22_0
P66
SIN3_0
TIOA12_2
110
-
-
-
-
E
K
INT11_2
Document Number: 002-05646 Rev. *E
Page 33 of 149
CY9A150RB Series
Pin No
I/O Circuit
Pin State
Type
Pin Name
Type
LQFP-120
LQFP-100
BGA-112
LQFP-80
BGA-96
P65
SCK5_1
(SCL5_1)
111
-
-
-
-
E
K
TIOB7_0
TIOB12_2
INT23_0
P64
SOT5_1
(SDA5_1)
112
-
-
-
-
E
K
TIOA7_0
INT10_2
P63
TIOB15_1
93
-
D6
-
73
-
B5
-
113
E
K
INT03_0
MWEX_0
SIN5_1
P62
ADTG_3
SCK5_0
(SCL5_0)
114
94
C5
74
C5
E
K
TIOA15_1
INT07_1
MOEX_0
P61
SOT5_0
115
95
B4
75
B4
E
J
(SDA5_0)
TIOB2_2
P60
SIN5_0
IGTRG_1
TIOA2_2
INT15_1
WKUP3
CEC1_0
MRDY_0
116
96
C4
76
C4
H[1]
Q
Document Number: 002-05646 Rev. *E
Page 34 of 149
CY9A150RB Series
Pin No
BGA-112
A4
I/O Circuit
Pin State
Type
Pin Name
Type
LQFP-120
LQFP-100
LQFP-80
BGA-96
117
97
77
A4
VCC
P80
-
118
119
98
A3
78
A3
TIOB15_0
INT16_1
P81
E
E
K
K
99
A2
A1
79
80
A2
A1
TIOA15_0
INT17_1
VSS
120
100
-
[1]. 5V tolerant I/O
Document Number: 002-05646 Rev. *E
Page 35 of 149
CY9A150RB Series
4.2 List of Pin Functions
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these
pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR)
to select the pin.
Pin No
Pin
Pin
Function Description
Function
Name
LQFP-120 LQFP-100 BGA-112 LQFP-80 BGA-96
ADC
ADTG_0
ADTG_1
ADTG_2
ADTG_3
ADTG_4
ADTG_5
ADTG_6
ADTG_7
ADTG_8
AN00
99
7
84
7
A7
D3
F4
66
7
A8
D3
G3
C5
-
23
114
81
80
17
35
-
18
94
-
13
74
-
C5
-
A/D converter external trigger
input pin
70
12
30
-
D11
E4
-
-
12
-
G2
-
J5
-
-
-
62
63
64
65
66
67
68
69
73
74
75
76
77
78
79
80
86
87
88
89
97
98
52
53
54
55
56
57
58
59
63
64
65
66
67
68
69
70
71
72
73
74
82
83
J11
J10
J8
42
43
44
45
46
47
48
49
53
54
55
56
-
J11
J10
J8
H10
H9
G10
G9
F10
F9
E11
E10
E9
-
AN01
AN02
AN03
H10
H9
H7
G10
G9
G8
F10
F9
AN04
AN05
AN06
AN07
AN08
AN09
AN10
AN11
E11
E10
F8
A/D converter analog input pin.
ANxx describes ADC ch.xx.
AN12
AN13
-
-
AN14
E9
-
-
AN15
D11
D10
E8
-
-
AN16
57
58
59
60
-
D10
D9
C11
C10
-
AN17
AN18
C11
C10
C8
D9
AN19
AN20
AN21
-
-
AN22
AN23
99
84
85
A7
B7
66
-
A8
-
100
Document Number: 002-05646 Rev. *E
Page 36 of 149
CY9A150RB Series
Pin No
LQFP-120 LQFP-100 BGA-112 LQFP-80 BGA-96
Pin
Function
Pin Function
Name
Description
Base Timer 0
TIOA0_0
TIOA0_1
TIOA0_2
TIOB0_0
TIOB0_1
TIOB0_2
TIOA1_0
TIOA1_1
TIOA1_2
TIOB1_0
TIOB1_1
TIOB1_2
TIOA2_0
TIOA2_1
TIOA2_2
TIOB2_0
TIOB2_1
TIOB2_2
TIOA3_0
TIOA3_1
TIOA3_2
TIOB3_0
TIOB3_1
32
24
100
45
14
101
33
25
5
27
19
85
40
9
J4
G3
B7
J6
-
-
Base timer ch.0 TIOA pin
Base timer ch.0 TIOB pin
Base timer ch.1 TIOA pin
Base timer ch.1 TIOB pin
Base timer ch.2 TIOA pin
Base timer ch.2 TIOB pin
Base timer ch.3 TIOA pin
Base timer ch.3 TIOB pin
14
-
H1
-
30
9
K6
E2
-
E1
C7
L5
86
28
20
5
-
Base Timer 1
Base Timer 2
Base Timer 3
-
-
H1
D1
L7
15
5
H2
D1
J6
E3
D2
-
46
15
6
41
10
6
31
10
6
E2
D2
K5
H2
C4
K7
E3
B4
J5
34
26
116
47
16
115
35
27
105
48
17
29
21
96
42
11
95
30
22
90
43
12
-
16
76
32
11
75
-
H3
C4
L7
G1
B4
-
G4
C6
H6
E4
17
70
33
12
J1
B6
K7
G2
TIOB3_2
TIOA4_0
TIOA4_1
TIOA4_2
TIOB4_0
TIOB4_1
TIOB4_2
TIOA5_0
TIOA5_1
TIOA5_2
TIOB5_0
TIOB5_1
106
36
28
51
49
18
52
37
29
97
50
19
91
31
23
-
A5
H5
H3
-
71
21
18
-
C6
L5
J2
-
Base Timer 4
Base timer ch.4 TIOA pin
Base timer ch.4 TIOB pin
Base timer ch.5 TIOA pin
Base timer ch.5 TIOB pin
44
13
-
J7
F1
-
34
-
J7
-
-
-
Base Timer 5
32
24
82
45
14
L6
J2
C8
K8
F2
22
19
-
K5
J4
-
35
-
K8
-
TIOB5_2
98
83
D9
-
-
Document Number: 002-05646 Rev. *E
Page 37 of 149
CY9A150RB Series
Pin No
LQFP-120 LQFP-100 BGA-112 LQFP-80 BGA-96
Pin
Function
Pin Function
Name
Description
Base Timer 6
TIOA6_0
TIOA6_1
TIOA6_2
TIOB6_0
TIOB6_1
TIOB6_2
53
104
82
-
89
-
-
B6
-
-
69
-
-
B7
-
Base timer ch.6 TIOA pin
Base timer ch.6 TIOB pin
54
-
-
-
-
103
81
88
-
A6
-
68
-
C7
-
Base Timer 7
Base Timer 8
Base Timer 9
TIOA7_0
TIOA7_1
TIOA7_2
TIOB7_0
TIOB7_1
TIOB7_2
TIOA8_0
TIOA8_1
TIOA8_2
TIOB8_0
TIOB8_1
TIOB8_2
TIOA9_0
TIOA9_1
TIOA9_2
TIOB9_0
TIOB9_1
112
86
109
111
87
108
8
-
-
D10
-
-
57
-
-
D10
-
Base timer ch.7 TIOA pin
Base timer ch.7 TIOB pin
Base timer ch.8 TIOA pin
Base timer ch.8 TIOB pin
Base timer ch.9 TIOA pin
Base timer ch.9 TIOB pin
71
-
-
-
-
-
72
-
E8
-
58
-
D9
-
8
D5
G8
G2
C1
J10
F4
-
8
E1
F9
-
73
22
2
63
17
2
53
-
2
C1
J10
-
63
23
9
53
18
-
43
-
-
-
74
79
3
64
69
3
F10
E9
C2
J8
54
-
E11
-
3
C2
J8
64
54
44
TIOB9_2
TIOA10_0
TIOA10_1
TIOA10_2
TIOB10_0
TIOB10_1
TIOB10_2
80
10
75
89
4
70
-
D11
-
-
-
Base Timer 10
-
-
Base timer ch.10 TIOA
pin
65
74
4
F9
55
60
4
E10
C10
B3
C10
B3
Base timer ch.10 TIOB
pin
65
88
55
73
H10
C11
45
59
H10
C11
Base Timer 11
TIOA11_0
TIOA11_1
TIOA11_2
TIOB11_0
TIOB11_1
TIOB11_2
11
76
83
5
-
66
-
-
E11
-
-
56
-
-
E9
-
Base timer ch.11 TIOA
pin
5
D1
H9
-
5
D1
H9
-
Base timer ch.11 TIOB
pin
66
84
56
-
46
-
Document Number: 002-05646 Rev. *E
Page 38 of 149
CY9A150RB Series
Pin No
LQFP-120 LQFP-100 BGA-112 LQFP-80 BGA-96
Pin
Function
Pin Function
Name
Description
Base Timer 12
TIOA12_0
TIOA12_1
TIOA12_2
TIOB12_0
TIOB12_1
TIOB12_2
TIOA13_0
TIOA13_1
TIOA13_2
TIOB13_0
TIOB13_1
TIOB13_2
TIOA14_0
TIOA14_1
TIOA14_2
TIOB14_0
TIOB14_1
TIOB14_2
TIOA15_0
TIOA15_1
TIOA15_2
TIOB15_0
TIOB15_1
TIOB15_2
12
77
110
6
-
-
E10
-
-
-
-
-
Base timer ch.12 TIOA
pin
67
-
-
-
6
D2
H7
-
6
D2
G10
-
Base timer ch.12 TIOB
pin
67
111
13
78
14
7
57
-
47
-
Base Timer 13
Base Timer 14
Base Timer 15
-
-
-
-
Base timer ch.13 TIOA
pin
68
9
F8
E1
D3
G10
E2
G1
-
-
-
9
E2
D3
G9
E3
-
7
7
Base timer ch.13 TIOB
pin
68
15
21
84
92
20
85
94
119
114
18
118
113
19
58
10
16
-
48
10
-
Base timer ch.14 TIOA
pin
-
-
77
15
-
A9
F3
-
61
-
A10
-
Base timer ch.14 TIOB
pin
-
-
79
99
94
13
98
93
14
B11
A2
C5
F1
A3
D6
F2
63
79
74
-
B11
A2
C5
-
Base timer ch.15 TIOA
pin
78
73
-
A3
B5
-
Base timer ch.15 TIOB
pin
Document Number: 002-05646 Rev. *E
Page 39 of 149
CY9A150RB Series
Pin No
LQFP-120 LQFP-100 BGA-112 LQFP-80 BGA-96
Pin Function Pin Name
Function Description
Serial wire debug interface
clock input pin
SWCLK
SWDIO
SWO
93
95
96
78
80
81
B9
A8
B8
62
64
65
B9
A9
B8
Serial wire debug interface
data input / output pin
Serial wire viewer output
pin
TCK
TDI
JTAG test clock input pin
JTAG test data input pin
JTAG debug data output
pin
93
94
78
79
B9
62
63
B9
B11
B11
TDO
96
95
81
80
86
B8
A8
C7
65
64
-
B8
A9
-
Debugger
JTAG test mode state
input/output pin
TMS
Trace CLK output pin of
ETM
TRACECLK
101
TRACED0
TRACED1
TRACED2
TRACED3
TRSTX
97
98
99
100
92
36
37
44
45
46
47
48
49
50
63
64
65
66
67
68
69
73
82
83
84
85
77
31
32
39
40
41
42
43
44
45
53
54
55
56
57
58
59
63
C8
D9
A7
B7
A9
H5
L6
-
-
-
-
Trace data output pin of
ETM
-
-
-
-
JTAG test reset input pin
61
21
22
29
30
31
32
33
34
35
43
44
45
46
47
48
49
53
A10
L5
K5
J5
External
Bus
MAD00_0
MAD01_0
MAD02_0
MAD03_0
MAD04_0
MAD05_0
MAD06_0
MAD07_0
MAD08_0
MAD09_0
MAD10_0
MAD11_0
MAD12_0
MAD13_0
MAD14_0
MAD15_0
MAD16_0
K6
J6
K6
J6
L7
K7
H6
J7
L7
K7
J7
K8
J10
J8
K8
J10
J8
H10
H9
H7
G10
G9
G8
H10
H9
G10
G9
F10
F9
External bus interface
address bus
MAD17_0
MAD18_0
MAD19_0
MAD20_0
74
75
76
77
64
65
66
67
F10
F9
54
55
56
-
E11
E10
E9
-
E11
E10
MAD21_0
MAD22_0
MAD23_0
78
79
80
68
69
70
F8
E9
-
-
-
-
-
-
D11
MAD24_0
89
74
C10
60
C10
Document Number: 002-05646 Rev. *E
Page 40 of 149
CY9A150RB Series
Pin No
LQFP-120 LQFP-100 BGA-112 LQFP-80 BGA-96
Pin Function
Pin Name
Function Description
MCSX0_0
MCSX1_0
MCSX2_0
MCSX3_0
MCSX4_0
MCSX5_0
MCSX6_0
MCSX7_0
MDQM0_0
MDQM1_0
103
102
101
100
98
88
87
86
85
83
82
79
77
90
91
A6
D7
C7
B7
D9
C8
B11
A9
C6
A5
68
67
-
C7
C8
-
-
-
External bus interface chip
select output pin
-
-
97
-
-
94
63
61
70
71
B11
A10
B6
C6
92
105
106
External bus interface byte
mask signal output pin
External bus interface read
enable signal for SRAM
MOEX_0
MWEX_0
114
113
94
93
C5
D6
74
73
C5
B5
External bus interface write
enable signal for SRAM
External bus interface ALE
signal to control NAND
Flash memory output pin
External bus interface CLE
signal to control NAND
Flash memory output pin
External bus interface read
enable signal to control
NAND Flash memory
MNALE_0
MNCLE_0
MNREX_0
MNWEX_0
18
19
21
20
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
External Bus
External bus interface write
enable signal to control
NAND Flash memory
MADATA00_0
MADATA01_0
MADATA02_0
MADATA03_0
MADATA04_0
MADATA05_0
MADATA06_0
2
3
4
5
6
7
8
2
3
4
5
6
7
8
C1
C2
B3
D1
D2
D3
D5
2
3
4
5
6
7
8
C1
C2
B3
D1
D2
D3
E1
External bus interface data
bus
MADATA07_0
9
9
E1
9
E2
MADATA08_0
MADATA09_0
MADATA10_0
MADATA11_0
10
11
12
13
10
11
12
13
E2
E3
E4
F1
10
11
12
-
E3
G1
G2
-
MADATA12_0
14
14
F2
-
-
Document Number: 002-05646 Rev. *E
Page 41 of 149
CY9A150RB Series
Pin No
LQFP-120 LQFP-100 BGA-112 LQFP-80 BGA-96
Pin Function
Pin Name
Function Description
MADATA13_0
MADATA14_0
MADATA15_0
15
16
17
15
16
17
F3
G1
G2
-
-
-
-
-
-
Latch enable signal for
multiplex
External Bus
MALE_0
MRDY_0
104
116
99
89
96
84
B6
C4
A7
69
76
66
B7
C4
A8
External RDY input signal
External bus clock output
pin
MCLKOUT_0
INT00_0
INT00_1
INT00_2
INT01_0
INT01_1
INT01_2
INT02_0
INT02_1
INT02_2
INT03_0
INT03_1
INT03_2
INT04_0
INT04_1
INT04_2
INT05_0
INT05_1
INT05_2
INT06_0
INT06_1
INT06_2
INT07_0
INT07_1
INT07_2
INT08_0
INT08_1
INT08_2
INT09_0
2
97
102
3
2
C1
C8
D7
C2
D9
-
2
-
C1
-
External interrupt request
00 input pin
82
87
3
67
3
C8
C2
-
External interrupt request
01 input pin
98
85
4
83
-
-
-
-
4
B3
J10
-
4
B3
J10
-
External interrupt request
02 input pin
63
82
113
66
14
17
69
15
89
75
16
23
88
50
24
114
5
53
-
43
-
93
56
9
D6
H9
E1
E4
G9
E2
C10
F9
E3
F4
C11
K8
G3
C5
D1
K5
F2
D5
J5
73
46
9
B5
H9
E2
G2
F10
E3
C10
E10
G1
G3
C11
K8
H1
C5
D1
-
External interrupt request
03 input pin
12
59
10
74
65
11
18
73
45
19
94
5
12
49
10
60
55
11
13
59
35
14
74
5
External interrupt request
04 input pin
External interrupt request
05 input pin
External
Interrupt
External interrupt request
06 input pin
External interrupt request
07 input pin
34
19
8
29
14
8
-
External interrupt request
08 input pin
-
-
8
E1
-
35
30
-
External interrupt request
09 input pin
INT09_1
20
15
F3
-
-
INT09_2
INT10_0
INT10_1
INT10_2
INT11_0
INT11_1
11
36
-
-
-
21
-
-
L5
-
31
16
-
H5
G1
-
External interrupt request
10 input pin
21
112
37
-
-
32
17
L6
G2
22
-
K5
-
External interrupt request
11 input pin
22
INT11_2
110
-
-
-
-
Document Number: 002-05646 Rev. *E
Page 42 of 149
CY9A150RB Series
Pin No
LQFP-120 LQFP-100 BGA-112 LQFP-80 BGA-96
Pin Function
Pin Name
Function Description
INT12_0
INT12_1
INT12_2
48
32
43
27
-
H6
J4
-
33
-
K7
External interrupt request 12
input pin
-
-
108
-
INT13_0
INT13_1
INT13_2
INT14_0
INT14_1
INT14_2
INT15_0
INT15_1
INT15_2
INT16_0
INT16_1
INT16_2
INT17_0
INT17_1
INT17_2
INT18_0
INT18_1
INT18_2
INT19_0
INT19_1
49
33
44
28
-
J7
L5
-
34
-
J7
-
External interrupt request 13
input pin
52
-
-
67
57
39
-
H7
K6
-
47
29
-
G10
J5
-
External interrupt request 14
input pin
44
53
68
58
96
-
G10
C4
-
48
76
-
G9
C4
-
External interrupt request 15
input pin
116
54
100
118
12
85
98
-
B7
A3
-
-
-
External interrupt request 16
input pin
78
-
A3
-
101
119
13
86
99
-
C7
A2
-
-
-
External interrupt request 17
input pin
79
-
A2
-
103
6
88
6
A6
D2
H2
B6
D3
68
6
C7
D2
H3
B7
D3
External interrupt request 18
input pin
External
Interrupt
26
21
89
7
16
69
7
104
7
External interrupt request 19
input pin
INT19_2
INT20_0
INT20_1
INT20_2
INT21_0
INT21_1
INT21_2
INT22_0
INT22_1
INT22_2
INT23_0
INT23_1
INT23_2
28
105
45
23
90
40
66
91
41
67
-
H3
C6
J6
18
70
30
56
71
31
-
J2
B6
K6
E9
C6
J6
-
External interrupt request 20
input pin
76
E11
A5
L7
E10
-
106
46
External interrupt request 21
input pin
77
109
47
-
-
External interrupt request 22
input pin
42
68
-
K7
F8
-
32
-
L7
-
78
111
99
-
-
External interrupt request 23
input pin
84
69
A7
E9
66
-
A8
-
79
Non-Maskable Interrupt
input pin
NMIX
107
92
B5
72
A6
Document Number: 002-05646 Rev. *E
Page 43 of 149
CY9A150RB Series
Pin
Pin No
LQFP-120 LQFP-100 BGA-112 LQFP-80 BGA-96
Pin Function
Function Description
Name
P00
P01
P02
P03
P04
P05
P06
P07
P08
P09
P0A
P0B
P0C
P0D
P0E
P0F
P10
P11
P12
P13
P14
P15
P16
P17
P18
P19
P1A
P1B
P1C
P1D
P1E
P1F
P20
P21
P22
92
93
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
52
53
54
55
56
57
58
59
63
64
65
66
67
68
69
70
74
73
72
A9
B9
61
62
63
64
65
-
A10
B9
B11
A9
B8
-
94
B11
A8
95
96
B8
97
C8
98
D9
-
-
99
A7
66
-
A8
-
General-purpose I/O port 0
100
101
102
103
104
105
106
107
62
B7
C7
-
-
D7
67
68
69
70
71
72
42
43
44
45
46
47
48
49
53
54
55
56
-
C8
C7
B7
B6
C6
A6
J11
J10
J8
A6
B6
C6
A5
B5
J11
J10
J8
63
64
65
H10
H9
H10
H9
G10
G9
F10
F9
E11
E10
E9
-
66
GPIO
67
H7
68
G10
G9
G8
F10
F9
69
General-purpose I/O port 1
73
74
75
76
E11
E10
F8
77
78
-
-
79
E9
-
-
80
D11
C10
C11
E8
-
-
89
60
59
58
C10
C11
D9
88
87
P23
P24
P25
P26
P27
P28
86
85
84
83
82
81
71
-
D10
57
-
D10
-
-
-
-
-
-
-
-
-
-
General-purpose I/O port 2
-
-
-
-
-
-
-
-
Document Number: 002-05646 Rev. *E
Page 44 of 149
CY9A150RB Series
Pin No
LQFP-120 LQFP-100 BGA-112 LQFP-80 BGA-96
Pin
Pin Function
Function Description
Name
P30
P31
P32
P33
P34
P35
P36
P37
P38
P39
P3A
P3B
P3C
P3D
P3E
P3F
P40
P41
P42
P43
P44
P45
P46
P47
P48
P49
P4A
P4B
P4C
P4D
P4E
P50
P51
P52
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
32
33
34
35
36
37
41
42
44
45
46
47
48
49
50
2
9
E1
E2
E3
E4
F1
F2
F3
G1
G2
F4
G3
H1
H2
G4
H3
J2
9
10
11
12
-
E2
E3
G1
G2
-
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
27
28
29
30
31
32
36
37
39
40
41
42
43
44
45
2
-
-
-
-
-
-
General-purpose I/O port 3
-
-
13
14
15
16
17
18
19
-
G3
H1
H2
H3
J1
J2
J4
-
J4
L5
K5
J5
-
-
-
-
-
-
H5
L6
L3
K3
K6
J6
21
22
26
27
29
30
31
32
33
34
35
2
L5
K5
L3
K3
J5
K6
J6
L7
K7
J7
K8
C1
C2
B3
GPIO
General-purpose I/O port 4
L7
K7
H6
J7
K8
C1
C2
B3
3
3
3
4
4
4
P53
P54
P55
P56
P57
P58
P59
P5A
5
6
5
6
7
8
-
D1
D2
D3
D5
-
5
6
7
8
-
D1
D2
D3
E1
-
7
General-purpose I/O port 5
8
9
10
11
12
-
-
-
-
-
-
-
-
-
-
-
-
P5B
13
-
-
-
-
Document Number: 002-05646 Rev. *E
Page 45 of 149
CY9A150RB Series
Pin No
LQFP-120 LQFP-100 BGA-112 LQFP-80 BGA-96
Pin Function
Pin Name
Function Description
P60
P61
P62
P63
P64
P65
P66
P67
P68
P70
P71
P72
P73
P74
P80
P81
PE0
PE2
PE3
116
115
114
113
112
111
110
109
108
51
96
95
94
93
-
C4
B4
C5
D6
-
76
75
74
73
-
C4
B4
C5
B5
-
General-purpose I/O port 6
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
GPIO
-
-
-
-
52
-
-
-
-
General-purpose I/O port 7
53
-
-
-
-
54
-
-
-
-
55
-
-
-
-
118
119
56
98
99
46
48
49
A3
A2
K9
L9
L10
78
79
36
38
39
A3
A2
K9
L9
L10
General-purpose I/O port 8
General-purpose I/O port E
58
59
Document Number: 002-05646 Rev. *E
Page 46 of 149
CY9A150RB Series
Pin No
LQFP-120 LQFP-100 BGA-112 LQFP-80 BGA-96
Pin
Pin Function
Function Description
Name
SIN0_0
SIN0_1
88
66
73
56
C11
H9
59
46
C11
H9
Multi-function serial
interface ch.0 input pin
Multi-function serial
interface ch.0 output pin.
This pin operates as SOT0
when it is used in a
SOT0_0
87
67
86
68
72
57
71
58
E8
H7
58
47
57
48
D9
G10
D10
G9
(SDA0_0)
UART/CSIO (operation
modes 0 to 2) and as
SOT0_1
Multi- function
Serial 0
(SDA0_1)
SDA0 when it is used in an
I2C (operation mode 4).
Multi-function serial
interface ch.0 clock I/O pin.
This pin operates as SCK0
when it is used in a
SCK0_0
D10
G10
(SCL0_0)
UART/CSIO (operation
modes 0 to 2) and as
SCK0_1
(SCL0_1)
SCL0 when it is used in an
I2C (operation mode 4).
SIN1_0
SIN1_1
8
-
-
-
-
Multi-function serial
interface ch.1 input pin
63
53
J10
43
J10
Multi-function serial
interface ch.1 output pin.
This pin operates as SOT1
when it is used in a
SOT1_0
9
-
-
J8
-
-
-
J8
-
(SDA1_0)
UART/CSIO (operation
modes 0 to 2) and as
SOT1_1
64
10
65
54
44
Multi- function
Serial 1
(SDA1_1)
SDA1 when it is used in an
I2C (operation mode 4).
Multi-function serial
interface ch.1 clock I/O pin.
This pin operates as SCK1
when it is used in a
SCK1_0
-
-
(SCL1_0)
UART/CSIO (operation
modes 0 to 2) and as
SCK1_1
55
H10
45
H10
(SCL1_1)
SCL1 when it is used in an
I2C (operation mode 4).
Document Number: 002-05646 Rev. *E
Page 47 of 149
CY9A150RB Series
Pin No
LQFP-120 LQFP-100 BGA-112 LQFP-80 BGA-96
Pin
Pin Function
Function Description
Name
SIN2_0
SIN2_1
SIN2_2
53
85
69
-
-
-
-
-
-
-
-
Multi-function serial
interface ch.2 input pin
59
G9
49
F10
Multi-function serial
interface ch.2 output pin.
This pin operates as SOT2
when it is used in a
SOT2_0
54
84
-
-
-
-
-
-
-
-
(SDA2_0)
SOT2_1
(SDA2_1)
UART/CSIO (operation
modes 0 to 2) and as
Multi- function
Serial 2
SOT2_2
SDA2 when it is used in an
I2C (operation mode 4).
Multi-function serial
73
63
G8
53
F9
(SDA2_2)
SCK2_0
55
83
-
-
-
-
-
-
-
-
interface ch.2 clock I/O pin.
This pin operates as SCK2
when it is used in a
(SCL2_0)
SCK2_1
(SCL2_1)
UART/CSIO (operation
modes 0 to 2) and as
SCK2_2
74
64
F10
54
E11
SCL2 when it is used in an
I2C (operation mode 4).
(SCL2_2)
SIN3_0
SIN3_1
SIN3_2
110
2
-
-
-
-
Multi-function serial
2
C1
K6
2
C1
J5
interface ch.3 input pin
44
39
29
Multi-function serial
interface ch.3 output pin.
This pin operates as SOT3
when it is used in a
SOT3_0
109
3
-
-
-
-
(SDA3_0)
SOT3_1
3
C2
3
C2
(SDA3_1)
UART/CSIO (operation
modes 0 to 2) and as
Multi- function
Serial 3
SOT3_2
SDA3 when it is used in an
I2C (operation mode 4).
Multi-function serial
45
40
J6
30
K6
(SDA3_2)
SCK3_0
108
4
-
-
-
-
interface ch.3 clock I/O pin.
This pin operates as SCK3
when it is used in a
(SCL3_0)
SCK3_1
4
B3
4
B3
(SCL3_1)
UART/CSIO (operation
modes 0 to 2) and as
SCK3_2
46
41
L7
31
J6
SCL3 when it is used in an
I2C (operation mode 4).
(SCL3_2)
Document Number: 002-05646 Rev. *E
Page 48 of 149
CY9A150RB Series
Pin No
LQFP-120 LQFP-100 BGA-112 LQFP-80 BGA-96
Pin
Pin Function
Function Description
Name
SIN4_0
SIN4_1
SIN4_2
102
75
87
65
82
D7
F9
C8
67
55
-
C8
E10
-
Multi-function serial
interface ch.4 input pin
97
Multi-function serial
interface ch.4 output pin.
This pin operates as SOT4
when it is used in a
SOT4_0
103
76
88
66
A6
68
56
C7
E9
(SDA4_0)
SOT4_1
E11
(SDA4_1)
UART/CSIO (operation
modes 0 to 2) and as
SDA4 when it is used in an
I2C (operation mode 4).
Multi-function serial
SOT4_2
98
83
D9
-
-
(SDA4_2)
SCK4_0
Multi- function
Serial 4
104
77
89
67
B6
69
-
B7
-
interface ch.4 clock I/O pin.
This pin operates as SCK4
when it is used in a
(SCL4_0)
SCK4_1
E10
(SCL4_1)
UART/CSIO (operation
modes 0 to 2) and as
SCL4 when it is used in an
I2C (operation mode 4).
Multi-function serial
SCK4_2
99
84
A7
-
-
(SCL4_2)
RTS4_0
RTS4_1
RTS4_2
CTS4_0
CTS4_1
CTS4_2
105
79
90
69
86
91
68
85
C6
E9
C7
A5
F8
B7
70
-
B6
interface ch.4 RTS output
pin
-
-
101
106
78
-
71
-
C6
-
Multi-function serial
interface ch.4 CTS input
pin
100
-
-
SIN5_0
SIN5_1
SIN5_2
116
113
20
96
-
C4
-
76
-
C4
Multi-function serial
-
-
interface ch.5 input pin
15
F3
-
SOT5_0
Multi-function serial
115
112
95
-
B4
-
75
-
B4
-
interface ch.5 output pin.
(SDA5_0)
This pin operates as SOT5
when it is used in a
SOT5_1
(SDA5_1)
UART/CSIO (operation
modes 0 to 2) and as
Multi- function
Serial 5
SOT5_2
21
16
G1
-
-
SDA5 when it is used in an
I2C (operation mode 4).
(SDA5_2)
SCK5_0
Multi-function serial
interface ch.5 clock I/O pin.
This pin operates as SCK5
when it is used in a
114
111
94
-
C5
-
74
-
C5
-
(SCL5_0)
SCK5_1
(SCL5_1)
UART/CSIO (operation
modes 0 to 2) and as
SCK5_2
SCL5 when it is used in an
I2C (operation mode 4).
22
17
G2
-
-
(SCL5_2)
Document Number: 002-05646 Rev. *E
Page 49 of 149
CY9A150RB Series
Pin No
LQFP-120 LQFP-100 BGA-112 LQFP-80 BGA-96
Pin
Pin Function
Function Description
Name
SIN6_0
SIN6_1
5
5
D1
E4
5
D1
G2
Multi-function serial
interface ch.6 input pin
Multi-function serial
17
12
12
SOT6_0
interface ch.6 output pin.
This pin operates as SOT6
when it is used in a
6
16
7
6
11
7
D2
E3
D3
E2
6
11
7
D2
G1
D3
E3
(SDA6_0)
UART/CSIO (operation
modes 0 to 2) and as
SDA6 when it is used in an
I2C (operation mode 4).
Multi-function serial
SOT6_1
(SDA6_1)
Multi- function
Serial 6
SCK6_0
interface ch.6 clock I/O pin.
This pin operates as SCK6
when it is used in a
(SCL6_0)
UART/CSIO (operation
modes 0 to 2) and as
SCL6 when it is used in an
I2C (operation mode 4).
SCK6_1
15
10
10
(SCL6_1)
11
50
-
-
-
-
SIN7_0
SIN7_1
Multi-function serial
interface ch.7 input pin
45
K8
35
K8
SOT7_0
Multi-function serial
interface ch.7 output pin.
This pin operates as SOT7
when it is used in a
12
-
-
-
-
(SDA7_0)
UART/CSIO (operation
modes 0 to 2) and as
SOT7_1
49
44
J7
34
J7
(SDA7_1)
Multi- function
Serial 7
SDA7 when it is used in an
I2C (operation mode 4).
SCK7_0
Multi-function serial
13
48
-
-
-
-
interface ch.7 clock I/O pin.
(SCL7_0)
This pin operates as SCK7
when it is used in a
UART/CSIO (operation
modes 0 to 2) and as
SCK7_1
43
H6
33
K7
(SCL7_1)
SCL7 when it is used in an
I2C (operation mode 4).
Document Number: 002-05646 Rev. *E
Page 50 of 149
CY9A150RB Series
Pin No
LQFP-120 LQFP-100 BGA-112 LQFP-80 BGA-96
Pin
Pin Function
Function Description
Name
Multi-function serial
SIN8_0
97
82
C8
-
-
-
-
interface ch.8 input pin
Multi-function serial
interface ch.8 output pin.
This pin operates as SOT8
when it is used in a
SOT8_0
94
79
B11
(SDA8_0)
UART/CSIO (operation
modes 0 to 2) and as
Multi- function
Serial 8
SDA8 when it is used in an
I2C (operation mode 4).
Multi-function serial
interface ch.8 clock I/O pin.
This pin operates as SCK8
when it is used in a
SCK8_0
92
17
18
77
12
13
A9
E4
F1
-
-
-
-
-
-
(SCL8_0)
UART/CSIO (operation
modes 0 to 2) and as
SCL8 when it is used in an
I2C (operation mode 4).
Multi-function serial
SIN9_0
interface ch.9 input pin
Multi-function serial
interface ch.9 output pin.
This pin operates as SOT9
when it is used in a
SOT9_0
(SDA9_0)
UART/CSIO (operation
modes 0 to 2) and as
Multi- function
Serial 9
SDA9 when it is used in an
I2C (operation mode 4).
Multi-function serial
interface ch.9 clock I/O pin.
This pin operates as SCK9
when it is used in a
SCK9_0
19
14
F2
-
-
(SCL9_0)
UART/CSIO (operation
modes 0 to 2) and as
SCL9 when it is used in an
I2C (operation mode 4).
Document Number: 002-05646 Rev. *E
Page 51 of 149
CY9A150RB Series
Pin No
LQFP-120 LQFP-100 BGA-112 LQFP-80 BGA-96
Pin Function
Pin Name
Function Description
Multi-function serial
SIN10_0
23
18
F4
13
14
G3
H1
interface ch.10 input pin
Multi-function serial
interface ch.10 output pin.
This pin operates as
SOT10 when it is used in
a UART/CSIO (operation
modes 0 to 2) and as
SDA10 when it is used in
an I2C (operation mode
4).
SOT10_0
24
19
G3
(SDA10_0)
Multi- function
Serial 10
Multi-function serial
interface ch.10 clock I/O
pin.
This pin operates as
SCK10 when it is used in
a UART/CSIO (operation
modes 0 to 2) and as
SCL10 when it is used in
an I2C (operation mode
4).
SCK10_0
25
20
H1
15
H2
(SCL10_0)
Multi-function serial
interface ch.11 input pin
Multi-function serial
interface ch.11 output pin.
This pin operates as
SOT11 when it is used in
a UART/CSIO (operation
modes 0 to 2) and as
SDA11 when it is used in
an I2C (operation mode
4).
SIN11_0
26
27
21
22
H2
G4
16
17
H3
J1
SOT11_0
(SDA11_0)
Multi- function
Serial 11
Multi-function serial
interface ch.11 clock I/O
pin.
This pin operates as
SCK11 when it is used in
a UART/CSIO (operation
modes 0 to 2) and as
SCL11 when it is used in
an I2C (operation mode
4).
SCK11_0
28
23
H3
18
J2
(SCL11_0)
Document Number: 002-05646 Rev. *E
Page 52 of 149
CY9A150RB Series
Pin No
Pin Function
Pin Name
Function Description
LQFP-120 LQFP-100 BGA-112 LQFP-80 BGA-96
Multi-function serial interface ch.12
input pin
SIN12_0
32
27
J4
-
-
Multi-function serial interface ch.12
output pin.
This pin operates as SOT12 when it
is used in a UART/CSIO (operation
modes 0 to 2) and as SDA12 when
it is used in an I2C (operation mode
4).
SOT12_0
33
28
L5
-
-
(SDA12_0)
Multi- function
Serial 12
Multi-function serial interface ch.12
clock I/O pin.
This pin operates as SCK12 when it
is used in a UART/CSIO (operation
modes 0 to 2) and as SCL12 when
it is used in an I2C (operation mode
4).
SCK12_0
34
35
29
30
K5
J5
-
-
-
-
(SCL12_0)
Multi-function serial interface ch.13
input pin
SIN13_0
Multi-function serial interface ch.13
output pin.
This pin operates as SOT13 when it
is used in a UART/CSIO (operation
modes 0 to 2) and as SDA13 when
it is used in an I2C (operation mode
4).
SOT13_0
36
31
H5
-
-
(SDA13_0)
Multi- function
Serial 13
Multi-function serial interface ch.13
clock I/O pin.
This pin operates as SCK13 when it
is used in a UART/CSIO (operation
modes 0 to 2) and as SCL13 when
it is used in an I2C (operation mode
4).
SCK13_0
37
32
L6
-
-
(SCL13_0)
Document Number: 002-05646 Rev. *E
Page 53 of 149
CY9A150RB Series
Pin No
Pin Function
Pin Name
Function Description
LQFP-120 LQFP-100 BGA-112 LQFP-80 BGA-96
Multi-function serial
interface ch.14 input pin
Multi-function serial
interface ch.14 output pin.
This pin operates as
SOT14 when it is used in
a UART/CSIO (operation
modes 0 to 2) and as
SDA14 when it is used in
an I2C (operation mode
4).
SIN14_0
50
-
-
-
-
-
-
-
SOT14_0
51
-
(SDA14_0)
Multi- function
Serial 14
Multi-function serial
interface ch.14 clock I/O
pin.
This pin operates as
SCK14 when it is used in
a UART/CSIO (operation
modes 0 to 2) and as
SCL14 when it is used in
an I2C (operation mode
4).
SCK14_0
52
-
-
-
-
(SCL14_0)
Multi-function serial
SIN15_0
82
81
-
-
-
-
-
-
interface ch.15 input pin
Multi-function serial
interface ch.15 output pin.
This pin operates as
SOT15 when it is used in
a UART/CSIO (operation
modes 0 to 2) and as
SDA15 when it is used in
an I2C (operation mode
4).
SOT15_0
(SDA15_0)
Multi- function
Serial 15
Multi-function serial
interface ch.15 clock I/O
pin.
This pin operates as
SCK15 when it is used in
a UART/CSIO (operation
modes 0 to 2) and as
SCL15 when it is used in
an I2C (operation mode
4).
SCK15_0
80
-
-
-
(SCL15_0)
Document Number: 002-05646 Rev. *E
Page 54 of 149
CY9A150RB Series
Pin No
Pin Function
Pin Name
Function Description
LQFP-120 LQFP-100 BGA-112 LQFP-80 BGA-96
Input signal of waveform
generator to control outputs
RTO00 to RTO05 of multi-
function timer 0.
DTTI0X_0
DTTI0X_1
23
79
18
69
F4
E9
13
-
G3
-
FRCK0_0
FRCK0_1
FRCK0_2
IC00_0
18
80
63
22
13
70
53
17
F1
D11
J10
G2
-
-
-
16-bit free-run timer ch.0
external clock input pin
-
J10
-
43
-
Multi- function
Timer 0
IC00_1
IC00_2
IC01_0
IC01_1
IC01_2
IC02_0
IC02_1
IC02_2
IC03_0
IC03_1
IC03_2
75
64
21
76
65
20
77
66
19
78
67
65
54
16
66
55
15
67
56
14
68
57
F9
J8
55
44
-
E10
J8
G1
E11
H10
F3
-
E9
H10
-
16-bit input capture input pin
of multi-function timer 0.
56
45
-
ICxx describes channel
number.
E10
H9
F2
-
-
46
-
H9
-
F8
-
-
H7
47
G10
Document Number: 002-05646 Rev. *E
Page 55 of 149
CY9A150RB Series
Pin No
Pin Function
Pin Name
Function Description
LQFP-120 LQFP-100 BGA-112 LQFP-80 BGA-96
Waveform generator output
pin of multi-function timer 0.
This pin operates as PPG00
when it is used in PPG0
output mode.
RTO00_0
24
86
25
85
26
84
27
83
19
71
20
-
G3
D10
H1
-
14
57
15
-
H1
D10
H2
-
(PPG00_0)
RTO00_1
(PPG00_1)
Waveform generator output
pin of multi-function timer 0.
This pin operates as PPG00
when it is used in PPG0
output mode.
RTO01_0
(PPG00_0)
RTO01_1
(PPG00_1)
Waveform generator output
pin of multi-function timer 0.
This pin operates as PPG02
when it is used in PPG0
output mode.
RTO02_0
21
-
H2
-
16
-
H3
-
(PPG02_0)
RTO02_1
(PPG02_1)
Waveform generator output
pin of multi-function timer 0.
This pin operates as PPG02
when it is used in PPG0
output mode.
RTO03_0
22
-
G4
-
17
-
J1
-
Multi- function
Timer 0
(PPG02_0)
RTO03_1
(PPG02_1)
RTO04_0
Waveform generator output
pin of multi-function timer 0.
28
82
29
81
23
-
H3
-
18
-
J2
-
(PPG04_0)
This pin operates as PPG04
when it is used in PPG0
output mode.
RTO04_1
(PPG04_1)
RTO05_0
Waveform generator output
pin of multi-function timer 0.
24
-
J2
-
19
-
J4
-
(PPG04_0)
This pin operates as PPG04
when it is used in PPG0
output mode.
RTO05_1
(PPG04_1)
IGTRG_0
IGTRG_1
46
41
96
L7
31
76
J6
PPG IGMT mode external
trigger input pin
116
C4
C4
Document Number: 002-05646 Rev. *E
Page 56 of 149
CY9A150RB Series
Pin No
LQFP-120 LQFP-100 BGA-112 LQFP-80 BGA-96
Pin
Pin Function
Function Description
Name
Quadrature
Position/
AIN0_0
AIN0_1
AIN0_2
BIN0_0
BIN0_1
BIN0_2
ZIN0_0
ZIN0_1
ZIN0_2
AIN1_1
AIN1_2
BIN1_1
BIN1_2
ZIN1_1
ZIN1_2
RTCCO_0
RTCCO_1
RTCCO_2
SUBOUT_
0
14
45
2
9
E1
J6
9
E2
K6
C1
E3
J6
QPRC ch.0 AIN input pin
40
2
30
2
Revolution
Counter 0
C1
E2
L7
15
46
3
10
41
3
10
31
3
QPRC ch.0 BIN input pin
QPRC ch.0 ZIN input pin
C2
E3
K7
B3
C10
H6
C11
J7
C2
G1
L7
16
47
4
11
42
4
11
32
4
B3
C10
K7
C11
J7
Quadrature
Position/
89
48
88
49
87
50
107
65
24
74
43
73
44
72
45
92
55
19
60
33
59
34
58
35
72
45
14
QPRC ch.1 AIN input pin
QPRC ch.1 BIN input pin
QPRC ch.1 ZIN input pin
Revolution
Counter 1
E8
K8
B5
H10
G3
D9
K8
A6
H10
H1
Real-time clock
0.5 seconds pulse output
pin of Real-time clock
107
65
92
55
19
92
53
73
96
9
B5
H10
G3
B5
72
45
14
72
43
59
76
9
A6
H10
H1
SUBOUT_
1
Sub clock output pin
SUBOUT_
2
24
Low-Power
Consumption
Mode
Deep standby mode
return signal input pin 0
Deep standby mode
return signal input pin 1
Deep standby mode
return signal input pin 2
Deep standby mode
return signal input pin 3
Deep standby mode
return signal input pin 4
Deep standby mode
return signal input pin 5
HDMI-CEC/Remote
Control Reception ch.0
input/output pin
WKUP0
WKUP1
WKUP2
WKUP3
WKUP4
WKUP5
107
63
A6
J10
C11
C4
J10
C11
C4
88
116
14
E1
E2
102
87
D7
67
C8
HDMI-
CEC/ Remote
Control
CEC0_0
CEC0_1
CEC1_0
48
43
88
96
H6
A6
C4
33
68
76
K7
C7
C4
103
116
Reception
HDMI-CEC/Remote
Control Reception ch.1
input/output pin
CEC1_1
8
8
D5
8
E1
Document Number: 002-05646 Rev. *E
Page 57 of 149
CY9A150RB Series
Pin No
LQFP-120 LQFP-100 BGA-112 LQFP-80 BGA-96
Pin function
Pin name Function description
Reset
External Reset Input pin.
INITX
A reset is valid when
INITX=L.
43
38
K4
28
37
K4
L8
Mode
Mode 0 pin.
During normal operation,
MD0=L must be input.
During serial
programming to Flash
memory, MD0=H must be
input.
MD0
57
47
L8
Mode 1 pin.
During serial
programming to Flash
memory, MD1=L must be
input.
MD1
56
46
K9
36
K9
Power
VCC
VCC
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
Power supply pin
Power supply pin
Power supply pin
Power supply pin
Power supply pin
Power supply pin
GND pin
1
31
40
61
91
117
-
1
26
35
51
76
97
-
B1
J1
K1
K11
A10
A4
-
1
-
B1
-
25
41
-
K1
K11
-
77
-
A4
F1
F2
F3
B2
L1
K2
J3
-
GND
GND pin
-
-
-
-
GND pin
-
-
-
-
GND pin
-
-
B2
L1
K2
J3
H4
-
-
GND pin
30
-
25
-
20
-
GND pin
GND pin
-
-
-
GND pin
-
-
-
GND pin
-
-
-
L6
L4
L11
K10
J9
-
GND pin
39
60
-
34
50
-
L4
L11
K10
J9
H8
B10
C9
-
24
40
-
GND pin
GND pin
GND pin
-
-
-
GND pin
-
-
-
GND pin
-
-
-
B10
C9
D11
GND pin
-
-
-
GND pin
-
-
-
VSS
GND pin
90
75
A11
-
A11
VSS
VSS
VSS
VSS
VSS
GND pin
GND pin
GND pin
GND pin
GND pin
-
-
-
-
-
-
-
-
-
-
D8
-
-
-
-
-
-
-
A7
-
D4
C3
-
C3
A5
VSS
GND pin
120
100
A1
80
A1
Document Number: 002-05646 Rev. *E
Page 58 of 149
CY9A150RB Series
Pin No
LQFP-120 LQFP-100 BGA-112 LQFP-80 BGA-96
Pin
Pin Function
Function Description
Name
Clock
Main clock (oscillation)
input pin
X0
X0A
X1
58
41
59
42
48
36
49
37
L9
L3
38
26
39
27
L9
L3
Sub clock (oscillation)
input pin
Main clock (oscillation)
I/O pin
L10
K3
L10
K3
Sub clock (oscillation) I/O
pin
X1A
CROUT_0
CROUT_1
89
74
92
C10
B5
60
72
C10
A6
Built-in High-speed CR-
osc clock output port
107
ADC Power
A/D converter analog
power supply pin
AVCC
AVRH
70
71
60
61
H11
F11
50
51
H11
F11
A/D converter analog
reference voltage input
pin
ADC
GND
AVSS
C
A/D converter GND pin
72
38
62
33
G11
L2
52
23
G11
L2
C pin
Power stabilization
capacity pin
Note:
−
While this device contains a Test Access Port (TAP) based on the IEEE 1149.1-2001 JTAG standard, it is not fully compliant
to all requirements of that standard. This device may contain a 32-bit device ID that is the same as the 32-bit device ID in
other devices with different functionality. The TAP pins may also be configurable for purposes other than access to the TAP
controller.
Document Number: 002-05646 Rev. *E
Page 59 of 149
CY9A150RB Series
5. I/O Circuit Type
Type
Circuit
Remarks
A
It is possible to select the main oscillation / GPIO
function
When the main oscillation is selected.
◼Oscillation feedback resistor:
Pull-up
resistor
Approximately 1 MΩ
◼With standby mode control
Digital output
Digital output
P-ch
P-ch
When the GPIO is selected.
X1
◼CMOS level output.
◼CMOS level hysteresis input
◼With pull-up resistor control
◼With standby mode control
◼Pull-up resistor: Approximately 33 kΩ
◼IOH= -4 mA, IOL= 4 mA
N-ch
R
Pull-up resistor
control
Digital input
Standby mode
control
Clock input
Feedback
resistor
Standby mode control
Digital input
Standby mode control
Pull-up
resistor
R
Digital output
Digital output
P-ch
N-ch
P-ch
X0
Pull-up resistor
control
Document Number: 002-05646 Rev. *E
Page 60 of 149
CY9A150RB Series
Type
Circuit
Remarks
B
◼CMOS level hysteresis input
◼Pull-up resistor: Approximately 33 kΩ
Pull-up resistor
Digital input
C
◼Open drain output
◼CMOS level hysteresis input
Digital input
Digital output
N-ch
Document Number: 002-05646 Rev. *E
Page 61 of 149
CY9A150RB Series
Type
Circuit
Remarks
D
It is possible to select the sub oscillation / GPIO
function
When the sub oscillation is selected.
Pull-up
resistor
◼Oscillation feedback resistor
: Approximately 5MΩ
P-ch
P-ch
Digital output
Digital output
◼With standby mode control
X1A
When the GPIO is selected.
◼CMOS level output.
◼CMOS level hysteresis input
◼With pull-up resistor control
◼With standby mode control
◼Pull-up resistor: Approximately 33 kΩ
◼IOH= -4 mA, IOL= 4 mA
N-ch
R
Pull-up resistor control
Digital input
Standby mode control
Clock input
Feedback
resistor
Standby mode control
Digital input
Standby mode control
Pull-up
resistor
R
Digital output
P-ch
N-ch
P-ch
X0A
Digital output
Pull-up resistor control
Document Number: 002-05646 Rev. *E
Page 62 of 149
CY9A150RB Series
Type
Circuit
Remarks
E
◼CMOS level output
◼CMOS level hysteresis input
◼With pull-up resistor control
◼With standby mode control
◼Pull-up resistor
Digital output
Digital output
: Approximately 33 kΩ
P-ch
P-ch
◼IOH= -4 mA, IOL= 4 mA
◼When this pin is used as an I2C pin, the
digital output
P-ch transistor is always off
N-ch
R
Pull-up resistor control
Digital input
Standby mode control
F
◼CMOS level output
◼CMOS level hysteresis input
◼With input control
◼Analog input
◼With pull-up resistor control
◼With standby mode control
Digital output
Digital output
P-ch
P-ch
◼Pull-up resistor
: Approximately 33 kΩ
◼IOH= -4 mA, IOL= 4 mA
◼When this pin is used as an I2C pin, the
digital output
N-ch
P-ch transistor is always off
Pull-up resistor control
Digital input
R
Standby mode control
Analog input
Input control
Document Number: 002-05646 Rev. *E
Page 63 of 149
CY9A150RB Series
Type
Circuit
Remarks
G
CMOS level hysteresis input
Mode input
H
◼CMOS level output
◼CMOS level hysteresis input
◼5 V tolerant
◼With pull-up resistor control
◼With standby mode control
◼Pull-up resistor: Approximately 33 kΩ
◼IOH= -4 mA, IOL= 4 mA
Digital output
Digital output
P-ch
P-ch
◼Available to control PZR registers.
◼When this pin is used as an I2C pin, the
digital output
N-ch
P-ch transistor is always off
R
Pull-up resistor control
Digital input
Standby mode control
Document Number: 002-05646 Rev. *E
Page 64 of 149
CY9A150RB Series
6. Handling Precautions
Any semiconductor devices have inherently a certain rate of failure. The possibility of failure is greatly affected by the conditions in
which they are used (circuit conditions, environmental conditions, etc.). This page describes precautions that must be observed to
minimize the chance of failure and to obtain higher reliability from your Cypress semiconductor devices.
6.1 Precautions for Product Design
This section describes precautions when designing electronic equipment using semiconductor devices.
◼Absolute Maximum Ratings
Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of
certain established limits, called absolute maximum ratings. Do not exceed these ratings.
◼Recommended Operating Conditions
Recommended operating conditions are normal operating ranges for the semiconductor device. All the device's electrical
characteristics are warranted when operated within these ranges.
Always use semiconductor devices within the recommended operating conditions. Operation outside these ranges may adversely
affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users
considering application outside the listed conditions are advised to contact their sales representative beforehand.
◼Processing and Protection of Pins
These precautions must be followed when handling the pins which connect semiconductor devices to power supply and
input/output functions.
1. Preventing Over-Voltage and Over-Current Conditions
Exposure to voltage or current levels in excess of maximum ratings at any pin is likely to cause deterioration within the device, and
in extreme cases leads to permanent damage of the device. Try to prevent such overvoltage or over-current conditions at the
design stage.
2. Protection of Output Pins
Shorting of output pins to supply pins or other output pins, or connection to large capacitance can cause large current flows. Such
conditions if present for extended periods of time can damage the device. Therefore, avoid this type of connection.
3. Handling of Unused Input Pins
Unconnected input pins with very high impedance levels can adversely affect stability of operation. Such pins should be connected
through an appropriate resistance to a power supply pin or ground pin.
◼Latch-up
Semiconductor devices are constructed by the formation of P-type and N-type areas on a substrate. When subjected to abnormally
high voltages, internal parasitic PNPN junctions (called thyristor structures) may be formed, causing large current levels in excess
of several hundred mA to flow continuously at the power supply pin. This condition is called latch-up.
CAUTION:
The occurrence of latch-up not only causes loss of reliability in the semiconductor device, but can cause injury or damage from
high heat, smoke or flame. To prevent this from happening, do the following:
1. Be sure that voltages applied to pins do not exceed the absolute maximum ratings. This should include attention to abnormal
noise, surge levels, etc.
2. Be sure that abnormal current flows do not occur during the power-on sequence.
Document Number: 002-05646 Rev. *E
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CY9A150RB Series
◼Observance of Safety Regulations and Standards
Most countries in the world have established standards and regulations regarding safety, protection from electromagnetic
interference, etc. Customers are requested to observe applicable regulations and standards in the design of products.
◼Fail-Safe Design
Any semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage or loss from such
failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and
prevention of over-current levels and other abnormal operating conditions.
◼Precautions Related to Usage of Devices
Cypress semiconductor devices are intended for use in standard applications (computers, office automation and other office
equipment, industrial, communications, and measurement equipment, personal or household devices, etc.).
CAUTION:
Customers considering the use of our products in special applications where failure or abnormal operation may directly affect
human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as
aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.)
are requested to consult with sales representatives before such use. The company will not be responsible for damages arising
from such use without prior approval.
6.2 Precautions for Package Mounting
Package mounting may be either lead insertion type or surface mount type. In either case, for heat resistance during soldering, you
should only mount under Cypress' recommended conditions. For detailed information about mount conditions, contact your sales
representative.
◼Lead Insertion Type
Mounting of lead insertion type packages onto printed circuit boards may be done by two methods: direct soldering on the board,
or mounting by using a socket.
Direct mounting onto boards normally involves processes for inserting leads into through-holes on the board and using the flow
soldering (wave soldering) method of applying liquid solder. In this case, the soldering process usually causes leads to be
subjected to thermal stress in excess of the absolute ratings for storage temperature. Mounting processes should conform to
Cypress recommended mounting conditions.
If socket mounting is used, differences in surface treatment of the socket contacts and IC lead surfaces can lead to contact
deterioration after long periods. For this reason, it is recommended that the surface treatment of socket contacts and IC leads be
verified before mounting.
◼Surface Mount Type
Surface mount packaging has longer and thinner leads than lead-insertion packaging, and therefore leads are more easily
deformed or bent. The use of packages with higher pin counts and narrower pin pitch results in increased susceptibility to open
connections caused by deformed pins, or shorting due to solder bridges.
You must use appropriate mounting techniques. Cypress recommends the solder reflow method, and has established a ranking of
mounting conditions for each product. Users are advised to mount packages in accordance with Cypress ranking of recommended
conditions.
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CY9A150RB Series
◼Lead-Free Packaging
CAUTION:
When ball grid array (BGA) packages with Sn-Ag-Cu balls are mounted using Sn-Pb eutectic soldering, junction strength may be
reduced under some conditions of use.
◼Storage of Semiconductor Devices
Because plastic chip packages are formed from plastic resins, exposure to natural environmental conditions will cause absorption
of moisture. During mounting, the application of heat to a package that has absorbed moisture can cause surfaces to peel,
reducing moisture resistance and causing packages to crack. To prevent, do the following:
1.
2.
3.
4.
Avoid exposure to rapid temperature changes, which cause moisture to condense inside the product. Store products in
locations where temperature changes are slight.
Use dry boxes for product storage. Products should be stored below 70% relative humidity, and at temperatures between 5°C
and 30°C. When you open Dry Package that recommends humidity 40% to 70% relative humidity.
When necessary, Cypress packages semiconductor devices in highly moisture-resistant aluminum laminate bags, with a
silica gel desiccant. Devices should be sealed in their aluminum laminate bags for storage.
Avoid storing packages where they are exposed to corrosive gases or high levels of dust.
◼Baking
Packages that have absorbed moisture may be de-moisturized by baking (heat drying). Follow the Cypress recommended
conditions for baking.
Condition: 125°C/24 h
◼Static Electricity
Because semiconductor devices are particularly susceptible to damage by static electricity, you must take the following
precautions:
1.
Maintain relative humidity in the working environment between 40% and 70%. Use of an apparatus for ion generation may
be needed to remove electricity.
2.
3.
Electrically ground all conveyors, solder vessels, soldering irons and peripheral equipment.
Eliminate static body electricity by the use of rings or bracelets connected to ground through high resistance (on the level of
1 MΩ). Wearing of conductive clothing and shoes, use of conductive floor mats and other measures to minimize shock loads
is recommended.
4.
5.
Ground all fixtures and instruments, or protect with anti-static measures.
Avoid the use of styrofoam or other highly static-prone materials for storage of completed board assemblies.
Document Number: 002-05646 Rev. *E
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CY9A150RB Series
6.3 Precautions for Use Environment
Reliability of semiconductor devices depends on ambient temperature and other conditions as described above.
For reliable performance, do the following:
1. Humidity
Prolonged use in high humidity can lead to leakage in devices as well as printed circuit boards. If high humidity levels are
anticipated, consider anti-humidity processing.
2. Discharge of Static Electricity
When high-voltage charges exist close to semiconductor devices, discharges can cause abnormal operation. In such cases, use
anti-static measures or processing to prevent discharges.
3. Corrosive Gases, Dust, or Oil
Exposure to corrosive gases or contact with dust or oil may lead to chemical reactions that will adversely affect the device. If you
use devices in such conditions, consider ways to prevent such exposure or to protect the devices.
4. Radiation, Including Cosmic Radiation
Most devices are not designed for environments involving exposure to radiation or cosmic radiation. Users should provide shielding
as appropriate.
5. Smoke, Flame
CAUTION:
Plastic molded devices are flammable, and therefore should not be used near combustible substances. If devices begin to smoke
or burn, there is danger of the release of toxic gases.
Customers considering the use of Cypress products in other special environmental conditions should consult with sales
representatives.
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CY9A150RB Series
7. Handling Devices
7.1 Power Supply Pins
In products with multiple VCC and VSS pins, respective pins at the same potential are interconnected within the device in order to
prevent malfunctions such as latch-up. However, all of these pins should be connected externally to the power supply or ground
lines in order to reduce electromagnetic emission levels, to prevent abnormal operation of strobe signals caused by the rise in the
ground level, and to conform to the total output current rating.
Moreover, connect the current supply source with each Power supply pin and GND pin of this device at low impedance. It is also
advisable that a ceramic capacitor of approximately 0.1 µF be connected as a bypass capacitor between each Power supply pin
and GND pin, between AVCC pin and AVSS pin near this device.
7.2 Stabilizing Power Supply Voltage
A malfunction may occur when the power supply voltage fluctuates rapidly even though the fluctuation is within the recommended
operating conditions of the VCC power supply voltage. As a rule, with voltage stabilization, suppress the voltage fluctuation so that
the fluctuation in VCC ripple (peak-to-peak value) at the commercial frequency (50 Hz/60 Hz) does not exceed 10% of the VCC
value in the recommended operating conditions, and the transient fluctuation rate does not exceed 0.1 V/μs when there is a
momentary fluctuation on switching the power supply.
7.3 Crystal Oscillator Circuit
Noise near the X0/X1 and X0A/X1A pins may cause the device to malfunction. Design the printed circuit board so that X0/X1,
X0A/X1A pins, the crystal oscillator, and the bypass capacitor to ground are located as close to the device as possible.
It is strongly recommended that the PC board artwork be designed such that the X0/X1 and X0A/X1A pins are surrounded by
ground plane as this is expected to produce stable operation.
Evaluate oscillation of your using crystal oscillator by your mount board.
7.4 Sub Crystal Oscillator
This series sub oscillator circuit is low gain to keep the low current consumption.
The crystal oscillator to fill the following conditions is recommended for sub crystal oscillator
to stabilize the oscillation.
◼Surface mount type
Size : More than 3.2 mm × 1.5 mm
Load capacitance : Approximately 6 pF to 7 pF
◼Lead type
Load capacitance : Approximately 6 pF to 7 pF
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CY9A150RB Series
7.5 Using an external clock
When using an external clock as an input of the main clock, set X0/X1 to the external clock input, and input the clock to X0.
X1(PE3) can be used as a general-purpose I/O port. Similarly, when using an external clock as an input of the sub clock, set
X0A/X1A to the external clock input, and input the clock to X0A. X1A (P47) can be used as a general-purpose I/O port.
Example of Using an External Clock
Device
X0(X0A)
Set as
Can be used as
general-purpose
I/O ports.
External clock
input
1(PE3),
1A (P47)
7.6 Handling when using Multi-function serial pin as I2C pin
If it is using the multi-function serial pin as I2C pins, P-ch transistor of digital output is always disabled. However, I2C pins need to
keep the electrical characteristic like other pins and not to connect to the external I2C bus system with power OFF.
7.7 C pin
This series contains the regulator. Be sure to connect a smoothing capacitor (CS) for the regulator between the C pin and the GND
pin. Please use a ceramic capacitor or a capacitor of equivalent frequency characteristics as a smoothing capacitor. However,
some laminated ceramic capacitors have the characteristics of capacitance variation due to thermal fluctuation (F characteristics
and Y5V characteristics). Please select the capacitor that meets the specifications in the operating conditions to use by evaluating
the temperature characteristics of a capacitor. A smoothing capacitor of about 4.7 μF would be recommended for this series.
C
Device
CS
VSS
GND
7.8 Mode pins (MD0)
Connect the MD pin (MD0) directly to VCC or VSS pins. Design the printed circuit board such that the pull-up/down resistor stays
low, as well as the distance between the mode pins and VCC pins or VSS pins is as short as possible and the connection
impedance is low, when the pins are pulled-up/down such as for switching the pin level and rewriting the Flash memory data. It is
because of preventing the device erroneously switching to test mode due to noise.
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CY9A150RB Series
7.9 Notes on power-on
Turn power on/off in the following order or at the same time.
If not using the A/D converter, connect AVCC = VCC and AVSS = VSS.
Turning on : VCC →AVCC → AVRH
Turning off : AVRH → AVCC → VCC
7.10 Serial Communication
There is a possibility to receive wrong data due to the noise or other causes on the serial communication.
Therefore, design a printed circuit board so as to avoid noise.
Consider the case of receiving wrong data due to noise, perform error detection such as by applying a checksum of data at the
end. If an error is detected, retransmit the data.
7.11 Differences in features among the products with different memory sizes and between Flash memory
products and MASK products
The electric characteristics including power consumption, ESD, latch-up, noise characteristics, and oscillation characteristics
among the products with different memory sizes and between Flash memory products and MASK products are different because
chip layout and memory structures are different.
If you are switching to use a different product of the same series, please make sure to evaluate the electric characteristics.
7.12 Pull-Up function of 5 V tolerant I/O
Please do not input the signal more than VCC voltage at the time of Pull-Up function use of 5 V tolerant I/O.
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CY9A150RB Series
8. Block Diagram
TRSTX,TCK,
TDI,TMS
TDO
SWJ-DP
TPIU*
ETM*
SRAM0
16/24/32 Kbyte
ROM
Table
TRACEDx,
TRACECLK
I
SRAM1
16/24/32 Kbyte
D
NVIC
Sys
On-Chip Flash
256+32 Kbyte/
384+32 Kbyte/
512+32 Kbyte
Flash I/F
Security
Dual-Timer
WatchDog Timer
(Software)
Clock Reset
Generator
INITX
WatchDog Timer
(Hardware)
DMAC
8ch.
CSV
CLK
X0
X1
Main
Source Clock
CR
PLL
CR
Osc
Sub
Osc
X0A
X1A
4 MHz 100 kHz
CROUT
MADx
AVCC,
AVSS,
AVRH
MADATAx
External Bus I/F
12-bit A/D Converter
Unit 0
MCSXx,MDQMx,
MOEX,MWEX,
MALE,MRDY,
MNALE,MNCLE,
MNWEX,MNREX,
MCLKOUT
ANxx
Unit 1
Power-On
Reset
ADTGx
LVD
LVD Ctrl
TIOAx
TIOBx
Base Timer
16-bit 16ch./
32-bit 8ch.
Regulator
C
IRQ-Monitor
CRC Accelerator
Watch Counter
AINx
BINx
ZINx
QPRC
2ch.
WKUPx
Deep Standby Ctrl
CEC0,
CEC1
HDMI-CEC/
Remote Reciver Control
A/D Activation Compare
2ch.
RTCCO,
SUBOUT
Real-Time Clock
16-bit Input Capture
4ch.
IC0x
External Interrupt
Controller
24-pin + NMI
INTx
16-bit Free-run Timer
3ch.
FRCK0
NMIX
16-bit Output Compare
6ch.
MD0,
MD1
MODE-Ctrl
GPIO
DTTI0X
RTO0x
P0x,
P1x,
Waveform Generator
3ch.
.
.
.
PIN-Function-Ctrl
PEx
SCKx
SINx
SOTx
CTS4
RTS4
16-bit PPG
3ch.
IGTRG
Multi-Function Serial I/F
16ch.
HW flow control(ch.4)
Multi-function Timer × 1
*:For the CY9AF154MB, CY9AF155MB, and CY9AF156MB, ETM is not available.
9. Memory Size
See Memory size in Product Lineup to confirm the memory size.
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CY9A150RB Series
10.Memory Map
10.1 Memory Map (1)
Peripherals Area
0x41FF_FFFF
Reserved
0xFFFF_FFFF
Reserved
0xE010_0000
0xE000_0000
Cortex-M3 Private
Peripherals
0x4006_1000
0x4006_0000
DMAC
Reserved
0x4004_0000
0x4003_F000
0x4003_C000
0x4003_B000
0x4003_A000
0x4003_9000
0x4003_8000
EXT-bus I/F
Reserved
RTC
Reserved
Watch Counter
CRC
0x7000_0000
0x6000_0000
External Device
Area
MFS
Reserved
0x4003_6000
0x4003_5000
Reserved
LVD/DS mode
HDMI-CEC/
Remote Control Receiver
0x4400_0000
0x4200_0000
0x4000_0000
32Mbytes
Bit band alias
0x4003_4000
0x4003_3000
0x4003_2000
0x4003_1000
0x4003_0000
0x4002_F000
0x4002_E000
GPIO
Reserved
Int-Req.Read
EXTI
Peripherals
Reserved
Reserved
CR Trim
0x2400_0000
0x2200_0000
32Mbytes
Bit band alias
Reserved
0x4002_8000
0x4002_7000
0x4002_6000
0x4002_5000
0x4002_4000
A/DC
QPRC
Reserved
Base Timer
PPG
0x2008_0000
0x2000_0000
0x1FF8_0000
0x0020_8000
0x0020_0000
0x0010_4000
0x0010_0000
SRAM1
SRAM0
Reserved
Reserved
Flash(Work area)
Reserved
0x4002_1000
0x4002_0000
See "lMemory Map (2)"
for the memory size
details.
MFT Unit0
Reserved
Security/CR Trim
0x4001_6000
0x4001_5000
Dual Timer
Reserved
Flash(Main area)
0x4001_3000
SW WDT
HW WDT
0x4001_2000
0x4001_1000
0x0000_0000
Clock/Reset
0x4001_0000
Reserved
Flash I/F
0x4000_1000
0x4000_0000
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CY9A150RB Series
10.2 Memory Map (2)
For more information about Flash (Main area)/Flash (Work area),
see CY9AB40N/A40N/340N/140N/150R, CY9B520M/320M/120M Series Flash Programming Manual.
Document Number: 002-05646 Rev. *E
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CY9A150RB Series
10.3 Peripheral Address Map
Start address
End address
Bus
Peripherals
0x4000_0000
0x4000_1000
0x4001_0000
0x4001_1000
0x4001_2000
0x4001_3000
0x4001_5000
0x4001_6000
0x4002_0000
0x4002_1000
0x4002_4000
0x4002_5000
0x4002_6000
0x4002_7000
0x4002_8000
0x4002_E000
0x4002_F000
0x4003_0000
0x4003_1000
0x4003_2000
0x4003_3000
0x4003_4000
0x4003_5000
0x4003_5800
0x4003_6000
0x4003_8000
0x4003_9000
0x4003_A000
0x4003_B000
0x4003_C000
0x4003_F000
0x4004_0000
0x4006_0000
0x4006_1000
0x4000_0FFF
0x4000_FFFF
0x4001_0FFF
0x4001_1FFF
0x4001_2FFF
0x4001_4FFF
0x4001_5FFF
0x4001_FFFF
0x4002_0FFF
0x4002_3FFF
0x4002_4FFF
0x4002_5FFF
0x4002_6FFF
0x4002_7FFF
0x4002_DFFF
0x4002_EFFF
0x4002_FFFF
0x4003_0FFF
0x4003_1FFF
0x4003_2FFF
0x4003_3FFF
0x4003_4FFF
0x4003_57FF
0x4003_5FFF
0x4003_7FFF
0x4003_8FFF
0x4003_9FFF
0x4003_AFFF
0x4003_BFFF
0x4003_EFFF
0x4003_FFFF
0x4005_FFFF
0x4006_0FFF
0x41FF_FFFF
Flash memory I/F register
Reserved
AHB
Clock/Reset Control
Hardware Watchdog timer
Software Watchdog timer
Reserved
APB0
Dual Timer
Reserved
Multi-function timer unit0
Reserved
PPG
Base Timer
APB1
Quadrature Position/Revolution Counter
A/D Converter
Reserved
Built-in CR trimming
Reserved
External Interrupt
Interrupt Source Check Register
Reserved
GPIO
HDMI-CEC/Remote control Reception
Low-Voltage Detector
Deep standby mode Controller
Reserved
APB2
Multi-function serial
CRC
Watch Counter
Real-time clock
Reserved
External bus interface
Reserved
AHB
DMAC register
Reserved
Document Number: 002-05646 Rev. *E
Page 75 of 149
CY9A150RB Series
11.Pin Status in Each CPU State
The terms used for pin status have the following meanings.
◼INITX=0
This is the period when the INITX pin is the L level.
◼INITX=1
This is the period when the INITX pin is the H level.
◼SPL=0
This is the status that the standby pin level setting bit (SPL) in the standby mode control register (STB_CTL) is set to 0.
◼SPL=1
This is the status that the standby pin level setting bit (SPL) in the standby mode control register (STB_CTL) is set to 1.
◼Input enabled
Indicates that the input function can be used.
◼Internal input fixed at 0
This is the status that the input function cannot be used. Internal input is fixed at L.
◼Hi-Z
Indicates that the pin drive transistor is disabled and the pin is put in the Hi-Z state.
◼Setting disabled
Indicates that the setting is disabled.
◼Maintain previous state
Maintains the state that was immediately prior to entering the current mode.
If a built-in peripheral function is operating, the output follows the peripheral function.
If the pin is being used as a port, that output is maintained.
◼Analog input is enabled
Indicates that the analog input is enabled.
◼Trace output
Indicates that the trace function can be used.
◼GPIO selected
In Deep standby mode, pins switch to the general-purpose I/O port.
Document Number: 002-05646 Rev. *E
Page 76 of 149
CY9A150RB Series
11.1 List of Pin Status
Return
Power-on
Run
mode or
Sleep
mode
state
Device
internal
reset
Deep standby Rtc
mode or Deep
standby Stop mode
state
from
Deep
reset or low-
voltage
INITX
input
state
Timer mode,
RTC mode, or
Stop mode state
standby
mode
state
detection
state
state
Function
group
Power
Power
supply
stable
INITX = 1
-
Power
supply
stable
INITX = 1
-
supply
Power supply stable
INITX = 0 INITX = 1
Power supply stable
INITX = 1
Power supply stable
INITX = 1
unstable
-
-
-
-
SPL = 0
SPL = 1
SPL = 0
SPL = 1
GPIO
Hi-Z /
Hi-Z /
selected
Maintain
previous
state
Maintain
previous
state
GPIO
Setting
Setting
Setting
Internal
input
Internal
input
GPIO
Internal
input
selected
disabled
disabled
disabled
selected
fixed at 0
fixed at 0
fixed at 0
Main crystal
oscillator
input pin/
External
main clock
input
A
Input
Input
Input
Input
Input
Input
Input
Input
Input
enabled
enabled
enabled
enabled
enabled
enabled
enabled
enabled
enabled
selected
GPIO
Hi-Z /
Hi-Z /
Maintain
previous
state
Maintain
previous
state
selected
Internal
input
GPIO
Setting
Setting
Setting
Internal
input
Internal
input
GPIO
selected
disabled
disabled
disabled
selected
fixed at 0
fixed at 0
fixed at 0
External
main clock
input
Hi-Z /
Hi-Z /
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Setting
Setting
Setting
Internal
input
Internal
input
disabled
disabled
disabled
selected
fixed at 0
fixed at 0
B
Maintain
previous
state/
Maintain
previous
state/
Maintain
previous
state/
Maintain
previous
state/
Maintain
previous
state/
Maintain
previous
state/
Hi-Z /
Hi-Z /
Hi-Z /
When
When
When
When
When
When
Main crystal
oscillator
Internal input
fixed at 0/
or Input
Internal
input
Internal
input
oscillation
stops[1],
Hi-Z /
oscillatio
oscillatio
oscillatio
oscillatio
oscillatio
n stops[1], n stops[1], n stops[1], n stops[1], n stops[1],
output pin
fixed at 0
fixed at 0
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
enable
Internal
input fixed
at 0
Internal
input
Internal
input
Internal
input
Internal
input
Internal
input
fixed at 0
fixed at 0
fixed at 0
fixed at 0
fixed at 0
Pull-up /
Input
Pull-up /
Input
Pull-up /
Input
Pull-up /
Input
Pull-up /
Input
Pull-up /
Input
Pull-up /
Input
Pull-up /
Input
Pull-up /
Input
INITX
C
input pin
enabled
enabled
enabled
enabled
enabled
enabled
enabled
enabled
enabled
Document Number: 002-05646 Rev. *E
Page 77 of 149
CY9A150RB Series
Return
Power-on
reset or low-
voltage
Run
mode or
Sleep
mode
state
Device
internal
reset
Deep standby Rtc
mode or Deep
standby Stop mode
state
from
Deep
INITX
input
state
Timer mode,
RTC mode, or
Stop mode state
standby
mode
state
detection
state
state
Function
group
Power
Power
supply
stable
INITX = 1
-
Power
supply
stable
INITX = 1
-
supply
Power supply stable
INITX = 0 INITX = 1
Power supply stable
INITX = 1
Power supply stable
INITX = 1
unstable
-
-
-
-
SPL = 0
SPL = 1
SPL = 0
SPL = 1
Mode
Input
Input
Input
Input
Input
Input
Input
Input
Input
D
E
input pin
enabled
enabled
enabled
enabled
enabled
enabled
enabled
enabled
enabled
Mode
Input
Input
Input
Input
Input
Input
Input
Input
Input
input pin
enabled
enabled
enabled
enabled
enabled
enabled
enabled
enabled
enabled
Maintain
previous
state
Maintain
previous
state
Hi-Z /
Hi-Z /
GPIO
Setting
Setting
Setting
GPIO
GPIO
Input
Input
selected
disabled
disabled
disabled
selected
selected
enabled
enabled
GPIO
Hi-Z /
Hi-Z /
Maintain
previous
state
Maintain
previous
state
selected
Internal
input
GPIO
Setting
Setting
Setting
Internal
input
Internal
input
GPIO
selected
disabled
disabled
disabled
selected
fixed at 0
fixed at 0
fixed at 0
F
Sub crystal
oscillator
input pin /
External sub
clock input
selected
Input
Input
Input
Input
Input
Input
Input
Input
Input
enabled
enabled
enabled
enabled
enabled
enabled
enabled
enabled
enabled
Document Number: 002-05646 Rev. *E
Page 78 of 149
CY9A150RB Series
Power-
on reset
or low-
voltage
detectio
n state
Power
supply
unstable
-
Return
Run
mode or
Sleep
mode
state
Device
internal
reset
from
INITX
input
state
Timer mode,
RTC mode, or
Stop mode state
Deep standby Rtc mode
Deep
or Deep standby Stop
standby
mode state
state
mode
Function
group
state
Power
supply
stable
Power
Power supply stable
Power supply stable
INITX = 1
Power supply stable
INITX = 1
supply
stable
INITX = 1
-
INITX = 0 INITX = 1 INITX = 1
-
-
-
-
SPL = 0
SPL = 1
SPL = 0
SPL = 1
GPIO
Hi-Z /
Hi-Z /
selected
Maintain
previous
state
Maintain
previous
state
GPIO
Setting
Setting
Setting
Internal
input fixed
at 0
Internal
input fixed
at 0
GPIO
Internal
input fixed
at 0
selected
disabled
disabled
disabled
selected
External
sub clock
input
Hi-Z /
Hi-Z/
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Setting
Setting
Setting
Internal
input fixed
at 0
Internal
input fixed
at 0
disabled
disabled
disabled
selected
G
Maintain
previous
state/
Maintain
previous
state/
Maintain
previous
state/
Maintain
previous
state/When
oscillation
stops[2],
Hi-Z/
Maintain
previous
state/When
oscillation
stops[2], Hi-
Z / Internal
input fixed
at 0
Hi-Z /
Internal
input
Sub
Hi-Z /
Hi-Z /
When
When
When
Maintain
previous
state
crystal
Internal
input
Internal
input
oscillation
stops[2],
Hi-Z /
oscillation
stops[2],
Hi-Z/
oscillation
stops[2],
Hi-Z/
fixed at
0/
oscillator
output pin
fixed at 0
fixed at 0
Internal
input fixed
at 0
or Input
enable
Internal
input fixed
at 0
Internal
input fixed
at 0
Internal
input fixed
at 0
Maintain
previous
state
NMIX
Setting
Setting
Setting
selected
disabled
disabled
disabled
Hi-Z /
Resource
other than
above
Maintain
previous
state
Maintain
previous
state
WKUP
input
WKUP
input
GPIO
H
Hi-Z /
selected
Hi-Z /
Hi-Z /
enabled
Internal
input fixed
at 0
enabled
selected
Hi-Z
Input
Input
enabled
enabled
GPIO
selected
Document Number: 002-05646 Rev. *E
Page 79 of 149
CY9A150RB Series
Power-
on reset
or low-
voltage
detectio
n state
Power
supply
unstable
-
Return
Run
mode or
Sleep
mode
state
Device
internal
reset
from
INITX
input
state
Timer mode,
RTC mode, or
Stop mode state
Deep standby Rtc mode
Deep
or Deep standby Stop
standby
mode state
state
mode
Function
group
state
Power
supply
stable
Power
Power supply stable
Power supply stable
INITX = 1
Power supply stable
INITX = 1
supply
stable
INITX = 1
-
INITX = 0 INITX = 1 INITX = 1
-
-
-
-
SPL = 0
SPL = 1
SPL = 0
SPL = 1
Pull-up /
Input
Pull-up /
Input
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
JTAG
Hi-Z
selected
enabled
enabled
Maintain
previous
state
Maintain
previous
state
GPIO
I
Resource
selected
Hi-Z /
Hi-Z /
selected
Setting
Setting
Setting
Internal
input fixed
at 0
Internal
input fixed
at 0
GPIO
Internal
input fixed
at 0
disabled
disabled
disabled
selected
GPIO
selected
Resource
selected
GPIO
Hi-Z /
Hi-Z /
selected
Hi-Z /
Hi-Z /
Maintain
previous
state
Maintain
previous
state
Internal
input fixed
at 0
Internal
input fixed
at 0
GPIO
J
Hi-Z
Input
Input
Internal
input fixed
at 0
selected
enabled
enabled
GPIO
selected
External
interrupt
enabled
selected
Maintain
previous
state
Setting
Setting
Setting
disabled
disabled
disabled
GPIO
Resource
other than
above
Hi-Z /
selected
Maintain
previous
state
Maintain
previous
state
Internal
input fixed
at 0
GPIO
K
Internal
input fixed
at 0
selected
Hi-Z /
selected
Hi-Z /
Hi-Z /
Internal
input fixed
at 0
Hi-Z
Input
Input
enabled
enabled
GPIO
selected
Document Number: 002-05646 Rev. *E
Page 80 of 149
CY9A150RB Series
Power-
on reset
or low-
voltage
detectio
n state
Power
supply
unstable
-
Return
Run
mode or
Sleep
mode
state
Device
internal
reset
from
INITX
input
state
Timer mode,
RTC mode, or
Stop mode state
Deep standby Rtc mode
Deep
or Deep standby Stop
standby
mode state
state
mode
Function
group
state
Power
supply
stable
Power
Power supply stable
Power supply stable
INITX = 1
Power supply stable
INITX = 1
supply
stable
INITX = 1
-
INITX = 0 INITX = 1 INITX = 1
-
-
-
-
SPL = 0
SPL = 1
SPL = 0
SPL = 1
Hi-Z /
Internal
input
Hi-Z /
Internal
input
Hi-Z /
Internal
input
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Internal
input fixed
at 0 /
Internal
input fixed
at 0 /
Internal
input fixed
at 0 /
Internal
input fixed
at 0 /
Internal
input fixed
at "0" /
Analog
input
fixed at 0
/
fixed at 0
/
fixed at 0
/
Hi-Z
Analog
selected
Analog
input
Analog
input
Analog
input
Analog
input
Analog
input
Analog
input
Analog
input
input
enabled
enabled
enabled
enabled
enabled
L
enabled
enabled
enabled
Resource
other than
above
GPIO
Hi-Z /
Hi-Z /
selected
Maintain
previous
state
Maintain
previous
state
Setting
Setting
Setting
Internal
input fixed
at 0
Internal
input fixed
at 0
GPIO
Internal
input fixed
at 0
selected
disabled
disabled
disabled
selected
GPIO
selected
Hi-Z /
Internal
input
Hi-Z /
Internal
input
Hi-Z /
Internal
input
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Internal
input fixed
at 0 /
Internal
input fixed
at 0 /
Internal
input fixed
at 0 /
Internal
input fixed
at 0 /
Internal
input fixed
at 0 /
Analog
input
fixed at 0
/
fixed at 0
/
fixed at 0
/
Hi-Z
Analog
selected
Analog
input
Analog
input
Analog
input
Analog
input
Analog
input
Analog
input
Analog
input
input
enabled
enabled
enabled
enabled
enabled
enabled
enabled
enabled
External
interrupt
enabled
selected
Maintain
previous
state
M
GPIO
Hi-Z /
selected
Maintain
previous
state
Maintain
previous
state
Resource
other than
above
Setting
Setting
Setting
Internal
input fixed
at 0
GPIO
Internal
input fixed
at 0
disabled
disabled
disabled
selected
Hi-Z /
Internal
input fixed
at 0
selected
GPIO
selected
Document Number: 002-05646 Rev. *E
Page 81 of 149
CY9A150RB Series
Power-
on reset
or low-
voltage
detectio
n state
Power
supply
unstable
-
Return
Run
mode or
Sleep
mode
state
Device
internal
reset
from
INITX
input
state
Timer mode,
RTC mode, or
Stop mode state
Deep standby Rtc mode
Deep
or Deep standby Stop
standby
mode state
state
mode
Function
group
state
Power
supply
stable
Power
Power supply stable
Power supply stable
INITX = 1
Power supply stable
INITX = 1
supply
stable
INITX = 1
-
INITX = 0 INITX = 1 INITX = 1
-
-
-
-
SPL = 0
Hi-Z /
SPL = 1
Hi-Z /
SPL = 0
Hi-Z /
SPL = 1
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Internal
input
Internal
input
Internal
input
Internal
input fixed
at 0 /
Internal
input fixed
at 0
Internal
input fixed
at 0 /
Internal
input fixed
at 0 /
Internal
Analog
input
input fixed
at 0 /Analog
input
Hi-Z
fixed at 0
/Analog
input
fixed at 0
/Analog
input
fixed at 0
/Analog
input
selected
Analog
input
/Analog
input
Analog
input
Analog
input
enabled
enabled
enabled
enabled
enabled
enabled
enabled
enabled
Trace
Trace
output
N
selected
GPIO
Resource
other than
above
Hi-Z /
selected
Maintain
previous
state
Maintain
previous
state
Setting
Setting
Setting
Internal
input fixed
at 0
GPIO
Hi-Z /
Internal
input fixed
at 0
disabled
disabled
disabled
selected
Internal
input fixed
at 0
selected
GPIO
selected
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Internal
input
Internal
input
Internal
input
Internal
input fixed
at 0
Internal
input fixed
at 0
Internal
input fixed
at 0
Internal
input fixed
at 0 /Analog
input
Internal
input fixed
at 0 /Analog
input
Analog
input
Hi-Z
fixed at 0
/Analog
input
fixed at 0
/Analog
input
fixed at 0
/Analog
input
selected
/Analog
input
/Analog
input
/Analog
input
enabled
enabled
enabled
enabled
enabled
enabled
enabled
enabled
Trace
Trace
output
selected
O
External
interrupt
enabled
selected
Maintain
previous
state
GPIO
Hi-Z /
Maintain
previous
state
Maintain
previous
state
selected
Internal
input fixed
at 0
Setting
Setting
Setting
Internal
input fixed
at 0
GPIO
disabled
disabled
disabled
selected
Resource
other than
above
Hi-Z /
Internal
input fixed
at 0
selected
GPIO
selected
Document Number: 002-05646 Rev. *E
Page 82 of 149
CY9A150RB Series
Power-
on reset
or low-
voltage
detectio
n state
Power
supply
unstable
-
Return
Run
mode or
Sleep
mode
state
Device
internal
reset
from
INITX
input
state
Timer mode,
RTC mode, or
Stop mode state
Deep standby Rtc mode
Deep
or Deep standby Stop
standby
mode state
state
mode
Function
group
state
Power
supply
stable
Power
Power supply stable
Power supply stable
INITX = 1
Power supply stable
INITX = 1
supply
stable
INITX = 1
-
INITX = 0 INITX = 1 INITX = 1
-
-
-
-
SPL = 0
SPL = 1
SPL = 0
SPL = 1
Hi-Z /
Internal
input
Hi-Z /
Internal
input
Hi-Z /
Internal
input
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Internal
input fixed
at 0 /
Internal
input fixed
at 0 /
Internal
input fixed
at 0 /
Internal
input fixed
at 0 /
Internal
input fixed
at 0 /
Analog
input
fixed at 0
/
fixed at 0
/
fixed at 0
/
Hi-Z
selected
Analog
input
Analog
input
Analog
input
Analog
input
Analog
input
Analog
input
Analog
input
Analog
input
enabled
enabled
enabled
enabled
enabled
enabled
enabled
enabled
Hi-Z /
WKUP
input
WKUP
WKUP
input
enabled
enabled
Maintain
previous
state
P
enabled
External
interrupt
enabled
selected
Resource
other than
above
Maintain
previous
state
Maintain
previous
state
Setting
Setting
Setting
GPIO
GPIO
disabled
disabled
disabled
selected
Hi-Z /
selected
Internal
input fixed
at 0
Internal
input fixed
at 0
Hi-Z /
Internal
input fixed
at 0
selected
GPIO
selected
Document Number: 002-05646 Rev. *E
Page 83 of 149
CY9A150RB Series
Power-
on reset
or low-
voltage
detectio
n state
Return
Run
mode or
Sleep
mode
state
Device
internal
reset
from
INITX
input
state
Timer mode,
RTC mode, or
Stop mode state
Deep standby Rtc mode
Deep
or Deep standby Stop
standby
mode state
state
mode
state
Function
group
Power
supply
Power
supply
stable
Power
Power supply stable
Power supply stable
INITX = 1
Power supply stable
INITX = 1
supply
stable
unstable
-
-
INITX = 0 INITX = 1 INITX = 1
INITX = 1
-
-
-
-
SPL = 0
SPL = 1
SPL = 0
SPL = 1
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
CEC
Setting
Setting
Setting
enabled
disabled
disabled
disabled
Hi-Z /
WKUP
input
WKUP
WKUP
input
enabled
enabled
Maintain
previous
state
enabled
Setting
Setting
Setting
disabled
disabled
disabled
External
interrupt
enabled
selected
Q
Maintain
previous
state
Maintain
previous
state
GPIO
GPIO
selected
Hi-Z /
selected
Internal
input fixed
at 0
Resource
other than
above
Internal
input fixed
at 0
Hi-Z /
Hi-Z /
Hi-Z /
Internal
input fixed
at 0
Hi-Z
Input
Input
selected
GPIO
enabled
enabled
selected
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
CEC
Setting
Setting
Setting
disabled
disabled
disabled
enabled
External
interrupt
enabled
selected
Maintain
previous
state
Setting
Setting
Setting
disabled
disabled
disabled
GPIO
R
Hi-Z /
selected
Maintain
previous
state
Maintain
previous
state
Internal
input fixed
at 0
GPIO
Resource
other than
above
Internal
input fixed
at 0
selected
Hi-Z /
Hi-Z /
Hi-Z /
Internal
input fixed
at 0
Hi-Z
Input
Input
selected
enabled
enabled
GPIO
selected
Document Number: 002-05646 Rev. *E
Page 84 of 149
CY9A150RB Series
Power-
on reset
or low-
voltage
detectio
n state
Return
Run
mode or
Sleep
mode
state
Device
internal
reset
from
INITX
input
state
Timer mode,
RTC mode, or
Stop mode state
Deep standby Rtc mode
Deep
or Deep standby Stop
standby
mode state
state
mode
state
Function
group
Power
supply
Power
supply
stable
Power
Power supply stable
Power supply stable
INITX = 1
Power supply stable
INITX = 1
supply
stable
unstable
-
-
INITX = 0 INITX = 1 INITX = 1
INITX = 1
-
-
-
-
SPL = 0
SPL = 1
SPL = 0
SPL = 1
Hi-Z /
WKUP
input
WKUP
WKUP
input
enabled
enabled
Maintain
previous
state
enabled
Setting
Setting
Setting
disabled
disabled
disabled
External
interrupt
enabled
selected
Maintain
previous
state
Maintain
previous
state
GPIO
S
GPIO
selected
Hi-Z /
selected
Resource
other than
above
Internal
input fixed
at 0
Internal
input fixed
at 0
Hi-Z /
Hi-Z /
Hi-Z /
Internal
input fixed
at 0
Hi-Z
Input
Input
selected
enabled
enabled
GPIO
selected
[1]. Oscillation is stopped at Sub Timer mode, Low-speed CR Timer mode, RTC mode, Stop mode, Deep Standby RTC mode, and Deep Standby
Stop mode.
[2]. Oscillation is stopped at Stop mode and Deep Standby Stop mode.
Document Number: 002-05646 Rev. *E
Page 85 of 149
CY9A150RB Series
12.Electrical Characteristics
12.1 Absolute Maximum Ratings
Rating
Parameter
Symbol
Unit
Remarks
Min
Max
Power supply voltage[1], [2]
VCC
VSS - 0.5
VSS + 4.6
V
V
Analog power supply voltage[1], [3]
Analog reference voltage[1], [3]
AVCC
AVRH
VSS - 0.5
VSS + 4.6
VSS - 0.5
VSS + 4.6
V
VSS - 0.5
VCC + 0.5 (≤ 4.6 V)
V
Input voltage[1]
VI
VSS - 0.5
VSS + 6.5
V
5 V tolerant
Analog pin input voltage[1]
VIA
VO
VSS - 0.5
AVCC + 0.5 (≤ 4.6 V)
V
Output voltage[1]
VSS - 0.5
VCC + 0.5 (≤ 4.6 V)
V
L level maximum output current[4]
L level average output current[5]
L level total maximum output current
L level total average output current[6]
H level maximum output current[4]
H level average output current[5]
H level total maximum output current
H level total average output current[6]
Power consumption
IOL
-
10
4
mA
mA
mA
mA
mA
mA
mA
mA
mW
°C
IOLAV
∑IOL
∑IOLAV
IOH
-
-
100
50
-
-
- 10
- 4
IOHAV
∑IOH
∑IOHAV
PD
-
-
- 100
- 50
300
+ 150
-
-
Storage temperature
TSTG
- 55
[1]. These parameters are based on the condition that VSS = AVSS = 0.0 V.
[2]. VCC must not drop below VSS - 0.5 V.
[3]. Ensure that the voltage does not exceed VCC + 0.5 V, for example, when the power is turned on.
[4]. The maximum output current is defined as the value of the peak current flowing through any one of the corresponding pins.
[5]. The average output current is defined as the average current value flowing through any one of the corresponding pins for a 100 ms period.
[6]. The total average output current is defined as the average current value flowing through all of corresponding pins for a 100 ms.
WARNING:
Semiconductor devices may be permanently damaged by application of stress (including, without limitation, voltage, current or
temperature) in excess of absolute maximum ratings. Do not exceed any of these ratings.
Document Number: 002-05646 Rev. *E
Page 86 of 149
CY9A150RB Series
12.2 Recommended Operating Conditions
(VSS = AVSS = 0.0V)
Value
Parameter
Power supply voltage
Symbol
Conditions
Unit
Remarks
Min
1.65[2]
1.65
2.7
Max
3.6
VCC
-
-
V
V
V
V
Analog power supply voltage
AVCC
3.6
AVCC = VCC
AVCC
AVCC
AVCC ≥ 2.7 V
Analog reference voltage
AVRH
-
AVCC
AVCC < 2.7 V
For built-in
Regulator[1]
Smoothing capacitor
CS
TA
-
-
1
10
μF
Operating temperature
- 40
+ 85
°C
[1]. See C pin in Handling Devices for the connection of the smoothing capacitor.
[2]. In between less than the minimum power supply voltage and low voltage reset/interrupt detection voltage or more, instruction execution and low
voltage detection function by built-in High-speed CR(including Main PLL is used) or built-in Low-speed CR is possible to operate only.
WARNING:
The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of
the device's electrical characteristics are warranted when the device is operated under these conditions.
Any use of semiconductor devices will be under their recommended operating condition.
Operation under any conditions other than these conditions may adversely affect reliability of device and could result in device
failure. No warranty is made with respect to any use, operating conditions or combinations not represented on this data sheet. If
you are considering application under any conditions other than listed herein, please contact sales representatives beforehand.
Document Number: 002-05646 Rev. *E
Page 87 of 149
CY9A150RB Series
12.3 DC Characteristics
12.3.1 Current rating
(VCC = AVCC = 1.65V to 3.6V, VSS = AVSS = 0V, TA = - 40°C to + 85°C)
Value
Typ[3] Max[4]
Pin
Parameter Symbol
Conditions
Unit Remarks
name
CPU: 40 MHz,
[1] [5]
17.5
23.7
mA
mA
,
Peripheral: 40 MHz
PLL
CPU: 40 MHz,
Peripheral: the clock
stops
Run mode
[1] [5]
8
11
,
NOP operation
ICC
High-speed
[1]
CPU/ Peripheral: 4 MHz[2]
1.9
3.1
mA
CR Run mode
Power
supply
current
[1] [6]
Sub Run mode
CPU/ Peripheral: 32 kHz
CPU/ Peripheral: 100 kHz
Peripheral: 40 MHz
120
140
11
810
830
15
μA
μA
,
VCC
Low-speed CR
Run mode
[1]
[1] [5]
PLL Sleep mode
mA
mA
,
High-speed CR
Sleep mode
[1]
Peripheral: 4 MHz[2]
0.82
1.7
ICCS
[1] [6]
Sub Sleep mode
Peripheral: 32 kHz
Peripheral: 100 kHz
105
125
800
810
μA
μA
,
Low-speed
[1]
CR Sleep mode
[1]. When all ports are fixed.
[2]. When setting it to 4 MHz by trimming.
[3]. TA=+25°C, VCC=3.6 V
[4]. TA=+85°C, VCC=3.6 V
[5]. When using the crystal oscillator of 4 MHz(Including the current consumption of the oscillation circuit)
[6]. When using the crystal oscillator of 32 kHz(Including the current consumption of the oscillation circuit)
Document Number: 002-05646 Rev. *E
Page 88 of 149
CY9A150RB Series
Value
Pin
Parameter Symbol
Conditions
Unit
Remarks
Typ[2] Max[2]
name
TA = + 25°C,
[1], [3]
[1], [3]
[1], [4}
[1], [4}
[1], [4]
[1], [4]
[1]
2.0
-
2.7
3.2
45
mA
mA
μA
μA
μA
μA
μA
μA
When LVD is off
TA = + 85°C,
Main
Timer mode
When LVD is off
TA = + 25°C,
ICCT
15
-
When LVD is off
TA = + 85°C,
Sub
Timer mode
440
40
When LVD is off
TA = + 25°C,
13
-
When LVD is off
TA = + 85°C,
ICCR
RTC mode
Stop mode
380
38
When LVD is off
TA = + 25°C,
11
-
When LVD is off
TA = + 85°C,
ICCH
[1]
370
When LVD is off
TA = + 25°C,
[1], [4],[5]
[1], [4],[5]
When LVD is off,
When RAM is off
2.0
9.2
12
25
μA
μA
Power
supply
current
ICCRD
TA = + 25°C,
VCC
When LVD is off,
When RAM is on
Deep
Standby
RTC mode
TA = + 85°C,
[1], [4],[5]
[1], [4],[5]
[1], [5]
When LVD is off,
When RAM is off
TA = + 85°C,
125
195
10
μA
μA
μA
μA
μA
μA
-
When LVD is off,
When RAM is on
TA = + 25°C,
When LVD is off,
When RAM is off
TA = + 25°C,
1.4
8.6
[1], [5]
When LVD is off,
When RAM is on
TA = + 85°C,
23
Deep
ICCHD
Standby
Stop mode
[1], [5]
When LVD is off,
When RAM is off
TA = + 85°C,
120
190
-
[1], [5]
When LVD is off,
When RAM is on
[1]. When all ports are fixed.
[2]. VCC=3.6 V
[3]. When using the crystal oscillator of 4 MHz(Including the current consumption of the oscillation circuit)
[4]. When using the crystal oscillator of 32 kHz(Including the current consumption of the oscillation circuit)
[5]. RAM on/off setting is on-chip SRAM only.
Document Number: 002-05646 Rev. *E
Page 89 of 149
CY9A150RB Series
12.3.1.1 Low-Voltage Detection Current
(VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C)
Value
Typ
Pin
Parameter
Symbol
Conditions
Unit
Remarks
name
Max
At operation for reset
VCC = 3.6 V
0.13
0.13
0.3
μA
μA
At not detect
Low-voltage
detection circuit
(LVD) power
ICCLVD
VCC
At operation for interrupt
VCC = 3.6 V
supply current
0.3
At not detect
12.3.1.2 Flash Memory Current
(VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C)
Value
Pin
Parameter
Symbol
Conditions
Unit
Remarks
name
Typ
Max
Flash memory
[1]
ICCFLASH
VCC
At Write/Erase
9.5
11.2
mA
write/erase current
[1]. The current at which to write or erase Flash memory, ICCFLASH is added to ICC
.
12.3.1.3 A/D Converter Current
(VCC = AVCC = 1.65V to 3.6V, VSS = AVSS = 0V, TA = - 40°C to +85°C)
Value
Pin
Parameter
Symbol
Conditions
Unit
Remarks
name
Typ
Max
At 1unit operation
At stop
0.27
0.42
mA
Power supply
current
ICCAD
AVCC
0.03
0.72
0.02
10
1.29
2.6
μA
At 1unit operation
AVRH=3.6 V
mA
Reference power
supply current
ICCAVRH
AVRH
At stop
μA
Document Number: 002-05646 Rev. *E
Page 90 of 149
CY9A150RB Series
12.3.2 Pin Characteristics
(VCC = AVCC = 1.65V to 3.6V, VSS = AVSS = 0V, TA = - 40°C to + 85°C)
Value
Typ
Sym
Parameter
Pin name
Conditions
Unit
Remarks
bol
Min
Max
CMOS
VCC ≥ 2.7 V
VCC × 0.8
hysteresis
input pin,
MD0, MD1
-
-
-
-
VCC + 0.3
V
H level input
VCC < 2.7 V
VCC × 0.7
Voltage
VIHS
(hysteresis
VCC ≥ 2.7 V
VCC < 2.7 V
VCC ≥ 2.7 V
VCC × 0.8
VCC × 0.7
input)
5V tolerant
input pin
VSS + 5.5
V
V
V
CMOS
VCC × 0.2
VCC × 0.3
hysteresis
input pin,
MD0, MD1
VSS - 0.3
L level input
VCC < 2.7 V
Voltage
VILS
(hysteresis
VCC ≥ 2.7 V
VCC × 0.2
VCC × 0.3
input)
5 V tolerant
input pin
VSS - 0.3
VCC - 0.5
VCC < 2.7 V
VCC ≥ 2.7 V, IOH = - 4
mA
H level
VOH
4mA type
-
VCC
V
output voltage
VCC < 2.7 V, IOH = - 2
mA
VCC -
0.45
VSS
- 5
VCC ≥ 2.7 V, IOL = 4 mA
L level
VOL
4mA type
-
-
0.4
+ 5
V
output voltage
VCC < 2.7 V, IOL = 2 mA
-
-
μA
CEC0_0,
CEC0_1,
CEC1_0,
CEC1_1
Input leak
current
IIL
VCC = AVCC = AVRH =
VSS = AVSS = 0.0 V
-
-
+1.8
μA
VCC ≥ 2.7 V
21
-
33
-
66
Pull-up resistor
value
RPU
Pull-up pin
kΩ
VCC < 2.7 V
134
Other than
VCC, VSS,
Input
CIN
-
-
5
15
pF
capacitance
AVCC, AVSS,
AVRH
Document Number: 002-05646 Rev. *E
Page 91 of 149
CY9A150RB Series
12.4 AC Characteristics
12.4.1 Main Clock Input Characteristics
(VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C)
Value
Pin
Parameter
Input frequency
Input clock cycle
Symbol
Conditions
Unit
Remarks
name
Min
4
Max
48
VCC ≥ 2.7V
When crystal oscillator is
MHz
MHz
ns
connected
VCC < 2.7V
4
20
fCH
When using external
clock
-
-
4
20.83
45
48
250
55
5
X0,
X1
When using external
clock
tCYLH
PWH/tCYLH,
PWL/tCYLH
When using external
clock
Input clock pulse
width
-
%
tCF,
tCR
When using external
clock
Input clock rising
-
-
ns
time and falling time
fCM
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
40
40
40
40
40
-
MHz
MHz
MHz
MHz
MHz
ns
Master clock
fCC
Base clock (HCLK/FCLK)
APB0 bus clock[2]
APB1 bus clock[2]
APB2 bus clock[2]
Base clock (HCLK/FCLK)
APB0 bus clock[2]
APB1 bus clock[2]
APB2 bus clock[2]
Internal operating
clock[1] frequency
fCP0
-
fCP1
-
fCP2
-
25
25
25
25
tCYCC
tCYCP0
tCYCP1
tCYCP2
-
ns
Internal operating
clock[1] cycle time
-
ns
-
ns
[1]. For more information about each internal operating clock, see Chapter 2-1: Clock in FM3 Family Peripheral Manual.
[2]. For about each APB bus which each peripheral is connected to, see Block Diagram in this data sheet.
X0
Document Number: 002-05646 Rev. *E
Page 92 of 149
CY9A150RB Series
12.4.2 Sub Clock Input Characteristics
(VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C)
Value
Typ
Pin
Parameter
Symbol
Conditions
Unit
Remarks
name
Min
Max
When crystal oscillator
is connected[1]
-
-
32.768
-
kHz
kHz
μs
Input frequency
fCL
When using external
clock
-
-
32
10
45
-
-
-
100
31.25
55
X0A,
X1A
When using external
clock
Input clock cycle
tCYLL
PWH/tCYLL,
PWL/tCYLL
Input clock pulse
width
When using external
clock
-
%
[1]. For more information about crystal oscillator, see Sub Crystal Oscillator in Handling Devices.
X0A
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Page 93 of 149
CY9A150RB Series
12.4.3 Built-in CR Oscillation Characteristics
12.4.3.1 Built-in High-speed CR
(VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C)
Value
Typ
Symbo
Parameter
Conditions
Unit
Remarks
l
Min
3.94
Max
4.06
TA = + 25°C,VCC ≥ 2.7V
4
4
TA = - 20°C to + 85°C,
3.92
4.08
VCC ≥ 2.7V
TA = - 40°C to + 85°C,
3.88
3.9
4
4
4.12
4.1
When trimming[1]
VCC ≥ 2.7V
Clock frequency
fCRH
MHz
TA = + 25°C, VCC < 2.7V
TA = - 40°C to + 85°C
VCC < 2.7V
3.66
2.8
-
4
4
-
4.20
5.2
30
TA = - 40°C to + 85°C
-
When not trimming
Frequency
[2]
tCRWT
μs
stabilization time
[1]. In the case of using the values in CR trimming area of Flash memory at shipment for frequency/temperature trimming.
[2]. This is the time to stabilize the frequency of High-speed CR clock after setting trimming value. This period is able to use High-speed CR clock
as source clock.
12.4.3.2 Built-in Low-speed CR
(VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C)
Value
Parameter
Symbol
Conditions
Unit
Remarks
Min
50
Typ
100
Max
150
Clock frequency
fCRL
-
kHz
Document Number: 002-05646 Rev. *E
Page 94 of 149
CY9A150RB Series
12.4.4 Operating Conditions of Main PLL
12.4.4.1 Operating Conditions of Main PLL (In the case of using main clock for input of Main PLL)
(VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C)
Value
Parameter
Symbol
Unit
Remarks
Min
100
Typ
Max
-
PLL oscillation stabilization wait time[1]
(LOCK UP time)
tLOCK
fPLLI
-
fPLLO
fCLKPLL
-
μs
PLL input clock frequency
PLL multiplication rate
4
-
-
-
-
16
MHz
5
37
multiplier
MHz
PLL macro oscillation clock frequency
Main PLL clock frequency[2]
75
-
150
40
MHz
[1]. Time from when the PLL starts operating until the oscillation stabilizes.
[2]. For more information about Main PLL clock (CLKPLL), see Chapter 2-1: Clock in FM3 Family Peripheral Manual.
12.4.4.2 Operating Conditions of Main PLL (In the case of using the built-in High-speed CR for input clock of Main PLL)
(VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C)
Value
Parameter
Symbol
Unit
Remarks
Min
100
Typ
Max
PLL oscillation stabilization wait time[1]
(LOCK UP time)
tLOCK
fPLLI
-
fPLLO
fCLKPLL
-
-
μs
PLL input clock frequency
PLL multiplication rate
3.8
19
72
-
4
-
4.2
35
MHz
multiplier
MHz
PLL macro oscillation clock frequency
Main PLL clock frequency[2]
-
150
40
-
MHz
[1]. Time from when the PLL starts operating until the oscillation stabilizes.
[2]. For more information about Main PLL clock (CLKPLL), see Chapter 2-1: Clock in FM3 Family Peripheral Manual.
Note:
◼Make sure to input to the Main PLL source clock, the High-speed CR clock (CLKHC) that the frequency has been trimmed.
◼When setting PLL multiple rate, please take the accuracy of the built-in High-speed CR clock into account and prevent the
master clock from exceeding the maximum frequency.
Main PLL connection
Main PLL
PLLinput
clock
PLL macro
clock
Main clock (CLKMO)
oscillation clock
(CLKPLL)
K
M
Main
PLL
High-speed CR clock
(CLKHC)
divider
divider
N
divider
Document Number: 002-05646 Rev. *E
Page 95 of 149
CY9A150RB Series
12.4.5 Reset Input Characteristics
(VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C)
Value
Pin
Parameter
Reset input time
Symbol
Conditions
Unit
Remarks
name
Min
Max
tINITX
INITX
-
500
-
ns
12.4.6 Power-on Reset Timing
(Vss = 0V, TA = - 40°C to + 85°C)
Value
Typ
Parameter
Symbol
Pin name
Conditions
Unit
Remarks
*1
Min
Max
Power supply shut down time
Power ramp rate
tOFF
-
1
-
-
-
-
ms
Vcc:0.2V to
2.70V
dV/dt
0.9
1000 mV/us *2
0.744 ms
VCC
Time until releasing Power-on
reset
tPRT
-
0.446
*1: VCC must be held below 0.2V for minimum period of tOFF. Improper initialization may occur if this condition is not met.
*2: This dV/dt characteristic is applied at the power-on of cold start (tOFF>1ms).
Note:
−
If tOFF cannot be satisfied designs must assert external reset(INITX) at power-up and at any brownout event per 12. 4. 5.
2.7V
VCC
VDH
0.2V
0.2V
0.2V
dV/dt
tPRT
tOFF
Internal RST
release
start
RST Active
CPU Operation
Glossary
VDH: detection voltage of Low Voltage detection reset. See “12.6 Low-Voltage Detection Characteristics”
Document Number: 002-05646 Rev. *E
Page 96 of 149
CY9A150RB Series
12.4.7 External Bus Timing
12.4.7.1 External bus clock output characteristics
(VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C)
Value
Parameter
Symbol
Pin name
Conditions
Unit
Min
Max
40
VCC ≥ 2.7 V
-
-
MHz
MHz
Output frequency
tCYCLE
MCLKOUT[1]
VCC < 2.7 V
20
The external bus clock (MCLKOUT) is a divided clock of HCLK. For more information about setting of clock divider,
see Chapter 12: External Bus Interface in FM3 Family Peripheral Manual..
When external bus clock is not output, this characteristic does not give any effect on external bus operation.
MCLKOUT
12.4.7.2 External bus signal input/output characteristics
(VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C)
Parameter
Symbol
Conditions
Value
Unit
Remarks
VIH
VIL
0.8 × VCC
0.2 × VCC
0.8 × VCC
0.2 × VCC
V
V
V
V
Signal input characteristics
-
VOH
VOL
Signal output characteristics
VIH
VIL
VIH
VIL
Input signal
VOH
VOL
VOH
VOL
Output signal
Document Number: 002-05646 Rev. *E
Page 97 of 149
CY9A150RB Series
12.4.7.3 Separate Bus Access Asynchronous SRAM Mode
(VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C)
Value
Parameter
Symbol
tOEW
Pin name
Conditions
Unit
Min
Max
VCC ≥ 2.7 V
MOEX Min pulse width
MOEX
MCLK×n-3
-
ns
VCC < 2.7 V
VCC ≥ 2.7 V
VCC < 2.7 V
VCC ≥ 2.7 V
VCC < 2.7 V
VCC ≥ 2.7 V
VCC < 2.7 V
VCC ≥ 2.7 V
VCC < 2.7 V
VCC ≥ 2.7 V
VCC < 2.7 V
VCC ≥ 2.7 V
VCC < 2.7 V
-9
+9
MCSX ↓ → Address output
MCSX[7:0],
MAD[24:0]
tCSL – AV
ns
ns
ns
ns
ns
ns
delay time
-12
+12
MCLK×m+9
MCLK×m+12
MCLK×m+9
MCLK×m+12
MCLK×m+9
MCLK×m+12
MCLK×m+9
MCLK×m+12
-
MOEX,
MOEX ↑ → Address hold time tOEH - AX
0
MAD[24:0]
MCLK×m-9
MCSX ↓ →MOEX ↓ delay
tCSL - OEL
time
MCLK×m-12
MOEX,
MCSX[7:0]
MOEX ↑ → MCSX ↑ time
tOEH - CSH
tCSL - RDQML
tDS - OE
0
MCLK×m-9
MCSX ↓ → MDQM ↓ delay
MCSX,
time
MDQM[1:0]
MCLK×m-12
20
38
MOEX,
Data set up → MOEX ↑ time
MADATA[15:0]
-
VCC ≥ 2.7 V
VCC < 2.7 V
VCC ≥ 2.7 V
VCC < 2.7 V
MOEX,
MOEX ↑ →Data hold time
tDH - OE
0
-
-
ns
ns
MADATA[15:0]
MWEX Min pulse width
tWEW
MWEX
MCLK×n-3
VCC ≥ 2.7 V
VCC < 2.7 V
VCC ≥ 2.7 V
VCC < 2.7 V
VCC ≥ 2.7 V
VCC < 2.7 V
VCC ≥ 2.7 V
VCC < 2.7 V
VCC ≥ 2.7 V
VCC < 2.7 V
VCC ≥ 2.7 V
VCC < 2.7 V
MCLK×m+9
MCLK×m+12
MCLK×n+9
MCLK×n+12
MCLK×m+9
MCLK×m+12
MCLK×n+9
MCLK×n+12
MCLK+9
MWEX ↑ → Address output
MWEX,
tWEH - AX
tCSL - WEL
tWEH - CSH
tCSL-WDQML
tCSL-DV
0
ns
ns
ns
ns
ns
ns
delay time
MAD[24:0]
MCLK×n-9
MCSX ↓ → MWEX ↓ delay
time
MCLK×n-12
MWEX,
MCSX[7:0]
MWEX ↑ → MCSX ↑ delay
0
time
MCLK×n-9
MCLK×n-12
MCLK-9
MCSX ↓→ MDQM ↓ delay
MCSX,
time
MDQM[1:0]
MCSX,
MCSX ↓→ Data output time
MADATA[15:0]
MCLK-12
MCLK+12
MCLK×m+9
MCLK×m+12
MWEX ↑ →
MWEX,
tWEH - DX
0
Data hold time
MADATA[15:0]
Note:
When the external load capacitance CL = 30 pF (m = 0 to 15, n = 1 to 16).
Document Number: 002-05646 Rev. *E
Page 98 of 149
CY9A150RB Series
MCLK
MCSX[7:0]
MAD[24:0]
MOEX
MDQM[1:0]
MWEX
MADATA[15:0]
Document Number: 002-05646 Rev. *E
Page 99 of 149
CY9A150RB Series
12.4.7.4 Separate Bus Access Synchronous SRAM Mode
(VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C)
Value
Parameter
Symbol
tAV
Pin name
Conditions
Unit
Min
Max
9
VCC ≥ 2.7 V
VCC < 2.7 V
VCC ≥ 2.7 V
VCC < 2.7 V
VCC ≥ 2.7 V
VCC < 2.7 V
VCC ≥ 2.7 V
VCC < 2.7 V
VCC ≥ 2.7 V
VCC < 2.7 V
VCC ≥ 2.7 V
VCC < 2.7 V
VCC ≥ 2.7 V
VCC < 2.7 V
VCC ≥ 2.7 V
VCC < 2.7 V
VCC ≥ 2.7 V
VCC < 2.7 V
VCC ≥ 2.7 V
VCC < 2.7 V
VCC ≥ 2.7 V
VCC < 2.7 V
VCC ≥ 2.7 V
VCC < 2.7 V
VCC ≥ 2.7 V
VCC < 2.7 V
MCLK,
Address delay time
1
ns
MAD[24:0]
12
9
tCSL
1
1
1
1
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
12
9
MCLK,
MCSX delay time
MOEX delay time
MCSX[7:0]
tCSH
12
9
tREL
12
9
MCLK,
MOEX
tREH
12
19
37
MCLK,
Data set up →MCLK ↑ time
MCLK ↑ → Data hold time
tDS
-
-
MADATA[15:0]
MCLK,
tDH
0
MADATA[15:0]
9
tWEL
tWEH
tDQML
tDQMH
tODS
tOD
1
12
MCLK,
MWEX
MWEX delay time
9
1
12
9
1
12
MCLK,
MDQM[1:0] delay time
MDQM[1:0]
9
12
1
MCLK+1
1
MCLK+18
MCLK+24
18
MCLK,
MCLK ↑ → Data output time
MCLK ↑ → Data hold time
MADATA[15:0]
MCLK,
MADATA[15:0]
24
Note:
−
When the external load capacitance CL = 30 pF.
Document Number: 002-05646 Rev. *E
Page 100 of 149
CY9A150RB Series
tCYCLE
MCLK
tCSL
tCSH
MCSX[7:0]
MAD[24:0]
MOEX
tAV
tAV
Address
Address
tREL
tREH
tDQML
tDQMH
tDQML
tDQMH
tWEH
tOD
MDQM[1:0]
tWEL
MWEX
tDS
tDH
MADATA[15:0]
RD
Invalid
WD
tODS
Document Number: 002-05646 Rev. *E
Page 101 of 149
CY9A150RB Series
12.4.7.5 Multiplexed Bus Access Asynchronous SRAM Mode
(VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C)
Value
Parameter
Symbol
tALE-CHMADV
tCHMADH
Pin name
Conditions
Unit
ns
Min
Max
+10
VCC ≥ 2.7 V
VCC < 2.7 V
VCC ≥ 2.7 V
VCC < 2.7 V
Multiplexed address
delay time
0
+20
MALE,
MADATA[15:0]
MCLK×n+0
MCLK×n+0
MCLK×n+10
MCLK×n+20
Multiplexed address
hold time
ns
Note:
−
When the external load capacitance CL = 30 pF (m = 0 to 15, n = 1 to 16).
MCLK
MCSX[7:0]
MALE
MAD [24:0]
MOEX
MDQM [1:0]
MWEX
MADATA[15:0]
Document Number: 002-05646 Rev. *E
Page 102 of 149
CY9A150RB Series
12.4.7.6 Multiplexed Bus Access Synchronous SRAM Mode
(VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C)
Value
Parameter
Symbol
tCHAL
Pin name
Conditions
Unit Remarks
Min Max
VCC ≥ 2.7 V
VCC < 2.7 V
VCC ≥ 2.7 V
VCC < 2.7 V
VCC ≥ 2.7 V
9
ns
ns
ns
ns
1
12
MALE delay time
MCLK, ALE
9
tCHAH
1
12
MCLK ↑ → Multiplexed Address
tCHMADV
1
1
tOD
ns
ns
delay time
VCC < 2.7 V
VCC ≥ 2.7 V
VCC < 2.7 V
MCLK, MADATA[15:0]
MCLK ↑ → Multiplexed Data output
tCHMADX
tOD
time
Note:
−
When the external load capacitance CL = 30 pF.
MCLK
MCSX[7:0]
MALE
MAD [24:0]
MOEX
MDQM [1:0]
MWEX
MADATA[15:0]
Document Number: 002-05646 Rev. *E
Page 103 of 149
CY9A150RB Series
12.4.7.7 NAND Flash Memory Mode
(VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C)
Value
Parameter
Symbol
tNREW
Pin name
Conditions
Unit
Min
Max
VCC ≥ 2.7 V
VCC < 2.7 V
VCC ≥ 2.7 V
VCC < 2.7 V
VCC ≥ 2.7 V
VCC < 2.7 V
VCC ≥ 2.7 V
VCC < 2.7 V
VCC ≥ 2.7 V
VCC < 2.7 V
VCC ≥ 2.7 V
VCC < 2.7 V
VCC ≥ 2.7 V
VCC < 2.7 V
VCC ≥ 2.7 V
VCC < 2.7 V
VCC ≥ 2.7 V
VCC < 2.7 V
VCC ≥ 2.7 V
VCC < 2.7 V
MNREX Min pulse width
MNREX
MCLK×n-3
-
ns
20
38
-
-
MNREX,
Data setup → MNREX↑time
MNREX↑→ Data hold time
MNALE↑→MNWEX delay time
MNALE↓→MNWEX delay time
MNCLE↑→MNWEX delay time
MNWEX↑→MNCLE delay time
MNWEX Min pulse width
tDS – NRE
ns
ns
ns
ns
ns
ns
ns
ns
ns
MADATA[15:0]
MNREX,
tDH – NRE
0
-
MADATA[15:0]
MCLK×m-9
MCLK×m-12
MCLK×m-9
MCLK×m-12
MCLK×m-9
MCLK×m-12
MCLK×m+9
MCLK×m+12
MCLK×m+9
MCLK×m+12
MCLK×m+9
MCLK×m+12
MCLK×m+9
MCLK×m+12
MNALE,
MNWEX
tALEH - NWEL
tALEL - NWEL
tCLEH - NWEL
tNWEH - CLEL
tNWEW
MNALE,
MNWEX
MNCLE,
MNWEX
MNCLE,
MNWEX
0
MNWEX
MCLK×n-3
-
- 9
+ 9
+12
MNWEX,
MNWEX↓→Data output time
MNWEX↑→Data hold time
tNWEL – DV
MADATA[15:0]
-12
MCLK×m+9
MCLK×m+12
MNWEX,
tNWEH – DX
0
MADATA[15:0]
Note:
−
When the external load capacitance CL = 30 pF (m=0 to 15, n=1 to 16).
Document Number: 002-05646 Rev. *E
Page 104 of 149
CY9A150RB Series
Figure 1. NAND Flash Memory Read
MCLK
MNREX
MADATA[15:0]
Read
Figure 2. NAND Flash Memory Address Write
MCLK
MNALE
MNCLE
MNWEX
MADATA[15:0]
Write
Document Number: 002-05646 Rev. *E
Page 105 of 149
CY9A150RB Series
Figure 3. NAND Flash Memory Command Write
MCLK
MNALE
MNCLE
MNWEX
MADATA[15:0]
Write
Document Number: 002-05646 Rev. *E
Page 106 of 149
CY9A150RB Series
12.4.7.8 External Ready Input Timing
(VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C)
Value
Parameter
Symbol
Pin name Conditions
Unit
Remarks
Min
19
Max
VCC ≥ 2.7 V
MCLK ↑ MRDY input
MCLK,
MRDY
tRDYI
-
ns
setup time
VCC < 2.7 V
37
When RDY is input
···
MCLK
Over 2cycles
Original
MOEX
MWEX
tRDYI
MRDY
When RDY is released
··· ···
MCLK
2 cycles
Extended
MOEX
MWEX
tRDYI
0.5×VCC
MRDY
Document Number: 002-05646 Rev. *E
Page 107 of 149
CY9A150RB Series
12.4.8 Base Timer Input Timing
12.4.8.1 Timer input timing
(VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C)
Value
Parameter
Symbol
Pin name
Conditions
Unit
Remarks
Min
Max
TIOAn/TIOBn
tTIWH
,
Input pulse width
-
2tCYCP
-
ns
(when using as
ECK, TIN)
tTIWL
tTIWH
tTIWL
ECK
TIN
VIHS
VIHS
VILS
VILS
12.4.8.2 Trigger input timing
(VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C)
Value
Parameter
Symbol
Pin name
Conditions
Unit
Remarks
Min
Max
TIOAn/TIOBn
tTRGH
,
Input pulse width
-
2tCYCP
-
ns
(when using
as TGIN)
tTRGL
tTRGH
tTRGL
VIHS
VIHS
TGIN
VILS
VILS
Note:
−
tCYCP indicates the APB bus clock cycle time.
About the APB bus number which the Base Timer is connected to, see Block Diagram in this data sheet.
Document Number: 002-05646 Rev. *E
Page 108 of 149
CY9A150RB Series
12.4.9 CSIO/UART Timing
12.4.9.1 CSIO (SPI = 0, SCINV = 0)
(VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C)
VCC < 2.7 V
Min Max
VCC ≥ 2.7 V
Pin
Parameter
Symbol
Conditions
Unit
name
Min
-
Max
Baud rate
-
-
-
-
8
-
8
-
Mbps
ns
Serial clock cycle time
tSCYC
SCKx
4tCYCP
4tCYCP
SCKx,
SOTx
SCK ↓ → SOT delay time
tSLOVI
- 30
50
0
+ 30
- 20
30
0
+ 20
ns
ns
ns
Master mode
SCKx,
SINx
SIN → SCK ↑ setup time
SCK ↑ → SIN hold time
tIVSHI
-
-
-
-
SCKx,
SINx
tSHIXI
Serial clock L pulse width
Serial clock H pulse width
tSLSH
tSHSL
SCKx
SCKx
2tCYCP - 10
tCYCP + 10
-
-
2tCYCP - 10
tCYCP + 10
-
-
ns
ns
SCKx,
SOTx
SCK ↓ → SOT delay time
SIN → SCK ↑ setup time
tSLOVE
tIVSHE
tSHIXE
-
50
-
-
30
-
ns
ns
ns
SCKx,
SINx
Slave mode
10
20
10
20
SCKx,
SINx
SCK ↑ → SIN hold time
-
-
SCK falling time
tF
SCKx
SCKx
-
-
5
5
-
-
5
5
ns
ns
SCK rising time
tR
Notes:
−
−
The above characteristics apply to clock synchronous mode.
tCYCP indicates the APB bus clock cycle time. About the APB bus number which Multi-function
Serial is connected to, see Block Diagram in this data sheet.
−
−
These characteristics only guarantee the same relocate port number.
For example, the combination of SCKx_0 and SOTx_1 is not guaranteed.
When the external load capacitance CL = 30 pF.
Document Number: 002-05646 Rev. *E
Page 109 of 149
CY9A150RB Series
tSCYC
VOH
SCK
SOT
VOL
VOL
tSLOVI
VOH
VOL
tIVSHI
VIH
VIL
tSHIXI
VIH
VIL
SIN
Master mode
tSLSH
tSHSL
VIH
tR
VIH
tF
VIH
SCK
VIL
VIL
tSLOVE
VOH
VOL
SOT
SIN
tIVSHE
tSHIXE
VIH
VIL
VIH
VIL
Slave mode
Document Number: 002-05646 Rev. *E
Page 110 of 149
CY9A150RB Series
12.4.9.2 CSIO (SPI = 0, SCINV = 1)
(VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C)
VCC < 2.7 V
VCC ≥ 2.7 V
Pin
Parameter
Symbol
Conditions
Unit
name
Min
-
Max
Min
Max
Baud rate
-
-
-
8
-
-
8
-
Mbps
ns
Serial clock cycle time
tSCYC
tSHOVI
SCKx
4tCYCP
4tCYCP
SCKx,
SOTx
SCK ↑ → SOT delay time
- 30
50
0
+ 30
- 20
30
0
+ 20
ns
ns
ns
Master mode
SCKx,
SINx
SIN → SCK ↓ setup time
SCK ↓ → SIN hold time
tIVSLI
-
-
-
-
SCKx,
SINx
tSLIXI
tSLSH
tSHSL
Serial clock L pulse width
Serial clock H pulse width
SCKx
SCKx
2tCYCP - 10
tCYCP + 10
-
-
2tCYCP - 10
tCYCP + 10
-
-
ns
ns
SCKx,
SOTx
SCK ↑ → SOT delay time
SIN → SCK ↓ setup time
tSHOVE
tIVSLE
tSLIXE
-
50
-
-
30
-
ns
ns
ns
SCKx,
SINx
Slave mode
10
20
10
20
SCKx,
SINx
SCK ↓ → SIN hold time
-
-
SCK falling time
tF
SCKx
SCKx
-
-
5
5
-
-
5
5
ns
ns
SCK rising time
tR
Notes:
−
−
The above characteristics apply to clock synchronous mode.
tCYCP indicates the APB bus clock cycle time. About the APB bus number which Multi-function
Serial is connected to, see Block Diagram in this data sheet.
−
−
These characteristics only guarantee the same relocate port number.
For example, the combination of SCKx_0 and SOTx_1 is not guaranteed.
When the external load capacitance CL = 30 pF.
Document Number: 002-05646 Rev. *E
Page 111 of 149
CY9A150RB Series
tSCYC
VOH
VOH
SCK
VOL
tSHOVI
VOH
VOL
SOT
SIN
tIVSLI
VIH
VIL
tSLIXI
VIH
VIL
Master mode
tSHSL
tSLSH
VIH
VIH
tF
SCK
VIL
VIL
tR
VIL
tSHOVE
VOH
VOL
SOT
SIN
tIVSLE
tSLIXE
VIH
VIL
VIH
VIL
Slave mode
Document Number: 002-05646 Rev. *E
Page 112 of 149
CY9A150RB Series
12.4.9.3 CSIO (SPI = 1, SCINV = 0)
(VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C)
VCC < 2.7 V
VCC ≥ 2.7 V
Pin
Parameter
Symbol
Conditions
Unit
name
Min
-
Max
Min
-
Max
Baud rate
-
-
-
8
-
8
-
Mbps
ns
Serial clock cycle time
tSCYC
tSHOVI
SCKx
4tCYCP
4tCYCP
SCKx,
SOTx
SCK ↑ → SOT delay time
- 30
+ 30
- 20
+ 20
ns
ns
ns
ns
SCKx,
SINx
SIN → SCK ↓ setup time
SCK ↓→ SIN hold time
SOT → SCK ↓ delay time
tIVSLI
tSLIXI
tSOVLI
50
0
-
-
-
30
0
-
-
-
Master mode
SCKx,
SINx
SCKx,
SOTx
2tCYCP - 30
2tCYCP - 30
Serial clock L pulse width
Serial clock H pulse width
tSLSH
tSHSL
SCKx
SCKx
2tCYCP - 10
tCYCP + 10
-
-
2tCYCP - 10
tCYCP + 10
-
-
ns
ns
SCKx,
SOTx
SCK ↑ → SOT delay time
SIN → SCK ↓ setup time
tSHOVE
tIVSLE
tSLIXE
-
50
-
-
30
-
ns
ns
ns
SCKx,
SINx
Slave mode
10
20
10
20
SCKx,
SINx
SCK ↓→ SIN hold time
-
-
SCK falling time
tF
SCKx
SCKx
-
-
5
5
-
-
5
5
ns
ns
SCK rising time
tR
Notes:
−
−
The above characteristics apply to clock synchronous mode.
tCYCP indicates the APB bus clock cycle time. About the APB bus number which Multi-function
Serial is connected to, see Block Diagram in this data sheet.
−
−
These characteristics only guarantee the same relocate port number.
For example, the combination of SCKx_0 and SOTx_1 is not guaranteed.
When the external load capacitance CL = 30 pF.
Document Number: 002-05646 Rev. *E
Page 113 of 149
CY9A150RB Series
tSCYC
VOH
SCK
VOL
VOL
tSHOVI
tSOVLI
VOH
VOL
VOH
VOL
SOT
SIN
tIVSLI
tSLIXI
VIH
VIL
VIH
VIL
Master mode
tSLSH
tSHSL
VIH
tF
VIH
VIH
SCK
SOT
SIN
VIL
VIL
tR
tSHOVE
*
VOH
VOL
VOH
VOL
tIVSLE
tSLIXE
VIH
VIL
VIH
VIL
Slave mode
*: Changes when writing to TDR register
Document Number: 002-05646 Rev. *E
Page 114 of 149
CY9A150RB Series
12.4.9.4 CSIO (SPI = 1, SCINV = 1)
(VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C)
VCC < 2.7 V
VCC ≥ 2.7 V
Pin
Parameter
Symbol
Conditions
Unit
name
Min
-
Max
Min
-
Max
Baud rate
-
-
-
8
-
8
-
Mbps
ns
Serial clock cycle time
tSCYC
tSLOVI
SCKx
4tCYCP
4tCYCP
SCKx,
SOTx
SCK ↓ → SOT delay time
- 30
+ 30
- 20
+ 20
ns
ns
ns
ns
SCKx,
SINx
SIN → SCK ↑ setup time
SCK ↑ → SIN hold time
SOT → SCK ↑ delay time
tIVSHI
tSHIXI
tSOVHI
50
0
-
-
-
30
0
-
-
-
Master mode
SCKx,
SINx
SCKx,
SOTx
2tCYCP - 30
2tCYCP - 30
Serial clock L pulse width
Serial clock H pulse width
tSLSH
tSHSL
SCKx
SCKx
2tCYCP - 10
tCYCP + 10
-
-
2tCYCP - 10
tCYCP + 10
-
-
ns
ns
SCKx,
SOTx
SCK ↓ → SOT delay time
SIN → SCK ↑ setup time
tSLOVE
tIVSHE
tSHIXE
-
50
-
-
30
-
ns
ns
ns
SCKx,
SINx
Slave mode
10
20
10
20
SCKx,
SINx
SCK ↑ → SIN hold time
-
-
SCK falling time
tF
SCKx
SCKx
-
-
5
5
-
-
5
5
ns
ns
SCK rising time
tR
Notes:
−
−
The above characteristics apply to clock synchronous mode.
tCYCP indicates the APB bus clock cycle time. About the APB bus number which Multi-function
Serial is connected to, see Block Diagram in this data sheet.
−
−
These characteristics only guarantee the same relocate port number.
For example, the combination of SCKx_0 and SOTx_1 is not guaranteed.
When the external load capacitance CL = 30 pF.
Document Number: 002-05646 Rev. *E
Page 115 of 149
CY9A150RB Series
tSCYC
VOH
VOH
SCK
VOL
tSOVHI
tSLOVI
VOH
VOL
VOH
VOL
SOT
SIN
tSHIXI
tIVSHI
VIH
VIL
VIH
VIL
Master mode
tR
tF
tSHSL
tSLSH
VIH
VIH
SCK
VIL
VIL
VIL
tSLOVE
VOH
VOL
VOH
VOL
SOT
SIN
tIVSHE
tSHIXE
VIH
VIL
VIH
VIL
Slave mode
12.4.9.5 UART external clock input (EXT = 1)
(VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C)
Value
Parameter
Symbol Conditions
Unit
ns
Remarks
Min
Max
Serial clock L pulse width
Serial clock H pulse width
SCK falling time
tSLSH
tCYCP + 10
-
-
tSHSL
tCYCP + 10
ns
ns
ns
CL = 30 pF
tF
-
-
5
5
SCK rising time
tR
tF
tR
tSHSL
tSLSH
SCK
VIH
VIH
VIH
IL
IL
IL
V
V
V
Document Number: 002-05646 Rev. *E
Page 116 of 149
CY9A150RB Series
12.4.10 External Input Timing
(VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C)
Value
Min
Condition
s
Parameter
Symbol
Pin name
Unit
Remarks
Ma
x
A/D converter trigger
input
ADTG
Free-run timer input
clock
[1]
FRCKx
-
2tCYCP
-
ns
ns
ICxx
Input capture
tINH,
tINL
Input pulse width
DTIxX
Waveform generator
2tCYCP
+
[2]
-
External interrupt,
NMI
100[1]
INTxx, NMIX
WKUPx
[3]
[4]
500
-
-
ns
ns
600
Deep Standby wake up
[1]. tCYCP indicates the APB bus clock cycle time.
About the APB bus number which the Multi-function Timer is connected to, see Block Diagram in this data sheet.
[2]. When in Run mode, in Sleep mode.
[3]. When in Stop mode, in Timer mode.
[4]. When in Deep Standby RTC mode, in Deep Standby Stop mode.
Document Number: 002-05646 Rev. *E
Page 117 of 149
CY9A150RB Series
12.4.11 Quadrature Position/Revolution Counter timing
(VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C)
Value
Parameter
AIN pin H width
Symbol
Conditions
Unit
Min
Max
tAHL
tALL
tBHL
tBLL
-
-
-
-
AIN pin L width
BIN pin H width
BIN pin L width
BIN rising time from AIN pin H
level
tAUBU
PC_Mode2 or PC_Mode3
PC_Mode2 or PC_Mode3
AIN falling time from BIN pin H
level
tBUAD
BIN falling time from AIN pin L
level
tADBD
tBDAU
tBUAU
PC_Mode2 or PC_Mode3
PC_Mode2 or PC_Mode3
PC_Mode2 or PC_Mode3
AIN rising time from
AIN rising time from BIN pin H
level
[1]
2tCYCP
-
ns
BIN falling time from AIN pin H
level
tAUBD
tBDAD
tADBU
PC_Mode2 or PC_Mode3
PC_Mode2 or PC_Mode3
PC_Mode2 or PC_Mode3
AIN falling time from BIN pin L
level
BIN rising time from AIN pin L
level
ZIN pin H width
ZIN pin L width
tZHL
tZLL
QCR:CGSC=0
QCR:CGSC=0
AIN/BIN rising and falling time
from determined ZIN level
tZABE
QCR:CGSC=1
QCR:CGSC=1
Determined ZIN level from
tABEZ
AIN/BIN rising and falling time
[1]. tCYCP indicates the APB bus clock cycle time. About the APB bus number which the Quadrature Position/Revolution Counter is connected to,
see Block Diagram in this data sheet.
Document Number: 002-05646 Rev. *E
Page 118 of 149
CY9A150RB Series
tALL
tAHL
AIN
BIN
tADBD
tAUBU
tBUAD
tBDAU
tBHL
tBLL
tBLL
tBHL
BIN
AIN
tBDAD
tBUAU
tAUBD
tADBU
tAHL
tALL
Document Number: 002-05646 Rev. *E
Page 119 of 149
CY9A150RB Series
ZIN
ZIN
AIN/BIN
Document Number: 002-05646 Rev. *E
Page 120 of 149
CY9A150RB Series
12.4.12 I2C Timing
(VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C)
Standard-mode
Fast-mode
Parameter
Symbol Conditions
Unit Remarks
Min
Max
Min
Max
SCL clock frequency
fSCL
0
100
0
400
kHz
(Repeated) START condition hold
tHDSTA
4.0
-
0.6
-
μs
time SDA ↓ → SCL ↓
SCL clock L width
SCL clock H width
tLOW
4.7
4.0
-
-
1.3
0.6
-
-
μs
μs
tHIGH
(Repeated) START condition
tSUSTA
tHDDAT
tSUDAT
4.7
0
-
3.45[2]
-
0.6
0
-
0.9[3]
-
μs
μs
ns
setup time SCL ↑ → SDA ↓
CL = 30 pF,
Data hold time SCL ↓ → SDA ↓ ↑
[1]
R = (VP/IOL
)
Data setup time
250
100
SDA ↓ ↑ → SCL ↑
STOP condition setup time
tSUSTO
4.0
-
0.6
-
μs
SCL ↑ → SDA ↑
Bus free time between
tBUF
4.7
-
-
1.3
-
-
μs
STOP condition and START
condition
[4]
[4]
Noise filter
tSP
-
2 tCYCP
2 tCYCP
ns
[1]. R and CL represent the pull-up resistor and load capacitance of the SCL and SDA lines, respectively. VP indicates the power supply voltage of
the pull-up resistor and IOL indicates VOL guaranteed current.
[2]. The maximum tHDDAT must satisfy that it does not extend at least L period (tLOW) of device's SCL signal.
[3]. A Fast-mode I2C bus device can be used on a Standard-mode I2C bus system as long as the device satisfies the requirement of tSUDAT ≥ 250 ns.
[4]. tCYCP is the APB bus clock cycle time. About the APB bus number that I2C is connected to, see Block Diagram in this data sheet.
To use Standard-mode, set the APB bus clock at 2 MHz or more. To use Fast-mode, set the APB bus clock at 8 MHz or more.
SDA
SCL
Document Number: 002-05646 Rev. *E
Page 121 of 149
CY9A150RB Series
12.4.13 ETM Timing
(VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C)
Value
Min
Parameter
Symbol
Pin name
Conditions
Unit
Remarks
Max
11
15
40
20
-
VCC ≥ 2.7V
VCC < 2.7V
VCC ≥ 2.7V
VCC < 2.7V
VCC ≥ 2.7V
VCC < 2.7V
2
2
TRACECLK,
TRACED[3:0]
Data hold
tETMH
ns
-
MHz
MHz
ns
TRACECLK frequency
1/ tTRACE
-
TRACECLK
25
50
TRACECLK clock cycle tTRACE
-
ns
Note:
−
When the external load capacitance CL = 30 pF.
HCLK
TRACECLK
TRACED[3:0]
Document Number: 002-05646 Rev. *E
Page 122 of 149
CY9A150RB Series
12.4.14 JTAG Timing
(VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C)
Value
Parameter
TMS, TDI setup time
TMS, TDI hold time
TDO delay time
Symbol
tJTAGS
Pin name
Conditions
Unit
Remarks
Min
Max
VCC ≥ 2.7V
VCC < 2.7V
VCC ≥ 2.7V
VCC < 2.7V
VCC ≥ 2.7V
VCC < 2.7V
TCK,
15
-
ns
ns
ns
TMS, TDI
TCK,
tJTAGH
15
-
TMS, TDI
-
-
25
45
TCK,
TDO
tJTAGD
Note:
−
When the external load capacitance CL = 30 pF.
TCK
TMS/TDI
TDO
Document Number: 002-05646 Rev. *E
Page 123 of 149
CY9A150RB Series
12.5 12-bit A/D Converter
12.5.1 Electrical Characteristics for the A/D Converter
(VCC = AVCC = 1.65V to 3.6V, VSS = AVSS = 0V, TA = - 40°C to + 85°C)
Value
Typ
Pin
Parameter
Resolution
Symbol
Unit
Remarks
name
Min
Max
12
-
-
-
-
-
-
-
-
bit
Integral Nonlinearity
Differential Nonlinearity
Zero transition voltage
Full-scale transition
voltage
-
-
± 2.4
± 2.3
± 7
± 4.5
± 2.5
± 15
LSB
LSB
mV
-
VZT
ANxx
VFST
ANxx
-
AVRH ± 7
AVRH ± 15
mV
2.0
4.0
10
-
-
-
-
-
-
-
-
-
AVCC ≥ 2.7 V
1.8 V< AVCC < 2.7 V
1.65 V< AVCC < 1.8 V
AVCC ≥ 2.7 V
Conversion time[1]
Sampling time[2]
-
-
μs
0.6
1.2
3.0
100
200
500
tS
-
-
10
us
ns
1.8 V< AVCC < 2.7 V
1.65 V< AVCC < 1.8 V
AVCC ≥ 2.7 V
Compare clock cycle[3]
tCCK
-
1000
1.0
1.8 V< AVCC < 2.7 V
1.65 V< AVCC < 1.8 V
State transition time to
operation permission
Analog input capacity
tSTT
-
-
-
-
-
-
μs
CAIN
9.4
2.2
5.5
10.5
4
pF
AVCC ≥ 2.7 V
Analog input resistor
RAIN
-
-
-
kΩ
1.8 V< AVCC < 2.7 V
1.65 V< AVCC < 1.8 V
Interchannel disparity
Analog port input leak
current
-
-
-
-
-
-
-
-
-
-
-
LSB
μA
V
ANxx
ANxx
AVRH
5
Analog input voltage
AVSS
2.7
AVRH
AVCC
AVCC ≥ 2.7 V
Reference voltage
V
AVCC
AVCC < 2.7 V
[1]. The conversion time is the value of sampling time (tS) + compare time (tC).
The condition of the minimum conversion time is the following.
AVCC ≥ 2.7 V, HCLK=40 MHz
sampling time: 0.6 μs, compare time: 1.4 μs
sampling time: 1.2 μs, compare time: 2.8 μs
sampling time: 3 μs, compare time: 7 μs
1.8 V < AVCC < 2.7 V, HCLK=40 MHz
1.65 V < AVCC < 1.8 V, HCLK=40 MHz
Ensure that it satisfies the value of the sampling time (tS) and compare clock cycle (tCCK).
For setting of the sampling time and compare clock cycle, see Chapter 1-1: A/D Converter in FM3 Family Peripheral Manual. Analog Macro Part.
The register settings of the A/D Converter are reflected in the operation according to the APB bus clock timing.
For the number of the APB bus to which the A/D Converter is connected, see Block Diagram. The base clock (HCLK) is used to generate the
sampling time and the compare clock cycle.
[2]. A necessary sampling time changes by external impedance.
Ensure that it sets the sampling time to satisfy (Equation 1).
[3]. The compare time (tC) is the value of (Equation 2).
Document Number: 002-05646 Rev. *E
Page 124 of 149
CY9A150RB Series
ANxx
Comparator
Analog input pin
REXT
RAIN
Analog signal
source
CAIN
(Equation 1) tS ≥ ( RAIN + REXT ) × CAIN × 9
tS: Sampling time[ns]
RAIN: input resistor of A/D[kΩ] = 2.2 kΩ at 2.7 V < AVCC < 3.6 V
input resistor of A/D[kΩ] = 5.5 kΩ at 1.8 V < AVCC < 2.7 V
input resistor of A/D[kΩ] = 10.5 kΩ at 1.65 V < AVCC < 1.8 V
CAIN: input capacity of A/D[pF] = 9.4 pF at 1.65 V < AVCC < 3.6 V
REXT: Output impedance of external circuit[kΩ]
(Equation 2) tC = tCCK × 14
tC: Compare time
tCCK: Compare clock cycle
Document Number: 002-05646 Rev. *E
Page 125 of 149
CY9A150RB Series
12.5.2 Definition of 12-bit A/D Converter Terms
◼Resolution: Analog variation that is recognized by an A/D converter.
◼Integral Nonlinearity: Deviation of the line between the zero-transition point
(0b000000000000 ←→ 0b000000000001) and the full-scale transition point
(0b111111111110 ←→ 0b111111111111) from the actual conversion characteristics.
◼Differential Nonlinearity: Deviation from the ideal value of the input voltage that is required to change the output code by 1 LSB.
Integral Nonlinearity
Differential Nonlinearity
0xFFF
Actual conversion
Actual conversion
characteristics
0xFFE
0xFFD
0x(N+1)
0xN
characteristics
{1 LSB(N-1) + VZT}
VFST
Ideal characteristics
(Actually-
measured
value)
VNT
0x004
(Actual
value)
V(N+1)T
(Actually-measured
value)
0x(N-1)
0x(N-2)
0x003
0x002
Actual conversion
characteristics
VNT
(Asured
value)
Ideal characteristics
0x001
ly-measured value)
Analog input
VZT
Actual conversion characteristics
AVSS
AVRH
AVSS
AVRH
Analog input
VNT - {1LSB × (N - 1) + VZT}
1LSB
Integral Nonlinearity of digital output N =
Differential Nonlinearity of digital output N =
[LSB]
V(N + 1) T - VNT
- 1 [LSB]
1LSB
VFST - VZT
1LSB =
4094
N: A/D converter digital output value.
VZT: Voltage at which the digital output changes from 0x000 to 0x001.
VFST: Voltage at which the digital output changes from 0xFFE to 0xFFF.
VNT: Voltage at which the digital output changes from 0x(N − 1) to 0xN.
Document Number: 002-05646 Rev. *E
Page 126 of 149
CY9A150RB Series
12.6 Low-Voltage Detection Characteristics
12.6.1 Low-Voltage Detection Reset
(TA = - 40°C to + 85°C)
Value
Typ
Parameter
Symbol
Conditions
SVHR[1] = 00000
SVHR[1] = 00001
SVHR[1] = 00010
SVHR[1] = 00011
SVHR[1] = 00100
SVHR[1] = 00101
SVHR[1] = 00110
SVHR[1] = 00111
SVHR[1] = 01000
SVHR[1] = 01001
SVHR[1] = 01010
SVHR[1] = 01011
SVHR[1] = 01100
SVHR[1] = 01101
SVHR[1] = 01110
SVHR[1] = 01111
Unit
Remarks
Min
1.38
Max
1.60
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
1.50
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
1.43
1.43
1.55
1.55
1.65
1.65
Same as SVHR = 00000 value
1.47 1.60 1.73
Same as SVHR = 00000 value
1.52 1.65 1.78
Same as SVHR = 00000 value
1.56 1.70 1.84
Same as SVHR = 00000 value
1.61 1.75 1.89
Same as SVHR = 00000 value
1.66 1.80 1.94
Same as SVHR = 00000 value
1.70 1.85 2.00
Same as SVHR = 00000 value
1.75 1.90 2.05
Same as SVHR = 00000 value
1.79 1.95 2.11
Same as SVHR = 00000 value
1.84 2.00 2.16
Same as SVHR = 00000 value
1.89 2.05 2.21
Same as SVHR = 00000 value
2.30 2.50 2.70
Same as SVHR = 00000 value
2.39 2.60 2.81
Same as SVHR = 00000 value
2.48 2.70 2.92
Same as SVHR = 00000 value
2.58 2.80 3.02
Same as SVHR = 00000 value
Document Number: 002-05646 Rev. *E
Page 127 of 149
CY9A150RB Series
Value
Typ
Parameter
Symbol
Conditions
SVHR[1] = 10000
SVHR[1] = 10001
SVHR[1] = 10010
SVHR[1] = 10011
Unit
Remarks
Min
2.67
Max
3.13
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
2.90
V
V
V
V
V
V
V
V
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
Same as SVHR = 00000 value
2.76 3.00 3.24
Same as SVHR = 00000 value
2.85 3.10 3.35
Same as SVHR = 00000 value
2.94 3.20 3.46
Same as SVHR = 00000 value
LVD stabilization
wait time
5200 ×
tLVDW
-
-
-
-
-
-
μs
μs
[2]
tCYCP
LVD detection delay
time
tLVDDL
200
[1]. The SVHR bit of Low-Voltage Detection Voltage Control Register (LVD_CTL) is initialized to 00000 by Low-Voltage Detection Reset.
[2]. tCYCP indicates the APB2 bus clock cycle time.
Document Number: 002-05646 Rev. *E
Page 128 of 149
CY9A150RB Series
12.6.2 Interrupt of Low-Voltage Detection
(TA = - 40°C to + 85°C)
Value
Typ
Parameter
Symbol
Conditions
SVHI = 00100
SVHI = 00101
SVHI = 00110
SVHI = 00111
SVHI = 01000
SVHI = 01001
SVHI = 01010
SVHI = 01011
SVHI = 01100
SVHI = 01101
SVHI = 01110
SVHI = 01111
SVHI = 10000
SVHI = 10001
SVHI = 10010
SVHI = 10011
-
Unit
Remarks
Min
1.56
1.61
1.61
1.66
1.66
1.70
1.70
1.75
1.75
1.79
1.79
1.84
1.84
1.89
1.89
1.93
2.30
2.39
2.39
2.48
2.48
2.58
2.58
2.67
2.67
2.76
2.76
2.85
2.85
2.94
2.94
3.04
Max
1.84
1.89
1.89
1.94
1.94
2.00
2.00
2.05
2.05
2.11
2.11
2.16
2.16
2.21
2.21
2.27
2.70
2.81
2.81
2.92
2.92
3.02
3.02
3.13
3.13
3.24
3.24
3.35
3.35
3.46
3.46
3.56
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
LVD stabilization wait
time
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
1.70
1.75
1.75
1.80
1.80
1.85
1.85
1.90
1.90
1.95
1.95
2.00
2.00
2.05
2.05
2.10
2.50
2.60
2.60
2.70
2.70
2.80
2.80
2.90
2.90
3.00
3.00
3.10
3.10
3.20
3.20
3.30
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
[1]
tLVDW
-
-
-
-
5200 × tCYCP
μs
μs
LVD detection delay
time
tLVDDL
-
200
[1]. tCYCP indicates the APB2 bus clock cycle time.
Document Number: 002-05646 Rev. *E
Page 129 of 149
CY9A150RB Series
12.7 Flash Memory Write/Erase Characteristics
12.7.1 Write / Erase time
(VCC = 1.65V to 3.6V, TA = - 40°C to + 85°C)
Value
Parameter
Unit
Remarks
Typ[1]
1.1
Max[1]
Large Sector
Small Sector
2.7
0.9
Sector erase
time
s
Includes write time prior to internal erase
0.3
Half word (16-bit)
write time
30
528
μs
Not including system-level overhead time
Includes write time prior to internal erase
Chip erase time
11.2
30.5
s
[1].The typical value is immediately after shipment, the maximum value is guarantee value under 100,000 cycle of erase/write.
12.7.2 Write cycles and data hold time
Erase/write cycles (cycle)
1,000
Data hold time (year)
Remarks
20[1]
10*
10,000
[1]. At average + 85°C
Document Number: 002-05646 Rev. *E
Page 130 of 149
CY9A150RB Series
12.8 Return Time from Low-Power Consumption Mode
12.8.1 Return Factor: Interrupt/WKUP
The return time from Low-Power consumption mode is indicated as follows. It is from receiving the return factor to starting the
program operation.
12.8.1.1 Return Count Time
(VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C)
Value
Parameter
Symbol
Unit
μs
Remarks
Typ
Max[1]
Sleep mode
tCYCC
High-speed CR Timer mode,
40
80
μs
Main Timer mode, PLL Timer mode
Low-speed CR Timer mode
Sub Timer mode
350
690
278
318
278
700
880
523
603
523
μs
μs
μs
μs
μs
tICNT
RTC mode, Stop mode
When RAM is off
When RAM is on
Deep Standby RTC mode
Deep Standby Stop mode
[1]. The maximum value depends on the accuracy of built-in CR.
12.8.1.2 Operation example of return from Low-Power consumption mode (by external interrupt[1])
External
interrupt
Interrupt factor
Active
accept
tICNT
Interrupt factor
clear by CPU
CPU
Operation
Start
[1]. External interrupt is set to detecting fall edge.
Document Number: 002-05646 Rev. *E
Page 131 of 149
CY9A150RB Series
12.8.1.3 Operation example of return from Low-Power consumption mode (by internal resource interrupt[1])
Internal
resource
interrupt
Interrupt factor
accept
Active
tICNT
Interrupt factor
clear by CPU
CPU
Operation
Start
[1]. Internal resource interrupt is not included in return factor by the kind of Low-Power consumption mode.
Notes:
−
The return factor is different in each Low-Power consumption modes. See Chapter 6: Low
Power Consumption Mode and Operations of Standby Modes in FM3 Family Peripheral
Manual.
−
When interrupt recoveries, the operation mode that CPU recoveries depend on the state before
the Low-Power consumption mode transition. See Chapter 6: Low Power Consumption Mode
in FM3 Family Peripheral Manual.
Document Number: 002-05646 Rev. *E
Page 132 of 149
CY9A150RB Series
12.8.2 Return Factor: Reset
The return time from Low-Power consumption mode is indicated as follows. It is from releasing reset to starting the program
operation.
12.8.2.1 Return Count Time
(VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C)
Value
Parameter
Symbol
Unit
μs
Remarks
Typ
Max[1]
Sleep mode
148
263
High-speed CR Timer mode,
148
263
μs
Main Timer mode, PLL Timer mode
Low-speed CR Timer mode
Sub Timer mode
258
322
278
318
278
483
516
523
603
523
μs
μs
μs
μs
μs
tRCNT
RTC/Stop mode
When RAM is off
When RAM is on
Deep Standby RTC mode
Deep Standby Stop mode
[1]. The maximum value depends on the accuracy of built-in CR.
12.8.2.2 Operation example of return from Low-Power consumption mode (by INITX)
INITX
Internal reset
Reset active
Release
tRCNT
CPU
Operation
Start
Document Number: 002-05646 Rev. *E
Page 133 of 149
CY9A150RB Series
12.8.2.3 Operation example of return from low power consumption mode (by internal resource reset[1])
Internal
resource
reset
Internal reset
Reset active
Release
tRCNT
CPU
Operation
Start
[1]. Internal resource reset is not included in return factor by the kind of Low-Power consumption mode.
Notes:
−
−
−
−
−
The return factor is different in each Low-Power consumption modes.
See Chapter 6: Low Power Consumption Mode and Operations of Standby Modes in
FM3 Family Peripheral Manual
When interrupt recoveries, the operation mode that CPU recoveries depend on the state before
the Low-Power consumption mode transition. See Chapter 6: Low Power Consumption Mode
in FM3 Family Peripheral Manual
The time during the power-on reset/low-voltage detection reset is excluded.
See 12.4.6 Power-on Reset Timing in 12.4 AC Characteristics in Electrical Characteristics for
the detail on the time during the power-on reset/low-voltage detection reset.
When in recovery from reset, CPU changes to the High-speed CR Run mode. When using the
main clock or the PLL clock, it is necessary to add the main clock oscillation stabilization wait
time or the Main PLL clock stabilization wait time.
The internal resource reset means the watchdog reset and the CSV reset.
Document Number: 002-05646 Rev. *E
Page 134 of 149
CY9A150RB Series
13.Ordering Information
On-chip
SRAM
On-chip Flash
memory
Part number
Package
Packing
Main: 256 Kbyte
Work: 32 Kbyte
CY9AF154MBPMC-G-JNE2
CY9AF155MBPMC-G-JNE2
CY9AF156MBPMC-G-JNE2
CY9AF154MBBGL-GK9E1
CY9AF155MBBGL-GK9E1
CY9AF156MBBGL-GK9E1
CY9AF154NBPMC-G-JNE2
CY9AF155NBPMC-G-JNE2
CY9AF156NBPMC-G-JNE2
CY9AF154NBBGL-GK9E1
CY9AF155NBBGL-GK9E1
CY9AF156NBBGL-GK9E1
CY9AF154RBPMC-G-JNE2
CY9AF155RBPMC-G-JNE2
CY9AF156RBPMC-G-JNE2
32 Kbyte
48 Kbyte
64 Kbyte
32 Kbyte
48 Kbyte
64 Kbyte
32 Kbyte
48 Kbyte
64 Kbyte
32 Kbyte
48 Kbyte
64 Kbyte
32 Kbyte
48 Kbyte
64 Kbyte
Plastic LQFP 80-pin
Main: 384 Kbyte
Work: 32 Kbyte
(0.5 mm pitch),
(LQH080)
Main: 512 Kbyte
Work: 32 Kbyte
Main: 256 Kbyte
Work: 32 Kbyte
Plastic PFBGA 96-pin
Main: 384 Kbyte
Work: 32 Kbyte
(0.5 mm pitch),
(FDG096)
Main: 512 Kbyte
Work: 32 Kbyte
Main: 256 Kbyte
Work: 32 Kbyte
Plastic LQFP 100-pin
Main: 384 Kbyte
Work: 32 Kbyte
Tray
(0.5 mm pitch),
(LQI100)
Main: 512 Kbyte
Work: 32 Kbyte
Main: 256 Kbyte
Work: 32 Kbyte
Plastic PFBGA 112-pin
Main: 384 Kbyte
Work: 32 Kbyte
(0.8 mm pitch),
(LBC112)
Main: 512 Kbyte
Work: 32 Kbyte
Main: 256 Kbyte
Work: 32 Kbyte
Plastic LQFP 120-pin
Main: 384 Kbyte
Work: 32 Kbyte
(0.5 mm pitch),
(LQM120)
Main: 512 Kbyte
Work: 32 Kbyte
Document Number: 002-05646 Rev. *E
Page 135 of 149
CY9A150RB Series
14.Package Dimensions
Package Type
Package Code
LQFP 120
LQM120
4
D
5
7
D1
90
61
61
90
91
91
60
60
E1
E
4
5
7
3
6
31
31
120
1
30
30
1
5
2 7
A-B D
e
0.10
C
3
BOTTOM VIEW
0.20
C A-B D
0.08
C
A-B
D
b
8
TOP VIEW
2
A
c
9
θ
A
SEATING
PLANE
A1
b
SECTION A-A'
0.25
A'
10
0.08
C
L
SIDE VIEW
DIMENSIONS
SYMBOL
MIN. NOM. MAX.
1.70
A
A1
b
0.05
0.17 0.22 0.27
0.115 0.195
18.00 BSC
0.15
c
D
D1
e
16.00 BSC
0.50 BSC
E
18.00 BSC
16.00 BSC
E1
L
0.45 0.60 0.75
0° 8°
θ
002-16172 **
PACKAGE OUTLINE, 120 LEAD LQFP
18.0X18.0X1.7 MM LQM120 REV**
Document Number: 002-05646 Rev. *E
Page 136 of 149
CY9A150RB Series
Package Type
Package Code
LQFP 100
LQI100
4
4
D
D
5
7
5
7
D1
D1
75
51
51
75
76
50
50
76
E1
E1
E
E
5
5
4
4
7
7
3
6
100
26
26
100
1
1
25
25
2
5
7
e
0.10
C A-B D
3
BOTTOM VIEW
0.20
C A-B D
b
8
0.08
C
A-B
D
TOPVIEW
2
A
9
A
SEATING
PLANE
c
A1
A'
0.25
b
L1
0.08
C
10
SECTION A-A'
L
SIDE VIEW
DETAIL A
NOTES:
1. ALL DIMENSIONSAREIN MILLIMETERS.
DIMENSIONS
SYMBOL
MIN. NOM. MAX.
1.70
2. DATUM PLANEH ISLOCATED ATTHEBOTTOM OF THE MOLD PARTING
LINECOINCIDENTWITH WHERETHELEAD EXITSTHEBODY.
3. DATUMSA-BAND D TO BEDETERMINED ATDATUM PLANEH.
A
A1
b
0.05
0.15
0.09
0.15
0.27
0.20
4. TO BEDETERMINED ATSEATING PLANEC.
5. DIMENSIONSD1 AND E1 DO NOTINCLUDEMOLD PROTRUSION.
ALLOW ABLEPROTRUSION IS0.25mm PRESIDE.
c
D
16.00 BSC
14.00 BSC
0.50 BSC
DIMENSIONSD1 AND E1 INCLUDEMOLD MISMATCH AND AREDETERMINED
ATDATUM PLANE H.
D1
e
6. DETAILSOF PIN 1 IDENTIFIERAREOPTIONALBUTMUSTBE LOCATED
WITHIN THEZONEINDICATED.
E
16.00 BSC
14.00 BSC
7. REGARDLESSOFTHERELATIVESIZEOF THEUPPERAND LOWERBODY
SECTIONS. DIMENSIONSD1 AND E1 AREDETERMINED ATTHELARGEST
FEATUREOF THEBODY EXCLUSIVEOF MOLD FLASH AND GATE BURRS.
BUTINCLUDING ANY MISMATCH BETWEEN THEUPPERAND LOWER
SECTIONSOF THEMOLDERBODY.
E1
L
0.45
0.60 0.75
L1
0.30 0.50 0.70
8. DIMENSION b DOESNOTINCLUDE DAMBARPROTRUSION. THEDAMBAR
PROTRUSION (S) SHALL NOTCAUSETHELEAD WIDTH TO EXCEED b
MAXIMUM BY MORETHAN 0.08mm. DAMBARCANNOTBELOCATED ON
THELOWERRADIUSORTHELEAD FOOT.
9. THESEDIMENSIONSAPPLY TO THEFLATSECTION OF THE LEAD
BETWEEN 0.10mm AND 0.25mm FROM THELEAD TIP.
10. A1 ISDEFINED ASTHEDISTANCEFROM THESEATING PLANE TO
THELOWESTPOINTOF THEPACKAGEBODY.
002-11500 *A
PACKAGE OUTLINE, 100 LEAD LQFP
14.0X14.0X1.7 MM LQI100 REV*A
Document Number: 002-05646 Rev. *E
Page 137 of 149
CY9A150RB Series
Package Type
Package Code
LQFP 80
LQH080
4
D
5
7
D1
60
41
41
60
61
40
40
61
5
7
E1
E
4
3
6
80
21
21
80
1
20
20
1
2
5
8
7
D
0.10
C
C
A-B D
BOTTOM VIEW
3
e
0.08
A-B
D
b
0.20
C A-B D
TOP VIEW
2
A
A
SEATING
PLANE
9
c
A'
L1
0.25
0.08
C
A1
b
L
10
SIDE VIEW
SECTION A-A'
DIMENSIONS
SYMBOL
MIN. NOM. MAX.
1.70
A
A1
b
0.05
0.15
0.09
0.15
0.27
0.20
c
D
14.00 BSC.
D1
e
12.00 BSC.
0.50 BSC
E
14.00 BSC.
12.00 BSC.
E1
L
0.45 0.60 0.75
0.30 0.50 0.70
L1
002-11501 **
PACKAGE OUTLINE, 80 LEAD LQFP
12.0X12.0X1.7 MM LQH080 Rev **
Document Number: 002-05646 Rev. *E
Page 138 of 149
CY9A150RB Series
Package Type
Package Code
BGA 112
LBC112
A
0.20
2X
C
11
10
9
6
8
7
6
5
4
3
2
1
L
K
J
H
G
F
E
D
C
B
A
INDEX MARK
PIN A1
6
B
CORNER
7
0.20
C
2X
TOP VIEW
BOTTOM VIEW
DETAILA
5
C
112xφb
0.10
C
SIDE VIEW
0.08
C A B
DETAIL A
NOTES:
1. ALLDIMENSIONSAREIN MILLIMETERS.
2. SOLDER BALL POSITION DESIGNATIO
DIMENSIONS
NOM.
SYMBOL
N PERJEP95, SECTION 3, SPP-020.
MIN.
-
MAX.
1.45
0.45
3. "e"REPRESENTSTHESOLDERBALL GRID PITCH.
A
A1
D
-
0.35
4. SYMBOL "MD"ISTHEBALL MATRIX SIZEIN THE"D"DIRECTION.
SYMBOL "ME"ISTHEBALL MATRIX SIZEIN THE"E"DIRECTION.
N ISTHENUMBEROF POPULATED SOLDERBALL POSITIONSFORMATRIX
SIZEMD X ME.
0.25
10.00 BSC
E
10.00 BSC
8.00 BSC
8.00 BSC
11
D1
E1
MD
ME
N
5.
DIMENSION "b"ISMEASURED ATTHEMAXIMUM BALLDIAMETERIN A
PLANEPARALLELTO DATUM C.
6.
"SD"AND "SE"AREMEASUREDWITH RESPECTTO DATUMSA AND BAND
DEFINETHEPOSITION OFTHECENTERSOLDERBALL IN THEOUTERROW.
11
112
0.45
WHEN THEREISAN ODD NUMBEROFSOLDERBALLSIN THEOUTERROW,
"SD"OR"SE"= 0.
b
0.35
0.55
eD
eE
SD
SE
0.80 BSC
0.80 BSC
0.00
WHEN THEREISAN EVEN NUMBEROFSOLDERBALLSIN THEOUTERROW,
"SD"= eD/2 AND "SE"= eE/2.
A1 CORNERTO BEIDENTIFIED BY
CHAMFER, LASERORINK MARK
7.
0.00
METALIZED MARK, INDENTATION OROTHERMEANS.
8. "+"INDICATESTHETHEORETICALCENTEROFDEPOPULATED SOLDER
BALLS.
002-13225 **
PACKAGE OUTLINE, 112 BALL FBGA
10.00X10.00X1.45 MM LBC112 REV**
Document Number: 002-05646 Rev. *E
Page 139 of 149
CY9A150RB Series
Package Type
Package Code
BGA 96
FDG096
A
0.20
2X
C
11
10
9
6
8
7
6
5
4
3
2
1
L
K
J
H
G
F
E
D
C
B
A
INDEX MARK
7
PIN A1
CORNER
6
B
0.20
2X
C
TOP VIEW
BOTTOM VIEW
DETAIL A
0.20
C
C
5
0.08
C
96xφb
SIDE VIEW
DETAIL A
0.05
C
A B
NOTES:
1. ALLDIMENSIONSAREIN MILLIMETERS.
2. SOLDERBALL POSITION DESIGNATIO
DIMENSIONS
SYMBOL
N PERJEP95, SECTION 3, SPP-020.
MIN.
NOM.
MAX.
3. "e"REPRESENTSTHESOLDERBALL GRID PITCH.
A
A1
D
1.30
0.35
-
-
0.25
4. SYMBOL "MD"ISTHEBALL MATRIX SIZEIN THE"D"DIRECTION.
SYMBOL "ME"ISTHEBALL MATRIX SIZEIN THE"E"DIRECTION.
N ISTHENUMBEROF POPULATED SOLDERBALL POSITIONSFORMATRIX
SIZEMD X ME.
0.15
6.00 BSC
E
6.00 BSC
5.00 BSC
5.00 BSC
11
D1
E1
MD
ME
N
5.
DIMENSION "b"ISMEASURED ATTHEMAXIMUM BALLDIAMETERIN A
PLANEPARALLELTO DATUM C.
6.
"SD"AND "SE"AREMEASUREDWITH RESPECTTO DATUMSA AND BAND
DEFINETHEPOSITION OFTHECENTERSOLDERBALL IN THEOUTERROW.
11
96
WHEN THEREISAN ODD NUMBEROFSOLDERBALLSIN THEOUTERROW,
"SD"OR"SE"= 0.
0.30
b
0.20
0.40
eD
eE
SD
SE
0.50 BSC
WHEN THEREISAN EVEN NUMBEROFSOLDERBALLSIN THEOUTERROW,
"SD"= eD/2 AND "SE"= eE/2.
0.50 BSC
0.00
A1 CORNERTO BEIDENTIFIED BY
CHAMFER, LASERORINK MARK
7.
0.00
METALIZED MARK, INDENTATION OROTHERMEANS.
8. "+"INDICATESTHETHEORETICALCENTEROFDEPOPULATED SOLDER
BALLS.
002-13224 **
PACKAGE OUTLINE, 96 BALLFBGA
6.0X6.0X1.3 MM FDG096 REV**
Document Number: 002-05646 Rev. *E
Page 140 of 149
CY9A150RB Series
15.Errata
This chapter describes the errata for CY9B150R series. Details include errata trigger conditions, scope of impact, available
workaround, and silicon revision applicability.
Contact your local Cypress Sales Representative if you have questions.
15.1 Part Numbers Affected
Part Number
Initial Revision
CY9AF154RPMC-G-JNE2, CY9AF155RPMC-G-JNE2, CY9AF156RPMC-G-JNE2,
CY9AF154NPMC-G-JNE2, CY9AF155NPMC-G-JNE2, CY9AF156NPMC-G-JNE2,
CY9AF154NBGL-GE1, CY9AF155NBGL-GE1, CY9AF156NBGL-GE1,
CY9AF154NBGL-GK9E1, CY9AF155NBGL-GK9E1, CY9AF156NBGL-GK9E1,
CY9AF154MPMC-G-JNE2, CY9AF155MPMC-G-JNE2, CY9AF156MPMC-G-JNE2,
CY9AF154MBGL-GE1, CY9AF155MBGL-GE1, CY9AF156MBGL-GE1,
CY9AF154MBGL-GK9E1, CY9AF155MBGL-GK9E1, CY9AF156MBGL-GK9E1,
MB9AF154RPMC-G-JNE2, MB9AF155RPMC-G-JNE2, MB9AF156RPMC-G-JNE2,
MB9AF154NPMC-G-JNE2, MB9AF155NPMC-G-JNE2, MB9AF156NPMC-G-JNE2,
MB9AF154NBGL-GE1, MB9AF155NBGL-GE1, MB9AF156NBGL-GE1,
MB9AF154MPMC-G-JNE2, MB9AF155MPMC-G-JNE2, MB9AF156MPMC-G-JNE2,
MB9AF154MBGL-GE1, MB9AF155MBGL-GE1, MB9AF156MBGL-GE1
Rev. A
CY9AF154RAPMC-G-JNE2, CY9AF155RAPMC-G-JNE2, CY9AF156RAPMC-G-JNE2,
CY9AF154NAPMC-G-JNE2, CY9AF155NAPMC-G-JNE2, CY9AF156NAPMC-G-JNE2,
CY9AF154NABGL-GE1, CY9AF155NABGL-GE1, CY9AF156NABGL-GE1,
CY9AF154NABGL-GK9E1, CY9AF155NABGL-GK9E1, CY9AF156NABGL-GK9E1,
CY9AF154MAPMC-G-JNE2, CY9AF155MAPMC-G-JNE2, CY9AF156MAPMC-G-JNE2,
CY9AF154MABGL-GE1, CY9AF155MABGL-GE1, CY9AF156MABGL-GE1,
CY9AF154MABGL-GK9E1, CY9AF155MABGL-GK9E1, CY9AF156MABGL-GK9E1,
MB9AF154RAPMC-G-JNE2, MB9AF155RAPMC-G-JNE2, MB9AF156RAPMC-G-JNE2,
MB9AF154NAPMC-G-JNE2, MB9AF155NAPMC-G-JNE2, MB9AF156NAPMC-G-JNE2,
MB9AF154NABGL-GE1, MB9AF155NABGL-GE1, MB9AF156NABGL-GE1,
MB9AF154MAPMC-G-JNE2, MB9AF155MAPMC-G-JNE2, MB9AF156MAPMC-G-JNE2,
MB9AF154MABGL-GE1, MB9AF155MABGL-GE1, MB9AF156MABGL-GE1
15.2 Qualification Status
Product Status: In Production − Qual.
15.3 Errata Summary
This table defines the errata applicability to available devices.
Items
Part Number
Refer to 15.1
Refer to 15.1
Silicon Revision
Initial rev.
Fix Status
[1] HDMI-CEC arbitration lost issue
[2] HDMI-CEC polling message issue
Fixed in Rev. A
Fixed in Rev. B
Initial rev., Rev. A
Document Number: 002-05646 Rev. *E
Page 141 of 149
CY9A150RB Series
1. HDMI-CEC arbitration lost issue
◼PROBLEM DEFINITION
Large external load on CEC bus may cause arbitration lost.
◼PARAMETERS AFFECTED
N/A
◼TRIGGER CONDITION(S)
The arbitration lost detection mechanism samples outputting signals and determines that arbitration lost occurs if sampled signals
do not match the outputting signals. The large external load on the CEC bus increases slew rate of the signals. The increased slew
rate makes the mismatch between outputting signals and sampled signals and the mismatch misleads MCU that arbitration lost
occurs.
◼SCOPE OF IMPACT
Once the arbitration lost is detected, the CEC aborts the transmission. Any transmission cannot be completed.
◼WORKAROUND
This error cannot be avoided by any software. Reduce the external load.
◼FIX STATUS
This issue was fixed in Rev. A.
2. HDMI-CEC polling message issue
◼PROBLEM DEFINITION
Error#1) While MCU sends a Polling Message, it always returns a NACK to a message coming to the MCU from another node.
Error#2) MCU always waits for 7-bit signal free on CEC line before it drives the line even when the last line initiator was another
node.
◼PARAMETERS AFFECTED
N/A
◼TRIGGER CONDITION(S)
This error always happens.
◼SCOPE OF IMPACT
MCU does not reply properly to another node.
◼WORKAROUND
The software workaround is applied to Error #1.
1. Store 0x0 to SFREE register.
2. Monitor CEC line with GPIO and wait until High on the CEC line lasts for the signal free time.
3. Store frame data to TXDATA register and store 0x0F to RCADR1 or RCADR2 register.
It sends a message after 3~4 clocks of 32.768 kHz clock when TXDATA is stored.
If the device receives a frame from another node within 2~3 clocks after storing TXDATA, the bus error occurs and if the device
receives a frame from another node within 3~4 clocks after storing TXDATA, the arbitration lost occurs. In these cases:
4-A-1. Set RCADR1 or RCADR2 to former value from 0x0F to reply ACK
4-A-2. Return back to step 2 above
If the device receives a frame from another node within 1~2 clocks after storing TXDATA, take these steps.
4-B-1. Monitor CEC line with GPIO after 50us from storing TXDATA
4-B-2. Set TXEN to 1 -> 0 -> 1 immediately when GPIO finds Low on the CEC line
4-B-3. Set RCADR1 or RCADR2 to former value from 0x0F to reply ACK
Document Number: 002-05646 Rev. *E
Page 142 of 149
CY9A150RB Series
4-B-4. Return back to step 2 above
For Error #2, there is no software workaround, but signal free time of fixed 7-bit does not violate HDMI-CEC specification. The
specification says signal free time must be more than and equals to 5-bit.
◼FIX STATUS
◼This issue was fixed in Rev. B.
Document Number: 002-05646 Rev. *E
Page 143 of 149
CY9A150RB Series
16.Major Changes
Spansion Publication Number: MB9A150RB_DS706-00047
Page
Section
Change Results
Revision 0.1
-
-
Initial release
Revision 1.0
-
-
Preliminary → Data Sheet
Features
Corrected the description of "Flash memory".
1
On-chip Memories
1. Product Lineup
1.2. Function
Corrected the value of channel number of the "Base Timer".
7
7.Handling Devices
◼Added the description of "Crystal oscillator circuit".
71
◼Added the description of "Sub crystal oscillator".
8.Block Diagram
Corrected the figure.
74
◼TIOA: input → input/output
◼TIOB: output → input
10.Memory Map
Corrected the value of address of "SRAM0".
75
75
10.1 Memory Map (1)
10.2 Memory Map (2)
11. Pin Status In Each CPU State
11.1 List of Pin Status
Added the footnote.
◼Corrected the Return from Deep standby mode state of
78, 79
"Pin status type H".
◼Corrected the function group of "Pin status type I".
◼Revised the value of "TBD".
◼Revised the typical value of "Power supply voltage
(ICCH, ICCT, ICCR)".
◼Added the "Flash Memory Write/Erase current (ICCFLASH)".
◼Added the footnote.
13. Electrical Characteristics
13.3. DC Characteristics
13.3.1 Current Rating
77, 78
13.4. AC Characteristics
◼Added the description of Note of "Input frequency (FCL)".
◼Added the footnote.
13.4.2 Sub Clock Input Characteristics
13.4.3 Built-in CR Oscillation
Characteristics
◼Revised the condition.
94, 95,
◼Corrected the value.
13.4.3.1 Built-in high-speed CR
◼Added the item of "Frequency stabilization time".
◼Added the footnote.
13.4.7. External Bus Timing
13.4.7.1. Separate Bus Access
Asynchronous SRAM Mode
◼Corrected the value.
◼Deleted the "MWEX ↓ → Data output time".
◼Added the "MCSX ↓ → Data output time".
◼Corrected the figure.
99
13.4.7.2 Separate Bus Access
Synchronous SRAM Mode
◼Corrected the "MCLK↑ → Data output time".
◼Added the "MCLK↑ → Data hold time".
101
◼Corrected the figure.
13.4.9. CSIO Timming
Corrected the description of section title.
UART Timming → CSIO Timming
110,
112,
Corrected the description of "Note".
UART is connected → Multi-function Serial is connected
Added the footnote.
114, 116
122
125
13.4.12 I2C Timing
13.5. 12-bit A/D Converter
◼Revised the parameter.
◼Revised the symbol.
◼Corrected the value.
Document Number: 002-05646 Rev. *E
Page 144 of 149
CY9A150RB Series
Page
127
Section
Change Results
◼Revised the parameter.
◼Revised the symbol.
13.5.2 Definition of 12-bit A/D Converter
Terms
◼Corrected "Conditions" and "Value" in the table.
◼Added the Item.
13.6. Low-Voltage Detection
Characteristics
128, 129
13.6.1 Low-Voltage Detection Reset
13.6.2 Interrupt of Low-Voltage Detection
◼Added the footnote.
130
Added the Item.
Revision 1.1
-
-
Company name and layout design change
Revision 2.0
Corrected the Series name.
-
-
MB9A150R Series → MB9A150RA Series
Corrected the Product name as follows.
MB9AF156MA, MB9AF155MA, MB9AF154MA
MB9AF156NA, MB9AF155NA, MB9AF154NA
MB9AF156RA, MB9AF155RA, MB9AF154RA
-
-
Features
Added the Item.
1
External Bus Interface
Multi-function Serial Interface
Multi-function Timer
1.Product Lineup
1.2 Function
◼Maximum area size : Up to 256 Mbytes
Corrected the description of "I2C"
1
2
Corrected the channel count of "A/D activation compare"
7
Added the footnote
Delete the following packages.
◼FPT-100P-M36
9
2. Packages
◼FPT-80P-M40
3. Pin Assignment
3.2 FPT-100P-M36
11
12
Delete the Item
Corrected the description of section title.
3.3 FPT-80P-M37
FPT-80P-M37/M40 →FPT-80P-M37
4. List Of Pin Function
4.1 List of numbers
15 – 36
37 - 60
75
Delete column of terminal number "QFP-100"
Delete column of terminal number "QFP-100"
Corrected the address "External Device Area"
4.2 List of pin functions
10.Memory Map
10.1 Memory Map (1)
13.Electrical Characteristics
13.2.Recommended Operating
Conditions
88
89
Add the footnote
◼Corrected the Condition
◼Delete the minmun value
◼Corrected the remarks
◼Add the footnote
13.3.DC Characteristics
13.3.1 Current rating
13.9. CSIO Timing
116
117
13.9.4 Synchronous serial (SPI=1,
SCINV=1)
Corrected the figure of "MS bit=1"
13.9 CSIO Timing
13.4.9.5. External
Corrected the figure
clock(EXT=1):asyntironous only
Document Number: 002-05646 Rev. *E
Page 145 of 149
CY9A150RB Series
Page
Section
Change Results
Add the terminal as follows
◼FRCKx
◼ICxx
118
13.4.10. External Input Timing
◼DTTIxX
Corrected the description as follows.
◼Typical mode → Standard-mode
122
125
13.4.12. I2C Timing
◼High-speed mode → Fast-mode
◼Corrected the terminal name
AN00 to AN23 → ANxx
13.5.12-bit A/D Converter
13.5.1 Electrical Characteristics for
the A/D Converter
◼Corrected the minimum value of "Sampling time"
◼Corrected the max and min value of "State transition time to
operation permission"
◼Corrected the footnote
137
14. ORDERING INFORMATON
-
Corrected the "Part number"
Revision 3.0
Corrected the Series name.
-
-
MB9A150RA Series → MB9A150RB Series
Corrected the Product name as follows.
MB9AF156MB, MB9AF155MB, MB9AF154MB
MB9AF156NB, MB9AF155NB, MB9AF154NB
MB9AF156RB, MB9AF155RB, MB9AF154RB
-
10.Memory Map
76
89
Added the summary of Flash memory sector
10.2. Memory map(2)
◼Changed the table format
13. Electrical Characteristics
13.3. DC Characteristics
◼Added Main TIMER mode current
◼Moved A/D Converter Current
13.3.1 Current rating
13. Electrical Characteristics
13.4. AC Characteristics
96
◼Added the figure of Main PLL connection
13.4.1 Operating Conditions of Main PLL
13.4.2 Operating Conditions of Main PLL
13. Electrical Characteristics
13. 4. AC Characteristics
13.4.6. Power-on Reset Timing
13.Electrical Characteristics
13.4. AC Characteristics
◼Added Time until releasing Power-on reset
◼Changed the figure of timing
97
◼Modified from UART Timing to CSIO/UART Timing
110 - 117
◼Changed from Internal shift clock operation to Master mode
13.4.9 CSIO/UART Timing
◼Changed from External shift clock operation to Slave mode
◼Added the typical value of Integral Nonlinearity, Differential
Nonlinearity, Zero transition voltage and Full-scale transition
voltage
13. Electrical Characteristics
13.5. 12bit A/D Converter
125
◼Added the value of conversion time at AVCC < 2.7 V
13. Electrical Characteristics
13.8. Return Time from Low-Power
Consumption Mode
132 - 134
Added Return Time from Low-Power Consumption Mode
137
14. Ordering Information
15. Package Dimensions
Changed notation of part number
137 - 141
Deleted FPT-100P-M36 and FPT-80P-M40
NOTE: Please see “Document History” about later revised information.
Document Number: 002-05646 Rev. *E
Page 146 of 149
CY9A150RB Series
Document History
Document Title: CY9A150RB Series 32-bit Arm® Cortex®-M3 FM3 Microcontroller
Document Number: 002-05646
Orig. of Submission
Revision
ECN
Description of Change
Change
Date
−
**
AKIH
04/28/2015 Migrated to Cypress and assigned document number 002-05646.
No change to document contents.
5226742
5535819
*A
*B
AKIH
04/27/2016 Updated to Cypress template.
YSKA
02/09/2017 Updated “12.4.6 Power-On Reset Timing”. Changed parameter from
“Power Supply rise time(Tr)[ms]” to “Power ramp
rate(dV/dt)[mV/us]” and added some comments (Page 96)
Modified RTC description in “Features, Real-Time Clock(RTC)” as
below
Changed starting count value from 01 to 00. Deleted “second , or
day of the week” in the Interrupt function (Page 3)
Added Notes for JTAG (Page 59), Changed “J-TAG” to” JTAG” in
“4.2 List of Pin Functions” (Page 40)
Updated Package code and dimensions as follows (Page 8-13, 135-
140)
FPT-80P-M37 -> LQH080, BGA-96P-M07 -> FDG096,
FPT-100P-M23 -> LQI100, BGA-112P-M04 -> LBC112,
FPT-120P-M37 -> LQM120
Added “15.Errta (Page 141)”
Deleted the note below from the footer of the first page.
"CONFIDENTIAL - RELEASED ONLY UNDER NONDISCLOSURE
AGREEMENT (NDA)" (Page 1)
Added the Baud rate spec in “12.4.9 CSIO/UART Timing”(Page
109, 111, 113, 115)
5774754
6575922
*C
*D
YSAT
HUAL
06/19/2017 Updated Cypress Logo and Copyright.
05/17/2019 Updated Document Title to read as “CY9A150RB Series 32-bit Arm®
Cortex®-M3 FM3 Microcontroller”.
Replaced “MB9A150RB Series” with “CY9A150RB Series” in all
instances across the document.
Updated Ordering Information:
Updated part numbers.
Updated to new template.
7153046
*E
XITO
06/15/2021 Updated the part numbers in Ordering Information as follows:
CY9AF154MBBGL-GE1 to CY9AF154MBBGL-GK9E1
CY9AF155MBBGL-GE1 to CY9AF155MBBGL-GK9E1
CY9AF156MBBGL-GE1 to CY9AF156MBBGL-GK9E1
Document Number: 002-05646 Rev. *E
Page 147 of 149
CY9A150RB Series
Orig. of Submission
Change Date
Revision
ECN
Description of Change
CY9AF154NBBGL-GE1 to CY9AF154NBBGL-GK9E1
CY9AF155NBBGL-GE1 to CY9AF155NBBGL-GK9E1
CY9AF156NBBGL-GE1 to CY9AF156NBBGL-GK9E1
Updated Errata:
Updated Part Numbers Affected:
Updated part numbers in the table.
Corrected some typos.
Completing Sunset Review.
Document Number: 002-05646 Rev. *E
Page 148 of 149
CY9A150RB Series
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the
office closest to you, visit us at Cypress Locations.
Products
PSoC® Solutions
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP | PSoC 6 MCU
Arm® Cortex® Microcontrollers
cypress.com/arm
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cypress.com/interface
cypress.com/iot
Automotive
Cypress Developer Community
Community | Code Examples | Projects | Videos | Blogs |
Training | Components
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Interface
Technical Support
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cypress.com/psoc
cypress.com/pmic
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cypress.com/usb
Power Management ICs
Touch Sensing
USB Controllers
Wireless/RF
cypress.com/wireless
All other trademarks or registered trademarks referenced herein are the property of their respective owners.
© Cypress Semiconductor Corporation, 2012-2021. This document is the property of Cypress Semiconductor Corporation and its subsidiaries (“Cypress”). This document, including any software or
firmware included or referenced in this document (“Software”), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries worldwide. Cypress
reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other intellectual property
rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress hereby grants
you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to modify and
reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users (either
directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress’s patents that are infringed by the Software (as
provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or
compilation of the Software is prohibited.
TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. No computing
device can be absolutely secure. Therefore, despite security measures implemented in Cypress hardware or software products, Cypress shall have no liability arising out of any security breach,
such as unauthorized access to or use of a Cypress product. CYPRESS DOES NOT REPRESENT, WARRANT, OR GUARANTEE THAT CYPRESS PRODUCTS, OR SYSTEMS CREATED USING
CYPRESS PRODUCTS, WILL BE FREE FROM CORRUPTION, ATTACK, VIRUSES, INTERFERENCE, HACKING, DATA LOSS OR THEFT, OR OTHER SECURITY INTRUSION (collectively,
“Security Breach”). Cypress disclaims any liability relating to any Security Breach, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from any Security
Breach. In addition, the products described in these materials may contain design defects or errors known as errata which may cause the product to deviate from published specifications. To the
extent permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of
any product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes.
It is the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. “High-Risk
Device” means any device or system whose failure could cause personal injury, death, or property damage. Examples of High-Risk Devices are weapons, nuclear installations, surgical implants,
and other medical devices. “Critical Component” means any component of a High-Risk Device whose failure to perform can be reasonably expected to cause, directly or indirectly, the failure of the
High-Risk Device, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from
any use of a Cypress product as a Critical Component in a High-Risk Device. You shall indemnify and hold Cypress, its directors, officers, employees, agents, affiliates, distributors, and assigns
harmless from and against all claims, costs, damages, and expenses, arising out of any claim, including claims for product liability, personal injury or death, or property damage arising from any use
of a Cypress product as a Critical Component in a High-Risk Device. Cypress products are not intended or authorized for use as a Critical Component in any High-Risk Device except to the limited
extent that (i) Cypress’s published data sheet for the product explicitly states Cypress has qualified the product for use in a specific High-Risk Device, or (ii) Cypress has given you advance written
authorization to use the product as a Critical Component in the specific High-Risk Device and you have signed a separate indemnification agreement.
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in
the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Document Number: 002-05646 Rev. *E
June 15, 2021
Page 149 of 149
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