CY9AF1A2MPMC-G-UNE2 [INFINEON]
FM3 CY9AFxAxL/M/N-Series Ultra Low Leakage Arm® Cortex®-M3 Microcontroller (MCU) Family;
| 型号： | CY9AF1A2MPMC-G-UNE2 |
| 厂家： | 
Infineon |
| 描述： | FM3 CY9AFxAxL/M/N-Series Ultra Low Leakage Arm® Cortex®-M3 Microcontroller (MCU) Family 微控制器 |
| 文件： | 总100页 (文件大小：2338K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Please note that Cypress is an Infineon Technologies Company.
The document following this cover page is marked as “Cypress” document as this is the
company that originally developed the product. Please note that Infineon will continue
to offer the product to new and existing customers as part of the Infineon product
portfolio.
Continuity of document content
The fact that Infineon offers the following product as part of the Infineon product
portfolio does not lead to any changes to this document. Future revisions will occur
when appropriate, and any changes will be set out on the document history page.
Continuity of ordering part numbers
Infineon continues to support existing part numbers. Please continue to use the
ordering part numbers listed in the datasheet for ordering.
www.infineon.com
CY9A1A0N Series
32-bit Arm® Cortex®-M3
FM3 Microcontroller
The CY9A1A0N Series are highly integrated 32-bit microcontrollers that dedicated for embedded controllers with low-power
consumption mode and competitive cost.
The CY9A1A0N Series are based on the Arm® Cortex® -M3 Processor with on-chip Flash memory and SRAM, and have peripheral
functions such as Motor Control Timers, ADCs, DACs and Communication Interfaces (UART, CSIO, I2C).
The products which are described in this data sheet are placed into TYPE7 product categories in FM3 Family Peripheral Manual.
Features
32-bit Arm® Cortex®-M3 Core
Processor version: r2p1
[CSIO]
Full duplex double buffer
Up to 20 MHz Operation Frequency
Built-in dedicated baud rate generator
Overrun error detection function available
Integrated Nested Vectored Interrupt Controller (NVIC): 1
channel NMI (non-maskable interrupt) and
32 channels' peripheral interrupts and 8 priority levels
[I2C]
Standard-mode (Max 100 kbps) / Fast-mode (Max 400 kbps)
supported
24-bit System timer (Sys Tick): System timer for OS task
management
A/D Converter (Max 16 channels)
On-chip Memories
[12-bit A/D Converter]
[Flash memory]
Successive Approximation type
Conversion time: Min 1.0 μs
Up to 128 Kbytes
Read cycle: 0 wait-cycle
Security function for code protection
Priority conversion available (priority at 2levels)
Scanning conversion mode
[SRAM]
Built-in FIFO for conversion data storage (for SCAN
conversion: 16steps, for Priority conversion: 4steps)
This series contains a total of up to 16 Kbyte on-chip SRAM
that is connected to System bus of Cortex-M3 core.
SRAM1: Up to 16 Kbytes
D/A Converter (Max 2 channels)
R-2R type
Multi-function Serial Interface (Max 8 channels)
Operation mode is selectable from the followings for each
channel.
10-bit resolution
Base Timer (Max 8 channels)
Operation mode is selectable from the followings for each
channel.
UART
CSIO
I2C
16-bit PWM timer
16-bit PPG timer
[UART]
16-/32-bit reload timer
16-/32-bit PWC timer
Full duplex double buffer
Selection with or without parity supported
Built-in dedicated baud rate generator
External clock available as a serial clock
Various error detection functions available (parity errors,
framing errors, and overrun errors)
Cypress Semiconductor Corporation
Document Number: 002-05675 Rev. *E
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised May 17, 2019
CY9A1A0N Series
General-Purpose I/O Port
HDMI-CEC transmitter
This series can use its pins as general-purpose I/O ports when
they are not used for peripherals. Moreover, the port relocate
function is built in. It can set which I/O port the peripheral
function can be allocated to.
Header block automatic transmission by judging Signal free
Generating status interrupt by detecting Arbitration lost
Generating START, EOM, ACK automatically to output CEC
transmission by setting 1 byte data
Capable of pull-up control per pin
Capable of reading pin level directly
Built-in the port relocate function
Generating transmission status interrupt when transmitting 1
block (1 byte data and EOM/ACK)
Up to 84 high-speed general-purpose I/O Ports@100 pin
Real-time clock (RTC)
Package
The Real-time clock can count
Year/Month/Day/Hour/Minute/Second/A day of the week from
00 to 99.
Some ports are 5 V tolerant I/O
See List of Pin Functions and I/O Circuit Type to confirm the
corresponding pins.
The interrupt function with specifying date and time
(Year/Month/Day/Hour/Minute) is available. This function is
also available by specifying only Year, Month, Day, Hour or
Minute.
Multi-function Timer
The Multi-function timer is composed of the following blocks.
Timer interrupt function after set time or each set time.
Capable of rewriting the time with continuing the time count.
Leap year automatic count is available.
16-bit free-run timer × 3ch.
Input capture × 4ch.
Output compare × 6ch.
A/D activation compare × 1ch.
Waveform generator × 3ch.
External Interrupt Controller Unit
Up to 16 external interrupt input pins
16-bit PPG timer × 3ch.
IGBT mode is contained
Include one non-maskable interrupt (NMI) input pin
Watchdog Timer (2 channels)
A watchdog timer can generate interrupts or a reset when a
time-out value is reached.
The following function can be used to achieve the motor
control.
PWM signal output function
This series consists of two different watchdogs, a Hardware
watchdog and a Software watchdog.
DC chopper waveform output function
Dead time function
The Hardware watchdog timer is clocked by the built-in
Low-speed CR oscillator. Therefore, the Hardware watchdog is
active in any low-power consumption mode except RTC, Stop,
Deep Standby RTC and Deep Standby Stop modes.
Input capture function
A/D convertor activate function
DTIF (Motor emergency stop) interrupt function
Clock and Reset
HDMI-CEC/Remote Control Receiver (Up to 2
channels)
[Clocks]
Selectable from five clock sources (2 external oscillators, 2
built-in CR oscillators, and Main PLL).
HDMI- CEC receiver / Remote control receiver
Main Clock:
Sub Clock:
4 MHz to 20 MHz
32.768 kHz
Operating modes supporting the following standards can be
selected
Built-in High-speed CR Clock: 4 MHz
Built-in Low-speed CR Clock: 100 kHz
Main PLL Clock
SIRCS
NEC/Association for Electric Home Appliances
HDMI-CEC
Capable of adjusting detection timings for start bit and data
bit
Equipped with noise filter
Document Number: 002-05675 Rev. *E
Page 2 of 99
CY9A1A0N Series
[Resets]
Low-Power Consumption Mode
Six low-power consumption modes supported.
Reset requests from INITX pin
Power-on reset
Sleep
Timer
Software reset
RTC
Watchdog timers reset
Low-voltage detection reset
Clock Super Visor reset
Stop
Deep Standby RTC
Deep Standby Stop
The back up register is 16 bytes.
Clock Super Visor (CSV)
Clocks generated by built-in CR oscillators are used to
supervise abnormality of the external clocks.
Debug
Serial Wire JTAG Debug Port (SWJ-DP)
If external clock failure (clock stop) is detected, reset is
asserted.
Power Supply
Wide range voltage: VCC = 1.8 V to 5.5 V
If external frequency anomaly is detected, interrupt or reset is
asserted.
Low-Voltage Detector (LVD)
This Series includes 2-stage monitoring of voltage on the VCC.
When the voltage falls below the voltage that has been set,
Low-Voltage Detector generates an interrupt or reset.
LVD1: error reporting via interrupt
LVD2: auto-reset operation
Document Number: 002-05675 Rev. *E
Page 3 of 99
CY9A1A0N Series
Contents
1. Product Lineup.................................................................................................................................................................. 6
2. Packages ........................................................................................................................................................................... 7
3. Pin Assignment................................................................................................................................................................. 8
4. List of Pin Functions....................................................................................................................................................... 12
5. I/O Circuit Type ............................................................................................................................................................... 31
6. Handling Precautions ..................................................................................................................................................... 35
6.1
6.2
6.3
Precautions for Product Design................................................................................................................................... 35
Precautions for Package Mounting.............................................................................................................................. 36
Precautions for Use Environment................................................................................................................................ 37
7. Handling Devices ............................................................................................................................................................ 38
8. Block Diagram................................................................................................................................................................. 40
9. Memory Size.................................................................................................................................................................... 41
10. Memory Map.................................................................................................................................................................... 41
11. Pin Status in Each CPU State ........................................................................................................................................ 44
12. Electrical Characteristics ............................................................................................................................................... 52
12.1 Absolute Maximum Ratings......................................................................................................................................... 52
12.2 Recommended Operating Conditions ......................................................................................................................... 53
12.3 DC Characteristics ...................................................................................................................................................... 54
12.3.1 Current Rating.............................................................................................................................................................. 54
12.3.2 Pin Characteristics ....................................................................................................................................................... 57
12.4 AC Characteristics....................................................................................................................................................... 58
12.4.1 Main Clock Input Characteristics.................................................................................................................................. 58
12.4.2 Sub Clock Input Characteristics ................................................................................................................................... 59
12.4.3 Built-in CR Oscillation Characteristics.......................................................................................................................... 59
12.4.4 Operating Conditions of Main PLL (In the case of using main clock for input of PLL).................................................. 60
12.4.5 Operating Conditions of Main PLL (In the case of using the built-in High-speed CR for the input clock of the Main
PLL) ............................................................................................................................................................................. 60
12.4.6 Reset Input Characteristics.......................................................................................................................................... 61
12.4.7 Power-on Reset Timing................................................................................................................................................ 61
12.4.8 Base Timer Input Timing.............................................................................................................................................. 62
12.4.9 CSIO/UART Timing...................................................................................................................................................... 64
12.4.10 External Input Timing................................................................................................................................................ 72
12.4.11 I2C Timing................................................................................................................................................................. 73
12.4.12 JTAG Timing............................................................................................................................................................. 74
12.5 12-bit A/D Converter.................................................................................................................................................... 75
12.6 10-bit D/A Converter.................................................................................................................................................... 78
12.7 Low-Voltage Detection Characteristics........................................................................................................................ 79
12.7.1 Low-Voltage Detection Reset....................................................................................................................................... 79
12.7.2 Interrupt of Low-Voltage Detection............................................................................................................................... 80
12.8 Flash Memory Write/Erase Characteristics ................................................................................................................. 82
12.8.1 Write / Erase time......................................................................................................................................................... 82
12.8.2 Write cycles and data hold time ................................................................................................................................... 82
12.9 Return Time from Low-Power Consumption Mode...................................................................................................... 83
12.9.1 Return Factor: Interrupt/WKUP .................................................................................................................................... 83
12.9.2 Return Factor: Reset.................................................................................................................................................... 85
13. Ordering Information ...................................................................................................................................................... 87
14. Package Dimensions ...................................................................................................................................................... 88
Document Number: 002-05675 Rev. *E
Page 4 of 99
CY9A1A0N Series
15. Errata................................................................................................................................................................................ 94
15.1 Part Numbers Affected ................................................................................................................................................ 94
15.2 Qualification Status ..................................................................................................................................................... 94
15.3 Errata Summary .......................................................................................................................................................... 94
15.4 Errata Detail ................................................................................................................................................................ 94
15.4.1 HDMI-CEC polling message issue............................................................................................................................... 94
15.4.2 RTC delay issue........................................................................................................................................................... 95
Major Changes...................................................................................................................................................................... 96
Document History................................................................................................................................................................. 98
Sales, Solutions, and Legal Information............................................................................................................................. 99
Document Number: 002-05675 Rev. *E
Page 5 of 99
CY9A1A0N Series
1. Product Lineup
Memory size
Product name
CY9AF1A1L/M/N
64 Kbytes
CY9AF1A2L/M/N
128 Kbytes
On-chip Flash memory
On-chip SRAM
SRAM1
12 Kbytes
16 Kbytes
Function
CY9AF1A1L
CY9AF1A2L
CY9AF1A1M
CY9AF1A2M
CY9AF1A1N
CY9AF1A2N
Product name
Pin count
CPU
64
80
100
Cortex-M3
20 MHz
Freq.
Power supply voltage range
1.8 V to 5.5 V
Multi-function Serial Interface
8ch. (Max)
8ch. (Max)
(UART/CSIO/I2C)
Base Timer
(PWC/ Reload timer/PWM/PPG)
A/D activation
1ch.
compare
Input capture
4ch.
3ch.
Free-run timer
MF-
Timer
Output
compare
1 unit (Max)
2ch. (Max)
6ch.
3ch.
3ch.
Waveform
generator
PPG
(IGBT mode)
HDMI-CEC/ Remote Control
Receiver
Real-time clock (RTC)
Watchdog timer
1 unit
1ch. (SW) + 1ch. (HW)
11 pins (Max)+ NMI × 1
67 pins (Max)
12ch. (1 unit)
2ch. (Max)
External Interrupts
8 pins (Max)+ NMI × 1
52 pins (Max)
16 pins (Max)+ NMI × 1
84 pins (Max)
General-purpose I/O ports
12-bit A/D converter
10-bit D/A converter
CSV (Clock Super Visor)
LVD (Low-Voltage Detector)
9ch. (1 unit)
16ch. (1 unit)
Yes
2ch.
High-speed
Built-in CR
4 MHz
Low-speed
100 kHz
Debug Function
SWJ-DP
Note:
−
All signals of the peripheral function in each product cannot be allocated by limiting the pins of package.
It is necessary to use the port relocate function of the I/O port according to your function use.
See Electrical Characteristics 12.4 AC Characteristics 12.4.3 Built-in CR Oscillation Characteristics for accuracy of built-in CR.
Document Number: 002-05675 Rev. *E
Page 6 of 99
CY9A1A0N Series
2. Packages
Product name
CY9AF1A1L
CY9AF1A2L
CY9AF1A1M
CY9AF1A2M
CY9AF1A1N
CY9AF1A2N
Package
-
LQFP:
LQFP:
LQFP:
LQFP:
LQFP:
QFP:
LQD064 (0.5mm pitch)
LQG064 (0.65mm pitch)
-
-
-
-
-
LQH080 (0.5mm pitch)
LQJ080 (0.65mm pitch)
LQI100 (0.5mm pitch)
PQH100 (0.65mm pitch)
-
-
-
-
-
-
: Supported
Note:
−
See Package Dimensions for detailed information on each package.
Document Number: 002-05675 Rev. *E
Page 7 of 99
CY9A1A0N Series
3. Pin Assignment
LQD064/LQG064
(TOP VIEW)
VCC
P50 / SIN3_1 / INT00_0
P51 / SOT3_1 / INT01_0
P52 / SCK3_1 / INT02_0
P30 / TIOB0_1 / INT03_2
1
2
3
4
5
6
7
8
9
48 P21 / SIN0_0 / INT06_1 / WKUP2
47 P22 / SOT0_0 / TIOB7_1
46 P23 / SCK0_0 / TIOA7_1
45 P19 / AN09 / SCK2_2
44 P18 / AN08 / SOT2_2
43 AVSS
P31 / SCK6_1 / TIOB1_1 / INT04_2
P32 / SOT6_1 / TIOB2_1 / INT05_2
P33 / SIN6_1 / TIOB3_1 / INT04_0 / ADTG_6
P39 / DTTI0X_0 / ADTG_2
42 AVRH
41 AVCC
LQFP - 64
40 P17 / AN07 / SIN2_2 / INT04_1
39 P15 / AN05 / IC03_2
P3A / TIOA0_1 / RTO00_0 / RTCCO_2 / SUBOUT_2 10
P3B / TIOA1_1 / RTO01_0 11
P3C / TIOA2_1 / RTO02_0 12
P3D / TIOA3_1 / RTO03_0 13
P3E / TIOA4_1 / RTO04_0 14
P3F / TIOA5_1 / RTO05_0 15
VSS 16
38 P14 / AN04 / INT03_1 / IC02_2
37 P13 / AN03 / SCK1_1 / IC01_2 / RTCCO_1 / SUBOUT_1
36 P12 / AN02 / SOT1_1 / IC00_2
35 P11 / AN01 / SIN1_1 / INT02_1 / FRCK0_2 / WKUP1
34 P10 / AN00
33 VCC
Note:
−
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these
pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register
(EPFR) to select the pin.
Document Number: 002-05675 Rev. *E
Page 8 of 99
CY9A1A0N Series
LQH080/LQJ080
(TOP VIEW)
VCC
P50 / SIN3_1 / INT00_0
P51 / SOT3_1 / INT01_0
P52 / SCK3_1 / INT02_0
P53 / SIN6_0 / TIOA1_2 / INT07_2
P54 / SOT6_0 / TIOB1_2
P55 / SCK6_0 / ADTG_1
P56 / INT08_2
1
2
3
4
5
6
7
8
9
60 P20 / INT05_0 / CROUT_0
59 P21 / SIN0_0 / INT06_1 / WKUP2
58 P22 / SOT0_0 / TIOB7_1
57 P23 / SCK0_0 / TIOA7_1
56 P1B / AN11 / SOT4_1 / IC01_1
55 P1A / AN10 / SIN4_1 / INT05_1 / IC00_1
54 P19 / AN09 / SCK2_2
53 P18 / AN08 / SOT2_2
P30 / TIOB0_1 / INT03_2
52 AVSS
P31 / SCK6_1 / TIOB1_1 / INT04_2 10
P32 / SOT6_1 / TIOB2_1 / INT05_2 11
51 AVRH
LQFP - 80
50 AVCC
P33 / SIN6_1 / TIOB3_1 / INT04_0 / ADTG_6 12
P39 / DTTI0X_0 / ADTG_2 13
49 P17 / AN07 / SIN2_2 / INT04_1
48 P16 / AN06 / SCK0_1
P3A / TIOA0_1 / RTO00_0 / RTCCO_2 / SUBOUT_2 14
P3B / TIOA1_1 / RTO01_0 15
47 P15 / AN05 / SOT0_1 / IC03_2
46 P14 / AN04 / SIN0_1 / INT03_1 / IC02_2
45 P13 / AN03 / SCK1_1 / IC01_2 / RTCCO_1 / SUBOUT_1
44 P12 / AN02 / SOT1_1 / IC00_2
43 P11 / AN01 / SIN1_1 / INT02_1 / FRCK0_2 / WKUP1
42 P10 / AN00
P3C / TIOA2_1 / RTO02_0 16
P3D / TIOA3_1 / RTO03_0 17
P3E / TIOA4_1 / RTO04_0 18
P3F / TIOA5_1 / RTO05_0 19
VSS 20
41 VCC
Note:
−
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these
pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register
(EPFR) to select the pin.
Document Number: 002-05675 Rev. *E
Page 9 of 99
CY9A1A0N Series
LQI100
(TOP VIEW)
VCC
P50 / SIN3_1 / INT00_0
P51 / SOT3_1 / INT01_0
P52 / SCK3_1 / INT02_0
P53 / SIN6_0 / TIOA1_2 / INT07_2
P54 / SOT6_0 / TIOB1_2
P55 / SCK6_0 / ADTG_1
P56 / INT08_2
1
2
3
4
5
6
7
8
9
75 VSS
74 P20 / INT05_0 / CROUT_0
73 P21 / SIN0_0 / INT06_1 / WKUP2
72 P22 / SOT0_0 / TIOB7_1
71 P23 / SCK0_0 / TIOA7_1 / RTO00_1
70 P1F / AN15 / FRCK0_1 / ADTG_5
69 P1E / AN14 / RTS4_1 / DTTI0X_1
68 P1D / AN13 / CTS4_1 / IC03_1
67 P1C / AN12 / SCK4_1 / IC02_1
66 P1B / AN11 / SOT4_1 / IC01_1
65 P1A / AN10 / SIN4_1 / INT05_1 / IC00_1
64 P19 / AN09 / SCK2_2
P30 / TIOB0_1 / INT03_2
P31 / SCK6_1 / TIOB1_1 / INT04_2 10
P32 / SOT6_1 / TIOB2_1 / INT05_2 11
P33 / SIN6_1 / TIOB3_1 / INT04_0 / ADTG_6 12
P34 / TIOB4_1 / FRCK0_0 13
63 P18 / AN08 / SOT2_2
LQFP - 100
P35 / TIOB5_1 / INT08_1 / IC03_0 14
P36 / SIN5_2 / INT09_1 / IC02_0 15
P37 / SOT5_2 / INT10_1 / IC01_0 16
P38 / SCK5_2 / INT11_1 / IC00_0 17
P39 / DTTI0X_0 / ADTG_2 18
62 AVSS
61 AVRH
60 AVCC
59 P17 / AN07 / SIN2_2 / INT04_1
58 P16 / AN06 / SCK0_1
P3A / TIOA0_1 / RTO00_0 / RTCCO_2 / SUBOUT_2 19
P3B / TIOA1_1 / RTO01_0 20
57 P15 / AN05 / SOT0_1 / IC03_2
56 P14 / AN04 / SIN0_1 / INT03_1 / IC02_2
55 P13 / AN03 / SCK1_1 / IC01_2 / RTCCO_1 / SUBOUT_1
54 P12 / AN02 / SOT1_1 / IC00_2
53 P11 / AN01 / SIN1_1 / INT02_1 / FRCK0_2 / WKUP1
52 P10 / AN00
P3C / TIOA2_1 / RTO02_0 21
P3D / TIOA3_1 / RTO03_0 22
P3E / TIOA4_1 / RTO04_0 23
P3F / TIOA5_1 / RTO05_0 24
VSS 25
51 VCC
Note:
−
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these
pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register
(EPFR) to select the pin.
Document Number: 002-05675 Rev. *E
Page 10 of 99
CY9A1A0N Series
PQH100
(TOP VIEW)
P51 / SOT3_1 / INT01_0 81
P52 / SCK3_1 / INT02_0 82
50 P22 / SOT0_0 / TIOB7_1
49 P23 / SCK0_0 / TIOA7_1 / RTO00_1
48 P1F / AN15 / FRCK0_1 / ADTG_5
47 P1E / AN14 / RTS4_1 / DTTI0X_1
46 P1D / AN13 / CTS4_1 / IC03_1
45 P1C / AN12 / SCK4_1 / IC02_1
44 P1B / AN11 / SOT4_1 / IC01_1
43 P1A / AN10 / SIN4_1 / INT05_1 / IC00_1
42 P19 / AN09 / SCK2_2
P53 / SIN6_0 / TIOA1_2 / INT07_2 83
P54 / SOT6_0 / TIOB1_2 84
P55 / SCK6_0 / ADTG_1 85
P56 / INT08_2 86
P30 / TIOB0_1 / INT03_2 87
P31 / SCK6_1 / TIOB1_1 / INT04_2 88
P32 / SOT6_1 / TIOB2_1 / INT05_2 89
P33 / SIN6_1 / TIOB3_1 / INT04_0 / ADTG_6 90
P34 / TIOB4_1 / FRCK0_0 91
41 P18 / AN08 / SOT2_2
QFP - 100
40 AVSS
P35 / TIOB5_1 / INT08_1 / IC03_0 92
P36 / SIN5_2 / INT09_1 / IC02_0 93
P37 / SOT5_2 / INT10_1 / IC01_0 94
P38 / SCK5_2 / INT11_1 / IC00_0 95
P39 / DTTI0X_0 / ADTG_2 96
39 AVRH
38 AVCC
37 P17 / AN07 / SIN2_2 / INT04_1
36 P16 / AN06 / SCK0_1
35 P15 / AN05 / SOT0_1 / IC03_2
34 P14 / AN04 / SIN0_1 / INT03_1 / IC02_2
33 P13 / AN03 / SCK1_1 / IC01_2 / RTCCO_1 / SUBOUT_1
32 P12 / AN02 / SOT1_1 / IC00_2
31 P11 / AN01 / SIN1_1 / INT02_1 / FRCK0_2 / WKUP1
P3A / TIOA0_1 / RTO00_0 / RTCCO_2 / SUBOUT_2 97
P3B / TIOA1_1 / RTO01_0 98
P3C / TIOA2_1 / RTO02_0 99
P3D / TIOA3_1 / RTO03_0 100
Note:
−
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these
pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register
(EPFR) to select the pin.
Document Number: 002-05675 Rev. *E
Page 11 of 99
CY9A1A0N Series
4. List of Pin Functions
List of pin numbers
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins,
there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to
select the pin.
Pin No
LQFP-80 LQFP-100
I/O circuit
type
Pin state
type
Pin name
LQFP-64
QFP-100
79
1
1
1
VCC
-
P50
2
3
2
2
80
INT00_0
SIN3_1
P51
E
E
F
INT01_0
SOT3_1
(SDA3_1)
3
4
3
4
81
F
F
P52
INT02_0
4
82
83
E
E
SCK3_1
(SCL3_1)
P53
SIN6_0
TIOA1_2
INT07_2
P54
-
5
5
F
SOT6_0
(SDA6_0)
-
-
6
7
6
7
84
85
E
E
H
H
TIOB1_2
P55
SCK6_0
(SCL6_0)
ADTG_1
P56
-
8
9
8
9
86
87
E
E
O
F
INT08_2
P30
5
TIOB0_1
INT03_2
P31
TIOB1_1
6
7
10
11
10
11
88
89
E
E
F
F
SCK6_1
(SCL6_1)
INT04_2
P32
TIOB2_1
SOT6_1
(SDA6_1)
INT05_2
Document Number: 002-05675 Rev. *E
Page 12 of 99
CY9A1A0N Series
Pin No
LQFP-80 LQFP-100
I/O circuit
type
Pin state
type
Pin name
LQFP-64
QFP-100
P33
INT04_0
TIOB3_1
SIN6_1
ADTG_6
P34
8
12
12
90
E
F
-
-
-
-
13
14
91
92
FRCK0_0
TIOB4_1
P35
E
E
H
F
IC03_0
TIOB5_1
INT08_1
P36
IC02_0
SIN5_2
INT09_1
P37
-
-
-
-
15
16
93
94
E
E
F
F
IC01_0
SOT5_2
(SDA5_2)
INT10_1
P38
IC00_0
-
-
17
18
95
96
E
E
F
SCK5_2
(SCL5_2)
INT11_1
P39
9
13
DTTI0X_0
ADTG_2
P3A
H
RTO00_0
(PPG00_0)
10
14
19
97
E
H
TIOA0_1
RTCCO_2
SUBOUT_2
P3B
RTO01_0
(PPG00_0)
11
12
15
16
20
21
98
99
E
E
H
H
TIOA1_1
P3C
RTO02_0
(PPG02_0)
TIOA2_1
Document Number: 002-05675 Rev. *E
Page 13 of 99
CY9A1A0N Series
Pin No
LQFP-80 LQFP-100
I/O circuit
type
Pin state
type
Pin name
LQFP-64
QFP-100
P3D
RTO03_0
(PPG02_0)
13
17
18
19
22
23
24
100
E
E
E
H
TIOA3_1
P3E
RTO04_0
(PPG04_0)
14
15
1
2
H
H
TIOA4_1
P3F
RTO05_0
(PPG04_0)
TIOA5_1
VSS
16
20
25
26
3
4
-
-
-
-
VCC
P40
-
-
27
5
TIOA0_0
INT12_1
P41
E
F
-
-
-
-
-
-
28
29
30
6
7
8
TIOA1_0
INT13_1
P42
E
E
E
F
H
H
TIOA2_0
P43
TIOA3_0
ADTG_7
P44
-
-
21
22
31
32
9
E
E
H
H
TIOA4_0
P45
10
TIOA5_0
C
17
-
23
24
25
33
34
35
11
12
13
-
-
-
VSS
18
VCC
P46
19
26
36
14
D
M
X0A
P47
20
21
27
28
37
38
15
16
D
B
N
C
X1A
INITX
P48
-
29
39
17
INT14_1
SIN3_2
E
F
Document Number: 002-05675 Rev. *E
Page 14 of 99
CY9A1A0N Series
Pin No
LQFP-80 LQFP-100
I/O circuit
type
Pin state
type
Pin name
LQFP-64
22
QFP-100
P49
TIOB0_0
30
40
18
E
H
SOT3_2
-
(SDA3_2)
P4A
23
-
TIOB1_0
31
32
41
42
19
20
E
E
H
H
SCK3_2
(SCL3_2)
P4B
24
25
TIOB2_0
IGTRG
P4C
TIOB3_0
33
34
43
44
21
22
G
J
Q
T
SCK7_1
(SCL7_1)
CEC0
P4D
TIOB4_0
26
27
SOT7_1
(SDA7_1)
DA0
P4E
TIOB5_0
INT06_2
SIN7_1
DA1
35
45
23
J
S
PE0
28
29
30
36
37
38
46
47
48
24
25
26
C
H
A
P
D
A
MD1
MD0
PE2
X0
PE3
31
39
49
27
A
B
X1
32
33
40
41
50
51
28
29
VSS
-
-
VCC
P10
34
42
52
30
F
J
AN00
P11
AN01
SIN1_1
INT02_1
FRCK0_2
WKUP1
35
43
53
31
F
L
Document Number: 002-05675 Rev. *E
Page 15 of 99
CY9A1A0N Series
Pin No
LQFP-80 LQFP-100
I/O circuit
type
Pin state
type
Pin name
LQFP-64
QFP-100
P12
AN02
36
44
54
32
F
J
SOT1_1
(SDA1_1)
IC00_2
P13
AN03
SCK1_1
(SCL1_1)
37
38
45
55
33
F
J
IC01_2
RTCCO_1
SUBOUT_1
P14
AN04
46
47
56
57
34
35
IC02_2
INT03_1
SIN0_1
P15
F
F
K
J
-
39
AN05
IC03_2
SOT0_1
(SDA0_1)
-
-
P16
AN06
48
49
58
59
36
37
F
F
J
SCK0_1
(SCL0_1)
P17
AN07
SIN2_2
INT04_1
AVCC
AVRH
AVSS
P18
40
K
41
42
43
50
51
52
60
61
62
38
39
40
-
-
-
AN08
44
45
53
54
63
64
41
42
F
F
J
J
SOT2_2
(SDA2_2)
P19
AN09
SCK2_2
(SCL2_2)
Document Number: 002-05675 Rev. *E
Page 16 of 99
CY9A1A0N Series
Pin No
LQFP-80 LQFP-100
I/O circuit
type
Pin state
type
Pin name
LQFP-64
QFP-100
P1A
AN10
-
55
65
43
SIN4_1
INT05_1
IC00_1
P1B
F
K
AN11
-
-
56
66
67
44
45
F
F
J
J
SOT4_1
(SDA4_1)
IC01_1
P1C
AN12
-
SCK4_1
(SCL4_1)
IC02_1
P1D
AN13
-
-
-
-
-
-
68
69
70
46
47
48
F
F
F
J
J
J
CTS4_1
IC03_1
P1E
AN14
RTS4_1
DTTI0X_1
P1F
AN15
ADTG_5
FRCK0_1
P23
SCK0_0
(SCL0_0)
46
-
57
-
71
72
49
50
E
E
H
H
TIOA7_1
RTO00_1
P22
SOT0_0
(SDA0_0)
47
58
TIOB7_1
P21
SIN0_0
INT06_1
WKUP2
P20
48
59
60
73
74
51
52
E
E
G
F
-
INT05_0
CROUT_0
Document Number: 002-05675 Rev. *E
Page 17 of 99
CY9A1A0N Series
Pin No
LQFP-80 LQFP-100
I/O circuit
type
Pin state
type
Pin name
LQFP-64
QFP-100
53
-
-
-
-
75
76
VSS
-
-
54
VCC
P00
49
50
51
52
61
62
63
64
77
78
79
80
55
E
E
E
E
E
E
E
E
TRSTX
P01
56
57
58
TCK
SWCLK
P02
TDI
P03
TMS
SWDIO
P04
53
65
81
82
59
60
TDO
E
E
E
F
SWO
P05
TIOA5_2
SIN4_2
INT00_1
P06
-
-
TIOB5_2
-
-
-
83
84
61
62
E
E
F
SOT4_2
(SDA4_2)
INT01_1
P07
66
ADTG_0
H
SCK4_2
(SCL4_2)
-
P08
-
-
85
86
87
63
64
65
TIOA0_2
CTS4_2
P09
E
E
G
H
H
F
-
-
TIOB0_2
RTS4_2
P0A
54
67
SIN4_0
INT00_2
P0B
SOT4_0
(SDA4_0)
55
56
68
69
88
89
66
67
G
G
H
H
TIOB6_1
P0C
SCK4_0
(SCL4_0)
TIOA6_1
Document Number: 002-05675 Rev. *E
Page 18 of 99
CY9A1A0N Series
Pin No
LQFP-100
I/O circuit
type
Pin state
type
Pin name
LQFP-64
LQFP-80
QFP-100
P0D
-
-
70
90
91
68
69
RTS4_0
TIOA3_2
P0E
E
E
H
H
71
72
CTS4_0
TIOB3_2
P0F
NMIX
CROUT_1
RTCCO_0
SUBOUT_0
WKUP0
P63
57
92
70
E
I
-
73
74
93
94
71
72
E
E
O
H
INT03_0
P62
SCK5_0
(SCL5_0)
58
ADTG_3
P61
SOT5_0
(SDA5_0)
59
60
75
76
95
96
73
74
E
H
R
TIOB2_2
DTTI0X_2
P60
SIN5_0
TIOA2_2
INT15_1
WKUP3
CEC1
G
P80
61
62
77
78
97
98
75
76
G
G
H
H
SIN7_2
P81
SOT7_2
(SDA7_2)
P82
63
64
79
80
99
77
78
G
H
SCK7_2
(SCL7_2)
100
VSS
-
Document Number: 002-05675 Rev. *E
Page 19 of 99
CY9A1A0N Series
List of pin functions
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins,
there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to
select the pin.
Pin No
LQFP-80 LQFP-100
Pin
Pin name
Function description
function
LQFP-64
QFP-100
62
85
96
72
-
ADC
ADTG_0
ADTG_1
ADTG_2
ADTG_3
ADTG_4
ADTG_5
ADTG_6
ADTG_7
ADTG_8
AN00
-
66
7
84
7
-
9
13
74
-
18
94
-
58
-
A/D converter external trigger input pin
-
-
70
12
30
-
48
90
8
8
12
-
-
-
-
-
34
35
36
37
38
39
-
42
43
44
45
46
47
48
49
53
54
55
56
-
52
53
54
55
56
57
58
59
63
64
65
66
67
68
69
70
30
31
32
33
34
35
36
37
41
42
43
44
45
46
47
48
AN01
AN02
AN03
AN04
AN05
AN06
AN07
40
44
45
-
A/D converter analog input pin.
ANxx describes ADC ch.xx.
AN08
AN09
AN10
AN11
-
AN12
-
AN13
-
-
AN14
-
-
AN15
-
-
Document Number: 002-05675 Rev. *E
Page 20 of 99
CY9A1A0N Series
Pin No
Pin
Pin name
Function description
function
LQFP-64
LQFP-80
LQFP-100
27
QFP-100
Base Timer TIOA0_0
-
-
5
0
TIOA0_1
Base timer ch.0 TIOA pin
10
-
14
-
19
85
40
9
97
63
18
87
64
6
TIOA0_2
TIOB0_0
22
5
30
9
TIOB0_1
Base timer ch.0 TIOB pin
Base timer ch.1 TIOA pin
Base timer ch.1 TIOB pin
Base timer ch.2 TIOA pin
Base timer ch.2 TIOB pin
Base timer ch.3 TIOA pin
Base timer ch.3 TIOB pin
Base timer ch.4 TIOA pin
Base timer ch.4 TIOB pin
Base timer ch.5 TIOA pin
Base timer ch.5 TIOB pin
TIOB0_2
-
-
86
28
20
5
Base Timer TIOA1_0
1
-
-
TIOA1_1
11
-
15
5
98
83
19
88
84
7
TIOA1_2
TIOB1_0
23
6
31
10
6
41
10
6
TIOB1_1
TIOB1_2
-
Base Timer TIOA2_0
2
-
-
29
21
96
42
11
95
30
22
90
43
12
91
31
23
-
TIOA2_1
12
60
24
7
16
76
32
11
75
-
99
74
20
89
73
8
TIOA2_2
TIOB2_0
TIOB2_1
TIOB2_2
59
-
Base Timer TIOA3_0
3
TIOA3_1
13
-
17
70
33
12
71
21
18
-
100
68
21
90
69
9
TIOA3_2
TIOB3_0
25
8
TIOB3_1
TIOB3_2
-
Base Timer TIOA4_0
4
-
TIOA4_1
14
-
1
TIOA4_2
TIOB4_0
-
26
-
34
-
44
13
-
22
91
-
TIOB4_1
TIOB4_2
-
-
Base Timer TIOA5_0
5
-
22
19
-
32
24
82
45
14
83
10
2
TIOA5_1
15
-
TIOA5_2
TIOB5_0
TIOB5_1
TIOB5_2
60
23
92
61
27
-
35
-
-
-
Base Timer
TIOA6_1
Base timer ch.6 TIOA pin
Base timer ch.6 TIOB pin
56
55
69
68
89
88
67
66
6
TIOB6_1
Base Timer TIOA7_0
-
-
-
-
7
TIOA7_1
Base timer ch.7 TIOA pin
Base timer ch.7 TIOB pin
46
-
57
-
71
-
49
-
TIOA7_2
TIOB7_0
TIOB7_1
TIOB7_2
-
-
-
-
47
-
58
-
72
-
50
-
Document Number: 002-05675 Rev. *E
Page 21 of 99
CY9A1A0N Series
Pin No
Pin
Pin name
SWCLK
Function description
function
LQFP-64 LQFP-80 LQFP-100
QFP-100
56
Debugger
Serial wire debug interface clock input pin
50
62
78
Serial wire debug interface data input /
output pin
SWDIO
52
64
80
58
SWO
Serial wire viewer output pin
JTAG reset input pin
53
49
50
51
52
53
2
65
61
62
63
64
65
2
81
77
78
79
80
81
2
59
55
56
57
58
59
80
60
65
81
61
82
31
71
34
87
90
37
88
52
43
89
51
23
83
92
86
93
94
95
5
TRSTX
TCK
JTAG test clock input pin
JTAG test data input pin
TDI
TMS
JTAG test mode state input/output pin
JTAG debug data output pin
TDO
External
Interrupt
INT00_0
INT00_1
INT00_2
INT01_0
INT01_1
INT02_0
INT02_1
INT03_0
INT03_1
INT03_2
INT04_0
INT04_1
INT04_2
INT05_0
INT05_1
INT05_2
INT06_1
INT06_2
INT07_2
INT08_1
INT08_2
INT09_1
INT10_1
INT11_1
INT12_1
INT13_1
INT14_1
INT15_1
NMIX
External interrupt request 00 input pin
-
-
82
87
3
54
3
67
3
External interrupt request 01 input pin
External interrupt request 02 input pin
-
-
83
4
4
4
35
-
43
73
46
9
53
93
56
9
External interrupt request 03 input pin
External interrupt request 04 input pin
External interrupt request 05 input pin
38
5
8
12
49
10
60
55
11
59
35
5
12
59
10
74
65
11
73
45
5
40
6
-
-
7
48
27
-
External interrupt request 06 input pin
External interrupt request 07 input pin
External interrupt request 08 input pin
-
-
14
8
-
8
External interrupt request 09 input pin
External interrupt request 10 input pin
External interrupt request 11 input pin
External interrupt request 12 input pin
External interrupt request 13 input pin
External interrupt request 14 input pin
External interrupt request 15 input pin
Non-Maskable Interrupt input pin
-
-
15
16
17
27
28
39
96
92
-
-
-
-
-
-
-
-
6
-
29
76
72
17
74
70
60
57
Document Number: 002-05675 Rev. *E
Page 22 of 99
CY9A1A0N Series
Pin No
Pin
Pin name
P00
Function description
function
LQFP-64
LQFP-80
LQFP-100
QFP-100
55
GPIO
49
50
51
52
53
-
61
77
P01
P02
P03
P04
P05
P06
P07
P08
P09
P0A
P0B
P0C
P0D
P0E
P0F
P10
P11
P12
P13
P14
P15
P16
P17
P18
P19
P1A
P1B
P1C
P1D
P1E
P1F
P20
P21
P22
P23
62
63
64
65
-
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
52
53
54
55
56
57
58
59
63
64
65
66
67
68
69
70
74
73
72
71
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
30
31
32
33
34
35
36
37
41
42
43
44
45
46
47
48
52
51
50
49
-
-
-
66
-
General-purpose I/O port 0
-
-
-
54
55
56
-
67
68
69
70
71
72
42
43
44
45
46
47
48
49
53
54
55
56
-
-
57
34
35
36
37
38
39
-
40
44
45
-
General-purpose I/O port 1
-
-
-
-
-
-
-
-
-
60
59
58
57
48
47
46
General-purpose I/O port 2
Document Number: 002-05675 Rev. *E
Page 23 of 99
CY9A1A0N Series
Pin No
LQFP-100
Pin
Pin name
P30
Function description
function
LQFP-64 LQFP-80
QFP-100
GPIO
5
9
9
87
88
89
90
91
92
93
94
95
96
97
98
99
P31
P32
P33
P34
P35
P36
P37
P38
P39
P3A
P3B
P3C
P3D
P3E
P3F
P40
P41
P42
P43
P44
P45
P46
P47
P48
P49
P4A
P4B
P4C
P4D
P4E
P50
P51
P52
P53
P54
P55
P56
P60
P61
P62
P63
P80
P81
P82
PE0
PE2
PE3
6
10
11
12
-
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
27
28
29
30
31
32
36
37
39
40
41
42
43
44
45
2
7
8
-
-
-
-
-
-
-
General-purpose I/O port 3
-
-
9
13
14
15
16
17
18
19
-
10
11
12
13
14
15
-
100
1
2
5
-
-
6
-
-
7
-
-
8
-
21
22
26
27
29
30
31
32
33
34
35
2
9
-
10
14
15
17
18
19
20
21
22
23
80
81
82
83
84
85
86
74
73
72
71
75
76
77
24
26
27
19
20
-
General-purpose I/O port 4
22
23
24
25
26
27
2
3
3
3
4
4
4
General-purpose I/O port 5
General-purpose I/O port 6
-
5
5
-
6
6
-
7
7
-
8
8
60
59
58
-
76
75
74
73
77
78
79
36
38
39
96
95
94
93
97
98
99
46
48
49
61
62
63
28
30
31
General-purpose I/O port 8
General-purpose I/O port E
Document Number: 002-05675 Rev. *E
Page 24 of 99
CY9A1A0N Series
Pin No
Pin
function
Pin name
Function description
LQFP-64 LQFP-80 LQFP-100
QFP-100
Multi-
function
Serial
0
SIN0_0
SIN0_1
48
59
46
73
56
51
34
Multi-function serial interface ch.0 input
pin
-
Multi-function serial interface ch.0 output
pin.
This pin operates as SOT0 when it is used
in a UART/CSIO (operation modes 0 to 2)
and as SDA0 when it is used in an I2C
(operation mode 4).
SOT0_0
(SDA0_0)
47
-
58
47
57
72
57
71
50
35
49
SOT0_1
(SDA0_1)
Multi-function serial interface ch.0 clock
I/O pin.
This pin operates as SCK0 when it is used
in a UART/CSIO (operation modes 0 to 2)
and as SCL0 when it is used in an I2C
(operation mode 4).
SCK0_0
(SCL0_0)
46
SCK0_1
(SCL0_1)
-
48
43
58
53
36
31
Multi-
function
Serial
1
Multi-function serial interface ch.1 input
pin
SIN1_1
35
Multi-function serial interface ch.1 output
pin.
SOT1_1
(SDA1_1)
This pin operates as SOT1 when it is used
in a UART/CSIO (operation modes 0 to 2)
and as SDA1 when it is used in an I2C
(operation mode 4).
36
37
44
45
54
55
32
33
Multi-function serial interface ch.1 clock
I/O pin.
This pin operates as SCK1 when it is used
in a UART/CSIO (operation modes 0 to 2)
and as SCL1 when it is used in an I2C
(operation mode 4).
SCK1_1
(SCL1_1)
Multi-
function
Serial
2
Multi-function serial interface ch.2 input
pin
SIN2_2
40
44
49
53
59
63
37
41
Multi-function serial interface ch.2 output
pin.
This pin operates as SOT2 when it is used
in a UART/CSIO (operation modes 0 to 2)
and as SDA2 when it is used in an I2C
(operation mode 4).
SOT2_2
(SDA2_2)
Multi-function serial interface ch.2 clock
I/O pin.
SCK2_2
(SCL2_2)
This pin operates as SCK2 when it is used
in a UART/CSIO (operation modes 0 to 2)
and as SCL2 when it is used in an I2C
(operation mode 4).
45
54
64
42
Document Number: 002-05675 Rev. *E
Page 25 of 99
CY9A1A0N Series
Pin No
Pin
function
Pin name
Function description
LQFP-64
LQFP-80
LQFP-100
QFP-100
Multi-
function
Serial
3
SIN3_1
SIN3_2
2
2
2
80
17
Multi-function serial interface ch.3 input
pin
-
29
39
Multi-function serial interface ch.3 output
pin.
This pin operates as SOT3 when it is
used in a UART/CSIO (operation modes
0 to 2) and as SDA3 when it is used in
an I2C (operation mode 4).
SOT3_1
(SDA3_1)
3
3
3
81
18
82
19
SOT3_2
(SDA3_2)
-
30
4
40
4
Multi-function serial interface ch.3 clock
I/O pin.
This pin operates as SCK3 when it is
used in a UART/CSIO (operation modes
0 to 2) and as SCL3 when it is used in an
I2C (operation mode 4).
SCK3_1
(SCL3_1)
4
-
SCK3_2
(SCL3_2)
31
41
Multi-
function
Serial
4
SIN4_0
SIN4_1
SIN4_2
54
-
67
55
-
87
65
82
65
43
60
Multi-function serial interface ch.4 input
pin
-
SOT4_0
(SDA4_0)
Multi-function serial interface ch.4 output
pin.
This pin operates as SOT4 when it is
used in a UART/CSIO (operation modes
0 to 2) and as SDA4 when it is used in
an I2C (operation mode 4).
55
-
68
56
-
88
66
83
89
67
84
66
44
61
67
45
62
SOT4_1
(SDA4_1)
SOT4_2
(SDA4_2)
-
SCK4_0
(SCL4_0)
Multi-function serial interface ch.4 clock
I/O pin.
This pin operates as SCK4 when it is
used in a UART/CSIO (operation modes
0 to 2) and as SCL4 when it is used in an
I2C (operation mode 4).
56
-
69
-
SCK4_1
(SCL4_1)
SCK4_2
(SCL4_2)
-
-
RTS4_0
RTS4_1
RTS4_2
CTS4_0
CTS4_1
CTS4_2
-
-
-
-
-
-
70
-
90
69
86
91
68
85
68
47
64
69
46
63
Multi-function serial interface ch.4 RTS
output pin
-
71
-
Multi-function serial interface ch.4 CTS
input pin
-
Document Number: 002-05675 Rev. *E
Page 26 of 99
CY9A1A0N Series
Pin No
LQFP-80 LQFP-100
Pin
Pin name
Function description
function
LQFP-64
60
QFP-100
74
Multi-
function
Serial
5
SIN5_0
SIN5_2
76
96
15
Multi-function serial interface ch.5 input
pin
-
-
93
Multi-function serial interface ch.5 output
pin.
This pin operates as SOT5 when it is
used in a UART/CSIO (operation modes
0 to 2) and as SDA5 when it is used in
an I2C (operation mode 4).
SOT5_0
(SDA5_0)
59
75
-
95
16
94
17
73
SOT5_2
(SDA5_2)
-
94
72
95
Multi-function serial interface ch.5 clock
I/O pin.
This pin operates as SCK5 when it is
used in a UART/CSIO (operation modes
0 to 2) and as SCL5 when it is used in
an I2C (operation mode 4).
SCK5_0
(SCL5_0)
58
-
74
-
SCK5_2
(SCL5_2)
Multi-
function
Serial
6
SIN6_0
SIN6_1
-
5
5
83
90
Multi-function serial interface ch.6 input
pin
8
12
12
Multi-function serial interface ch.6 output
pin.
This pin operates as SOT6 when it is
used in a UART/CSIO (operation modes
0 to 2) and as SDA6 when it is used in
an I2C (operation mode 4).
SOT6_0
(SDA6_0)
-
6
6
84
89
85
88
SOT6_1
(SDA6_1)
7
-
11
7
11
7
Multi-function serial interface ch.6 clock
I/O pin.
This pin operates as SCK6 when it is
used in a UART/CSIO (operation modes
0 to 2) and as SCL6 when it is used in
an I2C (operation mode 4).
SCK6_0
(SCL6_0)
SCK6_1
(SCL6_1)
6
10
10
Multi-
function
Serial
7
SIN7_1
SIN7_2
27
61
35
77
45
97
23
75
Multi-function serial interface ch.7 input
pin
Multi-function serial interface ch.7 output
pin.
This pin operates as SOT7 when it is
used in a UART/CSIO (operation modes
0 to 2) and as SDA7 when it is used in
an I2C (operation mode 4).
SOT7_1
(SDA7_1)
26
62
25
63
34
78
33
79
44
98
43
99
22
76
21
77
SOT7_2
(SDA7_2)
Multi-function serial interface ch.7 clock
I/O pin.
This pin operates as SCK7 when it is
used in a UART/CSIO (operation modes
0 to 2) and as SCL7 when it is used in
an I2C (operation mode 4).
SCK7_1
(SCL7_1)
SCK7_2
(SCL7_2)
Document Number: 002-05675 Rev. *E
Page 27 of 99
CY9A1A0N Series
Pin No
Pin
function
Pin name
Function description
LQFP-64
LQFP-80
LQFP-100
QFP-100
96
Multi-
function
Timer
0
DTTI0X_0
DTTI0X_1
DTTI0X_2
FRCK0_0
FRCK0_1
FRCK0_2
IC00_0
9
13
-
18
Input signal of waveform generator to
control outputs RTO00 to RTO05 of
Multi-function timer 0
-
69
95
13
70
53
17
65
54
16
66
55
15
67
56
14
68
57
47
73
91
48
31
95
43
32
94
44
33
93
45
34
92
46
35
59
-
75
-
16-bit free-run timer ch.0 external clock
input pin
-
-
35
-
43
-
IC00_1
-
55
44
-
IC00_2
36
-
IC01_0
IC01_1
-
56
45
-
16-bit input capture input pin of
Multi-function timer 0.
ICxx describes a channel number.
IC01_2
37
-
IC02_0
IC02_1
-
-
IC02_2
38
-
46
-
IC03_0
IC03_1
-
-
IC03_2
39
47
RTO00_0
(PPG00_0)
Waveform generator output pin of
Multi-function timer 0.
This pin operates as PPG00 when it is
used in PPG0 output mode.
10
14
19
71
97
49
RTO00_1
(PPG00_1)
-
-
Waveform generator output pin of
Multi-function timer 0.
This pin operates as PPG00 when it is
used in PPG0 output mode.
RTO01_0
(PPG00_0)
11
12
13
14
15
16
17
18
20
21
22
23
98
99
100
1
Waveform generator output pin of
Multi-function timer 0.
This pin operates as PPG02 when it is
used in PPG0 output mode.
RTO02_0
(PPG02_0)
Waveform generator output pin of
Multi-function timer 0.
This pin operates as PPG02 when it is
used in PPG0 output mode.
RTO03_0
(PPG02_0)
Waveform generator output pin of
Multi-function timer 0.
This pin operates as PPG04 when it is
used in PPG0 output mode.
RTO04_0
(PPG04_0)
Waveform generator output pin of
Multi-function timer 0.
This pin operates as PPG04 when it is
used in PPG0 output mode.
RTO05_0
(PPG04_0)
15
24
19
32
24
42
2
PPG IGBT mode external trigger input
pin
IGTRG
20
Document Number: 002-05675 Rev. *E
Page 28 of 99
CY9A1A0N Series
Pin No
LQFP-80 LQFP-100
Pin
Pin name
Function description
function
LQFP-64
57
QFP-100
70
Real-time
clock
RTCCO_0
RTCCO_1
RTCCO_2
SUBOUT_0
72
45
14
72
45
14
92
55
19
92
55
19
Pulse output pin of Real-time clock
37
10
57
37
10
33
97
70
33
97
SUBOUT_1 Sub clock output pin
SUBOUT_2
Low-
Power
Consumption
Mode
Deep standby mode return signal input
pin 0
WKUP0
WKUP1
WKUP2
WKUP3
57
35
48
60
72
43
59
76
92
53
73
96
70
31
51
74
Deep standby mode return signal input
pin 1
Deep standby mode return signal input
pin 2
Deep standby mode return signal input
pin 3
DAC
DA0
D/A converter ch.0 analog output pin
D/A converter ch.1 analog output pin
HDMI-CEC ch.0 pin
26
27
25
60
34
35
33
76
44
45
43
96
22
23
21
74
DA1
HDMI-
CEC
CEC0
CEC1
HDMI-CEC ch.1 pin
Document Number: 002-05675 Rev. *E
Page 29 of 99
CY9A1A0N Series
Pin No
Pin
Pin name
Function description
External Reset Input Pin.
function
LQFP-64
21
LQFP-80
LQFP-100
QFP-100
16
Reset
Mode
INITX
28
38
A reset is valid when INITX = L.
Mode 0 pin.
During normal operation, MD0 = L must
be input.
During serial programming to Flash
memory, MD0 = H must be input.
MD0
MD1
29
28
37
36
47
46
25
Mode 1 pin.
During normal operation, input is not
needed. During serial programming to
Flash memory, MD1 = L must be input.
24
Power
GND
1
1
1
79
4
-
-
26
35
51
76
25
34
50
75
100
48
36
49
37
74
92
VCC
VSS
Power supply pin
18
33
-
25
41
-
13
29
54
3
16
-
20
24
40
-
12
28
53
78
26
14
27
15
52
70
GND pin
32
-
64
30
19
31
20
-
80
38
26
39
27
60
72
Clock
X0
Main clock (oscillation) input pin
Sub clock (oscillation) input pin
Main clock (oscillation) I/O pin
Sub clock (oscillation) I/O pin
X0A
X1
X1A
CROUT_0
CROUT_1
Built-in High-speed CR-osc clock output
port
57
Analog
Power
A/D converter and D/A converter
analog power supply pin
AVCC
AVRH
41
42
50
51
60
61
38
39
A/D converter analog reference voltage
input pin
Analog
GND
A/D converter and D/A converter
GND pin
AVSS
C
43
17
52
23
62
33
40
11
C pin
Power supply stabilization capacity pin
Note:
−
While this device contains a Test Access Port (TAP) based on the IEEE 1149.1-2001 JTAG standard, it is not fully compliant to
all requirements of that standard. This device may contain a 32-bit device ID that is the same as the 32-bit device ID in other
devices with different functionality. The TAP pins may also be configurable for purposes other than access to the TAP
controller.
Document Number: 002-05675 Rev. *E
Page 30 of 99
CY9A1A0N Series
5. I/O Circuit Type
Type
Circuit
Remarks
It is possible to select the main oscillation
/ GPIO function.
A
Pull-up
resistor
When the main oscillation is selected.
• Oscillation feedback resistor
: Approximately 1 MΩ
• With standby mode control
P-ch
P-ch
Digital output
Digital output
X1
When the GPIO is selected.
• CMOS level output.
N-ch
• CMOS level hysteresis input
• With pull-up resistor control
• With standby mode control
R
• Pull-up resistor
: Approximately 50 kΩ
• IOH = -4 mA, IOL = 4 mA
Pull-up resistor control
Digital input
Standby mode control
Clock input
Feedback
resistor
Standby mode control
Digital input
Standby mode control
Pull-up
resistor
R
Digital output
P-ch
N-ch
P-ch
X0
Digital output
Pull-up resistor control
B
• CMOS level hysteresis input
• Pull-up resistor
: Approximately 50 kΩ
Pull-up resistor
Digital input
Document Number: 002-05675 Rev. *E
Page 31 of 99
CY9A1A0N Series
Type
Circuit
Remarks
C
• Open drain output
• CMOS level hysteresis input
Digital input
Digital output
N-ch
It is possible to select the sub oscillation /
GPIO function
D
Pull-up
resistor
When the sub oscillation is selected.
• Oscillation feedback resistor
: Approximately 5 MΩ
P-ch
P-ch
Digital output
• With standby mode control
X1A
When the GPIO is selected.
• CMOS level output.
N-ch
• CMOS level hysteresis input
• With pull-up resistor control
• With standby mode control
Digital output
R
• Pull-up resistor
: Approximately 50 kΩ
• IOH = -4 mA, IOL = 4 mA
Pull-up resistor control
Digital input
Standby mode control
Clock input
Feedback
resistor
Standby mode control
Digital input
Standby mode control
Pull-up
resistor
R
Digital output
P-ch
N-ch
P-ch
X0A
Digital output
Pull-up resistor control
Document Number: 002-05675 Rev. *E
Page 32 of 99
CY9A1A0N Series
Type
Circuit
Remarks
E
• CMOS level output
• CMOS level hysteresis input
• With pull-up resistor control
• With standby mode control
• Pull-up resistor
: Approximately 50 kΩ
• IOH = -4 mA, IOL = 4 mA
• When this pin is used as an I2C pin, the
digital output P-ch transistor is always
off
P-ch
P-ch
Digital output
Digital output
N-ch
R
Pull-up resistor control
Digital input
Standby mode control
F
• CMOS level output
• CMOS level hysteresis input
• With input control
• Analog input
• With pull-up resistor control
• With standby mode control
• Pull-up resistor
: Approximately 50 kΩ
• IOH = -4 mA, IOL = 4 mA
• When this pin is used as an I2C pin, the
digital output P-ch transistor is always
off
Digital output
Digital output
P-ch
P-ch
N-ch
Pull-up resistor control
R
Digital input
Standby mode control
Analog input
Input control
Document Number: 002-05675 Rev. *E
Page 33 of 99
CY9A1A0N Series
Type
Circuit
Remarks
G
• CMOS level output
• CMOS level hysteresis input
• With standby mode control
• 5 V tolerant input
• IOH = -4 mA, IOL = 4 mA
Digital output
Digital output
P-ch
• Available to control PZR registers.
P0B, P0C, P4C, P60, P81, P82 only.
• When this pin is used as an I2C pin, the
digital output P-ch transistor is always
off
N-ch
R
Digital input
Standby mode control
CMOS level hysteresis input
H
J
Mode input
• CMOS level output
• CMOS level hysteresis input
• With input control
• Analog output
• With pull-up resistor control
• With standby mode control
• Pull-up resistor
: Approximately 50 kΩ
• IOH = -4 mA, IOL = 4 mA
• When this pin is used as an I2C pin, the
digital output P-ch transistor is always
off
P-ch
P-ch
Digital output
Digital output
N-ch
Pull-up resistor control
R
Digital input
Standby mode control
Analog output
Document Number: 002-05675 Rev. *E
Page 34 of 99
CY9A1A0N Series
6. Handling Precautions
Any semiconductor devices have inherently a certain rate of failure. The possibility of failure is greatly affected by the conditions in
which they are used (circuit conditions, environmental conditions, etc.). This page describes precautions that must be observed to
minimize the chance of failure and to obtain higher reliability from your Cypress semiconductor devices.
6.1 Precautions for Product Design
This section describes precautions when designing electronic equipment using semiconductor devices.
Absolute Maximum Ratings
Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of
certain established limits, called absolute maximum ratings. Do not exceed these ratings.
Recommended Operating Conditions
Recommended operating conditions are normal operating ranges for the semiconductor device. All the device's electrical
characteristics are warranted when operated within these ranges.
Always use semiconductor devices within the recommended operating conditions. Operation outside these ranges may adversely
affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users
considering application outside the listed conditions are advised to contact their sales representative beforehand.
Processing and Protection of Pins
These precautions must be followed when handling the pins which connect semiconductor devices to power supply and input/output
functions.
1. Preventing Over-Voltage and Over-Current Conditions
Exposure to voltage or current levels in excess of maximum ratings at any pin is likely to cause deterioration within the device,
and in extreme cases leads to permanent damage of the device. Try to prevent such overvoltage or over-current conditions at
the design stage.
2. Protection of Output Pins
Shorting of output pins to supply pins or other output pins, or connection to large capacitance can cause large current flows.
Such conditions if present for extended periods of time can damage the device.
Therefore, avoid this type of connection.
3. Handling of Unused Input Pins
Unconnected input pins with very high impedance levels can adversely affect stability of operation. Such pins should be
connected through an appropriate resistance to a power supply pin or ground pin.
Latch-up
Semiconductor devices are constructed by the formation of P-type and N-type areas on a substrate. When subjected to abnormally
high voltages, internal parasitic PNPN junctions (called thyristor structures) may be formed, causing large current levels in excess of
several hundred mA to flow continuously at the power supply pin. This condition is called latch-up.
CAUTION: The occurrence of latch-up not only causes loss of reliability in the semiconductor device, but can cause injury or
damage from high heat, smoke or flame. To prevent this from happening, do the following:
1. Be sure that voltages applied to pins do not exceed the absolute maximum ratings. This should include attention to abnormal
noise, surge levels, etc.
2. Be sure that abnormal current flows do not occur during the power-on sequence.
Observance of Safety Regulations and Standards
Most countries in the world have established standards and regulations regarding safety, protection from electromagnetic
interference, etc. Customers are requested to observe applicable regulations and standards in the design of products.
Fail-Safe Design
Any semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage or loss from such
failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and
prevention of over-current levels and other abnormal operating conditions.
Document Number: 002-05675 Rev. *E
Page 35 of 99
CY9A1A0N Series
Precautions Related to Usage of Devices
Cypress semiconductor devices are intended for use in standard applications (computers, office automation and other office
equipment, industrial, communications, and measurement equipment, personal or household devices, etc.).
CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly
affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as
aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.)
are requested to consult with sales representatives before such use. The company will not be responsible for damages arising from
such use without prior approval.
6.2 Precautions for Package Mounting
Package mounting may be either lead insertion type or surface mount type. In either case, for heat resistance during soldering, you
should only mount under Cypress' recommended conditions. For detailed information about mount conditions, contact your sales
representative.
Lead Insertion Type
Mounting of lead insertion type packages onto printed circuit boards may be done by two methods: direct soldering on the board, or
mounting by using a socket.
Direct mounting onto boards normally involves processes for inserting leads into through-holes on the board and using the flow
soldering (wave soldering) method of applying liquid solder. In this case, the soldering process usually causes leads to be subjected
to thermal stress in excess of the absolute ratings for storage temperature. Mounting processes should conform to Cypress
recommended mounting conditions.
If socket mounting is used, differences in surface treatment of the socket contacts and IC lead surfaces can lead to contact
deterioration after long periods. For this reason it is recommended that the surface treatment of socket contacts and IC leads be
verified before mounting.
Surface Mount Type
Surface mount packaging has longer and thinner leads than lead-insertion packaging, and therefore leads are more easily deformed
or bent. The use of packages with higher pin counts and narrower pin pitch results in increased susceptibility to open connections
caused by deformed pins, or shorting due to solder bridges.
You must use appropriate mounting techniques. Cypress Inc. recommends the solder reflow method, and has established a ranking
of mounting conditions for each product. Users are advised to mount packages in accordance with Cypress ranking of
recommended conditions.
Lead-Free Packaging
CAUTION: When ball grid array (BGA) packages with Sn-Ag-Cu balls are mounted using Sn-Pb eutectic soldering, junction strength
may be reduced under some conditions of use.
Storage of Semiconductor Devices
Because plastic chip packages are formed from plastic resins, exposure to natural environmental conditions will cause absorption of
moisture. During mounting, the application of heat to a package that has absorbed moisture can cause surfaces to peel, reducing
moisture resistance and causing packages to crack. To prevent, do the following:
1. Avoid exposure to rapid temperature changes, which cause moisture to condense inside the product. Store products in
locations where temperature changes are slight.
2. Use dry boxes for product storage. Products should be stored below 70% relative humidity, and at temperatures between 5°C
and 30°C.
When you open Dry Package that recommends humidity 40% to 70% relative humidity.
3. When necessary, Cypress Inc. packages semiconductor devices in highly moisture-resistant aluminum laminate bags, with a
silica gel desiccant. Devices should be sealed in their aluminum laminate bags for storage.
4. Avoid storing packages where they are exposed to corrosive gases or high levels of dust.
Baking
Packages that have absorbed moisture may be de-moisturized by baking (heat drying). Follow the Cypress recommended
conditions for baking.
Condition: 125°C/24 h
Document Number: 002-05675 Rev. *E
Page 36 of 99
CY9A1A0N Series
Static Electricity
Because semiconductor devices are particularly susceptible to damage by static electricity, you must take the following precautions:
1. Maintain relative humidity in the working environment between 40% and 70%. Use of an apparatus for ion generation may be
needed to remove electricity.
2. Electrically ground all conveyors, solder vessels, soldering irons and peripheral equipment.
3. Eliminate static body electricity by the use of rings or bracelets connected to ground through high resistance (on the level of 1
MΩ).
Wearing of conductive clothing and shoes, use of conductive floor mats and other measures to minimize shock loads is
recommended.
4. Ground all fixtures and instruments, or protect with anti-static measures.
5. Avoid the use of styrofoam or other highly static-prone materials for storage of completed board assemblies.
6.3 Precautions for Use Environment
Reliability of semiconductor devices depends on ambient temperature and other conditions as described above.
For reliable performance, do the following:
1. Humidity
Prolonged use in high humidity can lead to leakage in devices as well as printed circuit boards. If high humidity levels are
anticipated, consider anti-humidity processing.
2. Discharge of Static Electricity
When high-voltage charges exist close to semiconductor devices, discharges can cause abnormal operation. In such cases,
use anti-static measures or processing to prevent discharges.
3. Corrosive Gases, Dust, or Oil
Exposure to corrosive gases or contact with dust or oil may lead to chemical reactions that will adversely affect the device. If
you use devices in such conditions, consider ways to prevent such exposure or to protect the devices.
4. Radiation, Including Cosmic Radiation
Most devices are not designed for environments involving exposure to radiation or cosmic radiation. Users should provide
shielding as appropriate.
5. Smoke, Flame
CAUTION: Plastic molded devices are flammable, and therefore should not be used near combustible substances. If devices
begin to smoke or burn, there is danger of the release of toxic gases.
Customers considering the use of Cypress products in other special environmental conditions should consult with sales
representatives.
Document Number: 002-05675 Rev. *E
Page 37 of 99
CY9A1A0N Series
7. Handling Devices
Power supply pins
In products with multiple VCC and VSS pins, respective pins at the same potential are interconnected within the device in order to
prevent malfunctions such as latch-up. However, all of these pins should be connected externally to the power supply or ground
lines in order to reduce electromagnetic emission levels, to prevent abnormal operation of strobe signals caused by the rise in the
ground level, and to conform to the total output current rating.
Moreover, connect the current supply source with each Power supply pins and GND pins of this device at low impedance. It is also
advisable that a ceramic capacitor of approximately 0.1 µF be connected as a bypass capacitor between each Power supply pin and
GND pin, between AVCC pin and AVSS pin near this device.
Stabilizing power supply voltage
A malfunction may occur when the power supply voltage fluctuates rapidly even though the fluctuation is within the recommended
operating conditions of the VCC power supply voltage. As a rule, with voltage stabilization, suppress the voltage fluctuation so that
the fluctuation in VCC ripple (peak-to-peak value) at the commercial frequency (50 Hz/60 Hz) does not exceed 10% of the VCC
value in the recommended operating conditions, and the transient fluctuation rate does not exceed 0.1 V/μs when there is a
momentary fluctuation on switching the power supply.
Crystal oscillator circuit
Noise near the X0/X1 and X0A/X1A pins may cause the device to malfunction. Design the printed circuit board so that X0/X1,
X0A/X1A pins, the crystal oscillator, and the bypass capacitor to ground are located as close to the device as possible.
It is strongly recommended that the PC board artwork be designed such that the X0/X1 and X0A/X1A pins are surrounded by
ground plane as this is expected to produce stable operation.
Evaluate oscillation of your using crystal oscillator by your mount board.
Using an external clock
To use the external clock, set general-purpose I/O ports to input the clock to X0/PE2 and X0A/P46 pin.
Example of Using an External Clock
Device
X0/PE2 (X0A/P46)
Set as
general-purpose I/O
ports.
Can be used as
general-purpose I/O
ports.
X1/PE3 (X1A/P47)
Handling when using Multi-function serial pin as I2C pin
If it is using the multi-function serial pin as I2C pins, P-ch transistor of digital output is always disabled. However, I2C pins need to
keep the electrical characteristic like other pins and not to connect to the external I2C bus system with power OFF.
Document Number: 002-05675 Rev. *E
Page 38 of 99
CY9A1A0N Series
C Pin
This series contains the regulator. Be sure to connect a smoothing capacitor (CS) for the regulator between the C pin and the GND
pin. Please use a ceramic capacitor or a capacitor of equivalent frequency characteristics as a smoothing capacitor.
However, some laminated ceramic capacitors have the characteristics of capacitance variation due to thermal fluctuation (F
characteristics and Y5V characteristics). Please select the capacitor that meets the specifications in the operating conditions to use
by evaluating the temperature characteristics of a capacitor.
A smoothing capacitor of about 4.7μF would be recommended for this series.
C
Device
Cs
VSS
GND
Mode pins (MD0, MD1)
Connect the MD pin (MD0, MD1) directly to VCC or VSS pins. Design the printed circuit board such that the pull-up/down resistance
stays low, as well as the distance between the mode pins and VCC pins or VSS pins is as short as possible and the connection
impedance is low, when the pins are pulled-up/down such as for switching the pin level and rewriting the Flash memory data. It is
because of preventing the device erroneously switching to test mode due to noise.
Notes on power-on
Turn power on/off in the following order or at the same time.
If not using the A/D converter, connect AVCC = VCC and AVSS = VSS.
Turning on: VCC AVCC AVRH
Turning off: AVRH AVCC VCC
Serial Communication
There is a possibility to receive wrong data due to the noise or other causes on the serial communication.
Therefore, design a printed circuit board so as to avoid noise.
Consider the case of receiving wrong data due to noise, perform error detection such as by applying a checksum of data at the end.
If an error is detected, retransmit the data.
Differences in features among the products with different memory sizes and between Flash memory
products and MASK products
The electric characteristics including power consumption, ESD, latch-up, noise characteristics, and oscillation characteristics among
the products with different memory sizes and between Flash memory products and MASK products are different because chip
layout and memory structures are different.
If you are switching to use a different product of the same series, please make sure to evaluate the electric characteristics.
Document Number: 002-05675 Rev. *E
Page 39 of 99
CY9A1A0N Series
8. Block Diagram
MB9AF1A1/1A2
TRSTX,TCK,
TDI,TMS
ROM
Table
SWJ-DP
TDO
Cortex-M3 Core
@20MHz(Max)
On-Chip
Flash
64/128Kbyte
Flash I/F
Security
I
D
NVIC
Sys
SRAM1
12/16Kbyte
Watchdog Timer
(Software)
Clock Reset
Generator
INITX
Watchdog Timer
(Hardware)
CSV
CLK
X0
Main
Source Clock
PLL
Osc
Sub
Osc
X1
CR
4MHz
CR
100kHz
X0A
X1A
CROUT
Deep Standby Ctrl
WKUPx
AVCC,
12-bit A/D Converter
Unit 0
AVSS,AVRH
Power On
Reset
ANxx
LVD
LVD Ctrl
ADTGx
C
Regulator
IRQ-Monitor
10-bit D/A Converter
2ch.
DAx
TIOAx
TIOBx
Base Timer
16-bit 8ch./
32-bit 4ch.
HDMI-CEC/
Remote Receiver
Control
CECx
RTCCO
SUBOUT
A/D Activation
Compare
1ch.
Real Time Clock
External Interrupt
Controller
16-pin + NMI
INTxx
IC0x
16-bit Input Capture
4ch.
NMIX
16-bit FreeRun Timer
3ch.
FRCK0
MD1,
MD0
MODE-Ctrl
GPIO
16-bit Output
Compare
6ch.
P0x,
P1x,
.
.
.
PIN-Function-Ctrl
DTTI0X
RTO0x
Waveform Generator
3ch.
Pxx
SCKx
Multi-Function
Serial IF
SINx
16-bit PPG
3ch.
SOTx
CTS4
RTS4
IGTRG
8ch.
HW flow control(ch.4)*
Multi-Function Timer ×1
*: For the CY9AF1A1L and CY9AF1A2L, Multi-function Serial Interface does not support hardware flow control in these products.
Document Number: 002-05675 Rev. *E
Page 40 of 99
CY9A1A0N Series
9. Memory Size
See Memory size in Product Lineup to confirm the memory size.
10.Memory Map
Memory Map (1)
Peripherals Area
0x41FF_FFFF
0xFFFF_FFFF
Reserved
0xE010_0000
Cortex-M3 Private
Reserved
Peripherals
0xE000_0000
Reserved
0x4003_C000
0x4003_B000
RTC
Reserved
MFS
0x4003_9000
0x4003_8000
0x4400_0000
0x4200_0000
Reserved
32Mbytes
Bit band alias
0x4003_6000
0x4003_5000
LVD/DS mode
HDMI-CEC/
Remote Control Receiver
GPIO
0x4003_4000
0x4003_3000
0x4003_2000
0x4003_1000
0x4003_0000
0x4002_F000
0x4002_E000
Peripherals
Reserved
0x4000_0000
Reserved
Int-Req.Read
EXTI
Reserved
CR Trim
0x2400_0000
0x2200_0000
32Mbytes
Bit band alias
Reserved
0x4002_9000
0x4002_8000
0x4002_7000
0x4002_6000
0x4002_5000
0x4002_4000
D/AC
A/DC
Reserved
Base Timer
PPG
Reserved
0x2008_0000
0x2000_0000
SRAM1
Reserved
Reserved
MFT unit0
0x0010_0008
0x0010_0000
0x4002_1000
0x4002_0000
See " Memory Map (2)"
for the memory size
details.
Security/CR Trim
Reserved
Flash
0x4001_3000
0x4001_2000
0x4001_1000
0x4001_0000
0x0000_0000
SW WDT
HW WDT
Clock/Reset
Reserved
Flash I/F
0x4000_1000
0x4000_0000
Document Number: 002-05675 Rev. *E
Page 41 of 99
CY9A1A0N Series
Memory Map (2)
*: See CY9AAA0N/1A0N/A30N/130N/130L Series Flash Programming Manual to confirm the detail of Flash memory.
Peripheral Address Map
Document Number: 002-05675 Rev. *E
Page 42 of 99
CY9A1A0N Series
Start address
End address
Bus
AHB
Peripherals
0x4000_0000
0x4000_1000
0x4001_0000
0x4001_1000
0x4001_2000
0x4001_3000
0x4001_5000
0x4001_6000
0x4002_0000
0x4002_1000
0x4002_2000
0x4002_4000
0x4002_5000
0x4002_6000
0x4002_7000
0x4002_8000
0x4002_9000
0x4002_E000
0x4002_F000
0x4003_0000
0x4003_1000
0x4003_2000
0x4003_3000
0x4003_4000
0x4003_5000
0x4003_5100
0x4003_6000
0x4003_7000
0x4003_8000
0x4003_9000
0x4003_A000
0x4003_B000
0x4003_C000
0x4004_0000
0x4005_0000
0x4006_0000
0x4006_1000
0x4006_2000
0x4006_3000
0x4006_4000
0x4000_0FFF
0x4000_FFFF
0x4001_0FFF
0x4001_1FFF
0x4001_2FFF
0x4001_4FFF
0x4001_5FFF
0x4001_FFFF
0x4002_0FFF
0x4002_1FFF
0x4002_3FFF
0x4002_4FFF
0x4002_5FFF
0x4002_6FFF
0x4002_7FFF
0x4002_8FFF
0x4002_DFFF
0x4002_EFFF
0x4002_FFFF
0x4003_0FFF
0x4003_1FFF
0x4003_2FFF
0x4003_3FFF
0x4003_4FFF
0x4003_50FF
0x4003_5FFF
0x4003_6FFF
0x4003_7FFF
0x4003_8FFF
0x4003_9FFF
0x4003_AFFF
0x4003_BFFF
0x4003_FFFF
0x4004_FFFF
0x4005_FFFF
0x4006_0FFF
0x4006_1FFF
0x4006_2FFF
0x4006_3FFF
0x41FF_FFFF
Flash memory I/F register
Reserved
Clock/Reset Control
Hardware Watchdog timer
Software Watchdog timer
Reserved
APB0
Reserved
Reserved
Multi-function timer unit0
Reserved
Reserved
PPG
Base Timer
APB1
Reserved
A/D Converter
D/A Converter
Reserved
Built-in CR trimming
Reserved
External Interrupt
Interrupt Source Check Register
Reserved
GPIO
HDMI-CEC/ Remote Control Receiver
Low-Voltage Detector
Deep standby mode Controller
Reserved
APB2
Reserved
Multi-function serial
Reserved
Reserved
Real-time clock
Reserved
Reserved
Reserved
Reserved
AHB
Reserved
Reserved
Reserved
Reserved
Document Number: 002-05675 Rev. *E
Page 43 of 99
CY9A1A0N Series
11.Pin Status in Each CPU State
The terms used for pin status have the following meanings.
INITX = 0
This is the period when the INITX pin is the L level.
INITX = 1
This is the period when the INITX pin is the H level.
SPL = 0
This is the status that the standby pin level setting bit (SPL) in the standby mode control register (STB_CTL) is set to 0.
SPL = 1
This is the status that the standby pin level setting bit (SPL) in the standby mode control register (STB_CTL) is set to 1.
Input enabled
Indicates that the input function can be used.
Internal input fixed at 0
This is the status that the input function cannot be used. Internal input is fixed at L.
Hi-Z
Indicates that the pin drive transistor is disabled and the pin is put in the Hi-Z state.
Setting disabled
Indicates that the setting is disabled.
Maintain previous state
Maintains the state that was immediately prior to entering the current mode.
If a built-in peripheral function is operating, the output follows the peripheral function.
If the pin is being used as a port, that output is maintained.
Analog input is enabled
Indicates that the analog input is enabled.
Trace output
Indicates that the trace function can be used.
GPIO selected
In Deep Standby mode, pins switch to the general-purpose I/O port.
Document Number: 002-05675 Rev. *E
Page 44 of 99
CY9A1A0N Series
List of Pin Status
Power-on
Run
mode or
Sleep
mode
state
Device
internal
reset
reset or
low-voltage
detection
state
INITX
input
state
Timer mode,
RTC mode, or
Stop mode state
Deep Standby RTC mode Return from
or Deep Standby Stop Deep Standby
mode state
mode state
state
Function
group
Power
supply
unstable
Power
Power supply
stable
Power supply stable supply Power supply stable
stable
Power supply stable
INITX = 1
-
-
INITX = 0 INITX = 1 INITX = 1
INITX = 1
SPL = 0 SPL = 1
INITX = 1
-
-
-
SPL = 0
SPL = 1
-
Main
crystal
oscillator enabled
input pin
Input
Input
enabled enabled
Input
Input
enabled enabled
Input
Input
enabled
Input
enabled
Input
enabled
Input enabled
Maintain
previous
state /
When
oscillation
Hi-Z /
Input
enabled /
When
oscillation
stops*1,
Hi-Z /
Internal
input fixed
at 0
Output
External
maintains
previous
state /
Internal input
fixed at 0
main
Maintain stops*1,
previous output
Hi-Z /
Setting
clock
Setting
disabled disabled
Setting
Internal input GPIO selected
fixed at 0
disabled
input
selected
state
maintains
previous
state /
Internal
input fixed
at 0
A
Output
maintains
Maintain previous
previous state /
Output
maintains
previous
Hi-Z /
Internal
Hi-Z /
GPIO
selected disabled
Setting
Setting
disabled disabled
Setting
Maintain
Internal input
previous state
fixed at 0
input fixed state /
state
Internal
input fixed
at 0
at 0
Internal input
fixed at 0
Maintain Maintain
previous previous
Maintain
previous
state /
Maintain
previous
state /
Maintain
previous
state /
Maintain
previous state
/
state /
When
state /
When
When
Main
crystal
Hi-Z /
Internal
Hi-Z /
Internal
Hi-Z /
Internal
oscillation oscillation oscillation When
When
oscillation
When
oscillation
stops*1, stops*1, stops*1,
oscillation
oscillator input fixed input fixed input fixed
output pin at 0
Hi-Z
Hi-Z output Hi-Z output stops*1, Hi-Z stops*1, Hi-Z stops*1, Hi-Z
at 0
at 0
output /
/
/
output /
output /
output /
Internal Internal
input
Internal
Internal input Internal input Internal input
B
input fixed input fixed fixed at 0
fixed at 0
fixed at 0
fixed at 0 at 0
at 0
Output
Hi-Z /
Internal
maintains
previous
input fixed state /
Maintain Maintain
previous previous
Hi-Z /
Internal input
fixed at 0
GPIO
selected disabled
Setting
Setting
disabled disabled
Setting
Maintain
previous state
state
state
at 0
Internal input
fixed at 0
Pull-up /
INITX
Pull-up / Pull-up /
Pull-up / Pull-up /
Input Input
enabled enabled
Pull-up /
Input
enabled
Pull-up /
Input
enabled
Pull-up /
Input
enabled
Pull-up / Input
enabled
C
Input
Input
Input
input pin
enabled
enabled enabled
Document Number: 002-05675 Rev. *E
Page 45 of 99
CY9A1A0N Series
Power-on
reset or
low-voltage
detection
state
Run
mode or
Sleep
mode
state
Device
internal
reset
INITX
input
state
Timer mode,
RTC mode, or
Stop mode state
Deep Standby RTC mode Return from
or Deep Standby Stop Deep Standby
mode state
mode state
state
Function
group
Power
supply
unstable
Power
Power supply
stable
Power supply stable supply Power supply stable
stable
Power supply stable
INITX = 1
-
-
INITX = 0 INITX = 1 INITX = 1
INITX = 1
SPL = 0 SPL = 1
Input
INITX = 1
-
-
-
SPL = 0
SPL = 1
-
Mode
input pin enabled
Input
Input
Input
Input
enabled enabled
Input
Input
Input
D
E
Input enabled
enabled enabled
enabled
enabled
enabled
Pull-up / Pull-up /
Maintain
previous
state
Maintain
previous
state
JTAG
Hi-Z
Input
Input
selected
enabled enabled
Maintain Maintain
previous previous
Maintain
previous
state
Maintain
previous state
Hi-Z /
Hi-Z /
Internal input
fixed at 0
state
state
GPIO
Setting
Setting
Setting
Internal
input fixed
at 0
selected disabled
disabled disabled
External
Maintain
previous
state
interrupt Setting
enabled disabled
selected
Setting
disabled disabled
Setting
GPIO
selected
Internal input
fixed at 0
GPIO selected
Resource
other than
above
Maintain Maintain
previous previous
Hi-Z /
Internal input
fixed at 0
F
selected
Hi-Z /
state
state
Hi-Z /
Input
enabled enabled
Hi-Z /
Input
Internal
input fixed
at 0
Output
Hi-Z
maintains
previous
state /
GPIO
selected
Maintain
previous state
Internal input
fixed at 0
Hi-Z /
Internal
input fixed enabled
at 0
Hi-Z /
WKUP input
enabled
WKUP
Setting
Setting
Setting
WKUP input
enabled disabled
disabled disabled
External
Maintain
previous
interrupt Setting
enabled disabled
selected
Setting
disabled disabled
Setting
GPIO selected
GPIO
state
selected
Maintain Maintain
previous previous
Internal input
fixed at 0
Resource
other than
above
G
state
state
Hi-Z /
Internal input
fixed at 0
selected
Hi-Z /
Hi-Z /
Input
enabled enabled
Hi-Z /
Input
Internal
input fixed
at 0
Output
Hi-Z
maintains
previous
state /
GPIO
selected
Maintain
previous state
Internal input
fixed at 0
Document Number: 002-05675 Rev. *E
Page 46 of 99
CY9A1A0N Series
Power-on
reset or
low-voltage
detection
state
Run
mode or
Sleep
mode
state
Device
internal
reset
INITX
input
state
Timer mode,
RTC mode, or
Stop mode state
Deep Standby RTC mode Return from
or Deep Standby Stop Deep Standby
mode state
mode state
state
Function
group
Power
supply
unstable
Power
Power supply
stable
Power supply stable supply Power supply stable
stable
Power supply stable
INITX = 1
-
-
INITX = 0 INITX = 1 INITX = 1
INITX = 1
SPL = 0 SPL = 1
INITX = 1
-
-
-
SPL = 0
SPL = 1
-
GPIO
Resource
selected
selected
Internal input
fixed at 0
GPIO selected
Hi-Z /
Hi-Z /
Input
enabled enabled
Hi-Z /
Input
Maintain Maintain
previous previous
Hi-Z /
Internal input
fixed at 0
Internal
input fixed
at 0
Output
H
Hi-Z
maintains
previous
state /
state
state
GPIO
selected
Maintain
previous state
Internal input
fixed at 0
Maintain
previous
state
NMIX
selected disabled
Setting
Setting
disabled disabled
Setting
GPIO selected
Resource
other than
above
Maintain Maintain
previous previous
Hi-Z /
WKUP input
enabled
WKUP input
enabled
I
Hi-Z /
Hi-Z /
Input
enabled enabled
Hi-Z /
Input
state
state
Internal
input fixed
at 0
Hi-Z
selected
GPIO
Maintain
selected
previous state
Hi-Z /
Internal
input
fixed at 0
/
Analog
input
enabled
Hi-Z /
Internal
input fixed input fixed
at 0 /
Analog
input
enabled enabled
Hi-Z /
Internal
Hi-Z /
Internal
Hi-Z /
Internal
Hi-Z /
Hi-Z /
Hi-Z /
Analog
input
selected
input fixed input fixed Internal input Internal input Internal input
at 0 /
Analog
input
enabled
Hi-Z
at 0 /
Analog
input
at 0 /
Analog
input
fixed at 0 /
Analog input Analog input Analog input
enabled
fixed at 0 /
fixed at 0 /
enabled
enabled
enabled
Resource
other than
above
GPIO
J
selected
Internal input
fixed at 0
GPIO selected
selected
Hi-Z /
Maintain Maintain
previous previous
Hi-Z /
Internal input
fixed at 0
Setting
disabled
Setting
disabled disabled
Setting
Internal
input fixed
at 0
Output
maintains
previous
state /
state
state
GPIO
selected
Maintain
previous state
Internal input
fixed at 0
Document Number: 002-05675 Rev. *E
Page 47 of 99
CY9A1A0N Series
Power-on
reset or
low-voltage
detection
state
Run
mode or
Sleep
mode
state
Device
internal
reset
INITX
input
state
Timer mode,
RTC mode, or
Stop mode state
Deep Standby RTC mode Return from
or Deep Standby Stop Deep Standby
mode state
mode state
state
Function
group
Power
supply
unstable
Power
Power supply
stable
Power supply stable supply Power supply stable
stable
Power supply stable
INITX = 1
-
-
INITX = 0 INITX = 1 INITX = 1
INITX = 1
SPL = 0 SPL = 1
INITX = 1
-
-
-
SPL = 0
SPL = 1
-
Hi-Z /
Internal
input
fixed at 0
/
Analog
input
enabled
Hi-Z /
Internal
input fixed input fixed
at 0 /
Analog
input
enabled enabled
Hi-Z /
Internal
Hi-Z /
Internal
Hi-Z /
Internal
Hi-Z /
Hi-Z /
Hi-Z /
Analog
input
selected
input fixed input fixed Internal input Internal input Internal input
at 0 /
Analog
input
enabled
Hi-Z
at 0 /
Analog
input
at 0 /
Analog
input
fixed at 0 /
Analog input Analog input Analog input
enabled
fixed at 0 /
fixed at 0 /
enabled
enabled
enabled
External
interrupt
enabled
selected
Maintain
previous
state
GPIO
K
selected
Internal input
fixed at 0
GPIO selected
Resource
other than
above
Maintain Maintain
previous previous
Hi-Z /
Internal input
fixed at 0
Setting
Setting
disabled disabled
Setting
selected disabled
Hi-Z /
state
state
Internal
input fixed
at 0
Output
maintains
previous
state /
GPIO
selected
Maintain
previous state
Internal input
fixed at 0
Hi-Z /
Internal
input
fixed at 0
/
Analog
input
enabled
Hi-Z /
Internal
input fixed input fixed
at 0 /
Analog
input
enabled enabled
Hi-Z /
Internal
Hi-Z /
Internal
Hi-Z /
Internal
Hi-Z /
Hi-Z /
Hi-Z /
Analog
input
selected
input fixed input fixed Internal input Internal input Internal input
at 0 /
Analog
input
enabled
Hi-Z
at 0 /
Analog
input
at 0 /
Analog
input
fixed at 0 /
Analog input Analog input Analog input
enabled
fixed at 0 /
fixed at 0 /
enabled
enabled
enabled
Hi-Z /
Internal
input fixed enabled
at 0
Hi-Z /
WKUP input
enabled
WKUP
enabled
WKUP input
External
interrupt
enabled
selected
Resource
other than
above
L
Maintain
previous
state
GPIO selected
GPIO
selected
Internal input
fixed at 0
Maintain Maintain
previous previous
Setting
disabled
Setting
disabled disabled
Setting
state
state
Hi-Z /
Internal input
fixed at 0
selected
Hi-Z /
Internal
input fixed
at 0
Output
maintains
previous
state /
GPIO
selected
Maintain
previous state
Internal input
fixed at "0"
Document Number: 002-05675 Rev. *E
Page 48 of 99
CY9A1A0N Series
Power-on
reset or
low-voltage
detection
state
Run
mode or
Sleep
mode
state
Device
internal
reset
INITX
input
state
Timer mode,
RTC mode, or
Stop mode state
Deep Standby RTC mode Return from
or Deep Standby Stop Deep Standby
mode state
mode state
state
Function
group
Power
supply
unstable
Power
Power supply
stable
Power supply stable supply Power supply stable
stable
Power supply stable
INITX = 1
-
-
INITX = 0 INITX = 1 INITX = 1
INITX = 1
SPL = 0 SPL = 1
INITX = 1
-
-
-
SPL = 0
SPL = 1
-
Sub
crystal
oscillator enabled
input pin
Input
Input
enabled enabled
Input
Input
enabled enabled
Input
Input
enabled
Input
enabled
Input
enabled
Input enabled
Maintain
previous
state /
When
oscillation
Maintain
previous
state / When
oscillation
stops*2,
Hi-Z / Input
enabled /
When
oscillation
stops*2,
Hi-Z /
Internal
input fixed
at 0
Hi-Z / Input Maintain
enabled /
When
previous state
/
External
Maintain stops*2,
previous output
sub clock Setting
Setting
disabled disabled
Setting
oscillation
When Return
output
input
disabled
stops*2, Hi-Z from Deep
state
maintains
previous
state /
Internal
input fixed
at 0
maintains
previous
state /
Internal input
fixed at 0
M selected
/ Internal
Standby STOP
input fixed at mode, GPIO is
0
selected
Output
maintains
Maintain previous
previous state /
Output
maintains
previous
Hi-Z /
Internal
Hi-Z /
Internal input
fixed at 0
GPIO
selected disabled
Setting
Setting
disabled disabled
Setting
Maintain
previous state
input fixed state /
state
Internal
input fixed
at 0
at 0
Internal input
fixed at 0
Maintain
previous
state /
Maintain
previous
state /
Maintain
previous
Maintain
previous
Maintain
previous state
Sub
crystal
Hi-Z /
Internal
Hi-Z /
Internal
Hi-Z /
Internal
When
When
state / When state / When /
Maintain
previous
state
oscillation oscillation oscillation
oscillation
When
oscillator input fixed input fixed input fixed
output pin at 0
stops*2,
Hi-Z /
stops*2,
Hi-Z /
stops*2, Hi-Z stops*2, Hi-Z oscillation
at 0
at 0
/ Internal
/ Internal
stops*2,
Internal
input fixed input fixed
Internal
input fixed at input fixed at Hi-Z / Internal
N
0
0
input fixed at 0
at 0
at 0
Output
Hi-Z /
Internal
maintains
previous
input fixed state /
Maintain Maintain
previous previous
Hi-Z /
Internal input
fixed at 0
GPIO
selected disabled
Setting
Setting
disabled disabled
Setting
Maintain
previous state
state
state
at 0
Internal input
fixed at 0
GPIO
External
Maintain
previous
state
selected /
Internal input
fixed at 0
interrupt Setting
enabled disabled
selected
Setting
disabled disabled
Setting
GPIO selected
Maintain Maintain
previous previous
Hi-Z /
Output
maintains
previous
O
Internal input
fixed at 0
Hi-Z /
Internal
state
state
Hi-Z /
Input
enabled enabled
Hi-Z /
Input
GPIO
Hi-Z
Maintain
selected
input fixed state /
at 0
Internal input
fixed at 0
previous state
Document Number: 002-05675 Rev. *E
Page 49 of 99
CY9A1A0N Series
Power-on
reset or
low-voltage
detection
state
Run
mode or
Sleep
mode
state
Device
internal
reset
INITX
input
state
Timer mode,
RTC mode, or
Stop mode state
Deep Standby RTC mode Return from
or Deep Standby Stop Deep Standby
mode state
mode state
state
Function
group
Power
supply
unstable
Power
Power supply
stable
Power supply stable supply Power supply stable
stable
Power supply stable
INITX = 1
-
-
INITX = 0 INITX = 1 INITX = 1
INITX = 1
SPL = 0 SPL = 1
Input
INITX = 1
-
-
-
SPL = 0
SPL = 1
Input
enabled
-
Mode
input pin enabled
Input
Input
Input
Input
enabled enabled
Input
Input
enabled
Input enabled
enabled enabled
enabled
P
Maintain Maintain
previous previous
Maintain
previous
state
GPIO
selected disabled
Setting
Setting Setting
disabled disabled
Hi-Z / input
enabled
Hi-Z / input Maintain
enabled
previous state
state
state
Maintain Maintain
previous previous
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
CEC
Setting
Setting
disabled disabled
Setting
Maintain
previous state
enabled disabled
state
state
Resource
other than
above
GPIO
selected
Internal input
fixed at 0
GPIO selected
selected
Q
Hi-Z /
Hi-Z /
Input
enabled enabled
Hi-Z /
Input
Maintain Maintain
previous previous
Hi-Z /
Internal input
fixed at 0
Internal
input fixed
at 0
Output
Hi-Z
maintains
previous
state /
state
state
GPIO
selected
Maintain
previous state
Internal input
fixed at 0
Maintain Maintain
previous previous
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
CEC
Setting
Setting
disabled disabled
Setting
Maintain
previous state
enabled disabled
state
state
Hi-Z /
Internal
input fixed enabled
at 0
Hi-Z /
WKUP input
enabled
WKUP
enabled
Setting
WKUP input
Setting
Setting
disabled
disabled disabled
External
interrupt
enabled
Maintain
previous
GPIO selected
GPIO
state
R selected
selected
Maintain Maintain
previous previous
Internal input
fixed at 0
Resource
other than
above
state
state
Hi-Z /
Internal input
fixed at 0
selected
Hi-Z /
Hi-Z /
Input
enabled enabled
Hi-Z /
Input
Internal
input fixed
at 0
Output
Hi-Z
maintains
previous
state /
GPIO
selected
Maintain
previous state
Internal input
fixed at 0
Document Number: 002-05675 Rev. *E
Page 50 of 99
CY9A1A0N Series
Power-on
reset or
low-voltage
detection
state
Run
mode or
Sleep
mode
state
Device
internal
reset
INITX
input
state
Timer mode,
RTC mode, or
Stop mode state
Deep Standby RTC mode Return from
or Deep Standby Stop Deep Standby
mode state
mode state
state
Function
group
Power
supply
unstable
Power
Power supply
stable
Power supply stable supply Power supply stable
stable
Power supply stable
INITX = 1
-
-
INITX = 0 INITX = 1 INITX = 1
INITX = 1
SPL = 0 SPL = 1
INITX = 1
-
-
-
SPL = 0
SPL = 1
-
Analog
output
selected
Setting
disabled
Setting
disabled disabled
Setting
*3
*4
External
Maintain
previous
state
GPIO
selected
Internal input
fixed at 0
interrupt Setting
enabled disabled
selected
Setting
disabled disabled
Setting
GPIO selected
Maintain
previous
state
Hi-Z /
Resource
other than
above
S
Internal input
fixed at 0
Maintain
previous
state
selected
Hi-Z /
Hi-Z /
Input
enabled enabled
Hi-Z /
Input
Internal
input fixed
at 0
Output
Hi-Z
maintains
previous
state /
GPIO
selected
Maintain
previous state
Internal input
fixed at 0
Analog
Setting
output
Setting
disabled disabled
Setting
*3
*4
disabled
selected
GPIO
selected
Internal input
fixed at 0
GPIO selected
Resource
other than
above
Maintain
previous
state
Hi-Z /
Internal input
fixed at 0
T selected
Hi-Z /
Hi-Z /
Input
enabled enabled
Hi-Z /
Input
Maintain
previous
state
Internal
input fixed
at 0
Output
Hi-Z
maintains
previous
state /
GPIO
selected
Maintain
previous state
Internal input
fixed at 0
*1: Oscillation is stopped at Sub run mode, Low-speed CR Run mode, Sub Sleep mode, Low-speed CR Sleep mode,
Sub Timer mode, Low-speed CR Timer mode, RTC mode, Stop mode, Deep Standby RTC mode, and Deep Standby Stop
mode.
*2: Oscillation is stopped at Stop mode and Deep Standby Stop mode.
*3: Maintain previous state at Timer mode. GPIO selected Internal input fixed at 0 at RTC mode, Stop mode.
*4: Maintain previous state at Timer mode. Hi-Z/Internal input fixed at 0 at RTC mode, Stop mode.
Document Number: 002-05675 Rev. *E
Page 51 of 99
CY9A1A0N Series
12.Electrical Characteristics
12.1 Absolute Maximum Ratings
Rating
Parameter
Symbol
VCC
Unit
Remarks
Min
Max
Power supply voltage*1,*2
Analog power supply voltage*1,*3
Analog reference voltage*1,*3
VSS - 0.5
VSS - 0.5
VSS - 0.5
VSS + 6.5
VSS + 6.5
VSS + 6.5
V
V
V
AVCC
AVRH
VCC + 0.5
(≤ 6.5 V)
VSS + 6.5
AVCC + 0.5
(≤ 6.5 V)
VCC + 0.5
(≤ 6.5 V)
VSS - 0.5
VSS - 0.5
VSS - 0.5
V
V
V
Input voltage*1
VI
5V tolerant
Analog pin input voltage*1
Output voltage*1
VIA
VO
VSS - 0.5
V
L level maximum output current*4
L level average output current*5
L level total maximum output current
L level total average output current*6
H level maximum output current*4
H level average output current*5
H level total maximum output current
H level total average output current*6
Power consumption
IOL
-
10
4
mA
mA
mA
mA
mA
mA
mA
mA
mW
C
IOLAV
∑IOL
∑IOLAV
IOH
-
-
100
50
-
-
- 10
- 4
IOHAV
∑IOH
∑IOHAV
PD
-
-
- 100
- 50
400
+ 150
-
-
Storage temperature
TSTG
- 55
*1: These parameters are based on the condition that VSS = AVSS = 0 V.
*2: VCC must not drop below VSS - 0.5 V.
*3: Be careful not to exceed VCC + 0.5 V, for example, when the power is turned on.
*4: The maximum output current is defined as the value of the peak current flowing through any one of the corresponding pins.
*5: The average output current is defined as the average current value flowing through any one of the corresponding pins for a 100
ms period.
*6: The total average output current is defined as the average current value flowing through all of corresponding pins for a 100 ms.
WARNING:
−
Semiconductor devices may be permanently damaged by application of stress (including, without limitation, voltage, current or
temperature) in excess of absolute maximum ratings.
Do not exceed any of these ratings.
Document Number: 002-05675 Rev. *E
Page 52 of 99
CY9A1A0N Series
12.2 Recommended Operating Conditions
(VSS = AVSS = 0.0V)
Value
Parameter
Symbol
Conditions
Unit
Remarks
Min
Max
Power supply voltage
VCC
-
-
1.8
1.8
2.7
AVCC
1
5.5
5.5
V
V
Analog power supply voltage
AVCC
AVCC = VCC
AVCC ≥ 2.7 V
Analog reference voltage
AVRH
CS
-
-
AVCC
10
V
AVCC < 2.7 V
Smoothing capacitor
μF
For built-in Regulator *
LQD064,
LQG064,
Operating
Temperature LQJ080,
LQI100,
LQH080,
TA
-
- 40
+ 85
C
PQH100
*: See C Pin in Handling Devices for the smoothing capacitor.
WARNING:
−
The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All
of the device's electrical characteristics are warranted when the device is operated under these conditions.
Any use of semiconductor devices will be under their recommended operating condition.
Operation under any conditions other than these conditions may adversely affect reliability of device and could result in device
failure.
No warranty is made with respect to any use, operating conditions or combinations not represented on this data sheet. If you
are considering application under any conditions other than listed herein, please contact sales representatives beforehand.
Document Number: 002-05675 Rev. *E
Page 53 of 99
CY9A1A0N Series
12.3 DC Characteristics
12.3.1 Current Rating
(VCC = AVCC = 1.8 V to 5.5 V, VSS = AVSS = 0 V, TA = - 40C to + 85C)
Value
Pin
name
Parameter Symbol
Conditions
Unit
Remarks
Typ*3
Max*4
CPU: 20 MHz,
Peripheral: 20 MHz,
Flash memory 0 Wait,
FRWTR.RWT = 00,
FSYNDN.SD = 000
19
24
mA
*1, *5
PLL
Run mode
CPU: 20 MHz,
Peripheral: clock stopped,
NOP operation
CPU/Peripheral: 4 MHz*2
Flash memory 0 Wait
FRWTR.RWT = 00
9.5
4.5
12.5
5
mA
mA
*1, *5
*1
High-spee
d
CR
ICC
Run mode
FSYNDN.SD = 000
CPU/Peripheral: 32 kHz,
Flash memory 0 Wait,
FRWTR.RWT = 00,
FSYNDN.SD = 000
Sub
Run mode
0.25
0.55
mA
*1, *6
Power
supply
current
CPU/Peripheral: 100 kHz,
Flash memory 0 Wait,
FRWTR.RWT = 00,
Low-speed
CR
Run mode
VCC
0.3
8
0.95
10.5
mA
mA
*1
FSYNDN.SD = 000
PLL
Sleep
mode
Peripheral: 20 MHz
Peripheral: 4 MHz*2
*1, *5
High-spee
d
CR
2
2.5
mA
*1
Sleep
mode
ICCS
Sub
Sleep
mode
Peripheral: 32 kHz
Peripheral: 100 kHz
0.2
0.45
0.65
mA
mA
*1, *6
*1
Low-speed
CR
Sleep
0.25
mode
*1: When all ports are fixed.
*2: When setting it to 4 MHz by trimming.
*3: TA=+25°C, VCC=3.3 V
*4: TA=+85°C, VCC=5.5 V
*5: When using the crystal oscillator of 4 MHz(Including the current consumption of the oscillation circuit)
*6: When using the crystal oscillator of 32 kHz(Including the current consumption of the oscillation circuit)
Document Number: 002-05675 Rev. *E
Page 54 of 99
CY9A1A0N Series
Value
Pin
name
Parameter Symbol
Conditions
Unit
Remarks
Typ*2
Max*3
TA = + 25°C,
When LVD is off
0.9
3.3
mA *1, *4
mA *1, *4
Main
Timer mode
TA = + 85°C,
When LVD is off
1.5
7.5
16
1.5
6
3.5
60
150
6.5
79
5
ICCT
TA = + 25°C,
When LVD is off
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
*1, *5
*1, *5
*1, *5
*1, *5
*1
Sub
Timer mode
TA = + 85°C,
When LVD is off
TA = + 25C,
When LVD is off
ICCR
RTC mode
Stop mode
TA = + 85C,
When LVD is off
Power
supply
current
VCC
TA = + 25C,
When LVD is off
0.6
4.2
1.3
3
ICCH
TA = + 85C,
When LVD is off
77
4.5
22
3
*1
TA = + 25C,
When LVD is off
*1, *5
*1, *5
*1
Deep
ICCRD
Standby
RTC mode
TA = + 85C,
When LVD is off
TA = + 25C,
When LVD is off
0.4
1.4
Deep
ICCHD
Standby
Stop mode
TA = + 85C,
When LVD is off
20
*1
*1: When all ports are fixed.
*2: VCC=3.3 V
*3: VCC=5.5 V
*4: When using the crystal oscillator of 4 MHz(Including the current consumption of the oscillation circuit)
*5: When using the crystal oscillator of 32 kHz(Including the current consumption of the oscillation circuit)
Document Number: 002-05675 Rev. *E
Page 55 of 99
CY9A1A0N Series
Low Voltage Detection Current
Pin
(VCC = AVCC = 1.8 V to 5.5 V, VSS = AVSS = 0 V, TA = - 40C to + 85C)
Value
Parameter
Symbol
Conditions
Unit
Remarks
name
Typ*
Max
For occurrence of reset or for
occurrence of interrupt in normal
mode operation
10
20
μA
Low-voltage
When not detected
When not detected
detection circuit
(LVD) power
supply current
For occurrence of reset and for
occurrence of interrupt in normal
mode operation
ICCLVD
VCC
14
30
2
μA
μA
For occurrence of interrupt in
low-power mode operation
0.3
*: When VCC = 3.3 V
Flash Memory Current
(VCC = 1.8 V to 5.5 V, VSS = 0 V, TA = - 40°C to + 85°C)
Value
Pin
name
Parameter
Symbol
Conditions
Unit
Remarks
Typ
Max
Flash memory
write/erase
current
ICCFLASH
VCC
At Write/Erase
10.8
11.9
mA
A/D Converter Current
(VCC = AVCC = 1.8 V to 5.5 V, VSS = AVSS = 0 V, TA = - 40°C to + 85°C)
Value
Pin
Parameter
Symbol
Conditions
Unit
Remarks
name
Typ
1.4
0.1
Max
2.5
At 1unit
operation
mA
μA
Power supply
current
ICCAD
AVCC
AVRH
At stop
0.35
At 1unit
operation
AVRH=5.5 V
0.5
0.1
1.5
0.3
mA
μA
Reference power
supply current
ICCAVRH
At stop
D/A Converter Current
(VCC = AVCC = 1.8 V to 5.5 V, VSS = AVSS = 0 V, TA = - 40°C to + 85°C)
Value
Pin
name
Parameter
Symbol
Conditions
Unit
Remarks
Typ
Max
At D/A 1ch.
operation
314
440
μA
*1, *2
AVCC=3.3 V
IDDA
Power supply
current
AVCC
At D/A 1ch.
operation
476
670
1.0
μA
μA
*1, *2
*1
AVCC=5.0 V
IDSA
At D/A stop
-
*1: No-load
*2: Generates the max current by the CODE about 0x200
Document Number: 002-05675 Rev. *E
Page 56 of 99
CY9A1A0N Series
12.3.2 Pin Characteristics
(VCC = AVCC = 1.8V to 5.5V, VSS = AVSS = 0V, TA = - 40C to + 85C)
Value
Parameter
Symbol
Pin name
Conditions
Unit
Remarks
Min
Typ
Max
MD0, MD1,
PE0, PE2,
PE3, P46, P47,
P3A, P3B,
P3C,
-
VCC × 0.8
-
VCC + 0.3
V
P3D, P3E, P3F,
INITX
H level input
voltage
(hysteresis
input)
VIHS
P0A, P0B,
P0C, P4C,
P60,
-
-
VCC × 0.7
VCC × 0.7
-
-
VSS + 5.5
VCC + 0.3
V
V
5V tolerant
P80, P81, P82
CMOS
hysteresis
input pins other
than the above
MD0, MD1,
PE0, PE2,
PE3,
P46, P47,
INITX
-
-
VSS - 0.3
-
VCC × 0.2
V
L level input
voltage
(hysteresis
input)
VILS
CMOS
hysteresis
input pins other
than the above
VSS - 0.3
VCC - 0.5
-
-
VCC × 0.3
V
V
VCC ≥ 4.5 V,
IOH = - 4 mA
H level
output voltage
VOH
Pxx
VCC
VCC < 4.5 V,
IOH = - 1 mA
VCC ≥ 4.5 V,
IOL = 4 mA
L level
output voltage
VOL
Pxx
VSS
-
0.4
V
VCC < 4.5 V,
IOL = 2 mA
-
-
- 5
-
-
+ 5
VCC = AVCC
AVRH = VSS
= AVSS = 0.0
V
=
Input leak
current
IIL
μA
CEC0,
CEC1
-
+ 1.8
VCC ≥ 4.5 V
25
40
50
100
400
Pull-up resistor
value
RPU
Pull-up pin
kΩ
pF
100
VCC 4.5 V
Other than
VCC, VSS,
AVCC, AVSS,
AVRH
Input
capacitance
CIN
-
-
5
15
Document Number: 002-05675 Rev. *E
Page 57 of 99
CY9A1A0N Series
12.4 AC Characteristics
12.4.1 Main Clock Input Characteristics
(VCC = 1.8V to 5.5V, VSS = 0V, TA = - 40C to + 85C)
Value
Pin
name
Parameter
Symbol
Conditions
Unit
Remarks
Min
Max
VCC ≥ 2.0 V
VCC 2.0 V
VCC ≥ 4.5 V
VCC 4.5 V
VCC ≥ 4.5 V
VCC 4.5 V
4
20
4
MHz
MHz
MHz
MHz
ns
When crystal oscillator is
connected
4
4
Input frequency
Input clock cycle
fCH
20
When using external
clock
4
16
X0,
X1
50
62.5
250
250
When using external
clock
tCYLH
ns
PWH/tCYLH,
PWL/tCYLH
When using external
clock
Input clock pulse
width
-
45
55
5
%
tCF
tCR
,
When using external
clock
Input clock rising
time and falling time
-
-
ns
fCM
fCC
-
-
-
-
-
-
-
-
-
-
-
-
-
-
20
20
20
20
20
-
MHz
MHz
MHz
MHz
MHz
ns
Master clock
Base clock (HCLK/FCLK)
APB0 bus clock*2
APB1 bus clock*2
Internal operating
clock*1
frequency
fCP0
fCP1
fCP2
-
-
-
APB2 bus clock*2
50
Base clock (HCLK/FCLK)
tCYCC
Internal operating
clock*1
cycle time
-
-
-
-
-
-
50
50
50
-
-
-
ns
ns
ns
APB0 bus clock*2
APB1 bus clock*2
APB2 bus clock*2
tCYCP0
tCYCP1
tCYCP2
*1: For more information about each internal operating clock, see Chapter 2-1: Clock in FM3 Family Peripheral Manual.
*2: For about each APB bus which each peripheral is connected to, see Block Diagram in this data sheet.
X0
Document Number: 002-05675 Rev. *E
Page 58 of 99
CY9A1A0N Series
12.4.2 Sub Clock Input Characteristics
(VCC = 1.8V to 5.5V, VSS = 0V, TA = - 40C to + 85C)
Value
Typ
Pin
name
Parameter
Symbol
Conditions
Unit
Remarks
Min
Max
When crystal oscillator is
connected
-
-
32.768
-
kHz
Input frequency
Input clock cycle
fCL
-
-
32
10
-
-
100
kHz When using external clock
X0A,
X1A
tCYLL
31.25
μs
When using external clock
PWH/tCYLL,
PWL/tCYLL
Input clock pulse
width
-
45
-
55
%
When using external clock
X0A
12.4.3 Built-in CR Oscillation Characteristics
Built-in High-speed CR
(VCC = 1.8V to 5.5V, VSS = 0V, TA = - 40C to + 85C)
Value
Parameter
Symbol
Conditions
Unit
Remarks
Min
3.92
3.8
Typ
4
Max
4.08
4.2
TA = + 25C
When trimming*1
VCC
2.2 V
≥
4
TA = - 40C to + 85C
MHz
When not
trimming
2.3
-
7.03
TA = - 40C to + 85C
Clock frequency
fCRH
3.4
4
4
4.6
TA = + 25C
When trimming*1
VCC
2.2 V
<
3.16
4.84
TA = - 40C to + 85C
MHz
μs
When not
trimming
2.3
-
-
-
7.03
10
TA = - 40C to + 85C
Frequency
stabilization time
tCRWT
-
*2
*1: In the case of using the values in CR trimming area of Flash memory at shipment for frequency trimming.
*2: This is the time to stabilize the frequency of High-speed CR clock after setting trimming value.
This period is able to use High-speed CR clock as source clock.
Document Number: 002-05675 Rev. *E
Page 59 of 99
CY9A1A0N Series
Built-in Low-speed CR
(VCC = 1.8V to 5.5V, VSS = 0V, TA = - 40C to + 85C)
Value
Typ
Parameter
Symbol
Conditions
Unit
Remarks
Min
Max
Clock frequency
fCRL
-
50
100
150
kHz
12.4.4 Operating Conditions of Main PLL (In the case of using main clock for input of PLL)
(VCC = 1.8V to 5.5V, VSS = 0V, TA = - 40C to + 85C)
Value
Typ
Parameter
Symbol
Unit
Remarks
Min
Max
PLL oscillation stabilization wait time*1
(LOCK UP time)
tLOCK
200
-
-
μs
PLL input clock frequency
PLL multiplication rate
fPLLI
-
fPLLO
fCLKPLL
4
1
-
-
-
-
20
5
MHz
multiplier
MHz
PLL macro oscillation clock frequency
Main PLL clock frequency*2
10
-
20
20
MHz
*1: Time from when the PLL starts operating until the oscillation stabilizes.
*2: For more information about Main PLL clock (CLKPLL), see Chapter 2-1: Clock in FM3 Family Peripheral Manual.
12.4.5 Operating Conditions of Main PLL (In the case of using the built-in High-speed CR for the input clock
of the Main PLL)
(VCC = 2.2V to 5.5V, VSS = 0V, TA = - 40C to + 85C)
Value
Typ
Parameter
Symbol
Unit
Remarks
Min
Max
PLL oscillation stabilization wait time*1
(LOCK UP time)
tLOCK
200
-
-
μs
PLL input clock frequency
PLL multiplication rate
fPLLI
-
fPLLO
fCLKPLL
3.8
3
4
-
4.2
4
MHz
multiplier
MHz
PLL macro oscillation clock frequency
Main PLL clock frequency*2
11.4
-
-
16.8
16.8
-
MHz
*1: Time from when the PLL starts operating until the oscillation stabilizes.
*2: For more information about Main PLL clock (CLKPLL), see Chapter 2-1: Clock in FM3 Family Peripheral Manual.
Note:
−
Make sure to input to the Main PLL source clock, the High-speed CR clock (CLKHC) that the frequency has been trimmed.
When setting PLL multiple rate, please take the accuracy of the built-in High-speed CR clock into account and prevent the
master clock from exceeding the maximum frequency.
Document Number: 002-05675 Rev. *E
Page 60 of 99
CY9A1A0N Series
Main PLL connection
Main PLL
clock
PLL input
clock
PLL macro
Main clock (CLKMO)
oscillation clock
(CLKPLL)
K
M
Main
PLL
High-speed CR clock (CLKHC)
divider
divider
N
divider
12.4.6 Reset Input Characteristics
(VCC = 1.8V to 5.5V, VSS = 0V, TA = - 40C to + 85C)
Value
Pin
Parameter
Symbol
Conditions
Unit
Remarks
name
Min
500
1.5
Max
-
-
-
ns
ms
ms
Reset input time
tINITX
INITX
-
When RTC mode or Stop mode
When Deep Standby mode
1.5
12.4.7 Power-on Reset Timing
(VCC = 1.8V to 5.5V, VSS = 0V, TA = - 40C to + 85C)
Value
Typ
Pin
Parameter
Symbol
dV/dt
Unit
Remarks
name
Min
Max
Power supply rising time
0.1
1
-
-
V/ms
ms
V
Power supply shut down time tOFF
-
-
Reset release voltage
Reset detection voltage
VDETH
VDETL
1.44
1.39
1.60
1.55
1.76
1.71
When voltage rises
VCC
V
When voltage drops
dV/dt ≥ 0.1mV/μs
dV/dt ≥ -0.04mV/μs
Time until releasing
Power-on reset
tPRT
0.46
-
-
11.4
0.4
ms
ms
Reset detection delay time
tOFFD
-
Document Number: 002-05675 Rev. *E
Page 61 of 99
CY9A1A0N Series
VDETH
VDETL
VCC
dV
dt
0.2V
tOFF
0.2V
tPRT
tOFFD
Reset active
Internal reset
Reset active
Release
start
CPU Operation
12.4.8 Base Timer Input Timing
Timer input timing
(VCC = 1.8V to 5.5V, VSS = 0V, TA = - 40C to + 85C)
Value
Parameter
Symbol
Pin name
Conditions
Unit
Remarks
Min
Max
TIOAn/TIOBn
(when using as
ECK, TIN)
tTIWH
tTIWL
,
Input pulse width
-
2tCYCP
-
ns
tTIWH
tTIWL
ECK
TIN
VIHS
VIHS
VILS
VILS
Document Number: 002-05675 Rev. *E
Page 62 of 99
CY9A1A0N Series
Trigger input timing
(VCC = 1.8V to 5.5V, VSS = 0V, TA = - 40C to + 85C)
Value
Parameter
Symbol
Pin name
Conditions
Unit
Remarks
Min
Max
TIOAn/TIOBn
(when using
as TGIN)
tTRGH
tTRGL
,
Input pulse width
-
2tCYCP
-
ns
tTRGH
tTRGL
VIHS
VIHS
TGIN
VILS
VILS
Note:
−
tCYCP indicates the APB bus clock cycle time.
About the APB bus number which the Base Timer is connected to, see Block Diagram in this data sheet.
Document Number: 002-05675 Rev. *E
Page 63 of 99
CY9A1A0N Series
12.4.9 CSIO/UART Timing
CSIO (SPI = 0, SCINV = 0)
(VCC = 1.8V to 5.5V, VSS = 0V, TA = - 40C to + 85C)
2.7 V ≤
VCC 2.7 V
VCC ≥ 4.5 V
Pin
VCC 4.5 V
Parameter
Baud rate
Symbol
Conditions
Unit
name
Min
Max
Min
Max
Min
Max
-
-
-
-
5
-
5
-
5
Mbps
ns
Serial clock cycle
time
tSCYC
SCKx
4tCYCP
-
4tCYCP
-
4tCYCP
-
SCKx,
SOTx
SCK SOT
tSLOVI
tIVSHI
tSHIXI
tSLSH
tSHSL
tSLOVE
tIVSHE
tSHIXE
-40
+40
-30
+30
-20
+20
ns
ns
ns
ns
ns
ns
ns
ns
delay time
Master mode
SCKx,
SINx
SIN SCK
setup time
75
-
-
50
-
-
30
-
-
SCKx,
SINx
SCK SIN
hold time
0
0
0
Serial clock L
pulse width
SCKx
SCKx
2tCYCP - 10
-
2tCYCP - 10
-
2tCYCP - 10
-
Serial clock H
pulse width
tCYCP + 10
-
tCYCP + 10
-
tCYCP + 10
-
SCKx,
SOTx
SCK SOT
delay time
-
75
-
-
50
-
-
30
-
Slave mode
SCKx,
SINx
SIN SCK
setup time
10
20
10
20
10
20
SCKx,
SINx
SCK SIN
hold time
-
-
-
SCK falling time
SCK rising time
tF
SCKx
SCKx
-
-
5
5
-
-
5
5
-
-
5
5
ns
ns
tR
Notes:
−
The above characteristics apply to clock synchronous mode.
−
tCYCP indicates the APB bus clock cycle time.
About the APB bus number which Multi-function serial is connected to, see Block Diagram in this data sheet.
−
−
These characteristics only guarantee the same relocate port number.
For example, the combination of SCKx_0 and SOTx_1 is not guaranteed.
When the external load capacitance CL = 50 pF.
Document Number: 002-05675 Rev. *E
Page 64 of 99
CY9A1A0N Series
tSCYC
VOH
VOH
SCK
VOL
tSHOVI
VOH
VOL
SOT
SIN
tIVSLI
VIH
VIL
tSLIXI
VIH
VIL
Master mode
tSHSL
tSLSH
VIH
VIH
tF
SCK
VIL
VIL
tR
VIL
tSHOVE
VOH
VOL
SOT
SIN
tIVSLE
tSLIXE
VIH
VIL
VIH
VIL
Slave mode
Document Number: 002-05675 Rev. *E
Page 65 of 99
CY9A1A0N Series
CSIO (SPI = 0, SCINV = 1)
(VCC = 1.8V to 5.5V, VSS = 0V, TA = - 40C to + 85C)
2.7 V ≤
VCC 2.7 V
VCC ≥ 4.5 V
Pin
VCC 4.5 V
Parameter
Baud rate
Symbol
Conditions
Unit
name
Min
Max
Min
Max
Min
Max
-
-
-
-
5
-
5
-
5
Mbps
ns
Serial clock cycle
time
tSCYC
SCKx
4tCYCP
-
4tCYCP
-
4tCYCP
-
SCKx,
SOTx
SCK SOT
tSHOVI
tIVSLI
-40
+40
-30
+30
-20
+20
ns
ns
ns
ns
ns
ns
ns
ns
delay time
Master mode
SCKx,
SINx
SIN SCK
setup time
75
-
-
50
-
-
30
-
-
SCKx,
SINx
SCK SIN
hold time
tSLIXI
0
0
0
Serial clock L
pulse width
tSLSH
tSHSL
tSHOVE
tIVSLE
tSLIXE
SCKx
SCKx
2tCYCP - 10
-
2tCYCP - 10
-
2tCYCP - 10
-
Serial clock H
pulse width
tCYCP + 10
-
tCYCP + 10
-
tCYCP + 10
-
SCKx,
SOTx
SCK SOT
delay time
-
75
-
-
50
-
-
30
-
Slave mode
SCKx,
SINx
SIN SCK
setup time
10
20
10
20
10
20
SCKx,
SINx
SCK SIN
hold time
-
-
-
SCK falling time
SCK rising time
tF
SCKx
SCKx
-
-
5
5
-
-
5
5
-
-
5
5
ns
ns
tR
Notes:
−
The above characteristics apply to clock synchronous mode.
−
tCYCP indicates the APB bus clock cycle time.
About the APB bus number which Multi-function serial is connected to, see Block Diagram in this data sheet.
−
−
These characteristics only guarantee the same relocate port number.
For example, the combination of SCKx_0 and SOTx_1 is not guaranteed.
When the external load capacitance CL = 50 pF.
Document Number: 002-05675 Rev. *E
Page 66 of 99
CY9A1A0N Series
tSCYC
VOH
VOH
SCK
VOL
tSHOVI
VOH
VOL
SOT
SIN
tIVSLI
VIH
VIL
tSLIXI
VIH
VIL
Master mode
tSHSL
tSLSH
VIH
VIH
tF
SCK
VIL
VIL
tR
VIL
tSHOVE
VOH
VOL
SOT
SIN
tIVSLE
tSLIXE
VIH
VIL
VIH
VIL
Slave mode
Document Number: 002-05675 Rev. *E
Page 67 of 99
CY9A1A0N Series
CSIO (SPI = 1, SCINV = 0)
(VCC = 1.8V to 5.5V, VSS = 0V, TA = - 40C to + 85C)
2.7 V ≤
VCC 2.7 V
Min Max
VCC ≥ 4.5 V
Pin
VCC 4.5 V
Parameter
Baud rate
Symbol
Conditions
Unit
name
Min
Max
Min
Max
-
-
-
-
5
-
5
-
5
Mbps
ns
Serial clock
cycle time
tSCYC
SCKx
4tCYCP
-
4tCYCP
-
4tCYCP
-
SCKx,
SOTx
SCK SOT
tSHOVI
tIVSLI
-40
+40
-30
+30
-20
+20
ns
ns
ns
ns
ns
ns
ns
ns
ns
delay time
SCKx,
SINx
SIN SCK
setup time
Master
mode
75
-
-
50
-
-
30
-
-
SCKx,
SINx
SCK SIN
hold time
tSLIXI
0
2tCYCP - 30
2tCYCP - 10
tCYCP + 10
-
0
2tCYCP - 30
2tCYCP - 10
tCYCP + 10
-
0
SCKx,
SOTx
SOT SCK
delay time
tSOVLI
tSLSH
tSHSL
tSHOVE
tIVSLE
tSLIXE
-
-
2tCYCP - 30
-
Serial clock L
pulse width
SCKx
SCKx
-
-
2tCYCP - 10
-
Serial clock H
pulse width
-
-
tCYCP + 10
-
SCKx,
SOTx
SCK SOT
delay time
75
-
50
-
-
30
-
Slave mode
SCKx,
SINx
SIN SCK
setup time
10
10
10
20
SCKx,
SINx
SCK SIN
hold time
20
-
20
-
-
SCK falling time tF
SCK rising time tR
SCKx
SCKx
-
-
5
5
-
-
5
5
-
-
5
5
ns
ns
Notes:
−
The above characteristics apply to clock synchronous mode.
−
tCYCP indicates the APB bus clock cycle time.
About the APB bus number which Multi-function serial is connected to, see Block Diagram in this data sheet.
−
−
These characteristics only guarantee the same relocate port number.
For example, the combination of SCKx_0 and SOTx_1 is not guaranteed.
When the external load capacitance CL = 50 pF.
Document Number: 002-05675 Rev. *E
Page 68 of 99
CY9A1A0N Series
tSCYC
VOH
SCK
VOL
VOL
tSHOVI
tSOVLI
VOH
VOL
VOH
VOL
SOT
SIN
tIVSLI
tSLIXI
VIH
VIL
VIH
VIL
Master mode
tSLSH
tSHSL
VIH
tF
VIH
VIH
SCK
SOT
SIN
VIL
VIL
tR
tSHOVE
*
VOH
VOL
VOH
VOL
tIVSLE
tSLIXE
VIH
VIL
VIH
VIL
Slave mode
*: Changes when writing to TDR register
Document Number: 002-05675 Rev. *E
Page 69 of 99
CY9A1A0N Series
CSIO (SPI = 1, SCINV = 1)
(VCC = 1.8V to 5.5V, VSS = 0V, TA = - 40C to + 85C)
2.7 V ≤
VCC 2.7 V
Min Max
VCC ≥ 4.5 V
Pin
VCC 4.5 V
Parameter
Baud rate
Symbol
Conditions
Unit
name
Min
Max
Min
Max
-
-
-
-
5
-
5
-
5
Mbps
ns
Serial clock
cycle time
tSCYC
SCKx
4tCYCP
-
4tCYCP
-
4tCYCP
-
SCKx,
SOTx
SCK SOT
delay time
tSLOVI
-40
+40
-30
+30
-20
+20
ns
Master
mode
SCKx,
SINx
SIN SCK
tIVSHI
tSHIXI
tSOVHI
tSLSH
tSHSL
tSLOVE
tIVSHE
tSHIXE
75
-
-
50
-
-
30
-
-
ns
ns
ns
ns
ns
ns
ns
ns
setup time
SCKx,
SINx
SCK SIN
hold time
0
2tCYCP - 30
2tCYCP - 10
tCYCP + 10
-
0
2tCYCP - 30
2tCYCP - 10
tCYCP + 10
-
0
SCKx,
SOTx
SOT SCK
delay time
-
-
2tCYCP - 30
-
Serial clock L
pulse width
SCKx
SCKx
-
-
2tCYCP - 10
-
Serial clock H
pulse width
-
-
tCYCP + 10
-
SCKx,
SOTx
SCK SOT
delay time
75
-
50
-
-
30
-
Slave mode
SCKx,
SINx
SIN SCK
setup time
10
10
10
20
SCKx,
SINx
SCK SIN
hold time
20
-
20
-
-
SCK falling time tF
SCK rising time tR
SCKx
SCKx
-
-
5
5
-
-
5
5
-
-
5
5
ns
ns
Notes:
−
The above characteristics apply to clock synchronous mode.
−
tCYCP indicates the APB bus clock cycle time.
About the APB bus number which Multi-function serial is connected to, see Block Diagram in this data sheet.
−
−
These characteristics only guarantee the same relocate port number.
For example, the combination of SCKx_0 and SOTx_1 is not guaranteed.
When the external load capacitance CL = 50 pF.
Document Number: 002-05675 Rev. *E
Page 70 of 99
CY9A1A0N Series
tSCYC
VOH
VOH
SCK
VOL
tSOVHI
tSLOVI
VOH
VOL
VOH
VOL
SOT
SIN
tSHIXI
tIVSHI
VIH
VIL
VIH
VIL
Master mode
tR
tF
tSHSL
tSLSH
VIH
VIH
SCK
VIL
VIL
VIL
tSLOVE
VOH
VOL
VOH
VOL
SOT
SIN
tIVSHE
tSHIXE
VIH
VIL
VIH
VIL
Slave mode
UART external clock input (EXT = 1)
(VCC = 1.8V to 5.5V, VSS = 0V, TA = - 40C to + 85C)
Value
Parameter
Symbol Conditions
Unit
Remarks
Min
Max
Serial clock L pulse width
Serial clock H pulse width
SCK falling time
tSLSH
tCYCP + 10
-
-
ns
ns
ns
ns
tSHSL
tCYCP + 10
CL = 50 pF
tF
-
-
5
5
SCK rising time
tR
tF
tR
tSHSL
tSLSH
SCK
VIH
VIH
VIH
IL
IL
IL
V
V
V
Document Number: 002-05675 Rev. *E
Page 71 of 99
CY9A1A0N Series
12.4.10 External Input Timing
(VCC = 1.8V to 5.5V, VSS = 0V, TA = - 40C to + 85C)
Value
Min
Parameter
Symbol
Pin name
ADTG
Conditions
Unit
Remarks
Max
A/D converter trigger input
1
-
2tCYCP
*
-
ns
FRCKx
ICxx
Free-run timer input clock
Input capture
tINH
tINL
,
1
1
DTTIxX
IGTRG
-
2tCYCP
2tCYCP
*
*
-
-
-
-
-
ns
ns
ns
ns
ns
Waveform generator
PPG IGBT mode
Input pulse width
-
*2
*3
*4
2tCYCP + 100*1
INTxx,
NMIX
External interrupt,
NMI
500
500
WKUPx
Deep standby wake up
*1: tCYCP indicates the APB bus clock cycle time.
About the APB bus number which the A/D converter, Multi-function Timer, PPG, External interrupt, Deep Standby mode
Controller are connected to, see Block Diagram in this data sheet.
*2: When in Run mode, in Sleep mode.
*3: When in Timer mode, in RTC mode, in Stop mode.
*4: When in Deep Standby RTC mode, in Deep Standby Stop mode.
Document Number: 002-05675 Rev. *E
Page 72 of 99
CY9A1A0N Series
12.4.11 I2C Timing
(VCC = 1.8V to 5.5V, VSS = 0V, TA = - 40C to + 85C)
Standard-mode
Fast-mode
Parameter
Symbol
Conditions
Unit
Remarks
Min
Max
Min
Max
SCL clock frequency
fSCL
0
100
0
400
kHz
(Repeated) START condition
hold time
tHDSTA
4.0
-
0.6
-
μs
SDA SCL
SCL clock L width
SCL clock H width
tLOW
tHIGH
4.7
4.0
-
-
1.3
0.6
-
-
μs
μs
(Repeated) START condition
setup time
tSUSTA
4.7
-
0.6
-
μs
SCL SDA
Data hold time
CL = 50 pF,
R = (VP/IOL)*1
tHDDAT
tSUDAT
tSUSTO
0
3.45*2
0
0.9*3
μs
ns
μs
SCL SDA
Data setup time
SDA SCL
STOP condition setup time
SCL SDA
250
4.0
-
-
100
0.6
-
-
Bus free time between
STOP condition and
START condition
tBUF
tSP
4.7
-
-
1.3
-
-
μs
ns
4
4
Noise filter
-
2 tCYCP
*
2 tCYCP*
*1: R and CL represent the pull-up resistor and load capacitance of the SCL and SDA lines, respectively.
VP indicates the power supply voltage of the pull-up resistor and IOL indicates VOL guaranteed current.
*2: The maximum tHDDAT must satisfy that it does not extend at least L period (tLOW) of device's SCL signal.
*3: A Fast-mode I2C bus device can be used on a Standard-mode I2C bus system as long as the device satisfies the requirement of
tSUDAT ≥ 250 ns.
*4: tCYCP is the APB bus clock cycle time.
About the APB bus number which I2C is connected to, see Block Diagram in this data sheet.
To use Standard-mode, set the APB bus clock at 2 MHz or more.
To use Fast-mode, set the APB bus clock at 8 MHz or more.
SDA
SCL
Document Number: 002-05675 Rev. *E
Page 73 of 99
CY9A1A0N Series
12.4.12 JTAG Timing
(VCC = 1.8V to 5.5V, VSS = 0V, TA = - 40C to + 85C)
Value
Parameter
Symbol
tJTAGS
tJTAGH
Pin name
Conditions
VCC ≥ 4.5 V
Unit
Remarks
Min
Max
TCK,
TMS,TDI
TMS,TDI setup
time
15
-
ns
VCC 4.5 V
VCC ≥ 4.5 V
VCC 4.5 V
VCC ≥ 4.5 V
TCK,
TMS,TDI
TMS,TDI hold
time
15
-
ns
ns
-
-
-
30
45
60
TCK,
TDO
TDO delay time tJTAGD
2.7 V ≤VCC 4.5 V
VCC 2.7 V
Note:
−
When the external load capacitance CL = 50 pF.
TCK
TMS/TDI
TDO
Document Number: 002-05675 Rev. *E
Page 74 of 99
CY9A1A0N Series
12.5 12-bit A/D Converter
Electrical Characteristics for the A/D Converter
(VCC = AVCC = 1.8V to 5.5V, VSS = AVSS = 0V, TA = - 40C to + 85C)
Value
Typ
-
Pin
name
Parameter
Resolution
Symbol
Unit
Remarks
Min
-
Max
12
-
-
-
bit
-
± 2.5
± 3.5
± 1.8
± 2.7
± 9
± 3.0
LSB AVCC ≥ 2.7 V
LSB AVCC < 2.7 V
LSB AVCC ≥ 2.7 V
LSB AVCC < 2.7 V
mV
Integral Nonlinearity
INL
-
± 4.0
-
± 1.9
Differential Nonlinearity
Zero transition voltage
DNL
VZT
-
-
± 2.9
ANxx
ANxx
-
± 20
Full-scale transition voltage VFST
-
AVRH ± 9
AVRH ± 20
mV
1.0
4.0
0.3
1.2
50
200
AVCC ≥ 2.7 V
μs
Conversion time*1
-
-
-
-
-
-
-
-
10
AVCC < 2.7 V
AVCC ≥ 2.7 V
μs
Sampling time*2
tS
AVCC < 2.7 V
AVCC ≥ 2.7 V
ns
Compare clock cycle*3
tCCK
1000
1
AVCC < 2.7 V
Period of operation enable
state transitions
tSTT
-
-
-
-
-
-
μs
Analog input capacity
Analog input resistor
Interchannel disparity
CAIN
15
0.9
1.6
4.0
4
pF
AVCC ≥ 4.5 V
RAIN
-
-
-
kΩ
2.7 V ≤ AVCC < 4.5 V
AVCC < 2.7 V
-
-
-
-
-
-
-
-
-
-
-
LSB
μA
V
Analog port input leak
current
ANxx
ANxx
AVRH
0.3
Analog input voltage
AVSS
2.7
AVRH
AVCC
AVCC ≥ 2.7 V
AVCC < 2.7 V
Reference voltage
V
AVCC
*1: The conversion time is the value of sampling time (tS) + compare time (tC).
The condition of the minimum conversion time is the following.
AVCC ≥ 2.7 V, HCLK=20 MHz
AVCC < 2.7 V, HCLK=20 MHz
sampling time: 0.3 μs, compare time: 0.7 μs
sampling time: 1.2 μs, compare time: 2.8 μs
Ensure that it satisfies the value of the sampling time (tS) and compare clock cycle (tCCK).
For setting*4 of the sampling time and compare clock cycle, see Chapter 1-1: A/D Converter in FM3 Family
Peripheral Manual Analog Macro Part.
The register settings of the A/D Converter are reflected in the operation according to the APB bus clock timing.
For the number of the APB bus to which the A/D Converter is connected, see Block Diagram.
The Base clock (HCLK) is used to generate the sampling time and the compare clock cycle.
*2: A necessary sampling time changes by external impedance.
Ensure to set the sampling time to satisfy (Equation 1).
*3: The compare time (tC) is the value of (Equation 2).
Document Number: 002-05675 Rev. *E
Page 75 of 99
CY9A1A0N Series
ANxx
Analog input pin
Comparator
REXT
RAIN
Analog
Signal source
CAIN
(Equation 1) tS ≥ ( RAIN + REXT ) × CAIN × 9
tS:
Sampling time
RAIN
:
input resistor of A/D = 0.9 kΩ at 4.5 V ≤ AVCC ≤ 5.5 V
input resistor of A/D = 1.6 kΩ at 2.7 V ≤ AVCC < 4.5 V
input resistor of A/D = 4.0 kΩ at 1.8 V ≤ AVCC < 2.7 V
input capacity of A/D = 15 pF at 1.8 V ≤ AVCC ≤ 5.5 V
Output impedance of external circuit
CAIN
:
REXT
:
(Equation 2) tC = tCCK × 14
tC:
Compare time
tCCK
:
Compare clock cycle
Document Number: 002-05675 Rev. *E
Page 76 of 99
CY9A1A0N Series
Definition of 12-bit A/D Converter Terms
• Resolution:
• Integral Nonlinearity:
Analog variation that is recognized by an A/D converter.
Deviation of the line between the zero-transition point
(0b000000000000←→0b000000000001) and the full-scale transition point
(0b111111111110←→0b111111111111) from the actual conversion characteristics.
• Differential Nonlinearity:
Deviation from the ideal value of the input voltage that is required to change
the output code by 1 LSB.
Integral Nonlinearity
Differential Nonlinearity
0xFFF
Actual conversion
Actual conversion
characteristics
0xFFE
0xFFD
0x(N+1)
0xN
characteristics
{1 LSB(N-1) + VZT}
VFST
Ideal characteristics
(Actually-
measured
value)
VNT
0x004
(Actual
value)
V(N+1)T
(Actually-measured
0x(N-1)
0x(N-2)
0x003
0x002
Actual conversion
characteristics
Ideal characteristics
value)
VNT
(Asured
value)
0x001
lly-measured value)
VZT
Actual conversion characteristics
AVSS
AVRH
AVSS
AVRH
Analog input
Analog input
VNT - {1LSB × (N - 1) + VZT}
Integral Nonlinearity of digital output N =
Differential Nonlinearity of digital output N =
[LSB]
1LSB
V(N + 1) T - VNT
- 1 [LSB]
1LSB
VFST - VZT
1LSB =
4094
N:
A/D converter digital output value.
VZT:
VFST
Voltage at which the digital output changes from 0x000 to 0x001.
Voltage at which the digital output changes from 0xFFE to 0xFFF.
Voltage at which the digital output changes from 0x(N − 1) to 0xN.
:
VNT
:
Document Number: 002-05675 Rev. *E
Page 77 of 99
CY9A1A0N Series
12.6 10-bit D/A Converter
Electrical Characteristics for the D/A Converter
(VCC = AVCC = 1.8V to 5.5V, VSS = AVSS = 0V, TA = - 40C to + 85C)
Value
Typ
-
Parameter
Resolution
Symbol Pin name
Unit
Remarks
Min
-
Max
10
-
bit
μs
tC20
tC100
INL
0.37
1.87
-4.0
-0.9
-
0.53
0.69
3.47
+4.0
+0.9
10.0
+5.5
5.5
Load 20 pF
Conversion time
2.67
μs
Load 100 pF
Integral Nonlinearity
-
LSB
LSB
mV
mV
kΩ
*
*
Differential Nonlinearity DNL
-
-
DAx
Code is 0x000
Code is 0x3FF
D/A operation
D/A stop
Output Voltage offset
VOFF
RO
tR
-50.0
2.45
5.0
-
3.50
9.0
Analog output
impedance
-
MΩ
Output undefined
period
-
-
250
ns
*: No-load
Document Number: 002-05675 Rev. *E
Page 78 of 99
CY9A1A0N Series
12.7 Low-Voltage Detection Characteristics
12.7.1 Low-Voltage Detection Reset
(TA = - 40C to + 85C)
Value
Typ
Parameter
Symbol
Conditions
SVHR = 0001
SVHR = 0100
Unit
Remarks
Min
1.43
1.53
1.80
1.90
Max
1.63
1.73
2.06
2.16
Detected voltage
Released voltage
Detected voltage
Released voltage
VDLR
VDHR
VDLR
VDHR
1.53
1.63
1.93
2.03
V
V
V
V
When voltage drops
When voltage rises
When voltage drops
When voltage rises
LVD stabilization wait
time
tLVDRW
-
-
-
-
-
633 × tCYCP
60
*
μs
μs
Detection delay time tLVDRD
dV/dt ≥ -4mV/μs
*: tCYCP indicates the APB2 bus clock cycle time.
Document Number: 002-05675 Rev. *E
Page 79 of 99
CY9A1A0N Series
12.7.2 Interrupt of Low-Voltage Detection
Normal mode
(TA = - 40C to + 85C)
Value
Typ
Parameter
Symbol Conditions
Unit
Remarks
Min
1.87
1.97
1.96
2.06
2.05
2.15
2.15
2.25
2.24
2.34
2.33
2.43
2.43
2.53
2.61
2.71
2.80
2.90
2.99
3.09
3.36
3.46
3.45
3.55
3.73
3.83
3.83
3.93
3.92
4.02
Max
2.13
2.23
2.24
2.34
2.35
2.45
2.45
2.55
2.56
2.66
2.67
2.77
2.77
2.87
2.99
3.09
3.20
3.30
3.41
3.51
3.84
3.94
3.95
4.05
4.27
4.37
4.37
4.47
4.48
4.58
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
VDLI
2.00
2.10
2.10
2.20
2.20
2.30
2.30
2.40
2.40
2.50
2.50
2.60
2.60
2.70
2.80
2.90
3.00
3.10
3.20
3.30
3.60
3.70
3.70
3.80
4.00
4.10
4.10
4.20
4.20
4.30
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
SVHI = 0000
VDHI
VDLI
SVHI = 0001
VDHI
VDLI
SVHI = 0010
VDHI
VDLI
SVHI = 0011
VDHI
VDLI
SVHI = 0100
VDHI
VDLI
SVHI = 0101
VDHI
VDLI
SVHI = 0110
VDHI
VDLI
SVHI = 0111
VDHI
VDLI
SVHI = 1000
VDHI
VDLI
SVHI = 1001
VDHI
VDLI
SVHI = 1010
VDHI
VDLI
SVHI = 1011
VDHI
VDLI
SVHI = 1100
VDHI
VDLI
SVHI = 1101
VDHI
VDLI
SVHI = 1110
VDHI
LVD stabilization
wait time
tLVDIW
-
-
-
-
-
633 × tCYCP
*
μs
μs
dV/dt ≥
- 4mV/μs
Detection delay time tLVDID
60
*: tCYCP indicates the APB2 bus clock cycle time.
Document Number: 002-05675 Rev. *E
Page 80 of 99
CY9A1A0N Series
Low power mode
Parameter
(TA = - 40C to + 85C)
Value
Typ
Symbol
Conditions
Unit
Remarks
Min
1.80
1.90
1.89
1.99
1.98
2.08
2.07
2.17
2.16
2.26
2.25
2.35
2.34
2.44
2.52
2.62
2.70
2.80
2.88
2.98
3.24
3.34
3.33
3.43
3.60
3.70
3.69
3.79
3.78
3.88
Max
2.20
2.30
2.31
2.41
2.42
2.52
2.53
2.63
2.64
2.74
2.75
2.85
2.86
2.96
3.08
3.18
3.30
3.40
3.52
3.62
3.96
4.06
4.07
4.17
4.40
4.50
4.51
4.61
4.62
4.72
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
VDLIL
VDHIL
VDLIL
VDHIL
VDLIL
VDHIL
VDLIL
VDHIL
VDLIL
VDHIL
VDLIL
VDHIL
VDLIL
VDHIL
VDLIL
VDHIL
VDLIL
VDHIL
VDLIL
VDHIL
VDLIL
VDHIL
VDLIL
VDHIL
VDLIL
VDHIL
VDLIL
VDHIL
VDLIL
VDHIL
2.00
2.10
2.10
2.20
2.20
2.30
2.30
2.40
2.40
2.50
2.50
2.60
2.60
2.70
2.80
2.90
3.00
3.10
3.20
3.30
3.60
3.70
3.70
3.80
4.00
4.10
4.10
4.20
4.20
4.30
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
SVHI = 0000
SVHI = 0001
SVHI = 0010
SVHI = 0011
SVHI = 0100
SVHI = 0101
SVHI = 0110
SVHI = 0111
SVHI = 1000
SVHI = 1001
SVHI = 1010
SVHI = 1011
SVHI = 1100
SVHI = 1101
SVHI = 1110
LVD stabilization
wait time
tLVDILW
-
-
-
-
-
8039 × tCYCP
*
μs
μs
Detection delay time tLVDILD
dV/dt ≥ - 0.4mV/μs
800
*: tCYCP indicates the APB2 bus clock cycle time.
Document Number: 002-05675 Rev. *E
Page 81 of 99
CY9A1A0N Series
12.8 Flash Memory Write/Erase Characteristics
12.8.1 Write / Erase time
(VCC = 2.0V to 5.5V, TA = - 40C to + 85C)
Value
Parameter
Unit
Remarks
Typ*
1.6
Max*
7.5
Large Sector
Small Sector
Sector erase
time
s
Includes write time prior to internal erase
0.4
2.1
Half word (16-bit)
write time
25
4
400
μs
s
Not including system-level overhead time.
Chip erase time
19.2
Includes write time prior to internal erase
*: The typical value is immediately after shipment, the maximam value is guarantee value under 100,000 cycle of erase/write.
12.8.2 Write cycles and data hold time
Erase/write cycles (cycle)
Data hold time (year)
Remarks
1,000
20 *
10 *
5*
10,000
100,000
*: At average + 85C
Document Number: 002-05675 Rev. *E
Page 82 of 99
CY9A1A0N Series
12.9 Return Time from Low-Power Consumption Mode
12.9.1 Return Factor: Interrupt/WKUP
The return time from Low-Power consumption mode is indicated as follows. It is from receiving the return factor to starting the
program operation.
Return Count Time
(VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C)
Value
Parameter
Symbol
Unit
Remarks
Typ
Max*
Sleep mode
tCYCC
μs
High-speed CR Timer mode,
Main Timer mode,
40
80
μs
PLL Timer mode
Low-speed CR Timer mode
630
630
1260
1260
μs
μs
tICNT
Sub Timer mode
RTC mode,
Stop mode
1083
1099
2100
2127
μs
μs
Deep Standby RTC mode
Deep Standby Stop mode
*: The maximum value depends on the accuracy of built-in CR.
Operation example of return from Low-Power consumption mode (by external interrupt*)
External
interrupt
Interrupt factor
Active
accept
tICNT
Interrupt factor
clear by CPU
CPU
Operation
Start
*: External interrupt is set to detecting fall edge.
Document Number: 002-05675 Rev. *E
Page 83 of 99
CY9A1A0N Series
Operation example of return from Low-Power consumption mode (by internal resource interrupt*)
Internal
resource
interrupt
Interrupt factor
accept
Active
tICNT
Interrupt factor
clear by CPU
CPU
Operation
Start
*: Internal resource interrupt is not included in return factor by the kind of Low-Power consumption mode.
Notes:
−
−
The return factor is different in each Low-Power consumption modes.
See Chapter 6: Low Power Consumption Mode and Operations of Standby Modes in FM3 Family
Peripheral Manual.
When interrupt recoveries, the operation mode that CPU recoveries depend on the state before
the Low-Power consumption mode transition. See Chapter 6: Low Power Consumption Mode in
FM3 Family Peripheral Manual.
Document Number: 002-05675 Rev. *E
Page 84 of 99
CY9A1A0N Series
12.9.2 Return Factor: Reset
The return time from Low-Power consumption mode is indicated as follows. It is from releasing reset to starting the program
operation.
Return Count Time
(VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C)
Value
Parameter
Symbol
Unit
Remarks
Typ
Max*
Sleep mode
359
647
μs
High-speed CR Timer mode,
Main Timer mode,
359
647
μs
PLL Timer mode
Low-speed CR Timer mode
Sub Timer mode
929
929
1787
1787
2127
μs
μs
μs
tRCNT
RTC/Stop mode
1099
Deep Standby RTC mode
Deep Standby Stop mode
1099
2127
μs
*: The maximum value depends on the accuracy of built-in CR.
Operation example of return from Low-Power consumption mode (by INITX)
INITX
Internal reset
Reset active
Release
tRCNT
CPU
Operation
Start
Document Number: 002-05675 Rev. *E
Page 85 of 99
CY9A1A0N Series
Operation example of return from low power consumption mode (by internal resource reset*)
Internal
resource
reset
Internal reset
Reset active
Release
tRCNT
CPU
Operation
Start
*: Internal resource reset is not included in return factor by the kind of Low-Power consumption mode.
Notes:
−
−
−
−
−
The return factor is different in each Low-Power consumption modes.
See Chapter 6: Low Power Consumption Mode and Operations of Standby Modes in FM3 Family
Peripheral Manual.
When interrupt recoveries, the operation mode that CPU recoveries depend on the state before
the Low-Power consumption mode transition. See Chapter 6: Low Power Consumption Mode in
FM3 Family Peripheral Manual.
The time during the power-on reset/low-voltage detection reset is excluded. See (12.4.7)
Power-on Reset Timing in 12.4 AC Characteristics in Electrical Characteristics for the detail on
the time during the power-on reset/low-voltage detection reset.
When in recovery from reset, CPU changes to the High-speed CR Run mode. When using the
main clock or the PLL clock, it is necessary to add the main clock oscillation stabilization wait time
or the Main PLL clock stabilization wait time.
The internal resource reset means the watchdog reset and the CSV reset.
Document Number: 002-05675 Rev. *E
Page 86 of 99
CY9A1A0N Series
13.Ordering Information
On-chip
Flash
memory
On-chip
SRAM
Part number
Package
Packing
Plastic LQFP
(0.5mm pitch), 64-pin
(LQD064)
CY9AF1A1LPMC1-G-SNE2
CY9AF1A2LPMC1-G-SNE2
CY9AF1A1LPMC-G-SNE2
CY9AF1A2LPMC-G-UNE2
CY9AF1A1MPMC-G-UNE2
CY9AF1A2MPMC-G-UNE2
CY9AF1A1MPMC1-G-SNE2
CY9AF1A2MPMC1-G-UNE2
CY9AF1A1NPMC-G-SNE2
CY9AF1A2NPMC-G-UNE2
CY9AF1A1NPF-G-SNE1
CY9AF1A2NPF-G-SNE1
64 Kbyte
12 Kbyte
128 Kbyte
64 Kbyte
128 Kbyte
64 Kbyte
128 Kbyte
64 Kbyte
128 Kbyte
64 Kbyte
128 Kbyte
64 Kbyte
128 Kbyte
16 Kbyte
12 Kbyte
16 Kbyte
12 Kbyte
16 Kbyte
12 Kbyte
16 Kbyte
12 Kbyte
16 Kbyte
12 Kbyte
16 Kbyte
Plastic LQFP
(0.65mm pitch), 64-pin
(LQG064)
Plastic LQFP
(0.5mm pitch), 80-pin
(LQH080)
Tray
Plastic LQFP
(0.65mm pitch), 80-pin
(LQJ080)
Plastic LQFP
(0.5mm pitch), 100-pin
(LQI100)
Plastic QFP
(0.65mm pitch), 100-pin
(PQH100)
Document Number: 002-05675 Rev. *E
Page 87 of 99
CY9A1A0N Series
14.Package Dimensions
Package Type
Package Code
LQFP 64
LQD064
4
D
5
7
D1
48
33
33
48
32
32
49
49
5
7
E1
E
4
3
6
17
17
64
64
1
16
16
1
2
5
7
e
C A-B D
3
0.10
0.08
C A-B D
BOTTOM VIEW
0.20
C
A-B
D
8
b
TOPVIEW
2
A
9
c
A
SEATING
PLANE
b
0.25
A'
A1
SECTION A-A'
L1
0.08
C
L
10
SIDE VIEW
DIMENSIONS
SYMBOL
MIN. NOM. MAX.
1.70
A
A1
b
0.00
0.15
0.09
0.20
0.2
c
0.20
D
12.00 BSC.
10.00 BSC.
0.50 BSC
D1
e
E
12.00 BSC.
10.00 BSC.
E1
L
0.45 0.60 0.75
0.30 0.50 0.70
L1
002-11499 **
PACKAGE OUTLINE, 64 LEAD LQFP
10.0X10.0X1.7 MM LQD064 Rev**
Document Number: 002-05675 Rev. *E
Page 88 of 99
CY9A1A0N Series
Package Type
Package Code
LQFP 64
LQG064
4
D
5
7
D1
48
33
33
48
49
32
32
49
E1
E
5
7
4
3
64
17
17
64
1
16
16
1
2
5
7
BOTTOM VIEW
e
3
0.10
C A-B D
0.20
C A-B D
0.13
C
A-B
D
b
8
TOP VIEW
2
A
θ
A
9
SEATING
PLA NE
A1
10
0.25
L
c
A'
L1
b
SECTION A -A'
0.10
C
SIDE VIEW
DIMENSION
MIN. NOM. MAX.
1.70
SYMBOL
A
A1
b
0.00
0.27 0.32 0.37
0.09 0.20
0.20
c
D
14.00 BSC
12.00 BSC
0.65 BSC
D1
e
E
14.00 BSC
12.00 BSC
E1
L
0.45 0.60 0.75
0.30 0.50 0.70
L1
θ
0°
8°
002-13881 **
PACKAGE OUTLINE, 64 LEAD LQFP
12.0X12.0X1.7 MM LQG064 REV**
Document Number: 002-05675 Rev. *E
Page 89 of 99
CY9A1A0N Series
Package Type
Package Code
LQFP 80
LQH080
4
D
5
7
D1
60
41
41
60
61
40
40
61
5
7
E1
E
4
3
6
80
21
21
80
1
20
20
1
2
5
8
7
D
0.10
C
C
A-B D
BOTTOM VIEW
3
e
0.08
A-B
D
b
0.20
C A-B D
TOP VIEW
2
A
A
SEATING
PLANE
9
c
A'
L1
0.25
0.08
C
A1
b
L
10
SIDE VIEW
SECTION A-A'
DIMENSIONS
SYMBOL
MIN. NOM. MAX.
1.70
A
A1
b
0.05
0.15
0.09
0.15
0.27
0.20
c
D
14.00 BSC.
D1
e
12.00 BSC.
0.50 BSC
E
14.00 BSC.
12.00 BSC.
E1
L
0.45 0.60 0.75
0.30 0.50 0.70
L1
002-11501 **
PACKAGE OUTLINE, 80 LEAD LQFP
12.0X12.0X1.7 MM LQH080 Rev **
Document Number: 002-05675 Rev. *E
Page 90 of 99
CY9A1A0N Series
Package Type
Package Code
LQFP 80
LQJ080
4
D
5
7
D1
60
41
41
60
61
40
40
61
E1
E
5
7
4
3
6
80
21
21
80
1
20
b
20
1
2
5
7
0.10
C
C
A-B
D
e
3
0.20
C A-B D
ddd
A-B
D
8
2
A
9
A
θ
SEATING
PLANE
c
A'
A1
b
0.10
C
0.25
L
L1
10
SECTION A-A'
DIMENSIONS
SYMBOL
MIN. NOM. MAX.
1.70
A
A1
b
0.00
0.16 0.32 0.38
0.09 0.20
0.20
c
D
16.00 BSC
14.00 BSC
0.65 BSC
D1
e
E
16.00 BSC
14.00 BSC
E1
L
0.45 0.60 0.75
0.30 0.50 0.70
L1
θ
0°
8°
002-14043 **
PACKAGE OUTLINE, 80 LEAD LQFP
14.0X14.0X1.7 MM LQJ080 REV**
Document Number: 002-05675 Rev. *E
Page 91 of 99
CY9A1A0N Series
Package Type
Package Code
LQFP 100
LQI100
4
4
D
D
5
7
5
7
D1
D1
75
51
51
75
76
50
50
76
E1
E1
E
E
5
5
4
4
7
7
3
6
100
26
26
100
1
1
25
25
2
5
7
e
0.10
C
A-B D
3
BOTTOM VIEW
0.20
C A-B D
b
8
0.08
C
A-B
D
TOPVIEW
2
A
9
A
SEATING
PLANE
c
A1
A'
0.25
b
L1
0.08
C
10
SECTION A-A'
L
SIDE VIEW
DETAIL A
NOTES:
1. ALL DIMENSIONSAREIN MILLIMETERS.
DIMENSIONS
SYMBOL
MIN. NOM. MAX.
1.70
2. DATUM PLANEH ISLOCATED ATTHEBOTTOM OF THE MOLD PARTING
LINECOINCIDENTWITH WHERETHELEAD EXITSTHEBODY.
3. DATUMSA-BAND D TO BEDETERMINED ATDATUM PLANEH.
A
A1
b
0.05
0.15
0.09
0.15
0.27
0.20
4. TO BEDETERMINED ATSEATING PLANEC.
5. DIMENSIONSD1 AND E1 DO NOTINCLUDEMOLD PROTRUSION.
ALLOW ABLEPROTRUSION IS0.25mm PRESIDE.
c
D
16.00 BSC
14.00 BSC
0.50 BSC
DIMENSIONSD1 AND E1 INCLUDEMOLD MISMATCH AND AREDETERMINED
ATDATUM PLANE H.
D1
e
6. DETAILSOF PIN 1 IDENTIFIERAREOPTIONALBUTMUSTBE LOCATED
WITHIN THEZONEINDICATED.
E
16.00 BSC
14.00 BSC
7. REGARDLESSOFTHERELATIVESIZEOF THEUPPERAND LOWERBODY
SECTIONS. DIMENSIONSD1 AND E1 AREDETERMINED ATTHELARGEST
FEATUREOF THEBODY EXCLUSIVEOF MOLD FLASH AND GATE BURRS.
BUTINCLUDING ANY MISMATCH BETWEEN THEUPPERAND LOWER
SECTIONSOF THEMOLDERBODY.
E1
L
0.45
0.60 0.75
L1
0.30 0.50 0.70
8. DIMENSION b DOESNOTINCLUDE DAMBARPROTRUSION. THEDAMBAR
PROTRUSION (S) SHALL NOTCAUSETHELEAD WIDTH TO EXCEED b
MAXIMUM BY MORETHAN 0.08mm. DAMBARCANNOTBELOCATED ON
THELOWERRADIUSORTHELEAD FOOT.
9. THESEDIMENSIONSAPPLY TO THEFLATSECTION OF THE LEAD
BETWEEN 0.10mm AND 0.25mm FROM THELEAD TIP.
10. A1 ISDEFINED ASTHEDISTANCEFROM THESEATING PLANE TO
THELOWESTPOINTOF THEPACKAGEBODY.
002-11500 *A
PACKAGE OUTLINE, 100 LEAD LQFP
14.0X14.0X1.7 MM LQI100 REV*A
Document Number: 002-05675 Rev. *E
Page 92 of 99
CY9A1A0N Series
Package Type
Package Code
QFP 100
PQH100
D
4
D1
5
7
80
51
51
80
81
50
50
81
E1
E
4
5
7
6
3
100
31
31
100
1
30
30
1
2
5
7
e
A-B D
0.20
C
A-B
D
3
BOTTOM VIEW
b
0.40
C
0.13
C A-B
D
8
TOP VIEW
2
θ
9
c
A
SEATING
PLANE
L2
A'
10
0.10
C
b
SECTION A-A'
DETAIL A
SIDE VIEW
DIMENSIONS
SYMBOL
MIN. NOM. MAX.
3.35
A
A1
b
0.05
0.27
0.11
0.45
0.37
0.23
0.32
c
D
23.90 BSC
20.00 BSC
0.65 BSC
D1
e
E
17.90 BSC
14.00 BSC
E1
0°
8°
0.88 1.03
1.95 REF
0.25 BSC
θ
L
0.73
L1
L2
002-15156 **
PACKAGE OUTLINE, 100 LEAD QFP
20.00X14.00X3.35 MM PQH100 REV**
Document Number: 002-05675 Rev. *E
Page 93 of 99
CY9A1A0N Series
15.Errata
This chapter describes the errata for CY9A1A0N Series. Details include errata trigger conditions, scope of impact, available
workaround, and silicon revision applicability.
Contact your local Cypress Sales Representative if you have questions.
15.1 Part Numbers Affected
Part Number
Initial Revision
CY9AF1A1LPMC1-G-SNE2, CY9AF1A2LPMC1-G-SNE2, CY9AF1A1LPMC-G-SNE2,
CY9AF1A2LPMC-G-SNE2, CY9AF1A2LPMC-G-UNE2, CY9AF1A1MPMC-G-SNE2,
CY9AF1A1MPMC-G-UNE2, CY9AF1A2MPMC-G-SNE2, CY9AF1A2MPMC-G-UNE2,
CY9AF1A1MPMC1-G-SNE2, CY9AF1A2MPMC1-G-SNE2, CY9AF1A2MPMC1-G-UNE2,
CY9AF1A1NPMC-G-SNE2, CY9AF1A2NPMC-G-SNE2, CY9AF1A2NPMC-G-UNE2,
CY9AF1A1NPF-G-SNE1, CY9AF1A2NPF-G-SNE1
15.2 Qualification Status
Product Status: In Production − Qual.
15.3 Errata Summary
This table defines the errata applicability to available devices.
Items
Part Number
Refer to 15.1
Refer to 15.1
Silicon Revision
Initial Rev
Fix Status
[15.4.1] HDMI-CEC polling message issue
[15.4.2] RTC delay issue
Next silicon is not planned
Next silicon is not planned
Initial Rev
15.4 Errata Detail
15.4.1
HDMI-CEC polling message issue
PROBLEM DEFINITION
Error#1) While MCU sends a Polling Message, it always returns a NACK to a message coming to the MCU from another node.
Error#2) MCU always waits for 7-bit signal free on CEC line before it drives the line even when the last line initiator was another
node.
PARAMETERS AFFECTED
N/A
TRIGGER CONDITION(S)
This error always happens.
SCOPE OF IMPACT
MCU does not reply properly to another node.
WORKAROUND
The software workaround is applied to Error #1.
1. Store 0x0 to SFREE register.
2. Monitor CEC line with GPIO and wait until 1 lasts for the signal free time.
3. Store frame data to TXDATA register and store 0x0F to RCADR1 or RCADR2 register.
It sends a message after 3~4 clocks of 32.768 kHz clock when TXDATA is stored 0x0F.
Document Number: 002-05675 Rev. *E
Page 94 of 99
CY9A1A0N Series
If the device receives a frame from another node within 2~3 clocks after storing TXDATA, the bus error occurs and if the device
receives a frame from another node within 3~4 clocks after storing TXDATA, the arbitration lost occurs. In these cases:
4-A-1. Set RCADR1 or RCADR2 to former value from 0x0F to reply ACK
4-A-2. Return back to step 2 above
If the device receives a frame from another node within 1~2 clocks after storing TXDATA, take these steps.
4-B-1. Monitor CEC line with GPIO after 50us from storing TXDATA
4-B-2. Set TXEN to 1 -> 0 -> 1 immediately when GPIO finds state low on the CEC line
4-B-3. Set RCADR1 or RCADR2 to former value from 0x0F to reply ACK
4-B-4. Return back to step 2 above
For Error #2, there is no software workaround, but signal free time of fixed 7-bit does not violate HDMI-CEC specification. The
specification says signal free time must be more than and equals to 5-bit.
FIX STATUS
The user uses the workaround to avoid the issue. The next silicon fixing the issue is not planned.
15.4.2
RTC delay issue
PROBLEM DEFINITION
RTC delays when software reset or APB2 reset occurs.
PARAMETERS AFFECTED
N/A
TRIGGER CONDITION(S)
This error happens when software reset or APB2 reset occurs.
SCOPE OF IMPACT
RTC delays and does not time correctly.
WORKAROUND
RTC block is supplied with sub-clock. Both software reset and APB2 reset disable two clocks of sub-clock to RTC block. The
workaround is to count occurrence of software and APB2 reset and calculate how many clocks of sub-clock were disabled and add
one second to RTC counter when accumulated disabled sub-clock period reaches one second.
FIX STATUS
The user uses the workaround to avoid the issue. The next silicon fixing the issue is not planned.
Document Number: 002-05675 Rev. *E
Page 95 of 99
CY9A1A0N Series
Major Changes
Spansion Publication Number: DS706-00068
Page
Section
Change Results
Revision 0.1
-
-
Initial release
Revision 1.0
-
-
-
Changed from Preliminary to Full Producton
Deleted a part of QFN
-
43
BLOCK DIAGRAM
Added note for MB9AF1AxL
ELECTRICAL
CHARACTERISTICS
3.DC Characteristics (1) Current
Rating
58,59
Revised the values of “TBD”
Revision 2.0
Features
· On-chip Memories
2
Changed the description of on-chip SRAM
Packages
7 - 31
Pin Assignment
List of Pin Functions
Deleted QFN package
Added the following description
"Evaluate oscillation of your using crystal oscillator by your
mount board."
Handling Devices
Crystal oscillator circuit
40
44
Memory Map
· Memory map(2)
Added the summary of Flash memory sector
· Changed the table format
· Added Main Timer mode current
· Added Flash Memory Current
· Moved A/D Converter Current
· Moved D/A Converter Current
Electrical Characteristics
57 - 59 3. DC Characteristics
(1) Current rating
Electrical Characteristics
60
63
64
3. DC Characteristics
(2) Pin Characteristics
Added the input leak current of CEC port at power off
Electrical Characteristics
4. AC Characteristics
(4-1) Operating Conditions of Main
PLL
(4-2) Operating Conditions of Main
PLL
· Added the figure of Main PLL connection
· Changed the figure of timing
· Changed from Reset release delay time(tOND) to Time until
Electrical Characteristics
4. AC Characteristics
(6) Power-on Reset Timing
releasing Power-on reset(tPRT
)
· Modified from UART Timing to CSIO/UART Timing
Electrical Characteristics
66 - 73 4. AC Characteristics
· Changed from Internal shift clock operation to Master mode
· Changed from External shift clock operation to Slave mode
(8) CSIO/UART Timing
· Added the typical value of Integral Nonlinearity, Differential
Nonlinearity, Zero transition voltage and Full-scale transition
voltage
Electrical Characteristics
5. 12bit A/D Converter
77
· Added Conversion time at AVCC < 2.7 V
Electrical Characteristics
81
84
7. Low-voltage Detection
Characteristics
Deleted the figure
Electrical Characteristics
8. Flash Memory Write/Erase
Characteristics
Change to the erase time of include write time prior to internal
erase
Document Number: 002-05675 Rev. *E
Page 96 of 99
CY9A1A0N Series
Page
Section
Change Results
Electrical Characteristics
85 - 88 9. Return Time from Low-Power
Added Return Time from Low-Power Consumption Mode
Consumption Mode
89
Ordering Information
Changed notation of part number
NOTE: Please see “Document History” about later revised information.
Document Number: 002-05675 Rev. *E
Page 97 of 99
CY9A1A0N Series
Document History
Document Title: CY9A1A0N Series 32-bit Arm® Cortex®-M3 FM3 Microcontroller
Document Number: 002-05675
Orig. of
Change
Submission
Date
Revision
ECN
Description of Change
**
-
AKIH
06/30/2015 Migrated to Cypress and assigned document number 002-05675.
No change to document contents or format.
*A
*B
5193131
5513616
AKIH
03/31/2016 Updated to Cypress template.
HTER
02/08/2017
Modified RTC description in “Features, Real-Time Clock(RTC)”. Changed starting
count value from 01 to 00. Deleted “second, or day of the week” in the Interrupt
function. (Page 2)
Changed package code as the following table in following section.
2. Package (Page 7)
3. Pin Assignment (Page 8 -11)
12. Electrical Characteristics (Page 53)
13. Ordering Information (Page 87)
14. Package Dimensions (Page 88 - 93)
Before
After
FPT-64P-M38
FPT-64P-M39
FPT-80P-M37
FPT-80P-M40
LQD064
LQG064
LQH080
LQJ080
FPT-100P-M23 LQI100
FPT-100P-M06 PQH100
Added the Baud rate spec in “12.4.9 CSIO/UART Timing” (Page 64 - 70)
Changed Part numbers in 13. Ordering Information (Page 87)
“MB9AF1A2LPMC-G-SNE2” to “MB9AF1A2LPMC-G-UNE2”
“MB9AF1A2MPMC-G-SNE2” to “MB9AF1A2MPMC-G-UNE2”
“MB9AF1A2NPMC-G-SNE2” to “MB9AF1A2NPMC-G-UNE2”
“MB9AF1A1MPMC-G-SNE2” to “MB9AF1A1MPMC-G-UNE2”
“MB9AF1A2MPMC1-G-SNE2” to “MB9AF1A2MPMC1-G-UNE2”
Added 15. Errata (Page 94 - 95)
*C
*D
5768635
5929772
YSAT
HTER
06/12/2017
10/16/2017
Updated to new template.
Corrected the following Analog output impedance MAX value (D/A operation)
4.55kΩ 5.5kΩ
in chapter 12.6 10-bit D/A Converter.
Updated Document Title to read as “CY9A1A0N Series 32-bit Arm® Cortex®-M3
FM3 Microcontroller”.
*E
6575847
XITO
05/17/2019
Replaced “MB9A1A0N Series” with “CY9A1A0N Series” in all instances across the
document.
Updated Ordering Information:
Updated part numbers.
Updated to new template.
Completing Sunset Review.
Document Number: 002-05675 Rev. *E
Page 98 of 99
CY9A1A0N Series
Sales, Solutions, and Legal Information
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Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in
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Document Number: 002-05675 Rev. *E
May 17, 2019
Page 99 of 99
相关型号：
CY9AF1A2MPMC1-G-UNE2
FM3 CY9AFxAxL/M/N-Series Ultra Low Leakage Arm® Cortex®-M3 Microcontroller (MCU) Family
INFINEON
CY9AF1A2NPMC-G-UNE2
FM3 CY9AFxAxL/M/N-Series Ultra Low Leakage Arm® Cortex®-M3 Microcontroller (MCU) Family
INFINEON
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