CY9BF518TBGL-GK7E1 [INFINEON]
FM3 CY9BFx1xS/T-Series Arm® Cortex®-M3 Microcontroller (MCU) Family;
| 型号： | CY9BF518TBGL-GK7E1 |
| 厂家： | 
Infineon |
| 描述： | FM3 CY9BFx1xS/T-Series Arm® Cortex®-M3 Microcontroller (MCU) Family 微控制器 |
| 文件： | 总126页 (文件大小：2000K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
The following document contains information on Cypress products. The document has the series
name, product name, and ordering part numbering with the prefix “MB”. However, Cypress will
offer these products to new and existing customers with the series name, product name, and
ordering part number with the prefix “CY”.
How to Check the Ordering Part Number
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2. Enter the keyword (for example, ordering part number) in the SEARCH PCNS field and click
Apply.
3. Click the corresponding title from the search results.
4. Download the Affected Parts List file, which has details of all changes
For More Information
Please contact your local sales office for additional information about Cypress products and
solutions.
About Cypress
Cypress is the leader in advanced embedded system solutions for the world's most innovative
automotive, industrial, smart home appliances, consumer electronics and medical products.
Cypress' microcontrollers, analog ICs, wireless and USB-based connectivity solutions and reliable,
high-performance memories help engineers design differentiated products and get them to market
first. Cypress is committed to providing customers with the best support and development
resources on the planet enabling them to disrupt markets by creating new product categories in
record time. To learn more, go to www.cypress.com.
MB9B510T Series
32-bit ARM® Cortex®-M3
FM3 Microcontroller
The MB9B510T Series are highly integrated 32-bit microcontrollers dedicated for embedded controllers with high-performance and
competitive cost.
These series are based on the ARM® Cortex®-M3 Processor with on-chip Flash memory and SRAM, and has peripheral functions
such as Motor Control Timers, ADCs and Communication Interfaces (USB, CAN, UART, CSIO, I2C, LIN).
The products which are described in this datasheet are placed into TYPE2 product categories in "FM3 Family Peripheral Manual".
Features
32-bit ARM® Cortex®-M3 Core
External Bus Interface
Processor version: r2p1
Supports SRAM, NOR and NAND Flash device
Up to 8 chip selects
Up to 144 MHz Frequency Operation
Memory Protection Unit (MPU): improves the reliability of an
embedded system
8-/16-bit Data width
Up to 25-bit Address bit
Integrated Nested Vectored Interrupt Controller (NVIC): 1
NMI (non-maskable interrupt) and 48 peripheral interrupts
and 16 priority levels
Maximum area size: Up to 256 Mbytes
Supports Address/Data multiplex
Supports external RDY input
24-bit System timer (Sys Tick): System timer for OS task
management
USB Interface (Max 2 channels)
USB interface is composed of Device and Host.
On-chip Memories
[Flash memory]
Up to 1 Mbyte
[USB device]
USB2.0 Full-Speed supported
Built-in Flash Accelerator System with 16 Kbyte trace buffer
memory
Max 6 EndPoint supported
EndPoint 0 is control transfer
EndPoint 1,2 can be selected Bulk-transfer,
The read access to Flash memory can be achieved without
wait cycle up to operation frequency of 72 MHz. Even at the
operation frequency more than 72 MHz, an equivalent
access to Flash memory can be obtained by Flash
Accelerator System.
Interrupt-transfer or Isochronous-transfer
EndPoint 3 – 5 can be selected Bulk-transfer or
Interrupt-transfer
EndPoint 1 to 5 is comprised Double Buffer
• EndPoint 0, 2 to 5: 64 bytes
• EndPoint 1: 256 bytes
Security function for code protection
[SRAM]
[USB host]
This Series contain a total of up to 128 Kbyte on-chip SRAM
memories. This is composed of two independent SRAM
(SRAM0, SRAM1). SRAM0 is connected to I-code bus and
D-code bus of Cortex-M3 core. SRAM1 is connected to System
bus.
USB2.0 Full/Low speed supported
Bulk-transfer, interrupt-transfer and Isochronous-transfer
support
USB Device connected/dis-connected automatically detect
IN/OUT token handshake packet automatically
Max 256-byte packet-length supported
SRAM0: Up to 64 Kbyte.
SRAM1: Up to 64 Kbyte.
Wake-up function supported
Cypress Semiconductor Corporation
Document Number: 002-05602 Rev. *C
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised July 11, 2017
MB9B510T Series
CAN Interface (Max. 2 channels)
Compatible with CAN Specification 2.0A/B
Maximum transfer rate: 1 Mbps
Built-in 32 message buffer
DMA Controller (8 channels)
DMA Controller has an independent bus for CPU, so CPU and
DMA Controller can process simultaneously.
8 independently configured and operated channels
Transfer can be started by software or request from the
built-in peripherals
Multi-function Serial Interface (Max 8 channels)
Transfer address area: 32 bit (4 Gbyte)
4 channels with 16steps×9-bit FIFO (ch.4 to ch.7), 4
channels without FIFO (ch.0 to ch.3)
Transfer mode: Block transfer/Burst transfer/Demand
transfer
Operation mode is selectable from the followings for each
channel.
UART
CSIO
LIN
Transfer data type: byte/half-word/word
Transfer block count: 1 to 16
Number of transfers: 1 to 65536
I2C
A/D Converter (Max 32 channels)
[12-bit A/D Converter]
[UART]
Full-duplex double buffer
Successive Approximation Register type
Built-in 3unit
Selection with or without parity supported
Built-in dedicated baud rate generator
External clock available as a serial clock
Conversion time: 1.0 μs @ 5 V
Priority conversion available (priority at 2 levels)
Scanning conversion mode
Hardware Flow control: Automatically control the
transmission by CTS/RTS (only ch.4)
Various error detect functions available (parity errors, framing
errors, and overrun errors)
Built-in FIFO for conversion data storage (for SCAN
conversion:16 steps, for Priority conversion:4 steps)
[CSIO]
Base Timer (Max 16 channels)
Operation mode is selectable from the followings for each
channel.
Full-duplex double buffer
Built-in dedicated baud rate generator
Overrun error detect function available
[LIN]
16-bit PWM timer
16-bit PPG timer
16-/32-bit reload timer
16-/32-bit PWC timer
LIN protocol Rev.2.1 supported
Full-duplex double buffer
Master/Slave mode supported
LIN break field generate (can be changed 13-16bit length)
LIN break delimiter generate (can be changed 1-4bit length)
General Purpose I/O Port
This series can use its pins as I/O ports when they are not used
for external bus or peripherals. Moreover, the port relocate
function is built in. It can set which I/O port the peripheral
function can be allocated.
Various error detect functions available (parity errors, framing
errors, and overrun errors)
[I2C]
Capable of pull-up control per pin
Capable of reading pin level directly
Built-in the port relocate function
Up 154 fast I/O Ports @ 176 pin Package
Standard-mode (Max 100 kbps) / Fast-mode (Max 400 kbps)
supported
Some pin is 5 V tolerant I/O.
See "Pin Description" to confirm the corresponding pins.
Document Number: 002-05602 Rev. *C
Page 2 of 125
MB9B510T Series
Multi-function Timer (Max 3 units)
Watch Counter
The Watch counter is used for wake up from power saving
mode.
The Multi-function timer is composed of the following blocks.
16-bit free-run timer × 3 ch/unit
Input capture × 4 ch/unit
Interval timer: up to 64 s (Max) @ Sub Clock: 32.768 kHz
External Interrupt Controller Unit
Up to 32 external interrupt input pin
Include one non-maskable interrupt(NMI)
Output compare × 6 ch/unit
A/D activation compare × 3 ch/unit
Waveform generator × 3 ch/unit
16-bit PPG timer × 3 ch/unit
Watch dog Timer (2 channels)
A watchdog timer can generate interrupts or a reset when a
time-out value is reached.
The following function can be used to achieve the motor
control.
This series consists of two different watchdogs, a "Hardware"
watchdog and a "Software" watchdog.
PWM signal output function
DC chopper waveform output function
Dead time function
"Hardware" watchdog timer is clocked by low speed internal
CR oscillator. Therefore, "Hardware" watchdog is active in any
power saving mode except STOP mode.
Input capture function
CRC (Cyclic Redundancy Check) Accelerator
The CRC accelerator helps a verify data transmission or
storage integrity.
A/D convertor activate function
DTIF (Motor emergency stop) interrupt function
CCITT CRC16 and IEEE-802.3 CRC32 are supported.
CCITT CRC16 Generator Polynomial: 0x1021
Quadrature Position/Revolution Counter (QPRC)
(Max 3 channels)
IEEE-802.3 CRC32 Generator Polynomial: 0x04C11DB7
The Quadrature Position/Revolution Counter (QPRC) is used
to measure the position of the position encoder. Moreover, it is
possible to use up/down counter.
Clock and Reset
[Clocks]
The detection edge of the three external event input pins AIN,
BIN and ZIN is configurable.
Five clock sources (2 external oscillators, 2 internal CR
oscillator, and Main PLL) that are dynamically selectable.
16-bit position counter
Main Clock:
Sub Clock:
4 MHz to 48 MHz
32.768 kHz
16-bit revolution counter
Two 16-bit compare registers
High-speed internal CR Clock:4 MHz
Low-speed internal CR Clock: 100 kHz
Main PLL Clock
Dual Timer (32-/16-bit Down Counter)
The Dual Timer consists of two programmable 32-/16-bit down
counters.
Operation mode is selectable from the followings for each
channel.
[Resets]
Reset requests from INITX pin
Power on reset
Free-running
Periodic (=Reload)
One-shot
Software reset
Watchdog timers reset
Low voltage detector reset
Clock supervisor reset
Document Number: 002-05602 Rev. *C
Page 3 of 125
MB9B510T Series
Clock Super Visor (CSV)
Clocks generated by internal CR oscillators are used to
supervise abnormality of the external clocks.
Debug
Serial Wire JTAG Debug Port (SWJ-DP)
Embedded Trace Macrocells (ETM) provide comprehensive
debug and trace facilities.
External OSC clock failure (clock stop) is detected, reset is
asserted.
External OSC frequency anomaly is detected, interrupt or
reset is asserted.
Power Supply
Three Power Supplies
Low Voltage Detector (LVD)
Wide range voltage VCC = 2.7 V to 5.5 V
This Series include 2-stage monitoring of voltage on the VCC
pins. When the voltage falls below the voltage has been set,
Low Voltage Detector generates an interrupt or reset.
USBVCC0
= 3.0 V to 3.6 V: for USB ch.0
I/O voltage, when USB ch.0
is used.
LVD1: error reporting via interrupt
LVD2: auto-reset operation
= 2.7 V to 5.5 V: when GPIO is
used.
USBVCC1
= 3.0 V to 3.6 V: for USB ch.1
I/O voltage, when USB ch.1
is used.
Low Power Mode
Three power saving modes supported.
= 2.7 V to 5.5 V: when GPIO
SLEEP
TIMER
STOP
is used.
Document Number: 002-05602 Rev. *C
Page 4 of 125
MB9B510T Series
Contents
1. Product Lineup.................................................................................................................................................................. 7
2. Packages ........................................................................................................................................................................... 8
3. Pin Assignment................................................................................................................................................................. 9
4. List of Pin Functions....................................................................................................................................................... 12
5. I/O Circuit Type................................................................................................................................................................ 48
6. Handling Precautions ..................................................................................................................................................... 54
6.1
6.2
6.3
Precautions for Product Design................................................................................................................................... 54
Precautions for Package Mounting.............................................................................................................................. 55
Precautions for Use Environment................................................................................................................................ 56
7. Handling Devices ............................................................................................................................................................ 57
8. Block Diagram................................................................................................................................................................. 60
9. Memory Size.................................................................................................................................................................... 61
10. Memory Map .................................................................................................................................................................... 61
11. Pin Status in Each CPU State ........................................................................................................................................ 64
12. Electrical Characteristics ............................................................................................................................................... 68
12.1 Absolute Maximum Ratings......................................................................................................................................... 68
12.2 Recommended Operating Conditions.......................................................................................................................... 70
12.3 DC Characteristics....................................................................................................................................................... 71
12.3.1Current Rating.............................................................................................................................................................. 71
12.3.2 Pin Characteristics ....................................................................................................................................................... 73
12.4 AC Characteristics....................................................................................................................................................... 75
12.4.1 Main Clock Input Characteristics.................................................................................................................................. 75
12.4.2 Sub Clock Input Characteristics ................................................................................................................................... 76
12.4.3 Internal CR Oscillation Characteristics......................................................................................................................... 76
12.4.4 Operating Conditions of Main PLL and USB PLL (In the case of using main clock for input of PLL) ........................... 77
12.4.5 Operating Conditions of Main PLL (In the case of using high-speed internal CR)........................................................ 77
12.4.6 Reset Input Characteristics .......................................................................................................................................... 78
12.4.7 Power-on Reset Timing................................................................................................................................................ 79
12.4.8 External Bus Timing..................................................................................................................................................... 80
12.4.9 Base Timer Input Timing.............................................................................................................................................. 90
12.4.10 CSIO/UART Timing .................................................................................................................................................. 91
12.4.11 External Input Timing................................................................................................................................................ 99
12.4.12 Quadrature Position/Revolution Counter timing...................................................................................................... 100
12.4.13 I2C Timing............................................................................................................................................................... 102
12.4.14 ETM Timing ............................................................................................................................................................ 103
12.4.15 JTAG Timing........................................................................................................................................................... 104
12.5 12-bit A/D Converter.................................................................................................................................................. 105
12.6 USB characteristics ................................................................................................................................................... 108
12.7 Low-Voltage Detection Characteristics...................................................................................................................... 112
12.7.1 Low-Voltage Detection Reset..................................................................................................................................... 112
12.7.2 Interrupt of Low-Voltage Detection............................................................................................................................. 112
12.8 Flash Memory Write/Erase Characteristics ............................................................................................................... 113
12.8.1 Write / Erase time....................................................................................................................................................... 113
12.8.2 Write cycles and data hold time ................................................................................................................................. 113
12.9 Return Time from Low-Power Consumption Mode.................................................................................................... 114
12.9.1 Return Factor: Interrupt.............................................................................................................................................. 114
12.9.2 Return Factor: Reset.................................................................................................................................................. 116
Document Number: 002-05602 Rev. *C
Page 5 of 125
MB9B510T Series
13. Ordering Information .................................................................................................................................................... 118
14. Package Dimensions .................................................................................................................................................... 119
15. Major Changes .............................................................................................................................................................. 122
Document History............................................................................................................................................................... 124
Sales, Solutions, and Legal Information........................................................................................................................... 125
Document Number: 002-05602 Rev. *C
Page 6 of 125
MB9B510T Series
1. Product Lineup
Memory Size
Product name
MB9BF516S/T
MB9BF517S/T
MB9BF518S/T
On-chip Flash memory
On-chip RAM
512 Kbyte
64 Kbyte
768 Kbyte
96 Kbyte
1 Mbyte
128 Kbyte
Function
Product name
Pin count
MB9BF516S
MB9BF517S
MB9BF518S
MB9BF516T
MB9BF517T
MB9BF518T
144
176/192
Cortex-M3
144 MHz
CPU
Freq.
VCC: 2.7 V to 5.5 V
( USBVCC0:3.0 V to 3.6 V )
( USBVCC1:3.0 V to 3.6 V )
2 ch. (Max)
Power supply voltage range
USB2.0 (Device/Host)
CAN Interface
DMAC
2 ch. (Max)
8ch.
Addr:19-bit (Max)
R/Wdata:8-/16-bit (Max)
CS: 8 (Max)
Addr:25-bit (Max)
R/Wdata:8-/16-bit (Max)
CS: 8 (Max)
External Bus Interface
Support: SRAM, NOR & NAND Flash
Support: SRAM, NOR & NAND Flash
8 ch. (Max)
ch.4 to ch.7: FIFO (16steps × 9-bit)
ch.0 to ch.3: No FIFO
Multi-function Serial Interface
(UART/CSIO/LIN/I2C)
Base Timer
(PWC/ Reload timer/PWM/PPG)
16 ch. (Max)
3 units (Max)
A/D activation compare
3 ch.
Input capture
Free-run timer
Output compare
Waveform generator
PPG
4 ch.
3 ch.
6 ch.
3 ch.
3 ch.
QPRC
3 ch. (Max)
Dual Timer
1 unit
1 unit
Yes
Watch Counter
CRC Accelerator
Watchdog timer
External Interrupts
I/O ports
12-bit A/D converter
CSV (Clock Super Visor)
LVD (Low Voltage Detector)
1 ch. (SW) + 1 ch. (HW)
32 pins (Max)+ NMI × 1
122 pins (Max)
24 ch. (3 units)
154 pins (Max)
32 ch. (3 units)
Yes
2 ch.
High-speed
Built-in CR
4 MHz
100 kHz
SWJ-DP/ETM
Low-speed
Debug Function
Note:
−
All signals of the peripheral function in each product cannot be allocated by limiting the pins of package. It is necessary to use
the port relocate function of the General I/O port according to your function use.
See "12. Electrical Characteristics 12.4. AC Characteristics 12.4.3. Internal CR Oscillation Characteristics” for accuracy of
built-in CR.
Document Number: 002-05602 Rev. *C
Page 7 of 125
MB9B510T Series
2. Packages
MB9BF516S
MB9BF517S
MB9BF518S
MB9BF516T
MB9BF517T
MB9BF518T
Product name
Package
LQFP: LQS144 (0.5 mm pitch)
LQFP: LQP176 (0.5 mm pitch)
-
-
BGA:
LBE192 (0.8 mm pitch)
-
: Supported
Note:
−
See "14. Package Dimensions" for detailed information on each package.
Document Number: 002-05602 Rev. *C
Page 8 of 125
MB9B510T Series
3. Pin Assignment
LQP176
(TOP VIEW)
VCC
1
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
VSS
PA0/RTO20_0/TIOA08_0/FRCK1_0
PA1/RTO21_0/TIOA09_0/IC10_0
2
P83/UDP1
3
P82/UDM1
PA2/RTO22_0/TIOA10_0/IC11_0
4
USBVCC1
PA3/RTO23_0/TIOA11_0/IC12_0
5
PF6/FRCK2_0/NMIX
PA4/RTO24_0/TIOA12_0/IC13_0/RX0_2/INT03_0
PA5/RTO25_0/TIOA13_0/TX0_2/INT10_2
P05/TRACED0/TIOA05_2/SIN4_2/INT00_1
P06/TRACED1/TIOB05_2/SOT4_2/INT01_1
P07/TRACED2/ADTG_0/SCK4_2
6
P20/INT05_0/CROUT_0/UHCONX1/AIN1_1/MAD18_0
P21/SIN0_0/INT06_1/BIN1_1
7
8
P22/AN31/SOT0_0/TIOB07_1/ZIN1_1
P23/AN30/SCK0_0/TIOA07_1/RTO00_1
P24/AN29/SIN2_1/INT01_2/RX1_0/RTO01_1/MAD17_0
P25/AN28/SOT2_1/TX1_0/RTO02_1/MAD16_0
P26/AN27/SCK2_1/RTO03_1/MAD15_0
P27/AN26/INT02_2/RTO04_1/MAD14_0
P28/AN25/ADTG_4/INT09_0/RTO05_1/MAD13_0
P29/AN24/MAD12_0
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
P08/TRACED3/TIOA00_2/CTS4_2
P09/TRACECLK/TIOB00_2/RTS4_2/DTTI2X_0
P50/INT00_0/AIN0_2/SIN3_1/RTO10_0/IC20_0/MOEX_0
P51/INT01_0/BIN0_2/SOT3_1/RTO11_0/IC21_0/MWEX_0
P52/INT02_0/ZIN0_2/SCK3_1/RTO12_0/IC22_0/MDQM0_0
P53/SIN6_0/TIOA01_2/INT07_2/RTO13_0/IC23_0/MDQM1_0
P54/SOT6_0/TIOB01_2/RTO14_0/MALE_0
P55/SCK6_0/ADTG_1/RTO15_0/MRDY_0
P56/SIN1_0/INT08_2/TIOA09_2/DTTI1X_0/MNALE_0
P57/SOT1_0/TIOB09_2/INT16_1/MNCLE_0
P58/SCK1_0/TIOA11_2/INT17_1/MNWEX_0
P59/SIN7_0/RX1_1/TIOB11_2/INT09_2/MNREX_0
P5A/SOT7_0/TX1_1/TIOA13_1/INT18_1/MCSX0_0
P5B/SCK7_0/TIOB13_1/INT19_1/MCSX1_0
P5C/TIOA06_2/INT28_0/IC20_1
PB7/AN23/TIOB12_1/INT23_0/ZIN2_2
PB6/AN22/TIOA12_1/SCK0_2/INT22_0/BIN2_2
PB5/AN21/TIOB11_1/SOT0_2/INT21_0/AIN2_2
PB4/AN20/TIOA11_1/SIN0_2/INT20_0
PB3/AN19/TIOB10_1/INT19_0
PB2/AN18/TIOA10_1/SCK7_2/INT18_0
PB1/AN17/TIOB09_1/SOT7_2/INT17_0
PB0/AN16/TIOA09_1/SIN7_2/INT16_0
VSS
LQFP - 176
AVSS
P5D/TIOB06_2/INT29_0/DTTI2X_1
AVRH
VSS
AVCC
P30/AIN0_0/TIOB00_1/INT03_2
P1F/AN15/ADTG_5/INT29_1/TIOB15_2/FRCK0_1/MAD11_0
P1E/AN14/RTS4_1/INT28_1/TIOA15_2/DTTI0X_1/MAD10_0
P1D/AN13/CTS4_1/INT27_1/TIOB14_2/IC03_1/MAD09_0
P1C/AN12/SCK4_1/INT26_1/TIOA14_2/IC02_1/MAD08_0
P1B/AN11/SOT4_1/INT25_1/TIOB13_2/IC01_1/MAD07_0
P1A/AN10/SIN4_1/INT05_1/TIOA13_2/IC00_1/MAD06_0
P19/AN09/SCK2_2/INT22_1/MAD05_0
P18/AN08/SOT2_2/INT21_1/MAD04_0
P17/AN07/SIN2_2/INT04_1/MAD03_0
P16/AN06/SCK0_1/INT20_1/MAD02_0
P15/AN05/SOT0_1/IC03_2/MAD01_0
P14/AN04/SIN0_1/INT03_1/IC02_2/MAD00_0
P13/AN03/SCK1_1/IC01_2/MCSX4_0
P12/AN02/SOT1_1/TX1_2/IC00_2/MCSX5_0
P11/AN01/SIN1_1/INT02_1/RX1_2/FRCK0_2/MCSX6_0
P10/AN00/MCSX7_0
P31/BIN0_0/TIOB01_1/SCK6_1/INT04_2
P32/ZIN0_0/TIOB02_1/SOT6_1/INT05_2
P33/INT04_0/TIOB03_1/SIN6_1/ADTG_6
P34/FRCK0_0/TIOB04_1/TX0_1
P35/IC03_0/TIOB05_1/RX0_1/INT08_1
P36/IC02_0/SIN5_2/INT09_1/TIOA12_2/MCSX2_0
P37/IC01_0/SOT5_2/INT10_1/TIOB12_2/MCSX3_0
P38/IC00_0/SCK5_2/INT11_1/MCLKOUT_0
P39/DTTI0X_0/ADTG_2
98
97
96
P3A/RTO00_0/TIOA00_1
95
P3B/RTO01_0/TIOA01_1
94
P3C/RTO02_0/TIOA02_1
93
P3D/RTO03_0/TIOA03_1
92
P3E/RTO04_0/TIOA04_1
91
P3F/RTO05_0/TIOA05_1
90
VSS
89
VCC
Note:
−
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these
pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register
(EPFR) to select the pin. TIOA09_0, TIOA09_1, and TIOA09_2 cannot be used as the external startup trigger input (TGIN
signal) at I/O mode 1 (timer full mode) of the Base Timer. See "Base Timer" in "7. Handling Devices" for details.
Document Number: 002-05602 Rev. *C
Page 9 of 125
MB9B510T Series
LQS144
(TOP VIEW)
VCC
PA0/RTO20_0/TIOA08_0/FRCK1_0
1
108
107
106
105
104
103
102
101
100
99
VSS
2
P83/UDP1
PA1/RTO21_0/TIOA09_0/IC10_0
3
P82/UDM1
PA2/RTO22_0/TIOA10_0/IC11_0
4
USBVCC1
PA3/RTO23_0/TIOA11_0/IC12_0
5
PF6/FRCK2_0/NMIX
PA4/RTO24_0/TIOA12_0/IC13_0/RX0_2/INT03_0
PA5/RTO25_0/TIOA13_0/TX0_2/INT10_2
P05/TRACED0/TIOA05_2/SIN4_2/INT00_1
P06/TRACED1/TIOB05_2/SOT4_2/INT01_1
P07/TRACED2/ADTG_0/SCK4_2
6
P20/INT05_0/CROUT_0/UHCONX1/AIN1_1/MAD18_0
P21/SIN0_0/INT06_1/BIN1_1
7
8
P22/AN31/SOT0_0/TIOB07_1/ZIN1_1
P23/AN30/SCK0_0/TIOA07_1/RTO00_1
P24/AN29/SIN2_1/INT01_2/RX1_0/RTO01_1/MAD17_0
P25/AN28/SOT2_1/TX1_0/RTO02_1/MAD16_0
P26/AN27/SCK2_1/RTO03_1/MAD15_0
P27/AN26/INT02_2/RTO04_1/MAD14_0
P28/AN25/ADTG_4/INT09_0/RTO05_1/MAD13_0
P29/AN24/MAD12_0
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
P08/TRACED3/TIOA00_2/CTS4_2
98
P09/TRACECLK/TIOB00_2/RTS4_2/DTTI2X_0
P50/INT00_0/AIN0_2/SIN3_1/RTO10_0/IC20_0/MOEX_0
P51/INT01_0/BIN0_2/SOT3_1/RTO11_0/IC21_0/MWEX_0
P52/INT02_0/ZIN0_2/SCK3_1/RTO12_0/IC22_0/MDQM0_0
P53/SIN6_0/TIOA01_2/INT07_2/RTO13_0/IC23_0/MDQM1_0
P54/SOT6_0/TIOB01_2/RTO14_0/MALE_0
P55/SCK6_0/ADTG_1/RTO15_0/MRDY_0
P56/SIN1_0/INT08_2/TIOA09_2/DTTI1X_0/MNALE_0
P57/SOT1_0/TIOB09_2/INT16_1/MNCLE_0
P58/SCK1_0/TIOA11_2/INT17_1/MNWEX_0
P59/SIN7_0/RX1_1/TIOB11_2/INT09_2/MNREX_0
P5A/SOT7_0/TX1_1/TIOA13_1/INT18_1/MCSX0_0
P5B/SCK7_0/TIOB13_1/INT19_1/MCSX1_0
VSS
97
96
95
94
93
VSS
92
AVSS
91
AVRH
LQFP - 144
90
AVCC
89
P1F/AN15/ADTG_5/INT29_1/TIOB15_2/FRCK0_1/MAD11_0
P1E/AN14/RTS4_1/INT28_1/TIOA15_2/DTTI0X_1/MAD10_0
P1D/AN13/CTS4_1/INT27_1/TIOB14_2/IC03_1/MAD09_0
P1C/AN12/SCK4_1/INT26_1/TIOA14_2/IC02_1/MAD08_0
P1B/AN11/SOT4_1/INT25_1/TIOB13_2/IC01_1/MAD07_0
P1A/AN10/SIN4_1/INT05_1/TIOA13_2/IC00_1/MAD06_0
P19/AN09/SCK2_2/INT22_1/MAD05_0
P18/AN08/SOT2_2/INT21_1/MAD04_0
P17/AN07/SIN2_2/INT04_1/MAD03_0
P16/AN06/SCK0_1/INT20_1/MAD02_0
P15/AN05/SOT0_1/IC03_2/MAD01_0
P14/AN04/SIN0_1/INT03_1/IC02_2/MAD00_0
P13/AN03/SCK1_1/IC01_2/MCSX4_0
P12/AN02/SOT1_1/TX1_2/IC00_2/MCSX5_0
P11/AN01/SIN1_1/INT02_1/RX1_2/FRCK0_2/MCSX6_0
P10/AN00/MCSX7_0
88
87
86
85
84
P36/IC02_0/SIN5_2/INT09_1/TIOA12_2/MCSX2_0
P37/IC01_0/SOT5_2/INT10_1/TIOB12_2/MCSX3_0
P38/IC00_0/SCK5_2/INT11_1/MCLKOUT_0
P39/DTTI0X_0/ADTG_2
83
82
81
80
P3A/RTO00_0/TIOA00_1
79
P3B/RTO01_0/TIOA01_1
78
P3C/RTO02_0/TIOA02_1
77
P3D/RTO03_0/TIOA03_1
76
P3E/RTO04_0/TIOA04_1
75
P3F/RTO05_0/TIOA05_1
74
VSS
73
VCC
Note:
−
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these
pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register
(EPFR) to select the pin. TIOA09_0 and TIOA09_2 cannot be used as the external startup trigger input (TGIN signal) at I/O
mode 1 (timer full mode) of the Base Timer. See "Base Timer" in "7. Handling Devices" for details.
Document Number: 002-05602 Rev. *C
Page 10 of 125
MB9B510T Series
LBE192
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
USB
VCC0
UDP0 UDM0
A
B
C
D
E
F
VSS PCD PCB VSS VCC PC8 VSS TCK VCC
TRSTX
VSS PA0 PF5 PF3 P61 PD1 PCA PC1 P95 P92 TDO TMS
VCC PA1 PA2 PF4 P60 PD2 PCC PC5 PC0 P93 P90 TDI PF6
PA5 PA4 P05 P06 PA3 PD3 PCE PC6 PC2 P94 P91 P21 P20
VSS P07 P08 P09 P50 P62 PCF PC7 PC3 P25 P24 P23 P22
VSS
UDP1
UDM1
USB
VCC1
P51 P52 P53 P54 P55 P56 PD0 PC9 PC4 P29 P28 P27 P26 VSS
VSS P57 P58 P59 P5A P5B VSS VSS PB7 PB6 PB5 PB4 PB3 AVSS
P5C P5D P30 P31 P32 P33 VSS VSS P1F P1E PB2 PB1 PB0 AVRH
VSS P37 P36 P35 P34 P70 VSS P76 P1D P1C P1B P1A P19 AVCC
P38 P39 P3A P3B P4A P4E VSS P74 P7B P7F P18 P16 P15 P17
P3C P3D P3E P43 P49 P4D VSS P73 P7A P7E P14 P13 P12 VSS
VSS P3F P42 P44 P48 P4C VSS P72 P79 PF0 PF2 P11 P10 VCC
VCC P40 P41 P45 INITX P4B VSS P71 P78 P7D PF1 MD0 MD1 VSS
G
H
J
K
L
M
N
P
C
VSS VCC X0A X1A VSS P75 P77 P7C VSS X0
X1
Note:
−
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these
pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register
(EPFR) to select the pin. TIOA09_0, TIOA09_1, and TIOA09_2 cannot be used as the external startup trigger input (TGIN
signal) at I/O mode 1 (timer full mode) of the Base Timer. See "Base Timer" in "7. Handling Devices" for details.
Document Number: 002-05602 Rev. *C
Page 11 of 125
MB9B510T Series
4. List of Pin Functions
List of pin numbers
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins,
there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to
select the pin.
Pin No
I/O circuit
type
Pin state
type
Pin Name
LQFP-176
LQFP-144
BGA-192
1
2
1
2
C1
VCC
PA0
-
RTO20_0
TIOA08_0
FRCK1_0
PA1
RTO21_0
TIOA09_0
IC10_0
PA2
B2
G
G
G
G
I
I
I
I
3
4
5
3
4
5
C2
C3
D5
RTO22_0
TIOA10_0
IC11_0
PA3
RTO23_0
TIOA11_0
IC12_0
PA4
RTO24_0
TIOA12_0
RX0_2
6
6
D2
G
H
IC13_0
INT03_0
PA5
RTO25_0
TX0_2
TIOA13_0
INT10_2
P05
TRACED0
TIOA05_2
SIN4_2
7
8
7
8
D1
D3
G
E
H
F
INT00_1
P06
TRACED1
TIOB05_2
SOT4_2
INT01_1
P07
TRACED2
ADTG_0
SCK4_2
9
9
D4
E2
E
E
F
10
10
G
Document Number: 002-05602 Rev. *C
Page 12 of 125
MB9B510T Series
Pin No
I/O circuit
type
Pin state
type
Pin Name
LQFP-176
LQFP-144
BGA-192
P08
TRACED3
TIOA00_2
CTS4_2
P09
TRACECLK
TIOB00_2
RTS4_2
DTTI2X_0
P50
11
12
11
12
E3
E
E
G
G
E4
INT00_0
AIN0_2
SIN3_1
RTO10_0
IC20_0
13
14
15
16
13
14
15
16
E5
F1
F2
F3
E
E
E
E
H
H
H
H
MOEX_0
P51
INT01_0
BIN0_2
SOT3_1
RTO11_0
IC21_0
MWEX_0
P52
INT02_0
ZIN0_2
SCK3_1
RTO12_0
IC22_0
MDQM0_0
P53
SIN6_0
TIOA01_2
INT07_2
RTO13_0
IC23_0
MDQM1_0
P54
SOT6_0
TIOB01_2
RTO14_0
MALE_0
P55
SCK6_0
ADTG_1
RTO15_0
MRDY_0
P56
17
18
17
18
F4
F5
E
E
I
I
SIN1_0
INT08_2
TIOA09_2
DTTI1X_0
MNALE_0
19
19
F6
E
H
Document Number: 002-05602 Rev. *C
Page 13 of 125
MB9B510T Series
Pin No
I/O circuit
type
Pin state
type
Pin Name
LQFP-176
LQFP-144
BGA-192
P57
SOT1_0
TIOB09_2
INT16_1
MNCLE_0
P58
SCK1_0
TIOA11_2
INT17_1
MNWEX_0
P59
SIN7_0
RX1_1
TIOB11_2
INT09_2
MNREX_0
P5A
SOT7_0
TX1_1
TIOA13_1
INT18_1
MCSX0_0
P5B
SCK7_0
TIOB13_1
INT19_1
MCSX1_0
P5C
TIOA06_2
INT28_0
IC20_1
P5D
20
21
20
21
G2
E
E
H
H
G3
G4
22
23
22
23
E
H
G5
E
E
H
H
24
25
24
-
G6
H1
E
E
H
H
TIOB06_2
INT29_0
DTTI2X_1
VSS
26
27
28
-
H2
J1
25
-
-
P30
AIN0_0
TIOB00_1
INT03_2
P31
BIN0_0
TIOB01_1
SCK6_1
INT04_2
P32
ZIN0_0
TIOB02_1
SOT6_1
INT05_2
H3
E
E
H
H
29
30
-
-
H4
H5
E
H
Document Number: 002-05602 Rev. *C
Page 14 of 125
MB9B510T Series
Pin No
I/O circuit
type
Pin state
type
Pin name
LQFP-176
LQFP-144
BGA-192
P33
INT04_0
TIOB03_1
SIN6_1
ADTG_6
P34
FRCK0_0
TX0_1
TIOB04_1
P35
31
32
33
-
-
-
H6
J4
J4
E
E
E
H
I
IC03_0
RX0_1
H
TIOB05_1
INT08_1
P36
IC02_0
SIN5_2
INT09_1
TIOA12_2
MCSX2_0
P37
34
26
J3
E
H
IC01_0
SOT5_2
INT10_1
TIOB12_2
MCSX3_0
P38
IC00_0
SCK5_2
INT11_1
MCLKOUT_0
P39
35
36
27
28
J2
E
E
H
H
K1
37
38
29
30
K2
K3
DTTI0X_0
ADTG_2
P3A
RTO00_0
TIOA00_1
P3B
E
I
I
G
RTO01_0
39
31
K4
G
I
TIOA01_1
P3C
40
41
42
32
33
34
L1
L2
L3
RTO02_0
TIOA02_1
P3D
RTO03_0
TIOA03_1
P3E
G
G
G
I
I
I
RTO04_0
TIOA04_1
Document Number: 002-05602 Rev. *C
Page 15 of 125
MB9B510T Series
Pin No
I/O circuit
type
Pin state
type
Pin name
LQFP-176
LQFP-144
BGA-192
M2
P3F
43
35
RTO05_0
TIOA05_1
VSS
G
I
44
45
36
37
M1
N1
-
-
VCC
P40
TIOA00_0
RTO10_1
INT12_1
P41
46
38
N2
G
H
TIOA01_0
RTO11_1
INT13_1
P42
TIOA02_0
RTO12_1
P43
TIOA03_0
RTO13_1
ADTG_7
P44
47
48
49
39
40
41
N3
M3
L4
G
G
G
H
I
I
50
51
42
43
M4
N4
TIOA04_0
RTO14_1
P45
TIOA05_0
RTO15_1
C
G
G
I
I
52
53
54
44
45
46
P2
P3
P4
-
-
-
VSS
VCC
P46
X0A
55
47
P5
D
M
P47
X1A
INITX
56
57
48
49
P6
N5
D
B
N
C
P48
DTTI1X_1
INT14_1
SIN3_2
P49
58
50
M5
E
H
TIOB00_0
IC10_1
AIN0_1
SOT3_2
P4A
59
51
L5
E
I
TIOB01_0
IC11_1
BIN0_1
SCK3_2
MADATA00_0
60
52
K5
E
I
Document Number: 002-05602 Rev. *C
Page 16 of 125
MB9B510T Series
Pin No
I/O circuit
type
Pin state
type
Pin name
LQFP-176
LQFP-144
BGA-192
P4B
TIOB02_0
IC12_1
ZIN0_1
MADATA01_0
P4C
TIOB03_0
IC13_1
SCK7_1
AIN1_2
MADATA02_0
P4D
TIOB04_0
FRCK1_1
SOT7_1
BIN1_2
MADATA03_0
P4E
61
62
53
54
N6
E
E
I
I
M6
L6
63
64
55
56
E
E
I
TIOB05_0
INT06_2
SIN7_1
K6
H
ZIN1_2
MADATA04_0
P70
TIOA04_2
TX0_0
MADATA05_0
P71
INT13_2
TIOB04_2
RX0_0
65
66
57
58
J6
E
E
I
N8
H
MADATA06_0
P72
SIN2_0
67
59
M8
INT14_2
AIN2_0
E
H
MADATA07_0
P73
SOT2_0
INT15_2
BIN2_0
MADATA08_0
P74
SCK2_0
ZIN2_0
MADATA09_0
P75
68
69
70
60
61
62
L8
K8
P8
E
E
E
H
I
SIN3_0
ADTG_8
INT07_1
MADATA10_0
H
Document Number: 002-05602 Rev. *C
Page 17 of 125
MB9B510T Series
I/O
Pin No
Pin state
circuit
type
Pin name
LQFP-176
LQFP-144
BGA-192
type
P76
SOT3_0
TIOA07_2
INT11_2
MADATA11_0
P77
71
63
J8
E
H
SCK3_0
TIOB07_2
INT12_2
MADATA12_0
P78
AIN1_0
TIOA15_0
MADATA13_0
P79
BIN1_0
TIOB15_0
INT23_1
MADATA14_0
VSS
72
73
74
64
65
66
P9
N9
E
E
E
H
I
M9
H
-
-
-
-
E1
G1
-
-
VSS
P7A
ZIN1_0
75
67
L9
E
H
INT24_1
MADATA15_0
P7B
76
77
-
-
K9
TIOB07_0
INT10_0
P7C
TIOA07_0
INT11_0
P7D
E
E
H
H
P10
TIOA14_1
FRCK2_1
INT12_0
P7E
TIOB14_1
IC21_1
INT24_0
P7F
TIOA15_1
IC22_1
78
79
80
-
-
-
N10
L10
K10
E
E
E
H
H
H
INT25_0
PF0
TIOB15_1
SIN1_2
INT13_0
IC23_1
81
82
-
-
M10
N11
I*
I*
H
H
PF1
TIOA08_1
SOT1_2
INT14_0
Document Number: 002-05602 Rev. *C
Page 18 of 125
MB9B510T Series
Pin No
I/O circuit
type
Pin state
type
Pin name
LQFP-176
LQFP-144
BGA-192
PF2
TIOB08_1
SCK1_2
INT15_0
PE0
MD1
MD0
83
-
M11
I*
H
84
85
86
68
69
70
N13
N12
P12
C
J
P
D
A
PE2
X0
A
PE3
X1
87
71
P13
A
B
88
89
-
72
73
-
N14
M14
L7
VSS
VCC
VSS
VSS
-
-
-
-
-
-
K7
P10
90
74
M13
AN00
MCSX7_0
P11
F
F
K
L
AN01
SIN1_1
RX1_2
INT02_1
FRCK0_2
MCSX6_0
P12
91
75
M12
AN02
SOT1_1
TX1_2
IC00_2
MCSX5_0
P13
92
93
94
76
77
78
L13
L12
L11
F
F
F
K
K
L
AN03
SCK1_1
IC01_2
MCSX4_0
P14
AN04
SIN0_1
INT03_1
IC02_2
MAD00_0
P15
AN05
95
96
79
80
K13
K12
SOT0_1
IC03_2
MAD01_0
P16
F
F
K
L
AN06
SCK0_1
INT20_1
MAD02_0
Document Number: 002-05602 Rev. *C
Page 19 of 125
MB9B510T Series
Pin No
I/O circuit
type
Pin state
type
Pin name
LQFP-176
LQFP-144
BGA-192
P17
AN07
97
81
K14
SIN2_2
INT04_1
MAD03_0
VSS
VSS
VSS
F
L
-
-
-
-
-
-
P7
P11
L14
-
-
-
P18
AN08
98
99
82
83
K11
J13
SOT2_2
INT21_1
MAD04_0
P19
F
F
L
L
AN09
SCK2_2
INT22_1
MAD05_0
P1A
AN10
SIN4_1
INT05_1
TIOA13_2
IC00_1
MAD06_0
P1B
100
101
102
103
104
84
85
86
87
88
J12
J11
J10
J9
F
F
F
F
F
L
L
L
L
L
AN11
SOT4_1
INT25_1
TIOB13_2
IC01_1
MAD07_0
P1C
AN12
SCK4_1
INT26_1
TIOA14_2
IC02_1
MAD08_0
P1D
AN13
CTS4_1
INT27_1
TIOB14_2
IC03_1
MAD09_0
P1E
AN14
RTS4_1
INT28_1
TIOA15_2
DTTI0X_1
MAD10_0
H10
Document Number: 002-05602 Rev. *C
Page 20 of 125
MB9B510T Series
Pin No
I/O circuit
type
Pin state
type
Pin name
LQFP-176
LQFP-144
BGA-192
P1F
AN15
ADTG_5
INT29_1
TIOB15_2
FRCK0_1
MAD11_0
AVCC
AVRH
AVSS
VSS
105
89
H9
F
L
106
107
108
109
90
91
92
93
J14
H14
G14
F14
-
-
-
-
PB0
AN16
110
111
-
-
H13
H12
TIOA09_1
SIN7_2
INT16_0
PB1
F
F
L
L
AN17
TIOB09_1
SOT7_2
INT17_0
PB2
AN18
112
113
114
-
-
-
H11
G13
G12
TIOA10_1
SCK7_2
INT18_0
PB3
F
F
F
L
L
L
AN19
TIOB10_1
INT19_0
PB4
AN20
TIOA11_1
SIN0_2
INT20_0
PB5
AN21
TIOB11_1
SOT0_2
INT21_0
AIN2_2
VSS
VSS
PB6
AN22
TIOA12_1
SCK0_2
INT22_0
BIN2_2
115
-
G11
F
F
L
L
-
-
-
-
G7
J7
-
-
116
-
G10
Document Number: 002-05602 Rev. *C
Page 21 of 125
MB9B510T Series
Pin No
I/O circuit
type
Pin state
type
Pin name
LQFP-176
LQFP-144
BGA-192
PB7
AN23
117
-
G9
TIOB12_1
INT23_0
ZIN2_2
P29
AN24
MAD12_0
P28
F
F
L
118
119
94
F10
F11
K
AN25
ADTG_4
INT09_0
RTO05_1
MAD13_0
P27
95
F
L
AN26
120
121
96
97
F12
F13
INT02_2
RTO04_1
MAD14_0
P26
F
F
L
AN27
SCK2_1
RTO03_1
MAD15_0
P25
K
AN28
SOT2_1
TX1_0
RTO02_1
MAD16_0
P24
122
98
99
E10
F
K
AN29
SIN2_1
RX1_0
INT01_2
RTO01_1
MAD17_0
P23
123
124
E11
E12
F
F
L
AN30
100
SCK0_0
TIOA07_1
RTO00_1
P22
K
AN31
125
126
101
102
E13
D12
SOT0_0
TIOB07_1
ZIN1_1
P21
SIN0_0
INT06_1
BIN1_1
F
E
K
H
Document Number: 002-05602 Rev. *C
Page 22 of 125
MB9B510T Series
Pin No
I/O circuit
type
Pin state
type
Pin name
LQFP-176
LQFP-144
BGA-192
P20
INT05_0
CROUT_0
UHCONX1
AIN1_1
MAD18_0
PF6
127
103
D13
E
I*
H
J
128
104
C13
FRCK2_0
NMIX
129
130
105
106
E14
D14
USBVCC1
P82
UDM1
P83
UDP1
-
H
H
O
O
131
107
C14
132
133
108
109
B14
A13
VSS
VCC
-
-
P00
TRSTX
P01
TCK
SWCLK
P02
TDI
P03
TMS
134
135
136
137
110
111
112
113
B13
A12
C12
B12
E
E
E
E
E
E
E
E
SWDIO
P04
138
114
B11
TDO
SWO
P90
TIOB08_0
RTO20_1
INT30_0
MAD19_0
VSS
E
E
E
H
139
-
-
-
C11
A8
-
P91
TIOB09_0
RTO21_1
INT31_0
MAD20_0
P92
140
141
142
-
-
-
D11
B10
C10
E
E
E
H
I
TIOB10_0
RTO22_1
SIN5_1
MAD21_0
P93
TIOB11_0
RTO23_1
SOT5_1
MAD22_0
I
Document Number: 002-05602 Rev. *C
Page 23 of 125
MB9B510T Series
Pin No
I/O circuit
type
Pin state
type
Pin name
LQFP-176
LQFP-144
BGA-192
P94
TIOB12_0
RTO24_1
SCK5_1
INT26_0
MAD23_0
P95
TIOB13_0
RTO25_1
INT27_0
MAD24_0
PC0
143
-
-
D10
E
H
144
B9
E
H
145
146
147
115
116
117
C9
B8
D9
K
K
K
Q
Q
Q
PC1
PC2
PC3
TIOA06_1
PC4
TIOA08_2
PC5
TIOA10_2
VSS
PC6
TIOA14_0
PC7
CROUT_1
PC8
PC9
PCA
VCC
VSS
PCB
PCC
PCD
148
149
118
119
E9
F9
K
K
K
Q
Q
Q
150
-
120
-
C8
A5
D8
-
151
121
K
L
Q
Q
152
122
E8
153
154
155
156
157
158
159
160
123
124
125
126
127
128
129
130
A10
F8
B7
A9
A11
A7
K
K
K
Q
Q
Q
-
-
L
K
K
Q
Q
Q
C7
A6
PCE
161
162
131
132
D7
E7
RTS4_0
TIOB06_1
PCF
CTS4_0
TIOB08_2
PD0
L
L
Q
Q
SCK4_0
TIOB10_2
INT30_1
PD1
SOT4_0
TIOB14_0
INT31_1
VSS
163
164
133
134
F7
B6
L
L
R
R
-
-
-
-
-
-
-
-
N7
G8
H7
H8
-
-
-
-
VSS
VSS
VSS
Document Number: 002-05602 Rev. *C
Page 24 of 125
MB9B510T Series
Pin No
I/O circuit
type
Pin state
type
Pin name
LQFP-176
LQFP-144
BGA-192
PD2
SIN4_0
TIOA03_2
INT00_2
PD3
TIOB03_2
P62
SCK5_0
ADTG_3
P61
165
135
C6
L
R
166
167
136
137
D6
E6
L
Q
Q
E
SOT5_0
TIOB02_2
UHCONX0
P60
SIN5_0
TIOA02_2
INT15_1
PF3
168
169
138
139
B5
C5
E
E
I
H
TIOA06_0
SIN6_2
INT06_0
AIN2_1
PF4
170
-
B4
I*
H
TIOB06_0
SOT6_2
INT07_0
BIN2_1
PF5
SCK6_2
INT08_0
ZIN2_1
USBVCC0
P80
171
172
-
C4
B3
I*
I*
H
H
140
173
174
141
142
A4
A3
-
H
H
O
O
UDM0
P81
UDP0
VSS
175
143
A2
B1
176
-
144
-
-
-
M7
VSS
*: 5 V tolerant I/O
Document Number: 002-05602 Rev. *C
Page 25 of 125
MB9B510T Series
List of functions
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins,
there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to
select the pin.
Pin No
Module
ADC
Pin name
ADTG_0
Function
LQFP-176 LQFP-144 BGA-192
10
18
37
167
119
105
31
49
70
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
10
18
29
137
95
89
-
E2
F5
K2
E6
F11
H9
H6
L4
P8
M13
M12
L13
L12
L11
K13
K12
K14
K11
J13
J12
J11
J10
J9
ADTG_1
ADTG_2
ADTG_3
ADTG_4
ADTG_5
ADTG_6
ADTG_7
ADTG_8
AN00
AN01
AN02
AN03
AN04
AN05
AN06
AN07
AN08
AN09
AN10
AN11
AN12
AN13
AN14
AN15
AN16
AN17
AN18
AN19
AN20
AN21
AN22
AN23
AN24
AN25
AN26
AN27
AN28
A/D converter external trigger input pin
41
62
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
-
H10
H9
A/D converter analog input pin
ANxx describes ADC ch.xx
H13
H12
H11
G13
G12
G11
G10
G9
F10
F11
F12
F13
E10
E11
E12
E13
-
-
-
-
-
-
-
94
95
96
97
98
99
100
101
AN29
AN30
AN31
Document Number: 002-05602 Rev. *C
Page 26 of 125
MB9B510T Series
Pin No
Module
Pin name
TIOA0_0
TIOA0_1
TIOA0_2
TIOB0_0
TIOB0_1
TIOB0_2
TIOA1_0
Function
LQFP-176 LQFP-144
BGA-192
Base Timer
0
46
38
11
59
28
12
47
38
30
11
51
-
12
39
31
N2
K3
E3
L5
H3
E4
N3
Base timer ch.0 TIOA pin
Base timer ch.0 TIOB pin
Base timer ch.1 TIOA pin
Base Timer
1
TIOA1_1
39
K4
TIOA1_2
TIOB1_0
TIOB1_1
TIOB1_2
TIOA2_0
TIOA2_1
TIOA2_2
TIOB2_0
TIOB2_1
TIOB2_2
TIOA3_0
TIOA3_1
TIOA3_2
TIOB3_0
TIOB3_1
TIOB3_2
TIOA4_0
TIOA4_1
TIOA4_2
TIOB4_0
TIOB4_1
TIOB4_2
TIOA5_0
TIOA5_1
TIOA5_2
TIOB5_0
TIOB5_1
TIOB5_2
TIOA6_0
TIOA6_1
TIOA6_2
TIOB6_0
TIOB6_1
TIOB6_2
16
60
29
17
48
40
169
61
30
168
49
41
165
62
31
166
50
42
65
63
32
66
51
43
8
16
52
-
17
40
32
139
53
-
138
41
33
135
54
-
136
42
34
57
55
-
58
43
35
8
56
-
9
-
118
-
-
F3
K5
H4
F4
M3
L1
C5
N6
H5
B5
L4
Base timer ch.1 TIOB pin
Base timer ch.2 TIOA pin
Base timer ch.2 TIOB pin
Base timer ch.3 TIOA pin
Base timer ch.3 TIOB pin
Base timer ch.4 TIOA pin
Base timer ch.4 TIOB pin
Base timer ch.5 TIOA pin
Base timer ch.5 TIOB pin
Base timer ch.6 TIOA pin
Base timer ch.6 TIOB pin
Base Timer
2
Base Timer
3
L2
C6
M6
H6
D6
M4
L3
J6
L6
J5
N8
N4
M2
D3
K6
J4
D4
B4
E9
H1
C4
D7
H2
Base Timer
4
Base Timer
5
64
33
9
170
148
25
171
161
26
Base Timer
6
131
-
Document Number: 002-05602 Rev. *C
Page 27 of 125
MB9B510T Series
Pin No
Module
Pin name
TIOA07_0
TIOA07_1
TIOA07_2
TIOB07_0
TIOB07_1
TIOB07_2
TIOA08_0
Function
LQFP-176 LQFP-144
BGA-192
Base Timer
7
77
124
71
76
125
72
-
100
63
-
101
64
2
P10
E12
J8
K9
E13
P9
Base timer ch.7 TIOA pin
Base timer ch.7 TIOB pin
Base timer ch.8 TIOA pin
Base Timer
8
2
82
B2
N11
TIOA08_1
-
TIOA08_2
TIOB08_0
TIOB08_1
TIOB08_2
TIOA09_0
TIOA09_1
TIOA09_2
TIOB09_0
TIOB09_1
TIOB09_2
TIOA10_0
TIOA10_1
TIOA10_2
TIOB10_0
TIOB10_1
TIOB10_2
TIOA11_0
TIOA11_1
TIOA11_2
TIOB11_0
TIOB11_1
TIOB11_2
TIOA12_0
TIOA12_1
TIOA12_2
TIOB12_0
TIOB12_1
TIOB12_2
TIOA13_0
TIOA13_1
TIOA13_2
TIOB13_0
TIOB13_1
TIOB13_2
149
139
83
162
3
110
19
140
111
20
119
-
-
132
3
-
19
-
-
20
4
-
120
-
-
133
5
-
21
-
-
22
6
-
F9
C11
M11
E7
C2
H13
F6
D11
H12
G2
C3
H11
C8
B10
G13
F7
D5
G12
G3
C10
G11
G4
D2
G10
J3
Base timer ch.8 TIOB pin
Base timer ch.9 TIOA pin
Base timer ch.9 TIOB pin
Base timer ch.10 TIOA pin
Base timer ch.10 TIOB pin
Base timer ch.11 TIOA pin
Base timer ch.11 TIOB pin
Base timer ch.12 TIOA pin
Base timer ch.12 TIOB pin
Base timer ch.13 TIOA pin
Base timer ch.13 TIOB pin
Base Timer
9
Base Timer
10
4
112
150
141
113
163
5
114
21
142
115
22
6
116
34
143
117
35
Base Timer
11
Base Timer
12
26
-
-
27
7
23
84
-
D10
G9
J2
D1
G5
J12
B9
G6
Base Timer
13
7
23
100
144
24
24
85
101
J11
Document Number: 002-05602 Rev. *C
Page 28 of 125
MB9B510T Series
Pin No
LQFP-144
Module
Pin name
TIOA14_0
TIOA14_1
TIOA14_2
TIOB14_0
TIOB14_1
TIOB14_2
TIOA15_0
Function
LQFP-176
BGA-192
Base Timer
14
151
78
102
164
79
103
73
80
104
74
81
105
65
32
7
66
33
6
122
23
92
123
22
121
-
86
134
-
87
65
-
88
66
-
89
57
-
7
58
-
D8
N10
J10
B6
L10
J9
Base timer ch.14 TIOA pin
Base timer ch.14 TIOB pin
Base timer ch.15 TIOA pin
Base Timer
15
N9
TIOA15_1
K10
H10
M9
M10
H9
J6
J5
D1
N8
TIOA15_2
TIOB15_0
TIOB15_1
TIOB15_2
TX0_0
TX0_1
TX0_2
RX0_0
RX0_1
RX0_2
TX1_0
TX1_1
TX1_2
RX1_0
RX1_1
RX1_2
Base timer ch.15 TIOB pin
CAN interface ch.0 TX output
CAN interface ch.0 RX output
CAN interface ch.1 TX output
CAN interface ch.1 RX output
CAN 0
J4
D2
6
CAN 1
98
23
76
99
22
75
111
113
114
111
112
114
113
12
8
E10
G5
L13
E11
G4
M12
A12
B12
B11
A12
C12
B11
B12
E4
91
Debugger
SWCLK
SWDIO
SWO
TCK
TDI
Serial wire debug interface clock input
Serial wire debug interface data input / output
Serial wire viewer output
JTAG test clock input
JTAG test data input
JTAG debug data output
JTAG test mode state input/output
Trace CLK output of ETM
135
137
138
135
136
138
137
12
8
9
10
11
TDO
TMS
TRACECLK
TRACED0
TRACED1
TRACED2
TRACED3
TRSTX
D3
D4
E2
E3
9
Trace data output of ETM
JTAG test reset Input
10
11
110
134
B13
Document Number: 002-05602 Rev. *C
Page 29 of 125
MB9B510T Series
Pin No
Module
Pin name
MAD00_0
Function
LQFP-176 LQFP-144 BGA-192
External
Bus
94
95
96
97
98
78
79
80
81
82
83
84
85
86
87
88
89
94
95
96
97
98
99
103
-
L11
K13
K12
K14
K11
J13
J12
J11
J10
J9
MAD01_0
MAD02_0
MAD03_0
MAD04_0
MAD05_0
MAD06_0
MAD07_0
MAD08_0
MAD09_0
MAD10_0
MAD11_0
MAD12_0
MAD13_0
MAD14_0
MAD15_0
MAD16_0
MAD17_0
MAD18_0
MAD19_0
MAD20_0
MAD21_0
MAD22_0
MAD23_0
MAD24_0
MCSX0_0
MCSX1_0
MCSX2_0
MCSX3_0
MCSX4_0
MCSX5_0
MCSX6_0
MCSX7_0
MDQM0_0
MDQM1_0
99
100
101
102
103
104
105
118
119
120
121
122
123
127
139
140
141
142
143
144
23
H10
H9
External bus interface address bus
F10
F11
F12
F13
E10
E11
D13
C11
D11
B10
C10
D10
B9
G5
G6
J3
J2
L12
L13
M12
M13
F2
-
-
-
-
-
23
24
26
27
77
76
75
74
15
16
24
34
35
93
92
91
90
15
External bus interface chip select output pin
External bus interface byte mask signal output
16
F3
External bus interface read enable signal for
SRAM
External bus interface write enable signal for
SRAM
MOEX_0
MWEX_0
13
14
13
14
E5
F1
Document Number: 002-05602 Rev. *C
Page 30 of 125
MB9B510T Series
Pin No
Module
Pin name
MNALE_0
Function
LQFP-176 LQFP-144 BGA-192
External
Bus
External bus interface ALE signal to control NAND
Flash output pin
External bus interface CLE signal to control NAND
Flash output pin
External bus interface read enable signal to control
NAND Flash
External bus interface write enable signal to
control NAND Flash
19
20
22
21
19
20
22
21
F6
G2
G4
G3
MNCLE_0
MNREX_0
MNWEX_0
MADATA00_0
MADATA01_0
60
61
52
53
K5
N6
MADATA02_0
MADATA03_0
MADATA04_0
MADATA05_0
MADATA06_0
MADATA07_0
MADATA08_0
MADATA09_0
MADATA10_0
MADATA11_0
MADATA12_0
MADATA13_0
MADATA14_0
MADATA15_0
62
63
64
65
66
67
68
69
70
71
72
73
74
75
54
55
56
57
58
59
60
61
62
63
64
65
66
67
M6
L6
K6
J6
N8
M8
L8
K8
P8
J8
External bus interface data bus
(Address / data multiplex bus)
P9
N9
M9
L9
External bus interface Address Latch enable
output signal for multiplex
MALE_0
17
17
F4
MRDY_0
MCLKOUT_0
External bus interface external RDY input signal
External bus interface external clock output
18
36
18
28
F5
K1
Document Number: 002-05602 Rev. *C
Page 31 of 125
MB9B510T Series
Pin No
Module
Pin name
INT00_0
Function
LQFP-176 LQFP-144 BGA-192
External
Interrupt
13
8
165
14
9
123
15
91
120
6
13
8
135
14
9
99
15
75
96
6
78
-
-
81
-
103
84
-
E5
D3
C6
F1
D4
E11
F2
M12
F12
D2
L11
H3
H6
K14
H4
D13
J12
H5
B4
D12
K6
C4
P8
F3
B3
J4
F6
F11
J3
G4
K9
INT00_1
INT00_2
INT01_0
INT01_1
INT01_2
INT02_0
INT02_1
INT02_2
INT03_0
INT03_1
INT03_2
INT04_0
INT04_1
INT04_2
INT05_0
INT05_1
INT05_2
INT06_0
INT06_1
INT06_2
INT07_0
INT07_1
INT07_2
INT08_0
INT08_1
INT08_2
INT09_0
INT09_1
INT09_2
INT10_0
INT10_1
INT10_2
INT11_0
INT11_1
INT11_2
INT12_0
INT12_1
INT12_2
INT13_0
INT13_1
INT13_2
INT14_0
INT14_1
INT14_2
External interrupt request 00 input pin
External interrupt request 01 input pin
External interrupt request 02 input pin
External interrupt request 03 input pin
External interrupt request 04 input pin
External interrupt request 05 input pin
External interrupt request 06 input pin
External interrupt request 07 input pin
External interrupt request 08 input pin
External interrupt request 09 input pin
External interrupt request 10 input pin
External interrupt request 11 input pin
External interrupt request 12 input pin
External interrupt request 13 input pin
External interrupt request 14 input pin
94
28
31
97
29
127
100
30
170
126
64
171
70
16
172
33
19
119
34
22
76
35
7
77
36
71
78
46
72
81
47
66
82
58
67
-
102
56
-
62
16
140
-
19
95
26
22
-
27
7
-
28
63
-
38
64
-
J2
D1
P10
K1
J8
N10
N2
P9
M10
N3
N8
N11
M5
M8
39
58
-
50
59
Document Number: 002-05602 Rev. *C
Page 32 of 125
MB9B510T Series
Pin No
Module
Pin name
INT15_0
Function
LQFP-176 LQFP-144 BGA-192
External
Interrupt
83
169
68
110
20
111
21
112
23
113
24
114
96
115
98
116
99
117
74
79
75
80
101
143
102
144
103
25
-
139
60
-
20
-
21
-
23
-
24
-
80
-
82
-
83
-
66
-
67
-
85
-
86
-
87
-
88
-
89
-
133
-
M11
C5
L8
H13
G2
H12
G3
H11
G5
G13
G6
G12
K12
G11
K11
G10
J13
G9
M9
L10
L9
K10
J11
D10
J10
B9
J9
H1
H10
H2
H9
INT15_1
INT15_2
INT16_0
INT16_1
INT17_0
INT17_1
INT18_0
INT18_1
INT19_0
INT19_1
INT20_0
INT20_1
INT21_0
INT21_1
INT22_0
INT22_1
INT23_0
INT23_1
INT24_0
INT24_1
INT25_0
INT25_1
INT26_0
INT26_1
INT27_0
INT27_1
INT28_0
INT28_1
INT29_0
INT29_1
INT30_0
INT30_1
INT31_0
INT31_1
NMIX
External interrupt request 15 input pin
External interrupt request 16 input pin
External interrupt request 17 input pin
External interrupt request 18 input pin
External interrupt request 19 input pin
External interrupt request 20 input pin
External interrupt request 21 input pin
External interrupt request 22 input pin
External interrupt request 23 input pin
External interrupt request 24 input pin
External interrupt request 25 input pin
External interrupt request 26 input pin
External interrupt request 27 input pin
External interrupt request 28 input pin
External interrupt request 29 input pin
External interrupt request 30 input pin
104
26
105
139
163
140
164
128
C11
F7
D11
B6
External interrupt request 31 input pin
Non-Maskable Interrupt input
134
104
C13
Document Number: 002-05602 Rev. *C
Page 33 of 125
MB9B510T Series
Pin No
Module
GPIO
Pin name
Function
LQFP-176 LQFP-144 BGA-192
P00
P01
P02
P03
P04
P05
P06
P07
P08
P09
P10
P11
P12
P13
P14
P15
P16
P17
P18
P19
P1A
P1B
P1C
P1D
P1E
P1F
P20
P21
P22
P23
P24
P25
P26
P27
P28
P29
134
135
136
137
138
8
9
10
11
12
90
91
92
93
94
95
96
97
110
111
112
113
114
8
9
10
11
B13
A12
C12
B12
B11
D3
D4
E2
E3
E4
M13
M12
L13
L12
L11
K13
K12
K14
K11
J13
J12
J11
J10
J9
General-purpose I/O port 0
12
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
103
102
101
100
99
98
97
96
95
94
General-purpose I/O port 1
98
99
100
101
102
103
104
105
127
126
125
124
123
122
121
120
119
118
H10
H9
D13
D12
E13
E12
E11
E10
F13
F12
F11
F10
General-purpose I/O port 2
Document Number: 002-05602 Rev. *C
Page 34 of 125
MB9B510T Series
Pin No
Module
GPIO
Pin name
Function
LQFP-176 LQFP-144 BGA-192
P30
P31
P32
P33
P34
P35
P36
P37
P38
P39
P3A
P3B
P3C
P3D
P3E
P3F
P40
P41
P42
P43
P44
P45
P46
P47
P48
P49
P4A
P4B
P4C
P4D
P4E
P50
P51
P52
P53
P54
P55
P56
P57
P58
P59
P5A
P5B
P5C
P5D
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
46
47
48
49
50
51
55
56
58
59
60
61
62
63
64
13
14
15
16
17
18
19
20
21
22
23
24
25
26
-
-
-
-
-
-
H3
H4
H5
H6
J5
J4
J3
J2
K1
K2
K3
K4
L1
26
27
28
29
30
31
32
33
34
35
38
39
40
41
42
43
47
48
50
51
52
53
54
55
56
13
14
15
16
17
18
19
20
21
22
23
24
-
General-purpose I/O port 3
L2
L3
M2
N2
N3
M3
L4
M4
N4
P5
P6
M5
L5
General-purpose I/O port 4
K5
N6
M6
L6
K6
E5
F1
F2
F3
F4
F5
F6
G2
G3
G4
G5
G6
H1
H2
General-purpose I/O port 5
-
Document Number: 002-05602 Rev. *C
Page 35 of 125
MB9B510T Series
Pin No
Module
GPIO
Pin name
Function
LQFP-176 LQFP-144 BGA-192
P60
P61
P62
P70
P71
P72
P73
P74
P75
P76
P77
P78
P79
P7A
P7B
P7C
P7D
P7E
P7F
P80
P81
P82
P83
P90
P91
P92
P93
P94
P95
PA0
PA1
PA2
PA3
PA4
PA5
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
169
168
167
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
139
138
137
57
58
59
60
61
62
63
64
65
66
67
-
C5
B5
E6
J6
N8
M8
L8
K8
P8
J8
P9
N9
M9
L9
K9
P10
N10
L10
K10
A3
General-purpose I/O port 6
General-purpose I/O port 7
-
-
-
-
80
174
175
130
131
139
140
141
142
143
144
2
142
143
106
107
-
-
-
-
-
-
2
3
4
5
6
7
-
-
-
-
-
-
-
-
A2
General-purpose I/O port 8
General-purpose I/O port 9
D14
C14
C11
D11
B10
C10
D10
B9
B2
C2
C3
D5
3
4
5
6
General-purpose I/O port A
D2
D1
7
110
111
112
113
114
115
116
117
H13
H12
H11
G13
G12
G11
G10
G9
General-purpose I/O port B
Document Number: 002-05602 Rev. *C
Page 36 of 125
MB9B510T Series
Pin no
Module
GPIO
Pin name
Function
LQFP-176 LQFP-144 BGA-192
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
PC8
PC9
PCA
PCB
PCC
PCD
PCE
PCF
PD0
PD1
PD2
PD3
PE0
PE2
PE3
PF0
PF1
PF2
PF3
PF4
PF5
PF6
145
146
147
148
149
150
151
152
153
154
155
158
159
160
161
162
163
164
165
166
84
115
116
117
118
119
120
121
122
123
124
125
128
129
130
131
132
133
134
135
136
68
C9
B8
D9
E9
F9
C8
D8
E8
A10
F8
B7
A7
C7
A6
D7
E7
F7
B6
General-purpose I/O port C
General-purpose I/O port D
General-purpose I/O port E
C6
D6
N13
P12
P13
M10
N11
M11
B4
C4
B3
C13
86
87
81
82
70
71
-
-
-
-
-
83
General-purpose I/O port F*
170
171
172
128
140
104
Document Number: 002-05602 Rev. *C
Page 37 of 125
MB9B510T Series
Pin No.
Module
Pin name
Function
LQFP-176 LQFP-144 BGA-192
Multi Function
Serial
0
SIN0_0
SIN0_1
SIN0_2
126
94
114
102
78
-
D12
L11
G12
Multifunction serial interface ch.0 input pin
SOT0_0
(SDA0_0)
125
101
E13
Multifunction serial interface ch.0 output pin.
This pin operates as SOT0 when it is used in a
UART/CSIO (operation modes 0 to 2) and as
SDA0 when it is used in an I2C (operation mode 4).
SOT0_1
(SDA0_1)
95
79
-
K13
G11
E12
SOT0_2
(SDA0_2)
115
124
SCK0_0
(SCL0_0)
100
Multifunction serial interface ch.0 clock I/O pin.
This pin operates as SCK0 when it is used in a
UART/CSIO (operation modes 0 to 2) and as
SCL0 when it is used in an I2C (operation mode 4).
SCK0_1
(SCL0_1)
96
80
-
K12
G10
SCK0_2
(SCL0_2)
SIN1_0
SIN1_1
SIN1_2
116
Multi Function
Serial
1
19
91
81
19
75
-
F6
M12
M10
Multifunction serial interface ch.1 input pin
SOT1_0
(SDA1_0)
20
92
82
21
93
83
20
76
-
G2
L13
N11
G3
Multifunction serial interface ch.1 output pin.
This pin operates as SOT1 when it is used in a
UART/CSIO (operation modes 0 to 2) and as
SDA1 when it is used in an I2C (operation mode 4).
SOT1_1
(SDA1_1)
SOT1_2
(SDA1_2)
SCK1_0
(SCL1_0)
21
77
-
Multifunction serial interface ch.1 clock I/O pin.
This pin operates as SCK1 when it is used in a
UART/CSIO (operation modes 0 to 2) and as
SCL1 when it is used in an I2C (operation mode 4).
SCK1_1
(SCL1_1)
L12
M11
SCK1_2
(SCL1_2)
Document Number: 002-05602 Rev. *C
Page 38 of 125
MB9B510T Series
Pin No.
Module
Pin name
Function
LQFP-176 LQFP-144 BGA-192
Multi Function
Serial
2
SIN2_0
SIN2_1
SIN2_2
67
123
97
59
99
81
M8
E11
K14
Multifunction serial interface ch.2 input pin
SOT2_0
(SDA2_0)
SOT2_1
(SDA2_1)
SOT2_2
(SDA2_2)
SCK2_0
(SCL2_0)
SCK2_1
(SCL2_1)
SCK2_2
(SCL2_2)
SIN3_0
68
122
98
60
98
82
61
97
83
L8
E10
K11
K8
Multifunction serial interface ch.2 output pin.
This pin operates as SOT2 when it is used in a
UART/CSIO (operation modes 0 to 2) and as
SDA2 when it is used in an I2C (operation mode 4).
69
Multifunction serial interface ch.2 clock I/O pin.
This pin operates as SCK2 when it is used in a
UART/CSIO (operation modes 0 to 2) and as
SCL2 when it is used in an I2C (operation mode 4).
121
99
F13
J13
Multi Function
Serial
3
70
13
62
13
P8
E5
SIN3_1
SIN3_2
Multifunction serial interface ch.3 input pin
58
71
50
63
M5
J8
SOT3_0
(SDA3_0)
SOT3_1
(SDA3_1)
SOT3_2
(SDA3_2)
SCK3_0
(SCL3_0)
SCK3_1
(SCL3_1)
SCK3_2
(SCL3_2)
Multifunction serial interface ch.3 output pin.
This pin operates as SOT3 when it is used in a
UART/CSIO (operation modes 0 to 2) and as
SDA3 when it is used in an I2C (operation mode 4).
14
59
72
15
60
14
51
64
15
52
F1
L5
P9
F2
K5
Multifunction serial interface ch.3 clock I/O pin.
This pin operates as SCK3 when it is used in a
UART/CSIO (operation modes 0 to 2) and as
SCL3 when it is used in an I2C (operation mode 4).
Document Number: 002-05602 Rev. *C
Page 39 of 125
MB9B510T Series
Pin No
Module
Pin name
Function
LQFP-176 LQFP-144 BGA-192
Multi Function
Serial
4
SIN4_0
SIN4_1
SIN4_2
165
100
8
135
84
8
C6
J12
D3
Multifunction serial interface ch.4 input pin
SOT4_0
(SDA4_0)
SOT4_1
(SDA4_1)
SOT4_2
(SDA4_2)
SCK4_0
(SCL4_0)
SCK4_1
(SCL4_1)
SCK4_2
(SCL4_2)
RTS4_0
RTS4_1
RTS4_2
CTS4_0
CTS4_1
CTS4_2
SIN5_0
164
101
9
134
85
9
B6
J11
D4
F7
Multifunction serial interface ch.4 output pin.
This pin operates as SOT4 when it is used in a
UART/CSIO (operation modes 0 to 2) and as
SDA4 when it is used in an I2C (operation mode 4).
163
102
10
133
86
10
Multifunction serial interface ch.4 clock I/O pin.
This pin operates as SCK4 when it is used in a
UART/CSIO (operation modes 0 to 2) and as
SCL4 when it is used in an I2C (operation mode 4).
J10
E2
161
104
12
162
103
11
169
141
34
131
88
12
132
87
11
139
-
26
D7
H10
E4
E7
J9
Multifunction serial interface ch.4 RTS output pin
Multifunction serial interface ch.4 CTS input pin
Multifunction serial interface ch.5 input pin
E3
Multi Function
Serial
5
C5
B10
J3
SIN5_1
SIN5_2
SOT5_0
(SDA5_0)
168
138
B5
Multifunction serial interface ch.5 output pin.
This pin operates as SOT5 when it is used in a
UART/CSIO (operation modes 0 to 2) and as
SDA5 when it is used in an I2C (operation mode 4).
SOT5_1
(SDA5_1)
142
35
-
C10
J2
SOT5_2
(SDA5_2)
27
SCK5_0
(SCL5_0)
167
137
E6
Multifunction serial interface ch.5 clock I/O pin.
This pin operates as SCK5 when it is used in a
UART/CSIO (operation modes 0 to 2) and as
SCL5 when it is used in an I2C (operation mode 4).
SCK5_1
(SCL5_1)
143
36
-
D10
K1
SCK5_2
(SCL5_2)
28
Document Number: 002-05602 Rev. *C
Page 40 of 125
MB9B510T Series
Pin No
Module
Pin name
Function
LQFP-176 LQFP-144 BGA-192
Multi Function
Serial
6
SIN6_0
SIN6_1
SIN6_2
16
31
170
16
-
-
F3
H6
B4
Multifunction serial interface ch.6 input pin
SOT6_0
(SDA6_0)
SOT6_1
(SDA6_1)
SOT6_2
(SDA6_2)
SCK6_0
(SCL6_0)
SCK6_1
(SCL6_1)
SCK6_2
(SCL6_2)
SIN7_0
17
30
17
-
F4
H5
C4
F5
H4
B3
Multifunction serial interface ch.6 output pin.
This pin operates as SOT6 when it is used in a
UART/CSIO (operation modes 0 to 2) and as
SDA6 when it is used in an I2C (operation mode 4).
171
18
-
18
-
Multifunction serial interface ch.6 clock I/O pin.
This pin operates as SCK6 when it is used in a
UART/CSIO (operation modes 0 to 2) and as
SCL6 when it is used in an I2C (operation mode 4).
29
172
140
Multi Function
Serial
7
22
64
110
22
56
-
G4
K6
H13
SIN7_1
SIN7_2
Multifunction serial interface ch.7 input pin
SOT7_0
(SDA7_0)
23
63
23
55
-
G5
L6
Multifunction serial interface ch.7 output pin.
This pin operates as SOT7 when it is used in a
UART/CSIO (operation modes 0 to 2) and as
SDA7 when it is used in an I2C (operation mode 4).
SOT7_1
(SDA7_1)
SOT7_2
(SDA7_2)
111
24
H12
G6
SCK7_0
(SCL7_0)
24
Multifunction serial interface ch.7 clock I/O pin.
This pin operates as SCK7 when it is used in a
UART/CSIO (operation modes 0 to 2) and as
SCL7 when it is used in an I2C (operation mode 4).
SCK7_1
(SCL7_1)
62
54
-
M6
SCK7_2
(SCL7_2)
112
H11
Document Number: 002-05602 Rev. *C
Page 41 of 125
MB9B510T Series
Pin No
Module
Pin name
DTTI0X_0
Function
LQFP-176 LQFP-144 BGA-192
Multi Function
Timer
0
37
29
K2
Input signal controlling wave form generator
outputs RTO00 to RTO05 of multi-function timer 0.
DTTI0X_1
FRCK0_0
FRCK0_1
FRCK0_2
IC00_0
IC00_1
IC00_2
IC01_0
IC01_1
IC01_2
IC02_0
IC02_1
IC02_2
104
32
105
91
36
100
92
35
101
93
34
102
94
88
-
H10
J5
H9
M12
K1
J12
L13
J2
J11
L12
J3
J10
L11
J4
16-bit free-run timer ch.0 external clock input pin
89
75
28
84
76
27
85
77
26
86
78
-
16-bit input capture ch.0 input pin of multi-function
timer 0
ICxx describes channel number.
IC03_0
33
IC03_1
IC03_2
103
95
87
79
J9
K13
RTO00_0
(PPG00_0)
RTO00_1
(PPG00_1)
RTO01_0
(PPG00_0)
RTO01_1
(PPG00_1)
RTO02_0
(PPG02_0)
RTO02_1
(PPG02_1)
RTO03_0
(PPG02_0)
RTO03_1
(PPG02_1)
RTO04_0
(PPG04_0)
RTO04_1
(PPG04_1)
RTO05_0
(PPG04_0)
RTO05_1
(PPG04_1)
Wave form generator output of multi-function timer
0
This pin operates as PPG00 when it is used in
PPG0 output modes.
38
124
39
30
100
31
99
32
98
33
97
34
96
35
95
K3
E12
K4
Wave form generator output of multi-function timer
0
This pin operates as PPG00 when it is used in
PPG0 output modes.
123
40
E11
L1
Wave form generator output of multi-function timer
0
This pin operates as PPG02 when it is used in
PPG0 output modes.
Wave form generator output of multi-function timer
0
This pin operates as PPG02 when it is used in
PPG0 output modes.
122
41
E10
L2
121
42
F13
L3
Wave form generator output of multi-function timer
0
This pin operates as PPG04 when it is used in
PPG0 output modes.
120
43
F12
M2
F11
Wave form generator output of multi-function timer
0
This pin operates as PPG04 when it is used in
PPG0 output modes.
119
Document Number: 002-05602 Rev. *C
Page 42 of 125
MB9B510T Series
Pin No
Module
Pin name
DTTI1X_0
Function
LQFP-176 LQFP-144 BGA-192
Multi Function
Timer
1
19
58
19
50
F6
Input signal controlling wave form generator
outputs RTO10 to RTO15 of multi-function timer 1.
DTTI1X_1
M5
FRCK1_0
FRCK1_1
IC10_0
IC10_1
IC11_0
IC11_1
IC12_0
IC12_1
IC13_0
2
63
3
59
4
60
5
61
6
2
55
3
51
4
52
5
53
6
B2
L6
C2
L5
C3
K5
D5
N6
D2
M6
16-bit free-run timer ch.1 external clock input pin
16-bit input capture ch.1 input pin of multi-function
timer 1.
ICxx describes channel number
IC13_1
62
54
RTO10_0
(PPG10_0)
RTO10_1
(PPG10_1)
RTO11_0
(PPG10_0)
RTO11_1
(PPG10_1)
RTO12_0
(PPG12_0)
RTO12_1
(PPG12_1)
RTO13_0
(PPG12_0)
RTO13_1
(PPG12_1)
RTO14_0
(PPG14_0)
Wave form generator output of multi-function timer
1.
This pin operates as PPG10 when it is used in
PPG1 output modes.
13
46
14
47
15
48
16
49
17
13
38
14
39
15
40
16
41
17
E5
N2
F1
N3
F2
M3
F3
L4
F4
Wave form generator output of multi-function timer
1.
This pin operates as PPG10 when it is used in
PPG1 output modes.
Wave form generator output of multi-function timer
1.
This pin operates as PPG12 when it is used in
PPG1 output modes.
Wave form generator output of multi-function timer
1.
This pin operates as PPG12 when it is used in
PPG1 output modes.
Wave form generator output of multi-function timer
1.
This pin operates as PPG14 when it is used in
PPG1 output modes.
RTO14_1
(PPG14_1)
50
42
M4
RTO15_0
(PPG14_0)
RTO15_1
(PPG14_1)
Wave form generator output of multi-function timer
1.
This pin operates as PPG14 when it is used in
PPG1 output modes.
18
51
18
43
F5
N4
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Page 43 of 125
MB9B510T Series
Pin No
Module
Pin name
DTTI2X_0
Function
LQFP-176 LQFP-144 BGA-192
Multi Function
Timer
2
12
12
E4
Input signal controlling wave form generator
outputs RTO20 to RTO25 of multi-function timer 2.
DTTI2X_1
26
-
H2
FRCK2_0
FRCK2_1
IC20_0
IC20_1
IC21_0
IC21_1
IC22_0
IC22_1
IC23_0
128
78
13
25
14
79
15
80
16
81
104
-
13
-
14
-
15
-
C13
N10
E5
H1
F1
L10
F2
K10
F3
16-bit free-run timer ch.2 external clock input pin
16-bit input capture ch.2 input pin of multi-function
timer 2.
ICxx describes channel number.
16
-
IC23_1
M10
RTO20_0
(PPG20_0)
RTO20_1
(PPG20_1)
RTO21_0
(PPG20_0)
RTO21_1
(PPG20_1)
RTO22_0
(PPG22_0)
RTO22_1
(PPG22_1)
RTO23_0
(PPG22_0)
RTO23_1
(PPG22_1)
RTO24_0
(PPG24_0)
Wave form generator output of multi-function timer
2.
This pin operates as PPG20 when it is used in
PPG2 output modes.
2
139
3
2
-
B2
C11
C2
Wave form generator output of multi-function timer
2.
This pin operates as PPG20 when it is used in
PPG2 output modes.
Wave form generator output of multi-function timer
2.
This pin operates as PPG22 when it is used in
PPG2 output modes.
3
-
140
4
D11
C3
4
-
141
5
B10
D5
Wave form generator output of multi-function timer
2.
This pin operates as PPG22 when it is used in
PPG2 output modes.
5
-
142
6
C10
D2
6
Wave form generator output of multi-function timer
2.
This pin operates as PPG24 when it is used in
PPG2 output modes.
RTO24_1
(PPG24_1)
143
-
D10
RTO25_0
(PPG24_0)
RTO25_1
(PPG24_1)
Wave form generator output of multi-function timer
2.
This pin operates as PPG24 when it is used in
PPG2 output modes.
7
7
-
D1
B9
144
Document Number: 002-05602 Rev. *C
Page 44 of 125
MB9B510T Series
Pin No
Module
Pin name
Function
LQFP-176 LQFP-144 BGA-192
Quadrature
Position/
Revolution
Counter
0
AIN0_0
AIN0_1
AIN0_2
BIN0_0
BIN0_1
BIN0_2
ZIN0_0
ZIN0_1
ZIN0_2
AIN1_0
AIN1_1
AIN1_2
BIN1_0
BIN1_1
BIN1_2
ZIN1_0
ZIN1_1
ZIN1_2
AIN2_0
AIN2_1
AIN2_2
BIN2_0
BIN2_1
BIN2_2
ZIN2_0
ZIN2_1
ZIN2_2
UDM0
28
59
-
51
13
-
H3
L5
QPRC ch.0 AIN input pin
13
E5
29
H4
K5
QPRC ch.0 BIN input pin
QPRC ch.0 ZIN input pin
QPRC ch.1 AIN input pin
QPRC ch.1 BIN input pin
QPRC ch.1 ZIN input pin
QPRC ch.2 AIN input pin
QPRC ch.2 BIN input pin
QPRC ch.2 ZIN input pin
60
52
14
-
14
F1
30
H5
N6
F2
61
53
15
65
103
54
66
102
55
67
101
56
59
-
15
Quadrature
Position/
Revolution
Counter
1
73
N9
D13
M6
M9
D12
L6
127
62
74
126
63
75
L9
125
64
E13
K6
Quadrature
Position/
Revolution
Counter
2
67
M8
B4
170
115
68
-
G11
L8
60
-
171
116
69
C4
G10
K8
-
61
140
-
172
117
174
175
B3
G9
A3
USB0
USB1
USB ch.0 device/host D – pin
142
143
UDP0
USB ch.0 device/host D + pin
A2
USB ch.0
USB external pull-up control pin
UHCONX0
168
138
B5
UDM1
UDP1
USB ch.1 device/host D – pin
130
131
106
107
D14
C14
USB ch.1 device/host D + pin
USB ch.1
USB external pull-up control pin
UHCONX1
127
103
D13
Document Number: 002-05602 Rev. *C
Page 45 of 125
MB9B510T Series
Pin No
Module
Reset
Pin name
Function
LQFP-176 LQFP-144 BGA-192
External Reset Input. A reset is valid when
INITX="L".
INITX
MD0
57
49
N5
Mode
Mode 0 Pin.
During normal operation, MD0="L" must be input.
During serial programming to Flash memory,
MD0="H" must be input.
Mode 1 Pin.
85
69
N12
MD1
During serial programming to Flash memory,
MD1="L" must be input.
Power supply Pin
Power supply Pin
Power supply Pin
84
68
N13
Power
VCC
VCC
VCC
VCC
1
1
C1
N1
P4
45
54
89
37
46
73
Power supply Pin
M14
VCC
Power supply Pin
133
173
129
156
109
141
105
126
A13
A4
USBVCC0
USBVCC1
VCC
3.3V Power supply port for USB I/O
E14
A9
Power supply Pin
GND
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
GND Pin
GND Pin
GND Pin
GND Pin
GND Pin
GND Pin
GND Pin
GND Pin
GND Pin
GND Pin
GND Pin
GND Pin
GND Pin
GND Pin
GND Pin
GND Pin
GND Pin
GND Pin
GND Pin
GND Pin
GND Pin
GND Pin
GND Pin
GND Pin
27
44
53
88
109
132
157
176
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
25
36
45
72
93
108
127
144
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
J1
M1
P3
N14
F14
B14
A11
B1
E1
G1
P7
P11
L14
A8
A5
N7
M7
L7
K7
J7
G7
H7
H8
G8
Document Number: 002-05602 Rev. *C
Page 46 of 125
MB9B510T Series
Pin No.
Module
Clock
Pin name
Function
LQFP-176 LQFP-144 BGA-192
X0
X0A
X1
Main clock (oscillation) input pin
Sub clock (oscillation) input pin
Main clock (oscillation) I/O pin
Sub clock (oscillation) I/O pin
86
55
87
70
47
71
P12
P5
P13
P6
X1A
56
48
CROUT_0
CROUT_1
AVCC
127
152
106
107
103
122
90
D13
E8
J14
H14
Built-in high-speed CR-osc clock output port
Analog
Power
A/D converter analog power pin
A/D converter analog reference voltage input pin
AVRH
91
Analog
GND
C pin
AVSS
C
A/D converter GND pin
108
52
92
44
G14
P2
Power stabilization capacity pin
Note:
−
While this device contains a Test Access Port (TAP) based on the IEEE 1149.1-2001 JTAG standard, it is not fully compliant to
all requirements of that standard. This device may contain a 32-bit device ID that is the same as the 32-bit device ID in other
devices with different functionality. The TAP pins may also be configurable for purposes other than access to the TAP
controller.
Document Number: 002-05602 Rev. *C
Page 47 of 125
MB9B510T Series
5. I/O Circuit Type
Type
Circuit
Remarks
It is possible to select the main
oscillation / GPIO function
Pull-up
resistor
When the main oscillation is
selected.
P-ch
P-ch
Digital output
Digital output
−
Oscillation feedback resistor
: Approximately 1 MΩ
X1
−
With Standby mode control
When the GPIO is selected.
N-ch
−
−
−
−
−
CMOS level output.
R
CMOS level hysteresis input
With pull-up resistor control
With standby mode control
Pull-up resistor
Pull-up resistor control
Digital input
: Approximately 50 kΩ
IOH = -4 mA, IOL = 4 mA
Standby mode control
Clock input
−
Feedback
resistor
A
Standby mode control
Digital input
Standby mode control
Pull-up
resistor
R
Digital output
P-ch
N-ch
P-ch
X0
Digital output
Pull-up resistor control
−
−
CMOS level hysteresis input
Pull-up resistor
: Approximately 50 kΩ
Pull-up resistor
B
Digital input
Document Number: 002-05602 Rev. *C
Page 48 of 125
MB9B510T Series
Type
Circuit
Remarks
−
−
Open drain output
CMOS level hysteresis input
Digital input
Control pin
C
N-ch
It is possible to select the sub
oscillation / GPIO function
Pull-up
resistor
When the sub oscillation is selected.
−
Oscillation feedback resistor
: Approximately 5 MΩ
P-ch
P-ch
Digital output
Digital output
X1A
−
With Standby mode control
When the GPIO is selected.
N-ch
−
−
−
−
−
CMOS level output.
R
CMOS level hysteresis input
With pull-up resistor control
With standby mode control
Pull-up resistor
Pull-up resistor control
Digital input
: Approximately 50 kΩ
IOH = -4 mA, IOL = 4 mA
−
Standby mode control
Clock input
Feedback
resistor
D
Standby mode control
Digital input
Standby mode control
Pull-up
resistor
R
Digital output
P-ch
N-ch
P-ch
X0A
Digital output
Pull-up resistor control
Document Number: 002-05602 Rev. *C
Page 49 of 125
MB9B510T Series
Type
Circuit
Remarks
−
−
−
−
−
CMOS level output
CMOS level hysteresis input
With pull-up resistor control
With standby mode control
Pull-up resistor
P-ch
P-ch
Digital output
Digital output
: Approximately 50 kΩ
IOH = -4 mA, IOL = 4 mA
When this pin is used as an I2C
pin, the digital output P-ch
transistor is always off
+B input is available
−
−
E
N-ch
−
R
Pull-up resistor control
Digital input
Standby mode control
−
−
−
−
−
−
−
CMOS level output
CMOS level hysteresis input
With input control
Analog input
With pull-up resistor control
With standby mode control
Pull-up resistor
Digital output
Digital output
P-ch
P-ch
: Approximately 50 kΩ
IOH = -4 mA, IOL = 4 mA
When this pin is used as an I2C
pin, the digital output P-ch
transistor is always off
+B input is available
−
−
N-ch
F
−
Pull-up resistor control
Digital input
R
Standby mode control
Analog input
Input control
Document Number: 002-05602 Rev. *C
Page 50 of 125
MB9B510T Series
Type
Circuit
Remarks
−
−
−
−
−
CMOS level output
CMOS level hysteresis input
With pull-up resistor control
With standby mode control
Pull-up resistor
P-ch
P-ch
Digital output
Digital output
: Approximately 50 kΩ
IOH = -12 mA, IOL = 12 mA
+B input is available
−
−
G
N-ch
R
Pull-up resistor control
Digital input
Standby mode control
It is possible to select the USB I/O /
GPIO function.
GPIO Digital output
GPIO Digital input/output direction
GPIO Digital input
When the USB I/O is selected.
GPIO Digital input circuit control
−
Full-speed, Low-speed control
UDP (+) output
When the GPIO is selected.
EBP
−
−
−
−
CMOS level output
USB Full-speed/Low-speed control
UDP (+) input
CMOS level hysteresis input
With standby mode control
IOH = -20.5 mA, IOL = 18.5 mA
Differential
EBM
Differential input
USB/GPIO select
H
UDM (-) input
UDM (-) output
USB Digital input/output direction
GPIO Digital output
GPIO Digital input/output direction
GPIO Digital input
GPIO Digital input circuit control
Document Number: 002-05602 Rev. *C
Page 51 of 125
MB9B510T Series
Type
Circuit
Remarks
−
−
−
−
−
−
CMOS level output
CMOS level hysteresis input
5 V tolerant
With standby mode control
IOH = -4 mA, IOL = 4 mA
Available to control of PZR
registers.
When this pin is used as an I2C
pin, the digital output P-ch
transistor is always off
Digital output
Digital output
P-ch
−
I
N-ch
R
Digital input
Standby mode control
CMOS level hysteresis input
J
Mode input
Document Number: 002-05602 Rev. *C
Page 52 of 125
MB9B510T Series
Type
Circuit
Remarks
−
−
−
−
−
CMOS level output
TTL level hysteresis input
With pull-up resistor control
With standby mode control
Pull-up resistor
P-ch
P-ch
Digital output
Digital output
: Approximately 50 kΩ
IOH = -4 mA, IOL = 4 mA
−
K
N-ch
R
Pull-up resistor control
Digital input
Standby mode control
−
−
−
−
−
CMOS level output
CMOS level hysteresis input
With pull-up resistor control
With standby mode control
Pull-up resistor
P-ch
P-ch
Digital output
Digital output
: Approximately 50 kΩ
IOH = -8 mA, IOL = 8 mA
When this pin is used as an I2C pin,
the digital output
−
−
P-ch transistor is always off
+B input is available
L
N-ch
−
R
Pull-up resistor control
Digital input
Standby mode control
Document Number: 002-05602 Rev. *C
Page 53 of 125
MB9B510T Series
6. Handling Precautions
Any semiconductor devices have inherently a certain rate of failure. The possibility of failure is greatly affected by the conditions in
which they are used (circuit conditions, environmental conditions, etc.). This page describes precautions that must be observed to
minimize the chance of failure and to obtain higher reliability from your Cypress semiconductor devices.
6.1 Precautions for Product Design
This section describes precautions when designing electronic equipment using semiconductor devices.
Absolute Maximum Ratings
Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of
certain established limits, called absolute maximum ratings. Do not exceed these ratings.
Recommended Operating Conditions
Recommended operating conditions are normal operating ranges for the semiconductor device. All the device's electrical
characteristics are warranted when operated within these ranges.
Always use semiconductor devices within the recommended operating conditions. Operation outside these ranges may adversely
affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on the datasheet. Users
considering application outside the listed conditions are advised to contact their sales representative beforehand.
Processing and Protection of Pins
These precautions must be followed when handling the pins which connect semiconductor devices to power supply and input/output
functions.
1. Preventing Over-Voltage and Over-Current Conditions
Exposure to voltage or current levels in excess of maximum ratings at any pin is likely to cause deterioration within the device,
and in extreme cases leads to permanent damage of the device. Try to prevent such overvoltage or over-current conditions at
the design stage.
2. Protection of Output Pins
Shorting of output pins to supply pins or other output pins, or connection to large capacitance can cause large current flows.
Such conditions if present for extended periods of time can damage the device.
Therefore, avoid this type of connection.
3. Handling of Unused Input Pins
Unconnected input pins with very high impedance levels can adversely affect stability of operation. Such pins should be
connected through an appropriate resistance to a power supply pin or ground pin.
Latch-up
Semiconductor devices are constructed by the formation of P-type and N-type areas on a substrate. When subjected to abnormally
high voltages, internal parasitic PNPN junctions (called thyristor structures) may be formed, causing large current levels in excess of
several hundred mA to flow continuously at the power supply pin. This condition is called latch-up.
CAUTION: The occurrence of latch-up not only causes loss of reliability in the semiconductor device, but can cause injury or
damage from high heat, smoke or flame. To prevent this from happening, do the following:
1. Be sure that voltages applied to pins do not exceed the absolute maximum ratings. This should include attention to abnormal
noise, surge levels, etc.
2. Be sure that abnormal current flows do not occur during the power-on sequence.
Observance of Safety Regulations and Standards
Most countries in the world have established standards and regulations regarding safety, protection from electromagnetic
interference, etc. Customers are requested to observe applicable regulations and standards in the design of products.
Fail-Safe Design
Any semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage or loss from such
failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and
prevention of over-current levels and other abnormal operating conditions.
Document Number: 002-05602 Rev. *C
Page 54 of 125
MB9B510T Series
Precautions Related to Usage of Devices
Cypress semiconductor devices are intended for use in standard applications (computers, office automation and other office
equipment, industrial, communications, and measurement equipment, personal or household devices, etc.).
CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly
affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as
aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.)
are requested to consult with sales representatives before such use. The company will not be responsible for damages arising from
such use without prior approval.
6.2 Precautions for Package Mounting
Package mounting may be either lead insertion type or surface mount type. In either case, for heat resistance during soldering, you
should only mount under Cypress recommended conditions. For detailed information about mount conditions, contact your sales
representative.
Lead Insertion Type
Mounting of lead insertion type packages onto printed circuit boards may be done by two methods: direct soldering on the board, or
mounting by using a socket.
Direct mounting onto boards normally involves processes for inserting leads into through-holes on the board and using the flow
soldering (wave soldering) method of applying liquid solder. In this case, the soldering process usually causes leads to be subjected
to thermal stress in excess of the absolute ratings for storage temperature. Mounting processes should conform to Cypress
recommended mounting conditions.
If socket mounting is used, differences in surface treatment of the socket contacts and IC lead surfaces can lead to contact
deterioration after long periods. For this reason it is recommended that the surface treatment of socket contacts and IC leads be
verified before mounting.
Surface Mount Type
Surface mount packaging has longer and thinner leads than lead-insertion packaging, and therefore leads are more easily deformed
or bent. The use of packages with higher pin counts and narrower pin pitch results in increased susceptibility to open connections
caused by deformed pins, or shorting due to solder bridges.
You must use appropriate mounting techniques. Cypress recommends the solder reflow method, and has established a ranking of
mounting conditions for each product. Users are advised to mount packages in accordance with Cypress ranking of recommended
conditions.
Lead-Free Packaging
CAUTION: When ball grid array (BGA) packages with Sn-Ag-Cu balls are mounted using Sn-Pb eutectic soldering, junction strength
may be reduced under some conditions of use.
Storage of Semiconductor Devices
Because plastic chip packages are formed from plastic resins, exposure to natural environmental conditions will cause absorption of
moisture. During mounting, the application of heat to a package that has absorbed moisture can cause surfaces to peel, reducing
moisture resistance and causing packages to crack. To prevent, do the following:
1. Avoid exposure to rapid temperature changes, which cause moisture to condense inside the product. Store products in
locations where temperature changes are slight.
2. Use dry boxes for product storage. Products should be stored below 70% relative humidity, and at temperatures between 5°C
and 30°C. When you open Dry Package that recommends humidity 40% to 70% relative humidity.
3. When necessary, Cypress packages semiconductor devices in highly moisture-resistant aluminum laminate bags, with a silica
gel desiccant. Devices should be sealed in their aluminum laminate bags for storage.
4. Avoid storing packages where they are exposed to corrosive gases or high levels of dust.
Baking
Packages that have absorbed moisture may be de-moisturized by baking (heat drying). Follow the Cypress recommended
conditions for baking.
Condition: 125°C/24 h
Document Number: 002-05602 Rev. *C
Page 55 of 125
MB9B510T Series
Static Electricity
Because semiconductor devices are particularly susceptible to damage by static electricity, you must take the following precautions:
1. Maintain relative humidity in the working environment between 40% and 70%. Use of an apparatus for ion generation may be
needed to remove electricity.
2. Electrically ground all conveyors, solder vessels, soldering irons and peripheral equipment.
3. Eliminate static body electricity by the use of rings or bracelets connected to ground through high resistance (on the level
of 1 MΩ).
Wearing of conductive clothing and shoes, use of conductive floor mats and other measures to minimize shock loads is
recommended.
4. Ground all fixtures and instruments, or protect with anti-static measures.
5. Avoid the use of Styrofoam or other highly static-prone materials for storage of completed board assemblies.
6.3 Precautions for Use Environment
Reliability of semiconductor devices depends on ambient temperature and other conditions as described above.
For reliable performance, do the following:
1. Humidity
Prolonged use in high humidity can lead to leakage in devices as well as printed circuit boards. If high humidity levels are
anticipated, consider anti-humidity processing.
2. Discharge of Static Electricity
When high-voltage charges exist close to semiconductor devices, discharges can cause abnormal operation. In such cases,
use anti-static measures or processing to prevent discharges.
3. Corrosive Gases, Dust, or Oil
Exposure to corrosive gases or contact with dust or oil may lead to chemical reactions that will adversely affect the device. If
you use devices in such conditions, consider ways to prevent such exposure or to protect the devices.
4. Radiation, Including Cosmic Radiation
Most devices are not designed for environments involving exposure to radiation or cosmic radiation. Users should provide
shielding as appropriate.
5. Smoke, Flame
CAUTION: Plastic molded devices are flammable, and therefore should not be used near combustible substances. If devices
begin to smoke or burn, there is danger of the release of toxic gases.
Customers considering the use of Cypress products in other special environmental conditions should consult with sales
representatives.
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Page 56 of 125
MB9B510T Series
7. Handling Devices
Power supply pins
In products with multiple VCC and VSS pins, respective pins at the same potential are interconnected within the device in order to
prevent malfunctions such as latch-up. However, all of these pins should be connected externally to the power supply or ground
lines in order to reduce electromagnetic emission levels, to prevent abnormal operation of strobe signals caused by the rise in the
ground level, and to conform to the total output current rating.
Moreover, connect the current supply source with each Power supply pin and GND pin of this device at low impedance. It is also
advisable that a ceramic capacitor of approximately 0.1 µF be connected as a bypass capacitor between each Power supply pin and
GND pin, between AVCC pin and AVSS pin near this device.
Stabilizing power supply voltage
A malfunction may occur when the power supply voltage fluctuates rapidly even though the fluctuation is within the recommended
operating conditions of the VCC power supply voltage. As a rule, with voltage stabilization, suppress the voltage fluctuation so that
the fluctuation in VCC ripple (peak-to-peak value) at the commercial frequency (50 Hz/60 Hz) does not exceed 10% of the VCC
value in the recommended operating conditions, and the transient fluctuation rate does not exceed 0.1 V/μs when there is a
momentary fluctuation on switching the power supply.
Crystal oscillator circuit
Noise near the X0/X1 and X0A/X1A pins may cause the device to malfunction. Design the printed circuit board so that X0/X1,
X0A/X1A pins, the crystal oscillator (or ceramic oscillator), and the bypass capacitor to ground are located as close to the device as
possible.
It is strongly recommended that the PC board artwork be designed such that the X0/X1 and X0A/X1A pins are surrounded by
ground plane as this is expected to produce stable operation.
Evaluate oscillation of your using crystal oscillator by your mount board.
Using an external clock
When using an external clock, the clock signal should be input to the X0, X0A pin only and the X1,X1A pin should be kept open.
Example of Using an External Clock
Device
X0(X0A)
Open
X1(X1A)
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Page 57 of 125
MB9B510T Series
Handling when using Multi-function serial pin as I2C pin
If it is using multi-function serial pin as I2C pins, P-ch transistor of digital output is always disable. However, I2C pins need to keep
the electrical characteristic like other pins and not to connect to external I2C bus system with power OFF.
C Pin
This series contains the regulator. Be sure to connect a smoothing capacitor (CS) for the regulator between
the C pin and the GND pin. Please use a ceramic capacitor or a capacitor of equivalent frequency characteristics as a smoothing
capacitor.
However, some laminated ceramic capacitors have the characteristics of capacitance variation due to thermal fluctuation (F
characteristics and Y5V characteristics). Please select the capacitor that meets the specifications in the operating conditions to use
by evaluating the temperature characteristics of a capacitor.
A smoothing capacitor of about 4.7μF would be recommended for this series.
C
Device
CS
VSS
GND
Mode pins (MD0)
Connect the MD pin (MD0) directly to VCC or VSS pins. Design the printed circuit board such that the pull-up/down resistance stays
low, as well as the distance between the mode pins and VCC pins or VSS pins is as short as possible and the connection
impedance is low, when the pins are pulled-up/down such as for switching the pin level and rewriting the Flash memory data. It is
because of preventing the device erroneously switching to test mode due to noise.
Notes on power-on
Turn power on/off in the following order or at the same time.
If not using the A/D converter, connect AVCC = VCC and AVSS = VSS.
Turning on: VCC USBVCC0
VCC USBVCC1
VCC →AVCC → AVRH
Turning off:
AVRH → AVCC → VCC
USBVCC1 VCC
USBVCC0 VCC
Serial Communication
There is a possibility to receive wrong data due to the noise or other causes on the serial communication.
Therefore, design a printed circuit board so as to avoid noise.
Consider the case of receiving wrong data due to noise, perform error detection such as by applying a checksum of data at the end.
If an error is detected, retransmit the data.
Document Number: 002-05602 Rev. *C
Page 58 of 125
MB9B510T Series
Differences in features among the products with different memory sizes and between Flash products and
MASK products
The electric characteristics including power consumption, ESD, latch-up, noise characteristics, and oscillation characteristics among
the products with different memory sizes and between Flash products and MASK products are different because chip layout and
memory structures are different.
If you are switching to use a different product of the same series, please make sure to evaluate the electric characteristics.
Base Timer
In the case of using ch.8 and ch.9 at I/O mode 1 (timer full mode), the TIOA09 pin cannot be used for external startup trigger input
(TGIN).
Be sure to use the pin with making ESG1 and ESG2 bits of the Timer Control Register (Ch.9-TMCR) in the Base Timer to be "0b00"
in order to disable trigger input.
Document Number: 002-05602 Rev. *C
Page 59 of 125
MB9B510T Series
8. Block Diagram
MB9BF516/517/518
TRSTX,TCK,
TDI,TMS
TDO
SWJ-DP
TPIU
ETM
SRAM0
32/48/64Kbyte
ROM
Table
TRACED[3:0],
TRACECLK
On-chip Flash
512Kbyte/
768Kbyte/
Cortex-M3ꢀCore
144MHz(Max)
I
Flash I/F
Security
D
1024Kbyte
MPU NVIC
Trace Buffer
(16Kbyte)
Sys
SRAM1
32/48/64Kbyte
Dual-Timer
Watchdog Timer
(Software)
USBVCC0
USB 2.0
(Host/
Func)
PHY
PHY
UDP0,UDM0
UHCONX0
Clock Reset
Generator
INITX
USB 2.0
(Host/
Func)
USBVCC1
UDP1,UDM1
UHCONX1
Watchdog Timer
(Hardware)
CSV
CLK
DMAC
8ch.
TX0,
RX0
Main
CAN
CAN
Source Clock
X0
PLL
Osc
Sub
Osc
X1
TX1,
RX1
CR
4MHz
CR
100kHz
X0A
X1A
CROUT
AVCC,
AVSS,AVRH
12-bit A/D Converter
Unit 0
AN[31:00]
Unit 1
Unit 2
ADTG[8:0]
MAD[24:00]
MADATA[15:00]
External Bus I/F
TIOA[15:00]
TIOB[15:00]
Base Timer
16-bit 16ch./
32-bit 8ch.
MCSX[7:0],
MOEX,MWEX,
MNALE,
MNCLE,
MNWEX,
MNREX,
MDQM[1:0]
MALE
MRDY
USB Clk Ctrl
PLL
AIN[2:0]
BIN[2:0]
ZIN[2:0]
QPRC
3ch.
CAN Prescaler
Power On
Reset
MCLKOUT
LVD
LVD Ctrl
A/D Activation
Compare
3ch.
Regulator
C
IRQ-Monitor
IC0[3:0]
IC1[3:0]
IC2[3:0]
16-bit Input Capture
4ch.
CRC
Accelerator
16-bit Free-run Timer
3ch.
FRCK[2:0]
Watch Counter
External Interrupt
Controller
32-pin + NMI
16-bit Output
Compare
6ch.
INT[31:00]
NMIX
DTTI[2:0]X
Waveform Generator
3ch.
RTO0[5:0]
RTO1[5:0]
RTO2[5:0]
MD[1:0]
MODE-Ctrl
GPIO
P0x,
P1x,
.
16-bit PPG
3ch.
PIN-Function-Ctrl
.
.
PFx
Multi-function Timer ×3
SCK[7:0]
SIN[7:0]
SOT[7:0]
CTS4
Multi-Function
Serial I/F 8ch.
(with FIFO ch.4 to ch.7)
HW flow control(ch.4)
RTS4
Note:
−The following items vary depending on the package.
•
•
Number of external bus interface pin
Number of 12-bit A/D converter channel
Document Number: 002-05602 Rev. *C
Page 60 of 125
MB9B510T Series
9. Memory Size
See "Memory Size" in "1. Product Lineup" to confirm the memory size.
10.Memory Map
Memory Map (1)
Peripherals Area
0x41FF_FFFF
Reserved
0xFFFF_FFFF
Reserved
0x4006_4000
0x4006_3000
0x4006_2000
0x4006_1000
0x4006_0000
CAN ch.1
CAN ch.0
Reserved
DMAC
0xE010_0000
Cortex-M3 Private
Peripherals
0xE000_0000
USB ch.1
0x4005_0000
Reserved
USB ch.0
EXT-bus I/F
Reserved
0x4004_0000
0x4003_F000
0x7000_0000
External Device
0x4003_B000
0x4003_A000
0x4003_9000
0x4003_8000
0x4003_7000
0x4003_6000
0x4003_5000
0x4003_4000
0x4003_3000
0x4003_2000
0x4003_1000
0x4003_0000
0x4002_F000
0x4002_E000
Area
Watch Counter
CRC
0x6000_0000
Reserved
0x4400_0000
MFS
CAN Prescaler
USB Clk Ctrl
LVD Ctrl
Reserved
GPIO
32Mbyte
Bit band alias
0x4200_0000
Peripherals
0x4000_0000
Reserved
Int-Req.Read
EXTI
Reserved
0x2400_0000
32Mbyte
Bit band alias
0x2200_0000
Reserved
CR Trim
Reserved
Reserved
0x4002_8000
0x4002_7000
0x4002_6000
0x4002_5000
0x4002_4000
0x4002_3000
0x4002_2000
0x4002_1000
0x4002_0000
A/DC
QPRC
0x2008_0000
SRAM1
SRAM0
0x2000_0000
0x1FFF_0000
Base Timer
PPG
Reserved
Reserved
MFT unit2
MFT unit1
MFT unit0
0x0010_2000
0x0010_0000
See the next page
Security/CR Trim
“●Memory Map (2)” for
the memory size details.
On-chip Flash
Reserved
Dual Timer
Reserved
0x4001_6000
0x4001_5000
0x0000_0000
0x4001_3000
0x4001_2000
0x4001_1000
0x4001_0000
SW WDT
HW WDT
Clock/Reset
Reserved
Flash I/F
0x4000_1000
0x4000_0000
Document Number: 002-05602 Rev. *C
Page 61 of 125
MB9B510T Series
Memory Map (2)
MB9BF518S/T
MB9BF517S/T
MB9BF516S/T
0x2008_0000
0x2008_0000
0x2001_C000
0x2000_0000
0x2008_0000
Reserved
Reserved
0x2001_0000
0x2000_0000
Reserved
SRAM1
64Kbyte
0x2000_8000
0x2000_0000
0x1FFF_8000
SRAM1
48Kbyte
SRAM1
32Kbyte
SRAM0
32Kbyte
SRAM0
48Kbyte
SRAM0
64Kbyte
0x1FFF_4000
Reserved
0x1FFF_0000
Reserved
Reserved
0x0010_2000
0x0010_1000
0x0010_0000
0x0010_2000
0x0010_1000
0x0010_0000
0x0010_2000
0x0010_1000
0x0010_0000
CR trimming
Security
CR trimming
Security
CR trimming
Security
Reserved
0x000C_0000
Reserved
SA10-23(64KBx14)
0x0008_0000
SA10-19(64KBx10)
SA10-15(64KBx6)
SA8-9(48KBx2)
SA4-7(8KBx4)
SA8-9(48KBx2)
SA4-7(8KBx4)
SA8-9(48KBx2)
SA4-7(8KBx4)
0x0000_0000
0x0000_0000
0x0000_0000
Document Number: 002-05602 Rev. *C
Page 62 of 125
MB9B510T Series
Peripheral Address Map
Start address
End address
Bus
AHB
Peripherals
0x4000_0000
0x4000_1000
0x4001_0000
0x4001_1000
0x4001_2000
0x4001_3000
0x4001_5000
0x4001_6000
0x4002_0000
0x4002_1000
0x4002_2000
0x4002_4000
0x4002_5000
0x4002_6000
0x4002_7000
0x4002_8000
0x4002_E000
0x4002_F000
0x4003_0000
0x4003_1000
0x4003_2000
0x4003_3000
0x4003_4000
0x4003_5000
0x4003_6000
0x4003_7000
0x4003_8000
0x4003_9000
0x4003_A000
0x4003_B000
0x4003_F000
0x4004_0000
0x4005_0000
0x4006_0000
0x4006_1000
0x4006_2000
0x4006_3000
0x4006_4000
0x4000_0FFF
0x4000_FFFF
Flash memory I/F register
Reserved
0x4001_0FFF
0x4001_1FFF
0x4001_2FFF
0x4001_4FFF
0x4001_5FFF
0x4001_FFFF
0x4002_0FFF
0x4002_1FFF
0x4002_3FFF
0x4002_4FFF
0x4002_5FFF
0x4002_6FFF
0x4002_7FFF
0x4002_DFFF
0x4002_EFFF
0x4002_FFFF
0x4003_0FFF
0x4003_1FFF
0x4003_2FFF
0x4003_3FFF
0x4003_4FFF
0x4003_5FFF
0x4003_6FFF
0x4003_7FFF
0x4003_8FFF
0x4003_9FFF
0x4003_AFFF
0x4003_EFFF
0x4003_FFFF
0x4004_FFFF
0x4005_FFFF
0x4006_0FFF
0x4006_1FFF
0x4006_2FFF
0x4006_3FFF
0x41FF_FFFF
Clock/Reset Control
Hardware Watchdog timer
Software Watchdog timer
Reserved
APB0
Dual-Timer
Reserved
Multi-function timer unit0
Multi-function timer unit1
Multi-function timer unit2
PPG
Base Timer
APB1
Quadrature Position/Revolution Counter
A/D Converter
Reserved
Internal CR trimming
Reserved
External Interrupt Controller
Interrupt Request Batch-Read Function
Reserved
GPIO
Reserved
Low Voltage Detector
USB clock generator
CAN Prescaler
Multi-function serial Interface
CRC
APB2
Watch Counter
Reserved
External Memory interface
USB ch.0
USB ch.1
DMAC register
Reserved
AHB
CAN ch.0
CAN ch.1
Reserved
Document Number: 002-05602 Rev. *C
Page 63 of 125
MB9B510T Series
11.Pin Status in Each CPU State
The terms used for pin status have the following meanings.
INITX=0
This is the period when the INITX pin is the "L" level.
INITX=1
This is the period when the INITX pin is the "H" level.
SPL=0
This is the status that standby pin level setting bit (SPL) in standby mode control register (STB_CTL) is set to "0".
SPL=1
This is the status that standby pin level setting bit (SPL) in standby mode control register (STB_CTL) is set to "1".
Input enabled
Indicates that the input function can be used.
Internal input fixed at "0"
This is the status that the input function cannot be used. Internal input is fixed at "L".
Hi-Z
Indicates that the output drive transistor is disabled and the pin is put in the Hi-Z state.
Setting disabled
Indicates that the setting is disabled.
Maintain previous state
Maintains the state that was immediately prior to entering the current mode.
If a built-in peripheral function is operating, the output follows the peripheral function.
If the pin is being used as a port, that output is maintained.
Analog input is enabled
Indicates that the analog input is enabled.
Trace output
Indicates that the trace function can be used.
Document Number: 002-05602 Rev. *C
Page 64 of 125
MB9B510T Series
List of Pin Status
Pin
Power-on
reset or low
voltage
Device
internal
Run mode
or sleep
INITX input
state
Timer mode or sleep mode
state
detection
state
reset state
mode state
status
type
Function group
Power
supply
stable
INITX=1
-
Power supply
unstable
Power supply stable
Power supply stable
INITX=1
-
-
INITX=0
-
Setting
INITX=1
-
Setting
SPL=0
Maintain
previous state
SPL=1
Hi-Z/ Internal
input fixed at
"0"
GPIO selected
Setting disabled
Maintain
previous state
disabled
disabled
A
Main crystal
Input enabled
Input enabled
Input enabled
Input enabled
Input enabled
Input enabled
oscillator input pin
GPIO selected
Setting disabled
Setting
Setting
Maintain
Maintain
Hi-Z/
disabled
disabled
previous state
previous state
Internal input
fixed at "0"
B
Main crystal
Hi-Z/
Hi-Z/
Hi-Z/
Maintain
Maintain
Maintain
oscillator output pin
Internal input
fixed at "0"/
or Input enable
Internal input
fixed at "0"
Internal input
fixed at "0"
previous state
previous state/
Hi-Z at
previous state/
Hi-Z at
oscillation
oscillation
stop*1
stop*1
Internal input
fixed at "0"
Pull-up/ Input
enabled
Internal input
fixed at "0"
Pull-up/ Input
enabled
INITX input pin
Pull-up/
Input
enabled
Input enabled
Hi-Z
Pull-up/ Input
enabled
Pull-up/ Input
enabled
Pull-up/ Input
enabled
C
D
Mode input pin
JTAG
selected
GPIO
Input enabled
Pull-up/ Input
enabled
Setting
disabled
Input enabled
Pull-up/ Input
enabled
Setting
disabled
Input enabled
Maintain
previous state
Input enabled
Maintain
previous state
Input enabled
Maintain
previous state
Hi-Z/ Internal
input fixed at
"0"
Trace output
Maintain
previous state
Hi-Z/
E
Setting disabled
Setting disabled
Hi-Z
selected
Trace selected
External interrupt
enabled selected
GPIO
Setting
disabled
Setting
disabled
Maintain
previous state
Maintain
previous state
F
Hi-Z/
Hi-Z/
selected, or other
than above resource
selected
Input enabled
Input enabled
Internal input
fixed at "0"
Trace selected
Setting disabled
Hi-Z
Setting
disabled
Hi-Z/
Setting
disabled
Hi-Z/
Maintain
previous state
Maintain
previous state
Trace output
G
GPIO selected, or
other than above
resource selected
Hi-Z/
Internal input
fixed at "0"
Input enabled
Input enabled
Document Number: 002-05602 Rev. *C
Page 65 of 125
MB9B510T Series
Power-on
reset or low
voltage
detection
state
Device
internal
reset state
Run mode or
sleep mode
state
INITX input
state
Timer mode or sleep mode
state
Pin
status
type
Function group
Power
supply
stable
INITX=1
-
Power supply
unstable
Power supply stable
Power supply stable
INITX=1
-
-
INITX=0
-
INITX=1
-
SPL=0
Maintain
SPL=1
Maintain
External interrupt
enabled selected
GPIO selected, or
other than above
resource selected
GPIO selected,
Setting disabled
Setting
Setting
Maintain
previous state
disabled
Hi-Z/
disabled
Hi-Z/
previous state
previous state
Hi-Z/
H
I
Hi-Z
Hi-Z
Input enabled
Input enabled
Internal input
fixed at "0"
Hi-Z/ Internal
input fixed at
"0"
Hi-Z/
Hi-Z/
Maintain
previous state
Maintain
previous state
resource selected
Input enabled
Input enabled
NMIX selected
Setting disabled
Hi-Z
Setting
disabled
Hi-Z/
Setting
disabled
Hi-Z/
Maintain
previous state
Maintain
previous state
Maintain
previous state
Hi-Z/
Internal input
fixed at "0"
Hi-Z/
J
GPIO selected, or
other than above
resource selected
Analog input
Input enabled
Input enabled
Hi-Z
Hi-Z/
Hi-Z/
Hi-Z/
Hi-Z/
selected
Internal input
fixed at "0"/
Analog input
enabled
Internal input
fixed at "0"/
Analog input
enabled
Internal input
fixed at "0"/
Analog input
enabled
Internal input
fixed at "0"/
Analog input
enabled
Internal input
fixed at "0"/
Analog input
enabled
K
GPIO selected, or
other than above
resource selected
External interrupt
enabled selected
Analog input
Setting disabled
Setting
disabled
Setting
disabled
Maintain
previous state
Maintain
previous state
Hi-Z/
Internal input
fixed at "0"
Maintain
previous state
Hi-Z/
Setting disabled
Hi-Z
Setting
disabled
Hi-Z/
Setting
disabled
Hi-Z/
Maintain
previous state
Hi-Z/
Maintain
previous state
Hi-Z/
selected
Internal input
fixed at "0"/
Analog input
enabled
Internal input
fixed at "0"/
Analog input
enabled
Internal input
fixed at "0"/
Analog input
enabled
Internal input
fixed at "0"/
Analog input
enabled
Internal input
fixed at "0"/
Analog input
enabled
L
GPIO selected, or
other than above
resource selected
GPIO selected
Setting disabled
Setting disabled
Input enabled
Setting
disabled
Setting
disabled
Maintain
previous state
Maintain
previous state
Hi-Z/
Internal input
fixed at "0"
Hi-Z/ Internal
input fixed at
"0"
Setting
disabled
Setting
disabled
Maintain
previous state
Maintain
previous state
M
Sub crystal
Input enabled
Input enabled
Input enabled
Input enabled
Input enabled
oscillator input pin
Document Number: 002-05602 Rev. *C
Page 66 of 125
MB9B510T Series
Power-on
reset or low
voltage
detection
state
Run mode
or sleep
mode
Device
internal
reset state
INITX input
state
Timer mode or sleep mode
state
state
Pin
status
type
Function group
Power
supply
stable
INITX=1
-
Maintain
previous
state
Power supply
unstable
Power supply stable
Power supply stable
INITX=1
-
-
INITX=0
-
INITX=1
-
SPL=0
Maintain
SPL=1
Hi-Z/
GPIO selected
Sub crystal
Setting disabled
Setting
Setting
disabled
disabled
previous state
Internal input
fixed at "0"
Hi-Z/
Hi-Z/
Hi-Z/
Maintain
previous
state
Maintain
Maintain
N
oscillator output pin Internal input
fixed at "0"/
Internal input
fixed at "0"
Internal input
fixed at "0"
previous state/
Hi-Z at
previous state/
Hi-Z at
or Input enable
oscillation stop*2/ oscillation stop*2/
Internal input
fixed at "0"
Internal input
fixed at "0"
GPIO selected
USB I/O pin
Hi-Z
Hi-Z/
Input enabled
Hi-Z/
Input enabled
Maintain
previous
state
Maintain
previous state
Hi-Z/ Internal
input fixed at "0"
Setting disabled
Setting
disabled
Setting
disabled
Maintain
previous
state
Hi-Z at
Hi-Z at
transmission/
Input enabled/
Internal input
fixed at "0" at
reception
transmission/
Input enabled/
Internal input
fixed at "0" at
reception
O
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Mode input pin
GPIO selected
Input enabled
Input enabled
P
Maintain
previous
state
Maintain
previous
state
Setting
disabled
Setting
disabled
Hi-Z/
Input enabled
Setting disabled
Maintain
previous
state
Maintain
previous
state
Hi-Z/
Internal input
fixed at "0"
GPIO selected,
resource selected
Hi-Z/
Input enabled
Hi-Z/
Input enabled
Q
Hi-Z
Maintain
previous
state
External interrupt
enabled selected
Setting
disabled
Setting
disabled
Setting disabled
Hi-Z
Maintain
previous
state
Maintain
previous
state
R
GPIO selected, or
other than above
resource selected
Hi-Z/
Internal input
fixed at "0"
Hi-Z/
Input enabled
Hi-Z/
Input enabled
*1: Oscillation is stopped at Sub timer mode, Low speed CR timer mode, and STOP mode.
*2: Oscillation is stopped at STOP mode.
Document Number: 002-05602 Rev. *C
Page 67 of 125
MB9B510T Series
12.Electrical Characteristics
12.1 Absolute Maximum Ratings
Parameter
Power supply voltage*1,*2
Power supply voltage (for USB ch.0)*1,*3
Power supply voltage (for USB ch.1)*1,*3
Analog power supply voltage*1,*4
Analog reference voltage*1,*4
Rating
Symbol
Vcc
Unit
Remarks
Min
Vss - 0.5
Vss - 0.5
Max
Vss + 6.5
Vss + 6.5
Vss + 6.5
V
V
USBVcc0
USBVcc1
AVcc
AVRH
Vss - 0.5
Vss - 0.5
Vss - 0.5
V
V
V
Vss + 6.5
Vss + 6.5
Vcc + 0.5
(≤ 6.5 V)
USBVcc0 + 0.5
(≤ 6.5 V)
Vss - 0.5
Vss - 0.5
V
V
Except for USB pin
USB ch.0 pin
Input voltage*1
VI
USBVcc1 + 0.5
(≤ 6.5 V)
Vss + 6.5
AVcc + 0.5
(≤ 6.5 V)
Vss - 0.5
Vss - 0.5
Vss - 0.5
V
V
V
USB ch.1 pin
5V tolerant
Analog pin input voltage*1
Output voltage*1
VIA
Vcc + 0.5
(≤ 6.5 V)
VO
Vss - 0.5
-2
V
Clamp maximum current
ICLAMP
+2
mA
mA
mA
mA
*8
Σ[ICLAMP
]
Clamp total maximum current
+20
10
*8
4 mA type
8 mA type
20
"L" level maximum output current*5
"L" level average output current*6
IOL
-
20
39
4
mA
mA
mA
mA
mA
mA
mA
mA
12 mA type
P80,P81,P82,P83
4 mA type
8 mA type
12 mA type
P80,P81,P82,P83
8
IOLAV
-
12
18.5
100
50
"L" level total maximum output current
"L" level total average output current*7
∑IOL
∑IOLAV
-
-
- 10
- 20
mA
mA
4 mA type
8 mA type
"H" level maximum output current*5
"H" level average output current*6
IOH
-
-
- 20
- 39
- 4
mA
mA
mA
mA
mA
mA
mA
mA
mW
°C
12 mA type
P80,P81,P82,P83
4 mA type
8 mA type
12 mA type
- 8
IOHAV
- 12
- 20.5
- 100
- 50
1000
+ 150
P80,P81,P82,P83
"H" level total maximum output current
"H" level total average output current*7
Power consumption
∑IOH
∑IOHAV
PD
-
-
-
Storage temperature
TSTG
- 55
*1: These parameters are based on the condition that Vss = AVss = 0.0 V.
*2: Vcc must not drop below Vss - 0.5 V.
*3: USBVcc0 and USBVcc1 must not drop below Vss - 0.5 V.
*4: Ensure that the voltage does not to exceed Vcc + 0.5 V, for example, when the power is turned on.
*5: The maximum output current is the peak value for a single pin.
*6: The average output is the average current for a single pin over a period of 100 ms.
*7: The total average output current is the average current for all pins over a period of 100 ms.
Document Number: 002-05602 Rev. *C
Page 68 of 125
MB9B510T Series
*8:
• See "4. List of Pin Functions" and "5. I/O Circuit Type" about +B input available pin.
• Use within recommended operating conditions.
• Use at DC voltage (current) the +B input.
• The +B signal should always be applied a limiting resistance placed between the +B signal and the device.
• The value of the limiting resistance should be set so that when the +B signal is applied the input current to the device pin does
not exceed rated values, either instantaneously or for prolonged periods.
• Note that when the device drive current is low, such as in the low-power consumption modes, the +B input potential may pass
through the protective diode and increase the potential at the VCC and AVCC pin, and this may affect other devices.
• Note that if a +B signal is input when the device power supply is off (not fixed at 0 V), the power supply is provided from the
pins, so that incomplete operation may result.
• The following is a recommended circuit example (I/O equivalent circuit).
Protection Diode
VCC
VCC
P-ch
Limiting
resistor
+B input (0V to 16V)
Digital output
Digital input
N-ch
R
AVCC
Analog input
WARNING:
−
Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of
absolute maximum ratings. Do not exceed these ratings.
Document Number: 002-05602 Rev. *C
Page 69 of 125
MB9B510T Series
12.2 Recommended Operating Conditions
(Vss = AVss = 0.0V)
Value
Parameter
Power supply voltage
Symbol
Vcc
Conditions
Unit
Remarks
Min
2.7*6
Max
-
-
5.5
3.6
(≤ Vcc)
5.5
(≤ Vcc)
3.6
(≤ Vcc)
5.5
(≤ Vcc)
5.5
AVcc
10
V
3.0
2.7
3.0
2.7
*1
*2
*3
*4
Power supply voltage
(3V power supply) for
USB ch.0
USBVcc0
USBVcc1
V
V
Power supply voltage
(3V power supply) for
USB ch.1
-
Analog power supply voltage
Analog reference voltage
Smoothing capacitor
AVcc
AVRH
CS
-
-
-
2.7
2.7
1
V
V
μF
AVcc = Vcc
for built-in regulator *5
LQS144,
LQP176,
LBE192
When mounted
on four-layer
PCB
Operating
temperature
TA
- 40
+ 85
°C
*1: When P81/UDP0 and P80/UDM0 pin are used as USB (UDP0, UDM0).
*2: When P81/UDP0 and P80/UDM0 pin are used as GPIO (P81, P80).
*3: When P83/UDP1 and P82/UDM1 pin are used as USB (UDP1, UDM1).
*4: When P83/UDP1 and P82/UDM1 pin are used as GPIO (P83, P82).
*5: See "C pin" in "7. Handling Devices" for the connection of the smoothing capacitor.
*6: In between less than the minimum power supply voltage and low voltage reset/interrupt detection voltage
or more, instruction execution and low voltage detection function by built-in High-speed CR (including Main PLL is used) or
built-in Low-speed CR is possible to operate only.
WARNING:
−
The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All
of the device's electrical characteristics are warranted when the device is operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may
adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or
combinations not represented on the datasheet. Users considering application outside the listed conditions are advised to
contact their representatives beforehand.
Document Number: 002-05602 Rev. *C
Page 70 of 125
MB9B510T Series
12.3 DC Characteristics
12.3.1 Current Rating
(Vcc = AVcc = USBVcc0 = USBVcc1 = 2.7V to 5.5V, Vss = AVss = 0V, TA = - 40°C to + 85°C)
Value
Pin
name
Parameter
Symbol
Conditions
Unit
Remarks
Typ*3
Max*4
CPU: 144MHz,
Peripheral: 72MHz,
Flash 2Wait,
TraceBuffer: ON,
FRWTR.RWT = 10,
FSYNDN.SD = 000,
FBFCR.BE = 1
100
180
mA
*1, *5
PLL
RUN mode
CPU: 72MHz,
Peripheral: 72MHz,
Flash 0Wait,
TraceBuffer: OFF,
FRWTR.RWT = 00,
FSYNDN.SD = 000,
FBFCR.BE = 0
CPU/ Peripheral: 4MHz*2,
Flash 0Wait,
65
135
mA
mA
*1, *5
RUN
mode
current
Icc
High-speed
CR
RUN mode
6
57.8
*1
FRWTR.RWT = 00,
FSYNDN.SD = 000
VCC
CPU/ Peripheral: 32kHz,
Flash 0Wait,
FRWTR.RWT = 00,
FSYNDN.SD = 000
CPU/ Peripheral: 100kHz,
Flash 0Wait,
Sub
RUN mode
1.3
1.3
51.7
51.7
mA
mA
*1, *6
*1
Low-speed
CR
RUN mode
FRWTR.RWT = 00,
FSYNDN.SD = 000
PLL
Peripheral: 72MHz
Peripheral: 4MHz*2
Peripheral: 32kHz
Peripheral: 100kHz
30
89
mA
mA
mA
mA
*1, *5
*1
SLEEP mode
High-speed
CR
SLEEP mode
Sub
SLEEP mode
Low-speed
CR
4.5
1.2
1.2
55.9
51.6
51.6
SLEEP
mode
Iccs
current
*1, *6
*1
SLEEP mode
*1: When all ports are fixed.
*2: When setting it to 4 MHz by trimming.
*3: TA=+25°C, VCC=5.5 V
*4: TA=+85°C, VCC=5.5 V
*5: When using the crystal oscillator of 4 MHz (Including the current consumption of the oscillation circuit)
*6: When using the crystal oscillator of 32 kHz (Including the current consumption of the oscillation circuit)
Document Number: 002-05602 Rev. *C
Page 71 of 125
MB9B510T Series
(Vcc = AVcc = USBVcc0 = USBVcc1 = 2.7V to 5.5V, Vss = AVss = 0V, TA = - 40°C to + 85°C)
Value
Pin
Parameter
Symbol
Conditions
Unit
mA
mA
mA
mA
mA
mA
Remarks
*1, *3
*1, *3
*1, *4
*1, *4
*1
Typ*2
Max*2
name
TA = + 25°C,
When LVD is off
TA = + 85°C,
When LVD is off
TA = + 25°C,
When LVD is off
TA = + 85°C,
When LVD is off
TA = + 25°C,
When LVD is off
TA = + 85°C,
4
10
Main
TIMER
mode
-
55
5
TIMER
mode
current
ICCT
1.1
Sub
TIMER
mode
VCC
-
50
5
1
-
STOP
mode
current
ICCH
STOP mode
50
*1
When LVD is off
*1: When all ports are fixed.
*2: VCC=5.5 V
*3: When using the crystal oscillator of 4 MHz (Including the current consumption of the oscillation circuit)
*4: When using the crystal oscillator of 32 kHz (Including the current consumption of the oscillation circuit)
Low-Voltage Detection Current
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 85°C)
Value
Pin
name
Parameter
Symbol
Conditions
Unit
Remarks
Typ
Max
Low-voltage detection
circuit (LVD) power
supply current
At operation
for interrupt
ICCLVD
VCC
4
7
μA
At not detect
Flash Memory Current
Parameter
(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 85°C)
Value
Pin
Symbol
ICCFLASH
Conditions
At Write/Erase
Unit
mA
Remarks
name
Typ
Max
Flash memory
write/erase
current
VCC
12
14
A/D Converter Current
Parameter
(VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = AVRL = 0V, TA = - 40°C to + 85°C)
Value
Pin
Symbol
Conditions
At 1unit operation
At stop
Unit
mA
Remarks
name
Typ
0.57
Max
0.72
Power supply current
ICCAD
AVCC
0.06
1.1
35
1.96
4
μA
mA
μA
At 1unit operation
AVRH=5.5 V
Reference power
supply current
ICCAVRH
AVRH
At stop
0.06
Document Number: 002-05602 Rev. *C
Page 72 of 125
MB9B510T Series
12.3.2 Pin Characteristics
(Vcc = USBVcc0 = USBVcc1 = AVcc = 2.7V to 5.5V, Vss = AVss = 0V, TA = - 40°C to + 85°C)
Value
Parameter
Symbol
Pin name
Conditions
Unit
Remarks
Min
Typ
Max
CMOS
hysteresis
input pin,
MD0, MD1
5 V tolerant
input pin
-
Vcc × 0.8
-
Vcc + 0.3
V
*1
"H" level input
voltage
(hysteresis
input)
VIHS
-
-
Vcc × 0.8
2.0
-
-
Vss + 5.5
Vcc + 0.3
V
V
TTL Schmitt
input pin
CMOS
hysteresis
input pin,
MD0, MD1
5V tolerant
input pin
-
Vss - 0.3
-
Vcc × 0.2
V
*1
"L" level input
voltage
(hysteresis
input)
VILS
-
-
Vss - 0.3
Vss - 0.3
-
-
Vcc × 0.2
0.8
V
V
TTL Schmitt
input pin
Vcc ≥ 4.5 V,
IOH = - 4 mA
4mA type
Vcc - 0.5
-
Vcc
V
*1
*1
Vcc < 4.5 V,
IOH = - 2 mA
Vcc ≥ 4.5 V,
IOH = - 8 mA
Vcc < 4.5 V,
IOH = - 4 mA
Vcc ≥ 4.5 V,
IOH = - 12 mA
8mA type
Vcc - 0.5
-
-
-
Vcc
V
V
V
"H" level
output voltage
VOH
12mA type
Vcc - 0.5
Vcc
Vcc < 4.5 V,
IOH = - 8 mA
USBVcc ≥ 4.5 V,
IOH = - 20.5 mA
USBVcc < 4.5 V,
IOH = - 13.0 mA
P80, P81,
P82, P83
USBVcc - 0.4
USBVcc
*2
Document Number: 002-05602 Rev. *C
Page 73 of 125
MB9B510T Series
Value
Typ
Parameter
Symbol
Pin name
Conditions
Vcc ≥ 4.5 V,
Unit
Remarks
Min
Max
IOL = 4 mA
4 mA type
Vss
-
0.4
V
Vcc < 4.5 V,
IOL = 2 mA
Vcc ≥ 4.5 V,
IOL = 8 mA
Vcc < 4.5 V,
IOL = 4 mA
8 mA type
Vss
Vss
Vss
-
-
0.4
0.4
V
V
V
"L" level
output voltage
VOL
Vcc ≥ 4.5 V,
IOL = 12 mA
12 mA type
Vcc < 4.5 V,
IOL = 8 mA
USBVcc ≥ 4.5 V,
IOL = 18.5 mA
USBVcc < 4.5 V,
IOL = 10.5 mA
-
P80, P81,
P82, P83
-
-
0.4
+ 5
*
Input leak current
IIL
-
- 5
25
μA
kΩ
Vcc ≥ 4.5 V
50
80
100
200
Pull-up resistance
value
RPU
Pull-up pin
Vcc < 4.5 V
30
Other than
VCC,
USBVCC0,
USBVCC1,
VSS,
Input capacitance
CIN
-
-
5
15
pF
AVCC,
AVSS, AVRH
*: USBVcc0 and USBVcc1 are described as USBVcc.
Document Number: 002-05602 Rev. *C
Page 74 of 125
MB9B510T Series
12.4 AC Characteristics
12.4.1 Main Clock Input Characteristics
(Vcc = 2.7V to 5.5V, Vss = 0V, TA = - 40°C to + 85°C)
Value
Pin
Parameter
Symbol
Conditions
Vcc ≥ 4.5 V
Unit
MHz
Remarks
name
Min
Max
50
4
When crystal oscillator is
connected
Vcc < 4.5 V
Vcc ≥ 4.5 V
Vcc < 4.5 V
Vcc ≥ 4.5 V
4
20
Input frequency
FCH
4
50
When using external
clock
MHz
ns
4
20
X0,
X1
20
50
250
250
When using external
clock
Input clock cycle
tCYLH
-
Vcc < 4.5 V
PWH/tCYLH,
PWL/tCYLH
When using external
clock
When using external
clock
Input clock pulse width
45
-
55
5
%
Input clock rise time and
fall time
tCF,
tCR
-
ns
FCM
FCC
-
-
-
-
-
-
144
144
MHz
MHz
Master clock
Base clock (HCLK/FCLK)
Internal operating
clock*1 frequency
FCP0
FCP1
FCP2
-
-
-
-
-
-
-
-
-
72
72
72
MHz
MHz
MHz
APB0 bus clock*2
APB1 bus clock*2
APB2 bus clock*2
-
-
-
-
-
-
-
-
6.94
13.8
13.8
13.8
-
-
-
-
ns
ns
ns
ns
Base clock (HCLK/FCLK)
APB0 bus clock*2
APB1 bus clock*2
tCYCC
tCYCP0
tCYCP1
tCYCP2
Internal operating
clock*1 cycle time
APB2 bus clock*2
*1: For more information about each internal operating clock, see "Chapter 2-1: Clock" in "FM3 Family Peripheral Manual".
*2: For about each APB bus which each peripheral is connected to, see "8. Block Diagram" in this datasheet.
X0
Document Number: 002-05602 Rev. *C
Page 75 of 125
MB9B510T Series
12.4.2 Sub Clock Input Characteristics
(Vcc = 2.7V to 5.5V, Vss = 0V, TA = - 40°C to + 85°C)
Value
Pin
name
Parameter
Symbol
Conditions
Unit
Remarks
Min
Typ
Max
When crystal oscillator is
connected
-
-
32.768
-
kHz
Input frequency
1/tCYLL
-
-
32
10
-
-
100
kHz
When using external clock
When using external clock
X0A,
X1A
Input clock cycle
tCYLL
-
31.25
μs
PWH/tCYLL,
PWL/tCYLL
Input clock pulse width
45
-
55
%
When using external clock
*: See "Sub crystal oscillator" in "7. Handling Devices" for the crystal oscillator used.
X0A
12.4.3 Internal CR Oscillation Characteristics
High-speed Internal CR
(Vcc = 2.7V to 5.5V, Vss = 0V, TA = - 40°C to + 85°C)
Value
Typ
Parameter
Symbol
Conditions
Unit
Remarks
Min
3.96
Max
4.04
TA = + 25°C
4
When trimming*
Clock frequency
FCRH
TA = 0°C to + 70°C
3.84
4
4.16
MHz
TA = - 40°C to + 85°C
TA = - 40°C to + 85°C
3.8
3
4
4
4.2
5
When not trimming
*2
Frequency stability time
tCRWT
-
-
-
90
μs
*1: In the case of using the values in CR trimming area of Flash memory at shipment for frequency trimming.
*2: Frequency stable time is time to stable of the frequency of the High-speed CR clock after the trim value is set. After setting the
trim value, the period when the frequency stability time passes can use the High-speed CR clock as a source clock.
Document Number: 002-05602 Rev. *C
Page 76 of 125
MB9B510T Series
Low-speed Internal CR
(Vcc = 2.7V to 5.5V, Vss = 0V, TA = - 40°C to + 85°C)
Value
Typ
Parameter
Symbol
Conditions
Unit
Remarks
Min
50
Max
150
Clock frequency
FCRL
-
100
kHz
12.4.4 Operating Conditions of Main PLL and USB PLL (In the case of using main clock for input of PLL)
(Vcc = 2.7V to 5.5V, Vss = 0V, TA = - 40°C to + 85°C)
Value
Parameter
Symbol
Unit
Remarks
Min Typ Max
PLL oscillation stabilization wait time*1
(LOCK UP time)
tLOCK
100
-
-
μs
PLL input clock frequency
PLL multiple rate
FPLLI
4
-
-
-
-
-
16
MHz
-
13
200
-
75
multiple
MHz
MHz
PLL macro oscillation clock frequency
Main PLL clock frequency*2
USB clock frequency*3
FPLLO
FCLKPLL
FCLKSPLL
300
144
48
-
MHz
After the M frequency division
*1: Time from when the PLL starts operating until the oscillation stabilizes.
*2: For more information about Main PLL clock (CLKPLL), see "Chapter 2-1: Clock" in "FM3 Family Peripheral Manual".
*3: For more information about USB clock, see "Chapter 2-2: USB clock Generation" in "FM3 Family Peripheral Manual
Communication Macro Part".
12.4.5 Operating Conditions of Main PLL (In the case of using high-speed internal CR)
(Vcc = 2.7V to 5.5V, Vss = 0V, TA = - 40°C to + 85°C)
Value
Parameter
Symbol
Unit
Remarks
Min Typ Max
PLL oscillation stabilization wait time*1
(LOCK UP time)
tLOCK
100
-
-
μs
PLL input clock frequency
PLL multiple rate
FPLLI
-
3.8
50
190
-
4
-
4.2
71
MHz
multiple
MHz
MHz
PLL macro oscillation clock frequency
Main PLL clock frequency*2
FPLLO
FCLKPLL
-
-
300
144
*1: Time from when the PLL starts operating until the oscillation stabilizes.
*2: For more information about Main PLL clock (CLKPLL), see "Chapter 2-1: Clock" in "FM3 Family Peripheral Manual".
Note:
−
Make sure to input to the main PLL source clock, the high-speed CR clock (CLKHC) that the frequency has been trimmed.
Document Number: 002-05602 Rev. *C
Page 77 of 125
MB9B510T Series
Main PLL connection
Main PLL
clock
(CLKPLL)
PLL input
clock
PLL macro
oscillation clock
Main clock (CLKMO)
K
M
divider
Main
PLL
divider
High-speed CR clock (CLKHC)
N
divider
USB PLL connection
PLL input
clock
USB
clock
PLL macro
oscillation clock
Main clock (CLKMO)
K
M
ivider
USB
PLL
divider
N
divider
12.4.6 Reset Input Characteristics
(Vcc = 2.7V to 5.5V, Vss = 0V, TA = - 40°C to + 85°C)
Value
Parameter
Reset input time
Symbol
tINITX
Pin name
Conditions
Unit
ns
Remarks
Min
Max
INITX
-
500
-
Document Number: 002-05602 Rev. *C
Page 78 of 125
MB9B510T Series
12.4.7 Power-on Reset Timing
(Vss = 0V, TA = - 40°C to + 85°C)
Value
Typ
Parameter
Symbol Pin name
Conditions
Unit
Remarks
*1
Min
Max
Power supply shut down time
Power ramp rate
tOFF
-
50
0.9
-
-
-
-
ms
VCC
dV/dt
Vcc:0.2 V to 2.70 V
-
1000
0.76
mV/μs *2
Time until releasing Power-on reset
tPRT
0.46
ms
*1: VCC must be held below 0.2 V for minimum period of tOFF. Improper initialization may occur if this condition is not met.
*2: This dV/dt characteristic is applied at the power-on of cold start (tOFF>50 ms).
Note:
−
If tOFF cannot be satisfied designs must assert external reset(INITX) at power-up and at any brownout event per 12. 4. 6.
2.7V
VCC
VDH
0.2V
0.2V
0.2V
dV/dt
tPRT
tOFF
Internal RST
release
start
RST Active
CPU Operation
Glossary
VDH: detection voltage of Low Voltage detection reset. See ““12.7 Low-Voltage Detection Characteristics”
Document Number: 002-05602 Rev. *C
Page 79 of 125
MB9B510T Series
12.4.8 External Bus Timing
External bus clock output characteristics
(Vcc = 2.7V to 5.5V, Vss = 0V, TA = - 40°C to + 85°C)
Value
Parameter
Output frequency
Symbol
tCYCLE
Pin name
MCLKOUT*1
Conditions
Unit
Min
Max
50*2
32*3
Vcc ≥ 4.5 V
Vcc < 4.5 V
-
-
MHz
MHz
*1: External bus clock (MCLKOUT) is divided clock of HCLK.
For more information about setting of clock divider, see "CHAPTER 12: External Bus Interface" in "FM3 Family PERIPHERAL
MANUAL".
When external bus clock is not output, this characteristic does not give any effect on external bus operation.
*2: When AHB bus clock frequency is more than 100MHz, the divider setting for MCLKOUT must be more than 4.
*3: When AHB bus clock frequency is more than 64MHz, the divider setting for MCLKOUT must be more than 4.
MCLKOUT
External bus signal input/output characteristics
(Vcc = 2.7V to 5.5V, Vss = 0V, TA = - 40°C to + 85°C)
Parameter
Symbol
Conditions
Value
Unit
Remarks
VIH
VIL
0.8 × VCC
0.2 × VCC
0.8 × VCC
0.2 × VCC
V
V
V
V
Signal input characteristics
-
VOH
VOL
Signal output characteristics
VIH
VIL
VIH
VIL
Input signal
VOH
VOL
VOH
VOL
Output signal
Document Number: 002-05602 Rev. *C
Page 80 of 125
MB9B510T Series
Separate Bus Access Asynchronous SRAM Mode
(Vcc = 2.7V to 5.5V, Vss = 0V, TA = - 40°C to + 85°C)
Value
Parameter
Symbol
tOEW
Pin name
Conditions
Unit
ns
Min
Max
Vcc ≥ 4.5 V
Vcc < 4.5 V
Vcc ≥ 4.5 V
Vcc < 4.5 V
Vcc ≥ 4.5 V
Vcc < 4.5 V
Vcc ≥ 4.5 V
Vcc < 4.5 V
Vcc ≥ 4.5 V
Vcc < 4.5 V
Vcc ≥ 4.5 V
Vcc < 4.5 V
Vcc ≥ 4.5 V
Vcc < 4.5 V
Vcc ≥ 4.5 V
Vcc < 4.5 V
Vcc ≥ 4.5 V
Vcc < 4.5 V
Vcc ≥ 4.5 V
Vcc < 4.5 V
Vcc ≥ 4.5 V
Vcc < 4.5 V
Vcc ≥ 4.5 V
Vcc < 4.5 V
Vcc ≥ 4.5 V
Vcc < 4.5 V
Vcc ≥ 4.5 V
Vcc < 4.5 V
Vcc ≥ 4.5 V
Vcc < 4.5 V
MOEX
MOEX
MCLK×n-3
-
Min pulse width
MCSX ↓ → Address output
delay time
-9
-12
+9
+12
MCSX[7:0],
MAD[24:0]
MOEX,
tCSL – AV
tOEH - AX
tCSL - OEL
tOEH - CSH
tCSL - RDQML
tDS - OE
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MCLK×m+9
MCLK×m+12
MCLK×m+9
MCLK×m+12
MCLK×m+9
MCLK×m+12
MCLK×m+9
MCLK×m+12
-
MOEX ↑ →
Address hold time
0
MAD[24:0]
MCLK×m-9
MCLK×m-12
MCSX ↓ →
MOEX ↓ delay time
MOEX ↑ →
MOEX,
MCSX[7:0]
0
MCSX ↑ time
MCLK×m-9
MCLK×m-12
MCSX ↓ →
MCSX,
MDQM ↓ delay time
Data set up →
MOEX ↑ time
MDQM[1:0]
20
38
MOEX,
MADATA[15:0]
MOEX,
MADATA[15:0]
-
MOEX ↑ →
Data hold time
tDH - OE
0
-
-
MWEX
tWEW
MWEX
MCLK×n-3
0
Min pulse width
MWEX ↑ → Address output
delay time
MCLK×m+9
MCLK×m+12
MCLK×n+9
MCLK×n+12
MCLK×m+9
MCLK×m+12
MCLK×n+9
MCLK×n+12
MCLK+9
MWEX,
MAD[24:0]
tWEH - AX
tCSL - WEL
tWEH - CSH
tCSL-WDQML
tCSL - DV
tWEH - DX
MCLK×n-9
MCLK×n-12
MCSX ↓ →
MWEX ↓ delay time
MWEX,
MCSX[7:0]
MWEX ↑ →
MCSX ↑ delay time
MCSX ↓ →
0
MCLK×n-9
MCLK×n-12
MCLK-9
MCSX,
MDQM ↓ delay time
MDQM[1:0]
MCSX ↓ →
Data output time
MWEX ↑ →
MCSX,
MADATA[15:0]
MWEX,
MADATA[15:0]
MCLK-12
MCLK+12
MCLK×m+9
MCLK×m+12
0
Data hold time
Note:
−
When the external load capacitance = 30 pF. (m = 0 to 15, n = 1 to 16)
Document Number: 002-05602 Rev. *C
Page 81 of 125
MB9B510T Series
tCYCLE
MCLK
tOEH-CSH
tWEH-CSH
tWEH-AX
MCSX[7:0]
MAD[24:0]
MOEX
tCSL-AV
tOEH-AX
tCSL-AV
Address
Address
tCSL-OEL
tOEW
tCSL-WDQML
tCSL-RDQML
MDQM[1:0]
MWEX
tCSL-WEL
tWEW
tDS-OE
tDH-OE
tWEH-DX
Invalid
RD
WD
MADATA[15:0]
tCSL-DV
Document Number: 002-05602 Rev. *C
Page 82 of 125
MB9B510T Series
Separate Bus Access Synchronous SRAM Mode
(Vcc = 2.7V to 5.5V, Vss = 0V, TA = - 40°C to + 85°C)
Value
Parameter
Symbol
Pin name
Conditions
Unit
ns
Min
Max
9
12
9
12
9
12
9
12
9
12
MCLK,
Vcc ≥ 4.5 V
Vcc < 4.5 V
Vcc ≥ 4.5 V
Vcc < 4.5 V
Vcc ≥ 4.5 V
Vcc < 4.5 V
Vcc ≥ 4.5 V
Vcc < 4.5 V
Vcc ≥ 4.5 V
Vcc < 4.5 V
Vcc ≥ 4.5 V
Vcc < 4.5 V
Vcc ≥ 4.5 V
Vcc < 4.5 V
Vcc ≥ 4.5 V
Vcc < 4.5 V
Vcc ≥ 4.5 V
Vcc < 4.5 V
Vcc ≥ 4.5 V
Vcc < 4.5 V
Vcc ≥ 4.5 V
Vcc < 4.5 V
Vcc ≥ 4.5 V
Vcc < 4.5 V
Vcc ≥ 4.5 V
Vcc < 4.5 V
Address delay time
tAV
1
1
1
1
1
MAD[24:0]
tCSL
tCSH
tREL
tREH
tDS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MCLK,
MCSX delay time
MOEX delay time
MCSX[7:0]
MCLK,
MOEX
19
37
Data set up →
MCLK ↑ time
MCLK,
-
-
MADATA[15:0]
MCLK ↑ →
Data hold time
MCLK,
tDH
0
1
1
1
1
MADATA[15:0]
9
12
9
12
9
12
9
tWEL
tWEH
tDQML
tDQMH
tOD
MCLK,
MWEX
MWEX delay time
MDQM[1:0]
delay time
MCLK,
MDQM[1:0]
12
MCLK+18
MCLK+24
18
MCLK ↑ →
Data output time
MCLK,
MCLK+1
1
MADATA[15:0]
MCLK ↑ →
Data hold time
MCLK,
tOD
MADATA[15:0]
24
Note:
−
When the external load capacitance = 30 pF.
Document Number: 002-05602 Rev. *C
Page 83 of 125
MB9B510T Series
tCYCLE
MCLK
tCSL
tCSH
MCSX[7:0]
MAD[24:0]
MOEX
tAV
tAV
Address
Address
tREL
tREH
tDQML
tDQMH
tDQML
tDQMH
tWEH
tOD
MDQM[1:0]
MWEX
tWEL
tDS
tDH
MADATA[15:0]
RD
Invalid
WD
tODS
Multiplexed Bus Access Asynchronous SRAM Mode
(Vcc = 2.7V to 5.5V, Vss = 0V, TA = - 40°C to + 85°C)
Value
Parameter
Multiplexed
Symbol
tALE-CHMADV
tCHMADH
Pin name
Conditions
Unit
ns
ns
Min
Max
Vcc ≥ 4.5 V
Vcc < 4.5 V
Vcc ≥ 4.5 V
Vcc < 4.5 V
10
20
0
address delay time
MALE,
MADATA[15:0]
MCLK×n+0
MCLK×n+0
MCLK×n+10
MCLK×n+20
Multiplexed
address hold time
Note:
−
When the external load capacitance = 30 pF. (m = 0 to 15, n = 1 to 16)
Document Number: 002-05602 Rev. *C
Page 84 of 125
MB9B510T Series
MCLK
MCSX[7:0]
MALE
MAD [24:0]
MOEX
MDQM [1:0]
MWEX
MADATA[15:0]
Multiplexed Bus Access Synchronous SRAM Mode
(Vcc = 2.7V to 5.5V, Vss = 0V, TA = - 40°C to + 85°C)
Value
Parameter
Symbol
tCHAL
Pin name
MCLK,
Conditions
Unit
ns
ns
ns
ns
Remarks
Min
Max
Vcc ≥ 4.5 V
Vcc < 4.5 V
Vcc ≥ 4.5 V
Vcc < 4.5 V
9
12
9
1
1
MALE delay time
ALE
tCHAH
12
MCLK ↑ →
Multiplexed
Address delay time
Vcc ≥ 4.5 V
Vcc < 4.5 V
Vcc ≥ 4.5 V
Vcc < 4.5 V
tCHMADV
1
1
tOD
ns
ns
MCLK,
MADATA[15:0]
MCLK ↑ →
Multiplexed
Data output time
tCHMADX
tOD
Note:
−
When the external load capacitance = 30 pF.
Document Number: 002-05602 Rev. *C
Page 85 of 125
MB9B510T Series
MCLK
MCSX[7:0]
MALE
MAD [24:0]
MOEX
MDQM [1:0]
MWEX
MADATA[15:0]
NAND Flash Mode
Parameter
(Vcc = 2.7V to 5.5V, Vss = 0V, TA = - 40°C to + 85°C)
Value
Symbol
tNREW
Pin name
MNREX
Conditions
Unit
Min
Max
Vcc ≥ 4.5 V
Vcc < 4.5 V
Vcc ≥ 4.5 V
Vcc < 4.5 V
Vcc ≥ 4.5 V
Vcc < 4.5 V
Vcc ≥ 4.5 V
Vcc < 4.5 V
Vcc ≥ 4.5 V
Vcc < 4.5 V
Vcc ≥ 4.5 V
Vcc < 4.5 V
Vcc ≥ 4.5 V
Vcc < 4.5 V
Vcc ≥ 4.5 V
Vcc < 4.5 V
Vcc ≥ 4.5 V
Vcc < 4.5 V
Vcc ≥ 4.5 V
Vcc < 4.5 V
MNREX
MCLK×n-3
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Min pulse width
Data setup →
MNREX↑time
MNREX↑→
20
38
-
-
MNREX,
MADATA[15:0]
tDS – NRE
MNREX,
MADATA[15:0]
MNALE,
tDH – NRE
0
-
Data hold time
MCLK×m-9
MCLK×m-12
MCLK×m-9
MCLK×m-12
MCLK×m-9
MCLK×m-12
MCLK×m+9
MCLK×m+12
MCLK×m+9
MCLK×m+12
MCLK×m+9
MCLK×m+12
MCLK×m+9
MCLK×m+12
MNALE↑→
MNWEX delay time
MNALE↓→
tALEH - NWEL
tALEL - NWEL
tCLEH - NWEL
tNWEH - CLEL
tNWEW
MNWEX
MNALE,
MNWEX
MNWEX delay time
MNCLE↑→
MNWEX delay time
MNWEX↑→
MNCLE,
MNWEX
MNCLE,
MNWEX
0
MNCLE delay time
MNWEX
Min pulse width
MNWEX↓→
MNWEX
MCLK×n-3
-
-9
-12
+9
+12
MCLK×m+9
MCLK×m+12
MNWEX,
MADATA[15:0]
tNWEL – DV
tNWEH – DX
Data output time
MNWEX↑→
Data hold time
MNWEX,
MADATA[15:0]
0
Note:
−
When the external load capacitance = 30 pF. (m=0 to 15, n=1 to 16)
Document Number: 002-05602 Rev. *C
Page 86 of 125
MB9B510T Series
NAND Flash Read
MCLK
MNREX
MADATA[15:0]
Read
NAND Flash Address Write
MCLK
MNALE
MNCLE
MNWEX
MADATA[15:0]
Write
Document Number: 002-05602 Rev. *C
Page 87 of 125
MB9B510T Series
NAND Flash Command Write
MCLK
MNALE
MNCLE
MNWEX
MADATA[15:0]
Write
External Ready Input Timing
(Vcc = 2.7V to 5.5V, Vss = 0V, TA = - 40°C to + 85°C)
Value
Parameter
Symbol
Pin name
Conditions
Vcc ≥ 4.5 V
Vcc < 4.5 V
Unit
Remarks
Min
Max
MCLK ↑
19
37
MCLK,
MRDY
MRDY input
setup time
tRDYI
-
ns
Document Number: 002-05602 Rev. *C
Page 88 of 125
MB9B510T Series
When RDY is input
···
MCLK
Original
MOEX
MWEX
Over 2cycles
tRDYI
MRDY
When RDY is released
··· ···
MCLK
2 cycles
Extended
MOEX
MWEX
tRDYI
0.5×VCC
MRDY
Document Number: 002-05602 Rev. *C
Page 89 of 125
MB9B510T Series
12.4.9 Base Timer Input Timing
Timer input timing
(Vcc = 2.7V to 5.5V, Vss = 0V, TA = - 40°C to + 85°C)
Value
Parameter
Input pulse width
Symbol
Pin name
TIOAn/TIOBn
(when using as ECK,
TIN)
Conditions
Unit
ns
Remarks
Min
2tCYCP
Max
tTIWH
tTIWL
,
-
-
tTIWH
tTIWL
ECK
TIN
VIHS
VIHS
VILS
VILS
Trigger input timing
(Vcc = 2.7V to 5.5V, Vss = 0V, TA = - 40°C to + 85°C)
Value
Parameter
Symbol
Pin name
Conditions
Unit
ns
Remarks
Min
2tCYCP
Max
TIOAn/TIOBn
(when using as
TGIN)
tTRGH
,
Input pulse width
-
-
tTRGL
tTRGH
tTRGL
VIHS
VIHS
TGIN
VILS
VILS
Note:
−
tCYCP indicates the APB bus clock cycle time.
About the APB bus number which Base Timer is connected to, see "8. Block Diagram" in this datasheet.
Document Number: 002-05602 Rev. *C
Page 90 of 125
MB9B510T Series
12.4.10 CSIO/UART Timing
CSIO (SPI = 0, SCINV = 0)
(Vcc = 2.7V to 5.5V, Vss = 0V, TA = - 40°C to + 85°C)
Vcc < 4.5 V
Min Max
Vcc ≥ 4.5 V
Min Max
Pin
name
Parameter
Symbol
Conditions
Unit
-
8
-
-
8
-
Baud rate
-
-
-
Mbps
ns
Serial clock cycle time
tSCYC
tSLOVI
SCKx
4tCYCP
4tCYCP
SCKx,
SOTx
SCKx,
SINx
SCKx,
SINx
SCKx
SCKx
SCKx,
SOTx
SCKx,
SINx
SCK ↓ → SOT delay time
SIN → SCK ↑ setup time
SCK ↑ → SIN hold time
- 30
50
0
+ 30
- 20
30
0
+ 20
ns
ns
ns
Master mode
tIVSHI
-
-
-
-
tSHIXI
tSLSH
tSHSL
Serial clock "L" pulse width
Serial clock "H" pulse width
2tCYCP - 10
tCYCP + 10
-
-
2tCYCP - 10
tCYCP + 10
-
-
ns
ns
SCK ↓ → SOT delay time
SIN → SCK ↑ setup time
SCK ↑ → SIN hold time
tSLOVE
tIVSHE
tSHIXE
-
50
-
-
30
-
ns
ns
ns
Slave mode
10
20
10
20
SCKx,
SINx
-
-
SCK fall time
SCK rise time
tF
tR
SCKx
SCKx
-
-
5
5
-
-
5
5
ns
ns
Notes:
−
The above characteristics apply to CLK synchronous mode.
−
tCYCP indicates the APB bus clock cycle time.
About the APB bus number which Multi-function Serial is connected to, see "8. Block Diagram" in this datasheet.
−
−
These characteristics only guarantee the same relocate port number.
For example, the combination of SCKx_0 and SOTx_1 is not guaranteed.
When the external load capacitance = 30 pF.
Document Number: 002-05602 Rev. *C
Page 91 of 125
MB9B510T Series
tSCYC
VOH
SCK
VOL
VOL
tSLOVI
VOH
VOL
SOT
SIN
tIVSHI
VIH
VIL
tSHIXI
VIH
VIL
Master mode
tSLSH
tSHSL
VIH
VIH
tR
VIH
SCK
VIL
VIL
F
t
tSLOVE
VOH
VOL
SOT
SIN
tIVSHE
VIH
VIL
tSHIXE
VIH
VIL
Slave mode
Document Number: 002-05602 Rev. *C
Page 92 of 125
MB9B510T Series
CSIO (SPI = 0, SCINV = 1)
Parameter
(Vcc = 2.7V to 5.5V, Vss = 0V, TA = - 40°C to + 85°C)
Vcc < 4.5 V
Min Max
Vcc ≥ 4.5 V
Min Max
Pin
name
Symbol
Conditions
Unit
-
8
-
-
8
-
Baud rate
-
-
-
Mbps
ns
Serial clock cycle time
tSCYC
tSHOVI
tIVSLI
SCKx
4tCYCP
4tCYCP
SCKx,
SOTx
SCK ↑ → SOT delay time
- 30
+ 30
- 20
+ 20
ns
Master mode
SCKx,
SINx
SCKx,
SINx
SCKx
SCKx
SCKx,
SOTx
SCKx,
SINx
SIN → SCK ↓ setup time
SCK ↓ → SIN hold time
50
0
-
-
30
0
-
-
ns
ns
tSLIXI
tSLSH
tSHSL
Serial clock "L" pulse width
Serial clock "H" pulse width
2tCYCP - 10
tCYCP + 10
-
-
2tCYCP - 10
tCYCP + 10
-
-
ns
ns
SCK ↑ → SOT delay time
SIN → SCK ↓ setup time
SCK ↓ → SIN hold time
tSHOVE
tIVSLE
tSLIXE
-
50
-
-
30
-
ns
ns
ns
Slave mode
10
20
10
20
SCKx,
SINx
-
-
SCK fall time
SCK rise time
tF
tR
SCKx
SCKx
-
-
5
5
-
-
5
5
ns
ns
Notes:
−
The above characteristics apply to CLK synchronous mode.
−
tCYCP indicates the APB bus clock cycle time.
About the APB bus number which Multi-function serial is connected to, see "8. Block Diagram" in this datasheet.
−
−
These characteristics only guarantee the same relocate port number.
For example, the combination of SCKx_0 and SOTx_1 is not guaranteed.
When the external load capacitance = 30 pF.
Document Number: 002-05602 Rev. *C
Page 93 of 125
MB9B510T Series
tSCYC
VOH
VOH
SCK
VOL
tSHOVI
VOH
VOL
SOT
SIN
tIVSLI
VIH
VIL
tSLIXI
VIH
VIL
Master mode
tSHSL
tSLSH
VIH
VIH
tF
SCK
VIL
VIL
tR
VIL
tSHOVE
VOH
VOL
SOT
SIN
tIVSLE
tSLIXE
VIH
VIL
VIH
VIL
Slave mode
Document Number: 002-05602 Rev. *C
Page 94 of 125
MB9B510T Series
CSIO (SPI = 1, SCINV = 0)
Parameter
(Vcc = 2.7V to 5.5V, Vss = 0V, TA = - 40°C to + 85°C)
Vcc < 4.5 V
Min Max
Vcc ≥ 4.5 V
Min Max
Pin
name
Symbol
Conditions
Unit
-
8
-
-
8
-
Baud rate
-
-
-
Mbps
ns
Serial clock cycle time
tSCYC
SCKx
4tCYCP
4tCYCP
SCKx,
SOTx
SCK ↑ → SOT delay time
tSHOVI
- 30
+ 30
- 20
+ 20
ns
SCKx,
SINx
SCKx,
SINx
SCKx,
SOTx
SCKx
SCKx
SCKx,
SOTx
SCKx,
SINx
SIN → SCK ↓ setup time
SCK ↓ → SIN hold time
SOT → SCK ↓ delay time
tIVSLI
tSLIXI
tSOVLI
50
-
-
-
30
-
-
-
ns
ns
ns
Master mode
0
0
2tCYCP - 30
2tCYCP - 30
Serial clock "L" pulse width
Serial clock "H" pulse width
tSLSH
tSHSL
2tCYCP - 10
tCYCP + 10
-
-
2tCYCP - 10
tCYCP + 10
-
-
ns
ns
SCK ↑ → SOT delay time
SIN → SCK ↓ setup time
SCK ↓ → SIN hold time
tSHOVE
tIVSLE
tSLIXE
-
50
-
-
30
-
ns
ns
ns
Slave mode
10
20
10
20
SCKx,
SINx
-
-
SCK fall time
SCK rise time
tF
tR
SCKx
SCKx
-
-
5
5
-
-
5
5
ns
ns
Notes:
−
The above characteristics apply to CLK synchronous mode.
−
tCYCP indicates the APB bus clock cycle time.
About the APB bus number which Multi-function serial is connected to, see "8. Block Diagram" in this datasheet.
−
−
These characteristics only guarantee the same relocate port number.
For example, the combination of SCKx_0 and SOTx_1 is not guaranteed.
When the external load capacitance = 30 pF.
Document Number: 002-05602 Rev. *C
Page 95 of 125
MB9B510T Series
tSCYC
VOH
SCK
VOL
VOL
tSHOVI
tSOVLI
VOH
VOL
VOH
VOL
SOT
SIN
tIVSLI
tSLIXI
VIH
VIL
VIH
VIL
Master mode
tSLSH
tSHSL
SCK
VIH
tF
VIH
VIL
VIH
VIL
tSHOVE
tR
*
VOH
VOL
VOH
VOL
SOT
SIN
tIVSLE
tSLIXE
VIH
VIL
VIH
VIL
Slave mode
*: Changes when writing to TDR register
Document Number: 002-05602 Rev. *C
Page 96 of 125
MB9B510T Series
CSIO (SPI = 1, SCINV = 1)
Parameter
(Vcc = 2.7V to 5.5V, Vss = 0V, TA = - 40°C to + 105°C)
VCC < 4.5 V
Min Max
VCC ≥ 4.5 V
Min Max
Pin
name
Symbol
Conditions
Unit
-
8
-
-
8
-
Baud rate
-
-
-
Mbps
ns
Serial clock cycle time
tSCYC
SCKx
4tCYCP
4tCYCP
SCKx,
SOTx
SCK ↓ → SOT delay time
tSLOVI
- 30
+ 30
- 20
+ 20
ns
SCKx,
SINx
SCKx,
SINx
SCKx,
SOTx
SCKx
SCKx
SCKx,
SOTx
SCKx,
SINx
Master mode
SIN → SCK ↑ setup time
SCK ↑ → SIN hold time
SOT → SCK ↑ delay time
tIVSHI
tSHIXI
tSOVHI
50
-
-
-
30
-
-
-
ns
ns
ns
0
0
2tCYCP - 30
2tCYCP - 30
Serial clock L pulse width
Serial clock H pulse width
tSLSH
tSHSL
2tCYCP - 10
tCYCP + 10
-
-
2tCYCP - 10
tCYCP + 10
-
-
ns
ns
SCK ↓ → SOT delay time
SIN → SCK ↑ setup time
SCK ↑ → SIN hold time
tSLOVE
tIVSHE
tSHIXE
-
50
-
-
30
-
ns
ns
ns
Slave mode
10
20
10
20
SCKx,
SINx
-
-
SCK falling time
SCK rising time
tF
tR
SCKx
SCKx
-
-
5
5
-
-
5
5
ns
ns
Notes:
−
The above characteristics apply to CLK synchronous mode.
−
tCYCP indicates the APB bus clock cycle time.
About the APB bus number which Multi-function serial is connected to, see "8. Block Diagram" in this datasheet.
−
−
These characteristics only guarantee the same relocate port number.
For example, the combination of SCKx_0 and SOTx_1 is not guaranteed.
When the external load capacitance = 30 pF.
Document Number: 002-05602 Rev. *C
Page 97 of 125
MB9B510T Series
tSCYC
VOH
VOH
SCK
VOL
tSOVHI
tSLOVI
VOH
VOL
VOH
VOL
SOT
SIN
tSHIXI
tIVSHI
VIH
VIL
VIH
VIL
Master mode
tR
tF
tSHSL
tSLSH
VIH
VIH
SCK
VIL
VIL
VIL
tSLOVE
VOH
VOL
VOH
VOL
SOT
SIN
tIVSHE
tSHIXE
VIH
VIL
VIH
VIL
Slave mode
UART external clock input (EXT = 1)
Parameter
(Vcc = 2.7V to 5.5V, Vss = 0V, TA = - 40°C to + 85°C)
Value
Symbol
Conditions
Unit
Remarks
Min
tCYCP + 10
tCYCP + 10
Max
Serial clock "L" pulse width
Serial clock "H" pulse width
SCK fall time
tSLSH
tSHSL
tF
-
-
5
5
ns
ns
ns
ns
CL = 30 pF
-
-
SCK rise time
tR
tR
tF
VIH
tSHSL
tSLSH
SCK
VIH
VIH
VIL
VIL
VIL
Document Number: 002-05602 Rev. *C
Page 98 of 125
MB9B510T Series
12.4.11 External Input Timing
(Vcc = 2.7V to 5.5V, Vss = 0V, TA = - 40°C to + 85°C)
Value
Parameter
Symbol
Pin name
ADTG
Conditions
Unit
Remarks
Min
Max
A/D converter trigger input
-
-
2tCYCP
*
-
ns
FRCKx
ICxx
Free-run timer input clock
Input capture
tINH,
tINL
DTTIxX
2tCYCP
*
-
-
ns
ns
Wave form generator
Input pulse width
Except
Timer mode,
Stop mode
Timer mode,
Stop mode
2tCYCP + 100*
500
INTxx,
NMIX
External interrupt
NMI
-
ns
*: tCYCP indicates the APB bus clock cycle time.
About the APB bus number which the A/D converter, Multi-function Timer, External interrupt are connected to,
see "8. Block Diagram” in this datasheet.
Document Number: 002-05602 Rev. *C
Page 99 of 125
MB9B510T Series
12.4.12 Quadrature Position/Revolution Counter timing
(Vcc = 2.7V to 5.5V, Vss = 0V, TA = - 40°C to + 85°C)
Value
Parameter
AIN pin "H" width
AIN pin "L" width
BIN pin "H" width
BIN pin "L" width
BIN rise time from
AIN pin "H" level
AIN fall time from
BIN pin "H" level
BIN fall time from
AIN pin "L" level
AIN rise time from
BIN pin "L" level
AIN rise time from
BIN pin "H" level
BIN fall time from
AIN pin "H" level
AIN fall time from
BIN pin "L" level
Symbol
tAHL
tALL
tBHL
tBLL
Conditions
Unit
Min
Max
-
-
-
-
tAUBU
tBUAD
tADBD
tBDAU
tBUAU
tAUBD
tBDAD
tADBU
PC_Mode2 or PC_Mode3
PC_Mode2 or PC_Mode3
PC_Mode2 or PC_Mode3
PC_Mode2 or PC_Mode3
PC_Mode2 or PC_Mode3
PC_Mode2 or PC_Mode3
PC_Mode2 or PC_Mode3
PC_Mode2 or PC_Mode3
2tCYCP
*
-
ns
BIN rise time from
AIN pin "L" level
ZIN pin "H" width
ZIN pin "L" width
tZHL
tZLL
QCR:CGSC="0"
QCR:CGSC="0"
AIN/BIN rise and fall time from
determined ZIN level
Determined ZIN level from AIN/BIN
rise and fall time
tZABE
tABEZ
QCR:CGSC="1"
QCR:CGSC="1"
*: tCYCP indicates the APB bus clock cycle time.
About the APB bus number which the Quadrature Position/Revolution Counter is connected to, see "8. Block Diagram" in this
datasheet.
tALL
tAHL
AIN
BIN
tADBD
tAUBU
tBUAD
tBDAU
tBHL
tBLL
Document Number: 002-05602 Rev. *C
Page 100 of 125
MB9B510T Series
tBLL
tBHL
BIN
AIN
tBDAD
tBUAU
tAUBD
tADBU
tAHL
tALL
ZIN
ZIN
AIN/BIN
Document Number: 002-05602 Rev. *C
Page 101 of 125
MB9B510T Series
12.4.13 I2C Timing
(Vcc = 2.7V to 5.5V, Vss = 0V, TA = - 40°C to + 85°C)
Standard-mode
Fast-mode
Parameter
Symbol
FSCL
Conditions
Unit
kHz
Remarks
Min
Max
100
Min
Max
SCL clock frequency
(Repeated) START condition hold time
SDA ↓ → SCL ↓
0
0
400
-
tHDSTA
4.0
-
0.6
μs
SCLclock "L" width
SCLclock "H" width
(Repeated) START setup time
SCL ↑ → SDA ↓
Data hold time
SCL ↓ → SDA ↓ ↑
Data setup time
SDA ↓ ↑ → SCL ↑
STOP condition setup time
SCL ↑ → SDA ↑
tLOW
tHIGH
4.7
4.0
-
-
1.3
0.6
-
-
μs
μs
tSUSTA
tHDDAT
tSUDAT
tSUSTO
4.7
0
-
0.6
0
-
μs
μs
ns
μs
CL = 30 pF,
3.45*2
0.9*3
R = (Vp/IOL)*1
250
4.0
-
-
100
0.6
-
-
Bus free time between
"STOP condition" and
"START condition"
tBUF
4.7
-
1.3
-
μs
8 MHz ≤
tCYCP ≤ 40 MHz
40 MHz <
tCYCP ≤ 60 MHz
60 MHz <
tCYCP ≤ 72 MHz
4
4
2 tCYCP
3 tCYCP
4 tCYCP
*
*
*
-
-
-
2 tCYCP
3 tCYCP
4 tCYCP
*
*
*
-
-
-
ns
ns
ns
*5
4
4
4
4
Noise filter
tSP
*5
*5
*1: R and C represent the pull-up resistance and load capacitance of the SCL and SDA lines, respectively.
Vp indicates the power supply voltage of the pull-up resistance and IOL indicates VOL guaranteed current.
*2: The maximum tHDDAT must satisfy that it does not extend at least "L" period (tLOW) of device's SCL signal.
*3: A Fast-mode I2C bus device can be used on a Standard-mode I2C bus system as long as the device satisfies the requirement
of "tSUDAT ≥ 250 ns".
*4: tCYCP is the APB bus clock cycle time.
About the APB bus number that I2C is connected to, see "8. Block Diagram" in this datasheet.
To use Standard-mode, set the APB bus clock at 2 MHz or more
To use Fast-mode, set the APB bus clock at 8 MHz or more.
*5: The number of steps of the noise filter can be changed with register settings.
Change the number of the noise filter steps according to APB2 bus clock frequency.
SDA
SCL
Document Number: 002-05602 Rev. *C
Page 102 of 125
MB9B510T Series
12.4.14 ETM Timing
(Vcc = 2.7V to 5.5V, Vss = 0V, TA = - 40°C to + 85°C)
Value
Parameter
Symbol
tETMH
Pin name
TRACECLK,
Conditions
Vcc ≥ 4.5 V
Unit
ns
Remarks
Min
Max
2
2
-
9
Data hold
TRACED[3:0]
Vcc < 4.5 V
Vcc ≥ 4.5 V
Vcc < 4.5 V
Vcc ≥ 4.5 V
Vcc < 4.5 V
15
50
32
-
MHz
MHz
ns
TRACECLK
frequency
1/ tTRACE
-
TRACECLK
20
TRACECLK
cycle time
tTRACE
31.25
-
ns
Note:
−
When the external load capacitance = 30 pF.
HCLK
TRACECLK
TRACED[3:0]
Document Number: 002-05602 Rev. *C
Page 103 of 125
MB9B510T Series
12.4.15 JTAG Timing
(Vcc = 2.7V to 5.5V, Vss = 0V, TA = - 40°C to + 85°C)
Value
Parameter
Symbol
tJTAGS
Pin name
TCK,
Conditions
Vcc ≥ 4.5 V
Unit
ns
Remarks
Min
Max
TMS, TDI setup time
15
15
-
-
TMS, TDI
Vcc < 4.5 V
Vcc ≥ 4.5 V
TCK,
TMS, TDI
TMS, TDI hold time
TDO delay time
tJTAGH
ns
ns
Vcc < 4.5 V
Vcc ≥ 4.5 V
-
-
25
45
TCK,
TDO
tJTAGD
Vcc < 4.5 V
Note:
−
When the external load capacitance = 30 pF.
TCK
TMS/TDI
TDO
Document Number: 002-05602 Rev. *C
Page 104 of 125
MB9B510T Series
12.5 12-bit A/D Converter
Electrical Characteristics for the A/D Converter
(Vcc = AVcc = 2.7V to 5.5V, Vss = AVss = 0V, TA = - 40°C to + 85°C)
Value
Pin
Parameter
Resolution
Symbol
Unit
Remarks
name
Min
Typ
Max
-
-
-
-
-
-
-
-
-
-
-
-
12
bit
Integral Nonlinearity
± 4.5
± 2.5
± 15
LSB
LSB
mV
mV
Differential Nonlinearity
Zero transition voltage
Full-scale transition voltage
AVRH = 2.7 V to 5.5 V
VZT
VFST
ANxx
ANxx
AVRH ± 15
1.0*1
1.2*1
*2
-
-
-
-
-
-
-
-
AVcc ≥ 4.5 V
AVcc < 4.5 V
AVcc ≥ 4.5 V
AVcc < 4.5 V
Conversion time
Sampling time
-
-
-
μs
Ts
ns
*2
Compare clock cycle*3
Tcck
Tstt
-
-
50
-
-
-
2000
ns
State transition time to
operation permission
1.0
μs
Analog input capacity
Analog input resistance
CAIN
RAIN
-
-
-
-
-
-
12.9
pF
2
AVcc ≥ 4.5 V
kΩ
3.8
4
AVcc < 4.5 V
Interchannel disparity
Analog port input leak current
Analog input voltage
Reference voltage
-
-
-
-
-
-
-
-
-
-
LSB
μA
V
ANxx
ANxx
AVRH
-
5
AVSS
2.7
AVRH
AVCC
V
*1: The Conversion time is the value of sampling time (Ts) + compare time (Tc).
The condition of the minimum conversion time is the following.
AVcc ≥ 4.5 V, HCLK=120 MHz
AVcc < 4.5 V, HCLK=120 MHz
sampling time: 300 ns
sampling time: 500 ns
compare time: 700 ns
compare time: 700 ns
Ensure that it satisfies the value of the sampling time (Ts) and compare clock cycle (Tcck).
For setting of the sampling time and compare clock cycle, see "Chapter 1-1: A/D Converter" in "FM3 Family Peripheral
Manual Analog Macro Part".
The registers setting of the A/D Converter are reflected in the operation according to the APB bus clock timing.
The sampling clock and compare clock is generated from the Base clock (HCLK).
About the APB bus number which the A/D Converter is connected to, see "8. Block Diagram" in this datasheet.
*2: A necessary sampling time changes by external impedance.
Ensure that it set the sampling time to satisfy (Equation 1).
*3: Compare time (Tc) is the value of (Equation 2).
Document Number: 002-05602 Rev. *C
Page 105 of 125
MB9B510T Series
ANxx
Comparator
Analog input pin
RAIN
Rext
Analog signal
source
CAIN
(Equation 1) TS ≥ ( RAIN + Rext ) × CAIN × 9
TS:
Sampling time
RAIN
:
Input resistance of A/ D = 2 kΩ at 4.5 V ≤ AVCC ≤ 5.5 V
Input resistance of A/D = 3.8 kΩ at 2.7 V ≤ AVCC < 4.5 V
Input capacity of A/D = 12.9 pF at 2.7 V ≤ AVCC ≤ 5.5 V
Output impedance of external circuit
CAIN
:
Rext:
(Equation 2) Tc = Tcck × 14
Tc:
Compare time
Compare clock cycle
Tcck:
Document Number: 002-05602 Rev. *C
Page 106 of 125
MB9B510T Series
Definition of 12-bit A/D Converter Terms
Resolution:
Analog variation that is recognized by an A/D converter.
Deviation of the line between the zero-transition point
Integral Nonlinearity:
(0b000000000000←→0b000000000001) and the full-scale transition point
(0b111111111110←→0b111111111111) from the actual conversion characteristics.
Differential Nonlinearity:
Deviation from the ideal value of the input voltage that is required to change the output code
by 1 LSB.
Integral Nonlinearity
Differential Nonlinearity
0xFFF
Actual conversion
Actual conversion
characteristics
0xFFE
0xFFD
0x(N+1)
0xN
characteristics
{1 LSB(N-1) + VZT}
VFST
Ideal characteristics
(Actually-
measured
value)
VNT
0x004
0x003
0x002
0x001
(Actual
value)
V(N+1)T
0x(N-1)
0x(N-2)
(Actually-measured
value)
Actual conversion
characteristics
VNT
(Asured
value)
Ideal characteristics
ly-measured value)
Analog input
VZT
Actual conversion characteristics
AVss
AVRH
AVss
AVRH
Analog input
VNT - {1LSB × (N - 1) + VZT}
1LSB
Integral Nonlinearity of digital output N =
[LSB]
V(N + 1) T - VNT
- 1 [LSB]
1LSB
Differential Nonlinearity of digital output N =
VFST - VZT
1LSB =
4094
N:
A/D converter digital output value.
VZT:
VFST
VNT:
Voltage at which the digital output changes from 0x000 to 0x001.
Voltage at which the digital output changes from 0xFFE to 0xFFF.
Voltage at which the digital output changes from 0x(N − 1) to 0xN.
:
Document Number: 002-05602 Rev. *C
Page 107 of 125
MB9B510T Series
12.6 USB characteristics
The USB characteristics of ch.0 and those of ch.1 are the same.
USBVcc0 and USBVcc1 are described as USBVcc below.
(Vcc = 2.7V to 5.5V, USBVcc = 3.0V to 3.6V, Vss = 0V, TA = - 40°C to + 85°C)
Value
Parameter
Symbol Pin name
Conditions
Unit Remarks
Min
2.0
Max
Input "H" level voltage
VIH
VIL
-
-
-
-
USBVcc + 0.3
V
V
V
V
*1
*1
*2
*2
Input "L" level voltage
Vss - 0.3 0.8
Input
characteristics
Differential input sensitivity
Different common mode range
VDI
VCM
0.2
0.8
-
2.5
External pull-down
resistance= 15 kΩ
External pull-up
resistance= 1.5 kΩ
-
Output "H" level voltage
Output "L" level voltage
VOH
2.8
0.0
3.6
0.3
V
V
*3
*3
UDP0,
VOL
UDM0
VCRS
Crossover voltage
Rise time
1.3
4
2.0
20
V
*4
*5
*5
*5
*6
*7
*7
*7
tFR
Full-Speed
ns
ns
%
Ω
ns
ns
%
Output
characteristics
Fall time
tFF
Full-Speed
Full-Speed
Full-Speed
Low-Speed
Low-Speed
Low-Speed
4
20
Rise/ fall time matching
Output impedance
Rise time
Fall time
Rise/ fall time matching
tFRFM
ZDRV
tLR
tLF
tLRFM
90
28
75
75
80
111.11
44
300
300
125
*1: The switching threshold voltage of Single-End-Receiver of USB I/O buffer is set as within VIL (Max) = 0.8 V,
VIH (Min) = 2.0 V (TTL input standard).
There are some hysteresis to lower noise sensitivity.
*2: Use differential-Receiver to receive USB differential data signal.
Differential-Receiver has 200 mV of differential input sensitivity when the differential data input is within 0.8 V to 2.5 V to the local
ground reference level.
Above voltage range is the common mode input voltage range.
Common mode input voltage [V]
Document Number: 002-05602 Rev. *C
Page 108 of 125
MB9B510T Series
*3: The output drive capability of the driver is below 0.3 V at Low-State (VOL) (to 3.6 V and 1.5 kΩ load), and 2.8 V or above
(to ground and 1.5 kΩ load) at High-State (VOH).
*4: The cross voltage of the external differential output signal (D + /D −) of USB I/O buffer is within 1.3 V to 2.0 V.
VCRS specified range
*5: They indicate rise time (Trise) and fall time (Tfall) of the full-speed differential data signal.
They are defined by the time between 10% and 90% of the output signal voltage.
For full-speed buffer, Tr/Tf ratio is regulated as within ± 10% to minimize RFI emission.
Falling time
Rising time
Document Number: 002-05602 Rev. *C
Page 109 of 125
MB9B510T Series
*6: USB Full-speed connection is performed via twist pair cable shield with 90Ω ± 15% characteristic impedance (Differential Mode).
USB standard defines that output impedance of USB driver must be in range from 28 Ω to 44 Ω. So, discrete series resistor (Rs)
addition is defined in order to satisfy the above definition and keep balance.
When using this USB I/O, use it with 25 Ω to 30 Ω (recommendation value 27 Ω) series resistor Rs.
28Ω to 44Ω Equiv. Imped.
28Ω to 44Ω Equiv. Imped.
Mount it as external resistance.
Rs series resistor 25Ω to 30Ω
Series resistor of 27Ω (recommendation value) must be added.
And, use "resistance with an uncertainty of 5% by E24 sequence".
*7: They indicate rise time (Trise) and fall time (Tfall) of the low-speed differential data signal.
They are defined by the time between 10% and 90% of the output signal voltage.
Rising time
Falling time
See Figure "Low-Speed Load (Compliance Load)" for conditions of external load.
Document Number: 002-05602 Rev. *C
Page 110 of 125
MB9B510T Series
Low-Speed Load (Upstream Port Load) - Reference 1
CL = 50pF to 150pF
CL = 50pF to 150pF
Low-Speed Load (Downstream Port Load) - Reference 2
CL =200pF to
600pF
CL =200pF to
600pF
Low-Speed Load (Compliance Load)
CL = 200pF to 450pF
CL = 200pF to 450pF
Document Number: 002-05602 Rev. *C
Page 111 of 125
MB9B510T Series
12.7 Low-Voltage Detection Characteristics
12.7.1 Low-Voltage Detection Reset
(TA = - 40°C to + 85°C)
Value
Typ
2.45
Parameter
Detected voltage
Released voltage
Symbol
Conditions
Unit
Remarks
Min
2.25
2.30
Max
2.65
2.70
VDL
VDH
-
-
V
V
When voltage drops
When voltage rises
2.50
12.7.2 Interrupt of Low-Voltage Detection
(TA = - 40°C to + 85°C)
Value
Typ
2.8
Parameter
Symbol
Conditions
Unit
Remarks
Min
Max
Detected voltage
Released voltage
Detected voltage
VDL
VDH
VDL
2.58
2.67
2.76
3.02
V
When voltage drops
When voltage rises
When voltage drops
SVHI = 0000
2.9
3.0
3.1
3.2
3.3
3.6
3.7
3.7
3.8
4.0
4.1
4.1
4.2
4.2
4.3
3.13
3.24
3.34
3.45
3.56
3.88
3.99
3.99
4.10
4.32
4.42
4.42
4.53
4.53
4.64
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
SVHI = 0001
SVHI = 0010
SVHI = 0011
SVHI = 0100
SVHI = 0111
SVHI = 1000
SVHI = 1001
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
2.85
2.94
3.04
3.31
3.40
3.40
3.50
3.68
3.77
3.77
3.86
3.86
3.96
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
LVD stabilization wait time
TLVDW
-
-
-
4032 × tCYCP
*
μs
*: tCYCP indicates the APB2 bus clock cycle time.
Document Number: 002-05602 Rev. *C
Page 112 of 125
MB9B510T Series
12.8 Flash Memory Write/Erase Characteristics
12.8.1 Write / Erase time
(Vcc = 2.7V to 5.5V, TA = - 40°C to + 85°C)
Value
Parameter
Typ*
Unit
Remarks
Max*
Large Sector
Small Sector
0.7
0.3
3.7
1.1
Sector erase time
s
Includes write time prior to internal erase
Half word (16-bit)
write time
12
384
68
μs
Not including system-level overhead time.
Includes write time prior to internal erase
Chip erase time
13.6
s
*: The typical value is immediately after shipment, the maximum value is guarantee value under 100,000 cycle of erase/write.
12.8.2 Write cycles and data hold time
Erase/write cycles
(cycle)
Data hold time
(year)
Remarks
1,000
20*
10*
5*
10,000
100,000
*: At average + 85C
Document Number: 002-05602 Rev. *C
Page 113 of 125
MB9B510T Series
12.9 Return Time from Low-Power Consumption Mode
12.9.1 Return Factor: Interrupt
The return time from Low-Power consumption mode is indicated as follows. It is from receiving the return factor to starting the
program operation.
Return Count Time
(VCC = 2.7V to 5.5V, TA = - 40°C to + 85°C)
Value
Parameter
Symbol
Unit
Remarks
Typ
Max*
SLEEP mode
tCYCC
40
ns
High-speed CR TIMER mode,
Main TIMER mode,
80
μs
PLL TIMER mode
Ticnt
Low-speed CR TIMER mode
Sub TIMER mode
453
453
453
737
737
737
μs
μs
μs
STOP mode
*: The maximum value depends on the accuracy of built-in CR.
Operation example of return from Low-Power consumption mode (by external interrupt*)
Ext.INT
Interrupt factor
Active
accept
Ticnt
Interrupt factor
clear by CPU
CPU
Operation
Start
*: External interrupt is set to detecting fall edge.
Document Number: 002-05602 Rev. *C
Page 114 of 125
MB9B510T Series
Operation example of return from Low-Power consumption mode (by internal resource interrupt*)
Internal
Resource INT
Interrupt factor
accept
Active
Ticnt
Interrupt factor
clear by CPU
CPU
Operation
Start
*: Internal resource interrupt is not included in return factor by the kind of Low-Power consumption mode.
Notes:
−
The return factor is different in each Low-Power consumption modes.
See "Chapter 6: Low Power Consumption Mode" and "Operations of Standby Modes" in FM3 Family Peripheral Manual about
the return factor from Low-Power consumption mode.
−
When interrupt recoveries, the operation mode that CPU recoveries depend on the state before
the Low-Power consumption mode transition. See "Chapter 6: Low Power Consumption Mode" in "FM3 Family Peripheral
Manual".
Document Number: 002-05602 Rev. *C
Page 115 of 125
MB9B510T Series
12.9.2 Return Factor: Reset
The return time from Low-Power consumption mode is indicated as follows. It is from releasing reset to starting the program
operation.
Return Count Time
(VCC = 2.7V to 5.5V, TA = - 40°C to + 85°C)
Value
Parameter
Symbol
Unit
Remarks
Typ
Max*
SLEEP mode
321
321
461
461
μs
μs
High-speed CR TIMER mode,
Main TIMER mode,
PLL TIMER mode
Trcnt
Low-speed CR TIMER mode
Sub TIMER mode
441
441
441
701
701
701
μs
μs
μs
STOP mode
*: The maximum value depends on the accuracy of built-in CR.
Operation example of return from Low-Power consumption mode (by INITX)
INITX
Internal RST
RST Active
Release
Trcnt
CPU
Operation
Start
・
Document Number: 002-05602 Rev. *C
Page 116 of 125
MB9B510T Series
Operation example of return from low power consumption mode (by internal resource reset*)
Internal
Resource RST
Internal RST
RST Active
Release
Trcnt
CPU
Operation
Start
*: Internal resource reset is not included in return factor by the kind of Low-Power consumption mode.
Notes:
−
−
−
The return factor is different in each Low-Power consumption modes.
See "Chapter 6: Low Power Consumption Mode" and "Operations of Standby Modes" in FM3 Family Peripheral Manual.
When interrupt recoveries, the operation mode that CPU recoveries depend on the state before the Low-Power consumption
mode transition. See "Chapter 6: Low Power Consumption Mode" in "FM3 Family Peripheral Manual".
The time during the power-on reset/low-voltage detection reset is excluded. See “12.4.3. Internal CR Oscillation
Characteristics in 12.4. AC Characteristics in 12. Electrical Characteristics” for the detail on the time during the power-on
reset/low -voltage detection reset.
−
−
When in recovery from reset, CPU changes to the high-speed CR run mode. When using the main clock or the PLL clock, it is
necessary to add the main clock oscillation stabilization wait time or the Main PLL clock stabilization wait time.
The internal resource reset means the watchdog reset and the CSV reset.
Document Number: 002-05602 Rev. *C
Page 117 of 125
MB9B510T Series
13.Ordering Information
On-chip
Flash
memory
On-chip
SRAM
Part number
Package
Packing
MB9BF516SPMC-GK7E1
MB9BF517SPMC-GK7E1
MB9BF518SPMC-GK7E1
MB9BF516TPMC-GK7E1
MB9BF517TPMC-GK7E1
MB9BF518TPMC-GK7E1
MB9BF516TBGL-GK7E1
MB9BF517TBGL-GK7E1
MB9BF518TBGL-GK7E1
512 Kbyte
64 Kbyte
144-pin plastic LQFP
(0.5 mm pitch), (LQS144)
768 Kbyte
1 Mbyte
96 Kbyte
128 Kbyte
64 Kbyte
96 Kbyte
128 Kbyte
64 Kbyte
96 Kbyte
128 Kbyte
512 Kbyte
768 Kbyte
1 Mbyte
176-pin plastic LQFP
(0.5 mm pitch) , (LQP176)
Tray
512 Kbyte
768 Kbyte
1 Mbyte
192-ball plastic FBGA
(0.8 mm pitch), (LBE192)
Document Number: 002-05602 Rev. *C
Page 118 of 125
MB9B510T Series
14.Package Dimensions
Package Type
Package Code
LQP176
LQFP 176
4
D
5
7
D1
132
89
89
132
133
133
88
88
E1
E
5
7
4
3
6
176
45
45
176
1
44
44
1
e
2
A-B
5
7
D
3
0.10
A-B
C
BOTTOM VIEW
0.20
C A-B D
b
0.08
C
D
8
TOP VIEW
2
A
c
9
A
SEATING
PLANE
A1
0.25
A'
b
L1
10
0.08
C
SECTION A-A'
L
SIDE VIEW
DIMENSIONS
SYMBOL
MIN. NOM. MAX.
1.70
A
A1
b
0.05
0.17
0.09
0.15
0.27
0.20
0.22
c
D
26.00 BSC
24.00 BSC
0.50 BSC
26.00 BSC
24.00 BSC
0.60
D1
e
E
E1
L
0.45
0.30
0
0.75
0.70
8
L1
0.50
PACKAGE OUTLINE, 176 LEAD LQFP
24.0X24.0X1.7 MM LQP176 REV**
002-15150 **
Document Number: 002-05602 Rev. *C
Page 119 of 125
MB9B510T Series
Package Type
Package Code
LQFP 144
LQS144
4
5
4
5
D
D
7
7
D1
D1
108
73
73
108
109
109
72
72
E1
E
E
E1
5
7
5
7
4
4
3
3
6
144
144
37
37
1
1
36
36
2
A-B
5
D
7
BOTTOM VIEW
e
A-B
3
0.10
A-B
C
0.20
C
D
b
0.08
C
D
8
TOP VIEW
2
A
9
c
A
A1
SEATING
PLANE
0.25
L
b
L1
10
A'
SECTION A-A'
0.08
C
SIDE VIEW
DIMENSIONS
SYMBOL
MIN. NOM. MAX.
1.70
A
A1
b
0.05
0.17 0.22 0.27
0.09 0.20
0.15
c
D
D1
e
22.00 BSC
20.00 BSC
0.50 BSC
E
22.00 BSC
20.00 BSC
E1
L
0.45 0.60 0.75
0.30 0.50 0.70
L1
PACKAGE OUTLINE, 144 LEAD LQFP
20.0X20.0X1.7 MM LQS144 REV*A
002-13015 *A
Document Number: 002-05602 Rev. *C
Page 120 of 125
MB9B510T Series
Package Type
Package Code
FBGA 192
LBE192
A
0.20
C
14
13
12
11
10
9
2X
7
8
7
6
5
4
3
2
1
P
N
M
L
K
J
H
G
F
E
D
C
B
A
INDEX MARK
8
PIN A1
CORNER
B
7
192xφ b
0.08
C A B
0.20
2X
C
6
TOP VIEW
BOTTOM VIEW
DETAIL A
C
0.10
C
SIDE VIEW
DETAIL A
NOTES
1. ALL DIMENSIONS ARE IN MILLIMETERS.
DIMENSIONS
SYMBOL
A
MIN. NOM. MAX.
1.45
2. DIMENSIONS AND TOLERANCES METHODS PER ASME Y14.5-2009.
THIS OUTLINE CONFORMS TO JEP95, SECTION 4.5.
3. BALL POSITION DESIGNATION PER JEP95, SECTION 3, SPP-010.
4. "e" REPRESENTS THE SOLDER BALL GRID PITCH.
A
D
E
0.25
0.35
12.00 BSC
12.00 BSC
10.40 BSC
10.40 BSC
14
0.45
1
5. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D" DIRECTION.
SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION.
n IS THE NUMBER OF POPULATED SOLDER BALL POSITIONS FOR MATRIX
SIZE MD X ME.
D
E
1
6. DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER
IN A PLANE PARALLEL TO DATUM C.
1
MD
ME
n
7. "SD" AND "SE" ARE MEASURED WITH RESPECT TO DATUMS A AND B AND
DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW.
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW,
"SD" OR "SE" =0.
14
192
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW,
"SD" = eD/2 AND "SE" = eE/2.
b
eD
0.35
0.45
0.55
0.80 BSC
0.80 BSC
0.40 BSC
8. A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK.
METALLIZED MARK INDENTATION OR OTHER MEANS.
eE
9. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS.
SD / SE
PACKAGE OUTLINE, 192 BALL FBGA
12.00X12.00X1.45 MM LBE192 REV**
002-13493 **
Document Number: 002-05602 Rev. *C
Page 121 of 125
MB9B510T Series
15.Major Changes
Spansion Publication Number: DS706-00019
Page
Section
Change Results
Revision 1.0
-
-
-
-
Initial release
Preliminary → Datasheet
FEATURES
Multi-function Serial Interface
(Max 8channels)
Revised the following description.
"4 channels with 16-byte FIFO"
"4 channels with 16steps×9-bit FIFO"
Added the following description.
"ch.4 to ch.7: FIFO (16steps × 9-bit)
ch.0 to ch.3: No FIFO"
3
7
PRODUCT LINEUP
Multi-function Serial Interface
(UART/CSIO/LIN/I2C)
PIN ASSIGNMENT
Added the description of "Note".
9 to 11
54
I/O CIRCUIT TYPE
HANDLING DEVICES
BLOCK DIAGRAM
Added the following description to "Type H".
IOH = -20.5mA, IOL = 18.5mA
Revised the description of "•C pin".
Added the description of "Base Timer".
Corrected the figure.
62, 63
64
TIOA: input → input/output
TIOB: output → input
ELECTRICAL CHARACTERISTICS
2. Recommended Operating Conditions
Corrected the value of "Analog reference voltage (AVRH)".
Min: AVSS → 2.7V
Added the "Smoothing capacitor (CS)".
Added the footnote.
75
3. DC Characteristics
(1) Current Rating
Revised the value of "TBD".
Revised the unit.
77
Deleted "and estimated values."
Deleted the footnote "*1".
(2) Pin Characteristics
78, 79
80
4. AC Characteristics
Revised the value of Input frequency (FCH) at "Vcc ≥ 4.5V".
Max: 50 → 48
Added "Internal operating clock frequency (FCM): Master clock".
Added "Main PLL clock frequency (FCLKPLL)".
Added "USB/Ethernet clock frequency (FCLKSPLL)".
(1) Main Clock Input Characteristics
(4-1) Operating Conditions of Main and USB PLL (In
the case of using main clock for input of PLL)
(4-2) Operating Conditions of Main PLL
(In the case of using high-speed internal CR)
5. 12-bit A/D Converter
82
Deleted "(Preliminary value)".
Added the Symbol.
Electrical characteristics for the
A/D converter
Revised the value of "TBD".
Corrected the parameter and value as follows.
Full transition voltage
Full-scale transition voltage
Min : - 20 → AVRH - 20
Max : + 20 → AVRH + 20
Revised the maximum value of "Power supply current
(analog + digital)":
A/D 1unit operation:
Typ: 0.47 → 0.57 / Max: 0.62 → 0.72
When A/D stops: Typ: 0.01 → 0.06
Revised the value of "Reference power supply current (between AVRH
to AVSS)"
109
When A/D stops: Typ: 0.01 → 0.06 / Max: 1.6 → 4
Deleted the following Pin name.
- "Sampling time"
- "Compare clock cycle"
- "State transition time to operation permission"
- "Analog input capacity"
- "Analog input resistance"
Corrected the value of "Compare clock cycle (Tcck)".
Max: 10000 → 2000
Document Number: 002-05602 Rev. *C
Page 122 of 125
MB9B510T Series
Page
116
Section
Change Results
7. Low-voltage Detection Characteristics
(2) Interrupt of Low-voltage Detection
8. Flash Memory Write/Erase Characteristics
Erase/write cycles and data hold time
Corrected the value of "LVD stabilization wait time (TLVDW)".
Max: 2240×tcyc → 4032×tCYCP
Deleted "(targeted value)".
117
Revision 1.1
-
-
Company name and layout design change
Revision 2.0
Features
External Bus Interface
Features
USB Interface
Features
USB Interface
Pin Assignment
2
2
Added the description of Maximum area size
Added the description of PLL for USB
Added the size of each EndPoint
2
9, 10
51 to 56
61
Added SWCLK and SWDIO and SWO
Added the description of I2C to the type of E, F, I, L
Added about +B input
Added "Stabilizing power supply voltage"
Added the following description
I/O Circuit Type
Handling Devices
Handling Devices
Crystal oscillator circuit
61
"Evaluate oscillation of your using crystal oscillator by your mount
board."
Handling Devices
C Pin
Block Diagram
Memory Map
Memory map(1)
Memory Map
Memory map(2)
62
64
66
Changed the description
Modified the block diagram
Modified the area of "External Device Area"
67
Added the summary of Flash memory sector and the note
Added the Clamp maximum current
Added the output current of P80, P81, P82, P83
Added about +B input
Electrical Characteristics
1. Absolute Maximum Ratings
74, 75
Modified the minimum value of Analog reference voltage
Added Smoothing capacitor
Added the note about less than the minimum power supply voltage
Changed the table format
Added Main TIMER mode current
Added Flash Memory Current
Electrical Characteristics
2. Recommended Operation Conditions
76
Electrical Characteristics
3. DC Characteristics
(1) Current rating
77, 78
Moved A/D Converter Current
Electrical Characteristics
4. AC Characteristics
82
Added Frequency stability time at Built-in high-speed CR
(3) Built-in CR Oscillation Characteristics
Electrical Characteristics
4. AC Characteristics
(6) Power-on Reset Timing
Electrical Characteristics
4. AC Characteristics
(7) External Bus Timing
Electrical Characteristics
4. AC Characteristics
Added Time until releasing Power-on reset
Changed the figure of timing
84
86 to 88
95 to 102
Modified Data output time
Modified from UART Timing to CSIO/UART Timing
Changed from Internal shift clock operation to Master mode
Changed from External shift clock operation to Slave mode
Added the typical value of Integral Nonlinearity, Differential Nonlinearity,
Zero transition voltage and Full-scale transition voltage
Added Conversion time at AVcc < 4.5 V
(9) CSIO/UART Timing
Electrical Characteristics
5. 12bit A/D Converter
109
Modified Stage transition time to operation permission
Modified the minimum value of Reference voltage
Electrical Characteristics
9. Return Time from Low-Power Consumption Mode
Ordering Information
118 to 121
Added Return Time from Low-Power Consumption Mode
Change to full part number
122
Note:
−
Please see “Document History” about later revised information.
Document Number: 002-05602 Rev. *C
Page 123 of 125
MB9B510T Series
Document History
Document Title: MB9B510T Series 32-bit ARM® Cortex®-M3 FM3 Microcontroller
Document Number: 002-05602
Orig. of
Change
Submission
Date
Revision
ECN
Description of Change
Migrated to Cypress and assigned document number 002-05602.
No change to document contents or format.
**
-
TOYO
TOYO
03/18/2015
*A
5206259
04/11/2016 Updated to Cypress format.
Updated “12.4.7 Power-On Reset Timing”. Changed parameter from “Power Supply
rising time(Tr)[ms]” to “Power ramp rate(dV/dt)[mV/us]” and added some comments
(Page 79)
Added Notes for JTAG (Page 47), Changed “J-TAG” to” JTAG” in “4 List of Pin
Functions” (Page 29)
Updated Package code and dimensions as follows (Page 8-11, 70, 118-121)
FPT-144P-M08 -> LQS144, FPT-176P-M07 -> LQP176,
BGA-192P-M06 -> LBE192
Change the name from “USB Function” to “USB Device” (Page 1, 7, 45)
Corrected the following statement
Analog port input current Analog port input leak current
in chapter 12.5. 12-bit A/D Converter (Page 105)
*B
5560212
YSKA
03/09/2017
Added the Baud rate spec in “12.4.10 CSIO/UART Timing”.(Page 91, 93, 95, 97)
Deleted MPNs below from “13. Ordering Information” (Page 118)
MB9BF516SPMC-GE1, MB9BF516TBGL-GE1, MB9BF516TPMC-GE1,
MB9BF517SPMC-GE1, MB9BF517TBGL-GE1, MB9BF517TPMC-GE1,
MB9BF518SPMC-GE1, MB9BF518TBGL-GE1, MB9BF518TPMC-GE1
Added MPNs below to “13. Ordering Information” (Page 118)
MB9BF516SPMC-GK7E1, MB9BF516TBGL-GK7E1, MB9BF516TPMC-GK7E1,
MB9BF517SPMC-GK7E1, MB9BF517TBGL-GK7E1, MB9BF517TPMC-GK7E1,
MB9BF518SPMC-GK7E1, MB9BF518TBGL-GK7E1, MB9BF518TPMC-GK7E1
*C
5797514
YSAT
07/11/2017 Adapted new Cypress logo
Document Number: 002-05602 Rev. *C
Page 124 of 125
MB9B510T Series
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the
office closest to you, visit us at Cypress Locations.
Products
PSoC® Solutions
ARM® Cortex® Microcontrollers
cypress.com/arm
cypress.com/automotive
cypress.com/clocks
cypress.com/interface
cypress.com/iot
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP | PSoC 6
Automotive
Cypress Developer Community
Clocks & Buffers
Interface
Forums | WICED IOT Forums | Projects | Video | Blogs |
Training | Components
Internet of Things
Memory
Technical Support
cypress.com/memory
cypress.com/mcu
cypress.com/support
Microcontrollers
PSoC
cypress.com/psoc
cypress.com/pmic
cypress.com/touch
cypress.com/usb
Power Management ICs
Touch Sensing
USB Controllers
Wireless/RF
cypress.com/wireless
ARM and Cortex are the registered trademarks of ARM Limited in the EU and other countries.
All other trademarks or registered trademarks referenced herein are the property of their respective owners.
© Cypress Semiconductor Corporation, 2011-2017. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC (“Cypress”). This document,
including any software or firmware included or referenced in this document (“Software”), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or
other intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software,
then Cypress hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source
code form, to modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form
externally to end users (either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress’s patents that are
infringed by the Software (as provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction,
modification, translation, or compilation of the Software is prohibited.
TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. To the extent
permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any
product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It
is the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress
products are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support
devices or systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the
failure of the device or system could cause personal injury, death, or property damage (“Unintended Uses”). A critical component is any component of a device or system whose failure to perform
can be reasonably expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress
from any claim, damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs,
damages, and other liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products.
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in
the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Document Number: 002-05602 Rev. *C
July 11, 2017
Page 125 of 125
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