CY9BF564LPMC1-G-JNE2 [INFINEON]
FM4 CY9BFx6xK/L-Series Motor Control Arm® Cortex®-M4 Microcontroller (MCU) Family;
| 型号： | CY9BF564LPMC1-G-JNE2 |
| 厂家： | 
Infineon |
| 描述： | FM4 CY9BFx6xK/L-Series Motor Control Arm® Cortex®-M4 Microcontroller (MCU) Family 微控制器 |
| 文件： | 总130页 (文件大小：1570K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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company that originally developed the product. Please note that Infineon will continue
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ordering part numbers listed in the datasheet for ordering.
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name, product name, and ordering part numbering with the prefix “MB”. However, Cypress will
offer these products to new and existing customers with the series name, product name, and
ordering part number with the prefix “CY”.
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About Cypress
Cypress is the leader in advanced embedded system solutions for the world's most innovative
automotive, industrial, smart home appliances, consumer electronics and medical products.
Cypress' microcontrollers, analog ICs, wireless and USB-based connectivity solutions and reliable,
high-performance memories help engineers design differentiated products and get them to market
first. Cypress is committed to providing customers with the best support and development
resources on the planet enabling them to disrupt markets by creating new product categories in
record time. To learn more, go to www.cypress.com.
MB9B560L Series
32-Bit Arm® Cortex®-M4F
FM4 Microcontroller
Devices in the MB9B560L Series are highly integrated 32-bit microcontrollers with high performance and competitive cost.
This series is based on the Arm® Cortex®-M4F Processor with on-chip Flash memory and SRAM. The series has peripheral
functions such as Motor Control Timers, ADCs and Communication Interfaces (USB, CAN, UART, CSIO, I2C, LIN).
The products that are described in this datasheet are placed into TYPE2-M4 product categories in the "FM4 Family Peripheral
Manual Main Part (002-04856)”.
Features
32-bit Arm® Cortex®-M4F Core
Processor version: r0p1
Up to 160 MHz Frequency Operation
FPU built-in
[SRAM]
This is composed of three independent SRAMs (SRAM0,
SRAM1, and SRAM2). SRAM0 is connected to I-code bus and
D-code bus of Cortex-M4F core. SRAM1 and SRAM2 are
connected to System bus of Cortex-M4F core.
SRAM0: Up to 32 Kbytes
SRAM1: Up to 16 Kbytes
SRAM2: Up to 16 Kbytes
Support DSP instruction
Memory Protection Unit (MPU): improves the reliability of an
embedded system
Integrated Nested Vectored Interrupt Controller (NVIC): 1
NMI (non-maskable interrupt) and 128 peripheral interrupts
and 16 priority levels
USB Interface
USB interface is composed of Device and Host.
USB device
24-bit System timer (Sys Tick): System timer for OS task
USB2.0 Full-Speed supported
Max 6 Endpoint supported
• Endpoint 0 is control transfer
management
On-Chip Memories
• Endpoint 1, 2 can be selected Bulk-transfer,
Interrupt-transfer or Isochronous-transfer
• Endpoint 3 to 5 can select Bulk-transfer or
Interrupt-transfer
[Flash Memory]
These series are based on two independent on-chip Flash
memories.
• Endpoint 1 to 5 comprise Double Buffer
The size of each endpoint is according to the follows.
• Endpoint 0, 2 to 5: 64 bytes
MainFlash memory
Up to 512 Kbytes
Built-in Flash Accelerator System with 16 Kbytes trace
buffer memory
• Endpoint 1: 256 bytes
The read access to Flash memory can be achieved without
wait-cycle up to operation frequency of 72 MHz. Even at
the operation frequency more than 72 MHz, an equivalent
access to Flash memory can be obtained by Flash
Accelerator System.
USB host
USB2.0 Full/Low-speed supported
Bulk-transfer, interrupt-transfer and Isochronous-transfer
support
USB Device connected/dis-connected automatically detect
IN/OUT token handshake packet automatically
Max 256-byte packet-length supported
Security function for code protection
WorkFlash memory
32 Kbytes
Read cycle:
Wake-up function supported
• 6wait-cycle: the operation frequency more than 120 MHz,
and up to 160 MHz
CAN Interface (1 Channel)
Compatible with CAN Specification 2.0A/B
Maximum transfer rate: 1 Mbps
Built-in 32 message buffer
• 4wait-cycle: the operation frequency more than 72 MHz,
and up to 120 MHz
• 2wait-cycle: the operation frequency more than 40 MHz,
and up to 72 MHz
• 0wait-cycle: the operation frequency up to 40 MHz
Security function is shared with code protection
Cypress Semiconductor Corporation
Document Number: 002-04922 Rev.*B
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised December 15, 2017
MB9B560L Series
Multi-Function Serial Interface (Max 6 Channels)
DSTC (Descriptor System data Transfer Controller)
(128 Channels)
64 bytes with FIFO (the FIFO step numbers are variable
depending on the settings of the communication mode or bit
length.)
The DSTC can transfer data at high-speed without going via
the CPU. The DSTC adopts the Descriptor system and,
following the specified contents of the Descriptor which has
already been constructed on the memory, can access directly
the memory /peripheral device and performs the data transfer
operation.
Operation mode is selectable from the followings for each
channel.
UART
CSIO
LIN
It supports the software activation, the hardware activation and
the chain activation functions.
I2C
UART
Full-duplex double buffer
Selection with or without parity supported
Built-in dedicated baud rate generator
External clock available as a serial clock
Hardware Flow control : Automatically control the
transmission by CTS/RTS (only ch.4)
Various error detect functions available (parity errors,
framing errors, and overrun errors)
A/D Converter (Max 15 Channels)
[12-bit A/D Converter]
Successive Approximation type
Built-in 2 units
Conversion time: 0.5 μs @ 5 V
Priority conversion available (priority at 2levels)
Scanning conversion mode
CSIO
Full-duplex double buffer
Built-in FIFO for conversion data storage (for SCAN
conversion: 16steps, for Priority conversion: 4steps)
Built-in dedicated baud rate generator
Overrun error detect function available
Serial chip select function (ch.6 only)
Supports high-speed SPI (ch.0 and ch.6 only)
Data length 5 to 16-bit
DA Converter (Max 2 Channels)
R-2R type
12-bit resolution
LIN
LIN protocol Rev.2.1 supported
Full-duplex double buffer
Master/Slave mode supported
LIN break field generation (can change to 13 to 16-bit
length)
Base Timer (Max 8 Channels)
Operation mode is selectable from the followings for each
channel.
16-bit PWM timer
16-bit PPG timer
LIN break delimiter generation (can change to 1 to 4-bit
length)
Various error detect functions available (parity errors,
16-/32-bit reload timer
16-/32-bit PWC timer
framing errors, and overrun errors)
I2C
Standard mode (Max 100 kbps) / Fast-mode (Max 400
kbps) supported
General Purpose I/O Port
Fast mode Plus (Fm+) (Max 1000 kbps, only for ch.3=ch.A
and ch.4=ch.B) supported
This series can use its pins as general purpose I/O ports when
they are not used for external bus or peripherals. Moreover, the
port relocate function is built in. It can set which I/O port the
peripheral function can be allocated.
DMA Controller (8 Channels)
DMA Controller has an independent bus for CPU, so CPU and
DMA Controller can process simultaneously.
Capable of pull-up control per pin
Capable of reading pin level directly
Built-in the port relocate function
8 independently configured and operated channels
Transfer can be started by software or request from the
built-in peripherals
Up to 48 high-speed general-purpose I/O ports @ 64 pin
Package
Transfer address area: 32-bit (4 Gbytes)
Some pin is 5 V tolerant I/O.
See 4. Pin Description and 5. I/O Circuit Type for the
corresponding pins.
Transfer mode: Block transfer/Burst transfer/Demand
transfer
Transfer data type: bytes/half-word/word
Transfer block count: 1 to 16
Number of transfers: 1 to 65536
Document Number: 002-04922 Rev.*B
Page 2 of 128
MB9B560L Series
Multi-Function Timer (Max 2 Units)
The Multi-function timer is composed of the following blocks.
Dual Timer (32-/16-bit Down Counter)
The Dual Timer consists of two programmable 32-/16-bit down
counters.
Minimum resolution: 6.25 ns
Operation mode is selectable from the followings for each
channel.
16-bit free-run timer × 3 ch./unit
Input capture × 4 ch./unit
Free-running
Periodic (=Reload)
One-shot
Output compare × 6 ch./unit
A/D activation compare × 6 ch./unit
Waveform generator × 3 ch./unit
16-bit PPG timer × 3 ch./unit
Watch Counter
The Watch counter is used for wake up from the low-power
consumption mode. It is possible to select the main clock, sub
clock, built-in high-speed CR clock or built-in low-speed CR
clock as the clock source.
The following function can be used to achieve the motor
control.
Interval timer: up to 64 s (Max) @ Sub Clock: 32.768 kHz
PWM signal output function
DC chopper waveform output function
Dead time function
External Interrupt Controller Unit
External interrupt input pin: Max 16 pins
Include one non-maskable interrupt (NMI)
Input capture function
A/D convertor activate function
DTIF (Motor emergency stop) interrupt function
Watchdog Timer (2 Channels)
A watchdog timer can generate interrupts or a reset when a
time-out value is reached.
Real-Time Clock (RTC)
This series consists of two different watchdogs, a "Hardware"
watchdog and a "Software" watchdog.
The Real-time clock can count
Year/Month/Day/Hour/Minute/Second/A day of the week from
00 to 99.
"Hardware" watchdog timer is clocked by low-speed internal
CR oscillator. Therefore, "Hardware" watchdog is active in any
power saving mode except STOP.
Interrupt function with specifying date and time
(Year/Month/Day/Hour/Minute) is available. This function is
also available by specifying only Year, Month, Day, Hour or
Minute.
CRC (Cyclic Redundancy Check) Accelerator
The CRC accelerator helps a verify data transmission or
storage integrity.
Timer interrupt function after set time or each set time.
Capable of rewriting the time with continuing the time count.
Leap year automatic count is available.
CCITT CRC16 and IEEE-802.3 CRC32 are supported.
CCITT CRC16 Generator Polynomial: 0x1021
IEEE-802.3 CRC32 Generator Polynomial: 0x04C11DB7
Quadrature Position/Revolution Counter (QPRC) (1
Channel)
The Quadrature Position/Revolution Counter (QPRC) is used
to measure the position of the position encoder. Moreover, it is
possible to use up/down counter.
The detection edge of the three external event input pins AIN,
BIN, and ZIN is configurable.
16-bit position counter
16-bit revolution counter
Two 16-bit compare registers
Document Number: 002-04922 Rev.*B
Page 3 of 128
MB9B560L Series
Clock and Reset
VBAT
The consumption power during the RTC operation can be
reduced by supplying the power supply independent from the
RTC (calendar circuit)/32 kHz oscillation circuit. The following
circuits can also be used.
[Clocks]
Five clock sources (2 external oscillators, 2 internal CR
oscillator, and Main PLL) that are dynamically selectable.
Main clock:
Sub Clock:
4 MHz to 48 MHz
32.768 kHz
RTC
32 kHz oscillation circuit
Power-on circuit
Back up register: 32 bytes
Port circuit
High-speed internal CR Clock: 4 MHz
Low-speed internal CR Clock: 100 kHz
Main PLL Clock
[Resets]
Debug
Reset requests from INITX pin
Power on reset
Serial Wire JTAG Debug Port (SWJ-DP)
Unique ID
Unique value of the device (41-bit) is set.
Software reset
Watchdog timers reset
Low voltage detector reset
Clock supervisor reset
Power Supply
Three Power Supplies (when 64 pin Package)
Two Power Supplies (when 48 pin Package)
Wide range voltage:
Clock Super Visor (CSV)
Clocks generated by internal CR oscillators are used to
VCC
= 2.7 V to 5.5 V
supervise abnormality of the external clocks.
Power supply for USB I/O:
USBVCC = 3.0 V to 3.6 V (when USB is used)
External OSC clock failure (clock stop) is detected, reset is
asserted.
= 2.7 V to 5.5 V (when GPIO is used)
External OSC frequency anomaly is detected, interrupt or
reset is asserted.
Power supply for VBAT (only 64 pin Package):
VBAT
= 2.7 V to 5.5 V
Low-Voltage Detector (LVD)
This Series include 2-stage monitoring of voltage on the VCC
pins. When the voltage falls below the voltage has been set,
Low-Voltage Detector generates an interrupt or reset.
LVD1: error reporting via interrupt
LVD2: auto-reset operation
Low-Power Consumption Mode
Six low-power consumption modes are supported.
SLEEP
TIMER
RTC
STOP
Deep standby RTC (selectable from with/without RAM
retention)
Deep standby stop (selectable from with/without RAM
retention)
Document Number: 002-04922 Rev.*B
Page 4 of 128
MB9B560L Series
Contents
Features................................................................................................................................................................................... 1
1. Product Lineup.................................................................................................................................................................. 7
2. Packages ........................................................................................................................................................................... 8
3. Pin Assignment................................................................................................................................................................. 9
4. Pin Description................................................................................................................................................................ 13
4.1
4.2
List of Pin Numbers ..................................................................................................................................................... 13
List of Pin Functions .................................................................................................................................................... 19
5. I/O Circuit Type ............................................................................................................................................................... 28
6. Handling Precautions ..................................................................................................................................................... 35
6.1
6.2
6.3
Precautions for Product Design................................................................................................................................... 35
Precautions for Package Mounting.............................................................................................................................. 36
Precautions for Use Environment................................................................................................................................ 37
7. Handling Devices ............................................................................................................................................................ 38
8. Block Diagram................................................................................................................................................................. 41
9. Memory Size.................................................................................................................................................................... 42
10. Memory Map.................................................................................................................................................................... 42
11. Pin Status in Each CPU State ........................................................................................................................................ 45
12. Electrical Characteristics ............................................................................................................................................... 52
12.1 Absolute Maximum Ratings......................................................................................................................................... 52
12.2 Recommended Operating Conditions ......................................................................................................................... 53
12.3 DC Characteristics ...................................................................................................................................................... 57
12.3.1 Current Rating.............................................................................................................................................................. 57
12.3.2 Pin Characteristics ....................................................................................................................................................... 64
12.4 AC Characteristics....................................................................................................................................................... 66
12.4.1 Main Clock Input Characteristics.................................................................................................................................. 66
12.4.2 Sub Clock Input Characteristics ................................................................................................................................... 67
12.4.3 Built-in CR Oscillation Characteristics.......................................................................................................................... 67
12.4.4 Operating Conditions of Main PLL (In the Case of Using Main Clock for Input Clock of PLL)...................................... 68
12.4.5 Operating Conditions of USB PLL (In the Case of Using Main Clock for Input Clock of PLL)...................................... 68
12.4.6 Operating Conditions of Main PLL (In the Case of Using Built-in High-Speed CR Clock for Input Clock of Main PLL) 68
12.4.7 Reset Input Characteristics.......................................................................................................................................... 69
12.4.8 Power-on Reset Timing................................................................................................................................................ 69
12.4.9 GPIO Output Characteristics........................................................................................................................................ 70
12.4.10 Base Timer Input Timing........................................................................................................................................... 71
12.4.11 CSIO/UART Timing .................................................................................................................................................. 72
12.4.12 External Input Timing................................................................................................................................................ 97
12.4.13 Quadrature Position/Revolution Counter Timing ...................................................................................................... 98
12.4.14 I2C Timing............................................................................................................................................................... 100
12.4.15 JTAG Timing........................................................................................................................................................... 102
12.5 12-bit A/D Converter.................................................................................................................................................. 103
12.6 12-bit D/A Converter.................................................................................................................................................. 106
12.7 USB Characteristics .................................................................................................................................................. 107
12.8 Low-Voltage Detection Characteristics...................................................................................................................... 111
12.8.1 Low-Voltage Detection Reset..................................................................................................................................... 111
12.8.2 Interrupt of Low-Voltage Detection............................................................................................................................. 111
12.9 MainFlash Memory Write/Erase Characteristics........................................................................................................ 112
12.10 WorkFlash Memory Write/Erase Characteristics....................................................................................................... 112
Document Number: 002-04922 Rev.*B
Page 5 of 128
MB9B560L Series
12.11 Standby Recovery Time ............................................................................................................................................ 113
12.11.1 Recovery Cause: Interrupt/WKUP.......................................................................................................................... 113
12.11.2 Recovery Cause: Reset.......................................................................................................................................... 115
13. Ordering Information .................................................................................................................................................... 117
14. Package Dimensions .................................................................................................................................................... 118
15. Major Changes .............................................................................................................................................................. 123
Document History............................................................................................................................................................... 125
Sales, Solutions, and Legal Information........................................................................................................................... 128
Document Number: 002-04922 Rev.*B
Page 6 of 128
MB9B560L Series
1. Product Lineup
Memory Size
Product Name
MainFlash memory
WorkFlash memory
On-chip SRAM
SRAM0
MB9BF564K/L
256 Kbytes
32 Kbytes
32 Kbytes
16 Kbytes
8 Kbytes
MB9BF565K/L
384 Kbytes
32 Kbytes
48 Kbytes
24 Kbytes
12 Kbytes
12 Kbytes
MB9BF566K/L
512 Kbytes
32 Kbytes
64 Kbytes
32 Kbytes
16 Kbytes
16 Kbytes
SRAM1
SRAM1
8 Kbytes
Function
Product Name
Pin count
MB9BF564K
MB9BF565K
MB9BF566K
MB9BF564L
MB9BF565L
MB9BF566L
48
64
Cortex-M4F, MPU, NVIC 128ch.
CPU
Freq.
160 MHz
2.7 V to 5.5 V
1ch.
Power supply voltage range
USB2.0 (Device/Host)
CAN
1ch.
DMAC
8ch.
DSTC
128ch.
6ch. (Max)
(In ch.1, only I2C is available.)
Multi-function Serial Interface
(UART/CSIO/LIN/I2C)
Base Timer
(PWC/Reload timer/PWM/PPG)
A/D activation compare
Input capture
6ch. (Max)
8ch. (Max)
6ch.
4ch.
3ch.
6ch.
3ch.
3ch.
Free-run timer
1 unit
2 units (Max)
Output compare
Waveform generator
PPG
QPRC
Dual Timer
1ch.
1 unit
1 unit
1 unit
Yes
Real-Time Clock
Watch Counter
CRC Accelerator
Watchdog Timer
External Interrupts
I/O Ports
1ch. (SW) + 1ch. (HW)
15 pins (Max) + NMI × 1
33 pins (Max)
16 pins (Max) + NMI × 1
48 pins (Max)
12-bit A/D Converter
12-bit D/A Converter
8ch. (2 units)
15ch. (2 units)
2 units (Max)
CSV (Clock Super Visor)
LVD (Low-Voltage Detector)
Yes
2ch.
High-speed
Built-in CR
4 MHz
100 kHz
SWJ-DP
Yes
Low-speed
Debug Function
Unique ID
Note:
−
All signals of the peripheral function in each product cannot be allocated by limiting the pins of package.
It is necessary to use the port relocate function of the I/O port according to your function use.
−
See “12. Electrical Characteristics 12.4. AC Characteristics 12.4.3. Internal CR Oscillation Characteristics” for accuracy of
built-in CR.
−
Document Number: 002-04922 Rev.*B
Page 7 of 128
MB9B560L Series
2. Packages
MB9BF564K
MB9BF565K
MB9BF566K
MB9BF564L
MB9BF565L
MB9BF566L
Product Name
Package
LQFP: LQG064 (0.65mm pitch)
LQFP: LQD064 (0.5mm pitch)
LQFP: LQA048 (0.5mm pitch)
QFN: VNC064 (0.5mm pitch)
QFN: VNA048 (0.5mm pitch)
-
-
-
-
-
: Supported
Note:
−
See 14. Package Dimensions for detailed information on each package.
Document Number: 002-04922 Rev.*B
Page 8 of 128
MB9B560L Series
3. Pin Assignment
LQD064/LQG064
(TOP VIEW)
VCC
P50/AIN0_0/INT00_0/TIOA0_0/CTS4_0
P51/BIN0_0/INT01_0/TIOB0_0/RTS4_0
1
2
3
4
5
6
7
8
9
48 P26/AN08/SIN1_0/INT09_1/IC12_0
47 P25/AN07/SOT1_0/INT08_1/IC11_0/CROUT_0
46 P24/AN06/SCK1_0/INT07_1/IC10_0
45 P23/AN05/SCK0_0/TIOB1_1/INT06_1/DTTI1X_0
44 P22/AN04/SOT0_0/TIOA1_1/INT05_1/FRCK1_0
43 P21/AN03/ADTG_3/SIN0_0/TIOB0_1/INT04_1/RTO15_0
42 AVRH
P52/IC00_0/ZIN0_0/INT02_0/TIOA1_0/SIN4_0
P53/IC01_0/INT03_0/TIOB1_0/SOT4_0
P54/IC02_0/INT04_0/TIOA2_0/SCK4_0
P55/IC03_0/INT05_0/TIOB2_0/SIN3_0
P56/FRCK0_0/INT06_0/TIOA3_0/SOT3_0
P57/DTTI0X_0/INT07_0/TIOB3_0/SCK3_0/ADTG_0
LQFP - 64
41 AVRL
40 AVSS
P30/RTO00_0/AIN0_1/INT08_0/TIOA4_0/SIN2_0 10
P31/RTO01_0/BIN0_1/INT09_0/TIOB4_0/SOT2_0 11
P32/RTO02_0/ZIN0_1/INT10_0/TIOA5_0/SCK2_0 12
P33/RTO03_0/INT11_0/TIOB5_0/SIN4_1 13
P34/RTO04_0/INT12_0/TIOA6_0/SOT4_1 14
P35/WKUP2/RTO05_0/INT13_0/TIOB6_0/SCK4_1 15
VSS 16
39 AVCC
38 P20/AN02/SIN6_0/TIOA0_1/INT03_1/RTO14_0/RTCCO_1/SUBOUT_1/WKUP1
37 P13/AN01/SOT6_0/TIOB7_1/RTO13_0/IC00_1/TX0_1
36 P12/AN00/SCK6_0/TIOA7_1/INT02_1/ZIN0_2/RTO12_0/IC01_1/RX0_1
35 P11/DA1/ADTG_2/SCS6_0/TIOB4_1/INT01_1/BIN0_2/RTO11_0/IC02_1
34 P10/DA0/TIOA4_1/INT00_1/AIN0_2/RTO10_0/IC03_1
33 VCC
Note:
−
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For
these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function
register (EPFR) to select the pin.
Document Number: 002-04922 Rev.*B
Page 9 of 128
MB9B560L Series
VNC064
(TOP VIEW)
VCC
P50/AIN0_0/INT00_0/TIOA0_0/CTS4_0
P51/BIN0_0/INT01_0/TIOB0_0/RTS4_0
P52/IC00_0/ZIN0_0/INT02_0/TIOA1_0/SIN4_0
P53/IC01_0/INT03_0/TIOB1_0/SOT4_0
P54/IC02_0/INT04_0/TIOA2_0/SCK4_0
P55/IC03_0/INT05_0/TIOB2_0/SIN3_0
1
2
3
4
5
6
7
8
9
48 P26/AN08/SIN1_0/INT09_1/IC12_0
47 P25/AN07/SOT1_0/INT08_1/IC11_0/CROUT_0
46 P24/AN06/SCK1_0/INT07_1/IC10_0
45 P23/AN05/SCK0_0/TIOB1_1/INT06_1/DTTI1X_0
44 P22/AN04/SOT0_0/TIOA1_1/INT05_1/FRCK1_0
43 P21/AN03/ADTG_3/SIN0_0/TIOB0_1/INT04_1/RTO15_0
42 AVRH
P56/FRCK0_0/INT06_0/TIOA3_0/SOT3_0
P57/DTTI0X_0/INT07_0/TIOB3_0/SCK3_0/ADTG_0
QFN - 64
41 AVRL
40 AVSS
P30/RTO00_0/AIN0_1/INT08_0/TIOA4_0/SIN2_0 10
P31/RTO01_0/BIN0_1/INT09_0/TIOB4_0/SOT2_0 11
P32/RTO02_0/ZIN0_1/INT10_0/TIOA5_0/SCK2_0 12
P33/RTO03_0/INT11_0/TIOB5_0/SIN4_1 13
P34/RTO04_0/INT12_0/TIOA6_0/SOT4_1 14
P35/WKUP2/RTO05_0/INT13_0/TIOB6_0/SCK4_1 15
VSS 16
39 AVCC
38 P20/AN02/SIN6_0/TIOA0_1/INT03_1/RTO14_0/RTCCO_1/SUBOUT_1/WKUP1
37 P13/AN01/SOT6_0/TIOB7_1/RTO13_0/IC00_1/TX0_1
36 P12/AN00/SCK6_0/TIOA7_1/INT02_1/ZIN0_2/RTO12_0/IC01_1/RX0_1
35 P11/DA1/ADTG_2/SCS6_0/TIOB4_1/INT01_1/BIN0_2/RTO11_0/IC02_1
34 P10/DA0/TIOA4_1/INT00_1/AIN0_2/RTO10_0/IC03_1
33 VCC
Note:
−
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For
these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function
register (EPFR) to select the pin.
Document Number: 002-04922 Rev.*B
Page 10 of 128
MB9B560L Series
LQA048
(TOP VIEW)
VCC
P54/IC02_0/INT04_0/TIOA2_0
1
2
3
4
5
6
7
8
9
36 P23/AN05/SCK0_0/TIOB1_1/INT06_1
35 P22/AN04/SOT0_0/TIOA1_1/INT05_1
34 P21/AN03/ADTG_3/SIN0_0/TIOB0_1/INT04_1
33 AVRH
P55/IC03_0/INT05_0/TIOB2_0/SIN3_0
P56/FRCK0_0/INT06_0/TIOA3_0/SOT3_0
P57/DTTI0X_0/INT07_0/TIOB3_0/SCK3_0/ADTG_0
P30/RTO00_0/AIN0_1/INT08_0/TIOA4_0/SIN2_0
P31/RTO01_0/BIN0_1/INT09_0/TIOB4_0/SOT2_0
P32/RTO02_0/ZIN0_1/INT10_0/TIOA5_0/SCK2_0
P33/RTO03_0/INT11_0/TIOB5_0/SIN4_1
32 AVRL
31 AVSS
LQFP - 48
30 AVCC
29 P20/AN02/SIN6_0/TIOA0_1/INT03_1/RTCCO_1/SUBOUT_1/WKUP1
28 P13/AN01/SOT6_0/TIOB7_1/IC00_1/TX0_1
27 P12/AN00/SCK6_0/TIOA7_1/INT02_1/ZIN0_2/IC01_1/RX0_1
26 P11/DA1/ADTG_2/SCS6_0/TIOB4_1/INT01_1/BIN0_2/IC02_1
25 P10/DA0/TIOA4_1/INIT00_1/AIN0_2/IC03_1
P34/RTO04_0/INT12_0/TIOA6_0/SOT4_1 10
P35/WKUP2/RTO05_0/INT13_0/TIOB6_0/SCK4_1 11
VSS 12
Note:
−
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these
pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register
(EPFR) to select the pin.
Document Number: 002-04922 Rev.*B
Page 11 of 128
MB9B560L Series
VNA048
(TOP VIEW)
VCC
P54/IC02_0/INT04_0/TIOA2_0
1
2
3
4
5
6
7
8
9
36 P23/AN05/SCK0_0/TIOB1_1/INT06_1
35 P22/AN04/SOT0_0/TIOA1_1/INT05_1
34 P21/AN03/ADTG_3/SIN0_0/TIOB0_1/INT04_1
33 AVRH
P55/IC03_0/INT05_0/TIOB2_0/SIN3_0
P56/FRCK0_0/INT06_0/TIOA3_0/SOT3_0
P57/DTTI0X_0/INT07_0/TIOB3_0/SCK3_0/ADTG_0
P30/RTO00_0/AIN0_1/INT08_0/TIOA4_0/SIN2_0
P31/RTO01_0/BIN0_1/INT09_0/TIOB4_0/SOT2_0
P32/RTO02_0/ZIN0_1/INT10_0/TIOA5_0/SCK2_0
P33/RTO03_0/INT11_0/TIOB5_0/SIN4_1
32 AVRL
31 AVSS
QFN - 48
30 AVCC
29 P20/AN02/SIN6_0/TIOA0_1/INT03_1/RTCCO_1/SUBOUT_1/WKUP1
28 P13/AN01/SOT6_0/TIOB7_1/IC00_1/TX0_1
27 P12/AN00/SCK6_0/TIOA7_1/INT02_1/ZIN0_2/IC01_1/RX0_1
26 P11/DA1/ADTG_2/SCS6_0/TIOB4_1/INT01_1/BIN0_2/IC02_1
25 P10/DA0/TIOA4_1/INIT00_1/AIN0_2/IC03_1
P34/RTO04_0/INT12_0/TIOA6_0/SOT4_1 10
P35/WKUP2/RTO05_0/INT13_0/TIOB6_0/SCK4_1 11
VSS 12
Note:
−
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For
these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function
register (EPFR) to select the pin.
Document Number: 002-04922 Rev.*B
Page 12 of 128
MB9B560L Series
4. Pin Description
4.1 List of Pin Numbers
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins,
there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to
select the pin.
Pin No
I/O Circuit
Type
Pin State
Type
Pin Name
LQFP64
QFN64
LQFP48
QFN48
1
1
VCC
P50
-
-
AIN0_0
INT00_0
TIOA0_0
CTS4_0
P51
2
-
E
K
BIN0_0
INT01_0
TIOB0_0
RTS4_0
P52
3
4
-
-
E
K
K
IC00_0
ZIN0_0
INT02_0
TIOA1_0
SIN4_0
P53
I
IC01_0
INT03_0
TIOB1_0
5
-
N
K
SOT4_0
(SDA4_0)
P54
IC02_0
INT04_0
2
-
6
7
8
N
K
K
K
TIOA2_0
SCK4_0
(SCL4_0)
P55
IC03_0
INT05_0
TIOB2_0
SIN3_0
P56
3
4
I
FRCK0_0
INT06_0
TIOA3_0
N
SOT3_0
(SDA3_0)
Document Number: 002-04922 Rev.*B
Page 13 of 128
MB9B560L Series
Pin No
I/O Circuit
Type
Pin State
Type
Pin Name
LQFP64
QFN64
LQFP48
QFN48
P57
DTTI0X_0
INT07_0
TIOB3_0
9
5
N
K
SCK3_0
(SCL3_0)
ADTG_0
P30
RTO00_0
AIN0_1
INT08_0
TIOA4_0
SIN2_0
P31
10
11
6
7
G
G
K
K
RTO01_0
BIN0_1
INT09_0
TIOB4_0
SOT2_0
(SDA2_0)
P32
RTO02_0
ZIN0_1
12
8
G
K
INT10_0
TIOA5_0
SCK2_0
(SCL2_0)
P33
RTO03_0
INT11_0
TIOB5_0
SIN4_1
P34
13
14
9
G
G
K
K
RTO04_0
INT12_0
TIOA6_0
10
SOT4_1
(SDA4_1)
P35
WKUP2
RTO05_0
INT13_0
TIOB6_0
15
11
G
Q
SCK4_1
(SCL4_1)
Document Number: 002-04922 Rev.*B
Page 14 of 128
MB9B560L Series
Pin No
I/O Circuit
Type
Pin State
Type
Pin Name
LQFP64
QFN64
LQFP48
QFN48
16
12
VSS
P46
X0A
P47
-
-
17
13
P
S
18
14
Q
T
X1A
VBAT
VCC
19
-
-
15
-
-
-
-
P48
VREGCTL
20
-
O
U
P49
VWAKEUP
INITX
21
-
O
U
22
23
24
25
16
17
18
19
B
-
C
-
C
VSS
VCC
-
-
-
-
P40
TIOA7_0
26
-
E
K
INT14_0
P41
TIOB7_0
INT15_0
ADTG_1
27
28
-
E
C
Q
E
WKUP3
PE0
20
MD1
29
30
21
22
MD0
PE2
X0
J
D
A
A
PE3
X1
31
23
A
B
32
33
24
-
VSS
VCC
-
-
-
-
P10
DA0
TIOA4_1
INT00_1
AIN0_2
IC03_1
RTO10_0
P11
25
-
34
35
R
R
J
J
DA1
ADTG_2
SCS6_0
TIOB4_1
INT01_1
BIN0_2
IC02_1
RTO11_0
26
-
Document Number: 002-04922 Rev.*B
Page 15 of 128
MB9B560L Series
Pin No
I/O Circuit
Type
Pin State
Type
Pin Name
LQFP64
QFN64
LQFP48
QFN48
P12
AN00
SCK6_0
TIOA7_1
INT02_1
ZIN0_2
IC01_1
27
36
M
M
RX0_1
-
28
-
RTO12_0
P13
AN01
SOT6_0
(SDA6_0)
TIOB7_1
IC00_1
TX0_1
37
M
L
RTO13_0
P20
AN02
SIN6_0
TIOA0_1
INT03_1
RTCCO_1
SUBOUT_1
WKUP1
RTO14_0
AVCC
29
38
F
O
-
39
40
41
42
30
31
32
33
-
-
-
-
-
-
-
-
AVSS
AVRL
AVRH
P21
AN03
ADTG_3
34
43
F
M
M
SIN0_0
TIOB0_1
INT04_1
RTO15_0
P22
AN04
SOT0_0
(SDA0_0)
TIOA1_1
INT05_1
FRCK1_0
P23
-
35
-
44
45
F
F
AN05
SCK0_0
(SCL0_0)
36
M
TIOB1_1
INT06_1
-
DTTI1X_0
Document Number: 002-04922 Rev.*B
Page 16 of 128
MB9B560L Series
Pin No
I/O Circuit
Type
Pin State
Type
Pin Name
LQFP64
QFN64
LQFP48
QFN48
P24
AN06
SCK1_0
(SCL1_0)
46
-
F
M
INT07_1
IC10_0
P25
AN07
SOT1_0
(SDA1_0)
INT08_1
IC11_0
CROUT_0
P26
47
48
-
-
F
F
M
M
AN08
SIN1_0
INT09_1
IC12_0
P04
49
50
37
38
TDO
E
E
G
G
SWO
P03
TMS
SWDIO
P02
TDI
P01
TCK
SWCLK
51
52
53
39
40
41
E
E
E
G
G
G
P00
TRSTX
P66
AN09
42
-
54
INT10_1
CROUT_1
IC13_0
P65
F
M
AN10
SCK0_1
(SCL0_1)
55
-
-
L
M
TIOA2_1
INT11_1
RTCCO_0
SUBOUT_0
P64
AN11
SOT0_1
(SDA0_1)
56
L
M
TIOB2_1
INT12_1
Document Number: 002-04922 Rev.*B
Page 17 of 128
MB9B560L Series
Pin No
I/O Circuit
Type
Pin State
Type
Pin Name
LQFP64
QFN64
LQFP48
QFN48
P63
AN12
SIN0_1
TX0_0
TIOA3_1
INT13_1
ADTG_4
P62
57
58
-
-
F
F
M
M
AN13
SIN1_1
RX0_0
TIOB3_1
INT14_1
P61
AN14
ADTG_5
SOT1_1
(SDA1_1)
INT15_1
UHCONX0
IC00_2
59
60
43
44
F
M
P60
SCK1_1
(SCK1_1)
NMIX
WKUP0
IC01_2
USBVCC
P80
I
F
61
62
45
46
-
-
H
R
UDM0
P81
63
64
47
48
H
-
R
-
UDP0
VSS
Document Number: 002-04922 Rev.*B
Page 18 of 128
MB9B560L Series
4.2 List of Pin Functions
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins,
there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to
select the pin.
Pin No
Pin
Function
Pin Name
Function Description
LQFP64
QFN64
9
LQFP48
QFN48
ADTG_0
ADTG_1
ADTG_2
ADTG_3
ADTG_4
ADTG_5
AN00
AN01
AN02
AN03
AN04
AN05
AN06
AN07
AN08
AN09
AN10
AN11
AN12
5
-
26
34
-
43
27
28
29
34
35
36
-
-
-
42
-
-
-
-
43
-
27
35
43
57
59
36
37
38
43
44
45
46
47
48
54
55
56
57
58
59
2
A/D converter external trigger input pin
ADC
A/D converter analog input pin.
ANxx describes ADC ch.xx.
AN13
AN14
TIOA0_0
TIOA0_1
TIOB0_0
TIOB0_1
TIOA1_0
TIOA1_1
TIOB1_0
TIOB1_1
TIOA2_0
TIOA2_1
TIOB2_0
TIOB2_1
TIOA3_0
TIOA3_1
TIOB3_0
TIOB3_1
TIOA4_0
TIOA4_1
TIOB4_0
TIOB4_1
TIOA5_0
TIOB5_0
Base timer ch.0 TIOA pin
Base timer ch.0 TIOB pin
Base timer ch.1 TIOA pin
Base timer ch.1 TIOB pin
Base timer ch.2 TIOA pin
Base timer ch.2 TIOB pin
Base timer ch.3 TIOA pin
Base timer ch.3 TIOB pin
Base timer ch.4 TIOA pin
Base timer ch.4 TIOB pin
38
3
43
4
44
5
45
6
55
7
56
8
57
9
58
10
34
11
35
12
13
29
-
34
-
35
-
36
2
-
3
-
4
-
5
-
6
25
7
26
8
Base Timer
0
Base Timer
1
Base Timer
2
Base Timer
3
Base Timer
4
Base timer ch.5 TIOA pin
Base timer ch.5 TIOB pin
Base Timer
5
9
Document Number: 002-04922 Rev.*B
Page 19 of 128
MB9B560L Series
Pin No
Pin
Function
Pin Name
Function Description
LQFP64
LQFP48
QFN64
14
15
26
36
27
37
57
37
58
36
52
50
49
52
51
49
50
53
2
QFN48
10
11
-
TIOA6_0
TIOB6_0
TIOA7_0
TIOA7_1
TIOB7_0
TIOB7_1
TX0_0
TX0_1
RX0_0
RX0_1
SWCLK
SWDIO
SWO
TCK
TDI
Base timer ch.6 TIOA pin
Base timer ch.6 TIOB pin
Base Timer
6
Base timer ch.7 TIOA pin
27
-
28
-
28
-
27
40
38
37
40
39
37
38
41
-
25
-
26
-
27
-
29
2
Base Timer
7
Base timer ch.7 TIOB pin
CAN interface ch.0 TX output pin
CAN interface ch.0 RX output pin
CAN 0
Serial wire debug interface clock input pin
Serial wire debug interface data input / output pin
Serial wire viewer output pin
JTAG test clock input pin
JTAG test data input pin
JTAG debug data output pin
JTAG test mode state input/output pin
JTAG test reset Input pin
Debugger
TDO
TMS
TRSTX
INT00_0
INT00_1
INT01_0
INT01_1
INT02_0
INT02_1
INT03_0
INT03_1
INT04_0
INT04_1
INT05_0
INT05_1
External interrupt request 00 input pin
External interrupt request 01 input pin
External interrupt request 02 input pin
External interrupt request 03 input pin
External interrupt request 04 input pin
External interrupt request 05 input pin
34
3
35
4
36
5
38
6
External
Interrupt
43
7
44
34
3
35
Document Number: 002-04922 Rev.*B
Page 20 of 128
MB9B560L Series
Pin No
Pin
Function
Pin Name
Function Description
LQFP64
LQFP48
QFN64
QFN48
INT06_0
INT06_1
INT07_0
INT07_1
INT08_0
INT08_1
INT09_0
INT09_1
INT10_0
INT10_1
INT11_0
INT11_1
INT12_0
INT12_1
INT13_0
INT13_1
INT14_0
INT14_1
INT15_0
INT15_1
NMIX
P00
P01
P02
P03
P04
P10
P11
P12
P13
P20
P21
P22
P23
P24
P25
P26
P30
8
45
9
4
36
5
-
6
-
7
-
8
42
9
-
10
-
11
-
-
-
-
43
44
41
40
39
38
37
25
26
27
28
29
34
35
36
-
-
-
6
7
8
9
10
11
External interrupt request 06 input pin
External interrupt request 07 input pin
External interrupt request 08 input pin
External interrupt request 09 input pin
External interrupt request 10 input pin
External interrupt request 11 input pin
External interrupt request 12 input pin
External interrupt request 13 input pin
External interrupt request 14 input pin
46
10
47
11
48
12
54
13
55
14
56
15
57
26
58
27
59
60
53
52
51
50
49
34
35
36
37
38
43
44
45
46
47
48
10
11
12
13
14
15
External
Interrupt
External interrupt request 15 input pin
Non-Maskable Interrupt input pin
General-purpose I/O port 0
General-purpose I/O port 1
GPIO
General-purpose I/O port 2
General-purpose I/O port 3
P31
P32
P33
P34
P35
Document Number: 002-04922 Rev.*B
Page 21 of 128
MB9B560L Series
Pin No
Pin
Function
Pin Name
Function Description
LQFP64
LQFP48
QFN64
26
27
17
18
20
21
2
QFN48
P40
P41
P46
P47
P48
P49
P50
P51
P52
P53
P54
P55
P56
P57
P60
P61
P62
P63
P64
P65
P66
P80
P81
PE0
PE2
PE3
-
-
13
14
-
-
-
-
-
-
2
3
4
General-purpose I/O port 4
3
4
5
6
7
8
9
60
59
58
57
56
55
54
62
63
28
30
31
General-purpose I/O port 5
GPIO
5
44
43
-
-
-
General-purpose I/O port 6
-
42
46
47
20
22
23
General-purpose I/O port 8
General-purpose I/O port E
Document Number: 002-04922 Rev.*B
Page 22 of 128
MB9B560L Series
Pin No
Pin
Function
Pin Name
Function Description
LQFP64
LQFP48
QFN48
QFN64
SIN0_0
SIN0_1
43
34
-
Multi-function serial interface ch.0 input pin
57
SOT0_0
(SDA0_0)
Multi-function serial interface ch.0 output pin.
This pin operates as SOT0 when it is used in a
UART/CSIO/LIN (operation modes 0 to 3) and as SDA0
when it is used in an I2C (operation mode 4).
44
35
-
Multi-
function
Serial
0
SOT0_1
(SDA0_1)
56
45
55
SCK0_0
(SCL0_0)
Multi-function serial interface ch.0 clock I/O pin.
This pin operates as SCK0 when it is used in a CSIO
(operation modes 2) and as SCL0 when it is used in an I2C
(operation mode 4).
36
-
SCK0_1
(SCL0_1)
SIN1_0
SIN1_1
48
58
-
-
Multi-function serial interface ch.1 input pin
SOT1_0
(SDA1_0)
Multi-function serial interface ch.1 output pin.
This pin operates as SOT1 when it is used in a
UART/CSIO/LIN (operation modes 0 to 3) and as SDA1
when it is used in an I2C (operation mode 4).
47
59
46
-
43
-
Multi-
function
Serial
1
SOT1_1
(SDA1_1)
SCK1_0
(SCL1_0)
Multi-function serial interface ch.1 clock I/O pin.
This pin operates as SCK1 when it is used in a CSIO
(operation modes 2) and as SCL1 when it is used in an I2C
(operation mode 4).
SCK1_1
(SCL1_1)
60
10
44
6
SIN2_0
Multi-function serial interface ch.2 input pin
Multi-function serial interface ch.2 output pin.
This pin operates as SOT2 when it is used in a
UART/CSIO/LIN (operation modes 0 to 3) and as SDA2
when it is used in an I2C (operation mode 4).
Multi-function serial interface ch.2 clock I/O pin.
This pin operates as SCK2 when it is used in a CSIO
(operation modes 2) and as SCL2 when it is used in an I2C
(operation mode 4).
SOT2_0
(SDA2_0)
Multi-
function
Serial
2
11
12
7
8
SCK2_0
(SCL2_0)
Document Number: 002-04922 Rev.*B
Page 23 of 128
MB9B560L Series
Pin No
Pin Function
Pin Name
Function Description
LQFP64
LQFP48
QFN48
3
QFN64
SIN3_0
Multi-function serial interface ch.3 input pin
Multi-function serial interface ch.3 output pin.
This pin operates as SOT3 when it is used in a
UART/CSIO/LIN (operation modes 0 to 3) and as SDA3
when it is used in an I2C (operation mode 4).
Multi-function serial interface ch.3 clock I/O pin.
This pin operates as SCK3 when it is used in a CSIO
(operation modes 2) and as SCL3 when it is used in an I2C
(operation mode 4).
7
SOT3_0
(SDA3_0)
Multi-
function
Serial
3
8
9
4
5
SCK3_0
(SCL3_0)
SIN4_0
SIN4_1
4
-
Multi-function serial interface ch.4 input pin
13
9
SOT4_0
(SDA4_0)
SOT4_1
(SDA4_1)
SCK4_0
(SCL4_0)
SCK4_1
(SCL4_1)
CTS4_0
RTS4_0
SIN6_0
Multi-function serial interface ch.4 output pin.
This pin operates as SOT4 when it is used in a
UART/CSIO/LIN (operation modes 0 to 3) and as SDA4
when it is used in an I2C (operation mode 4).
5
14
6
-
Multi-
function
Serial
4
10
-
Multi-function serial interface ch.4 clock I/O pin.
This pin operates as SCK4 when it is used in a CSIO
(operation modes 2) and as SCL4 when it is used in an I2C
(operation mode 4).
15
11
Multi-function serial interface ch.4 CTS input pin
Multi-function serial interface ch.4 RTS output pin
Multi-function serial interface ch.6 input pin
2
3
38
-
-
29
This pin operates as SOT6 when it is used in a
UART/CSIO/LIN (operation modes 0 to 3) and as SDA6
when it is used in an I2C (operation mode 4).
Multi-function serial interface ch.6 clock I/O pin.
This pin operates as SCK6 when it is used in a CSIO
(operation modes 2) and as SCL6 when it is used in an I2C
(operation mode 4).
SOT6_0
(SDA6_0)
37
28
Multi-
function
Serial
6
SCK6_0
(SCL6_0)
36
35
27
26
SCS6_0
Multi-function serial interface ch.6 serial chip select pin
Document Number: 002-04922 Rev.*B
Page 24 of 128
MB9B560L Series
Pin No
Pin Function
Pin Name
Function Description
LQFP64
LQFP48
QFN48
QFN64
Input signal controlling wave form generator outputs
RTO00 to RTO05 of Multi-function timer 0.
DTTI0X_0
9
5
FRCK0_0
IC00_0
IC00_1
IC00_2
IC01_0
IC01_1
IC01_2
IC02_0
IC02_1
IC03_0
IC03_1
16-bit free-run timer ch.0 external clock input pin
8
4
4
-
37
59
5
28
43
-
36
60
6
27
44
2
16-bit input capture ch.0 input pin of Multi-function timer 0.
ICxx describes channel number.
35
7
26
3
Multi-
function
Timer
0
34
25
Wave form generator output pin of Multi-function timer 0.
This pin operates as PPG00 when it is used in PPG0 output
modes.
Wave form generator output pin of Multi-function timer 0.
This pin operates as PPG00 when it is used in PPG0 output
modes.
Wave form generator output pin of Multi-function timer 0.
This pin operates as PPG02 when it is used in PPG0 output
modes.
Wave form generator output pin of Multi-function timer 0.
This pin operates as PPG02 when it is used in PPG0 output
modes.
Wave form generator output pin of Multi-function timer 0.
This pin operates as PPG04 when it is used in PPG0 output
modes.
Wave form generator output pin of Multi-function timer 0.
This pin operates as PPG04 when it is used in PPG0 output
modes.
RTO00_0
(PPG00_0)
10
11
12
13
14
15
6
7
RTO01_0
(PPG00_0)
RTO02_0
(PPG02_0)
8
RTO03_0
(PPG02_0)
9
RTO04_0
(PPG04_0)
10
11
RTO05_0
(PPG04_0)
Document Number: 002-04922 Rev.*B
Page 25 of 128
MB9B560L Series
Pin No
Pin Function
Pin Name
Function Description
LQFP64
LQFP48
QFN48
QFN64
Input signal controlling wave form generator outputs
RTO10 to RTO15 of Multi-function timer 1.
DTTI1X_0
FRCK1_0
45
-
16-bit free-run timer ch.1 external clock input pin
44
-
IC10_0
IC11_0
IC12_0
IC13_0
46
47
48
54
-
-
-
-
16-bit input capture ch.1 input pin of Multi-function timer 1.
ICxx describes channel number.
Wave form generator output pin of Multi-function timer 1.
This pin operates as PPG10 when it is used in PPG1 output
modes.
Wave form generator output pin of Multi-function timer 1.
This pin operates as PPG10 when it is used in PPG1 output
modes.
Wave form generator output pin of Multi-function timer 1.
This pin operates as PPG12 when it is used in PPG1 output
modes.
Wave form generator output pin of Multi-function timer 1.
This pin operates as PPG12 when it is used in PPG1 output
modes.
Wave form generator output pin of Multi-function timer 1.
This pin operates as PPG14 when it is used in PPG1 output
modes.
Wave form generator output pin of Multi-function timer 1.
This pin operates as PPG14 when it is used in PPG1 output
modes.
RTO10_0
(PPG10_0)
34
35
36
37
38
43
-
-
-
-
-
-
Multi-
function
Timer
1
RTO11_0
(PPG10_0)
RTO12_0
(PPG12_0)
RTO13_0
(PPG12_0)
RTO14_0
(PPG14_0)
RTO15_0
(PPG14_0)
AIN0_0
AIN0_1
AIN0_2
BIN0_0
BIN0_1
BIN0_2
ZIN0_0
ZIN0_1
ZIN0_2
2
-
6
25
-
7
26
-
QPRC ch.0 AIN input pin
QPRC ch.0 BIN input pin
QPRC ch.0 ZIN input pin
10
34
3
11
35
4
Quadrature
Position/
Revolution
Counter
0
12
36
8
36
Document Number: 002-04922 Rev.*B
Page 26 of 128
MB9B560L Series
Pin No
Pin Function
Pin Name
Function Description
LQFP64
LQFP48
QFN64
QFN48
RTCCO_0
RTCCO_1
SUBOUT_0
SUBOUT_1
UDM0
55
38
55
38
62
63
59
60
38
15
27
34
35
20
21
-
29
-
0.5 seconds pulse output pin of Real-time clock
Sub clock output pin
Real-time
clock
Sub clock output pin
29
46
47
43
44
29
11
-
USB device/host D – pin
USB device/host D + pin
USB
UDP0
UHCONX0
WKUP0
WKUP1
WKUP2
WKUP3
DA0
DA1
VREGCTL
VWAKEUP
USB external pull-up control pin
Deep standby mode return signal input pin 0
Deep standby mode return signal input pin 1
Deep standby mode return signal input pin 2
Deep standby mode return signal input pin 3
D/A converter ch.0 analog output pin
D/A converter ch.1 analog output pin
On-board regulator control pin
The return signal input pin from a hibernation state
External Reset Input pin.
A reset is valid when INITX="L".
Mode 1 pin.
Low-Power
Consumpti
on
Mode
25
26
-
DAC
VBAT
Reset
-
INITX
22
16
MD1
During serial programming to Flash memory, MD1="L" must
be input.
28
20
Mode
Mode 0 pin.
During normal operation, MD0="L" must be input. During
serial programming to Flash memory, MD0="H" must be
input.
MD0
29
21
1
1
-
15
19
-
VCC
USBVCC
VSS
Power supply Pin
Power
GND
25
33
61
16
24
32
64
30
31
17
18
47
54
39
42
3.3V Power supply port for USB I/O
GND Pin
45
12
18
24
48
22
23
13
14
-
X0
X1
X0A
Main clock (oscillation) input pin
Main clock (oscillation) I/O pin
Sub clock (oscillation) input pin
Sub clock (oscillation) I/O pin
Clock
X1A
CROUT_0
CROUT_1
AVCC
AVRH
Built-in high-speed CR-osc clock output port
42
30
33
A/D converter and D/A converter analog power supply pin
A/D converter analog reference voltage input pin
VBAT power supply pin.
Analog
Power
VBAT
Power
VBAT
Backup power supply (battery etc.) and system power
supply.
19
-
A/D converter and D/A converter
GND pin
A/D converter analog reference voltage input pin
Power supply stabilization capacity pin
AVSS
40
31
Analog
GND
AVRL
C
41
23
32
17
C pin
Note:
−
While this device contains a Test Access Port (TAP) based on the IEEE 1149.1-2001 JTAG standard, it is not fully compliant to
all requirements of that standard. This device may contain a 32-bit device ID that is the same as the 32-bit device ID in other
devices with different functionality. The TAP pins may also be configurable for purposes other than access to the TAP
controller.
Document Number: 002-04922 Rev.*B
Page 27 of 128
MB9B560L Series
5. I/O Circuit Type
Type
Circuit
Remarks
P-ch
P-ch
Digital output
Digital output
X1
N-ch
R
It is possible to select the main
oscillation / GPIO function
Pull-up resistor control
Digital input
When the main oscillation is
selected.
−
Oscillation feedback resistor
: Approximately 1 MΩ
Standby mode control
Clock input
−
With Standby mode control
A
When the GPIO is selected.
−
−
−
−
−
CMOS level output.
CMOS level hysteresis input
With pull-up resistor control
With standby mode control
Pull-up resistor
Standby mode control
Digital input
: Approximately 50 kΩ
IOH = -4 mA, IOL = 4 mA
Standby mode control
−
R
P-ch
P-ch
N-ch
Digital output
X0
Digital output
Pull-up resistor control
−
−
CMOS level hysteresis input
Pull-up resistor
Pull-up resistor
B
: Approximately 50 kΩ
Digital input
Document Number: 002-04922 Rev.*B
Page 28 of 128
MB9B560L Series
Type
Circuit
Remarks
Digital input
Digital output
−
−
Open drain output
C
N-ch
CMOS level hysteresis input
P-ch
P-ch
Digital output
−
−
−
−
−
CMOS level output
CMOS level hysteresis input
With pull-up resistor control
With standby mode control
Pull-up resistor
E
N-ch
Digital output
R
: Approximately 50 kΩ
IOH = -4 mA, IOL = 4 mA
−
Pull-up resistor control
Digital input
Standby mode control
P-ch
P-ch
Digital output
−
−
−
−
−
−
−
CMOS level output
CMOS level hysteresis input
With input control
Analog input
N-ch
Digital output
With pull-up resistor control
With standby mode control
Pull-up resistor
F
: Approximately 50 kΩ
IOH = -4 mA, IOL = 4 mA
When this pin is used as an I2C
pin, the digital output P-ch
transistor is always off
Pull-up resistor control
R
−
−
Digital input
Standby mode control
Analog input
Input control
Document Number: 002-04922 Rev.*B
Page 29 of 128
MB9B560L Series
Type
Circuit
Remarks
−
−
−
−
−
CMOS level output
P-ch
P-ch
Digital output
Digital output
CMOS level hysteresis input
With pull-up resistor control
With standby mode control
Pull-up resistor
G
: Approximately 50 kΩ
N-ch
−
−
IOH = -12 mA, IOL = 12 mA
When this pin is used as an I2C
pin, the digital output P-ch
transistor is always off
R
Pull-up resistor
control
Digital input
Standby mode
control
GPIO Digital output
GPIO Digital input/output direction
GPIO Digital input
GPIO Digital input circuit control
It is possible to select the USB
I/O / GPIO function.
UDP output
UDP/Pxx
USB Full-speed/Low-speed control
UDP input
When the USB I/O is selected.
−
Full-speed, Low-speed control
Differential
UDM/Pxx
Differential input
USB/GPIO select
H
When the GPIO is selected.
−
−
−
−
CMOS level output
UDM input
CMOS level hysteresis input
With standby mode control
IOH = -20.5 mA, IOL = 18.5 mA
UDM output
USB Digital input/output direction
GPIO Digital output
GPIO Digital input/output direction
GPIO Digital input
GPIO Digital input circuit control
Document Number: 002-04922 Rev.*B
Page 30 of 128
MB9B560L Series
Type
Circuit
Remarks
−
−
−
−
−
−
CMOS level output
CMOS level hysteresis input
With pull-up resistor control
5 V tolerant
P-ch
P-ch
Digital output
Digital output
With standby mode control
Pull-up resistor
: Approximately 50 kΩ
IOH = -4 mA, IOL = 4 mA
Available to control of PZR
registers.
I
N-ch
−
−
R
−
When this pin is used as an I2C
pin, the digital output P-ch
transistor is always off
Pull-up resistor
control
Digital input
Standby mode control
CMOS level hysteresis input
J
Mode input
−
−
−
−
−
CMOS level output
P-ch
P-ch
Digital output
Digital output
CMOS level hysteresis input
With pull-up resistor control
With standby mode control
Pull-up resistor
L
N-ch
: Approximately 50 kΩ
IOH = -8 mA, IOL = 8 mA
When this pin is used as an I2C
pin, the digital output P-ch
transistor is always off
−
−
Pull-up resistor
control
R
Digital input
Standby mode
control
Document Number: 002-04922 Rev.*B
Page 31 of 128
MB9B560L Series
Type
Circuit
Remarks
P-ch
P-ch
Digital output
Digital output
−
−
−
−
−
−
−
CMOS level output
CMOS level hysteresis input
With input control
Analog input
With pull-up resistor control
With standby mode control
Pull-up resistor
N-ch
M
: Approximately 50 kΩ
IOH = -8 mA, IOL = 8 mA
When this pin is used as an I2C
pin, the digital output P-ch
transistor is always off
−
−
Pull-up resistor
control
R
Digital input
Standby mode
control
Analog input
Input control
−
−
−
−
−
CMOS level output
Pull-up resistor
control
P-ch
CMOS level hysteresis input
With pull-up resistor control
With standby mode control
Pull-up resistor
P-ch
Digital output
: Approximately 50 kΩ
IOH = -4 mA, IOL = 4 mA
(GPIO)
−
−
−
N
N-ch
Digital output
N-ch
IOL = 20 mA
(Fast Mode Plus)
When this pin is used as an I2C
pin, the digital output P-ch
transistor is always off
Fast mode control
Digital input
R
Standby mode
control
Document Number: 002-04922 Rev.*B
Page 32 of 128
MB9B560L Series
Type
Circuit
Remarks
−
−
−
−
−
−
CMOS level output
Pull-up resistor
control
Digital output
P-ch
CMOS level hysteresis input
5 V tolerant
P-ch
N-ch
With pull-up resistor control
With standby mode control
Pull-up resistor
O
Digital output
: Approximately 50 kΩ
IOH = -4 mA, IOL = 4 mA
For I/O setting, refer to VBAT
Domain in the Peripheral
Manual
−
−
R
Digital input
Standby mode
control
P-ch
Pull-up resistor
control
−
−
−
−
−
CMOS level output
P-ch
N-ch
Digital output
X0A
CMOS level hysteresis input
With pull-up resistor control
With standby mode control
Pull-up resistor
Digital output
P
: Approximately 50 kΩ
IOH = -4 mA, IOL = 4 mA
For I/O setting, refer to VBAT
Domain in the Peripheral
Manual
−
−
R
Digital input
Standby mode
control
OSC
Document Number: 002-04922 Rev.*B
Page 33 of 128
MB9B560L Series
Type
Circuit
Remarks
It is possible to select the sub
oscillation / GPIO function
Pull-up resistor
control
P-ch
P-ch
N-ch
Digital output
X1A
When the sub oscillation is selected.
−
Oscillation feedback resistor
: Approximately 10 MΩ
−
With Standby mode control
Digital output
When the GPIO is selected.
−
−
−
−
−
CMOS level output.
Q
CMOS level hysteresis input
With pull-up resistor control
With standby mode control
Pull-up resistor
R
Digital input
: Approximately 50 kΩ
IOH = -4 mA, IOL = 4 mA
For I/O setting, refer to VBAT
Domain in the Peripheral
Manual
Standby mode
control
OSC
−
−
RX
Standby mode
control
Clock input
−
−
−
−
−
−
−
CMOS level output
CMOS level hysteresis input
With input control
P-ch
P-ch
Digital output
Digital output
Analog output
With pull-up resistor control
With standby mode control
Pull-up resistor
N-ch
R
: Approximately 50 kΩ
IOH = -12 mA, IOL = 12 mA
(4.5 V to 5.5 V)
−
−
Pull-up resistor
control
R
IOH = -8 mA, IOL = 8 mA
(2.7 V to 4.5 V)
Digital input
Standby mode
control
Analog output
Document Number: 002-04922 Rev.*B
Page 34 of 128
MB9B560L Series
6. Handling Precautions
Any semiconductor devices have inherently a certain rate of failure. The possibility of failure is greatly affected by the conditions in
which they are used (circuit conditions, environmental conditions, etc.). This page describes precautions that must be observed to
minimize the chance of failure and to obtain higher reliability from your Cypress semiconductor devices.
6.1 Precautions for Product Design
This section describes precautions when designing electronic equipment using semiconductor devices.
Absolute Maximum Ratings
Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of
certain established limits, called absolute maximum ratings. Do not exceed these ratings.
Recommended Operating Conditions
Recommended operating conditions are normal operating ranges for the semiconductor device. All the device's electrical
characteristics are warranted when operated within these ranges.
Always use semiconductor devices within the recommended operating conditions. Operation outside these ranges may adversely
affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users
considering application outside the listed conditions are advised to contact their sales representative beforehand.
Processing and Protection of Pins
These precautions must be followed when handling the pins which connect semiconductor devices to power supply and input/output
functions.
1. Preventing Over-Voltage and Over-Current Conditions
Exposure to voltage or current levels in excess of maximum ratings at any pin is likely to cause deterioration within the device,
and in extreme cases leads to permanent damage of the device. Try to prevent such overvoltage or over-current conditions at the
design stage.
2. Protection of Output Pins
Shorting of output pins to supply pins or other output pins, or connection to large capacitance can cause large current flows.
Such conditions if present for extended periods of time can damage the device.
Therefore, avoid this type of connection.
3. Handling of Unused Input Pins
Unconnected input pins with very high impedance levels can adversely affect stability of operation. Such pins should be
connected through an appropriate resistance to a power supply pin or ground pin.
Latch-Up
Semiconductor devices are constructed by the formation of P-type and N-type areas on a substrate. When subjected to abnormally
high voltages, internal parasitic PNPN junctions (called thyristor structures) may be formed, causing large current levels in excess of
several hundred mA to flow continuously at the power supply pin. This condition is called latch-up.
CAUTION: The occurrence of latch-up not only causes loss of reliability in the semiconductor device, but can cause injury or
damage from high heat, smoke or flame. To prevent this from happening, do the following:
1. Be sure that voltages applied to pins do not exceed the absolute maximum ratings. This should include attention to abnormal
noise, surge levels, etc.
2. Be sure that abnormal current flows do not occur during the power-on sequence.
Observance of Safety Regulations and Standards
Most countries in the world have established standards and regulations regarding safety, protection from electromagnetic
interference, etc. Customers are requested to observe applicable regulations and standards in the design of products.
Fail-Safe Design
Any semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage or loss from such
failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and
prevention of over-current levels and other abnormal operating conditions.
Document Number: 002-04922 Rev.*B
Page 35 of 128
MB9B560L Series
Precautions Related to Usage of Devices
Cypress semiconductor devices are intended for use in standard applications (computers, office automation and other office
equipment, industrial, communications, and measurement equipment, personal or household devices, etc.).
CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly
affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as
aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.)
are requested to consult with sales representatives before such use. The company will not be responsible for damages arising from
such use without prior approval.
6.2 Precautions for Package Mounting
Package mounting may be either lead insertion type or surface mount type. In either case, for heat resistance during soldering, you
should only mount under Cypress's recommended conditions. For detailed information about mount conditions, contact your sales
representative.
Lead Insertion Type
Mounting of lead insertion type packages onto printed circuit boards may be done by two methods: direct soldering on the board, or
mounting by using a socket.
Direct mounting onto boards normally involves processes for inserting leads into through-holes on the board and using the flow
soldering (wave soldering) method of applying liquid solder. In this case, the soldering process usually causes leads to be subjected
to thermal stress in excess of the absolute ratings for storage temperature. Mounting processes should conform to Cypress
recommended mounting conditions.
If socket mounting is used, differences in surface treatment of the socket contacts and IC lead surfaces can lead to contact
deterioration after long periods. For this reason it is recommended that the surface treatment of socket contacts and IC leads be
verified before mounting.
Surface Mount Type
Surface mount packaging has longer and thinner leads than lead-insertion packaging, and therefore leads are more easily deformed
or bent. The use of packages with higher pin counts and narrower pin pitch results in increased susceptibility to open connections
caused by deformed pins, or shorting due to solder bridges.
You must use appropriate mounting techniques. Cypress recommends the solder reflow method, and have established a ranking of
mounting conditions for each product. Users are advised to mount packages in accordance with Cypress ranking of recommended
conditions.
Lead-Free Packaging
CAUTION: When ball grid array (BGA) packages with Sn-Ag-Cu balls are mounted using Sn-Pb eutectic soldering, junction strength
may be reduced under some conditions of use.
Storage of Semiconductor Devices
Because plastic chip packages are formed from plastic resins, exposure to natural environmental conditions will cause absorption of
moisture. During mounting, the application of heat to a package that has absorbed moisture can cause surfaces to peel, reducing
moisture resistance and causing packages to crack. To prevent, do the following:
1. Avoid exposure to rapid temperature changes, which cause moisture to condense inside the product. Store products in
locations where temperature changes are slight.
2. Use dry boxes for product storage. Products should be stored below 70% relative humidity, and at temperatures between 5°C
and 30°C.
When you open Dry Package that recommends humidity 40% to 70% relative humidity.
3. When necessary, Cypress packages semiconductor devices in highly moisture-resistant aluminum laminate bags, with a silica
gel desiccant. Devices should be sealed in their aluminum laminate bags for storage.
4. Avoid storing packages where they are exposed to corrosive gases or high levels of dust.
Baking
Packages that have absorbed moisture may be de-moisturized by baking (heat drying). Follow the Cypress recommended
conditions for baking.
Condition: 125°C/24 h
Document Number: 002-04922 Rev.*B
Page 36 of 128
MB9B560L Series
Static Electricity
Because semiconductor devices are particularly susceptible to damage by static electricity, you must take the following precautions:
1. Maintain relative humidity in the working environment between 40% and 70%. Use of an apparatus for ion generation may be
needed to remove electricity.
2. Electrically ground all conveyors, solder vessels, soldering irons and peripheral equipment.
3. Eliminate static body electricity by the use of rings or bracelets connected to ground through high resistance (on the level of
1 MΩ).
Wearing of conductive clothing and shoes, use of conductive floor mats and other measures to minimize shock loads is
recommended.
4. Ground all fixtures and instruments, or protect with anti-static measures.
5. Avoid the use of Styrofoam or other highly static-prone materials for storage of completed board assemblies.
6.3 Precautions for Use Environment
Reliability of semiconductor devices depends on ambient temperature and other conditions as described above.
For reliable performance, do the following:
1. Humidity
Prolonged use in high humidity can lead to leakage in devices as well as printed circuit boards. If high humidity levels are
anticipated, consider anti-humidity processing.
2. Discharge of Static Electricity
When high-voltage charges exist close to semiconductor devices, discharges can cause abnormal operation. In such cases, use
anti-static measures or processing to prevent discharges.
3. Corrosive Gases, Dust, or Oil
Exposure to corrosive gases or contact with dust or oil may lead to chemical reactions that will adversely affect the device. If you
use devices in such conditions, consider ways to prevent such exposure or to protect the devices.
4. Radiation, Including Cosmic Radiation
Most devices are not designed for environments involving exposure to radiation or cosmic radiation. Users should provide
shielding as appropriate.
5. Smoke, Flame
CAUTION: Plastic molded devices are flammable, and therefore should not be used near combustible substances. If devices
begin to smoke or burn, there is danger of the release of toxic gases.
Customers considering the use of Cypress products in other special environmental conditions should consult with sales
representatives.
Document Number: 002-04922 Rev.*B
Page 37 of 128
MB9B560L Series
7. Handling Devices
Power Supply Pins
In products with multiple VCC and VSS pins, respective pins at the same potential are interconnected within the device in order to
prevent malfunctions such as latch-up. However, all of these pins should be connected externally to the power supply or ground
lines in order to reduce electromagnetic emission levels, to prevent abnormal operation of strobe signals caused by the rise in the
ground level, and to conform to the total output current rating.
Moreover, connect the current supply source with each POWER pins and GND pins of this device at low impedance. It is also
advisable that a ceramic capacitor of approximately 0.1 µF be connected as a bypass capacitor between VCC and VSS near this
device.
Power Supply Pins
A malfunction may occur when the power supply voltage fluctuates rapidly even though the fluctuation is within the guaranteed
operating range of the VCC power supply voltage. As a rule of voltage stabilization, suppress voltage fluctuation so that the
fluctuation in VCC ripple (peak-to-peak value) at the commercial frequency (50 Hz/60 Hz) does not exceed 10% of the standard
VCC value, and the transient fluctuation rate does not exceed 0.1 V/μs at a momentary fluctuation such as switching the power
supply.
Crystal Oscillator Circuit
Noise near the X0/X1 and X0A/X1A pins may cause the device to malfunction. Design the printed circuit board so that X0/X1,
X0A/X1A pins, the crystal oscillator (or ceramic oscillator), and the bypass capacitor to ground are located as close to the device as
possible.
It is strongly recommended that the PC board artwork be designed such that the X0/X1 and X0A/X1A pins are surrounded by
ground plane as this is expected to produce stable operation.
Evaluate oscillation of your using crystal oscillator by your mount board.
Sub Crystal Oscillator
This series sub oscillator circuit is low gain to keep the low current consumption.
The crystal oscillator to fill the following conditions is recommended for sub crystal oscillator to stabilize the oscillation.
• Surface mount type
Size:
Load capacitance: Approximately 6 pF to 7 pF
• Lead type
Load capacitance: Approximately 6 pF to 7 pF
More than 3.2 mm × 1.5 mm
Using an External Clock
When using an external clock as an input of the main clock, set X0/X1 to the external clock input, and input the clock to X0. X1 (PE3)
can be used as a general-purpose I/O port.
Similarly, when using an external clock as an input of the sub clock, set X0A/X1A to the external clock input, and input the clock to
X0A. X1A (P47) can be used as a general-purpose I/O port.
Example of Using an External Clock
Device
X0(X0A)
Set as External
clock input
Can be used as
general-purpose
I/O ports.
X1(PE3), X1A (P47)
Document Number: 002-04922 Rev.*B
Page 38 of 128
MB9B560L Series
Handling when Using Multi-Function Serial Pin as I2C Pin
If it is using the multi-function serial pin as I2C pins, P-ch transistor of digital output is always disabled.
However, I2C pins need to keep the electrical characteristic like other pins and not to connect to the external I2C bus system with
power OFF.
C Pin
This series contains the regulator. Be sure to connect a smoothing capacitor (CS) for the regulator between the C pin and the GND
pin. Please use a ceramic capacitor or a capacitor of equivalent frequency characteristics as a smoothing capacitor.
However, some laminated ceramic capacitors have the characteristics of capacitance variation due to thermal fluctuation (F
characteristics and Y5V characteristics). Please select the capacitor that meets the specifications in the operating conditions to use
by evaluating the temperature characteristics of a capacitor.
A smoothing capacitor of about 4.7 μF would be recommended for this series.
C
Device
CS
VSS
GND
Mode Pins (MD0)
Connect the MD pin (MD0) directly to VCC or VSS pins. Design the printed circuit board such that the pull-up/down resistance stays
low, as well as the distance between the mode pins and VCC pins or VSS pins is as short as possible and the connection
impedance is low, when the pins are pulled-up/down such as for switching the pin level and rewriting the Flash memory data. It is
because of preventing the device erroneously switching to test mode due to noise.
Notes on Power-on
Turn power on/off in the following order or at the same time. The device operates normally after all power on.
In the case of 64pin package, VBAT only Power-on is possible when turns all power on and Hibernation control is setting and then
except for VBAT turns power off. About Hibernation control, see Chapter 7-2: VBAT Domain (A) in FM4 Family Peripheral Manual
(002-04856).
If not using the A/D converter and D/A converter, connect AVCC = VCC and AVSS = VSS.
Turning on:
VBAT → VCC → USBVCC
VCC → AVCC → AVRH
AVRH → AVCC → VCC
USBVCC → VCC → VBAT
Turning off:
Serial Communication
There is a possibility to receive wrong data due to the noise or other causes on the serial communication.
Therefore, design a printed circuit board so as to avoid noise.
Consider the case of receiving wrong data due to noise, perform error detection such as by applying a checksum of data at the end.
If an error is detected, retransmit the data.
Differences in Features among the Products with Different Memory Sizes and between Flash Products and
MASK Products
The electric characteristics including power consumption, ESD, latch-up, noise characteristics, and oscillation characteristics among
the products with different memory sizes and between Flash products and MASK products are different because chip layout and
memory structures are different.
If you are switching to use a different product of the same series, please make sure to evaluate the electric characteristics.
Pull-Up Function of 5 V Tolerant I/O
Please do not input the signal more than VCC voltage at the time of pull-up function use of 5V tolerant I/O.
Document Number: 002-04922 Rev.*B
Page 39 of 128
MB9B560L Series
Handling when Using Debug Pins
When debug pins (TDO/TMS/TDI/TCK/TRSTX or SWO/SWDIO/SWCLK) are set to GPIO or other peripheral functions, only set
them as output, do not set them as input.
Document Number: 002-04922 Rev.*B
Page 40 of 128
MB9B560L Series
8. Block Diagram
MB9BF564K/L, F565K/L, F566K/L
TRSTX,TCK,
TDI,TMS
TDO
SRAM0
16/24/32 Kbytes
SWJ-DP
ROM
Table
SRAM1
8/12/16 Kbytes
I
D
)
SRAM2
8/12/16 Kbytes
FPU MPU NVIC
Sys
M
H
MainFlash I/F
MainFlash
512 Kbytes/
384 Kbytes/
256 Kbytes
z
Trace Buffer
(16 Kbytes)
1
Dual-Timer
6
0
)
:
Security
M
(
Watchdog Timer
(Software)
M
H
a
x
WorkFlash
32 Kbytes
8
z
0
WorkFlash I/F
Clock Reset
Generator
A M
-
(
P
a
0
INITX
USBVCC
B
x
l
USB2.0
PHY
a
-
B
A
y
Watchdog Timer
(Hardware)
UDP0,UDM0
(Host/
A
P
B
r
e
H
i
d
r
B
g
Device)
UHCONX0
A M
e
H
u
B l
CSV
t
i
DMAC
8ch.
CLK
DSTC
Source Clock
Main
Osc
X0
X1
CR
100 kHz
CR
PLL
TX0,
RX0
CAN
VBAT Domain
4 MHz
A
-
X0A
X1A
Sub
Osc
H
B
P0x,
P1x,
GPIO
B
A
r
H
i
d
B
g
CROUT
.
.
.
PIN-Function-
Ctrl
e
PEx
AVCC,
AVSS,
AVRH
12-bit A/D Converter
Unit 0
CAN Prescaler
USB Clock Ctrl
ANxx
PLL
Unit 1
Power-On
Reset
ADTGx
LVD
LVD Ctrl
TIOAx
TIOBx
Base Timer
16-bit 16ch./
32-bit 8ch.
Regulator
C
IRQ-Monitor
CRC Accelerator
Watch Counter
)
)
AINx
BINx
ZINx
M
H
QPRC
1ch.
M
H
z
8
z
1
0
WKUPx
Deep Standby Ctrl
6
0
M
(
M
(
a
Peripheral Clock Gating
Low-speed CR Prescaler
a
2
x
1
x
A/D Activation Compare
6ch.
A
A
:
P
:
P
VWAKEUP
VBAT Domain
Real-Time Clock
Port Ctrl.
B
B
VREGCTL
RTCCO,
SUBOUT
16-bit Input Capture
4ch.
ICxx
16-bit Free-run Timer
3ch.
A
-
External Interrupt
Controller
16pin + NMI
FRCKx
A
-
P
INTxx
NMIX
P
B
B
16-bit Output Compare
6ch.
B
A
B
A
r
H
r
i
d
B
g
H
i
d
B
g
MD0,
MD1
DTTIxX
RTOxx
e
MODE-Ctrl
e
Waveform Generator
3ch.
SCKx
SINx
Multi-function Serial I/F
6ch.
HW flow control(ch.4)
SOTx
CTS4
RTS4
16-bit PPG
3ch.
12-bit D/A Converter
2units
DAx
Multi-function Timer × 2
Document Number: 002-04922 Rev.*B
Page 41 of 128
MB9B560L Series
9. Memory Size
See Memory size in 1. Product Lineup to confirm the memory size.
10.Memory Map
Memory Map (1)
Peripherals Area
Reserved
0x41FF_FFFF
0x4007_0000
0x4006_F000
GPIO
Reserved
0xFFFF_FFFF
Reserved
0xE010_0000
Cortex-M4F Private
0x4006_3000
0x4006_2000
0x4006_1000
0x4006_0000
CAN ch.0
DSTC
DMAC
Peripherals
0xE000_0000
Reserved
USB ch.0
0x4005_0000
0x4004_0000
Reserved
External Device
Area
0x4003_C800
0x4003_C100
0x4003_C000
0x4003_B000
0x4003_A000
0x4003_9000
0x4003_8000
0x4003_7000
0x4003_6000
0x4003_5000
0x4003_4000
0x4003_3000
0x4003_2000
0x4003_1000
0x4003_0000
0x4002_F000
0x4002_E000
Peripheral Clock Gating
Low Speed CR Prescaler
RTC/Port Ctrl
Watch Counter
CRC
0x6000_0000
Reserved
0x4400_0000
0x4200_0000
MFS
32 Mbytes
Bit band alias
CAN prescaler
USB Clock ctrl
LVD/DS mode
Reserved
Peripherals
Reserved
0x4000_0000
D/AC
Reserved
Int-Req.Read
EXTI
Reserved
0x2400_0000
0x2200_0000
32 Mbytes
Bit band alias
CR Trim
Reserved
Reserved
0x4002_8000
0x4002_7000
0x4002_6000
0x4002_5000
0x4002_4000
0x2010_0000
0x200E_0000
0x200C_0000
A/DC
QPRC
Base Timer
PPG
WorkFlash I/F
WorkFlash
Reserved
0x2004_4000
0x2004_0000
0x2003_C000
0x2000_0000
0x1FFF_8000
0x0050_0000
0x0040_0000
Reserved
SRAM2
SRAM1
Reserved
SRAM0
Reserved
0x4002_2000
0x4002_1000
0x4002_0000
MFT Unit1
MFT Unit0
See "Memory Map (2)"
for the memory size
details.
Reserved
0x4001_6000
0x4001_5000
Security/CR Trim
Dual Timer
Reserved
0x4001_3000
MainFlash
0x4001_2000
0x4001_1000
SW WDT
HW WDT
0x0000_0000
0x4001_0000
Clock/Reset
Reserved
0x4000_1000
0x4000_0000
MainFlash I/F
Document Number: 002-04922 Rev.*B
Page 42 of 128
MB9B560L Series
Memory Map (2)
MB9BF566K/L
MB9BF565K/L
MB9BF564K/L
0x2008_0000
0x200C_8000
0x200C_0000
0x2008_0000
0x200C_8000
0x200C_0000
0x2008_0000
Reserved
Reserved
Reserved
0x200C_8000
0x200C_0000
WorkFlash
32 Kbytes
WorkFlash
32 Kbytes
WorkFlash
32 Kbytes
Reserved
Reserved
0x2004_4000
0x2004_0000
Reserved
0x2004_3000
0x2004_0000
0x2003_D000
SRAM2
16 Kbytes
0x2004_2000
0x2004_0000
0x2003_E000
SRAM2
12 Kbytes
SRAM2
8 Kbytes
SRAM1
8 Kbytes
SRAM1
12 Kbytes
SRAM1
16 Kbytes
0x2003_C000
0x2000_0000
Reserved
Reserved
Reserved
0x2000_0000
0x1FFF_A000
0x2000_0000
0x1FFF_C000
SRAM0
16 Kbytes
SRAM0
24 Kbytes
SRAM0
32 Kbytes
0x1FFF_8000
Reserved
Reserved
Reserved
0x0050_0000
0x0040_2000
0x0040_0000
0x0050_0000
0x0040_2000
0x0040_0000
0x0050_0000
0x0040_2000
0x0040_0000
CR trimming
Security
CR trimming
Security
CR trimming
Security
Reserved
0x0008_0000
Reserved
Reserved
0x0006_0000
MainFlash
512 Kbytes
0x0004_0000
0x0000_0000
MainFlash
384 Kbytes
MainFlash
256 Kbytes
0x0000_0000
0x0000_0000
Document Number: 002-04922 Rev.*B
Page 43 of 128
MB9B560L Series
Peripheral Address Map
Start Address
End Address
Bus
Peripherals
0x4000_0000
0x4000_1000
0x4001_0000
0x4001_1000
0x4001_2000
0x4001_3000
0x4001_5000
0x4001_6000
0x4002_0000
0x4002_1000
0x4002_2000
0x4002_4000
0x4002_5000
0x4002_6000
0x4002_7000
0x4002_8000
0x4002_E000
0x4002_F000
0x4003_0000
0x4003_1000
0x4003_2000
0x4003_3000
0x4003_4000
0x4003_5000
0x4003_5800
0x4003_6000
0x4003_7000
0x4003_8000
0x4003_9000
0x4003_A000
0x4003_B000
0x4003_C000
0x4003_C100
0x4003_C800
0x4004_0000
0x4005_0000
0x4006_0000
0x4006_1000
0x4006_2000
0x4006_3000
0x4006_F000
0x4006_7000
0x200E_0000
0x4000_0FFF
0x4000_FFFF
0x4001_0FFF
0x4001_1FFF
0x4001_2FFF
0x4001_4FFF
0x4001_5FFF
0x4001_FFFF
0x4002_0FFF
0x4002_1FFF
0x4003_FFFF
0x4002_4FFF
0x4002_5FFF
0x4002_6FFF
0x4002_7FFF
0x4002_DFFF
0x4002_EFFF
0x4002_FFFF
0x4003_0FFF
0x4003_1FFF
0x4003_4FFF
0x4003_3FFF
0x4003_4FFF
0x4003_57FF
0x4003_5FFF
0x4003_6FFF
0x4003_7FFF
0x4003_8FFF
0x4003_9FFF
0x4003_AFFF
0x4003_BFFF
0x4003_C0FF
0x4003_C7FF
0x4003_FFFF
0x4004_FFFF
0x4005_FFFF
0x4006_0FFF
0x4006_1FFF
0x4006_2FFF
0x4006_EFFF
0x4006_FFFF
0x41FF_FFFF
0x200E_FFFF
MainFlash I/F register
Reserved
AHB
Clock/Reset Control
Hardware Watchdog timer
Software Watchdog timer
Reserved
APB0
Dual-Timer
Reserved
Multi-function timer unit0
Multi-function timer unit1
Reserved
PPG
Base Timer
APB1
Quadrature Position/Revolution Counter
A/D Converter
Reserved
Internal CR trimming
Reserved
External Interrupt Controller
Interrupt Request Batch-Read Function
Reserved
D/A Converter
Reserved
Low Voltage Detector
Deep standby mode Controller
USB clock generator
CAN prescaler
APB2
Multi-function serial Interface
CRC
Watch Counter
RTC/Port Ctrl
Low-speed CR Prescaler
Peripheral Clock Gating
Reserved
USB ch.0
Reserved
DMAC register
DSTC register
AHB
CAN ch.0
Reserved
GPIO
Reserved
WorkFlash I/F register
Document Number: 002-04922 Rev.*B
Page 44 of 128
MB9B560L Series
11.Pin Status in Each CPU State
The terms used for pin status have the following meanings.
INITX=0
This is the period when the INITX pin is the L level.
INITX=1
This is the period when the INITX pin is the H level.
SPL=0
This is the status that the standby pin level setting bit (SPL) in the standby mode control register (STB_CTL) is set to 0.
SPL=1
This is the status that the standby pin level setting bit (SPL) in the standby mode control register (STB_CTL) is set to 1.
Input enabled
Indicates that the input function can be used.
Internal input fixed at 0
This is the status that the input function cannot be used. Internal input is fixed at L.
Hi-Z
Indicates that the pin drive transistor is disabled and the pin is put in the Hi-Z state.
Setting disabled
Indicates that the setting is disabled.
Maintain previous state
Maintains the state that was immediately prior to entering the current mode.
If a built-in peripheral function is operating, the output follows the peripheral function.
If the pin is being used as a port, that output is maintained.
Analog input is enabled
Indicates that the analog input is enabled.
Trace output
Indicates that the trace function can be used.
GPIO selected
In Deep standby mode, pins switch to the general-purpose I/O port.
Setting prohibition
Prohibition of a setting by specification limitation.
Document Number: 002-04922 Rev.*B
Page 45 of 128
MB9B560L Series
List of Pin Status
Power-on
Run
Mode
or Sleep
Mode
Device
Internal
Reset
Return from
Deep
Standby
Reset or
Low-Voltage
Detection
State
INITX
Input
State
Timer Mode,
RTC Mode, or
Stop Mode State
Deep Standby RTC
Mode or Deep Standby
Stop Mode State
State
Mode State
State
Function
Group
Power
Supply
Unstable
‐
Power
Supply
Stable
INITX=1
‐
Power
Supply
Stable
Power Supply
Stable
Power Supply
Stable
Power Supply
Stable
INITX=0
‐
INITX=1
‐
INITX=1
INITX=1
INITX=1
‐
SPL=0
SPL=1
SPL=0
SPL=1
-
GPIO
Hi-Z /
Hi-Z /
Maintain
previous
state
Maintain
previous
state
selected
Internal
input fixed
at 0
GPIO
selected
Setting
disabled
Setting
disabled
Setting
disabled
Internal
input fixed
at 0
Internal
input fixed
at 0
GPIO
selected
Main
A
crystal
oscillator
input pin/
External
main clock
input
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
selected
GPIO
Hi-Z /
Hi-Z /
Maintain
previous
state
Maintain
previous
state
selected
Internal
input fixed
at 0
GPIO
selected
Setting
disabled
Setting
disabled
Setting
disabled
Internal
input fixed
at 0
Internal
input fixed
at 0
GPIO
selected
External
main clock Setting
input
selected
Hi-Z /
Hi-Z /
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Setting
disabled
Setting
disabled
Internal
input fixed
at 0
Internal
input fixed
at 0
disabled
B
Hi-Z /
Main
crystal
oscillator
output pin
Hi-Z /
Hi-Z /
Internal input
fixed at "0"/
or Input
Maintain previous state /
When oscillation stops*1, Hi-Z /
Internal input fixed at 0
Internal
input fixed
at 0
Internal
input fixed
at 0
enabled
Pull-up /
Input
enabled
Pull-up /
Input
enabled
Pull-up /
Input
enabled
Pull-up /
Input
enabled
Pull-up /
Input
enabled
Pull-up /
Input
enabled
Pull-up /
Input
enabled
Pull-up /
Input
enabled
Pull-up /
Input
enabled
INITX
input pin
C
D
Mode
input pin
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Document Number: 002-04922 Rev.*B
Page 46 of 128
MB9B560L Series
Return
from
Deep
Standby
Mode
State
Power-on
Reset or
Low-Voltage
Detection
State
Device
Internal
Reset
Run Mode
or SLEEP
Mode
INITX
Input
State
TIMER Mode,
RTC Mode, or
STOP Mode State
Deep Standby RTC
Mode or Deep Standby
STOP Mode State
State
State
Function
Group
Power
Supply
Unstable
‐
Power
Supply
Stable
INITX=1
‐
Power
Supply
Stable
INITX=1
Power Supply
Stable
Power Supply
Stable
Power Supply
Stable
INITX=0
‐
INITX=1
‐
INITX=1
INITX=1
‐
SPL=0
SPL=1
Input
SPL=0
Input
SPL=1
Input
-
Mode
Input
Input
Input
Input
Input
Input
input pin
enabled
enabled
enabled
enabled
Maintain
previous
state
enabled
Maintain
previous
state
enabled
Hi-Z /
Input
enabled
enabled
Hi-Z /
Input
enabled
E
GPIO
selected
Setting
disabled
Setting
disabled
Setting
disabled
GPIO
selected
GPIO
selected
enabled
enabled
Maintain
previous
state
NMIX
selected
Setting
disabled
Setting
disabled
Setting
disabled
GPIO
selected
Hi-Z /
WKUP
input
Resource
other than
above
Maintain
previous
state
Maintain
previous
state
WKUP
input
enabled
F
Hi-Z /
Hi-Z /
Input
enabled
Hi-Z /
Input
enabled
Internal
input fixed
at 0
enabled
selected
Hi-Z
Hi-Z
Maintain
previous
state
GPIO
selected
Pull-up /
Input
enabled
Pull-up /
Input
enabled
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
JTAG
selected
Maintain
previous
state
Maintain
previous
state
G
GPIO
Hi-Z /
Hi-Z /
selected
Internal
input fixed
at 0
GPIO
selected
Setting
disabled
Setting
disabled
Setting
disabled
Internal
input fixed
at 0
Internal
input fixed
at 0
GPIO
selected
Analog
output
selected
Setting
disabled
Setting
disabled
Setting
disabled
*2
*3
GPIO
Hi-Z /
Resource
other than
above
Maintain
previous
state
selected
Internal
input fixed
at 0
Internal
input fixed
at 0
GPIO
selected
J
Hi-Z /
Hi-Z /
Input
enabled
Hi-Z /
Input
enabled
Maintain
previous
state
Internal
input fixed
at 0
Hi-Z
selected
GPIO
selected
External
interrupt
enabled
selected
Resource
other than
above
Maintain
previous
state
Setting
disabled
Setting
disabled
Setting
disabled
GPIO
Hi-Z /
Maintain
previous
state
Maintain
previous
state
selected
Internal
input fixed
at 0
Internal
input fixed
at 0
GPIO
selected
K
Hi-Z /
Hi-Z /
Input
enabled
Hi-Z /
Input
enabled
Internal
input fixed
at 0
Hi-Z
selected
GPIO
selected
Document Number: 002-04922 Rev.*B
Page 47 of 128
MB9B560L Series
Return
from
Deep
Standby
Mode
State
Power-on
Reset or
Low-Voltage
Detection
State
Device
Internal
Reset
Run Mode
or Sleep
Mode
INITX
Input
State
Timer Mode,
RTC Mode, or
Stop Mode State
Deep Standby RTC
Mode or Deep Standby
Stop Mode State
State
State
Function
Group
Power
Supply
Unstable
‐
Power
Supply
Stable
INITX=1
‐
Power
Supply
Stable
INITX=1
Power Supply
Stable
Power Supply
Stable
Power Supply
Stable
INITX=0
‐
INITX=1
‐
INITX=1
INITX=1
‐
SPL=0
SPL=1
SPL=0
SPL=1
-
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Internal
input fixed
at 0 /
Internal
input fixed
at 0 /
Internal
input fixed
at 0 /
Internal
input fixed
at 0 /
Internal
input fixed
at 0 /
Internal
input fixed
at 0 /
Internal
input fixed
at 0 /
Internal
input fixed
at 0 /
Analog
input
Hi-Z
selected
Analog
input
Analog
input
Analog
input
Analog
input
Analog
input
Analog
input
Analog
input
Analog
input
enabled
enabled
enabled
enabled
enabled
enabled
enabled
enabled
L
Resource
other than
above
GPIO
Hi-Z /
Hi-Z /
Maintain
previous
state
Maintain
previous
state
selected
Internal
input fixed
at 0
Setting
disabled
Setting
disabled
Setting
disabled
Internal
input fixed
at 0
Internal
input fixed
at 0
GPIO
selected
selected
GPIO
selected
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Internal
input fixed
at 0 /
Internal
input fixed
at 0 /
Internal
input fixed
at 0 /
Internal
input fixed
at 0 /
Internal
input fixed
at 0 /
Internal
input fixed
at 0 /
Internal
input fixed
at 0 /
Internal
input fixed
at 0 /
Analog
input
Hi-Z
selected
Analog
input
Analog
input
Analog
input
Analog
input
Analog
input
Analog
input
Analog
input
Analog
input
enabled
enabled
enabled
enabled
enabled
enabled
enabled
enabled
External
interrupt
enabled
selected
Resource
other than
above
M
Maintain
previous
state
GPIO
Hi-Z /
Maintain
previous
state
Maintain
previous
state
selected
Internal
input fixed
at 0
Setting
disabled
Setting
disabled
Setting
disabled
Internal
input fixed
at 0
GPIO
selected
Hi-Z /
Internal
input fixed
at 0
selected
GPIO
selected
Document Number: 002-04922 Rev.*B
Page 48 of 128
MB9B560L Series
Return
from
Deep
Standby
Mode
State
Power-on
Reset or
Low-Voltage
Detection
State
Device
Internal
Reset
Run Mode
or Sleep
Mode
INITX
Input
State
Timer Mode,
RTC Mode, or
Stop Mode State
Deep Standby RTC
Mode or Deep Standby
Stop Mode State
State
State
Function
Group
Power
Supply
Unstable
‐
Power
Supply
Stable
INITX=1
‐
Power
Supply
Stable
INITX=1
Power Supply
Stable
Power Supply
Stable
Power Supply
Stable
INITX=0
‐
INITX=1
‐
INITX=1
INITX=1
‐
SPL=0
SPL=1
Hi-Z /
SPL=0
Hi-Z /
SPL=1
Hi-Z /
-
Hi-Z /
Internal
Hi-Z /
Internal
Hi-Z /
Hi-Z /
Hi-Z /
Internal
input fixed
at 0 /
Internal
input fixed
at 0 /
Internal
input fixed
at 0 /
Internal
input fixed
at 0 /
Internal
input fixed
at 0 /
Internal
input fixed
at 0 /
Analog
input
input fixed input fixed
Hi-Z
at 0 /
at 0 /
selected
Analog
input
Analog
input
Analog
input
Analog
input
Analog
input
Analog
input
Analog
input
Analog
input
enabled
enabled
enabled
enabled
enabled
enabled
WKUP
input
enabled
WKUP
input
enabled
WKUP
enabled
enabled
enabled
Maintain
previous
state
Setting
disabled
Setting
disabled
Setting
disabled
O
External
interrupt
enabled
selected
Maintain
previous
state
Maintain
previous
state
GPIO
selected
GPIO
Hi-Z /
selected
Internal
input fixed
at 0
Resource
other than
above
Internal
input fixed
at 0
Hi-Z /
Hi-Z
Input
enabled
Hi-Z
Input
enabled
Internal
input fixed
at 0
Hi-Z
Hi-Z
selected
GPIO
selected
Hi-Z /
Internal
input fixed input fixed
at 0 /
Hi-Z /
Internal
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Internal
input fixed
at 0 /
Internal
input fixed
at 0 /
Internal
input fixed
at 0 /
Internal
input fixed
at 0 /
Internal
input fixed
at 0 /
Internal
input fixed
at 0 /
Analog
input
at 0 /
selected
Analog
input
Analog
input
Analog
input
Analog
input
Analog
input
Analog
input
Analog
input
Analog
input
enabled
enabled
enabled
enabled
enabled
enabled
enabled
Hi-Z /
WKUP
input
enabled
Maintain
previous
state
WKUP
input
enabled
WKUP
enabled
P
enabled
Maintain
previous
state
Maintain
previous
state
Resource
other than
above
Setting
disabled
Setting
disabled
Setting
disabled
GPIO
selected
GPIO
Hi-Z /
Hi-Z /
selected
Internal
input fixed
at 0
Internal
input fixed
at 0
Internal
input fixed
at 0
selected
GPIO
selected
Document Number: 002-04922 Rev.*B
Page 49 of 128
MB9B560L Series
Return
from
Deep
Standby
Mode
State
Power-on
Reset or
Low-Voltage
Detection
State
Device
Internal
Reset
Run Mode
or Sleep
Mode
INITX
Input
State
Timer Mode,
RTC Mode, or
Stop Mode State
Deep Standby RTC
Mode or Deep Standby
Stop Mode State
State
State
Function
Group
Power
Supply
Unstable
Power
Supply
Stable
Power
Supply
Stable
Power Supply
Stable
Power Supply
Stable
Power Supply
Stable
‐
INITX=0
INITX=1
INITX=1
INITX=1
INITX=1
INITX=1
-
‐
‐
‐
‐
SPL=0
SPL=1
SPL=0
SPL=1
Hi-Z /
WKUP
input
enabled
WKUP
enabled
WKUP
input
enabled
Maintain
previous
state
Setting
disabled
Setting
disabled
Setting
disabled
External
interrupt
enabled
selected
Resource
other than
above
selected
GPIO
selected
Maintain
previous
state
Maintain
previous
state
GPIO
selected
Q
GPIO
Hi-Z /
selected
Internal
input fixed
at 0
Internal
input fixed
at 0
Hi-Z /
Hi-Z /
Input
enabled
Hi-Z /
Input
enabled
Internal
input fixed
at 0
Hi-Z
Hi-Z
GPIO
Hi-Z /
selected
Internal
input fixed
at "0"
Hi-Z /
Input
Internal
input fixed
at "0"
Hi-Z /
Input
Hi-Z /
Hi-Z /
Input
enabled
Hi-Z /
Input
enabled
Maintain
previous
state
GPIO
selected
Internal
input fixed
at 0
GPIO
selected
enabled
enabled
Maintain
previous
state
R
Hi-Z at
trans-
Hi-Z at
trans-
mission/
Input
enabled/
Internal
input fixed
at 0 at
mission/
Input
enabled/
Internal
input fixed
at 0 at
Hi-Z /
Input
enabled
Hi-Z /
Input
enabled
Hi-Z /
Input
enabled
Setting
disabled
Setting
disabled
Setting
disabled
USB I/O pin
reception
reception
*1: Oscillation is stopped at Sub timer mode, sub CR timer mode, RTC mode, Stop mode, Deep Standby RTC mode, and Deep
Standby Stop mode.
*2: Maintain previous state at timer mode. GPIO selected Internal input fixed at 0 at RTC mode, Stop mode.
*3: Maintain previous state at timer mode. Hi-Z/Internal input fixed at 0 at RTC mode, Stop mode.
Document Number: 002-04922 Rev.*B
Page 50 of 128
MB9B560L Series
List of VBAT Domain Pin Status
Return
from
Deep
Standby
Mode
State
Return
from
VBAT
RTC
Mode
State
Run
Mode or
Sleep
Mode
Device
VBAT
RTC
Mode
State
INITX
Input
State
Timer Mode,
RTC Mode, or
Stop Mode State
Deep Standby
RTC Mode or Deep
Standby Stop Mode State
Power-on
Reset*1
Internal
Reset
State
State
Function
Group
Power
Supply
Unstable
‐
Power
Supply
Stable
INITX=1
‐
Power
Supply
Stable
INITX=1
-
Power
Supply
Stable
-
-
Power
Supply
Stable
-
-
Power Supply Stable
Power Supply Stable
INITX=1
Power Supply Stable
INITX=1
INITX=0
‐
INITX=1
‐
‐
SPL=0
Maintain
previous
state
SPL=1
Maintain
previous
state
SPL=0
Maintain
previous
state
SPL=1
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
GPIO
Setting
Setting
-
selected
disabled
prohibition
Sub
crystal
S
oscillator
input pin /
External
sub clock
input
Maintain
previous
state
Maintain
previous
state
Input
Input
Input
Input
Input
Input
Input
Input
Input
enabled
enabled
enabled
enabled
enabled
enabled
enabled
enabled
enabled
selected
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
GPIO
Setting
Setting
-
selected
disabled
prohibition
External
sub clock
input
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Setting
disabled
T
selected
Hi-Z /
Maintain
previous
state/When
oscillation
stops, Hi-Z
*2
Maintain
previous
state/When
oscillation
stops, Hi-Z
*2
Maintain
previous
state/When
oscillation
stops, Hi-Z
*2
Maintain
previous
state/When
oscillation
stops, Hi-Z
*2
Sub
Internal
input
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
crystal
oscillator
output pin
fixed at 0
or Input
enabled
Resource
selected
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
U
Hi-Z
GPIO
selected
*1: When VBAT and VCC power on.
*2: When The SOSCNTL bit in the WTOSCCNT Register is “0”, Sub crystal oscillator output pin is maintain previous state.
When The SOSCNTL bit in the WTOSCCNT Register is “1”, Oscillation is stopped at STOP mode and Deep standby STOP mode.
Document Number: 002-04922 Rev.*B
Page 51 of 128
MB9B560L Series
12.Electrical Characteristics
12.1 Absolute Maximum Ratings
Parameter
Rating
Symbol
Unit
Remarks
Min
Max
Power supply voltage *1, *2
Power supply voltage (for USB)*1, * 3
Power supply voltage (VBAT) *1 ,*4
Analog power supply voltage *1 ,*5
Analog reference voltage *1 ,*5
VCC
VSS - 0.5
VSS + 6.5
V
V
V
USBVCC
VBAT
VSS - 0.5
VSS - 0.5
VSS + 6.5
VSS + 6.5
VSS + 6.5
AVCC
VSS - 0.5
VSS - 0.5
V
V
AVRH
VSS + 6.5
VCC + 0.5
(≤ 6.5V)
V
SS - 0.5
V
Except for USB pin
Input voltage *1
VI
USBVCC + 0.5
(≤ 6.5V)
VSS - 0.5
VSS - 0.5
VSS - 0.5
V
V
V
USB pin
VSS + 6.5
5 V tolerant
AVCC + 0.5
(≤ 6.5V)
VCC + 0.5
(≤ 6.5V)
10
20
20
22.4
4
8
Analog pin input voltage *1
Output voltage *1
VIA
VO
VSS - 0.5
V
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
4 mA type
8 mA type
12 mA type
I2C Fm+
4 mA type
8 mA type
12 mA type
I2C Fm+
"L" level maximum output current *6
"L" level average output current *7
IOL
-
IOLAV
-
12
20
100
50
"L" level total maximum output current
"L" level total average output current *8
∑IOL
∑IOLAV
-
-
- 10
- 20
mA
mA
4 mA type
8 mA type
"H" level maximum output current *6
"H" level average output current *7
IOH
-
-
- 20
- 4
- 8
- 12
- 100
- 50
+ 150
mA
mA
mA
mA
mA
mA
°C
12 mA type
4 mA type
8 mA type
12 mA type
IOHAV
"H" level total maximum output current
"H" level total average output current *8
Storage temperature
∑IOH
∑IOHAV
TSTG
-
-
- 55
*1: These parameters are based on the condition that VSS = AVSS = 0.0 V.
*2: VCC must not drop below VSS - 0.5 V.
*3: USBVCC must not drop below VSS - 0.5 V.
*4: VBAT must not drop below VSS - 0.5 V.
*5: Ensure that the voltage does not exceed VCC + 0.5 V, for example, when the power is turned on.
*6: The maximum output current is defined as the value of the peak current flowing through any one of the
corresponding pins.
*7: The average output current is defined as the average current value flowing through any one of the
corresponding pins for a 100ms period.
*8: The total average output current is defined as the average current value flowing through all of
corresponding pins for a period of 100 ms.
WARNING:
−
Semiconductor devices may be permanently damaged by application of stress (including, without limitation, voltage, current
or temperature) in excess of absolute maximum ratings.
Do not exceed any of these ratings.
Document Number: 002-04922 Rev.*B
Page 52 of 128
MB9B560L Series
12.2 Recommended Operating Conditions
Value
Parameter
Symbol
Conditions
Unit
Remarks
Min
Max
Power supply voltage
VCC
-
2.7 *5
5.5
V
3.6
(≤ VCC
5.5
(≤ VCC
5.5
3.0
2.7
*1
*2
)
)
Power supply voltage (for USB)
USBVCC
-
V
Power supply voltage (VBAT)
Analog power supply voltage
Analog reference voltage
Smoothing capacitor
VBAT
AVCC
AVRH
CS
Tj
TA
-
-
-
-
-
-
2.7
2.7
*3
1
- 40
- 40
V
5.5
AVCC
10
+ 125
*4
V
V
μF
°C
°C
AVCC=VCC
for built-in regulator *6
Junction temperature
Ambient temperature
Operating
temperature
*1: When P81/UDP0 and P80/UDM0 pins are used as USB (UDP0, UDM0).
*2: When P81/UDP0 and P80/UDM0 pins are used as GPIO (P81, P80).
*3: The minimum value of Analog reference voltage depends on the value of compare clock cycle (Tcck).
See "5. 12-bit A/D Converter" for the details.
*4: The maximum temperature of the ambient temperature (TA) can guarantee a range that does not exceed
the junction temperature (Tj).
The calculation formula of the ambient temperature (TA) is shown below.
TA(Max) = Tj(Max) - Pd(Max) × θja
Pd: Power dissipation (W)
θja: Package thermal resistance (°C/W)
Pd (Max) = VCC × ICC (Max) + Σ (IOL×VOL) + Σ ((VCC-VOH) × (- IOH))
IOL
IOH
VOL
VOH
:
:
L level output current
H level output current
L level output voltage
H level output voltage
:
:
*5: In between less than the minimum power supply voltage and low voltage reset/interrupt detection voltage or more, instruction
execution and low voltage detection function by built-in High-speed CR (including Main PLL is used) or built-in Low-speed CR is
possible to operate only.
*6: See "C pin" in "Handling Devices" for the connection of the smoothing capacitor.
Package thermal resistance and maximum permissible power for each package are shown below.
The operation is guaranteed maximum permissible power or less for semiconductor devices.
Table for Package Thermal Resistance and Maximum Permissible Power
Thermal
resistance θja
Maximum permissible Power (mW)
Package
Printed Circuit Board
TA=+85°C
TA=+105°C
(°C/W)
87
53
30
24
70
45
61
40
Single-layered both sides
4 layers
Single-layered both sides
4 layers
Single-layered both sides
4 layers
Single-layered both sides
4 layers
460
755
1333
1667
571
889
656
1000
1667
1905
230
377
667
833
286
444
328
500
833
952
LQA048
(0.5mm pitch)
VNA048
(0.5mm pitch)
LQD064
(0.5mm pitch)
LQG064
(0.65mm pitch)
Single-layered both sides
4 layers
24
21
VNC064
(0.5mm pitch)
Document Number: 002-04922 Rev.*B
Page 53 of 128
MB9B560L Series
WARNING:
−
The recommended operating conditions are required to ensure the normal operation of the semiconductor device. All of the
device's electrical characteristics are warranted when the device is operated under these conditions.
Any use of semiconductor devices will be under their recommended operating condition.
Operation under any conditions other than these conditions may adversely affect reliability of device and could result in device
failure.
No warranty is made with respect to any use, operating conditions or combinations not represented on this data sheet. If you
are considering application under any conditions other than listed herein, please contact sales representatives beforehand.
Document Number: 002-04922 Rev.*B
Page 54 of 128
MB9B560L Series
Calculation Method of Power Dissipation (Pd)
The power dissipation is shown in the following formula.
Pd = VCC × ICC + Σ (IOL × VOL) + Σ ((VCC-VOH) × (-IOH))
IOL
IOH
VOL
VOH
:
"L" level output current
"H" level output current
"L" level output voltage
"H" level output voltage
:
:
:
ICC is a current consumed in device.
It can be analyzed as follows.
ICC = ICC(INT) + ΣICC(IO)
ICC(INT): Current consumed in internal logic and memory, etc. through regulator
ΣICC(IO): Sum of current (I/O switching current) consumed in output pin
For ICC (INT), it can be anticipated by "12.3.1 Current Rating" in "12.3 DC Characteristics" (This rating value does not include ICC (IO)
for a value at pin fixed).
For Icc (IO), it depends on system used by customers.
The calculation formula is shown below.
I
CC(IO) = (CINT + CEXT) × VCC × fsw
CINT: Pin internal load capacitance
CEXT: External load capacitance of output pin
fSW: Pin switching frequency
Parameter
Symbol
Conditions
Capacitance Value
4 mA type
1.93 pF
Pin internal load capacitance
CINT
8 mA type
3.45 pF
3.42 pF
12 mA type
Calculate ICC (Max) as follows when the power dissipation can be evaluated.
1. Measure current value ICC (Typ) at normal temperature (+25°C).
2. Add maximum leak current value ICC (leak_max) at operating on a value in (1).
ICC(Max) = ICC(Typ) + ICC(leak_max)
Parameter
Symbol
Conditions
Current Value
Tj = +125 °C
28 mA
Maximum leak current at operating
ICC(leak_max)
Tj = +105 °C
Tj = +85 °C
17 mA
13 mA
Document Number: 002-04922 Rev.*B
Page 55 of 128
MB9B560L Series
Current Explanation Diagram
Pd = VCC×ICC + Σ(IOL×VOL)＋Σ((VCC-VOH)×(－IOH))
CC = ICC(INT)＋ΣICC(IO)
VCC
I
A
ICC
Chip
ΣICC(IO)
ICC(INT)
A
IOL
Regulator
VOL
V
Flash
VOH
A
IOH
V
Logic
RAM
CEXT
Document Number: 002-04922 Rev.*B
Page 56 of 128
MB9B560L Series
12.3 DC Characteristics
12.3.1 Current Rating
Value
Pin
Name
Parameter
Symbol
Conditions
Frequency*4
Unit
Remarks
Typ*1
44
Max*2
72
160 MHz
144 MHz
40
67
120 MHz
100 MHz
80 MHz
60 MHz
40 MHz
20 MHz
8 MHz
34
29
23
18
13
7.7
4.6
3.6
30
60
55
48
42
37
31
27
26
58
*3
mA
When all peripheral
clocks are ON
Power
supply
current
Normal
operation
(PLL)
4 MHz
160 MHz
ICC
VCC
*5, *6
144 MHz
120 MHz
100 MHz
80 MHz
27
23
20
16
54
49
46
41
*3
mA
When all peripheral
clocks are OFF
60 MHz
13
38
40 MHz
20 MHz
8 MHz
4 MHz
9
33
30
27
26
5.7
3.7
3
Value
Pin
Name
Parameter
Symbol
Conditions
Frequency*7
Unit
Remarks
Typ*1
64
Max*2
101
160 MHz
144 MHz
60
96
120 MHz
100 MHz
80 MHz
60 MHz
40 MHz
20 MHz
8 MHz
52
46
39
32
25
15
7.8
5.2
47
88
81
73
65
58
47
39
36
80
*3
mA
When all peripheral
clocks are ON
Power
supply
current
Normal
operation
(PLL)
4 MHz
160 MHz
ICC
VCC
*8
144 MHz
120 MHz
100 MHz
80 MHz
43
39
35
30
75
71
66
61
*3
mA
When all peripheral
clocks are OFF
60 MHz
25
55
40 MHz
20 MHz
8 MHz
4MHz
20
13
6.7
4.6
50
42
36
34
*1: TA=+25 °C, VCC=3.3 V
*2: Tj=+125 °C, VCC=5.5 V
*3: When all ports are input and are fixed at "0".
*4: Frequency is a value of HCLK. PCLK0=PCLK1=PCLK2=HCLK/2
*5: When operating flash accelerator mode and trace buffer function (FRWTR.RWT = 10, FBFCR.BE = 1)
*6: Data access is nothing to MainFlash memory
*7: Frequency is a value of HCLK. PCLK0=PCLK2=HCLK/2, PCLK1=HCLK
*8: When stopping flash accelerator mode and trace buffer function (FRWTR.RWT = 10, FBFCR.BE = 0)
Document Number: 002-04922 Rev.*B
Page 57 of 128
MB9B560L Series
Value
Typ*1
Pin
Name
Frequency*4
(MHz)
Parameter
Symbol
Conditions
Unit
Remarks
Max*2
75
72 MHz
60 MHz
41
36
69
48 MHz
36 MHz
24 MHz
31
25
18
64
57
50
*3
mA
When all peripheral
clocks are ON
12 MHz
8 MHz
4 MHz
72 MHz
60 MHz
48 MHz
36 MHz
24 MHz
11
8.1
5.4
32
28
24
20
15
42
39
37
63
58
54
50
45
Power
supply
current
Normal
operation
(PLL)
ICC
VCC
*5
*3
mA
When all peripheral
clocks are OFF
12 MHz
8 MHz
4 MHz
9.1
6.9
4.6
38
36
34
*1: TA=+25 °C, VCC=3.3 V
*2: Tj=+125 °C, VCC=5.5 V
*3: When all ports are input and are fixed at "0".
*4: Frequency is a value of HCLK. PCLK0=PCLK1=PCLK2=HCLK
*5: When 0 wait-cycle mode (FRWTR.RWT = 00, FSYNDN.SD = 00)
Value
Pin
Name
Parameter
Symbol
Conditions
Frequency*4
Unit
Remarks
Typ*1
Max*2
*3
3.3
29
mA
When all peripheral
clocks are ON
*3
When all peripheral
clocks are OFF
Normal
operation
(built-in
high-speed CR)
*5
*5
4 MHz
2.8
29
27
27
27
27
mA
mA
mA
mA
mA
*3
0.51
0.50
0.54
0.52
When all peripheral
clocks are ON
Normal
operation
(sub oscillation)
Power
supply
current
32 kHz
ICC
VCC
*3
When all peripheral
clocks are OFF
*3
When all peripheral
clocks are ON
Normal
operation
(built-in
*5
100 kHz
*3
low-speed CR)
When all peripheral
clocks are OFF
*1: TA=+25 °C, VCC=3.3 V
*2: Tj=+125 °C, VCC=5.5 V
*3: When all ports are input and are fixed at "0".
*4: Frequency is a value of HCLK. PCLK0=PCLK1=PCLK2=HCLK/2
*5: When 0 wait-cycle mode (FRWTR.RWT = 00, FSYNDN.SD = 000)
Document Number: 002-04922 Rev.*B
Page 58 of 128
MB9B560L Series
Value
Max*2
Pin
Name
Parameter
Symbol
Conditions
Frequency*4
Unit
Remarks
Typ*1
160 MHz
144 MHz
28
25
58
55
120 MHz
100 MHz
80 MHz
60 MHz
40 MHz
20 MHz
8 MHz
21
18
15
50
46
43
39
36
32
30
29
44
*3
mA
When all peripheral
clocks are ON
12
8.8
5.6
3.8
3.2
14
Power
supply
current
SLEEP
operation
(PLL)
4 MHz
160 MHz
ICCS
VCC
144 MHz
120 MHz
100 MHz
80 MHz
13
11
9.7
8.1
43
40
38
36
*3
mA
When all peripheral
clocks are OFF
60 MHz
6.7
34
40 MHz
20 MHz
8 MHz
4 MHz
5.2
3.7
2.9
2.6
32
30
29
29
Value
Pin
Name
Parameter
Symbol
Conditions
Frequency*5
Unit
Remarks
Typ*1
Max*2
72 MHz
60 MHz
19
16
47
43
48 MHz
36 MHz
24 MHz
13
10
40
37
34
*3
mA
When all peripheral
clocks are ON
7.8
12 MHz
8 MHz
4 MHz
72 MHz
60 MHz
48 MHz
36 MHz
24 MHz
5.2
4.3
3.5
8.8
7.7
6.6
5.5
4.4
31
30
29
36
35
34
32
31
Power
supply
current
SLEEP
operation
(PLL)
ICCS
VCC
*3
mA
When all peripheral
clocks are OFF
12 MHz
8 MHz
4 MHz
3.4
3
30
29
29
2.7
*1: TA=+25 °C, VCC=3.3 V
*2: Tj=+125 °C, VCC=5.5 V
*3: When all ports are input and are fixed at "0".
*4: Frequency is a value of HCLK. PCLK0=PCLK1=PCLK2=HCLK/2
*5: Frequency is a value of HCLK. PCLK0=PCLK1=PCLK2=HCLK
Document Number: 002-04922 Rev.*B
Page 59 of 128
MB9B560L Series
Value
Typ*1
Pin
Name
Parameter
Symbol
Conditions
Frequency*4
Unit
Remarks
Max*2
*3
1.3
27
mA
When all peripheral
clocks are ON
SLEEP
operation
(built-in
high-speed CR)
4 MHz
*3
0.91
0.49
0.48
27
27
27
mA
mA
mA
When all peripheral
clocks are OFF
*3
When all peripheral
clocks are ON
*3
When all peripheral
clocks are OFF
SLEEP
operation
(sub oscillation)
Power
supply
current
32 kHz
ICCS
VCC
*3
0.51
0.49
27
27
mA
mA
When all peripheral
clocks are ON
SLEEP
operation
(built-in
100 kHz
*3
low-speed CR)
When all peripheral
clocks are OFF
*1: TA=+25 °C, VCC=3.3 V
*2: Tj=+125 °C, VCC=5.5 V
*3: When all ports are input and are fixed at "0".
*4: Frequency is a value of HCLK. PCLK0=PCLK1=PCLK2=HCLK/2
Document Number: 002-04922 Rev.*B
Page 60 of 128
MB9B560L Series
Value
Pin
Name
Parameter
Symbol
Conditions
Frequency
Unit
Remarks
Typ*1
Max*2
*3, *4
TA=+25°C
0.25
1.0
mA
*3, *4
TA =+85°C
*3, *4
TA =+105°C
*3, *4
TA =+25°C
*3, *4
TA =+85°C
*3, *4
TA =+105°C
ICCH
STOP mode
-
-
11
14
mA
mA
mA
mA
mA
-
0.54
1.54
12
TIMER mode
(built-in
high-speed CR)
4 MHz
32 kHz
-
-
15
*3, *4
TA =+25°C
0.25
-
1.0
11
mA
mA
Power supply
current
TIMER mode
(sub oscillation)
*3, *4
TA =+85°C
VCC
ICCT
*3, *4
TA =+105°C
*3, *4
TA =+25°C
*3, *4
TA =+85°C
*3, *4
TA =+105°C
*3, *4
TA =+25°C
*3, *4
TA =+85°C
*3, *4
TA =+105°C
-
14
1.0
11
mA
mA
mA
mA
mA
mA
mA
0.26
TIMER mode
(built-in
low-speed CR)
100 kHz
32 kHz
-
-
14
1.0
11
0.25
RTC mode
(sub oscillation)
ICCR
-
-
14
*1: VCC=3.3 V
*2: VCC=5.5 V
*3: When all ports are input and are fixed at "0".
*4: When LVD is OFF
Document Number: 002-04922 Rev.*B
Page 61 of 128
MB9B560L Series
Value
Max*2
Pin
Name
Parameter
Symbol
Conditions
Frequency
Unit
Remarks
Typ*1
*3, *4
TA=+25°C
*3, *4
TA =+85°C
*3, *4
TA =+105°C
*3, *4
TA =+25°C
*3, *4
TA =+85°C
*3, *4
TA =+105°C
*3, *4
TA =+25°C
*3, *4
TA =+85°C
*3, *4
TA =+105°C
*3, *4
TA =+25°C
*3, *4
TA =+85°C
*3, *4
TA =+105°C
*3, *4, *5
TA =+25°C
*3, *4, *5
TA =+85°C
*3, *4, *5
TA =+105°C
*3, *4
TA =+25°C
*3, *4
TA =+85°C
*3, *4
27
140
590
770
180
870
1200
140
590
770
180
870
1200
0.14
4.0
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
Deep standby
STOP mode
(When RAM is
OFF)*6
-
-
ICCHD
-
32
Deep standby
STOP mode
(When RAM is
ON)*6
-
-
VCC
27
Deep standby
RTC mode
(When RAM is
OFF)*7
-
-
Power
supply
current
ICCRD
32 kHz
32
Deep standby
RTC mode
(When RAM is
ON)*7
-
-
0.015
RTC stop*9
-
-
-
1.3
-
9.4
ICCVBAT
VBAT
2.4
RTC
operation*8, *9
32 kHz
6.2
-
12
TA =+105°C
*1: VCC=3.3 V
*2: VCC=5.5 V
*3: When all ports are input and are fixed at "0".
*4: When LVD is OFF
*5: When sub oscillation is OFF
*6: When 48 pin Package, add supply current of RTC stop.
*7: When 48 pin Package, add supply current of RTC operation.
*8: When using the crystal oscillator of 32 kHz (including the current consumption of the oscillation circuit).
*9: In the case of setting RTC after VCC power on.
Document Number: 002-04922 Rev.*B
Page 62 of 128
MB9B560L Series
Value
Typ
Pin
Name
Parameter
Symbol
Conditions
Unit
Remarks
Min
Max
Low-voltage
detection circuit
(LVD) power
supply current
For occurrence of
interrupt
ICCLVD
At operation
-
4
7
μA
Main flash
memory
write/erase
current
VCC
ICCFLASH
At Write/Erase
At Write/Erase
-
-
13.4
11.5
15.9
13.6
mA
mA
Work flash
memory
write/erase
current
ICCWFLASH
Peripheral Current Dissipation
Frequency (MHz)
Clock
Peripheral
System
Unit
Unit
Remarks
40
80
160
GPIO
All ports
0.21
0.43
0.92
2.74
1.46
0.11
1.60
0.70
DMAC
-
0.71
0.36
0.03
0.42
0.18
1.43
0.72
0.06
0.80
0.36
HCLK
DSTC
CAN
-
mA
1ch.
1ch.
4ch.
USB
Base timer
Multi-functional
timer/PPG
Quadrature
position/Revolution
counter
1 unit/4ch.
1 unit
0.57
0.04
1.13
0.08
2.24
0.16
PCLK1
PCLK2
mA
mA
A/DC
1 unit
1ch.
0.21
0.33
0.40
0.67
0.79
-
Multi-function serial
Document Number: 002-04922 Rev.*B
Page 63 of 128
MB9B560L Series
12.3.2 Pin Characteristics
(VCC = USBVCC = AVCC = 2.7V to 5.5V, VSS = AVSS = 0V)
Value
Parameter
Symbol
Pin Name
Conditions
Unit
Remarks
Min
Typ
Max
CMOS
hysteresis
input pin,
MD0, MD1
5V tolerant
input pin
Input pin
doubled as I2C
Fm+
-
VCC×0.8
-
VCC + 0.3
V
"H" level input
voltage
(hysteresis
input)
VIHS
-
-
VCC×0.8
VCC×0.7
-
-
VSS + 5.5
VSS + 5.5
V
V
CMOS
hysteresis
input pin,
MD0, MD1
5V tolerant
input pin
Input pin
doubled as I2C
Fm+
-
-
VSS - 0.3
-
VCC×0.2
V
"L" level input
voltage
(hysteresis
input)
VILS
VSS - 0.3
VSS
-
-
VCC×0.2
VCC×0.3
V
V
-
V
CC ≥ 4.5 V,
I
OH = - 4 mA
4mA type
8mA type
VCC - 0.5
VCC - 0.5
-
-
VCC
V
V
VCC < 4.5 V,
IOH = - 2 mA
V
IOH = - 8 mA
VCC < 4.5 V,
IOH = - 4 mA
VCC ≥ 4.5 V,
IOH = - 12 mA
CC ≥ 4.5 V,
VCC
"H" level output
voltage
VOH
12mA type
VCC - 0.5
-
VCC
V
VCC < 4.5 V,
IOH = - 8 mA
USBVCC ≥ 4.5 V,
IOH = - 20.5 mA
USBVCC < 4.5 V,
IOH = - 13.0 mA
VCC ≥ 4.5 V,
IOH = - 4 mA
VCC < 4.5 V,
IOH = - 3 mA
The pin
doubled as
USB I/O
USBVCC - 0.4
VCC - 0.5
-
-
USBVCC
V
V
The pin
doubled as I2C
Fm+
VCC
At GPIO
Document Number: 002-04922 Rev.*B
Page 64 of 128
MB9B560L Series
Value
Typ
Parameter
Symbol
Pin Name
Conditions
Unit
Remarks
Min
Max
V
CC ≥ 4.5 V,
IOL = 4 mA
4 mA type
VSS
-
-
-
-
0.4
V
V
V
V
VCC < 4.5 V,
IOL = 2 mA
V
CC ≥ 4.5 V,
IOH = 8 mA
8 mA type
VSS
VSS
VSS
0.4
0.4
0.4
VCC < 4.5 V,
IOH = 4 mA
V
CC ≥ 4.5 V,
I
OL = 12 mA
12 mA type
"L" level output
voltage
VCC < 4.5 V,
OL = 8 mA
VOL
I
USBVCC ≥ 4.5 V,
IOL = 18.5 mA
The pin
doubled as
USB I/O
USBVCC < 4.5 V,
IOL = 10.5 mA
V
CC ≥ 4.5 V,
IOH = 4 mA
At GPIO
The pin
VCC < 4.5 V,
IOH = 3 mA
doubled as
VSS
-
-
0.4
+ 5
V
I2C Fm+
VCC ≤ 5.5 V,
IOH = 20 mA
At I2C Fm+
Input leak
current
IIL
-
-
- 5
μA
kΩ
V
CC ≥ 4.5 V
25
30
50
80
100
200
Pull-up resistor
value
RPU
Pull-up pin
VCC < 4.5 V
Other than
VCC,
USBVCC,
VBAT,
VSS,
Input
capacitance
CIN
-
-
5
15
pF
AVCC,
AVSS,
AVRH
Document Number: 002-04922 Rev.*B
Page 65 of 128
MB9B560L Series
12.4 AC Characteristics
12.4.1 Main Clock Input Characteristics
(VCC = 2.7V to 5.5V, VSS = 0V)
Value
Min Max
Pin
Name
Parameter
Symbol
Conditions
Unit
Remarks
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
4
4
4
4
48
MHz
When crystal oscillator is connected
When using external clock
20
Input frequency
fCH
48
MHz
20
X0,
X1
20.83
50
250
250
Input clock cycle
tCYLH
-
ns
%
When using external clock
When using external clock
Input clock pulse
width
PWH/tCYLH
PWL/tCYLH
,
45
55
Input clock rising time tCF
,
-
-
-
-
5
ns
When using external clock
Base clock (HCLK/FCLK)
and falling time
tCR
fCC
-
160
MHz
fCP0
fCP1
fCP2
-
-
-
-
-
-
-
-
-
80
MHz
MHz
MHz
APB0 bus clock*2
APB1 bus clock*2
APB2 bus clock*2
Internal operating
clock*1 frequency
160
80
tCYCC
-
-
6.25
-
ns
Base clock (HCLK/FCLK)
tCYCP0
tCYCP1
tCYCP2
-
-
-
-
-
-
12.5
6.25
12.5
-
-
-
ns
ns
ns
APB0 bus clock*2
APB1 bus clock*2
APB2 bus clock*2
Internal operating
clock*1 cycle time
*1: For more information about each internal operating clock, see CHAPTER 2-1: Clock in FM4 Family Peripheral Manual Main
part (002-04856).
*2: For about each APB bus which each peripheral is connected to, see 8. Block Diagram in this data sheet.
t
CYLH
0.8 × Vcc
X0
0.8 × Vcc
0.2 × Vcc
0.8 × Vcc
0.2 × Vcc
P
WH
P
WL
t
CF
t
CR
Document Number: 002-04922 Rev.*B
Page 66 of 128
MB9B560L Series
12.4.2 Sub Clock Input Characteristics
(VBAT = 2.7V to 5.5V, VSS = 0V)
Value
Typ
Pin
Name
Parameter
Symbol
Conditions
Unit
Remarks
Min
Max
When crystal oscillator is
connected
-
-
32.768
-
kHz
Input frequency
1/ tCYLL
-
-
32
10
-
-
100
kHz
When using external clock
When using external clock
X0A,
X1A
Input clock cycle
tCYLL
-
31.25
μs
PWH/tCYLL
PWL/tCYLL
,
Input clock pulse width
45
-
55
%
When using external clock
t
CYLL
0.8 × VB
V
AT
0.8 ×
BAT
V
0.8 ×
BAT
V
V
0.2 ×
0.2 ×
BAT
BAT
X0A
P
WH
P
WL
In the case of 48 pin Package, VBAT is VCC.
12.4.3 Built-in CR Oscillation Characteristics
Built-in High-Speed CR
(VCC = 2.7V to 5.5V, VSS = 0V)
Value
Typ
Parameter
Symbol
Conditions
Unit
Remarks
Min
Max
TJ = -20°C to +105°C
3.92
3.88
3
4
4.08
4.12
5
When trimming *1
Clock frequency
fCRH
TJ = - 40°C to +125°C
4
4
-
MHz
TJ = - 40°C to +125°C
-
When not trimming
*2
Frequency
stabilization time
tCRWT
-
30
μS
*1: In the case of using the values in CR trimming area of Flash memory at shipment for frequency/temperature trimming.
*2: This is the time to stabilize the frequency of high-speed CR clock after setting trimming value.
This period is able to use high-speed CR clock as source clock.
Built-in Low-Speed CR
(VCC = 2.7V to 5.5V, VSS = 0V)
Remarks
Value
Typ
Parameter
Symbol
Condition
Unit
Min
Max
Clock frequency
fCRL
-
50
100
150
kHz
Document Number: 002-04922 Rev.*B
Page 67 of 128
MB9B560L Series
12.4.4 Operating Conditions of Main PLL (In the Case of Using Main Clock for Input Clock of PLL)
(VCC = 2.7V to 5.5V, VSS = 0V)
Value
Typ
Parameter
Symbol
Unit
Remarks
Min
Max
PLL oscillation stabilization wait time*1
(LOCK UP time)
tLOCK
200
-
-
μs
PLL input clock frequency
PLL multiplication rate
fPLLI
-
fPLLO
fCLKPLL
4
-
-
-
-
16
MHz
13
200
-
80
multiplier
MHz
PLL macro oscillation clock frequency
Main PLL clock frequency*2
320
160
MHz
*1: Time from when the PLL starts operating until the oscillation stabilizes.
*2: For more information about Main PLL clock (CLKPLL), see CHPATER 2-1: Clock in FM4 Family Peripheral Manual Main part
(002-04856).
12.4.5 Operating Conditions of USB PLL (In the Case of Using Main Clock for Input Clock of PLL)
(VCC = 2.7V to 5.5V, VSS = 0V)
Value
Parameter
Symbol
Unit
Remarks
Min
Typ
Max
PLL oscillation stabilization wait time*1
(LOCK UP time)
tLOCK
100
-
-
μs
PLL input clock frequency
PLL multiplication rate
fPLLI
-
fPLLO
fCLKSPLL
4
-
-
-
-
16
MHz
13
200
-
80
multiplier
MHz
PLL macro oscillation clock frequency
USB clock frequency*2
320
48
MHz
After the M frequency division
*1: Time from when the PLL starts operating until the oscillation stabilizes.
*2: For more information about USB clock, see CHAPTER 2-2: USB Clock Generation in FM4 Family Peripheral Manual
Communication Macro part (002-04862).
12.4.6 Operating Conditions of Main PLL (In the Case of Using Built-in High-Speed CR Clock for Input Clock of Main PLL)
(VCC = 2.7V to 5.5V, VSS = 0V)
Value
Parameter
Symbol
Unit
Remarks
Min
Typ
Max
PLL oscillation stabilization wait time*1
(LOCK UP time)
tLOCK
200
-
-
μs
PLL input clock frequency
fPLLI
-
fPLLO
fCLKPLL
3.8
50
190
-
4
-
4.2
75
MHz
PLL multiplication rate
multiplier
MHz
MHz
PLL macro oscillation clock frequency
Main PLL clock frequency*2
-
-
320
160
*1: Time from when the PLL starts operating until the oscillation stabilizes.
*2: For more information about Main PLL clock (CLKPLL), see CHAPTER 2-1: Clock in FM4 Family Peripheral Manual Main part
(002-04856).
Note:
−
Make sure to input to the main PLL source clock, the high-speed CR clock (CLKHC) that the frequency and temperature has
been trimmed.
Document Number: 002-04922 Rev.*B
Page 68 of 128
MB9B560L Series
12.4.7 Reset Input Characteristics
(VCC = 2.7V to 5.5V, VSS = 0V)
Value
Pin
Name
Parameter
Symbol
Condition
Unit
Remarks
Min
Max
Reset input time
tINITX
INITX
-
500
-
ns
12.4.8 Power-on Reset Timing
(VSS = 0V)
Remarks
*1
Value
Pin
Name
Parameter
Symbol
Conditions
Unit
ms
Min
Typ
Max
-
Power supply shut down time
Power ramp rate
tOFF
dV/dt
tPRT
-
50
1.3
-
-
-
VCC
VCC: 0.2V to 2.70V
-
1000
0.60
mV/µs *2
ms
Time until releasing Power-on reset
0.33
*1: VCC must be held below 0.2V for a minimum period of tOFF. Improper initialization may occur if this condition is not met.
*2: This dV/dt characteristic is applied at the power-on of cold start (tOFF>50ms).
Note:
−
tOFF must be satisfied. When tOFF cannot be satisfied, assert external reset (INITX) at power-up and at any brownout event.
Glossary
VDH: detection voltage of Low-Voltage detection reset. See 12.8 Low-Voltage Detection Characteristics.
Document Number: 002-04922 Rev.*B
Page 69 of 128
MB9B560L Series
12.4.9 GPIO Output Characteristics
(VCC = 2.7V to 5.5V, VSS = 0V)
Value
Parameter
Symbol
Pin Name
Conditions
Unit
Min
Max
VCC ≥ 4.5 V
VCC < 4.5 V
-
-
50
32
MHz
MHz
Output frequency
tPCYCLE
Pxx*
*: GPIO is a target.
Pxx
tPCYCLE
Document Number: 002-04922 Rev.*B
Page 70 of 128
MB9B560L Series
12.4.10 Base Timer Input Timing
Timer Input Timing
(VCC = 2.7V to 5.5V, VSS = 0V)
Value
Parameter
Symbol
Pin Name
Conditions
Unit
Remarks
Min
Max
TIOAn/TIOBn
(when using as
ECK, TIN)
tTIWH
tTIWL
,
Input pulse width
-
2tCYCP
-
ns
tTIWH
tTIWL
ECK
VIHS
VIHS
VILS
VILS
TIN
Trigger Input Timing
(VCC = 2.7V to 5.5V, VSS = 0V)
Value
Parameter
Symbol
Pin Name
Conditions
Unit
Remarks
Min
Max
TIOAn/TIOBn
(when using as
TGIN)
tTRGH
tTRGL
,
Input pulse width
-
2tCYCP
-
ns
tTRGH
tTRGL
VIHS
VIHS
TGIN
VILS
VILS
Note:
−
tCYCP indicates the APB bus clock cycle time.
About the APB bus number which the Base Timer is connected to, see 8. Block Diagram in this data sheet.
Document Number: 002-04922 Rev.*B
Page 71 of 128
MB9B560L Series
12.4.11 CSIO/UART Timing
Synchronous Serial (SPI = 0, SCINV = 0)
(VCC = 2.7V to 5.5V, VSS = 0V)
VCC < 4.5 V
Min Max
VCC ≥ 4.5 V
Pin
Name
Parameter
Symbol
Conditions
Unit
Min
Max
Baud rate
-
-
-
-
8
-
-
8
-
Mbps
ns
Serial clock cycle time
tSCYC
tSLOVI
SCKx
4tCYCP
4tCYCP
- 20
SCKx,
SOTx
SCKx,
SINx
SCKx,
SINx
SCKx
SCKx
SCKx,
SOTx
SCKx,
SINx
SCK↓→SOT delay time
- 30
50
0
+ 30
+ 20
ns
ns
ns
Internal shift
clock operation
SIN→SCK↑
setup time
tIVSHI
-
-
30
0
-
-
SCK↑→SIN hold time
tSHIXI
tSLSH
tSHSL
Serial clock "L" pulse width
Serial clock "H" pulse width
2tCYCP - 10
tCYCP + 10
-
-
2tCYCP - 10
tCYCP + 10
-
-
ns
ns
SCK↓→SOT delay time
tSLOVE
tIVSHE
tSHIXE
-
50
-
-
30
-
ns
ns
ns
External shift
clock
operation
SIN→SCK↑
setup time
10
20
10
20
SCKx,
SINx
SCK↑→SIN hold time
-
-
SCK falling time
SCK rising time
tF
tR
SCKx
SCKx
-
-
5
5
-
-
5
5
ns
ns
Notes:
−
The above characteristics apply to CLK synchronous mode.
−
tCYCP indicates the APB bus clock cycle time.
About the APB bus number which UART is connected to, see 8. Block Diagram in this data sheet.
−
−
These characteristics only guarantee the same relocate port number.
For example, the combination of SCKx_0 and SOTx_1 is not guaranteed.
When the external load capacitance CL = 30 pF.
Document Number: 002-04922 Rev.*B
Page 72 of 128
MB9B560L Series
tSCYC
VOH
SCK
VOL
VOL
tSLOVI
VOH
VOL
SOT
SIN
tIVSHI
VIH
VIL
tSHIXI
VIH
VIL
MS bit = 0
tSLSH
tSHSL
VIH
VIH
tR
VIH
VIL
VIL
SCK
F
t
tSLOVE
VOH
VOL
SOT
SIN
tIVSHE
VIH
VIL
tSHIXE
VIH
VIL
MS bit = 1
Document Number: 002-04922 Rev.*B
Page 73 of 128
MB9B560L Series
Synchronous Serial (SPI = 0, SCINV = 1)
Pin
(VCC = 2.7V to 5.5V, VSS = 0V)
VCC < 4.5 V
Min Max
VCC ≥ 4.5 V
Parameter
Symbol
Conditions
Unit
Name
Min
Max
Baud rate
-
-
-
-
8
-
-
8
Mbps
ns
Serial clock cycle time
tSCYC
SCKx
4tCYCP
- 30
4tCYCP
- 20
-
SCKx,
SOTx
SCK↑→SOT delay time
tSHOVI
+ 30
+ 20
ns
Internal shift
SIN→SCK↓
setup time
SCKx,
SINx
SCKx,
SINx
clock operation
tIVSLI
50
0
-
-
30
0
-
-
ns
ns
SCK↓→SIN hold time
tSLIXI
tSLSH
tSHSL
Serial clock "L" pulse width
Serial clock "H" pulse width
SCKx
SCKx
2tCYCP - 10
tCYCP + 10
-
-
2tCYCP - 10
tCYCP + 10
-
-
ns
ns
SCKx,
SOTx
SCKx,
SINx
SCKx,
SINx
SCK↑→SOT delay time
tSHOVE
tIVSLE
tSLIXE
-
50
-
-
30
-
ns
ns
ns
SIN→SCK↓
setup time
External shift
clock operation
10
20
10
20
SCK↓→SIN hold time
-
-
SCK falling time
SCK rising time
tF
SCKx
SCKx
-
-
5
5
-
-
5
5
ns
ns
tR
Notes:
−
The above characteristics apply to CLK synchronous mode.
−
tCYCP indicates the APB bus clock cycle time.
About the APB bus number which UART is connected to, see 8. Block Diagram in this data sheet.
−
−
These characteristics only guarantee the same relocate port number.
For example, the combination of SCKx_0 and SOTx_1 is not guaranteed.
When the external load capacitance CL = 30 pF.
Document Number: 002-04922 Rev.*B
Page 74 of 128
MB9B560L Series
tSCYC
VOH
VOH
SCK
VOL
tSHOVI
VOH
VOL
SOT
SIN
tIVSLI
VIH
VIL
tSLIXI
VIH
VIL
MS bit = 0
tSHSL
tSLSH
VIH
VIH
tF
VIL
VIL
tR
VIL
SCK
SOT
tSHOVE
VOH
VOL
tIVSLE
tSLIXE
VIH
VIL
VIH
VIL
SIN
MS bit = 1
Document Number: 002-04922 Rev.*B
Page 75 of 128
MB9B560L Series
Synchronous Serial (SPI = 1, SCINV = 0)
(VCC = 2.7V to 5.5V, VSS = 0V)
VCC < 4.5 V
Min Max
VCC ≥ 4.5 V
Pin
Name
Parameter
Symbol
Conditions
Unit
Min
Max
Baud rate
-
-
-
-
8
-
-
8
Mbps
ns
Serial clock cycle time
tSCYC
SCKx
4tCYCP
- 30
4tCYCP
- 20
-
SCKx,
SOTx
SCK↑→SOT delay time
tSHOVI
+ 30
+ 20
ns
Internal shift
clock
operation
SIN→SCK↓
setup time
SCKx,
SINx
SCKx,
SINx
SCKx,
SOTx
tIVSLI
tSLIXI
tSOVLI
50
-
-
-
30
-
-
-
ns
ns
ns
SCK↓→SIN hold time
0
0
SOT→SCK↓ delay time
2tCYCP - 30
2tCYCP - 30
Serial clock "L" pulse width
Serial clock "H" pulse width
tSLSH
tSHSL
SCKx
SCKx
2tCYCP - 10
tCYCP + 10
-
-
2tCYCP - 10
tCYCP + 10
-
-
ns
ns
SCKx,
SOTx
SCKx,
SINx
SCKx,
SINx
SCK↑→SOT delay time
tSHOVE
tIVSLE
tSLIXE
-
50
-
-
30
-
ns
ns
ns
External shift
clock
operation
SIN→SCK↓
setup time
10
20
10
20
SCK↓→SIN hold time
-
-
SCK falling time
SCK rising time
tF
SCKx
SCKx
-
-
5
5
-
-
5
5
ns
ns
tR
Notes:
−
The above characteristics apply to CLK synchronous mode.
−
tCYCP indicates the APB bus clock cycle time.
About the APB bus number which UART is connected to, see 8. Block Diagram in this data sheet.
−
−
These characteristics only guarantee the same relocate port number.
For example, the combination of SCKx_0 and SOTx_1 is not guaranteed.
When the external load capacitance CL = 30 pF.
Document Number: 002-04922 Rev.*B
Page 76 of 128
MB9B560L Series
tSCYC
VOH
VOL
VOL
SCK
SOT
tSHOVI
tSOVLI
VOH
VOL
VOH
VOL
tIVSLI
tSLIXI
VIH
VIL
VIH
VIL
SIN
MS bit = 0
tSLSH
tSHSL
VIH
tF
VIH
VIL
VIH
VIL
SCK
tSHOVE
tR
*
VOH
VOL
VOH
VOL
tIVSLE
tSLIXE
SOT
SIN
VIH
VIL
VIH
VIL
MS bit = 1
*: Changes when writing to TDR register
Document Number: 002-04922 Rev.*B
Page 77 of 128
MB9B560L Series
Synchronous Serial (SPI = 1, SCINV = 1)
(VCC = 2.7V to 5.5V, VSS = 0V)
VCC < 4.5 V
Min Max
VCC ≥ 4.5 V
Pin
Name
Parameter
Symbol
Conditions
Unit
Min
Max
Baud rate
-
-
-
-
8
-
8
Mbps
ns
Serial clock cycle time
tSCYC
tSLOVI
SCKx
4tCYCP
- 30
-
4tCYCP
- 20
-
SCKx,
SOTx
SCKx,
SINx
SCKx,
SINx
SCK↓→SOT delay time
+ 30
+ 20
ns
Internal shift
clock
operation
SIN→SCK↑
setup time
tIVSHI
tSHIXI
tSOVHI
50
-
-
-
30
-
-
-
ns
ns
ns
SCK↑→SIN hold time
SOT→SCK↑ delay time
0
0
SCKx,
SOTx
2tCYCP - 30
2tCYCP - 30
Serial clock "L" pulse width
Serial clock "H" pulse width
tSLSH
tSHSL
SCKx
SCKx
2tCYCP - 10
tCYCP + 10
-
-
2tCYCP - 10
tCYCP + 10
-
-
ns
ns
SCKx,
SOTx
SCKx,
SINx
SCKx,
SINx
SCK↓→SOT delay time
tSLOVE
tIVSHE
tSHIXE
-
50
-
-
30
-
ns
ns
ns
External shift
clock
operation
SIN→SCK↑
setup time
10
20
10
20
SCK↑→SIN hold time
-
-
SCK falling time
SCK rising time
tF
SCKx
SCKx
-
-
5
5
-
-
5
5
ns
ns
tR
Notes:
−
The above characteristics apply to CLK synchronous mode.
−
tCYCP indicates the APB bus clock cycle time.
About the APB bus number which UART is connected to, see 8. Block Diagram in this data sheet.
−
−
These characteristics only guarantee the same relocate port number.
For example, the combination of SCKx_0 and SOTx_1 is not guaranteed.
When the external load capacitance CL = 30 pF.
Document Number: 002-04922 Rev.*B
Page 78 of 128
MB9B560L Series
tSCYC
VOL
VOH
VOH
SCK
tSOVHI
tSLOVI
VOH
VOL
VOH
VOL
SOT
SIN
tSHIXI
tIVSHI
VIH
VIL
VIH
VIL
MS bit = 0
tSHSL
tSLSH
tR
tF
VIH
VIH
VIH
SCK
VIL
VIL
VIL
tSLOVE
VOH
VOL
VOH
VOL
SOT
SIN
tIVSHE
tSHIXE
VIH
VIL
VIH
VIL
MS bit = 1
Document Number: 002-04922 Rev.*B
Page 79 of 128
MB9B560L Series
High-Speed Synchronous Serial (SPI = 0, SCINV = 0)
Pin
(VCC = 2.7V to 5.5V, VSS = 0V)
VCC < 4.5V
Min
VCC ≥ 4.5V
Parameter
Serial clock cycle time
SCK↓→SOT delay time
Symbol
Conditions
Unit
Name
Max
Min
Max
tSCYC
SCKx
4tCYCP
-
4tCYCP
-
ns
ns
SCKx,
SOTx
tSLOVI
-10
+10
-
-10
+10
-
Internal shift
clock operation
14
SIN→SCK↑
setup time
SCKx,
SINx
tIVSHI
12.5
ns
12.5*
SCKx,
SINx
SCK↑→SIN hold time
tSHIXI
tSLSH
tSHSL
5
-
-
-
5
-
-
-
ns
ns
ns
Serial clock "L" pulse width
Serial clock "H" pulse width
SCKx
SCKx
2tCYCP – 5
tCYCP + 10
2tCYCP – 5
tCYCP + 10
SCKx,
SOTx
SCK↓→SOT delay time
tSLOVE
tIVSHE
tSHIXE
-
15
-
-
15
-
ns
ns
ns
External shift
clock operation
SIN→SCK↑
setup time
SCKx,
SINx
5
5
5
5
SCKx,
SINx
SCK↑→SIN hold time
-
-
SCK falling time
SCK rising time
tF
SCKx
SCKx
-
-
5
5
-
-
5
5
ns
ns
tR
Notes:
−
The above characteristics apply to CLK synchronous mode.
−
tCYCP indicates the APB bus clock cycle time.
About the APB bus number which UART is connected to, see 8. Block Diagram in this data sheet.
These characteristics only guarantee the following pins.
−
−
−
−
No chip select:
Chip select:
SIN0_1, SOT0_1, SCK0_1
SIN6_0, SOT6_0, SCK6_0, SCS6_0
When the external load capacitance CL = 30 pF. (For *, when CL = 10 pF)
Document Number: 002-04922 Rev.*B
Page 80 of 128
MB9B560L Series
tSCYC
VOH
SCK
VOL
VOL
tSLOVI
VOH
VOL
SOT
SIN
tIVSHI
VIH
VIL
tSHIXI
VIH
VIL
MS bit = 0
tSLSH
tSHSL
VIH
VIH
tR
VIH
SCK
VIL
VIL
F
t
tSLOVE
VOH
VOL
SOT
SIN
tIVSHE
VIH
VIL
tSHIXE
VIH
VIL
MS bit = 1
Document Number: 002-04922 Rev.*B
Page 81 of 128
MB9B560L Series
High-Speed Synchronous Serial (SPI = 0, SCINV = 1)
Pin
(VCC = 2.7V to 5.5V, VSS = 0V)
VCC < 4.5 V
Min Max
VCC ≥ 4.5 V
Parameter
Symbol
Conditions
Unit
Name
Min
Max
Serial clock cycle time
tSCYC
tSHOVI
tIVSLI
SCKx
4tCYCP
-
4tCYCP
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
SCKx,
SOTx
SCK↑→SOT delay time
-10
+10
-10
+10
Internal shift
clock operation
14
SIN→SCK↓
setup time
SCKx,
SINx
-
12.5
-
12.5*
SCKx,
SINx
SCK↓→SIN hold time
tSLIXI
5
-
5
-
Serial clock "L" pulse width
Serial clock "H" pulse width
SCK↑→SOT delay time
tSLSH
tSHSL
tSHOVE
tIVSLE
tSLIXE
SCKx
SCKx
2tCYCP – 5
-
2tCYCP – 5
-
tCYCP + 10
-
tCYCP + 10
-
SCKx,
SOTx
-
15
-
-
15
-
External shift
clock operation
SIN→SCK↓
setup time
SCKx,
SINx
5
5
5
5
SCKx,
SINx
SCK↓→SIN hold time
-
-
SCK falling time
SCK rising time
tF
SCKx
SCKx
-
-
5
5
-
-
5
5
ns
ns
tR
Notes:
−
The above characteristics apply to CLK synchronous mode.
−
tCYCP indicates the APB bus clock cycle time.
About the APB bus number which UART is connected to, see 8. Block Diagram in this data sheet.
These characteristics only guarantee the following pins.
−
−
−
−
No chip select:
Chip select:
SIN0_1, SOT0_1, SCK0_1
SIN6_0, SOT6_0, SCK6_0, SCS6_0
When the external load capacitance CL = 30 pF. (For *, when CL = 10 pF)
Document Number: 002-04922 Rev.*B
Page 82 of 128
MB9B560L Series
tSCYC
VOH
VOH
SCK
VOL
tSHOVI
VOH
VOL
SOT
SIN
tIVSLI
VIH
VIL
tSLIXI
VIH
VIL
MS bit = 0
tSHSL
tSLSH
VIH
VIH
tF
SCK
VIL
VIL
tR
VIL
tSHOVE
VOH
VOL
SOT
SIN
tIVSLE
tSLIXE
VIH
VIL
VIH
VIL
MS bit = 1
Document Number: 002-04922 Rev.*B
Page 83 of 128
MB9B560L Series
High-Speed Synchronous Serial (SPI = 1, SCINV = 0)
Pin
(VCC = 2.7V to 5.5V, VSS = 0V)
VCC < 4.5 V
Min Max
VCC ≥ 4.5 V
Parameter
Serial clock cycle time
SCK↑→SOT delay time
Symbol
Conditions
Unit
Name
Min
Max
tSCYC
tSHOVI
tIVSLI
SCKx
4tCYCP
-
4tCYCP
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SCKx,
SOTx
-10
+10
-10
+10
14
Internal shift
clock operation
SIN→SCK↓
setup time
SCKx,
SINx
-
12.5
-
12.5*
SCKx,
SINx
SCK↓→SIN hold time
tSLIXI
5
-
5
-
SCKx,
SOTx
SOT→SCK↓ delay time
Serial clock "L" pulse width
Serial clock "H" pulse width
SCK↑→SOT delay time
tSOVLI
tSLSH
tSHSL
tSHOVE
tIVSLE
tSLIXE
2tCYCP – 10
-
2tCYCP – 10
-
SCKx
SCKx
2tCYCP – 5
-
2tCYCP – 5
-
tCYCP + 10
-
tCYCP + 10
-
SCKx,
SOTx
-
15
-
-
15
-
External shift
clock operation
SIN→SCK↓
setup time
SCKx,
SINx
5
5
5
5
SCKx,
SINx
SCK↓→SIN hold time
-
-
SCK falling time
SCK rising time
tF
SCKx
SCKx
-
-
5
5
-
-
5
5
ns
ns
tR
Notes:
−
The above characteristics apply to CLK synchronous mode.
−
tCYCP indicates the APB bus clock cycle time.
About the APB bus number which UART is connected to, see 8. Block Diagram in this data sheet.
These characteristics only guarantee the following pins.
−
−
−
−
No chip select:
Chip select:
SIN0_1, SOT0_1, SCK0_1
SIN6_0, SOT6_0, SCK6_0, SCS6_0
When the external load capacitance CL = 30 pF. (For *, when CL = 10 pF)
Document Number: 002-04922 Rev.*B
Page 84 of 128
MB9B560L Series
tSCYC
VOH
VOL
VOL
SCK
SOT
SIN
tSHOVI
tSOVLI
VOH
VOL
VOH
VOL
tIVSLI
tSLIXI
VIH
VIL
VIH
VIL
MS bit = 0
tSLSH
tSHSL
VIH
tF
VIH
VIL
VIH
SCK
VIL
tSHOVE
tR
*
VOH
VOL
VOH
VOL
SOT
SIN
tIVSLE
tSLIXE
VIH
VIL
VIH
VIL
MS bit = 1
*: Changes when writing to TDR register
Document Number: 002-04922 Rev.*B
Page 85 of 128
MB9B560L Series
High-Speed Synchronous Serial (SPI = 1, SCINV = 1)
(VCC = 2.7V to 5.5V, VSS = 0V)
VCC < 4.5 V
Min
VCC ≥ 4.5 V
Parameter
Symbol Pin Name Conditions
Unit
Max
Min
Max
Internal shift clock operation
tSCYC
tSLOVI
tIVSHI
tSHIXI
tSOVHI
tSLSH
tSHSL
tSLOVE
tIVSHE
tSHIXE
SCKx
4tCYCP
-
4tCYCP
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SCKx,
SOTx
SCK↓→SOT delay time
-10
+10
-10
+10
Internal shift
clock
operation
14
SIN→SCK↑
setup time
SCKx,
SINx
-
12.5
-
12.5*
SCKx,
SINx
SCK↑→SIN hold time
5
-
5
-
SCKx,
SOTx
SOT→SCK↑ delay time
Serial clock "L" pulse width
Serial clock "H" pulse width
SCK↓→SOT delay time
2tCYCP – 10
-
2tCYCP – 10
-
SCKx
SCKx
2tCYCP – 5
-
2tCYCP – 5
-
tCYCP + 10
-
tCYCP + 10
-
SCKx,
SOTx
-
15
-
-
15
-
External shift
clock
operation
SIN→SCK↑
setup time
SCKx,
SINx
5
5
5
5
SCKx,
SINx
SCK↑→SIN hold time
-
-
SCK falling time
SCK rising time
tF
SCKx
SCKx
-
-
5
5
-
-
5
5
ns
ns
tR
Notes:
−
The above characteristics apply to CLK synchronous mode.
−
tCYCP indicates the APB bus clock cycle time.
About the APB bus number which UART is connected to, see 8. Block Diagram in this data sheet.
These characteristics only guarantee the following pins.
−
−
−
−
No chip select:
Chip select:
SIN0_1, SOT0_1, SCK0_1
SIN6_0, SOT6_0, SCK6_0, SCS6_0
When the external load capacitance CL = 30 pF. (For *, when CL = 10 pF)
Document Number: 002-04922 Rev.*B
Page 86 of 128
MB9B560L Series
tSCYC
VOL
VOH
VOH
SCK
tSOVHI
tSLOVI
VOH
VOL
VOH
VOL
SOT
SIN
tSHIXI
tIVSHI
VIH
VIL
VIH
VIL
MS bit = 0
tSHSL
tSLSH
tR
tF
VIH
VIH
VIH
SCK
VIL
VIL
VIL
tSLOVE
VOH
VOL
VOH
VOL
SOT
SIN
tIVSHE
tSHIXE
VIH
VIL
VIH
VIL
MS bit = 1
Document Number: 002-04922 Rev.*B
Page 87 of 128
MB9B560L Series
When Using High-Speed Synchronous Serial Chip Select (SCINV = 0, CSLVL=1)
VCC < 4.5 V
(VCC = 2.7V to 5.5V, VSS = 0V)
VCC ≥ 4.5 V
Parameter
Symbol
Conditions
Unit
Min
Max
Min
Max
SCS↓→SCK↓setup time
SCK↑→SCS↑ hold time
SCS deselect time
tCSSI
tCSHI
tCSDI
tCSSE
tCSHE
tCSDE
tDSE
(*1)-20
(*1)+0
(*1)-20
(*1)+0
ns
ns
ns
ns
ns
ns
ns
ns
Internal shift
clock operation
(*2)+0
(*2)+20
(*2)+0
(*2)+20
(*3)-20+5tCYCP
(*3)+20+5tCYCP
(*3)-20+5tCYCP
(*3)+20+5tCYCP
SCS↓→SCK↓setup time
SCK↑→SCS↑ hold time
SCS deselect time
3tCYCP+15
-
3tCYCP+15
-
0
-
0
-
External shift
clock operation
3tCYCP+15
-
3tCYCP+15
-
SCS↓→SOT delay time
SCS↑→SOT delay time
-
25
-
-
25
-
tDEE
0
0
(*1): CSSU bit value×serial chip select timing operating clock cycle [ns]
(*2): CSHD bit value×serial chip select timing operating clock cycle [ns]
(*3): CSDS bit value×serial chip select timing operating clock cycle [ns]
Notes:
−
tCYCP indicates the APB bus clock cycle time.
About the APB bus number which UART is connected to, see 8. Block Diagram in this data sheet.
−
−
About CSSU, CSHD, CSDS, serial chip select timing operating clock, see FM4 Family Peripheral Manual.
When the external load capacitance CL = 30 pF.
Document Number: 002-04922 Rev.*B
Page 88 of 128
MB9B560L Series
SCS
output
t
CSDI
t
CSHI
t
CSSI
SCK
output
SOT
(SPI=0)
SOT
(SPI=1)
MS bit = 0
SCS
input
tCSDE
tCSHE
t
CSSE
SCK
input
t
DEE
SOT
(SPI=0)
tDSE
SOT
(SPI=1)
MS bit = 1
Document Number: 002-04922 Rev.*B
Page 89 of 128
MB9B560L Series
When Using High-Speed Synchronous Serial Chip Select (SCINV = 1, CSLVL=1)
VCC < 4.5 V
(VCC = 2.7V to 5.5V, VSS = 0V)
VCC ≥ 4.5 V
Parameter
Symbol Conditions
Unit
Min
Max
Min
Max
SCS↓→SCK↑setup time
SCK↓→SCS↑ hold time
SCS deselect time
tCSSI
(*1)-20
(*1)+0
(*2)+20
(*1)-20
(*2)+0
(*1)+0
ns
ns
ns
ns
ns
ns
ns
ns
Internal shift
clock
operation
tCSHI
tCSDI
tCSSE
tCSHE
tCSDE
tDSE
(*2)+0
(*2)+20
(*3)-20+5tCYCP
(*3)+20+5tCYCP (*3)-20+5tCYCP
(*3)+20+5tCYCP
SCS↓→SCK↑setup time
SCK↓→SCS↑ hold time
SCS deselect time
3tCYCP+15
-
3tCYCP+15
-
0
-
0
-
External shift
clock
operation
3tCYCP+15
-
3tCYCP+15
-
SCS↓→SOT delay time
SCS↑→SOT delay time
-
25
-
-
25
-
tDEE
0
0
(*1): CSSU bit value×serial chip select timing operating clock cycle [ns]
(*2): CSHD bit value×serial chip select timing operating clock cycle [ns]
(*3): CSDS bit value×serial chip select timing operating clock cycle [ns]
Notes:
−
−
−
tCYCP indicates the APB bus clock cycle time.
About the APB bus number which UART is connected to, see 8. Block Diagram in this data sheet.
About CSSU, CSHD, CSDS, serial chip select timing operating clock, see FM4 Family Peripheral Manual Main part
(002-04856).
When the external load capacitance CL = 30 pF.
Document Number: 002-04922 Rev.*B
Page 90 of 128
MB9B560L Series
SCS
output
t
CSDI
t
CSHI
t
CSSI
SCK
output
SOT
(SPI=0)
SOT
(SPI=1)
MS bit = 0
SCS
input
tCSDE
t
CSHE
tCSSE
SCK
input
tDEE
SOT
(SPI=0)
tDSE
SOT
(SPI=1)
MS bit = 1
Document Number: 002-04922 Rev.*B
Page 91 of 128
MB9B560L Series
When Using High-Speed Synchronous Serial Chip Select (SCINV = 0, CSLVL=0)
VCC < 4.5 V
(VCC = 2.7V to 5.5V, VSS = 0V)
VCC ≥ 4.5 V
Parameter
Symbol
Conditions
Unit
Min
Max
Min
Max
SCS↑→SCK↓setup time
SCK↑→SCS↓ hold time
SCS deselect time
tCSSI
tCSHI
tCSDI
tCSSE
tCSHE
tCSDE
tDSE
(*1)-20
(*1)+0
(*1)-20
(*1)+0
ns
ns
ns
ns
ns
ns
ns
ns
Internal shift
clock
operation
(*2)+0
(*2)+20
(*2)+0
(*2)+20
(*3)-20+5tCYCP
(*3)+20+5tCYCP
(*3)-20+5tCYCP
(*3)+20+5tCYCP
SCS↑→SCK↓setup time
SCK↑→SCS↓ hold time
SCS deselect time
3tCYCP+15
-
3tCYCP+15
-
0
-
0
-
External shift
clock
operation
3tCYCP+15
-
3tCYCP+15
-
SCS↑→SOT delay time
SCS↓→SOT delay time
-
25
-
-
25
-
tDEE
0
0
(*1): CSSU bit value×serial chip select timing operating clock cycle [ns]
(*2): CSHD bit value×serial chip select timing operating clock cycle [ns]
(*3): CSDS bit value×serial chip select timing operating clock cycle [ns]
Notes:
−
−
−
tCYCP indicates the APB bus clock cycle time.
About the APB bus number which UART is connected to, see 8. Block Diagram in this data sheet.
About CSSU, CSHD, CSDS, serial chip select timing operating clock, see FM4 Family Peripheral Manual Main part
(002-04856).
When the external load capacitance CL = 30 pF.
Document Number: 002-04922 Rev.*B
Page 92 of 128
MB9B560L Series
t
CSDI
SCS
output
t
CSHI
t
CSSI
SCK
output
SOT
(SPI=0)
SOT
(SPI=1)
MS bit = 0
t
CSDE
SCS
input
t
CSHE
t
CSSE
SCK
input
t
DEE
SOT
(SPI=0)
t
DSE
SOT
(SPI=1)
MS bit = 1
Document Number: 002-04922 Rev.*B
Page 93 of 128
MB9B560L Series
When Using High-Speed Synchronous Serial Chip Select (SCINV = 1, CSLVL=0)
VCC < 4.5 V
(VCC = 2.7V to 5.5V, VSS = 0V)
VCC ≥ 4.5 V
Parameter
Symbol
Conditions
Unit
Min
Max
Min
Max
SCS↑→SCK↑setup time
SCK↓→SCS↓ hold time
SCS deselect time
tCSSI
tCSHI
tCSDI
tCSSE
tCSHE
tCSDE
tDSE
(*1)-20
(*1)+0
(*1)-20
(*1)+0
ns
ns
ns
ns
ns
ns
ns
ns
Internal shift
clock
operation
(*2)+0
(*2)+20
(*2)+0
(*2)+20
(*3)-20+5tCYCP
(*3)+20+5tCYCP
(*3)-20+5tCYCP
(*3)+20+5tCYCP
SCS↑→SCK↑setup time
SCK↓→SCS↓ hold time
SCS deselect time
3tCYCP+15
-
3tCYCP+15
-
0
-
0
-
External shift
clock
operation
3tCYCP+15
-
3tCYCP+15
-
SCS↑→SOT delay time
SCS↓→SOT delay time
-
25
-
-
25
-
tDEE
0
0
(*1): CSSU bit value×serial chip select timing operating clock cycle [ns]
(*2): CSHD bit value×serial chip select timing operating clock cycle [ns]
(*3): CSDS bit value×serial chip select timing operating clock cycle [ns]
Notes:
−
−
−
tCYCP indicates the APB bus clock cycle time.
About the APB bus number which UART is connected to, see 8. Block Diagram in this data sheet.
About CSSU, CSHD, CSDS, serial chip select timing operating clock, see FM4 Family Peripheral Manual Main part
(002-04856).
When the external load capacitance CL = 30 pF.
Document Number: 002-04922 Rev.*B
Page 94 of 128
MB9B560L Series
t
CSDI
SCS
output
t
CSHI
t
CSSI
SCK
output
SOT
(SPI=0)
SOT
(SPI=1)
MS bit = 0
SCS
input
t
CSDE
t
CSHE
t
CSSE
SCK
input
t
DEE
SOT
(SPI=0)
t
DSE
SOT
(SPI=1)
MS bit = 1
Document Number: 002-04922 Rev.*B
Page 95 of 128
MB9B560L Series
External Clock (EXT = 1): when in Asynchronous Mode Only
(VCC = 2.7V to 5.5V, VSS = 0V)
Value
Parameter
Symbol
Condition
Unit
Remarks
Min
Max
Serial clock "L" pulse width
Serial clock "H" pulse width
SCK falling time
tSLSH
tSHSL
tF
tCYCP + 10
tCYCP + 10
-
-
-
-
5
5
ns
ns
ns
ns
CL = 30 pF
SCK rising time
tR
tR
tF
VIH
tSHSL
tSLSH
SCK
VIH
VIH
VIL
VIL
VIL
Document Number: 002-04922 Rev.*B
Page 96 of 128
MB9B560L Series
12.4.12 External Input Timing
(VCC = 2.7V to 5.5V, VSS = 0V)
Value
Parameter
Symbol
Pin Name
Conditions
Unit
Remarks
Min
Max
ADTG
A/D converter trigger input
1
-
2tCYCP
*
-
ns
FRCKx
ICxx
Free-run timer input clock
Input capture
Input pulse
width
tINH
tINL
,
1
DTTIxX
INT00 to INT31,
NMIX
-
-
-
2tCYCP
*
-
-
-
-
ns
ns
ns
ns
Waveform generator
External interrupt,
NMI
2tCYCP + 100*1
500*2
WKUPx
500*3
Deep standby wake up
*1: tCYCP indicates the APB bus clock cycle time except stop when in Stop mode, in timer mode.
About the APB bus number which the A/D converter, multi-function timer, external interrupt are connected to, see 8. Block
Diagram in this data sheet.
*2: When in Stop mode, in timer mode.
*3: When in deep standby RTC mode, in Deep Standby Stop mode.
tINH
tINL
VIHS
VIHS
VILS
VILS
Document Number: 002-04922 Rev.*B
Page 97 of 128
MB9B560L Series
12.4.13 Quadrature Position/Revolution Counter Timing
(VCC = 2.7V to 5.5V, VSS = 0V)
Value
Unit
Parameter
Symbol
Conditions
Min
Max
AIN pin H width
AIN pin L width
BIN pin H width
BIN pin L width
tAHL
-
-
-
-
tALL
tBHL
tBLL
BIN rising time from
AIN pin H level
AIN falling time from
BIN pin H level
BIN falling time from
AIN pin L level
AIN rising time from
BIN pin L level
AIN rising time from
BIN pin H level
BIN falling time from
AIN pin H level
AIN falling time from
BIN pin L level
BIN rising time from
AIN pin L level
tAUBU
tBUAD
tADBD
tBDAU
tBUAU
tAUBD
tBDAD
tADBU
PC_Mode2 or PC_Mode3
PC_Mode2 or PC_Mode3
PC_Mode2 or PC_Mode3
PC_Mode2 or PC_Mode3
PC_Mode2 or PC_Mode3
PC_Mode2 or PC_Mode3
PC_Mode2 or PC_Mode3
PC_Mode2 or PC_Mode3
2tCYCP
*
-
ns
ZIN pin H width
ZIN pin L width
tZHL
tZLL
QCR:CGSC = 0
QCR:CGSC = 0
AIN/BIN rising and falling time from
determined ZIN level
Determined ZIN level from AIN/BIN rising
and falling time
tZABE
tABEZ
QCR:CGSC = 1
QCR:CGSC = 1
*: tCYCP indicates the APB bus clock cycle time except stop when in Stop mode, in timer mode.
About the APB bus number which Quadrature Position/Revolution Counter is connected to, see 8. Block Diagram in this data
sheet.
t
ALL
t
AHL
AIN
BIN
t
ADBD
t
AUBU
t
BUAD
tBDAU
t
BHL
tBLL
Document Number: 002-04922 Rev.*B
Page 98 of 128
MB9B560L Series
t
BLL
t
BHL
BIN
AIN
t
BDAD
t
BUAU
t
AUBD
t
ADBU
t
AHL
tALL
tZHL
ZIN
tZLL
ZIN
tABEZ
tZABE
AIN/BIN
Document Number: 002-04922 Rev.*B
Page 99 of 128
MB9B560L Series
12.4.14 I2C Timing
Standard-Mode, Fast-Mode
(VCC = 2.7V to 5.5V, VSS = 0V)
Standard-Mode
Min Max
Fast-Mode
Min Max
Parameter
Symbol
Conditions
Unit
Remarks
SCL clock frequency
(Repeated) START condition
hold time
FSCL
0
100
0
400
kHz
tHDSTA
4.0
-
0.6
-
μs
SDA ↓ → SCL ↓
SCL clock "L" width
SCL clock "H" width
tLOW
tHIGH
4.7
4.0
-
-
1.3
0.6
-
-
μs
μs
(Repeated) START condition
setup time
SCL ↑ → SDA ↓
Data hold time
SCL ↓ → SDA ↓ ↑
Data setup time
SDA ↓ ↑ → SCL ↑
STOP condition setup time
SCL ↑ → SDA ↑
tSUSTA
4.7
0
-
0.6
-
μs
CL = 30 pF,
R = (Vp/IOL)*1
tHDDAT
tSUDAT
tSUSTO
3.45*2
0
0.9*3
μs
ns
μs
250
4.0
-
-
100
0.6
-
-
Bus free time between
"STOP condition" and
"START condition"
tBUF
4.7
-
1.3
-
μs
2 MHz ≤
tCYCP<40 MHz
40 MHz ≤
tCYCP<60 MHz
60 MHz ≤
tCYCP<80 MHz
80 MHz ≤
tCYCP<100 MHz
100 MHz ≤
tCYCP<120 MHz
120 MHz ≤
tCYCP<140 MHz
140 MHz ≤
tCYCP<160 MHz
160 MHz ≤
4
4
4
4
4
4
2tCYCP
*
*
-
-
-
-
-
-
-
-
2tCYCP
4tCYCP
6tCYCP
8tCYCP
*
*
*
*
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
4tCYCP
6tCYCP*4
4
8tCYCP
*
Noise filter
tSP
*5
4
4
4
4
4
4
4
4
10tCYCP
12tCYCP
14tCYCP
16tCYCP
*
*
*
*
10tCYCP
12tCYCP
14tCYCP
16tCYCP
*
*
*
*
tCYCP<180 MHz
*1: R and CL represent the pull-up resistance and load capacitance of the SCL and SDA lines, respectively. Vp indicates the power
supply voltage of the pull-up resistance and IOL indicates VOL guaranteed current.
*2: The maximum tHDDAT must satisfy that it does not extend at least "L" period (tLOW) of device's SCL signal.
*3: A Fast-mode I2C bus device can be used on a Standard-mode I2C bus system as long as the device satisfies the requirement of
t
SUDAT ≥ 250 ns.
*4: tCYCP is the APB bus clock cycle time.
About the APB bus number that I2C is connected to, see "8. Block Diagram" in this data sheet.
*5: The noise filter time can be changed by register settings.
Change the number of the noise filter steps according to APB bus clock frequency.
Document Number: 002-04922 Rev.*B
Page 100 of 128
MB9B560L Series
Fast Mode Plus (Fm+)
Parameter
(VCC = 2.7V to 5.5V, VSS = 0V)
Fast Mode Plus
(Fm+)*6
Symbol
Conditions
Unit
Remarks
Min
Max
SCL clock frequency
(Repeated) START condition hold time
SDA ↓ → SCL ↓
FSCL
0
1000
kHz
tHDSTA
0.26
-
μs
SCL clock "L" width
SCL clock "H" width
SCL clock frequency
(Repeated) START condition hold time
SDA ↓ → SCL ↓
Data setup time
SDA ↓ ↑ → SCL ↑
STOP condition setup time
SCL ↑ → SDA ↑
tLOW
tHIGH
tSUSTA
0.5
0.26
0.26
-
-
-
μs
μs
μs
0.45*2, *3
μs
ns
μs
CL = 30 pF,
tHDDAT
tSUDAT
tSUSTO
0
R = (Vp/IOL)*1
50
0.26
-
-
Bus free time between
"STOP condition" and
"START condition"
tBUF
0.5
-
μs
60 MHz ≤
tCYCP<80 MHz
80 MHz ≤
tCYCP<100 MHz
100 MHz ≤
tCYCP<120 MHz
120 MHz ≤
tCYCP<140 MHz
140 MHz ≤
tCYCP<160 MHz
160 MHz ≤
4
4
6 tCYCP
*
*
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
8 tCYCP
4
4
4
4
10 tCYCP
12 tCYCP
14 tCYCP
16 tCYCP
*
*
*
*
Noise filter
tSP
*5
tCYCP<180 MHz
*1: R and CL represent the pull-up resistance and load capacitance of the SCL and SDA lines, respectively. Vp indicates the power
supply voltage of the pull-up resistance and IOL indicates VOL guaranteed current.
*2: The maximum tHDDAT must satisfy that it does not extend at least L period (tLOW) of device's SCL signal.
*3: A Fast-mode I2C bus device can be used on a Standard-mode I2C bus system as long as the device satisfies the requirement of
"tSUDAT ≥ 250 ns".
*4: tCYCP is the APB bus clock cycle time.
About the APB bus number that I2C is connected to, see 8. Block Diagram in this data sheet.
To use fast mode plus (Fm+), set the peripheral bus clock at 64 MHz or more.
*5: The noise filter time can be changed by register settings.
Change the number of the noise filter steps according to APB bus clock frequency.
*6: When using fast mode plus (Fm+), set the I/O pin to the mode corresponding to I2C Fm+ in the EPFR register. See CHAPTER
12: I/O Port in FM4 Family Peripheral Manual Main part (002-04856) for the details.
tSUSTA
tSUDAT
SDA
SCL
tBUF
tLOW
tHDSTA
tHDDAT
tHIGH
tHDSTA
tSP
tSUSTO
Document Number: 002-04922 Rev.*B
Page 101 of 128
MB9B560L Series
12.4.15 JTAG Timing
(VCC = 2.7V to 5.5V, VSS = 0V)
Value
Parameter
Symbol
Pin Name
Conditions
Unit
Remarks
Min
Max
VCC ≥ 4.5 V
TCK,
TMS, TDI
TMS, TDI setup time
tJTAGS
15
15
-
-
ns
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
VCC ≥ 4.5 V
VCC < 4.5 V
TCK,
TMS, TDI
TMS, TDI hold time
TDO delay time
tJTAGH
tJTAGD
ns
ns
-
-
25
45
TCK,
TDO
Note:
−
When the external load capacitance CL= 30 pF.
VOH
TCK
VOL
tJTAGS
tJTAGH
VOH
VOL
VOH
VOL
TMS/TDI
tJTAGD
VOH
VOL
TDO
Document Number: 002-04922 Rev.*B
Page 102 of 128
MB9B560L Series
12.5 12-bit A/D Converter
Electrical Characteristics for the A/D Converter
(VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = AVRL = 0V)
Value
Typ
Parameter
Symbol
Pin Name
Unit
Remarks
Min
Max
Resolution
Integral Nonlinearity
Differential Nonlinearity
Zero transition voltage
Full-scale transition voltage
-
-
-
-
-
-
-
-
-
-
-
-
12
+4.5
+2.5
+15
bit
-4.5
-2.5
-15
AVRH - 15
0.5*1
LSB
LSB
mV
AVRH =
2.7 V to 5.5 V
VZT
VFST
AN00 to AN14
AN00 to AN14
AVRH + 15
mV
Conversion time
-
-
-
-
-
-
-
-
μs
AVCC ≥ 4.5V
AVCC ≥ 4.5V
AVCC < 4.5V
AVCC ≥ 4.5V
AVCC < 4.5V
*2
*2
25
50
Sampling time
Ts
-
10
μs
1000
1000
Compare clock cycle*3
Tcck
-
ns
State transition time to
operation permission
Tstt
-
-
-
-
1.0
μs
-
-
0.69
0.3
0.92
12
mA
μA
A/D 1 unit operation
When A/D stop
Power supply current (analog
+ digital)
AVCC
A/D 1unit operation
AVRH=5.5 V
Reference power supply
current
(AVRH)
1.1
0.2
1.97
4.2
mA
-
AVRH
-
μA
When A/D stop
Analog input capacity
Analog input resistance
CAIN
RAIN
-
-
-
-
-
-
10
pF
1.2
1.8
4
AVCC ≥ 4.5 V
kΩ
AVCC < 4.5 V
Interchannel disparity
-
-
-
-
-
-
-
-
LSB
μA
V
Analog port input leak current
Analog input voltage
AN00 to AN14
AN00 to AN14
5
AVSS
4.5
2.7
-
-
-
AVRH
AVCC
AVCC
Tcck < 50 ns
Tcck ≥ 50 ns
Reference voltage
-
AVRH
V
*1: The conversion time is the value of sampling time (Ts) + compare time (Tc).
The condition of the minimum conversion time is when the value of sampling time: 150 ns, the value of compare time: 350 ns
(AVCC ≥ 4.5 V). Ensure that it satisfies the value of sampling time (Ts) and compare clock cycle (Tcck). For setting*4 of sampling
time and compare clock cycle, see CHAPTER 1-1: A/D Converter in FM4 Family Peripheral Manual Analog macro part
(002-04860). The register setting of the A/D Converter is reflected by the peripheral clock timing. The sampling and compare
clock are set at Base clock (HCLK).
*2: A necessary sampling time changes by external impedance. Ensure that it set the sampling time to satisfy (Equation 1).
*3: The compare time (Tc) is the value of (Equation 2).
*4: The register setting of the A/D Converter is reflected by the timing of the APB bus clock. The sampling clock and compare clock
are set in base clock (HCLK). About the APB bus number which the A/D Converter is connected to, see 8. Block Diagram in this
data sheet.
Document Number: 002-04922 Rev.*B
Page 103 of 128
MB9B560L Series
Comparator
AN00 to AN14
Rext
RAIN
Analog input pin
Analog signal
source
CAIN
(Equation 1) Ts ≥ (RAIN + Rext ) × CAIN × 9
Ts:
Sampling time
RAIN
:
Input resistance of A/D = 1.2 kΩ at 4.5 V < AVCC < 5.5 V
Input resistance of A/D = 1.8 kΩ at 2.7 V < AVCC < 4.5 V
Input capacity of A/D = 10 pF at 2.7 V < AVCC < 5.5 V
CAIN
:
Rext: Output impedance of external circuit
(Equation 2) Tc = Tcck × 14
Tc:
Compare time
Tcck: Compare clock cycle
Document Number: 002-04922 Rev.*B
Page 104 of 128
MB9B560L Series
Definition of 12-bit A/D Converter Terms
• Resolution:
Analog variation that is recognized by an A/D converter.
• Integral Nonlinearity:
Deviation of the line between the zero-transition point (0b000000000000 ←→ 0b000000000001)
and the full-scale transition point (0b111111111110 ←→ 0b111111111111) from the actual conversion
characteristics.
• Differential Nonlinearity: Deviation from the ideal value of the input voltage that is required to change the output code by
1 LSB.
Integral Nonlinearity
Differential Nonlinearity
0xFFF
Actual conversion
Actual conversion
characteristics
0xFFE
0xFFD
0x(N+1)
0xN
characteristics
{1 LSB(N-1) + VZT}
VFST
Ideal characteristics
(Actually-
measured
value)
VNT
0x004
(Actual
value)
V(N+1)T
(Actually-measured
value)
0x(N-1)
0x(N-2)
0x003
0x002
Actual conversion
characteristics
VNT
(Asured
value)
Ideal characteristics
0x001
ly-measured value)
Analog input
VZT
Actual conversion characteristics
AVss
AVRH
AVss
AVRH
Analog input
VNT - {1LSB × (N - 1) + VZT}
1LSB
Integral Nonlinearity of digital output N =
Differential Nonlinearity of digital output N =
[LSB]
V(N + 1) T - VNT
- 1 [LSB]
1LSB
VFST - VZT
1LSB =
4094
N:
A/D converter digital output value.
Voltage at which the digital output changes from 0x000 to 0x001.
VZT:
VFST
:
Voltage at which the digital output changes from 0xFFE to 0xFFF.
VNT
:
Voltage at which the digital output changes from 0x(N − 1) to 0xN.
Document Number: 002-04922 Rev.*B
Page 105 of 128
MB9B560L Series
12.6 12-bit D/A Converter
Electrical Characteristics for the D/A Converter
(VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = 0V)
Value
Typ
Parameter
Symbol Pin Name
Unit
Remarks
Min
Max
Resolution
-
-
-
12
bit
tc20
tc100
INL
0.56
2.79
-16
-0.98
-
-20.0
3.10
2.0
260
400
0.69
3.42
-
-
-
-
3.80
-
330
519
0.81
4.06
+16
+1.5
10.0
+1.4
4.50
-
μs
μs
Load 20pF
Load 100pF
Conversion time
Integral Nonlinearity*
Differential Nonlinearity*
LSB
LSB
mV
mV
kΩ
MΩ
μA
μA
DNL
DAx
When setting 0x000
When setting 0xFFF
D/A operation
When D/A stop
D/A 1unit operation AVCC=3.3 V
D/A 1unit operation AVCC=5.0 V
Output voltage offset
VOFF
Analog output impedance
RO
410
620
IDDA
IDSA
Power supply current*
*: During no load
AVCC
-
-
14
μA
When D/A stop
Document Number: 002-04922 Rev.*B
Page 106 of 128
MB9B560L Series
12.7 USB Characteristics
(VCC = 2.7V to 5.5V, USBVCC = 3.0V to 3.6V, VSS = 0V)
Value
Parameter
Symbol
Pin Name
Conditions
Unit Remarks
Min
Max
USBVCC + 0.3
0.8
Input H level voltage
VIH
VIL
-
-
2.0
V
V
*1
*1
Input L level voltage
Input
VSS - 0.3
0.2
character
-istics
Differential input
sensitivity
Different common mode
range
VDI
-
-
-
V
V
V
V
*2
*2
*3
*3
VCM
VOH
VOL
0.8
2.8
0.0
2.5
3.6
0.3
External pull-down
resistance = 15 kΩ
External pull-up
resistance = 1.5 kΩ
-
Output "H" level voltage
Output "L" level voltage
UDP0,UDM0
Crossover voltage
Rising time
VCRS
tFR
1.3
4
2.0
20
20
V
ns
ns
*4
*5
*5
Full-Speed
Output
character
-istics
Falling time
tFF
Full-Speed
4
Rising/falling time
matching
tFRFM
Full-Speed
90
111.11
%
*5
Output impedance
Rising time
Falling time
ZDRV
tLR
tLF
Full-Speed
Low-Speed
Low-Speed
28
75
75
44
300
300
Ω
ns
ns
*6
*7
*7
Rising/falling time
matching
tLRFM
Low-Speed
80
125
%
*7
*1: The switching threshold voltage of Single-End-Receiver of USB I/O buffer is set as within VIL (Max) = 0.8 V, VIH (Min) = 2.0 V
(TTL input standard).
There are some hysteresises to lower noise sensitivity.
*2: Use differential-Receiver to receive USB differential data signal.
Differential-Receiver has 200 mV of differential input sensitivity when the differential data input is within 0.8 V to 2.5 V to the local
ground reference level.
Above voltage range is the common mode input voltage range.
1.0
0.2
0.8
2.5
Common mode input voltage [V]
Document Number: 002-04922 Rev.*B
Page 107 of 128
MB9B560L Series
*3: The output drive capability of the driver is below 0.3 V at Low-State (VOL) (to 3.6 V and 1.5 kΩ load), and 2.8 V or above (to the
V
SS and 1.5 kΩ load) at High-State (VOH).
*4: The cross voltage of the external differential output signal (D + /D −) of USB I/O buffer is within 1.3 V to 2.0 V.
D+
Max 2.0V
VCRS specified range
Min 1.3V
D-
*5: They indicate rising time (Trise) and falling time (Tfall) of the full-speed differential data signal.
They are defined by the time between 10% and 90% of the output signal voltage.
For full-speed buffer, Tr/Tf ratio is regulated as within ± 10% to minimize RFI emission.
D+
90%
90%
10%
10%
D-
Trise
Tfall
Falling time
Rising time
Full-speed Buffer
Rs=27Ω
TxD+
CL=50pF
CL=50pF
Rs=27Ω
TxD-
3-State Enable
Document Number: 002-04922 Rev.*B
Page 108 of 128
MB9B560L Series
*6: USB Full-speed connection is performed via twist pair cable shield with 90 Ω ± 15% characteristic impedance (Differential Mode).
USB standard defines that output impedance of USB driver must be in range from 28 Ω to 44 Ω. So, discrete series resistor (Rs)
addition is defined in order to satisfy the above definition and keep balance.
When using this USB I/O, use it with 25 Ω to 30 Ω (recommendation value 27 Ω) Series resistor Rs.
Full-speed Buffer
Rs
TxD+
28Ω to 44Ω Equiv. Imped.
Rs
TxD-
28Ω to 44Ω Equiv. Imped.
3-State Enable
Mount it as external resistance.
Rs series resistor 25 Ω to 30 Ω
Series resistor of 27 Ω (recommendation value) must be added.
And, use "resistance with an uncertainty of 5% by E24 sequence".
*7: They indicate rising time (Trise) and falling time (Tfall) of the low-speed differential data signal.
They are defined by the time between 10% and 90% of the output signal voltage.
D+
90%
90%
10%
10%
D-
Trise
Rising time
Tfall
Falling time
See Low-Speed Load (Compliance Load) for conditions of external load.
Document Number: 002-04922 Rev.*B
Page 109 of 128
MB9B560L Series
Low-Speed Load (Upstream Port Load) - Reference 1
Low-speed Buffer
Rs=27Ω
TxD+
Rpd
Rs=27Ω
Rpd
CL = 50pF to 150pF
TxD-
CL = 50pF to 150pF
3-State Enable
Rpd=15kΩ
Low-Speed Load (Downstream Port Load) - Reference 2
Low-speed Buffer
Rs=27Ω
TxD+
VTERM
CL =200pF to
600pF
Rpu
Rs=27Ω
TxD-
CL =200pF to
600pF
Rpu=1.5kΩ
VTERM=3.6V
3-State Enable
Low-Speed Load (Compliance Load)
Low-speed Buffer
Rs=27Ω
Rs=27Ω
TxD+
TxD-
CL = 200pF to 450pF
CL = 200pF to 450pF
3-State Enable
Document Number: 002-04922 Rev.*B
Page 110 of 128
MB9B560L Series
12.8 Low-Voltage Detection Characteristics
12.8.1 Low-Voltage Detection Reset
Value
Typ
Parameter
Symbol
Conditions
Unit
Remarks
Min
Max
Detected voltage
Released voltage
VDL
VDH
-
-
2.25
2.30
2.45
2.50
2.65
2.70
V
V
When voltage drops
When voltage rises
12.8.2 Interrupt of Low-Voltage Detection
Value
Typ
Parameter
Symbol
Conditions
Unit
Remarks
Min
Max
Detected voltage
Released voltage
VDL
2.58
2.67
2.8
3.02
3.13
V
V
When voltage drops
When voltage rises
SVHI = 00111
SVHI = 00100
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
VDL
VDH
2.9
3.0
3.1
3.2
3.3
3.6
3.7
3.7
3.8
4.0
4.1
4.1
4.2
4.2
4.3
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
Detected voltage
Released voltage
2.76
2.85
2.94
3.04
3.31
3.40
3.40
3.50
3.68
3.77
3.77
3.86
3.86
3.96
3.24
3.34
3.45
3.56
3.88
3.99
3.99
4.10
4.32
4.42
4.42
4.53
4.53
4.64
V
V
V
V
V
V
V
V
V
V
V
V
V
V
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
SVHI = 01100
SVHI = 01111
SVHI = 01110
SVHI = 01001
SVHI = 01000
SVHI = 11000
4480×
LVD stabilization wait time
TLVDW
-
-
-
μs
tCYCP
*
*: tCYCP indicates the APB2 bus clock cycle time.
Document Number: 002-04922 Rev.*B
Page 111 of 128
MB9B560L Series
12.9 MainFlash Memory Write/Erase Characteristics
Value
(VCC = 2.7V to 5.5V)
Parameter
Unit
Remarks
Min
Typ
Max
Large Sector
Small Sector
0.7
3.7
Sector erase
time
-
s
Includes write time prior to internal erase
0.3
12
1.1
Write cycles
< 100 times
Write cycles >
100 times
100
Half word
(16-bit)
write time
-
-
μs
Not including system-level overhead time
Includes write time prior to internal erase
200
Chip erase time
8.0
38.4
s
Write cycles and data hold time
Erase/Write Cycles (Cycle)
Data Hold Time (Year)
1,000
20 *
10,000
10 *
5 *
100,000
*: This value comes from the technology qualification (using Arrhenius equation to translate high temperature acceleration test result
into average temperature value at +85°C).
12.10 WorkFlash Memory Write/Erase Characteristics
(VCC = 2.7V to 5.5V)
Value
Parameter
Unit
Remarks
Min
Typ
Max
Sector erase time
-
-
0.3
1.5
s
Includes write time prior to internal erase
Not including system-level overhead time
Half word (16-bit)
write time
20
200
6
μs
Chip erase time
-
1.2
s
Includes write time prior to internal erase
Write cycles and data hold time
Erase/Write Cycles (Cycle)
Data Hold Time (Year)
1,000
20 *
10,000
100,000
10 *
5 *
*: This value comes from the technology qualification (using Arrhenius equation to translate high temperature acceleration test result
into average temperature value at +85°C).
Document Number: 002-04922 Rev.*B
Page 112 of 128
MB9B560L Series
12.11 Standby Recovery Time
12.11.1 Recovery Cause: Interrupt/WKUP
The time from recovery cause reception of the internal circuit to the program operation start is shown.
Recovery Count Time
(VCC = 2.7V to 5.5V, VSS = 0V)
Remarks
Value
Parameter
Symbol
Unit
Typ
Max*
Sleep mode
HCLK×1
μs
High-speed CR Timer mode
Main Timer mode
40
80
μs
PLL Timer mode
Low-speed CR timer mode
Sub timer mode
450
896
900
μs
μs
1136
RTC mode
stop mode
(High-speed CR /Main/PLL run mode
return)
RTC mode
Ticnt
316
270
581
540
μs
μs
stop mode
(Low-speed CR/sub run mode return)
without RAM
retention
with RAM
retention
365
365
667
667
μs
μs
Deep standby RTC mode
Deep standby stop mode
*: The maximum value depends on the built-in CR accuracy.
Example of Standby Recovery Operation (when in External Interrupt Recovery*)
Ext.INT
Interrupt factor
Active
accept
Ticnt
Interrupt factor
clear by CPU
CPU
Operation
Start
*: External interrupt is set to detecting fall edge.
Document Number: 002-04922 Rev.*B
Page 113 of 128
MB9B560L Series
Example of Standby Recovery Operation (when in Internal Resource Interrupt Recovery*)
Internal
Resource INT
Interrupt factor
accept
Active
Ticnt
Interrupt factor
clear by CPU
CPU
Operation
Start
*: Depending on the standby mode, interrupt from the internal resource is not included in the recovery cause.
Notes:
−
The return factor is different in each Low-Power consumption modes.
See CHAPTER 6: Low Power Consumption Mode and Operations of Standby Modes in FM4 Family Peripheral Manual Main
part (002-04856).
−
When interrupt recoveries, the operation mode that CPU recoveries depend on the state before the Low-Power consumption
mode transition. See CHAPTER 6: Low Power Consumption Mode in FM4 Family Peripheral Manual Main part (002-04856).
Document Number: 002-04922 Rev.*B
Page 114 of 128
MB9B560L Series
12.11.2 Recovery Cause: Reset
The time from reset release to the program operation start is shown.
Recovery Count Time
(VCC = 2.7V to 5.5V, VSS = 0V)
Value
Parameter
Symbol
Unit
Remarks
Typ
Max*
Sleep mode
155
266
μs
High-speed CR timer mode
Main timer mode
155
266
μs
PLL timer mode
Low-speed CR timer mode
Sub timer mode
315
315
567
567
μs
μs
Trcnt
RTC mode
Stop mode
315
336
336
567
667
667
μs
μs
μs
without RAM
retention
with RAM
retention
Deep standby RTC mode
Deep standby stop mode
*: The maximum value depends on the built-in CR accuracy.
Example of Standby Recovery Operation (when in INITX Recovery)
INITX
Internal RST
RST Active
Release
Trcnt
CPU
Operation
Start
Document Number: 002-04922 Rev.*B
Page 115 of 128
MB9B560L Series
Example of Standby Recovery Operation (when in Internal Resource Reset Recovery*)
Internal
Resource RST
Internal RST
RST Active
Release
Trcnt
CPU
Operation
Start
*: Depending on the standby mode, the reset issue from the internal resource is not included in the recovery cause.
Notes:
−
The return factor is different in each Low-Power consumption modes.
See CHAPTER 6: Low Power Consumption Mode and Operations of Standby Modes in FM4 Family Peripheral Manual Main
part (002-04856).
−
The time during the power-on reset/low-voltage detection reset is excluded to the recovery source. See (6) Power-on Reset
Timing in 12.4 AC Characteristics in 12. Electrical Characteristics for the detail on the time during the power-on
reset/low-voltage detection reset.
−
−
When in recovery from reset, CPU changes to the high-speed CR run mode. When using the main clock or the PLL clock, it is
necessary to add the main clock oscillation stabilization wait time or the main PLL clock stabilization wait time.
The internal resource reset means the watchdog reset and the CSV reset.
Document Number: 002-04922 Rev.*B
Page 116 of 128
MB9B560L Series
13.Ordering Information
Part Number
Package
MB9BF564LPMC1
MB9BF565LPMC1
MB9BF566LPMC1
MB9BF564LPMC
MB9BF565LPMC
MB9BF566LPMC
MB9BF564KPMC
MB9BF565KPMC
MB9BF566KPMC
MB9BF564LQN
MB9BF565LQN
MB9BF566LQN
MB9BF564KQN
MB9BF565KQN
MB9BF566KQN
Plastic・LQFP (0.5mm pitch), 64 pin
(LQD064)
Plastic・LQFP (0.65mm pitch), 64 pin
(LQG064)
Plastic・LQFP (0.5mm pitch), 48 pin
(LQA048)
Plastic・QFN (0.5mm pitch), 64 pin
(VNC064)
Plastic・QFN (0.5mm pitch), 48 pin
(VNA048)
Document Number: 002-04922 Rev.*B
Page 117 of 128
MB9B560L Series
14.Package Dimensions
Package Type
Package Code
LQFP 64pin (0.5mm pitch)
LQD064
4
D
5
7
D1
48
33
33
48
32
32
49
49
5
7
E1
E
4
3
6
17
17
64
64
1
16
16
1
2
5
7
e
A-B D
3
0.10
0.08
C A-B D
BOTTOM VIEW
0.20
C
C
A-B
D
b
8
TOP VIEW
2
A
9
c
A
SEATING
PLANE
b
0.25
A'
A1
SECTION A -A '
L1
0.08
C
L
10
SIDE VIEW
DIMENSIONS
SYMBOL
MIN. NOM. MAX.
1.70
A
A1
b
0.00
0.15
0.09
0.20
0.2
c
0.20
D
12.00 BSC.
10.00 BSC.
0.50 BSC
D1
e
E
12.00 BSC.
10.00 BSC.
E1
L
0.45 0.60 0.75
0.30 0.50 0.70
L1
PACKAGE OUTLINE, 64 LEAD LQFP
10.0X10.0X1.7 MM LQD064 Rev**
002-11499 **
Document Number: 002-04922 Rev.*B
Page 118 of 128
MB9B560L Series
Package Type
Package Code
LQFP 64pin (0.65mm pitch)
LQG064
4
5
D
7
D1
48
33
33
48
49
32
32
49
E1
E
5
7
4
3
64
17
17
64
1
16
16
1
2
5
7
BOTTOM VIEW
e
3
0.10
C A-B D
0.20
C A-B D
0.13
C
A-B
D
b
8
TOP VIEW
2
A
θ
A
9
SEATI NG
PLA NE
A1
10
0.25
L
c
A'
L1
b
SECTION A -A'
0.10
C
SIDE VIEW
DIM ENSION
MIN. NOM. MAX.
1.70
SYM BOL
A
A1
b
0.00
0.27 0.32 0.37
0.09 0.20
0.20
c
D
14.00 BSC
12.00 BSC
0.65 BSC
D1
e
E
14.00 BSC
12.00 BSC
E1
L
0.45 0.60 0.75
0.30 0.50 0.70
L1
θ
0°
8°
002-13881 **
PACKAGE OUTLINE, 64 LEAD LQFP
12.0X12.0X1.7 MM LQG064 REV**
Document Number: 002-04922 Rev.*B
Page 119 of 128
MB9B560L Series
Package Type
Package Code
LQFP 48pin (0.5mm pitch)
LQA048
4
5
D
7
D1
36
36
25
25
37
24
24
37
E1
E
5
7
4
3
6
48
13
13
48
1
1
12
12
2
A-B
5
7
e
0.10
C
D
3
0.20
C A-B D
0.80
C
A-B
D
b
8
2
A
9
θ
A
SEATING
PLANE
c
A'
0.25
A1
10
b
0.80
C
L1
L
SECTION A-A'
DIMENSIONS
SYMBOL
MIN. NOM. MAX.
1.70
A
A1
b
0.00
0.15
0.09
0.20
0.27
0.20
c
D
9.00 BSC
7.00 BSC
0.50 BSC
9.00 BSC
7.00 BSC
0.60
D1
e
E
E1
L
0.45
0.30
0°
0.75
0.70
L1
θ
0.50
8°
PACKAGE OUTLINE, 48 LEAD LQFP
7.0X7.0X1.7 MM LQA048 REV**
002-13731 **
Document Number: 002-04922 Rev.*B
Page 120 of 128
MB9B560L Series
Package Type
Package Code
QFN 64pin (0.5mm pitch)
VNC064
0.10
C
A
B
D
D2
A
25
36
0.10
2X
C
0.10
C
A
B
24
37
(N D -1 )× e
5
E
E2
13
48
12
1
R
9
INDEX MARK
8
L
0.10
0.05
C
A
B
B
e
b
TOP VIEW
C
4
0.10
2X
C
BOTTOM VIEW
0.10
C
A
SEATING PLANE
C
0.05
A1
9
C
SIDE VIEW
NOTE
1. ALLDIMENSIONSAREIN MILLIMETERS.
DIMENSIONS
SYMBOL
A
2. DIMENSIONING AND TOLERANCINCCONFORMSTO ASMEY14.5-1994.
3. N ISTHETOTALNUMBEROFTERMINALS.
MIN. NOM. MAX.
0.90
4. DIMENSION "b"APPLIESTO METALLIZED TERMINALAND ISM EASURED
BETWEEN 0.15 AND 0.30mm FROM TERMINALTIP.IFTHETERMINALHAS
THEOPTIONALRADIUSON THEOTHEREND OFTHETERMINAL.THE
DIMENSION "b"SHOULD NOTBEMEASURED IN THATRADIUSAREA.
A
D
E
0.00
0.05
1
7.00 BSC
7.00 BSC
0.25
5. ND REFERTO THENUMBEROFTERMINALSON D ORESIDE.
6. MAX. PACKAGEWARPAGEIS0.05mm.
0.20
0.30
b
D
5.50 BSC
5.50 BSC
0.50 BSC
0.20 REF
0.40
2
2
7. MAXIMUM ALLOWABLEBURRSIS0.076mm IN ALLDIRECTIONS.
8. PIN #1 ID ON TOPWILL BE LOCATED WITHIN INDICATED ZONE.
E
e
9. BILATERALCOPLANARITY ZONEAPPLIESTO THEEXPOSED HEAT
SINKSLUG ASWELLASTHETERMINALS.
R
L
0.35
0.45
10. JEDECSPEC IFICATIONNO . REF: N/A
002-13234 **
PACKAGEOUTLINE, 48 LEAD QFN
7.0X7.0X0.9MMVNA048 5.5X5.5 MMEPAD(SAWN)REV**
Document Number: 002-04922 Rev.*B
Page 121 of 128
MB9B560L Series
Package Type
Package Code
QFN 48pin (0.5mm pitch)
VNA048
0.10
C
A
B
D
D2
A
25
36
0.10
2X
C
0.10
C
A
B
24
37
(N D -1 )× e
5
E
E2
13
48
12
1
R
9
INDEX MARK
8
L
0.10
0.05
C
A
B
B
e
b
TOP VIEW
C
4
0.10
2X
C
BOTTOM VIEW
0.10
C
A
SEATING PLANE
C
0.05
A1
9
C
SIDE VIEW
NOTE
1. ALLDIMENSIONSAREIN MILLIMETERS.
DIMENSIONS
SYMBOL
A
2. DIMENSIONING AND TOLERANCINCCONFORMSTO ASMEY14.5-1994.
3. N ISTHETOTALNUMBEROFTERMINALS.
MIN. NOM. MAX.
0.90
4. DIMENSION "b"APPLIESTO METALLIZED TERMINALAND ISM EASURED
BETWEEN 0.15 AND 0.30mm FROM TERMINALTIP.IFTHETERMINALHAS
THEOPTIONALRADIUSON THEOTHEREND OFTHETERMINAL.THE
DIMENSION "b"SHOULD NOTBEMEASURED IN THATRADIUSAREA.
A
D
E
0.00
0.05
1
7.00 BSC
7.00 BSC
0.25
5. ND REFERTO THENUMBEROFTERMINALSON D ORESIDE.
6. MAX. PACKAGEWARPAGEIS0.05mm.
0.20
0.30
b
D
5.50 BSC
5.50 BSC
0.50 BSC
0.20 REF
0.40
2
2
7. MAXIMUM ALLOWABLEBURRSIS0.076mm IN ALLDIRECTIONS.
8. PIN #1 ID ON TOPWILL BE LOCATED WITHIN INDICATED ZONE.
E
e
9. BILATERALCOPLANARITY ZONEAPPLIESTO THEEXPOSED HEAT
SINKSLUG ASWELLASTHETERMINALS.
R
L
0.35
0.45
10. JEDECSPEC IFICATIONNO . REF: N/A
002-15528 **
PACKAGEOUTLINE, 48 LEAD QFN
7.0X7.0X0.9MMVNA048 5.5X5.5 MMEPAD(SAWN)REV**
Document Number: 002-04922 Rev.*B
Page 122 of 128
MB9B560L Series
15.Major Changes
Spansion Publication Number: DS709-00005
Page
Section
Change Results
Preliminary → Data Sheet
-
-
■FEATURES
Added the following description :
[USB function]
• The size of each endpoint is according to the follows.
- Endpoint 0, 2 to 5 : 64bytes
3
- Endpoint 1 : 256bytes
■I/O CIRCUIT TYPE
Added the following description to Remarks of Type F, G, I, L, M, N:
When this pin is used as an I2C pin, the digital output P-ch transistor is
always off
31 to 34
35 to 36
Added the following description to Remarks of Type O, P, Q:
For I/O setting, refer to VBAT Domain in the PERIPHERAL MANUAL
■HANDLING DEVICES
Handling when using debug pins
Added new section
43
44
■BLOCK DIAGRAM
Revised the block diagram
Added the note to “AVRH”
■ELECTRICAL CHARACTERISTICS
2. Recommended Operating Conditions
57
58
Revised “Table for package thermal resistance and maximum
permissible power”
Revised “Icc(leakmax)”
■ELECTRICAL CHARACTERISTICS
• Revised the value of TBD
60 to 65 3. DC Characteristics
(1) Current Rating
• Added the note to “ICC
• Added the note to “ICCVBAT
”
”
■ELECTRICAL CHARACTERISTICS
4. AC Characteristics
(2) Sub Clock Input Characteristics
Revised the waveform chart :
VCC → VBAT
70
70
■ELECTRICAL CHARACTERISTICS
4. AC Characteristics
• Revised the value of TBD
• Revised the table and the note of “Built-in High-speed CR”
(3) Built-in CR OscillationCharacteristics
■ELECTRICAL CHARACTERISTICS
4. AC Characteristics
• Revised the table and the note
(4-1) Operating Conditions of Main PLL(In the
case of using main clock for input clock of PLL)
(4-2)Operating Conditions of USB PLL(In the case
of using main clock for input clock of PLL)
71
71
■ELECTRICAL CHARACTERISTICS
4. AC Characteristics
(4-3) Operating Conditions of Main PLL(In the
case of using built-in high-speed CR clock for
input clock of main PLL)
• Revised the value of TBD
• Revised the table and the note
■ELECTRICAL CHARACTERISTICS
5. 12-bit A/D Converter
・Electrical Characteristics for the A/D Converter
• Revised the value of TBD
• Revised the condition of the electrical characteristics table
• Revised the description of "Reference voltage"
106
109
■ELECTRICAL CHARACTERISTICS
6. 12-bit D/A Converter
・Electrical Characteristics for the D/A Converter
• Revised the value of TBD
• Revised the condition of the electrical characteristics table
• Revised the remarks of “IDDA”
Document Number: 002-04922 Rev.*B
Page 123 of 128
MB9B560L Series
Page
Section
Change Results
■ELECTRICAL CHARACTERISTICS
11. Standby Recovery Time
• Revised the value of TBD
• Revised the table of Recovery count time
116
(1) Recovery cause: Interrupt/WKUP
■ELECTRICAL CHARACTERISTICS
11. Standby Recovery Time
(2) Recovery cause:Reset
• Revised the value of TBD
• Revised the table of Recovery count time
118
NOTE: Please see “Document History” about later revised information.
Document Number: 002-04922 Rev.*B
Page 124 of 128
MB9B560L Series
Document History
Document Title: MB9B560L Series 32-Bit Arm® Cortex®-M4F, FM4 Microcontroller
Document Number: 002-04922
Orig. of
Change
Submission
Date
Revision
ECN
Description of Change
Migrated to Cypress and assigned document number 002-04922.
No change to document contents or format.
**
-
AKIH
AKIH
12/25/2013
*A
5273878
05/12/2016 Updated to Cypress format.
Added an explanation of product category in introduction (Page 1).
Changed an explanation from “from 01 to 99” to “from 00 to 99” in Real-Time Clock
(RTC) (Page 3) of Features, and Deleted “Second/A day of the week” of interrupt
function.
Corrected “USB Function" to “USB Device" in the following chapters.
Features (Page 1)
1. Product Lineup (Page 7)
4.2 List of Pin Functions (Page 19)
Divided an explanation into 64 pin and 48 pin in Power Supply (Page 4) of Features.
Changed package code as the following in chapter :
2. Packages (Page 8)
3. Pin Assignment (Page 9 - 12)
12.2 Recommended Operating Conditions (Page 53)
13. Ordering Information (Page 117)
14. Package Dimensions (Page 118-122).
FTP-48P-M49 -> LQA048, LCC-48P-M73 -> VNA048,
FTP-64P-M38 -> LQD064, FTP-64P-M39 -> LQG064,
LCC-64P-M24 -> VNC064
*B
5555936
YSKA
12/15/2017
Changed 15 pin (Page 15) at LQFP48 from VBAT to VCC in 4.1 List of Pin Numbers.
Added 15 pin (Page 27) to VCC of Power at LQFP48, Deleted 15 pin from VBAT of
VBAT Power at LQFP48 in 4.2 List of Pin Functions.
Added Note for JTAG pin (Page 27) in 4. Pin Description.
Added an explanation in Notes on Power-on (Page 39) of 7. Handling Devices.
Corrected "total maximum output current" to "total average output current" at ∑
IOLAV in 12.1 Absolute Maximum Ratings (Page52).
Added Smoothing capacitor to Parameter, and Added remarks *6 in 12.2
Recommended Operating Conditions (Page 53).
Changed remark *3 to "When all ports are input and are fixed at "0"." in 12.3.1
Current Rating (Page 57 - 62).
In 12.3.1 Current Rating, Added remark *6 to ICCHD, Added remark *7 to ICCRD,
Added remark *8/*9 to ICCVBAT/RTC operation, and Added remark *9 to
ICCVBAT/RTC stop (Page 62).
Added an explanation for 48 pin package in 12.4.2 Sub Clock Input Characteristics
(Page 67).
Document Number: 002-04922 Rev.*B
Page 125 of 128
MB9B560L Series
Orig. of
Change
Submission
Date
Revision
ECN
Description of Change
Changed Parameter “Power supply rising time (tVCCR)” to “Power ramp rate (dV/dt)” in
12.4.8 Power-on Reset Timing, Changed the minimum to 1.3mV/μs, Changed the
maximum to 1000mV/μs, and Added remarks and note (Page 69).
Deleted setting value “SPI=1” and “MS=0” at using chip select in 12.4.11 UART
Timing, and Added “MS bit = 0” and “MS bit = 1” on the Figure (Page 88-95).
Corrected "Analog port input current" to "Analog port input leak current" in 12.5 12-bit
A/D Converter (Page 103).
Reflected the following items in "Datasheet Errata for the MB9B560L Series
(002-04923)".
Added “Pull-up resistor : Approximately 50 kΩ” to remarks in Type I (Page 31) of
5.I/O Circuit Type.
Modified S/T of VBAT Pin Status Type and remark *2 in List of VBAT Domain Pin
Status (Page 51) of 11.Pin Status in Each CPU State.
Added remarks *5 in 12.2 Recommended Operating Conditions (Page 53).
Added Frequency stabilization time to Parameter, and Added remarks *2 in Built-in
High-speed CR of 12.4.3 Built-in CR Oscillation Characteristics (Page 67).
Added Conversion time to Parameter in Electrical Characteristics for the D/A
Converter of 12.6 12-bit D/A Converter (Page 106).
Revised Recovery Count Time of 12.11.1 Recovery cause: Interrupt/WKUP (Page
113) as follows.
- Typical Value of Sub timer mode is 896μs.
- Typical Value of RTC mode stop mode (High-speed CR / Main/PLL run mode
return) is 316μs.
- Typical Value of RTC mode stop mode (Low-speed CR / sub run mode return) is
270μs, and Max Value is 540μs.
- Typical Value of Deep standby RTC mode without RAM retention is 365μs.
- Typical Value of Deep standby RTC mode with RAM retention is 365μs.
Revised Recovery Count Time of 12.11.2 Recovery cause: Reset (Page 115) as
follows.
- Typical Value of Sleep mode is 155μs.
- Typical Value of High-speed CR timer mode is 155μs.
- Typical Value of Low-speed CR timer mode is 315μs.
- Typical Value of Sub timer mode is 315μs.
- Typical Value of RTC mode stop mode is 315μs, Max Value is 567μs.
- Typical Value of Deep standby RTC mode without RAM retention is 336μs.
- Typical Value of Deep standby RTC mode with RAM retention is 336μs.
Modified the Chapter name “12.4.11 UART Timing” to “12.4.11 CSIO/UART Timing”.
(Page 72)
Added the Baud rate spec in “12.4.11 CSIO/UART Timing”.(Page 72, 74, 76, 78)
Modified the expression for “Reference power supply current” from “between AVRH
and AVSS” to “AVRH” in chapter 12.5. 12-bit A/D Converter (Page 103)
Moved the value(1.0) in “State transition time to operation permission” from minimum
to maximum.(Page 103)
Document Number: 002-04922 Rev.*B
Page 126 of 128
MB9B560L Series
Orig. of
Change
Submission
Date
Revision
ECN
Description of Change
Modified the expression of Built-in CR in “1. Product Lineup”(Page 7)
Modified the mode name of I2C as follows(Page 2, 100)
High-speed mode Fast-mode, Typical Mode Standard-mode
Modified the typo as below.(Page 72, 74, 76, 78)
SCLKx_0 SCKx_0
Modified typo in the “Recovery Count Time” table in 12.11.1 Recovery cause:
Interrupt/WKUP (Page 113) and 12.11.2 Recovery Cause: Reset (Page 115) as
follows.
Old)
Deep standby RTC mode with RAM retention
Deep standby stop mode with RAM retention
New)
Deep standby RTC mode
Deep standby stop mode
Document Number: 002-04922 Rev.*B
Page 127 of 128
MB9B560L Series
Sales, Solutions, and Legal Information
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© Cypress Semiconductor Corporation, 2014-2017. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC (“Cypress”). This document,
including any software or firmware included or referenced in this document (“Software”), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or
other intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software,
then Cypress hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source
code form, to modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form
externally to end users (either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress’s patents that are
infringed by the Software (as provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction,
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TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
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permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any
product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It
is the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress
products are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support
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failure of the device or system could cause personal injury, death, or property damage (“Unintended Uses”). A critical component is any component of a device or system whose failure to perform
can be reasonably expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress
from any claim, damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs,
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Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in
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Document Number: 002-04922 Rev.*B
December 15, 2017
Page 128 of 128
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