CYBT-343151-02_技术文档

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CYBT-343151-02

EZ-BT™ WICED^®XT/XR Module

CYBT-343151-02, EZ-BT™ WICED^®XT/XR Module

General Description

The CYBT-343151-02 is a fully integrated Bluetooth^Smart Ready wireless module. The CYBT-343151-02 includes an onboard

crystal oscillator, passive components, flash memory, and the Cypress CYW20706 silicon device. Refer to the CYW20706 datasheet

for additional details on the capabilities of the silicon device used in this module.

The CYBT-343151-02 provides extended industrial temperature operation (XT). The CYBT-343151-02 supports peripheral functions

(ADC and PWM), UART, I2C, and SPI communication, and a PCM/I2S audio interface. The CYBT-343151-02 includes a royalty-free

Bluetooth stack compatible with Bluetooth 5.0 in a 12.0 × 15.5 × 1.95 mm package.

The CYBT-343151-02 includes 512 KB of onboard serial flash memory and is designed for standalone operation. The

CYBT-343151-02 uses an integrated power amplifier to achieve Class I or Class II output power capability.

The CYBT-343151-02 is fully qualified by Bluetooth SIG and is targeted at applications requiring cost optimized Bluetooth wireless

connectivity.

■ Low power mode support

❐ Deep Sleep: 2.69 µA

Module Description

■ Module size: 12.00 mm × 15.50 mm × 1.95 mm

❐ Drop-in compatible with CYBT-343026-01

Functional Capabilities

■ Bluetooth 5.0 Qualified Smart Ready module

❐ QDID: 164447

❐ Declaration ID: D054216

■ - ADC for audio (12 bits) and DC measurement (10 bits)

■ Serial Communications Interface compatible with I²C slaves

■ SPI support for both master and slave modes

■ HCI interface through UART

■ Certified to FCC, ISED, MIC, KC, NCC, ANATEL, and CE

regulations

■ Castelated solder pad connections for ease-of-use

■ 512-KB on-module serial flash memory

■ Up to 11 GPIOs

■ PCM/I2S Audio interface

■ Two-wire Global Coexistence Interface (GCI)

■ Integrated peripherals such as PWM, ADC

■ Programmable output power control

■ Temperature range: –30 °C to +105 °C

■ Arm^®Cortex^®-M3 32-bit processor

■ Maximum TX output power

❐ +12 dBm for Bluetooth Classic

❐ +9 dBm for Bluetooth Low Energy

• Bluetooth LE connection range of up to 250 meters at

9 dBm^[1]

■ Supports extended synchronous connections (eSCO), for

enhanced voice quality by allowing for retransmission of

dropped packets

Benefits

CYBT-343151-02 provides all necessary components required

to operate Bluetooth LE and/or BR/EDR communication

standards.

■ RX Receive Sensitivity:

❐ Bluetooth Classic:

• –93.5 dBm at 1 Mbps, GFSK

^{• –95.5 dBm at 2 Mbps,}/4-DQPSK

• –89.5 dBm at 3 Mbps, 8-DPSK

❐ –96.5 dBm for Bluetooth Low Energy

■ Proven hardware design ready to use

■ Dual-mode operation eliminates the need for multiple modules

■ Cost optimized for applications without space constraints

■ Nonvolatile memory for self-sufficient operation and

Over-the-Air (OTA) updates

Power Consumption

■ Enhanced Data Rate (EDR) at 8 dBm

❐ Peak TX current: 52.5 mA

❐ Peak RX current consumption: 26.4 mA

■ Bluetooth SIG Listed with QDID and Declaration ID

■ Fully certified module eliminates the time needed for design,

development and certification processes

■ Bluetooth LE at 0 dBm

❐ 1-second interval Bluetooth LE ADV average current

consumption: 315 µA

■ WICED™ Studio provides an easy-to-use integrated design

environment (IDE) to configure, develop, and program a

Bluetooth application

Note

1. Connection range tested module-to-module in full line-of-sight environment, free of obstacles or interference sources with output power of +9.0 dBm. Actual range will

vary based on end product design, environment, receive sensitivity and transmit output power of the central device.

Cypress Semiconductor Corporation

Document Number: 002-24961 Rev. *D

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised March 4, 2021

CYBT-343151-02

More Information

Cypress provides a wealth of data at www.cypress.com to help you to select the right module for your design, and to help you to

quickly and effectively integrate the module into your design.

References

■ Overview: EZ-BLE/BT Module Portfolio, Module Roadmap

■ CYW20706 BT Silicon Datasheet

■ Knowledge Base Article

❐ KBA97095 - EZ-BLE™ Module Placement

❐ KBA213260 - RF Regulatory Certifications for

CYBT-343026-01 EZ-BT™ WICED Modules

❐ KBA213976 - FAQ for Bluetooth LE and Regulatory

Certifications with EZ-BLE modules

❐ KBA210802 - Queries on Bluetooth LE Qualification and

Declaration Processes

■ Development Kits:

❐ CYBT-343026-EVAL, CYBT-343026-01 Evaluation Board

■ Test and Debug Tools:

❐ CYSmart, Bluetooth^®LE Test and Debug Tool (Windows)

❐ CYSmart Mobile, Bluetooth^®LE Test and Debug Tool

❐ KBA218122 - 3D Model Files for EZ-BLE/EZ-BT Modules

❐ KBA221025 - Platform Files for CYBT-343026-EVAL

❐ KBA223428 - Programming an EZ-BT WICED Module

(Android/iOS Mobile App)

Development Environments

Wireless Connectivity for Embedded Devices (WICED) Studio Software Development Kit (SDK)

Cypress’ WICED^®(Wireless Connectivity for Embedded Devices) is a full-featured platform with proven Software Development Kits

(SDKs) and turnkey hardware solutions from partners to readily enable Wi-Fi and Bluetooth^®connectivity in system design.

WICED Studio is the only SDK for the Internet of Things (IoT) that combines Wi-Fi and Bluetooth into a single integrated development

environment. In addition to providing WICED APIs and an application framework designed to abstract complexity, WICED Studio also

leverages many common industry standards.

Technical Support

■ Cypress Community: Whether you’re a customer, partner or a developer interested in the latest Cypress innovations, the Cypress

Developer Community offers you a place to learn, share and engage with both Cypress experts and other embedded engineers

around the world.

■ Frequently Asked Questions (FAQs): Learn more about our Bluetooth ECO System.

■ Visit our support page and create a technical support case or contact a local sales representatives. If you are in the United States,

you can talk to our technical support team by calling our toll-free number: +1-800-541-4736. Select option 2 at the prompt.

Document Number: 002-24961 Rev. *D

Page 2 of 53

CYBT-343151-02

Contents

Overview ............................................................................4

Functional Block Diagram ...........................................4

Module Description ......................................................4

Pad Connection Interface ................................................6

Recommended Host PCB Layout ...................................7

Module Connections ........................................................9

Connections and Optional External Components .......10

Power Connections (VDDIN) .....................................10

External Reset (XRES) ..............................................10

Multiple-Bonded GPIO Connections .........................11

Critical Components List ...........................................13

Antenna Design .........................................................13

Functional Description ...................................................14

Bluetooth Baseband Core .........................................14

Microcontroller Unit ...................................................15

External Reset (XRES) ..............................................16

Integrated Radio Transceiver ........................................17

Transmitter Path ........................................................17

Receiver Path ............................................................17

Local Oscillator Generation .......................................17

Calibration .................................................................17

Internal LDO ..............................................................18

Collaborative Coexistence .............................................18

Global Coexistence Interface ........................................18

SECI I/O ....................................................................18

Peripheral and Communication Interfaces ..................19

I2C Communication Interface ....................................19

HCI UART Interface ..................................................19

Peripheral UART Interface ........................................20

Serial Peripheral Interface .........................................20

PCM Interface ...........................................................20

Clock Frequencies ..........................................................21

GPIO Port ........................................................................21

PWM .................................................................................22

Power Management Unit ................................................23

RF Power Management ............................................23

Host Controller Power Management .........................23

BBC Power Management ..........................................23

Electrical Characteristics ...............................................24

Chipset RF Specifications .............................................27

Timing and AC Characteristics .....................................30

UART Timing .............................................................30

SPI Timing .................................................................31

I2C Interface Timing ..................................................33

PCM Interface Timing ................................................34

I2S Interface Timing ..................................................38

Environmental Specifications .......................................41

Environmental Compliance .......................................41

RF Certification ..........................................................41

Safety Certification ....................................................41

Environmental Conditions .........................................41

ESD and EMI Protection ...........................................41

Regulatory Information ..................................................42

FCC ...........................................................................42

ISED ..........................................................................43

European Declaration of Conformity .........................44

MIC Japan .................................................................44

KC Korea ...................................................................44

NCC Taiwan ..............................................................45

Anatel Brazil ..............................................................45

Packaging ........................................................................46

Ordering Information ......................................................48

Acronyms ........................................................................49

Document Conventions .................................................51

Units of Measure .......................................................51

Document History Page .................................................52

Sales, Solutions, and Legal Information ......................53

Worldwide Sales and Design Support .......................53

Products ....................................................................53

PSoC^®Solutions .......................................................53

Cypress Developer Community .................................53

Technical Support .....................................................53

Document Number: 002-24961 Rev. *D

Page 3 of 53

CYBT-343151-02

Overview

Functional Block Diagram

Figure 1 illustrates the CYBT-343151-02 functional block diagram.

Figure 1. Functional Block Diagram (GPIOs)

Module Description

The CYBT-343151-02 module is a complete module designed to be soldered to the application’s main board.

Module Dimensions and Drawing

Cypress reserves the right to select components from various vendors to achieve the Bluetooth module functionality. Such selections

will still guarantee that all mechanical specifications and module certifications are maintained. Designs should be held within the

physical dimensions shown in the mechanical drawings in Figure 2 on page 5. All dimensions are in millimeters (mm).

Table 1. Module Design Dimensions

Dimension Item

Specification

Length (X) 12.00 ± 0.15 mm

Width (Y) 15.50 ± 0.15 mm

Length (X) 12.0 mm

Width (Y) 4.62 mm

Module dimensions

Antenna connection location dimensions

PCB thickness

Height (H) 0.50 ± 0.05 mm

Height (H) 1.45 mm typical

Shield height

Maximum component height

Total module thickness (bottom of module to highest component) Height (H) 1.95 mm typical

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CYBT-343151-02

See Figure 2 for the mechanical reference drawing for CYBT-343151-02.

Figure 2. Module Mechanical Drawing

Side View

Top View (Seen from Top)

Bottom View

Notes

2. No metal should be located beneath or above the antenna area. Only bare PCB material should be located beneath the antenna area. For more information on

recommended host PCB layout, see “Recommended Host PCB Layout” on page 7.

3. The CYBT-343151-02 includes castellated pad connections, denoted as the circular openings at the pad location above.

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Page 5 of 53

CYBT-343151-02

Pad Connection Interface

As shown in the bottom view of Figure 2 on page 5, the CYBT-343151-02 connects to the host board via solder pads on the backside

of the module. Table 2 and Figure 3 detail the solder pad length, width, and pitch dimensions of the CYBT-343151-02 module.

Table 2. Connection Description

Name Connections

SP 24

Connection Type

Pad Length Dimension Pad Width Dimension

1.02 mm 0.71 mm

Pad Pitch

Solder Pads

1.22 mm

Figure 3. Solder Pad Dimensions (Seen from Bottom

To maximize RF performance, the host layout should follow these recommendations:

1. Antenna Area Keepout: The host board directly below the antenna area of the Cypress module (see Figure 2) must contain no

ground or signal traces. This keep out area requirement applies to all layers of the host board.

2. Module Placement: The ideal placement of the Cypress Bluetooth module is in a corner of the host board with the PCB trace

antenna located at the far corner. This placement minimizes the additional recommended keep out area stated in item 2. Refer to

AN96841 for module placement best practices.

Figure 4. Recommended Host PCB Keep Out Area Around the CYBT-343151-02 Antenna

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CYBT-343151-02

Recommended Host PCB Layout

Figure 5, Figure 6, Figure 7, and Table 3 on page 8 provide details that can be used for the recommended host PCB layout pattern

for the CYBT-343151-02. Dimensions are in millimeters unless otherwise noted. Pad length of 1.27 mm (0.635 mm from center of the

pad on either side) shown in Figure 7 is the minimum recommended host pad length. The host PCB layout pattern can be completed

using either Figure 5, Figure 6, or Figure 7. It is not necessary to use all figures to complete the host PCB layout pattern.

Figure 5. CYBT-343151-02 Host Layout (Dimensioned)

Figure 6. CYBT-343151-02 Host Layout (Relative to Origin)

Top View (Seen on Host PCB)

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Page 7 of 53

CYBT-343151-02

Table 3 provides the center location for each solder pad on the CYBT-343151-02. All dimensions are referenced to the center of the

solder pad. Figure 7 shows the location of each module solder pad.

Table 3. Module Solder Pad Location

Figure 7. Solder Pad Reference Location

Solder Pad

Location(X,Y)from Dimension from

(Center of Pad)

Orign (mm)

(0.38, 5.04)

(0.38, 6.26)

(0.38, 7.48)

(0.38, 8.70)

(0.38, 9.92)

(0.38, 11.14)

(0.38, 12.35)

(0.38, 13.57)

(1.73, 15.11)

(2.95, 15.11)

(4.17, 15.11)

(5.39, 15.11)

(6.61, 15.11)

(7.83, 15.11)

(9.05, 15.11)

(10.27, 15.11)

(11.62, 13.57)

(11.62, 12.35)

(11.62, 11.14)

(11.62, 9.92)

(11.62, 8.70)

(11.62, 7.48)

(11.62, 6.26)

(11.62, 5.04)

Orign (mils)

(14.96, 198.42)

(14.96, 246.46)

(14.96, 294.49)

(14.96, 342.52)

(14.96, 390.55)

(14.96, 438.58)

(14.96, 486.22)

(14.96, 534.25)

(68.11, 594.88)

(116.14, 594.88)

(164.17, 594.88)

(212.20, 594.88)

(260.24, 594.88)

(308.27, 594.88)

(356.30, 594.88)

(404.33, 594.88)

(457.48, 534.25)

(457.48, 486.22)

(457.48, 438.58)

(457.48, 390.55)

(457.48, 342.52)

(457.48, 294.49)

(457.48, 246.46)

(457.48, 198.42)

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

Top View (Seen on Host PCB)

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Page 8 of 53

CYBT-343151-02

Module Connections

Table 4 details the solder pad connection definitions and available functions for the pad connections for the CYBT-343151-02 module.

Table 4 lists the solder pads on the CYBT-343151-02 module, the silicon device pin, and denotes what functions are available for each

solder pad.

Table 4. CYBT-343151-02 Solder Pad Connection Definitions

Silicon Pin Silicon Port-Pin

CLK/

XTAL

[4, 5]

Pad Pad Name

UART

SPI

I2C

ADC

COEX

GPIO

Other

Name

PCM_Sync/

I2S_WS/P0/P34 PUART_RX/P34

PUART_TX/P0

SPI1_MOSI/P0

(master/slave)

IN29/P0

IN5/P34

✓

PCM_Sync

I2S_WS

1

2

P0/P34

C8

I2S_DO/

PUART_CTS/

PCM_Out/P3/

P3 or P35

SCL

SDA/

P35

✓

(P3/P29/P3

5)

I2S_DO

PCM_Out

PWM3 (P29)

SPI1_CLK/P3

(master/slave)

IN4/P35

IN10/29

I2C_SCL

A8

P29/P35

3

4

XRES

RESET_N

C7

RESET_N

External Reset (Active Low)

SDA IN23/P12

PCM_IN/

I2S_DI/P12

✓

(P12)

PCM_IN

I2S_DI

I2C_SDA

PCM_CLK/

I2S_CLK/P2/

P28/P37

SPI1_CS(slave)/P2

SPI1_MOSI(master)

/P2

SPI1_MISO(slave)

/P37

PWM2 (P28)

I2S_CLK

PCM_CLK

SCL/ IN11/P28

P37 IN2/P37

ACLK1/P

37

5

P2/P37/P28

B7

PUART_RX/P2

✓

6

7

SPI2_CS_N

GND

D7

GND

D8

N/A

GND

N/A

No Connect (Used for on-module memory SPI interface for CYBT-343151-02)

Ground

8

SPI2_MISO

SPI2_MOSI

SPI2_CLK

No Connect (Used for on-module memory SPI interface for CYBT-343151-02)

SPI1_CLK/P36

9

E8

10

E7

BT_GPIO_0/P36/

P38

IN3/P36

IN1/P38

ACLK0/P

36

✓

11

12

GPIO_0

GPIO_1

F8

F7

SPI1_MOSI/P38

(master/slave)

(DevWake)

SPI1_MISO/P25

(master/slave)

SPI1_CS/P32

(slave)

BT_GPIO_1/P25/ PUART_RX/P25

ACLK0/P

32

✓

IN7/P32

P32

PUART_TX/P32

(HostWake)

13

14

GND

D6

GND

Ground

IN8/P31

BT_GPIO_4/P6/P PUART_RTS/P6

31/LPO_IN PUART_TX/P31

SPI1_CS/P6

(slave)

Ext LPO In

GPIO_4

✓

SPI1_MOSI/P4

(master/slave)

SPI1_CLK/P24

(master/slave)

BT_CLK_REQ/P4 PUART_RX/P4

✓

15

P4/P24

G8

/P24

PUART_TX/P24

(CLK_REQ)

16 UART_TXD

17 UART_CTS

18 UART_RTS

F4

G4

F3

BT_UART_TXD

BT_UART_CTS

BT_UART_RTS

HCI UART Transmit Data

HCI UART Clear To Send Input

HCI UART Request To Send Output

✓

IN9/P30 (GCI_SECI

_OUT)

BT_GPIO_7/

P30

PUART_RTS/

P30

19

GPIO_7

C6

✓

20 UART_RXD

F5

BT_UART_RXD

VDDIN

HCI UART Receive Data

VDDIN (2.3V ~ 3.6V)

21

22

VDDIN

G1

SPI1_MOSI/P27

(master/slave)

SPI1_MOSI/P33

(slave)

PWM1 (P27)

PWM0 (P26)

BT_GPIO_3/P27/

P33

ACLK1/P

33

GPIO_3

C5

PUART_RX/P33

IN6/P33

✓

IN24/P11 (GCI_SECI

_IN)

BT_GPIO_6/P11/

P26

SPI1_CS/P26

(slave)

23

GPIO_6

GND

B6

24

GND

Ground

Notes

4. The CYBT-343026-01 contains a single SPI (SPI1) peripheral supporting both master or slave configurations. SPI2 is used for on-module serial memory interface.

5. In Master mode, any available GPIO can be configured as SPI1_CS. This function is not explicitly shown in the table above.

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Page 9 of 53

CYBT-343151-02

Connections and Optional External Components

Power Connections (V

)

DDIN

The CYBT-343151-02 contains one power supply connection, V_DDIN. V_DDINaccepts a supply input range of 2.3 V to 3.6 V for

CYBT-343151-02. Table 11 on page 24 provides this specification. The maximum power supply ripple for this power connection is

100 mV, as shown in Table 11.

It is not required to place any power supply decoupling or noise reduction circuitry on the host PCB. If desired, an external ferrite bead

between the supply and the module connection can be included, but is not necessary. If used, the ferrite bead should be positioned

as close as possible to the module pin connection and the recommended ferrite bead value is 330, 100 MHz.

Considerations and Optional Components for Brownout (BO) Conditions

Power supply design must be completed to ensure that the CYBT-343151-02 module does not encounter a Brownout condition, which

can lead to unexpected functionality, or module lock up. A Brownout condition may be met if power supply provided to the module

during power up or reset is in the following range: V_ILV_DDINV_IH.

Refer to Table 12 on page 24 for the V_ILand V_IHspecifications.

System design should ensure that the above condition is not encountered when power is removed from the system. In the event that

this cannot be guaranteed (that is, battery installation, high-value power capacitors with slow discharge), it is recommended that an

external voltage detection device be used to prevent the Brownout voltage range from occurring during power removal.

Figure 8 shows the recommended circuit design when using an external voltage detection IC.

Figure 8. Reference Circuit Block Diagram for External Voltage Detection IC

In the event that the module does encounter a Brownout condition, and is operating erratically or not responsive, power cycling the

module will correct this issue and once reset, the module should operate correctly. Brownout conditions can potentially cause issues

that cannot be corrected, but in general, a power-on reset (POR) operation will correct a Brownout condition.

External Reset (XRES)

The CYBT-343151-02 has an integrated POR circuit, which completely resets all circuits to a known power-on state. This action can

also be evoked by an external reset signal, forcing it into a power-on reset state. The XRES signal is an active-low signal, which is

an input to the CYBT-343151-02 module (solder pad 3). The CYBT-343151-02 module does not require an external pull-up resistor

on the XRES input.

During power-on operation, the XRES connection to the CYBT-343151-02 is required to be held low 50 ms after the V_DDpower supply

input to the module is stable. This can be accomplished in the following ways:

■ The host device should connect a GPIO to the XRES of the Cypress CYBT-343151-02 module and pull XRES low until V_DDis stable.

XRES is recommended to be released 50 ms after V_DDINis stable.

■ If the XRES connection of the CYBT-343151-02 module is not used in the application, a 10-µF capacitor may be connected to the

XRES solder pad of the CYBT-343151-02 in order to delay the XRES release. The capacitor value for this recommended imple-

mentation is approximate, and the exact value may differ depending on the V_DDINpower supply ramp time of the system. The

capacitor value should result in an XRES release timing of 50 ms after V_DDINstability.

■ The XRES release timing may be controlled by a external voltage detection IC. XRES should be released 50 ms after V_DDis stable.

Refer to Figure 11 on page 16 for XRES operating and timing requirements during power-on events.

Document Number: 002-24961 Rev. *D

Page 10 of 53

CYBT-343151-02

Multiple-Bonded GPIO Connections

The CYBT-343151-02 contains GPIOs, which are multiple-bonded at the silicon level. If any of these dual-bonded GPIOs are used,

only the functionality and features for one of these port pins may be used. The desired port pin should be configured in the WICED

Studio SDK. For details on the features and functions that each of these multiple-bonded GPIOs provide, refer to Table 4.

The list below details the multiple-bonded GPIOs available on the CYBT-343151-02 module:

■ PAD 1 P0/34: I2S_WS_PCM_SYNC/P0/P34 (triple bonded; only one of four is available)

■ PAD 2 I2C_SCL: I2S_PCM_OUT/P3/P29/P35 (quadruple bonded; only one of four is available)

■ PAD 4 I2C_SDA: I2S_PCM_IN/P12 (dual bonded; only one of two is available)

■ PAD 5 P2/P37/P28: I2S_PCM_CLK/P2/P28/P37 (quadruple bonded; only one of four is available)

■ PAD 11 GPIO_0: GPIO_0/P36/P38 (triple bonded; only one of three is available)

■ PAD 12 GPIO_1: GPIO_1/P25/P32 (triple bonded; only one of three is available)

■ PAD 14 GPIO_4: GPIO_4/LPO_IN/P6/P31 (quadruple bonded; only of four is available)

■ PAD 15 P4/P24: BT_CLK_REQ/P4/P24 (triple bonded; only one of three is available)

■ PAD 19 GPIO_7: GPIO_7/P30 (Dual bonded; only one of two is available)

■ PAD 22 GPIO_3: GPIO_3/P27/P33 (triple bonded; only one of three is available)

■ PAD 23 GPIO_6: GPIO_6/P11/P26 (triple bonded; only one of three is available)

Document Number: 002-24961 Rev. *D

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CYBT-343151-02

Figure 9 illustrates the CYBT-343151-02 schematic.

Figure 9. CYBT-343151-02 Schematic Diagram

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Page 12 of 53

CYBT-343151-02

Critical Components List

Table 5 details the critical components used in the CYBT-343151-02 module.

Table 5. Critical Component List

Component

Silicon

Reference Designator

Description

U1

U2

Y1

49-pin FBGA BT/Bluetooth LE Silicon Device - CYW20706

8-pin TDF8N, 512K Serial Flash

24 MHz, 12 pF

Silicon

Crystal

Antenna Design

Table 6 details trace antenna used in the CYBT-343151-02 module.

Table 6. Trace Antenna Specifications

Item

Description

2400–2500 MHz

Frequency Range

Peak Gain

–0.5 dBi typical

Return Loss

10 dB minimum

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Page 13 of 53

CYBT-343151-02

Functional Description

Bluetooth Baseband Core

The Bluetooth Baseband Core (BBC) implements all of the time-critical functions required for high-performance Bluetooth operation.

The BBC manages the buffering, segmentation, and routing of data for all connections. It also buffers data that passes through it,

handles data flow control, schedules SCO/ACL and TX/RX transactions, monitors Bluetooth slot usage, optimally segments, and

packages data into baseband packets, manages connection status indicators, and composes and decodes HCI packets. In addition

to these functions, it independently handles HCI event types, and HCI command types. The following transmit and receive functions

are also implemented in the BBC hardware to increase reliability and security of the TX/RX data before sending over-the-air:

■ Symbol timing recovery, data deframing, forward error correction (FEC), header error control (HEC), cyclic redundancy check (CRC),

data decryption, and data dewhitening in the receiver.

■ Data framing, FEC generation, HEC generation, CRC generation, key generation, data encryption, and data whitening in the

transmitter.

Table 7. Bluetooth Features

Bluetooth 1.0

Bluetooth 1.2

Interlaced Scans

Bluetooth 2.0

Basic Rate

SCO

EDR 2 Mbps and 3 Mbps

Adaptive Frequency Hopping

eSCO

–

Paging and Inquiry

Page and Inquiry Scan

Sniff

–

Bluetooth 2.1

Bluetooth 3.0

Bluetooth 4.0

Secure Simple Pairing

Enhanced Inquiry Response

Sniff Subrating

Unicast Connectionless Data

Enhanced Power Control

eSCO

Bluetooth Low Energy

–

Bluetooth 4.1

Bluetooth 4.2

Low Duty Cycle Advertising

Dual Mode

Data Packet Length Extension

LE Secure Connection

Link Layer Privacy

–

LE Link Layer Topology

Link Control Layer

The link control layer is part of the Bluetooth link control functions that are implemented in dedicated logic in the link control unit (LCU).

This layer consists of the command controller that takes commands from the software, and other controllers that are activated or

configured by the command controller, to perform the link control tasks. Each task is performed in a different state in the Bluetooth

Link Controller.

■ States:

❐ Standby

❐ Connection

❐ Page

❐ Page Scan

❐ Inquiry

❐ Inquiry Scan

❐ Sniff

❐ Advertising

❐ Scanning

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CYBT-343151-02

Test Mode Support

The CYBT-343151-02 fully supports Bluetooth Test Mode as described in Part I:1 of the Specification of the Bluetooth System Version

3.0. This includes the transmitter tests, normal and delayed loopback tests, and reduced hopping sequence.

In addition to the standard Bluetooth Test Mode, the CYBT-343151-02 also supports enhanced testing features to simplify RF

debugging and qualification and type-approval testing.

These features include:

■ Fixed frequency carrier wave (unmodulated) transmission

❐ Simplifies some type-approval measurements (Japan)

❐ Aids in transmitter performance analysis

■ Fixed frequency constant receiver mode

❐ Receiver output directed to I/O pin

❐ Allows for direct BER measurements using standard RF test equipment

❐ Facilitates spurious emissions testing for receive mode

■ Fixed frequency constant transmission

❐ 8-bit fixed pattern or PRBS-9

❐ Enables modulated signal measurements with standard RF test equipment.

Frequency Hopping Generator

The frequency hopping sequence generator selects the correct hopping channel number based on the link controller state, Bluetooth

clock, and device address.

Microcontroller Unit

The microprocessor unit in CYBT-343151-02 runs software from the link control (LC) layer up to the host controller interface (HCI).

The microprocessor is based on the Arm Cortex-M3 32-bit RISC processor with embedded ICE-RT debug and JTAG interface units.

The microprocessor also includes 848 KB of ROM memory for program storage and boot ROM, 352 KB of RAM for data scratch-pad,

and patch RAM code.

The internal boot ROM provides flexibility during power-on reset to enable the same device to be used in various configurations. At

power-up, the lower layer protocol stack is executed from the internal ROM.

External patches can be applied to the ROM-based firmware to provide flexibility for bug fixes and features additions. These patches

can be downloaded using external NVRAM. The device can also support the integration of user applications and profiles using an

external serial flash memory.

NVRAM Configuration Data and Storage

NVRAM contains configuration information about the customer application, including the following:

■ Fractional-N information

■ BD_ADDR

■ UART baud rate

■ SDP service record

■ File system information used for code, code patches, or data. The CYBT-343151-02 uses SPI Serial Flash for NVRAM storage.

One-Time Programmable Memory

The microprocessor unit in CYBT-343151-02 includes 2 KB of one-time programmable (OTP) memory allow manufacturing custom-

ization and to avoid the need for an onboard NVRAM. If customization is not required, then the OTP does not need to be programmed.

Whether the OTP is programmed or not, to save power it is disabled when the boot process is complete. The OTP is designed to

store a minimal amount of information. Aside from OTP data, most user configuration information will be downloaded to RAM after

the CYBT-343151-02 boots and is ready for host transport communication.

The OTP contents are limited to:

■ Parameters required prior to downloading the user configuration to RAM.

■ Parameters unique to each part and each customer (for example, the Bluetooth device address and/or the software license key).

■ V_DDINfor the module must be kept to 3.0 V to 3.6 V power supply range if OTP is used in the application.

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CYBT-343151-02

External Reset (XRES)

The CYBT-343151-02 has an integrated POR circuit that completely resets all circuits to a known power-on state. An external active

low reset signal, XRES, can be used to put the CYBT-343151-02 in the reset state. The XRES pin has an internal pull-up resistor and,

in most applications, it does not require anything to be connected to it.

Figure 10. External Reset Internal Timing

External Reset (XRES) Recommended External Components and Proper Operation

During a power-on event, the XRES line of the CYBT-343151-02 is required to be held low 50 ms after the V_DDpower supply input

to the module is stable. Refer to Figure 11 for the Power-On XRES timing operation. This power-on operation can be accomplished

in the following ways:

■ A host device should connect a GPIO to the XRES of the Cypress CYBT-343151-02 module and pull XRES low until V_DDis stable.

XRES can be released after V_DDis stable.

■ If the XRES connection of the CYBT-343151-02 module is not used in the application, a 10-µF capacitor may be connected to the

XRES solder pad of the CYBT-343151-02.

■ The XRES release timing can also be controlled via an external voltage detection circuit.

Figure 11. Power-On External Reset (XRES) Operation

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CYBT-343151-02

Integrated Radio Transceiver

The CYBT-343151-02 has an integrated radio transceiver that has been optimized for use in 2.4-GHz Bluetooth wireless systems. It

has been designed to provide low-power, low-cost, robust communications for applications operating in the globally available 2.4-GHz

unlicensed ISM band. The CYBT-343151-02 is fully compliant with the Bluetooth Radio Specification and EDR specification and meets

or exceeds the requirements to provide the highest communication link quality of service.

Transmitter Path

The CYBT-343151-02 a fully integrated zero-IF transmitter. The baseband transmit data is GFSK-modulated in the modem block and

upconverted to the 2.4-GHz ISM band in the transmitter path. The transmitter path consists of signal filtering, I/Q upconversion, output

^{power amplifier, and RF filtering. The transmitter path also incorporates}/4-DQPSK for 2 Mbps and 8-DPSK for 3 Mbps to support

EDR. The transmitter section is compatible with the Bluetooth LE specification. The transmitter PAbias can also be adjusted to provide

Bluetooth class 1 or class 2 operation.

Digital Modulator

^{The digital modulator performs the data modulation and filtering required for the GFSK,}4-DQPSK, and 8-DPSK signal. The fully

digital modulator minimizes any frequency drift or anomalies in the modulation characteristics of the transmitted signal and is much

more stable than direct VCO modulation schemes.

Digital Demodulator and Bit Synchronizer

The digital demodulator and bit synchronizer take the low-IF received signal and perform an optimal frequency tracking and bit

synchronization algorithm.

Power Amplifier

The fully integrated PAsupports Class 1 or Class 2 output using a highly linearized, temperature-compensated design. The transmitter

features a sophisticated on-chip transmit signal strength indicator (TSSI) block to keep the absolute output power variation within a

tight range across process, voltage, and temperature.

Receiver Path

The receiver path uses a low-IF scheme to downconvert the received signal for demodulation in the digital demodulator and bit

synchronizer. The receiver path provides a high degree of linearity, an extended dynamic range, and high-order on-chip channel

filtering to ensure reliable operation in the noisy 2.4 GHz ISM band. The front-end topology, with built-in out-of-band attenuation,

enables the CYBT-343151-02 to be used in most applications with minimal off-chip filtering. For integrated handset operation, in which

the Bluetooth function is integrated close to the cellular transmitter, external filtering is required to eliminate the desensitization of the

receiver by the cellular transmit signal.

Digital Demodulator and Bit Synchronizer

The digital demodulator and bit synchronizer take the low-IF received signal and perform an optimal frequency tracking and bit

synchronization algorithm.

Receiver Signal Strength Indicator

The radio portion of the CYBT-343151-02 provides a receiver signal strength indicator (RSSI) to the baseband. This enables the

controller to take part in a Bluetooth power-controlled link by providing a metric of its own receiver signal strength to determine whether

the transmitter should increase or decrease its output power.

Local Oscillator Generation

The local oscillator (LO) provides fast frequency hopping (1600 hops/second) across the 79 maximum available channels. The LO

generation sub-block employs an architecture for high immunity to LO pulling during PA operation. The CYBT-343151-02 uses an

internal loop filter.

Calibration

The CYBT-343151-02 radio transceiver features an automated calibration scheme that is fully self-contained in the radio. No user

interaction is required during normal operation or during manufacturing to provide optimal performance. Calibration tunes the perfor-

mance of all the major blocks within the radio to within 2% of optimal conditions, including gain and phase characteristics of filters,

matching between key components, and key gain blocks. This takes into account process variation and temperature variation.

Calibration occurs transparently during normal operation during the settling time of the hops, and calibrates for temperature variations

as the device cools and heats during normal operation in its environment.

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CYBT-343151-02

Internal LDO

The microprocessor in CYBT-343151-02 uses two LDOs: one for 1.2 V and the other for 2.5 V. The 1.2-V LDO provides power to the

baseband and radio and the 2.5-V LDO powers the PA.

Collaborative Coexistence

The CYBT-343151-02 provides extensions and collaborative coexistence to the standard Bluetooth AFH for direct communication

with WLAN devices. Collaborative coexistence enables WLAN and Bluetooth to operate simultaneously in a single device. The device

supports industry-standard coexistence signaling, including 802.15.2, and supports Cypress and third-party WLAN solutions.

Global Coexistence Interface

The CYBT-343151-02 supports the proprietary Cypress Global Coexistence Interface (GCI) which is a two-wire interface.

The following key features are associated with the interface:

■ Enhanced coexistence data can be exchanged over GCI_SECI_IN and GCI_SECI_OUT a two-wire interface, one serial input

(GCI_SECI_IN), and one serial output (GCI_SECI_OUT). The pad configuration registers must be programmed to choose the digital

I/O pins that serve the GCI_SECI_IN and GCI_SECI_OUT function.

■ It supports generic UART communication between WLAN and Bluetooth devices.

■ To conserve power, it is disabled when inactive.

■ It supports automatic resynchronization upon waking from sleep mode.

■ It supports a baud rate of up to 4 Mbps.

SECI I/O

The microprocessor in CYBT-343151-02 has dedicated GCI_SECI_IN (PAD 23/GPIO_6) and GCI_SECI_OUT (PAD19/GPIO_7) pins.

Table 4 on page 9 details the module solder pad number used for SECI I/O.

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CYBT-343151-02

Peripheral and Communication Interfaces

2

I C Communication Interface

The CYBT-343151-02 provides a two-pin master I²C interface, which can be used to retrieve configuration information from an external

EEPROM or to communicate with peripherals such as track-ball or touch-pad modules, and motion tracking ICs used in mouse

devices. This interface is compatible with I²C slave devices. I²C does not support multimaster capability or flexible wait-state insertion

by either master or slave devices.

The following transfer clock rates are supported by the I²C:

■ 100 kHz

■ 400 kHz

■ 800 kHz (Not a standard I²C-compatible speed.)

■ 1 MHz (Compatibility with high-speed I²C-compatible devices is not guaranteed.)

The following transfer types are supported by the I²C:

■ Read (Up to 127 bytes can be read.)

■ Write (Up to 127 bytes can be written.)

■ Read-then-Write (Up to 127 bytes can be read and up to 127 bytes can be written.)

■ Write-then-Read (Up to127 bytes can be written and up to 127 bytes can be read.)

Hardware controls the transfers, requiring minimal firmware setup and supervision.

The clock pad (I2C_SCL) and data pad 2 (I2C_SDA) are both open-drain I/O pins. Pull-up resistors, external to the CYBT-343151-02,

are required on both the SCL and SDA pad for proper operation.

HCI UART Interface

The UART physical interface is a standard, four-wire interface (RX, TX, RTS, and CTS) with adjustable baud rates from 38400 bps

to 4 Mbps. During initial boot, UART speed may be limited to 750 kbps. The baud rate may be selected via a vendor-specific UART

HCI command. The CYBT-343151-02 has a 1040-byte receive FIFO and a 1040-byte transmit FIFO to support enhanced data rates.

The interface supports the Bluetooth UART HCI (H4) specification. The default baud rate for H4 is 115.2 kbaud.

The UART clock default setting is 24 MHz, and can be configured to run as high as 48 MHz to support up to 4 Mbps. The baud rate

of the CYBT-343151-02 UART is controlled by two values. The first is a UART clock divisor (set in the DLBR register) that divides the

UART clock by an integer multiple of 16. The second is a baud rate adjustment (set in the DHBR register) that is used to specify a

number of UART clock cycles to stuff in the first or second half of each bit time. Up to eight UART cycles can be inserted into the first

half of each bit time, and up to eight UART clock cycles can be inserted into the end of each bit time.

Table 8 contains example values to generate common baud rates with a 24 MHz UART clock.

Table 8. Common Baud Rate Examples, 24 MHz Clock

Baud Rate Adjustment

Baud Rate (bps)

Mode

Error (%)

High Nibble

0xFF

Low Nibble

0xF4

4M

3M

High rate

Normal

0.00

0.16

0.00

0xFF

0xF8

2M

0XFF

0X44

0x05

0XF4

0XFF

0x05

1M

921600

460800

230400

115200

57600

38400

0x02

0x04

0x00

0x01

0x00

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CYBT-343151-02

Normally, the UART baud rate is set by a configuration record downloaded after reset. Support for changing the baud rate during

normal HCI UART operation is included through a vendor-specific command that allows the host to adjust the contents of the baud

rate registers.

The CYBT-343151-02 UART operates correctly with the host UART as long as the combined baud rate error of the two devices is

within ±2%.

Peripheral UART Interface

The CYBT-343151-02 has a second UART that may be used to interface to other peripherals. This peripheral UART is accessed

through the optional I/O ports, which can be configured individually and separately for each signal as shown in Table 9.

Table 9. CYBT-343151-02 Peripheral UART

Signal Name

PUART_TX

P0

PUART_RX

PUART_CTS_N

PUART_RTS_N

PUART Port Configuration #1

PUART Port Configuration #2

P2

P3

P6

P31

P33

P35

P30

Serial Peripheral Interface

The CYBT-343151-02 has two independent SPI interfaces. One is a master-only interface (SPI2) and the other (SPI1) can be either

a master or a slave. Each interface has a 64-byte transmit buffer and a 64-byte receive buffer. To support more flexibility for user

applications, the CYBT-343151-02 has optional I/O ports that can be configured individually and separately for each functional pin.

The CYBT-343151-02 acts as an SPI master device that supports 3.3 V SPI slaves. For master mode, refer to Table 4 on page 9 to

identify the solder pads available for SPI1_MISO, SPI1_MOSI, and SPI1_CLK connections.

Note In master mode, any available GPIO can be assigned as SPI1_CS.

The CYBT-343151-02 can also act as an SPI slave device that supports a 3.3 V SPI master. For SPI1 slave mode, refer to Table 4 to

identify the solder pads available for SPI1 slave mode connections.

SPI voltage depends on V_DDIN; therefore, V_DDINshould be set to 3.3 V for SPI communication.

PCM Interface

The CYBT-343151-02 includes a PCM interface that shares pins with the I²S interface. The PCM Interface on the CYBT-343151-02

can connect to linear PCM codec devices in master or slave mode. In master mode, the CYBT-343151-02 generates the PCM_CLK

and PCM_SYNC signals. In slave mode, these signals are provided by another master on the PCM interface and are inputs to the

CYBT-343151-02.

Slot Mapping

The CYBT-343151-02 supports up to three simultaneous full-duplex SCO or eSCO channels through the PCM interface. These three

channels are time-multiplexed onto the single PCM interface by using a time-slotting scheme where the 8 kHz or 16 kHz audio sample

interval is divided into as many as 16 slots. The number of slots is dependent on the selected interface rate (128 kHz, 512 kHz, or

1024 kHz). The corresponding number of slots for these interface rates is 1, 2, 4, 8, and 16, respectively. Transmit and receive PCM

data from an SCO channel is always mapped to the same slot. The PCM data output driver tristates its output on unused slots to allow

other devices to share the same PCM interface signals. The data output driver tristates its output after the falling edge of the PCM

clock during the last bit of the slot.

Frame Synchronization

The CYBT-343151-02 supports both short- and long-frame synchronization in both master and slave modes. In short-frame synchro-

nization mode, the frame synchronization signal is an active-high pulse at the audio frame rate that is a single-bit period in width and

is synchronized to the rising edge of the bit clock. The PCM slave looks for a high on the falling edge of the bit clock and expects the

first bit of the first slot to start at the next rising edge of the clock. In long-frame synchronization mode, the frame synchronization

signal is again an active-high pulse at the audio frame rate; however, the duration is three bit periods and the pulse starts coincident

with the first bit of the first slot.

Data Formatting

The CYBT-343151-02 may be configured to generate and accept several different data formats. For conventional narrowband speech

mode, the CYBT-343151-02 uses 13 of the 16 bits in each PCM frame. The location and order of these 13 bits can be configured to

support various data formats on the PCM interface. The remaining three bits are ignored on the input and may be filled with 0s, 1s, a

sign bit, or a programmed value on the output. The default format is 13-bit 2’s complement data, left justified, and clocked MSB first.

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CYBT-343151-02

Clock Frequencies

The CYBT-343151-02 has an integrated 24 MHz crystal on the module. There is no need to add an additional crystal oscillator.

GPIO Port

The CYBT-343151-02 has nine GPIOs besides two I²C pads. All GPIOs support programmable pull-ups and are capable of driving

up to 8 mA at 3.3 V or 4 mA at 1.8 V, except chips P26, P27, P28, and P29, which are capable of driving up to 16 mA at 3.3 V.

The following GPIOs are available on the module pads: