CYPD3171-24LQXQT [INFINEON]
PG-VQFN-24 tape and reel packing PD controller with PFET gate driver and dual-role port with direct-feedback and programmable;
| 型号： | CYPD3171-24LQXQT |
| 厂家： | 
Infineon |
| 描述： | PG-VQFN-24 tape and reel packing PD controller with PFET gate driver and dual-role port with direct-feedback and programmable 光电二极管 |
| 文件： | 总45页 (文件大小：734K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CYPD3171, CYPD3174, CYPD3175
EZ-PD™ CCG3PA Consumer USB Type-C port
controller
General description
EZ-PD™ CCG3PA is Infineon’s highly integrated USB Type-C port controller that complies with the latest USB
Type-C and PD standards and is targeted for PC power adapters, mobile chargers, car chargers, and power bank
applications. In such applications, CCG3PA provides additional functionalities and BOM integration advantages.
CCG3PA uses Infineon’s proprietary M0S8 technology with a 32-bit Arm® Cortex®-M0 processor, 64-KB flash, a
complete Type-C USB PD transceiver, all termination resistors required for a Type-C port, integrated feedback
control circuitry for voltage (VBUS) regulation, and system-level ESD protection. It is available in 24-pin QFN and
16-pin SOIC packages.
Features
• Type-C support and USB PD support
- Supports USB PD Revision 3.1 including programmable power supply (PPS) mode
- Configurable resistors RP and RD
- Supports one USB Type-C port and one Type-A port
• 2x legacy/proprietary charging blocks
- Supports QC 4.0, Apple charging 2.4A, AFC, BC 1.2
- Integrates all required terminations on DP/DM lines
• Integrated voltage (VBUS) regulation and current sense amplifier
- Analog regulation of secondary side feedback node (direct feedback or opto coupler)
- Integrated shunt regulator function for VBUS control
- Constant current or constant voltage mode
- Supports low-side current sensing for constant current control
• System-level fault protection
- VBUS to CC short protection
- On-chip OVP, OCP, UVP, and SCP
- Supports OTP through integrated ADC circuit
• 32-bit MCU subsystem
- Arm® Cortex®-M0 CPU
- 64-KB Flash
- 8-KB SRAM
• Clocks and oscillators
- Integrated oscillator eliminating the need for external clock
• Power
- 3.0-V to 24.5-V operation (30-V tolerant)
• System-level ESD protection
- On CC, VBUS_C_MON_DISCHARGE, DP0, DM0, P2.2, and P2.3 pins
- ± 8-kV contact discharge and ±15-kV air gap discharge based on IEC61000-4-2 level 4C
• Packages
- 24-pin QFN and 16-pin SOIC
- Supports extended industrial temperature range (–40°C to +105°C)
Datasheet
www.infineon.com
Please read the Important Notice and Warnings at the end of this document
page 1 of 45
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EZ-PD™ CCG3PA Consumer USB Type-C port controller
Logic block diagram
Logic block diagram
CCG3PA: Single- Chip Type - C Controller
MCU Subsystem
I/O Subsystem
CC
Integrated Digital Blocks
Arm®
4x TCPWM
Cortex®
- M0
2x SCB
(I2 C, SPI, UART)
GPIOs
USB PD Subsystem
Low- side Current
Sense Amplifier
2x PFET Gate
Drivers
System
Resources
2x Charger Detect
Internal block diagram
VBUS_P_CTRL
VBUS_C_CTRL
VBUS_C_MON_DISCHARGE
VBUS_IN_DISCHARGE
OV/UV,
R-Div
R-Div
VDDD
VCCD
HV Reg
DISCH
3.3 V
Prog
DISCH
1.8 V
LDO
CC1
BMC
PHY
CC2
MCU Subsystem
DP0 / GPIO
DM0 / GPIO
DP1 / GPIO
Charger
Detect0
Advanced High- Performance Bus (AHB)
SRAM
FB
Cortex®-M0
Flash (64 KB)
4x TCPWM
(8 KB)
Charger
Detect1
CATH/
COMP
DM1 / GPIO
2x SCB
(I2C, SPI, UART)
POR
AXRES / GPIO
LSCSA
2x ADCs
GPIO
GPIO
GND
CSP
Type-C Connector
Ground
Rs
Datasheet
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EZ-PD™ CCG3PA Consumer USB Type-C port controller
Table of contents
Table of contents
General description ...........................................................................................................................1
Features ...........................................................................................................................................1
Logic block diagram ..........................................................................................................................2
Internal block diagram ......................................................................................................................2
Table of contents...............................................................................................................................3
1 Functional overview .......................................................................................................................4
1.1 MCU subsystem.......................................................................................................................................................4
1.1.1 CPU .......................................................................................................................................................................4
1.1.2 Flash .....................................................................................................................................................................4
1.1.3 SROM ....................................................................................................................................................................4
1.2 USB PD subsystem (SS) ..........................................................................................................................................4
1.2.1 USB PD physical layer..........................................................................................................................................4
1.2.2 Analog-to-digital converter (ADC).......................................................................................................................4
1.2.3 Charger detection ................................................................................................................................................4
1.2.4 VBUS overcurrent and overvoltage protection ..................................................................................................4
1.2.5 VBUS short protection .........................................................................................................................................5
1.2.6 Low-side current sense amplifier (CSA)..............................................................................................................5
1.2.7 PFET gate drivers on VBUS path..........................................................................................................................5
1.2.8 VBUS discharge FETs ...........................................................................................................................................5
1.2.9 Voltage (VBUS) regulation ...................................................................................................................................5
1.3 Integrated digital blocks.........................................................................................................................................5
1.3.1 Serial Communication Blocks (SCB) ...................................................................................................................5
1.3.2 Timer/Counter/PWM Block (TCPWM)..................................................................................................................6
1.4 I/O subsystem .........................................................................................................................................................6
2 Power systems overview .................................................................................................................7
3 Pinouts ..........................................................................................................................................8
4 CCG3PA programming and bootloading ..........................................................................................12
4.1 Programming the device flash over SWD interface.............................................................................................12
4.2 Application firmware update over CC interface..................................................................................................13
5 Application diagrams ....................................................................................................................14
6 Electrical specifications.................................................................................................................19
6.1 Absolute maximum ratings ..................................................................................................................................19
6.2 Device-level specifications ...................................................................................................................................21
6.2.1 I/O .......................................................................................................................................................................22
6.3 Digital peripherals.................................................................................................................................................25
6.3.1 Pulse Width Modulation (PWM) for GPIO pins ..................................................................................................25
6.3.2 I2C .......................................................................................................................................................................25
6.4 System resources..................................................................................................................................................27
6.4.1 Power-on-reset (POR) with brown out SWD interface .....................................................................................27
6.4.2 Internal main oscillator .....................................................................................................................................28
6.4.3 Internal low-speed oscillator power down.......................................................................................................28
6.4.4 Gate driver specifications..................................................................................................................................31
6.4.5 Analog-to-digital converter ...............................................................................................................................34
6.4.6 Memory...............................................................................................................................................................35
7 Ordering information ....................................................................................................................36
7.1 Ordering code definitions.....................................................................................................................................36
8 Packaging ....................................................................................................................................37
9 Acronyms.....................................................................................................................................40
10 Document conventions................................................................................................................42
10.1 Units of measure .................................................................................................................................................42
Revision history ..............................................................................................................................43
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Functional overview
1
Functional overview
1.1
1.1.1
MCU subsystem
CPU
The Cortex®-M0 CPU in EZ-PD™ CCG3PA is part of the 32-bit MCU subsystem, which is optimized for low-power
operation with extensive clock gating.
The CPU also includes a serial wire debug (SWD) interface for programming and debugging. The debug configu-
ration used for EZ-PD™ CCG3PA has four breakpoint (address) comparators and two watchpoint (data) compar-
ators.
1.1.2
Flash
The EZ-PD™ CCG3PA device has a flash module with one bank of 64-KB flash, a flash accelerator, tightly coupled
to the CPU to improve average access times from the flash block.
1.1.3
SROM
A supervisory ROM that contains boot and configuration routines is provided.
1.2
USB PD subsystem (SS)
The USB PD subsystem provides the interface to the Type-C USB port. This subsystem comprises a current sense
amplifier, a high-voltage regulator, OVP, OCP, and supply switch blocks. This subsystem also includes all ESD
required and supported on the Type-C port.
1.2.1
USB PD physical layer
The USB PD physical layer consists of a transmitter and receiver that communicate BMC-encoded data over the
CC channel based on the PD 3.1 standard. All communication is half-duplex. The physical layer or PHY
implements collision avoidance to minimize communication errors on the channel.
The USBPD block includes all termination resistors (RP and RD) and their switches as required by the USB PD spec.
RP and RD resistors are required to implement connection detection, plug orientation detection, and for estab-
lishing USB DFP/UFP roles. The RP resistor is implemented as a current source.
According to the USB Type-C spec, a Type-C controller such as CCG3PA must present certain termination resistors
depending on its role in its unpowered state. The sink role in a power bank application requires RD resistors to
be present on the CC pins whereas the DFP role, as in a power adapter, requires both CC lines to be open. To be
flexible for such applications, CCG3PA includes the resistors required in the unpowered state on separate pads
or pins. The dead battery RD resistors are available on separate pads. The dead battery RD is implemented as a
bond option on parts for Power Bank applications. In these parts, each CC pin is bonded out together with its
corresponding dead battery RD resistor. On part numbers for the DFP application, the CC pins are not bonded
with the dead battery RD.
1.2.2
Analog-to-digital converter (ADC)
An 8-bit SAR ADC is available for general-purpose A-D conversion applications in the chip. This ADC can be
accessed from all GPIOs and the DP/DM pins through an on-chip analog mux. CCG3PA contains two instances of
the ADC. The voltage reference for the ADCs is generated either from the VDDD supply or from internal bandgap.
When sensing the GPIO pin voltage with an ADC, the pin voltage cannot exceed the VDDIO supply value.
1.2.3
Charger detection
The two charger detection blocks connected to the two pairs of DP/DM pins allow CCG3PA to emulate legacy
battery chargers conforming to BC 1.2, and the following proprietary charger specifications: Apple, Qualcomm’s
QuickCharge 4.0, and Samsung AFC.
1.2.4
VBUS overcurrent and overvoltage protection
The CCG3PA chip has an integrated hardware block for VBUS overvoltage protection (OVP)/overcurrent
protection (OCP) with configurable thresholds and response times on the Type C port.
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EZ-PD™ CCG3PA Consumer USB Type-C port controller
Functional overview
1.2.5
VBUS short protection
CCG3PA provides four VBUS pins tolerant of accidental shorts to high-voltage VBUS: CC1, CC2, P2.2, and P2.3.
Accidental shorts may occur because the CC1 and CC2 pins are placed next to the VBUS pins in the USB Type-C
connector. A Power Delivery controller without the high-voltage VBUS short protection will be damaged in the
event of accidental shorts. When the protection circuit is triggered, CCG3PA can handle up to 17 V forever and
between 17 V to 22 V DC for 1000 hours on the overvoltage tolerant (OVT) pins. When a VBUS short event occurs
on the CC pins, a temporary high-ringing voltage is observed due to the RLC elements in the USB Type-C cable.
Without CCG3PA connected, this ringing voltage can be twice (44 V) the maximum VBUS voltage (21.5 V).
However, when CCG3PA is connected, it is capable of clamping temporary high-ringing voltage and protecting
the CC pin using IEC ESD protection diodes.
1.2.6
Low-side current sense amplifier (CSA)
The CCG3PA chip also has an integrated low-side current sense amplifier that is capable of detecting current
levels ranging from 100 mA to 5.5 A across a 5 mΩ external resistor. It also supports constant current mode of
operation in power adapter application as a provider.
1.2.7
PFET gate drivers on VBUS path
CCG3PA has two integrated PFET gate drivers to drive external PFETs on the VBUS provider and consumer path.
The VBUS_P_CTRL gate driver has an active pull-up, and thus can drive high, low or High-Z.
The VBUS_C_CTRL gate driver can drive only low or high-Z, thus requiring an external pull-up. These pins are
VBUS voltage-tolerant.
1.2.8
VBUS discharge FETs
CCG3PA also has two integrated VBUS discharge FETs used to discharge VBUS to meet the USB PD specification
timing on a detach condition. VBUS Discharge FET on the provider side can be used to accelerate the ramp down
of VBUS to default 5V on the secondary side.
1.2.9
Voltage (VBUS) regulation
CCG3PA contains integrated feedback control circuitry (for AC/DC applications) for secondary side control with
analog regulation of the feedback/cathode pins to achieve the appropriate voltage on VBUS pin as per the
negotiated contract with the peer device over Type-C.
1.3
Integrated digital blocks
1.3.1
Serial Communication Blocks (SCB)
EZ-PD™ CCG3PA has two SCBs which can be configured to implement an I2C, SPI, or UART interface. The hardware
I2C blocks implement full multi-master and slave interfaces capable of multimaster arbitration. In the SPI mode,
the SCB blocks can be configured to act as master or slave.
In the I2C mode, the SCB blocks are capable of operating at speeds of up to 1 Mbps (Fast Mode Plus) and have
flexible buffering options to reduce interrupt overhead and latency for the CPU. These blocks also support I2C
that creates a mailbox address range in the memory of EZ-PD™ CCG3PA and effectively reduce I2C communi-
cation to reading from and writing to an array in memory. In addition, the blocks support 8-deep FIFOs for receive
and transmit which, by increasing the time given for the CPU to read data, greatly reduce the need for clock
stretching caused by the CPU not having read data on time.
The I2C peripherals are compatible with the I2C Standard-mode, Fast-mode, and Fast-mode Plus devices as
defined in the NXP I2C-bus specification and user manual (UM10204). The I2C bus I/Os are implemented with
GPIO in open-drain modes.
The I2C port on the SCB blocks of EZ-PD™ CCG3PA are not completely compliant with the I2C spec in the following
aspects:
• The GPIO cells for SCB 1’s I2C port are not overvoltage-tolerant and, therefore, cannot be hot-swapped or
powered up independently of the rest of the I2C system.
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EZ-PD™ CCG3PA Consumer USB Type-C port controller
Functional overview
• Fast-mode Plus has an IOL specification of 20 mA at a VOL of 0.4 V. The GPIO cells can sink a maximum of 8-mA
IOL with a VOL maximum of 0.6 V.
• Fast-mode and Fast-mode Plus specify minimum Fall times, which are not met with the GPIO cell; Slow strong
mode can help meet this spec depending on the bus load.
1.3.2
Timer/Counter/PWM Block (TCPWM)
EZ-PD™ CCG3PA has four TCPWM blocks. Each implements a 16-bit timer, counter, pulse-width modulator (PWM),
and quadrature decoder functionality. The block can be used to measure the period and pulse width of an input
signal (timer), find the number of times a particular event occurs (counter), generate PWM signals, or decode
quadrature signals.
1.4
I/O subsystem
EZ-PD™ CCG3PA has up to 12 GPIOs of which, some of them can be re-purposed to support functions of SCB (I2C,
UART, SPI). GPIO pins P0.0 and P0.1 are overvoltage-tolerant (OVT) (upto 6V).
The GPIO block implements the following:
• Seven drive strength modes:
- Input only
- Weak pull-up with strong pull-down
- Strong pull-up with weak pull-down
- Open drain with strong pull-down
- Open drain with strong pull-up
- Strong pull-up with strong pull-down
- Weak pull-up with weak pull-down
• Input threshold select (CMOS or LVTTL)
• Individual control of input and output buffer enabling/disabling in addition to the drive strength modes
• Hold mode for latching previous state (used for retaining I/O state in Deep Sleep mode)
• Selectable slew rates for dV/dt related noise control to improve EMI
During power-on and reset, the I/O pins are forced to the disable state so as not to crowbar any inputs and/or
cause excess turn-on current. A multiplexing network known as a high-speed I/O matrix is used to multiplex
between various signals that may connect to an I/O pin.
Port pins P1.0 and P1.1 can be configured to indicate Fault for OCP/SCP/OVP/UVP conditions. Any two fault condi-
tions can be mapped to two GPIOs or all the four faults can be OR’ed to indicate over one GPIO.
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Power systems overview
2
Power systems overview
CCG3PA can operate from two possible external supply sources: VBUS_IN_DISCHARGE (3.0 V–24.5 V) or VDDD
(2.7 V–5.5 V). When powered through VBUS_IN_DISCHARGE, the internal regulator generates VDDD of 3.3 V for
chip operation. The regulated supply, VDDD, is either used directly inside some analog blocks or further regulated
down to VCCD (1.8 V), which powers a majority of the core. CCG3PA has three different power modes: Active,
Sleep, and Deep Sleep. Transitions between these power modes are managed by the power system. When
powered through the VBUS_IN_DISCHARGE pin, VDDD cannot be used to power external devices and should be
connected to a 1-µF capacitor for the regulator stability only. These pins are not supported as power supplies.
Refer to the application diagrams for capacitor connections.
Table 1
CCG3PA power modes
Mode
Description
Power is valid and an internal reset source is asserted or SleepController is sequencing
the system out of reset.
Power is valid and CPU is executing instructions.
Power-on reset (POR)
ACTIVE
Power is valid and CPU is not executing instructions. All logic that is not operating is clock
gated to save power.
SLEEP
Main regulator and most blocks are shut off. DeepSleep regulator powers logic, but only
low-frequency clock is available.
DEEP SLEEP
SHV
Regulator
VBUS_IN_DISCHARGE
VBUS_C_MON_
DISCHARGE
UV/
OVP
Gate Driver
VBUS_P_CTRL
VDDD
Gate Driver
VBUS_C_CTRL
1 µF
1.8-V Regulator
VCCD
1 µF
CC
Tx/Rx
Core
CC1, CC2
VSS
GPIO
VSS
CCG3PA
Figure 1
Power system requirement block diagram
Datasheet
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EZ-PD™ CCG3PA Consumer USB Type-C port controller
Pinouts
3
Pinouts
Table 2
CCG3PA pin descriptions
24-pin 16-pin
Pin name
Description
QFN
SOIC
1
–
P1.0
Port 1 pin 0: GPIO/UART_1_CTS/I2C_SDA_1[1] / TCPWM_line_0[2]
Programmable SCP/OCP/OVP/UVP Fault indication
,
2
3
–
5
P1.1
Port 1 pin 1: GPIO/UART_1_RTS/I2C_SCL_1[1] / TCPWM_line_1[3]
Programmable SCP/OCP/OVP/UVP Fault indication
,
VBUS_P_CTRL Provider (PMOS) FET control (30-V tolerant)
0: Path ON
1: Path OFF
4
–
VBUS_C_CTRL VBUS consumer (PMOS) FET Control (30-V tolerant)
0: Path ON
Z: Path OFF
5
6
–
–
DP1/P1.2
DM1/P1.3
USB D+/Port 1 pin 2: GPIO/UART_1_TX1/AFC/QC/BC 1.2/Apple
Charging/No IEC
USB D-/Port 1 pin 3: GPIO/UART_1_RX1/AFC/QC/BC 1.2/Apple
Charging/No IEC
7
8
6
7
8
–
9
SWD_DAT_0/P0.0 Port 0 pin 0: GPIO/OVT/I2C_SDA_0/TCPWM_line_0/UART_0_CTS
SWD_CLK_0/P0.1 Port 0 pin 1: GPIO/OVT/I2C_SCL_0/TCPWM_line_1/UART_0_RTS
9
AXRES/P2.0
P2.1
Port 2 pin 0: GPIO/Alternate XRES[4]/TCPWM_line_0//UART_0_TX0
10
11
Port 2 pin 1: GPIO/TCPWM_line_1//UART_0_RX0
VBUS_C_MON_ Type C VBUS monitor with internal discharge FET
DISCHARGE
12
13
–
P2.2
Port 2 pin 2: GPIO with open drain with pull-up assist. Configurable as
GPIO_20VT/I2C_SDA_1/IEC. Tolerant to temporary short to VBUS pin.
–
P2.3
Port 2 pin 3: GPIO with open drain with pull-up assist. Configurable as
GPIO_20VT/I2C_SCL_1/IEC. Tolerant to temporary short to VBUS pin.
14
10
11
12
13
14
CC2
Communication channel 2 with dead-battery Rd bonding option/IEC.
Tolerant to temporary short to VBUS pin.
Communication channel 1 with dead-battery Rd bonding option/IEC.
Tolerant to temporary short to VBUS pin.
USB D-/Port 3 pin 1: GPIO/UART_1_RX0/AFC/QC/BC 1.2/Apple
Charging/IEC
USB D+/Port 3 pin 0: GPIO/UART_1_TX0/AFC/QC/BC 1.2/Apple
Charging/IEC
15
CC1
16
DM0/P3.1
DP0/P3.0
17
18
VBUS_IN_DIS
CHARGE
VBUS Power IN (3.0 V–24.5 V) with Internal Discharge FET
Notes
1. Out of the two SCB blocks (SCB0 and SCB1), while the SCB0’s I2C functionality is mapped out to the P0.0/P0.1
GPIO pins, the I2C functionality of SCB1 provides flexibility to have it mapped either on P1.0/P1.1 OR
P2.2/P2.3 GPIO pins.
2. TCPWM_line_0 can be mapped to port pins P1.0, P0.0, P2.0 or P2.2.
3. TCPWM_line_1 can be mapped to port pins P1.1, P0.1, P2.1 or P2.3.
4. AXRES pin will be internally pulled up during the Power On I/O initialization time (See Table 7 for more
details).
5. See Table 10 and Table 11 for specifications related to these pins.
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Pinouts
Table 2
CCG3PA pin descriptions (continued)
24-pin 16-pin
Pin name
Description
QFN
SOIC
19
16
CSP
FB
CS +: Current sense input
20
21
1
2
Voltage regulation feedback pin
CATH/COMP
GND
Cathode of voltage regulation and compensation for other applications
22
15
3
Ground
23
VDDD
Power Input: 2.7 V–5.5 V
24
4
VCCD
1.8-V Core Voltage pin (not intended for use as a power source)
Ground
–
–
EPAD
Notes
1. Out of the two SCB blocks (SCB0 and SCB1), while the SCB0’s I2C functionality is mapped out to the P0.0/P0.1
GPIO pins, the I2C functionality of SCB1 provides flexibility to have it mapped either on P1.0/P1.1 OR
P2.2/P2.3 GPIO pins.
2. TCPWM_line_0 can be mapped to port pins P1.0, P0.0, P2.0 or P2.2.
3. TCPWM_line_1 can be mapped to port pins P1.1, P0.1, P2.1 or P2.3.
4. AXRES pin will be internally pulled up during the Power On I/O initialization time (See Table 7 for more
details).
5. See Table 10 and Table 11 for specifications related to these pins.
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Table 3
GPIO ports, pins and their functionality
Protection
capability
Port 24-QFN 16-SOIC
SCB function
SPI
USB charging signal
IEC4
Fault
TCPWM
indicator
VBUS
Pin
Pin#
Pin#
UART
I2C
OVT AFC QC BC1.2 Apple
short
P0.0
7
6
UART_0_CTS SPI_1_MOSI I2C_0_ TCPWM_line_0:0
SDA
UART_0_RTS SPI_1_MISO I2C_0_ TCPWM_line_1:0
SCL
UART_1_CTS SPI_0_SEL I2C_1_ TCPWM_line_2:1
SDA:1
UART_1_RTS SPI_0_MISO I2C_1_ TCPWM_line_3:1
SCL:1
–
–
Yes
Yes
-
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
P0.1
P1.0
P1.1
8
1
2
7
–
–
–
–
Yes
Yes
-
P1.2
P1.3
P2.0
P2.1
P2.2
5
6
9
10
12
UART_1_TX1 SPI_0_MOSI
UART_1_RX1 SPI_0_CLK
UART_0_TX0 SPI_1_SEL
UART_0_RX0 SPI_1_CLK
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Yes
–
–
–
–
–
D+ D+
D+
D-
–
–
–
D+
D-
–
–
–
–
–
–
–
Yes
D-
–
D-
–
8
TCPWM_line_2:0
TCPWM_line_3:0
–
–
UART_0_TX1
–
I2C_1_ TCPWM_line_0:1
SDA:0
–
–
P2.3
13
UART_0_RX1
–
I2C_1_ TCPWM_line_1:1
SCL:0
–
Yes
–
–
–
–
–
Yes
P3.0
P3.1
17
16
13
12
UART_1_TX0
UART_1_RX0
–
–
–
–
–
–
–
–
–
–
–
–
D+ D+
D- D-
D+
D-
D+
D-
Yes
Yes
EZ-PD™ CCG3PA Consumer USB Type-C port controller
Pinouts
P1.0
VBUS_IN_DISCHARGE
1
2
3
4
5
6
18
17
16
15
14
13
DP0/P3.0
DM0/P3.1
CC1
P1.1
VBUS_P_CTRL
VBUS_C_CTRL
DP1/P1.2
EPAD
CC2
DM1/P1.3
P2.3
Figure 2
Pinout of 24-QFN package (Top view)
FB
CSP
1
16
15
14
13
12
11
10
9
CATH/ COMP
GND
2
VDDD
VBUS_IN_DISCHARGE
DP 0/P 3.0
3
SOIC
( Top View )
VCCD
VBUS_P_ CTRL
4
5
6
7
8
DM0/
P 3.1
CC1
SWD _ DAT_0/ P0.0
CC2
SWD_ CLK_0/
P0.1
AXRES/ P2.0
VBUS_C_ MON _DISCHARGE
Figure 3
Pinout of 16-SOIC package (Top view)
Datasheet
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EZ-PD™ CCG3PA Consumer USB Type-C port controller
CCG3PA programming and bootloading
4
CCG3PA programming and bootloading
There are two ways to program application firmware into a CCG3PA device:
1. Programming the device flash over SWD Interface
2. Application firmware update over CC interface
Generally, the CCG3PA devices are programmed over SWD interface only during development or during the
manufacturing process of the end product. Once the end product is manufactured, the CCG3PA device’s appli-
cation firmware can be updated via the CC bootloader interface.
4.1
Programming the device flash over SWD interface
CCG3PA family of devices can be programmed using the SWD interface. Infineon provides a programming kit
(CY8CKIT-002 MiniProg3 kit) called MiniProg3 and PSoC™ Programmer software which can be used to
program the flash as well as debug firmware. The flash is programmed by downloading the information from a
hex file. This hex file is a binary file generated as an output of building the firmware project in PSoC™ Creator
software. Click here for more information on how to use the MiniProg3 programmer. There are many third party
programmers that support mass programming in a manufacturing environment.
As shown in the block diagram in Figure 4, the SWD_0_DAT and SWD_0_CLK pins are connected to the host
programmer’s SWDIO (data) and SWDCLK (clock) pins respectively. During SWD programming, the CCG3PA
device has to be powered by the host programmer by connecting its VTARG (power supply to the target device)
to VDDD pin of CCG3PA device. While programming over SWD interface, the CCG3PA device cannot receive power
through VBUS_IN_DISCHARGE.
The CCG3PA device family does not have the XRES pin. Due to that, the XRES line from the host programmer
remains unconnected, and hence programming using Reset Mode is not supported. In other words, CCG3PA
devices are supported by power cycle programming mode only since XRES line is not used. For more details refer
to CYPDxxxx programming specifications.
Programming Hardware
Target Device from CCG3PA Family
(Only Power Cycle Programming Mode Supported)
VTARG
SWDCLK
SWDIO
XRES
VDDD
VCCD
1 µF
10 V
X7R
100 nF
10 V
X7R
SWD_0_CLK
SWD_0_DAT
AXRES
1 µF
10 V
X7R
X
While programming over SWD
interface, device cannot receive
power through VBUS_IN_DISHCARGE.
GND
VSS
GND
Figure 4
Connecting the programmer to CYPD317x device
Datasheet
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EZ-PD™ CCG3PA Consumer USB Type-C port controller
CCG3PA programming and bootloading
4.2
Application firmware update over CC interface
For bootloading CCG3PA applications, the CY4532 CCG3PA EVK can be used to send programming and configu-
ration data as Infineon specific vendor defined messages (VDMs) over the CC line. The CY4532 CCG3PA EVK’s
power board is connected to the system containing CCG3PA device on one end and a Windows PC running the
EZ-PD™ Configuration Utility as shown in Figure 5 on the other end to bootload the CCG3PA device.
USB Serial Device of
CY4532 EVK Power
Board
I2C
PC Running
EZ-PD™ Configuration
Utility
CC Line
USB Mini-B cable
CYPD317x Device to be
Bootloaded
CCG3 Device on
CY4532 EVK Power
Board
Type-C Receptacle
CY4532 CCG3PA EVK’s
Power Board
Mini-B Receptacle
Figure 5
Application firmware update over CC interface
Application firmware (FW) update feature over CC interface is intended for use during development and manufac-
turing. Infineon strongly recommends customers to use the EZ-PD™ Configuration Utility to turn off the appli-
cation FW update over CC interface in the firmware that is updated into CCG3PA’s flash before mass production.
This prevents unauthorized firmware from being updated over CC-interface in the field. Refer to the knowledge
base article KBA230192 on how to configure this in EZ-PD™ Configuration Utility.
If you desire to retain the application firmware update over CC interface feature post-production for on-field
firmware updates, contact Infineon support for further guidelines.
Datasheet
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EZ-PD™ CCG3PA Consumer USB Type-C port controller
Application diagrams
5
Application diagrams
Figure 6 and Figure 7 show the application diagrams of CCG3PA-based power adapter with opto-coupler
feedback control using 16-pin SOIC and 24-pin QFN parts respectively. In an opto-feedback power adapter,
CCG3PA implements a shunt regulator and the feedback to the primary controller is through an opto-coupler.
The current drawn through the CATH path is proportional to the potential difference between FB pin and the
internal bandgap reference voltage. At default 5-V VBUS, the FB pin will be held at the voltage set by the bandgap
reference voltage using internal VBUS resistor dividers.
If VBUS needs to be changed from default 5 V, using internal IDACs and an error amplifier, CCG3PA draws a
proportional current through the CATH pin. This in turn gets coupled to the primary controller through the
opto-coupler.
PFET Load Switch
VBUS
50 kΩ
14
5
VBUS_IN_
DISCHARGE
VBUS_P_CTRL
9
VBUS
VBUS_C_MON_
DISCHARGE
3
4
VDDD
VCCD
1 µF
100 nF
11
10
CC1
CC2
CC1
CC2
1 µF
390 pF
390 pF
5%
X7R
5%
CYPD3174-16SXQ
X7R
Type-C
Receptacle
1
2
R1
C1
FB
13
12
DP0
DM0
DP0
DM0
C2
8
CATH/
COMP
AXRES/GPIO
SWD_
SWD_
DAT_0
100 nF
CLK_0
CSP
16
GND
15
6
7
Note:
5 mΩ
R1, C1, and C2 values are selected based on
primary side controller's design.
GND
To Programming Header (Not needed for final production)
Figure 6
CCG3PA based power adapter application diagram with opto coupler feedback control
(16-pin SOIC device)
Datasheet
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2022-05-12
EZ-PD™ CCG3PA Consumer USB Type-C port controller
Application diagrams
PFET Load Switch
VBUS
50 kΩ
18
3
4
VBUS_IN_
DISCHARGE
VBUS_P_CTRL
VBUS_C_CTRL
VBUS
1, 2, 5,
6, 10
GPIO
23
24
VDDD
11
VBUS_C_MON_
DISCHARGE
1 µF
100 nF
VCCD
15
14
CC1
CC1
CC2
1 µF
CC2
390 pF
5%
X7R
390 pF
5%
CYPD3174-24LQXQ
X7R
12, 13
GPIO_20VT
FB
Type-C
Receptacle
17
20
21
R1
C1
DP0
DM0
DP0
16
9
DM0
C2
CATH/
COMP
AXRES/GPIO
SWD_
CLK_0
100 nF
SWD_
CSP
19
DAT_0
GND
22
7
8
Note:
R1, C1 and, C2 values are selected based on
primary side controller's design.
5 mΩ
GND
To Programming Header (Not needed for final production)
Figure 7
CCG3PA based power adapter application diagram with opto coupler feedback control
(24-pin QFN device)
Figure 8 shows the application diagram of CCG3PA based power adapter with direct feedback control. In this
application, VBUS is maintained at a constant voltage. The default value of VBUS upon power up (which is usually
at 5 V) is set up by choosing the appropriate resistor divider that will set the FB node at a voltage expected by the
secondary controller.
Feedback node is regulated using internal IDACs. Whenever a change in VBUS voltage is needed, CCG3PA will
either source or sink a proportional current at feedback node, based on the amount of voltage change needed.
Datasheet
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EZ-PD™ CCG3PA Consumer USB Type-C port controller
Application diagrams
PFET Load Switch
VBUS
50 kΩ
18
3
VBUS_IN_
DISCHARGE
VBUS_P_CTRL
11
4
VBUS
VBUS_C_MON_
DISCHARGE
23
24
VDDD
VCCD
VBUS_C_CTRL
1 µF
100 nF
15
14
CC1
CC2
CC1
CC2
1 µF
21
CATH/
COMP
390 pF
5%
X7R
390 pF
100 nF
R1
5%
X7R
CYPD3175-24LQXQ
SR
Type-C
Receptacle
9
Secondary
Or
Integrated
Controller
20
FB
AXRES/GPIO
FB
17
16
1, 2, 5, 6, 10,
12, 13,
DP0
DM0
DP0
GPIO
DM0
SWD_
CLK_0
SWD_
DAT_0
R2
CSP
19
GND
22
Select R1, R2 to get
the expected FB
voltage at 5V VBUS
7
8
5 mΩ
GND
To Programming Header (Not needed for final production)
Figure 8
CCG3PA based power adapter application diagram with direct feedback control
Figure 9 shows the application diagram of a CCG3PA based power adapter application with direct feedback
control for two port car charger. The car charger application can charge portable devices connected to the Type-C
and Type-A port simultaneously. The Type-C port supports USB PD 3.1, QC 4.0, Apple Charging 2.4A, and AFC. The
Type-A port supports QC 3.0, Apple Charging, and AFC.
Datasheet
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2022-05-12
EZ-PD™ CCG3PA Consumer USB Type-C port controller
Application diagrams
DC/DC Regulator 1
VBAT
Provider
FET
4
VBUS_C_CTRL
1
9
3
P1.0
VBUS_P_CTRL
18
11
P2.0/AXRES
FB
VBUS_IN_DISCHARGE
VBUS_C_MON_DIS
VBUS
20
15
14
CC1
CC2
CC1
CC2
2
P1.1
390 pF
5%
X7R
21
390 pF
5%
X7R
12 V
Supply
COMP
CYPD3175-24LQXQ
10
Type-C
Receptacle
P2.1
23
3.3 V/5 V
Regulator
2.7 V to 5.5 V
0.1 µF
VDDD
17
16
DP0/P3.0
DM0/P3.1
DPLUS
13
7
DMINUS
P2.3
5
6
P0.0/SWD_DAT_0
DP1/P1.2
DM1/P1.3
8
GND
P0.1/SWD_CLK_0
P2.2
12
VCCD
24
GND
22
CSP
19
1 µF
10 V
X7R
10 mΩ 1%
VBAT
DC/DC Regulator 2
VBUS
DPLUS
DMINUS
Pins 7 and 8 can also be connected to the
programming header (not needed for
final production)
Type-A
Receptacle
GND
Figure 9
CCG3PA based power adapter application with direct feedback control for two port car
charger
Figure 10 shows the application diagram of a CCG3PA based power bank application. It shows dual port power
bank implementation using CCG3PA device. The power bank application can charge portable devices connected
to the Type-C and Type-A port simultaneously. The Type-C port can be configured to support USB PD 3.1, QC 4.0,
Apple Charging 2.4A, and AFC. The Type-A port can be configured to support QC3.0, Apple Charging, and AFC.
The battery can be charged from Type-C and USB PD power adapters or BC1.2 power adapters.
Datasheet
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EZ-PD™ CCG3PA Consumer USB Type-C port controller
Application diagrams
Battery
Charger
Consumer
FET
EN
ILIM
Provider FET
Reg
EN
FB
R1
Select R1, R2 to get 5 V VBUS
R2
3
4
20
2
VBUS_P_CTRL
FB
P1.1
VBUS_C_CTRL
9
1
18
11
P2.0/AXRES
P1.0
VBUS_IN_DISCHARGE
VBUS_C_MON_DIS
VBUS
15
14
CC1
CC2
CC1
CC2
23
10
5 V
Regulator
2.7 V to 5.5 V
0.1 µF
VDDD
P2.1
390 pF
390 pF
5%
X7R
Battery
1S/2S
13
VBATT
P2.3
5%
499 kΩ
1%
X7R
Type-C
49.9 kΩ
1%
CYPD3171-24LQXQ
Receptacle
17
16
21
COMP
DP0/P3.0
DM0/P3.1
DPLUS
DMINUS
7
5
6
P0.0/SWD_DAT_0
P2.2
DP1/P1.2
DM1/P1.3
12
GND
P0.1/
SWD_CLK_0
VCCD
24
GND
22
CSP
19
8
1 µF
10 V
X7R
PWM/
GPIO
5 mΩ 1%
FB
EN
Reg
VBUS
DPLUS
FET
DMINUTS ype-A
Receptacle
GND
Pins 7 and 8 can also be
connected to the programming
header (not needed for final
production)
Type-A
Connect
Detect
Rsense
Figure 10
CCG3PA power bank application diagram
Datasheet
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2022-05-12
EZ-PD™ CCG3PA Consumer USB Type-C port controller
Electrical specifications
6
Electrical specifications
6.1
Absolute maximum ratings
Table 4
Absolute maximum ratings
Parameter
Description
Min
Typ
Max
Units Details/conditions
Max supply voltage relative to VSS
on VBUS_IN_DISCHARGE and
VBUS_C_MON_DISCHARGE pins
VBUS_MAX
VDDD_MAX
VCC_PIN_ABS
–
–
–
–
–
–
30
6
V
V
Max supply voltage relative to VSS
Max voltage on CC1, CC2 pins and
port pins P2.2 and P2.3 for appli-
cable devices
Absolute max
V
22[6]
VGPIO_ABS
IGPIO_ABS
GPIO voltage
Maximum current per GPIO
–0.5
–25
–
–
VDDD +0.5
25
V
mA
GPIO injection current, Max for VIH
> VDDD, and Min for VIL < VSS
Absolute max, current
IGPIO_injection
–0.5
–0.5
2200
–
–
–
0.5
6
mA
injected per pin
Applicable to port
pins P0.0 and P0.1
VGPIO_OVT_ABS OVT GPIO voltage
V
Electrostatic discharge human
body model
ESD_HBM
–
V
–
Electrostatic discharge charged
device model
Pin current for latch-up
ESD_CDM
LU
500
–
–
–
V
–
–
–100
100
mA
Contact discharge on
CC1, CC2, VBUS, P2.2
and P2.3 pins
Electrostatic discharge
IEC61000-4-2
ESD_IEC_CON
8000
–
–
V
Air discharge for
DPLUS, DMINUS, CC1,
CC2, VBUS, P2.2 and
P2.3 pins
Electrostatic discharge
IEC61000-4-2
ESD_IEC_AIR
15000
–
–
V
Note
6. As per USB PD specification, maximum allowed VBUS = 21.5 V.
Datasheet
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EZ-PD™ CCG3PA Consumer USB Type-C port controller
Electrical specifications
Table 5
Pin No.
Pin based absolute maximum ratings
Pin name Absolute minimum (Volts)
Absolute maximum (Volts)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
P1.0[8, 9]
P1.1[8, 9]
-0.5
-0.5
-0.3
-0.3
-0.5
-0.5
-0.5
-0.5
-0.5
-0.5
-0.5
-0.5
-0.5
-0.5
-0.5
-0.5
-0.5
-0.5
-0.5
-0.5
-0.5
0
VDDD + 0.5
VDDD + 0.5
VBUS_MAX
VBUS_MAX
VDDD + 0.5
VDDD + 0.5
6
VBUS_P_CTRL[7]
VBUS_C_CTRL[7]
DP1/P1.2[8, 9]
DM1/P1.3[8, 9]
SWD_DAT_0/P0.0[8]
SWD_CLK_0/P0.1[8]
AXRES*/P2.0[8, 9]
P2.1[8, 9]
6
VDDD + 0.5
VDDD + 0.5
VBUS_MAX
22
VBUS_C_MON_DISCHARGE[7]
SWD_DAT_1/P2.3/SBU[8]
SWD_CLK_1/P2.2/SBU[8]
CC1[8]
22
22
22
CC2[8]
DP0/P3.1[8, 9]
DM0/P3.0[8, 9]
VBUS_IN/ VBUS_IN_DISCHARGE
CSP[8, 9]
VDDD + 0.5
VDDD + 0.5
VBUS_MAX
VDDD + 0.5
VDDD + 0.5
VBUS_MAX
0
FB[8, 9]
CATH/COMP[7]
GND
VDDD
VCCD
-0.5
-0.5
6
2.3
Notes
7. Minimum limit applies to static/DC input when VBUS is no higher than its operational maximum.
8. Minimum limit applies to static/DC input when VDDD is no higher than its operational maximum.
9. Maximum of 6 V.
Datasheet
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EZ-PD™ CCG3PA Consumer USB Type-C port controller
Electrical specifications
6.2
Device-level specifications
All specifications are valid for –40 °C TA 105°C and TJ 120°C, except where noted.
Table 6
Spec ID
DC specifications
Parameter
Description
Min Typ Max Units Details/conditions
Power supply input
voltage
Power supply input
voltage
Power supply input
voltage
Output voltage for core
logic
Power supply decoupling
capacitor for VDDD
Power supply decoupling
capacitor for
VBUS_IN_DISHCARGE
Sinkmode,–40°CTA
SID.PWR#2
SID.PWR#2_A
SID.PWR#3
SID.PWR#5
SID.PWR#13
VDDD
VDDD
VBUS_IN
VCCD
2.7
3.0
3.0
–
–
–
5.5
5.5
24.5
–
V
V
V
V
105°C.
Sourcemode,–40°C
TA 105°C.
–
–40°C TA 105°C.
1.8
1
–
Cexc
0.8
–
µF X5R ceramic or better
µF X5R ceramic or better
SID.PWR#14
Cexv
–
0.1
–
Active mode. Typical values measured at VDDD = 5.0 V or VBUS = 5.0 V and TA = 25°C.
V
DDD = 5 V OR VBUS
=
5 V, TA = 25°C.
CC1/CC2 in Tx or Rx,
no I/O sourcing
current, 2 SCBs at
1 Mbps,
Supply current from VBUS
SID.PWR#8
IDD_A
–
10
–
–
mA
or VDDD
EA/ADC/CSA/UVOV
ON, CPU at 24 MHz.
Sleep mode. Typical values measured at VDD = 3.3 V and TA = 25°C.
VDDD = 3.3 V, TA = 25°C,
All blocks except CPU
mA are on, CC IO on,
EA/ADC/CSA/UVOV
On.
CC, I2C, WDT wakeup on.
IMO at 24 MHz.
SID25A
IDD_S
–
–
–
3
Deep Sleep mode. Typical values measured at TA = 25°C.
Power
adapter/charger
application
VBUS = 4.5 to 5.5 V. CC
Power Source = VBUS
µA = 5 V, TA = 25°C,
Type-C not attached.
CC attach, I2C and
WDT enabled for
Wakeup.
SID_PA_DS_UA IDD_PA_DS_UA Attach, I2C, WDT Wakeup
on
100
500
–
–
Power
adapter/charger
application
VBUS = 3.0 to 24.5 V. CC, I2C,
WDT Wakeup on
VBUS = 24.5 V, TA =
SID_PA_DS_A
IDD_PA_DS_A
µA
25°C,
Part is in Deep Sleep.
attached, CC I/O on,
ADC/CSA/UVOV On
Datasheet
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EZ-PD™ CCG3PA Consumer USB Type-C port controller
Electrical specifications
Table 6
Spec ID
DC specifications (continued)
Parameter Description
Min Typ Max Units Details/conditions
Power bank
application
Power source = VDDD
= 5 V, TA = 25°C,
Type-C not attached.
CC attach, I2C and
WDT enabled for
Wakeup.
Power bank source
application
VDDD = 5 V, TA= 25°C,
Part is in Deep Sleep.
attached, CC I/O on,
ADC/CSA/UVOV On.
VDDD = 3.0 to 5.5 V. CC
SID_PB_DS_UA IDD_PB_DS_UA Attach, I2C, WDT Wakeup
on
–
100
–
µA
µA
SID_P-
B_DS_A_SRC
IDD_P-
B_DS_A_SRC
VDDD = 3.0 to 5.5 V.
–
–
500
500
–
–
CC, I2C, WDT Wakeup on
Power bank sink
application
VBUS = 24.5 V, TA =
SID_P-
B_DS_A_SNK
IDD_P-
B_DS_A_SNK
VBUS 4.0 to 24.5 V.
µA 25°C,
CC, I2C, WDT Wakeup on
Part is in Deep Sleep.
Attached, CC I/O on,
ADC/CSA/UVOV On
Table 7
AC specifications
(Guaranteed by characterization)
Spec ID
SID.CLK#4
SID.PWR#17
Parameter
FCPU
TSLEEP
Description
CPU input frequency
Wakeup from Sleep mode
Min Typ Max Units Details/conditions
DC
–
–
0
48
–
MHz All VDDD
µs
–
Wakeup from Deep Sleep
mode
SID.PWR#18
TDEEPSLEEP
T_PWR_RDY
TPOR_HIZ_T
–
–
–
–
5
3
35
25
–
µs
–
Power-up to “Ready to
SYS.FES#1
ms
ms
–
–
accept I2C/CC command”
Power-on I/O initialization
time
SID.PWR#18A
6.2.1
Table 8
Spec ID
I/O
I/O DC specifications
Parameter
Description
Min Typ Max Units Details/conditions
Input voltage HIGH
threshold
Input voltage LOW
threshold
0.7 ×
SID.GIO#37
SID.GIO#38
SID.GIO#39
SID.GIO#40
VIH_CMOS
VIL_CMOS
–
–
–
–
–
V
V
V
V
CMOS input
VDDD
0.3 ×
VDDD
–
CMOS input
0.7×
VDDD
VIH_VDDD2.7- LVTTL input, VDDD < 2.7 V
VIL_VDDD2.7- LVTTL input, VDDD < 2.7 V
–
–
–
0.3 ×
VDDD
–
SID.GIO#41
SID.GIO#42
VIH_VDDD2.7+ LVTTL input, VDDD 2.7 V
VIL_VDDD2.7+ LVTTL input, VDDD 2.7 V
2.0
–
–
–
–
0.8
V
V
–
–
Datasheet
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EZ-PD™ CCG3PA Consumer USB Type-C port controller
Electrical specifications
Table 8
Spec ID
I/O DC specifications (continued)
Parameter
Description
Min Typ Max Units Details/conditions
VDDD
SID.GIO#33
SID.GIO#36
VOH_3V
Output voltage HIGH level
Output voltage LOW level
–
–
–
V
V
I
I
OH = 4 mA at 3-V VDDD
OL = 10 mA at 3-V
–0.6
VOL_3V
–
0.6
VDDD
SID.GIO#5
SID.GIO#6
RPU
RPD
Pull-up resistor value
Pull-down resistor value
3.5
3.5
5.6
5.6
8.5
8.5
k +25°C TA, all VDDD
k +25°C TA, all VDDD
Input leakage current
(absolute value)
+25°C TA, 3-V VDDD
SID.GIO#16
IIL
–
–
2
nA
Capacitance on DP0,
DM0, DP1, DMI pins.
SID.GIO#17
CPIN_A
Max pin capacitance
–
–
22
pF
Guaranteed by
characterization.
–40°C to +85°C TA, All
VDDD, all other I/OS.
SID.GIO#17A
CPIN
Max pin capacitance
–
3
7
pF
Guaranteed by
characterization.
Input hysteresis, LVTTL
Guaranteed by
SID.GIO#43
SID.GIO#44
VHYSTTL
15
40
–
–
–
mV
V
DDD 2.7 V
characterization.
V
DDD < 4.5 V.
0.05×
VDDD
VHYSCMOS
Input hysteresis CMOS
mV Guaranteed by
characterization.
Current through
protection diode to
VDDD/VSS
Maximum total sink chip
current
Guaranteed by
SID69
IDIODE
–
–
–
–
100
85
µA design.
Guaranteed by
design.
SID.GIO#45
OVT
ITOT_GPIO
mA
Input current when Pad >
VDDD for OVT inputs
10.0
0
SID.GIO#46
IIHS
–
–
µA Per I2C specification
Table 9
I/O AC specifications
(Guaranteed by characterization)
Spec ID
Parameter
Description
Min Typ Max Units Details/conditions
Rise time in Fast Strong
mode
Fall time in Fast Strong
mode
3.3-V VDDD, Cload
25 pF
3.3-V VDDD, Cload
25 pF
=
SID70
TRISEF
2
2
–
–
12
12
ns
ns
=
SID71
TFALLF
Datasheet
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EZ-PD™ CCG3PA Consumer USB Type-C port controller
Electrical specifications
Table 10
GPIO_20VT DC specifications (Applicable to port pins P2.2 and P2.3 only)
(Guaranteed by characterization)
Spec ID# Parameter
Description
Min Typ Max Units Details/conditions
SID.GPIO_20VT# GPIO_20VT_ GPIO_20VT Latch up
–140
–
140
mA Max/mincurrentinto
any input or output,
pin-to-pin,
4
I_LU current limits
pin-to-supply
SID.GPIO_20VT# GPIO_20VT_ GPIO_20VT Pull-up
RPU resistor value
1
2.5
–
–
–
25
20
2
kΩ +25°C TA, 1.4 V to
5
GPIO_20VT_Voh(min)
SID.GPIO_20VT# GPIO_20VT_ GPIO_20VT Pull-down
RPD resistor value
kΩ +25°C TA, 1.4-V to VDDD
6
SID.GPIO_20VT# GPIO_20VT_ GPIO_20VT Input leakage
16 IIL current (absolute value)
–
nA +25°C TA, 3-V VDDD
SID.GPIO_20VT# GPIO_20VT_ GPIO_20VT pin capaci-
17 CPIN tance
SID.GPIO_20VT# GPIO_20VT_ GPIO_20VT Output
36 Vol Voltage low level.
SID.GPIO_20VT# GPIO_20VT_ GPIO_20VT LVTTL Input
41 Vih_LVTTL Voltage high level.
SID.GPIO_20VT# GPIO_20VT_ GPIO_20VT LVTTL Input
42 Vil_LVTTL Voltage low level.
15
–
–
25
0.4
–
pF –40°C to +85°C TA, All
VDDD, F = 1 MHz
–
V
IOL = 2 mA
2
–
V
VDDD 2.7 V
VDDD 2.7 V
VDDD 2.7 V
–
–
0.8
–
V
SID.GPIO_20VT# GPIO_20VT_ GPIO_20VT Input
43 Vhysttl hysteresis LVTTL
15
–
40
–
mV
µA
SID.GPIO_20VT# GPIO_20VT_ GPIO_20VT Current
100
69
IDIODE
through protection diode
to VDDD/VSS
Table 11
GPIO_20VT AC specifications (Applicable to port pins P2.2 and P2.3 only)
(Guaranteed by characterization)
Spec ID#
SID.GPIO_20VT# GPIO_20VT_ GPIO_20VT Rise time in
70 TriseF Fast Strong Mode
Parameter
Description
Min Typ Max Units Details/conditions
1
–
45
ns All VDDD, Cload = 25 pF
–
SID.GPIO_20VT# GPIO_20VT_ GPIO_20VT Fall time in
2
15
ns All VDDD, Cload = 25 pF
71
TfallF
Fast Strong Mode
Datasheet
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EZ-PD™ CCG3PA Consumer USB Type-C port controller
Electrical specifications
6.3
Digital peripherals
The following specifications apply to the Timer/Counter/PWM (TCPWM) peripherals in the timer mode.
6.3.1
Pulse Width Modulation (PWM) for GPIO pins
Table 12
PWM AC specifications
(Guaranteed by characterization)
Spec ID
SID.TCPWM.3
SID.TCPWM.4
Parameter
Description
Min Typ Max Units Details/conditions
Fc max = CLK_SYS.
TCPWMFREQ Operating frequency
–
–
–
Fc
–
MHz
Maximum = 48 MHz.
TPWMENEXT Input trigger pulse width
2/Fc
ns For all trigger events
Minimum possible
width of Overflow,
Underflow, and CC
SID.TCPWM.5
TPWMEXT
Output trigger pulse width 2/Fc
–
–
ns
(Counter equals
Compare value)
outputs
Minimum time
ns between successive
counts
SID.TCPWM.5A TCRES
Resolution of counter
PWM resolution
1/Fc
1/Fc
–
–
–
–
Minimum pulse width
SID.TCPWM.5B PWMRES
ns
of PWM output
Minimum pulse width
Quadrature inputs
resolution
between
SID.TCPWM.5C QRES
1/Fc
–
–
ns
quadrature-phase
inputs
6.3.2
Table 13
(Guaranteed by characterization)
I2C
Fixed I2C DC specifications
Spec ID
Parameter
Description
Min Typ Max Units Details/conditions
Block current
SID149
II2C1
–
–
–
–
–
–
100
135
310
–
µA
µA
µA
µA
–
–
–
–
consumption at 100 kHz
Block current
consumption at 400 kHz
SID150
SID151
SID152
II2C2
II2C3
II2C4
Block current
–
consumption at 1 Mbps
I2C enabled in Deep Sleep
mode
1.4
Table 14
Fixed I2C AC specifications
(Guaranteed by characterization)
Spec ID
SID153
Parameter
FI2C1
Description
Bit rate
Min Typ Max Units Details/conditions
Mbps –
–
–
1
Datasheet
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EZ-PD™ CCG3PA Consumer USB Type-C port controller
Electrical specifications
Table 15
Fixed UART DC specifications
(Guaranteed by characterization)
Spec ID
SID160
Parameter
Description
Block current
consumption at 100 kbps
Block current
consumption at 1000 kbps
Min Typ Max Units Details/conditions
IUART1
–
–
–
–
20
µA
µA
–
–
SID161
IUART2
312
Table 16
Fixed UART AC specifications
(Guaranteed by characterization)
Spec ID
SID162
Parameter
FUART
Description
Min Typ Max Units Details/conditions
Mbps –
Bit rate
–
–
1
Table 17
Fixed SPI DC specifications
(Guaranteed by characterization)
Spec ID
SID163
Parameter
Description
Block current
consumption at 1 Mb/s
Block current
consumption at 4 Mb/s
Block current
consumption at 8 Mb/s
Min Typ Max Units Details/conditions
ISPI1
–
–
–
–
–
–
360
560
600
µA
µA
µA
–
–
–
SID164
SID165
ISPI2
ISPI3
Table 18
Fixed SPI AC specifications
(Guaranteed by characterization)
Spec ID
Parameter
Description
SPI Operating frequency
(Master; 6X oversampling)
Min Typ Max Units Details/Conditions
MHz –
SID166
FSPI
–
–
8
Table 19
Fixed SPI master mode AC specifications
(Guaranteed by characterization)
Spec ID
SID167
Parameter
Description
MOSI valid after SClock
driving edge
MISO valid before SClock
capturing edge
Previous MOSI data hold
time
Min Typ Max Units Details/conditions
TDMO
–
20
0
–
–
–
15
–
ns
ns
ns
–
Full clock, late MISO
sampling
Referred to slave
capturing edge
SID168
SID169
TDSI
THMO
–
Datasheet
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EZ-PD™ CCG3PA Consumer USB Type-C port controller
Electrical specifications
Table 20
Fixed SPI slave mode AC specifications
(Guaranteed by characterization)
Spec ID
SID170
Parameter
Description
MOSI valid before Sclock
capturing edge
Min Typ Max Units Details/conditions
TDMI
40
–
–
ns
–
42 + 3
×
TCPU
MISO valid after Sclock
driving edge
SID171
TDSO
–
–
ns TCPU = 1/FCPU
MISO valid after Sclock
driving edge in Ext Clk
mode
SID171A
TDSO_EXT
–
–
48
ns
–
Previous MISO data hold
time
SSEL valid to first SCK
valid edge
SID172
THSO
0
–
–
–
–
ns
ns
–
–
SID172A
TSSELSCK
100
6.4
System resources
6.4.1
Power-on-reset (POR) with brown out SWD interface
Table 21
Imprecise power-on reset (PRES)
(Guaranteed by characterization)
Spec ID
Parameter
Description
Min Typ Max Units Details/conditions
Power-on reset (POR)
rising trip voltage
POR falling trip voltage
SID185
VRISEIPOR
0.80
0.70
–
–
1.50
1.4
V
V
–
–
SID186
VFALLIPOR
Table 22
Precise power-on reset (POR)
(Guaranteed by characterization)
Spec ID
Parameter
Description
Min Typ Max Units Details/conditions
Brown-out detect (BOD)
trip voltage in
SID190
VFALLPPOR
1.48
1.1
–
–
1.62
1.5
V
V
–
–
Active/Sleep modes
BOD trip voltage in Deep
Sleep mode
SID192
VFALLDPSLP
Table 23
SWD interface specifications
(Guaranteed by characterization)
Spec ID
Parameter
Description
Min Typ Max Units Details/conditions
SWDCLK 1/3 CPU
SID.SWD#1
F_SWDCLK1 3.3V VDDD 5.5 V
F_SWDCLK2 2.7V VDDD 3.3 V
–
–
–
–
–
–
14
7
MHz
MHz
ns
clock frequency
SWDCLK 1/3 CPU
clock frequency
SID.SWD#2
SID.SWD#3
SID.SWD#4
T_SWDI_
SETUP
0.25
× T
0.25
× T
T = 1/f SWDCLK
–
–
–
T_SWDI_
T = 1/f SWDCLK
HOLD
–
ns
Datasheet
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EZ-PD™ CCG3PA Consumer USB Type-C port controller
Electrical specifications
Table 23
SWD interface specifications (continued)
(Guaranteed by characterization)
Spec ID
Parameter
T_SWDO_
VALID
T_SWDO_
HOLD
Description
T = 1/f SWDCLK
Min Typ Max Units Details/conditions
0.50×
SID.SWD#5
–
1
–
–
ns
ns
–
–
T
SID.SWD#6
T = 1/f SWDCLK
–
6.4.2
Internal main oscillator
Table 24
IMO DC specifications
(Guaranteed by design)
Spec ID
Parameter
Description
IMO operating current at
48 MHz
Min Typ Max Units Details/conditions
1000 µA
SID218
IIMO1
–
–
–
Table 25
Spec ID
IMO AC specifications
Parameter
Description
Min Typ Max Units Details/conditions
Frequency variation at 24,
36, and 48 MHz (trimmed)
SID.CLK#13
SID226
FIMOTOL
–
–
–
–
–
±2
7
%
µs
ps
–
Guaranteed by
characterization.
Guaranteed by
characterization.
TSTARTIMO
IMO start-up time
SID228
TJITRMSIMO2 RMS jitter at 24 MHz
FIMO IMO frequency
145
–
Only 3 frequencies
SID.CLK#1
24
36
48
MHz supported: 24 MHz,
36 MHz, and 48 MHz.
6.4.3
Internal low-speed oscillator power down
Table 26
ILO DC specifications
(Guaranteed by design)
Spec ID
SID231
SID233
Parameter
IILO1
IILOLEAK
Description
ILO operating current
ILO leakage current
Min Typ Max Units Details/conditions
–
–
0.3 1.05
15
µA
nA
–
–
2
Table 27
ILO AC specifications
Parameter
Spec ID
Description
Min Typ Max Units Details/conditions
Guaranteed by
SID234
TSTARTILO1
ILO start-up time
–
–
2
ms
%
characterization
Guaranteed by
characterization
kHz –
SID238
TILODUTY
FILO
ILO duty cycle
ILO frequency
40
20
50
40
60
80
SID.CLK#5
Datasheet
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EZ-PD™ CCG3PA Consumer USB Type-C port controller
Electrical specifications
Table 28
Spec ID
PD DC specifications
Parameter
Description
Min Typ Max Units Details/conditions
DFP CC termination for
default USB Power
DFP CC termination for
1.5 A power
DFP CC termination for
3.0 A power
UFP CC termination
SID.PD.1
SID.PD.2
Rp_std
64
80
96
µA
–
–
–
Rp_1.5A
166 180 194.4 µA
304 330 356.4 µA
SID.PD.3
SID.PD.4
Rp_3.0A
Rd
4.59 5.1 5.61
kΩ
–
UFP (Power bank) Dead
Battery CC termination on 4.08 5.1 6.12
CC1 and CC2
All supplies forced to
SID.PD.5
Rd_DB
kΩ 0 V and 1.32 V applied
at CC1 or CC2
Ground offset tolerated by
BMC receiver
Relative to the remote
BMC transmitter.
SID.PD.6
Vgndoffset
–500
–
500
mV
Table 29
LS-CSA specifications
Parameter
Spec ID
Description
Min Typ Max Units Details/conditions
Guaranteed by
SID.LSCSA.1
SID.LSCSA.2
SID.LSCSA.3
SID.LSCSA.4
SID.LSCSA.5
SID.LSCSA.6
SID.LSCSA.7
SID.LSCSA.8
SID.LSCSA.9
SID.LSCSA.10
SID.LSCSA.11
Cin_inp
CSP input capacitance
7
–
–
–
–
–
–
–
–
–
–
–
10
15
10
6
pF
%
%
%
%
%
%
%
%
%
%
characterization
CSA accuracy 5 mV <
Vsense < 10 mV
CSA accuracy 10 mV <
Vsense < 15 mV
CSA accuracy 15 mV <
Vsense < 20 mV
CSA accuracy 20 mV <
Vsense < 30 mV
CSA accuracy 30 mV <
Vsense < 50 mV
CSA accuracy 50 mV <
Vsense
Csa_Acc1
Csa_Acc2
Csa_Acc3
Csa_Acc4
Csa_Acc5
Csa_Acc6
–15
–10
–6
–5
5
–4
4
Active mode
–4
4
Csa_SCP_
Acc1
Csa_SCP_
Acc2
Csa_SCP_
Acc3
Csa_SCP_
Acc4
–
CSA SCP 80 mV
CSA SCP 100 mV
CSA SCP 150 mV
CSA SCP 200 mV
30
24
16
12
16.5
–
13.4
–9.4
–7.5
Nominal gain values
supported: 5, 10, 20, 35,
50, 75, 125, 150
SID.LSCSA.12
Av
5
–
150
V/V
–
Guaranteed by
SID.LSCSA.24
SID.LSCSA.31
Av1_E_Trim Gain Error
Av_E_SCP Gain Error of SCP stage
–3
–
–
3
%
%
characterization
Guaranteed by
–3.5
3.5
characterization
Datasheet
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EZ-PD™ CCG3PA Consumer USB Type-C port controller
Electrical specifications
Table 30
LS-CSA AC specifications
(Guaranteed by characterization)
Spec ID Parameter
Description
Min Typ Max Units Details/conditions
Delay from OCP threshold
trip to output GPIO toggle
Delay from OCP threshold
trip to external PFET
power gate turn off
Delay from SCP threshold
trip to output GPIO toggle
Delay from SCP threshold
trip to external PFET
power gate turn off
Available on P1.0 or
SID.LSCSA.AC.1 TOCP_GPIO
SID.LSCSA.AC.2 TOCP_Gate
SID.LSCSA.AC.3 TSCP_GPIO
SID.LSCSA.AC.4 TSCP_Gate
SID.LSCSA.AC.5 TSR_GPIO
–
–
–
–
–
–
–
–
–
–
20
50
15
50
20
µs
µs
µs
µs
µs
P1.1
–
Available on P1.0 or
P1.1
–
Delay from SR threshold
trip to output GPIO toggle
Available on P1.0 or
P1.1
Table 31
UV/OV specifications
(Guaranteed by characterization)
Spec ID
Parameter
Description
Min Typ Max Units Details/conditions
Overvoltage threshold
accuracy, 4.0 V to 11.0 V
Overvoltage threshold
accuracy, 11 V to 27.4 V
Undervoltage threshold
accuracy, 2.7 V to 3.3 V
Undervoltage threshold
accuracy, 3.3 V to 4.0 V
Undervoltage threshold
accuracy, 4.0 V to 11.0 V
Undervoltage threshold
accuracy, 11.0 V to 22.0 V
SID.UVOV.1
VTHOV1
–3
–3.2
-4
–
–
–
–
–
–
3
3.2
4
%
%
%
%
%
%
SID.UVOV.2
SID.UVOV.3
SID.UVOV.4
SID.UVOV.5
SID.UVOV.6
VTHOV2
VTHUV1
VTHUV2
VTHUV3
VTHUV4
Active mode
–3.5
–3
3.5
3
–2.9
2.9
Table 32
UV/OV AC specifications
(Guaranteed by characterization)
Spec ID
Parameter
Description
Min Typ Max Units Details/conditions
Delay from UV threshold
trip to output GPIO toggle
Delay from UV threshold
trip to external PFET
power gate turn off
Available on P1.0 or
SID.UVOV.AC.1 TOV_GPIO
SID.UVOV.AC.2 TOV_GATE
SID.UVOV.AC.3 TUV_GPIO
–
–
–
–
–
–
20
50
20
µs
µs
µs
P1.1
–
Delay from UV threshold
trip to output GPIO toggle
Available on P1.0 or
P1.1
Datasheet
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EZ-PD™ CCG3PA Consumer USB Type-C port controller
Electrical specifications
6.4.4
Gate driver specifications
Table 33
Gate driver DC specifications
Spec ID
Parameter
Description
Min Typ Max Units Details/conditions
Applicable on
VBUS_P_CTRL and
SID.GD.1
SID.GD.2
RPD
Pull-down resistance
–
–
–
–
3
4
kΩ
VBUS_C_CTRL to turn
ON external PFET.
Applicable on
RPU
Pull-up resistance
kΩ VBUS_P_CTRL to turn
OFF external PFET
Pull-down current sink at
drive strength of 1
Pull-down current sink at
drive strength of 2
Pull-down current sink at
drive strength of 4
Pull-down current sink at
drive strength of 8
Pull-down current sink at
drive strength of 16
Pull-down current sink at
drive strength of 32
Pin leakage on
VBUS_P_CTRL
Pin leakage on
VBUS_C_CTRL
Pin leakage on
VBUS_P_CTRL
Pin leakage on
VBUS_C_CTRL
Pin leakage on
VBUS_P_CTRL
Pin leakage on
VBUS_C_CTRL
SID.GD.3
SID.GD.4
SID.GD.5
SID.GD.6
SID.GD.7
SID.GD.8
SID.GD.9
SID.GD.10
SID.GD.11
SID.GD.12
SID.GD.13
SID.GD.14
IPD0
25
50
140
280
560
1120
–
–
75
150
300
580
1200
2300
–
µA
IPD1
–
µA
I-mode (current mode)
pull down at
IPD2
–
µA
5 V. Applicable on
VBUS_P_CTRL and
VBUS_C_CTRL to turn
IPD3
–
µA
ON external PFET
µA
IPD4
–
IPD5
–
µA
+25°C TJ, 5-V VDDD, 20-V
VBUS
+25°C TJ, 5-V VDDD, 20-V
VBU
+85°C TJ, 5-V VDDD, 20-V
VBU
+85°C TJ, 5-V VDDD, 20-V
VBU
I_leak_p1
I_leak_c1
I_leak_p2
I_leak_c2
I_leak_p3
I_leak_c3
0.003
µA
–
0.003
–
µA
–
–
–
–
–
2
µA
–
2
µA
+125°C TJ, 5-V VDDD
,
,
–
7
µA
µA
20-V VBU
+125°C TJ, 5-V VDDD
20-V VBU
–
7
Datasheet
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EZ-PD™ CCG3PA Consumer USB Type-C port controller
Electrical specifications
Table 34
Gate driver AC specifications
(Guaranteed by characterization)
Spec ID
Parameter
Description
Min Typ Max Units Details/conditions
Cload = 2 nF, Delay to
VBUS –1.5 V from initi-
ation of falling edge,
Pull down delay on
VBUS_C_CTRL
SID.GD.15
TPD1
–
–
–
–
–
–
2
5
2
µs VBUS = 5 V to 20 V,
50 K tied between
VBUS_C_CTRL and
VBUS
80% to 20%, 50 K tied
between
V/µs VBUS_C_CTRL and
VBUS, Cload = 2 nF,
Vinitial = 24 V
Discharge rate of output
node on VBUS_C_CTRL
SID.GD.16
SID.GD.17
Tr_discharge
Cload = 2 nF, Delay to
VBUS –1.5 V from initi-
ation of falling edge,
µs VBUS = 5 V to 20 V, 50 K
tied between
Pull down delay on
VBUS_P_CTRL
TPD2
VBUS_C_CTRL and
VBUS
Cload = 2 nF, Delay to
VBUS–1.5 V from initi-
ation of falling edge,
µs VBUS = 5 V to 20 V,
50 K tied between
VBUS_C_CTRL and
VBUS
Pull up delay on
VBUS_P_CTRL
SID.GD.18
TPU
–
–
18
Cload = 2 nF, 20% to
V/µs 80% of VBUS_P_CTRL
range
Cload = 2 nF, 80% to
V/µs 20% of VBUS_P_CTRL
range
Output slew rate on
VBUS_P_CTRL
SID.GD.19
SID.GD.20
SRPU
SRPD
–
–
–
–
5
5
Output slew rate on
VBUS_P_CTRL
Datasheet
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EZ-PD™ CCG3PA Consumer USB Type-C port controller
Electrical specifications
Table 35
Spec ID#
VBUS discharge specifications
Parameter Description
Min Typ Max Units Details/conditions
SID.VBUS.DISC
.6
SID.VBUS.DISC
.7
SID.VBUS.DISC
.8
SID.VBUS.DISC
.9
20-V NMOS ON current for
DS = 1
20-V NMOS ON current for
DS = 2
20-V NMOS ON current for
DS = 4
20-V NMOS ON current for
DS = 8
I1
0.15
0.4
0.9
2
–
–
–
–
–
1
2
mA
I2
mA
I4
4
mA Measured at 0.5 V
mA
I8
8
SID.VBUS.DISC
.10
20-V NMOS ON current for
DS = 16
I16
4
10
mA
When VBUS is
SID.VBUS.DISC VBUS_Stop_ Error percentage of final
discharged to 5 V.
–
–
10
%
.11
Error
VBUS value from setting
Guaranteed by
characterization.
Table 36
Voltage (VBUS) regulation DC specifications
Spec ID#
Parameter
Description
Min Typ Max Units Details/conditions
Active mode shunt
regulator at 3 V with
bandgap
SID.DC.VR.1
V_IN_3
V(pad_in) at 3-V target
2.85
3
3.15
V
Active mode shunt
regulator at 5 V
Active mode shunt
regulator at 9 V
Active mode shunt
regulator at 15 V
Active mode shunt
regulator at 20 V
SID.DC.VR.2
SID.DC.VR.3
SID.DC.VR.4
SID.DC.VR.5
V_IN_5
V_IN_9
V_IN_15
V_IN_20
V(pad_in) at 5-V target
V(pad_in) at 9-V target
V(pad_in) at 15-V target
V(pad_in) at 20-V target
4.75
8.55
5
9
5.25
9.45
V
V
V
V
14.2
5
15 15.75
19
20
3
21
DeepSleepmodeshunt
regulator at 3 V with
bandgap
SID.DC.VR.6
V_IN_3_DS
V(pad_in) at 3-V target
2.7
3.3
V
DeepSleepmodeshunt
regulator at 5 V
DeepSleepmodeshunt
regulator at 9 V
DeepSleepmodeshunt
regulator at 15 V
SID.DC.VR.7
SID.DC.VR.8
SID.DC.VR.9
V_IN_5_DS
V_IN_9_DS
V_IN_15_DS
V(pad_in) at 5-V target
V(pad_in) at 9-V target
V(pad_in) at 15-V target
4.5
8.1
5
9
5.5
9.1
V
V
V
13.5 15
16.5
DeepSleepmodeshunt
regulator at 20 V
–
SID.DC.VR.10 V_IN_20_DS
SID.DC.VR.11 IKA_OFF
SID.DC.VR.12 IKA_ON
V(pad_in) at 20-V target
Off-state cathode current
Current through cathode
pin
18
–
20
–
22
10
10
V
µA
mA
–
–
–
Datasheet
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Electrical specifications
Table 37
Spec ID
VBUS short protection specifications
Parameter Description
Short-to-VBUS
Min Typ Max Units Details/conditions
V_SHORT_T system-side clamping
Guaranteed by
SID.VSP.1
–
9
–
V
RIGGER
voltage on the
CC/P2.2/P2.3 pins
characterization.
Table 38
VBUS DC regulator specifications
Spec ID
Parameter
VBUS_-
DETECT
Description
VBUS detect threshold
voltage
Min Typ Max Units Details/conditions
1.08 2.62
SID.VREG.2
–
V
–
Table 39
Spec ID
VBUS AC regulator specifications
Parameter
Description
Min Typ Max Units Details/conditions
Total startup time for the
regulator supply outputs
Guaranteed by
characterization.
SID.VREG.3
Tstart
–
–
200
µs
6.4.5
Analog-to-digital converter
Table 40
ADC DC specifications
(Guaranteed by characterization)
Spec ID
Parameter
Description
Min Typ Max Units Details/conditions
SID.ADC.1
Resolution ADC resolution
–
8
–
Bits –
Reference voltage
SID.ADC.2
SID.ADC.2A
SID.ADC.3
INL
INL
DNL
Integral non-linearity
–2.5
–
2.5
LSB
generated from VDDD
Reference voltage
Integral non-linearity
–1.5
–2.5
–
–
1.5
2.5
LSB generated from
bandgap
Reference voltage
generated from VDDD
Reference voltage
LSB generated from
bandgap
Differential non-linearity
Differential non-linearity
LSB
SID.ADC.3A
SID.ADC.4
SID.ADC.6
DNL
–1.5
–1.5
–
–
1.5
1.5
Gain Error
VREF_ADC2
Gain error
ADC reference voltage
when generated from band 1.96 2.0
gap.
LSB –
Reference voltage
generated from
bandgap
2.04
V
Table 41
ADC AC specifications
(Guaranteed by design)
Spec ID
Parameter
Description
Min Typ Max Units
Details/conditions
Rate of change of sampled
voltage signal
–
SID.ADC.7
SLEW_Max
–
–
3
V/ms
Datasheet
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EZ-PD™ CCG3PA Consumer USB Type-C port controller
Electrical specifications
6.4.6
Memory
Table 42
Flash AC specifications
Spec ID
Parameter
Description
Min Typ Max Units
Details/conditions
FLASH_ERAS
E
–40°C TA 85°C, all
SID.MEM#3
SID.MEM#4
SID.MEM#8
Row erase time
–
–
–
–
–
–
15.5 ms
VDDD
FLASH_WRIT Row (Block) write time
(erase and program)
–40°C TA 85°C, all
VDDD
20
7
ms
ms
E
FLASH_ROW Row program time after
_PGM erase
25°C TA 55°C, all
VDDD
SID178
SID180
TBULKERASE Bulk erase time (32 KB)
–
–
–
–
35
7.5
ms
s
–
–
–
TDEVPROG
Total device program time
Flash retention, TA ≤ 55°C,
100K P/E cycles
SID182
FRET1
20
10
3
–
–
–
–
–
–
years
years
years
Flash retention, TA ≤ 85°C,
–
–
SID182A
SID182B
FRET2
FRET3
10K P/E cycles
Flash retention, TA ≤105°C,
10K P/E cycles
Datasheet
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EZ-PD™ CCG3PA Consumer USB Type-C port controller
Ordering information
7
Ordering information
Table 43 lists the EZ-PD™ CCG3PA part numbers and features.
Table 43 CCGPA ordering information
Termination
Package
type
MPN
Application
Role
Bootloader[10]
Si ID
resistor
CYPD3171-24LQXQ Power bank
Power adapter
RP, RD, RD-DB DRP UFP CC bootloader
DFP CC with opto
24-Pin QFN 2003
16-Pin
2001
CYPD3174-16SXQ
based on opto
RP
RP
RP
DFP coupler feedback
bootloader
SOIC
coupler feedback
Power adapter
CYPD3174-24LQXQ based on opto
coupler feedback
Power adapter
CYPD3175-24LQXQ based on direct
feedback
DFP CC with opto
DFP coupler feedback
bootloader
24-Pin QFN 2000
24-Pin QFN 2002
DFP CC with direct
DFP
feedback bootloader
7.1
Ordering code definitions
X
X
XX XX XX
X
X
X
PD
CY
-
T = Tape and reel (Optional)
Temperature grade:
Q = Extended industrial (-40°C to +105°C)
Lead: X = Pb-free
Package type: LQ = QFN; S = SOIC
Number of pins in the package
Application and feature combination designation
Number of Type-C ports: 1 = 1 port, 2 = 2 port
Product type: 3 = Third-generation product family
Marketing code: PD = Power Delivery product family
Company ID: CY = Infineon
Note
10.It is assumed that VBUS is at 5 V by default. Bootloader execution is not responsible for controlling the
generation of 5 V VBUS.
Datasheet
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EZ-PD™ CCG3PA Consumer USB Type-C port controller
Packaging
8
Packaging
Table 44
Parameter
TA
Package characteristics
Description
Operating ambient temperature Extended Indus-
trial
Conditions
Min
-40
Typ
25
Max
105
Units
°C
TJ
Operating junction temperature Extended Indus-
trial
-40
25
120
°C
TJA
TJC
TJA
TJC
Package JA (24-QFN)
Package JC (24-QFN)
Package JA (16-SOIC)
Package JC (16-SOIC)
–
–
–
–
–
–
–
–
–
–
–
–
19.98
4.78
84
°C/W
°C/W
°C/W
°C/W
33.9
Table 45
Solder reflow peak temperature
Package
Maximum peak temperature
Maximum time within 5°C of peak temperature
24-pin QFN
16-pin SOIC
260°C
260°C
30 seconds
30 seconds
Table 46
Package moisture sensitivity level (MSL), IPC/JEDEC J-STD-2
Package
24-pin QFN
16-pin SOIC
MSL
MSL3
MSL3
Datasheet
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EZ-PD™ CCG3PA Consumer USB Type-C port controller
Packaging
o
NOTES
DIMENSIONS
1. ALL DIMENSIONS ARE IN MILLIMETERS.
SYMBOL
MIN. NOM. MAX.
0.60
2. DIE THICKNESS ALLOWABLE IS 0.305 mm MAXIMUM(.012 INCHES MAXIMUM)
3. DIMENSIONING & TOLERANCES CONFORM TO ASME Y14.5M. -1994.
A
A1
4. THE PIN #1 IDENTIFIER MUST BE PLACED ON THE TOP SURFACE OF THE
PACKAGE BY USING INDENTATION MARK OR OTHER FEATURE OF
PACKAGE BODY.
0.00
0.05
A3 (Option 1)
A3 (Option 2)
0.152 REF
0.127 REF
0.25
5. EXACT SHAPE AND SIZE OF THIS FEATURE IS OPTIONAL.
6. PACKAGE WARPAGE MAX 0.08 mm.
0.18
2.65
0.30
2.85
b
7. APPLIED FOR EXPOSED PAD AND TERMINALS. EXCLUDE EMBEDDING PART
OF EXPOSED PAD FROM MEASURING.
D
4.00 BSC
2.75
D2
E
8. APPLIED ONLY TO TERMINALS.
4.00 BSC
2.75
9. JEDEC SPECIFICATION NO. REF: N.A.
E2
L
2.65
0.30
2.85
0.50
10. INDEX FEATURE CAN EITHER BE AN OPTION 1 : "MOUSE BITE" OR
OPTION 2 : CHAMFER.
0.40
e
0.50 BSC
R
0.09
002-16934 *E
Figure 11
24-pin QFN package outline
Datasheet
38 of 45
002-16951 Rev. *H
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EZ-PD™ CCG3PA Consumer USB Type-C port controller
Packaging
51-85068 *F
Figure 12
16-pin SOIC package outline
Datasheet
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EZ-PD™ CCG3PA Consumer USB Type-C port controller
Acronyms
9
Acronyms
Table 47
Acronyms used in this document
Acronym
Description
ADC
AES
API
analog-to-digital converter
advanced encryption standard
application programming interface
Arm®
CC
advanced RISC machine, a CPU architecture
configuration channel
CCG3
CPU
CRC
CS
Cable Controller Generation 3
central processing unit
cyclic redundancy check, an error-checking protocol
current sense
DFP
DIO
DRP
EEPROM
downstream facing port
digital input/output, GPIO with only digital capabilities, no analog. See GPIO.
dual role port
electrically erasable programmable read-only memory
electronically marked cable assembly, a USB cable that includes an IC that reports cable
characteristics (e.g., current rating) to the Type-C ports
EMCA
EMI
ESD
FS
electromagnetic interference
electrostatic discharge
full-speed
GPIO
IC
general-purpose input/output
integrated circuit
IDE
integrated development environment
Inter-Integrated Circuit, a communications protocol
internal low-speed oscillator, see also IMO
internal main oscillator, see also ILO
input/output, see also GPIO
low-dropout regulator
I2C, or IIC
ILO
IMO
I/O
LDO
LVD
low-voltage detect
LVTTL
MCU
NC
low-voltage transistor-transistor logic
microcontroller unit
no connect
NMI
NVIC
opamp
OCP
OTP
OVP
OVT
PCB
nonmaskable interrupt
nested vectored interrupt controller
operational amplifier
overcurrent protection
over temperature protection
overvoltage protection
overvoltage tolerant
printed circuit board
Datasheet
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EZ-PD™ CCG3PA Consumer USB Type-C port controller
Acronyms
Table 47
Acronyms used in this document (continued)
Acronym
Description
PD
power delivery
PGA
PHY
POR
PRES
PSoC™
PWM
RAM
RISC
RMS
RTC
RX
programmable gain amplifier
physical layer
power-on reset
precise power-on reset
programmable system-on-chip
pulse-width modulator
random-access memory
reduced-instruction-set computing
root-mean-square
real-time clock
receive
SAR
SCL
SCP
SDA
S/H
successive approximation register
I2C serial clock
short circuit protection
I2C serial data
sample and hold
SHA
SPI
SRAM
SWD
TX
secure hash algorithm
Serial Peripheral Interface, a communications protocol
static random access memory
serial wire debug, a test protocol
transmit
a new standard with a slimmer USB connector and a reversible cable, capable of sourcing
up to 100 W of power
Type-C
UART
USB
Universal Asynchronous Transmitter Receiver, a communications protocol
Universal Serial Bus
USBIO
UVP
USB input/output, CCG2 pins used to connect to a USB port
undervoltage protection
XRES
external reset I/O pin
Datasheet
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Document conventions
10
Document conventions
10.1
Units of measure
Table 48
Units of measure
Symbol
Unit of measure
°C
Hz
degrees Celsius
hertz
KB
kHz
k
Mbps
MHz
M
Msps
µA
1024 bytes
kilohertz
kilo ohm
megabits per second
megahertz
mega-ohm
mega samples per second
microampere
microfarad
microsecond
microvolt
µF
µs
µV
µW
mA
ms
mV
nA
microwatt
milliampere
millisecond
millivolt
nanoampere
nanosecond
ohm
ns
pF
picofarad
ppm
ps
s
parts per million
picosecond
second
sps
V
samples per second
volt
Datasheet
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EZ-PD™ CCG3PA Consumer USB Type-C port controller
Revision history
Revision history
Document
Date of release
Description of changes
version
**
2016-10-13
2016-12-13
New datasheet
*A
Changed datasheet status to Preliminary.
Updated Features.
Updated Logic block diagram.
Updated Functional overview
Updated Figure 2, Figure 3, Figure 6, Figure 8, Figure 9, and Figure 10.
Updated Pinouts.
Updated Table 4 with VCC_PIN_ABS and VSBU_PIN_ABS parameters.
Added Q-temp parts in Table 43.
*B
*C
2017-01-18
2017-03-22
Updated EZ-PD™ CCG3PA Datasheet, USB Type-C Port Controller, Features,
I/O subsystem, CPU, Charger detection, and Ordering information.
Updated Table 2 and Table 4.
Updated Figure 6 through Figure 10.
Updated Sales page.
Updated Figure 2, Figure 6, Figure 8, Figure 10, Table 1,Table 2, Table 4,
Table 43, Features, Logic block diagram, Functional overview, Power systems
overview, Ordering code definitions, Acronyms.
Added Internal block diagram.
Added Table 6 through Table 42 in Device-level specifications.
Updated compliance with USB spec in Sales, Solutions, and Legal Information.
Updated Infineon logo.
*D
2017-05-19
Added Application Diagram description before Figure 6, Figure 8, Figure 9, and
Figure 10.
Added Figure 1.
Added CCG3PA programming and bootloading section.
Added Revision history section.
Added Table 3.
Updated Figure 3, Figure 4, Figure 6, Figure 8, Figure 9, and Figure 10.
Updated Table 2, Table 4, Table 6, and Table 43.
Updated Figure 11 (spec 002-16934 Rev. ** to *A) in Packaging.
Updated Infineon logo, Sales page, and Copyright information.
*E
2017-12-06
Removed Preliminary document status.
Updated System-level fault protection, Power, and System-level ESD
protection.
Updated Internal block diagram
Updated Figure 2.
Table 2: Updated Pins 12 and 13. Added Note 5.
Updated Figure 6.
Added Figure 7.
Table 4: Updated max value for VCC_PIN_ABS
Table 6: Removed SID_DS and updated typ value for SID_PB_DS_UA.
Table 8: Added new SID.GIO#17 spec and changed SID.GIO#17 to SID.GIO#17A.
Added Table 10 and Table 11.
Table 13: Updated max value for SID149.
Table 23; Added “Guaranteed by Characterization”
Table 25: Updated Conditions for SID226 and SID228. Updated typ value and
conditions for SID.CLK#1.
Table 27: Updated Conditions for SID234 and SID238.
Table 29: Updated min, typ, and max values for SID.LSCSA.1,SID.LSCSA.7, and
SID.LSCSA.24
Datasheet
43 of 45
002-16951 Rev. *H
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EZ-PD™ CCG3PA Consumer USB Type-C port controller
Revision history
Document
Date of release
Description of changes
version
*E (Contd)
2017-12-06
Updated Conditions for SID.GIO#17A, SID.GIO#43, SID.GIO#44, SID.GIO#45, and
SID69.
Table 32: Added “Guaranteed by Characterization”
Table 33: Added SID.GD.9, SID.GD.10, SID.GD.11, SID.GD.12, SID.GD.13, SID.GD.14.
Changed description of spec IDs SID.GD.1 to SID.GD.8.
Table 34: Renumbered all spec IDs starting from SID.GD.15 to SID.GD.20. Modified
max values of SID.GD.15, SID.GD.17 and SID.GD.18. Modified Details/Conditions of
all parameters.
Table 35: Removed spec IDs SID.VBUS.DISC.1 to SID.VBUS.DISC5. Renumbered
SID.VBUS.DISC6 to SID.VBUS.DISC11. Added new spec IDs SID.VBUS.DISC6 to
SID.VBUS.DISC10.
Table 36: Added V_IN_3 and V_IN3_DS parameters and renumbered spec IDs from
SID.DC.VR.1 to SID.DC.VR.12.
Added Table 37.
Table 40: Updated min and max values for SID.ADC.4.
Table 43: Added new MPN CYPD3174-24LQXQ. Modified “Application” column of
CYPD3174-16SXQ and CYPD3175-24LQXQ MPNs.
Removed Errata.
Added Table 44, Table 45 and Table 46 to Packaging section.
*F
2018-03-02
Added “The voltage reference for the ADCs is generated either from the VDDD
supply or from internal bandgap. When sensing the GPIO pin voltage with an ADC,
the pin voltage cannot exceed the VDDIO supply value” to Analog-to-digital
converter (ADC) section.
Table 2: Updated the Description “GPIO with Open drain with pull-up assist.
Configurable as GPIO_20VT/I2C_SDA_1/IEC. Tolerant to temporary short to VBUS
pin” for Pins P2.2 and P2.3.
Table 8: Removed SBU1, SBU2 reference in Details/Conditions for Spec ID
SID.GIO#17.
Table 33: Moved “0.003” to Typ column for the Spec ID SID.GD.9 and SID.GD.10.
Table 13: Updated typical and max values for II2C4 parameter.
Table 10: Removed GPIO_20VT_Voh parameter.
Table 29: Updated max values of Csa_SCP_Acc parameters.
Table 40: Updated the Description of Spec ID SID.ADC.6 as “ADC reference voltage
when
generated from band gap.”. Removed SID.ADC.5 parameter and added
SID.ADC.2A and SID.ADC.3A parameters. Updated Details/Conditions of SID.ADC.2
and SID.ADC3 parameters.
Table 36: Added units (V) to SID.DC.VR.3, SID.DC.VR.4 and SID.DC.VR.5 param-
eters.
Updated VBUS short protection and I/O subsystem sections.
Updated Table 3 with information on Fault Indicator and VBUS Short Protection
Capability.
Updated Application diagrams section.
*G
*H
2020-04-20
2022-05-12
Updated Application firmware update over CC interface section. Added
reference to KBA230192.
Updated 24-pin QFN package outline (002-16934 *A to *C).
Updated 16-pin SOIC package outline (51-85068 *E to *F).
Updated Sales, Solutions, and Legal Information and Copyright year.
Changed USB PD revision from 3.0 to 3.1.
Updated Figure 2 and Figure 11 (spec revision from 002-16934 *C to *E).
Added Table 5.
Migrated to the Infineon template.
Datasheet
44 of 45
002-16951 Rev. *H
2022-05-12
Please read the Important Notice and Warnings at the end of this document
Trademarks
All referenced product or service names and trademarks are the property of their respective owners.
IMPORTANT NOTICE
For further information on the product, technology,
The information given in this document shall in no
event be regarded as a guarantee of conditions or
characteristics (“Beschaffenheitsgarantie”).
Edition 2022-05-12
Published by
delivery terms and conditions and prices please
contact your nearest Infineon Technologies office
(www.infineon.com).
Infineon Technologies AG
81726 Munich, Germany
With respect to any examples, hints or any typical
values stated herein and/or any information
regarding the application of the product, Infineon
Technologies hereby disclaims any and all
warranties and liabilities of any kind, including
without limitation warranties of non-infringement of
intellectual property rights of any third party.
WARNINGS
Due to technical requirements products may contain
dangerous substances. For information on the types
in question please contact your nearest Infineon
Technologies office.
© 2022 Infineon Technologies AG.
All Rights Reserved.
Except as otherwise explicitly approved by Infineon
Technologies in a written document signed by
In addition, any information given in this document
is subject to customer’s compliance with its
obligations stated in this document and any
applicable legal requirements, norms and standards
concerning customer’s products and any use of the
product of Infineon Technologies in customer’s
applications.
Do you have a question about this
document?
Go to www.infineon.com/support
authorized
representatives
of
Infineon
Technologies, Infineon Technologies’ products may
not be used in any applications where a failure of the
product or any consequences of the use thereof can
reasonably be expected to result in personal injury.
Document reference
002-16951 Rev. *H
The data contained in this document is exclusively
intended for technically trained staff. It is the
responsibility of customer’s technical departments
to evaluate the suitability of the product for the
intended application and the completeness of the
product information given in this document with
respect to such application.
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