CYPD3173-24LQXQ [INFINEON]
EZ-PD™ CCG3PA-NFET USB-C PD Controller;型号: | CYPD3173-24LQXQ |
厂家: | Infineon |
描述: | EZ-PD™ CCG3PA-NFET USB-C PD Controller 光电二极管 |
文件: | 总25页 (文件大小:399K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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The fact that Infineon offers the following product as part of the Infineon product
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CCG3PA-NFET
USB Type-C Port Controller
CCG3PA-NFET, USB Type-C Port Controller
General Description
EZ-PD™ CCG3PA-NFET is Cypress’ highly integrated USB Type-C port controller with NFET-Gate driver that complies with the latest
USB Type-C and PD standards and is targeted for Power adapters. CCG3PA-NFET provides additional functionalities and BOM
integration advantages. CCG3PA-NFET uses Cypress’ proprietary M0S8 technology with a complete Type-C USB-PD transceiver, all
termination resistors required for a Type-C port, VBUS NFET gate driver and an integrated feedback control circuitry for voltage
(VBUS) regulation. It is available in 24-pin QFN package.
■ Integrates all termination on DP/DM lines, low-side current
sense amplifier (LSCSA), 2 x VBUS discharge FETs, and a
NFET gate driver to drive the load switch
Applications
■ USB PD 3.0 PPS Power Adapter[1]
■ Analog regulation of secondary side feedback node (direct
feedback or opto coupler)
■ Quick Charge 4.0 Power Adapter
■ Power adapters supporting both USB PD and legacy charging
■ Supports independent constant current (CC) and constant
voltage (CV) modes of operation
Features
■ Protects against accidental VBUS to CC short
■ 6 GPIOs for independent functionality
■ Supports one USB Type-C port
■ Supports USB PD2.0, PD3.0 with PPS, QC4+, QC4.0, QC3.0,
QC2.0, Samsung AFC, Apple charging and BC v1.2 charging
protocols
■ 24-QFN package with –40 °C to +105 °C extended industrial
temperature range
■ Configurable overvoltage protection (OVP), undervoltage
protection (UVP), overcurrent protection (OCP), short circuit
protection (SCP), and over-temperature protection (OTP)
Functional Block Diagram
VDDD VCCD
VBUS_C
VBUS_IN
VBUS_CTRL
OV, UV
OV, UV
Slew Rate
Controlled NFET
Gate Driver
VBUS_IN
Discharge
VBUS_C
Discharge
LDO
MCU Subsystem
HV
Regulator
Advanced High- Performance Bus
(AHB)
Flash
(64KB)
SRAM
(4KB)
Cortex-M0
CC1
CC2
BMC
PHY
Protocol Engine
ADC
DP_GPIO5
DM_GPIO4
CC
Reference
Charger
Detect
VBUS_IN
CV
Reference
Error
Amplifier
(CV)
Error
Amplifier
(CC)
LSCSA
SCP
FB
POR/
RESET
XRES
GPIOs
IDACs
EA_OUT
CC_COMP_GPIO2
VSS
Type-C
GPIO3
CSN
CSP
GPIO0
GPIO1
Connector
Ground
Rs
Note
1. PPS supported for Opto-based feedback architecture.
Cypress Semiconductor Corporation
Document Number: 002-30172 Rev. *A
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised October 16, 2020
CCG3PA-NFET
Contents
Pinout ................................................................................3
Pin Description ............................................................5
Application Diagram .........................................................6
Functional Description .....................................................8
MCU Subsystem .........................................................8
Fault Protection ...........................................................8
Power Modes ..............................................................8
CCG3PA-NFET Programming and Bootloading ............9
Programming the Device Flash over SWD Interface
(Programmable Version) ..............................................9
Application Firmware Update over CC Interface
(Programmable Version) ............................................10
Electrical Specifications ................................................11
Absolute Maximum Ratings .......................................11
Device-Level Specifications ......................................11
Functional Block Specifications .................................12
I/O Specifications ......................................................15
System Resources Specifications .............................16
Ordering Information ......................................................18
Ordering Code Definitions .........................................18
Packaging ........................................................................19
Acronyms ........................................................................21
Document Conventions .................................................22
Units of Measure .............................................................22
Document History Page .................................................23
Sales, Solutions, and Legal Information ......................24
Worldwide Sales and Design Support .......................24
Products ....................................................................24
PSoC® Solutions .......................................................24
Cypress Developer Community .................................24
Technical Support .....................................................24
Document Number: 002-30172 Rev. *A
Page 2 of 24
CCG3PA-NFET
Pinout
Figure 1. 24-Pin QFN Pin Map
1
2
18
17
16
15
14
13
NC
VSS
VBUS_C
DP_GPIO5
DM_GPIO4
VSS
3
NC
EPAD
4
5
6
XRES
GPIO0
GPIO1
CC1
CC2
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CCG3PA-NFET
Table 1. CCG3PA-NFET Pin Description
Pin Number
Pin Name
NC
Description
1
No Connect
Ground
2
VSS
3
NC
No Connect
External reset input
GPIO P0.0
4
XRES
5
GPIO0
GPIO1
CC_COMP_GPIO2
EA_OUT
FB
6
GPIO P0.1
7
Pin for constant current mode compensation capacitor/GPIO P0.2
Error amplifier output
8
9
Error amplifier feedback
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
CSN
Low-side current sense amplifier negative input
Low-side current sense amplifier positive input
GPIO P0.3
CSP
GPIO3
CC2
Power delivery Communication Channel 2
Power delivery Communication Channel 1
Ground
CC1
VSS
DM_GPIO4
DP_GPIO5
VBUS_C
VBUS_CTRL
VBUS_IN
VCCD
USB D-/SWD_DATA/GPIO P0.4
USB D+/SWD_CLK/GPIO P0.5
USB Type-C VBUS monitor input
Load switch NFET gate control
Power source input
1.8-V core voltage LDO output
3.0 V–5.5 V internal LDO Output
No Connect
VDDD
NC
NC
No Connect
EPAD
EPAD for ground
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CCG3PA-NFET
Pin Description
FB, EA_OUT, CC_COMP_GPIO2
CCG3PA-NFET integrates two error amplifier blocks which handles secondary output sensing and regulation for CV and CC modes.
This block is responsible for both constant voltage and constant current operations. The output of the error amplifier is routed to the
EA_OUT pin. EA_OUT can further drive an opto-isolator to provide feedback to the primary controller. The negative input of the error
amplifier is the feedback (FB) pin and the positive input is internal reference of 0.744 V. The FB pin has internal resistor divider of
200 kΩ and 35 kΩ, this divider sets a default voltage of 0.744 V at FB pin when VBUS_IN is at 5 V. Based on the desired VBUS_C
output, the voltage at the FB pin will be varied using internal current source/sink IDACs. An external compensation network is required
between FB pin and EA_OUT pin, as shown in Figure 2.
Constant current operation makes use of an internal LSCSA, the output of which feeds into an independent error amplifier as shown
in Figure 2. CCG3PA-NFET error amplifier can ensure constant voltage regulation over 3.3 V to 21 V range and constant current
regulation over 1 A to 3 A as required by the USB-PD PPS specification.
CC1, CC2
CC1 and CC2 are the communication channels for USB PD protocol. CCG3PA-NFET integrates a USB PD transceiver consisting of
a transmitter and receiver that communicate Biphase Mark Code (BMC) encoded data over the Configuration Channel (CC) channels
as per the USB-PD standard. All communication is half-duplex. The physical layer implements collision avoidance to minimize commu-
nication errors on the channel. This block includes all termination resistors (Rp) and their switches as required by the USB-PD
specification. An external 390-pF capacitor is required on both the CC1 and CC2 pins.
DP_GPIO4, DM_GPIO5
The DP and DM lines are the standard USB D+ and D- lines. CCG3PA-NFET integrates a charge detect block, which handles legacy
charging protocols such as BC 1.2, Quick Charge, Apple charging, and Samsung AFC. This block integrates all the terminations
required for these charging protocols and no external components are required. When legacy charging is not required in the system,
the same DP and DM lines can be reused as standard GPIOs.
VBUS_IN, VDDD, VCCD
CCG3PA-NFET integrates a high-voltage regulator, which is powered from the VBUS_IN rail, the output of the regulator powers the
VDDD rail. The input to the regulator can range from 3.3 V minimum to 21.5 V maximum. When the input is between 5.5 V to 21.5 V,
the typical output of the regulator is 5 V. For inputs from 3.3 V to 5.5 V, the regulator output is VBUS_IN – 300 mV.
The regulator can drive a maximum load current of 50 mA, which includes the chip current consumption. This regulator is not expected
to drive any external loads or ICs. CCG3PA-NFET also has an internal configurable discharge path for the VBUS_IN rail, which is
used to discharge the VBUS rail during negative voltage transitions.
The regulated supply VDDD, is either used to directly power some internal analog blocks or further regulated down to 1.8 V VCCD,
which powers majority of the core. VDDD and VCCD is brought out on to pins to connect external capacitors for regulator stability,
these are not meant to be used as power supplies.
VBUS_C, VBUS_CTRL
VBUS_C is used to monitor the voltage at the Type-C connector. VBUS_C has an internal configurable discharge path, which is used
to discharge the VBUS_C rail during negative voltage transitions.
The load switch is between VBUS_IN and VBUS_C. CCG3PA-NFET integrates a NFET gate driver to control this load switch.
VBUS_CTRL is the output of this gate driver. To turn off the external NFET, the gate driver drives low. To turn on the external NFET,
it drives the gate to VBUS_IN + 8 V. In addition, there is a clamp circuit to limit the gate to VBUS_IN + 8 V.
CSP, CSN
CCG3PA-NFET integrates a LSCSA to monitor the load current. CSP is the positive input pin for the LSCSA and CSN is the negative
input. LSCSA offers wide gain options ranging from 5 to 150. Suggested Rsense for LSCSA is 5 mΩ. LSCSA has an active offset
cancellation mechanism to improve accuracy.
GPIO0, GPIO1, and GPIO3
CCG3PA-NFET has six GPIOs, out of which three are dedicated GPIOs and the rest are multiplexed with other functionalities. During
power-on and reset, the I/O pins (except GPIO1) are forced to the tristate so as not to crowbar any inputs and/or cause excess turn-on
current. GPIO1 is driven to zero at power-up.
XRES
The XRES pin can be used to initiate a reset, this pin is internally pulled high and needs to be pulled low externally to trigger reset.
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CCG3PA-NFET
Application Diagram
Figure 2 shows the application diagram of CCG3PA-NFET-based Power Adapter with Opto-Coupler Feedback control using 24-pin
QFN device. In an opto-feedback power adapter, CCG3PA-NFET implements an independent error amplifier for constant voltage (CV)
mode and an independent error amplifier for constant current (CC) mode. The feedback to the primary controller is through an
opto-coupler. The current drawn through the EA_OUT pin is proportional to the potential difference between FB pin and the internal
CV reference voltage for CV mode and between CC_COMP pin and the internal CC reference voltage for CC mode.
For CV mode, if VBUS needs to be changed from default 5 V, using internal IDACs and an CV error amplifier, CCG3PA-NFET draws
a proportional current through the EA_OUT pin. This in turn gets coupled to the primary controller through the opto-coupler.
For CC mode, in order to keep current at the certain level, using internal IDACs and an CC error amplifier, CCG3PA-NFET draws a
proportional current through the EA_OUT pin to change the voltage output. This in turn gets coupled to the primary controller through
the opto-coupler.
Figure 2. CCG3PA-NFET Based PowerAdapterApplication Diagramwith Opto Coupler Feedback Control (24-pin QFN Device)
Full-bridge
Snubber
VBUS_TypeC
VBUS_IN
Rectifier
EMI
Filter
SR Controller
CC_COMP_GPIO2
GD
CS
CC1
CC2
VDD700
EA_OUT
Primary Flyback
Controller
DP_GPIO5
DM_GPIO4
CCG3PA-NFET
FB
FB
GPIO1
GPIO3
GND
Temperature
Sensor
Primary Side
Secondary Side
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CCG3PA-NFET
Figure 3 shows the application diagram of CCG3PA-NFET based power adapter with Direct Feedback control. In this application,
VBUS is maintained at a constant voltage. The default value of VBUS upon power up (which is usually at 5 V) is set up by choosing
the appropriate resistor divider that will set the FB node at a voltage expected by the secondary controller.
Feedback node is regulated using internal IDACs. Whenever a change in VBUS voltage is needed, CCG3PA-NFET will either source
or sink a proportional current at feedback node, based on the amount of voltage change needed.
Figure 3. CCG3PA-NFET Based Power Adapter Application Diagram with Direct Feedback Control
VBUS_TypeC
VBUS_IN
CC_COMP_GPIO2
EA_OUT
CC1
CC2
R1
Secondary
or
Integrated
Controller
CCG3PA-NFET
DP_GPIO5
DM_GPIO4
FB
R2
GPIO1
GPIO3
Temperature
Sensor
Secondary Side
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CCG3PA-NFET
Functional Description
MCU Subsystem
CPU
The Cortex-M0 CPU in EZ-PD CCG3PA-NFET is part of the 32-bit MCU subsystem, which is optimized for low-power operation with
extensive clock gating. The CPU also includes a serial wire debug (SWD) interface, which is a 2-wire form of JTAG. The debug
configuration used for EZ-PD CCG3PA-NFET has four break-point (address) comparators and two watchpoint (data) comparators.
Flash
The EZ-PD CCG3PA-NFET device has a flash module with one bank of 64 KB flash, a flash accelerator, tightly coupled to the CPU
to improve average access times from the flash block.
SROM
A supervisory ROM that contains boot and configuration routines
Fault Protection
VBUS UVP and OVP
VBUS undervoltage and overvoltage faults are monitored using internal VBUS_IN/VBUS_C resistor dividers. The fault thresholds and
response times are configurable in CCG3PA-NFET. Configurability includes choosing between auto-restart or latch-off options for
each fault.
VBUS OCP and SCP
VBUS overcurrent and short-circuit faults are monitored using internal current sense amplifiers. Same as OVP and UVP, the OCP and
SCP fault thresholds and response times are configurable as well. Configurability includes choosing between auto-restart or latch-off
options for each fault.
OTP
Over temperature monitoring is done using an external thermistor and internal ADC. The thermistor can be connected to GPIO3. Once
the temperature exceeds the configured Over temperature limit, the USB-C port is disabled and the device waits for the temperature
to drop below the set limit to re-enable the port. The corresponding temperature limits to report the error as well as recover from the
error are user configurable. The user also has an option to enable or disable the Over temperature protection functionality.
ESD Protection
CCG3PA-NFET offers ESD protection on all the pins. The ESD protection level is 2.2 kV HBM and 500 V CDM.
VBUS to CC Short Protection
CCG3PA-NFET offers protection against accidental short from VBUS_C pin short to CC.
Power Modes
CCG3PA-NFET supports three power modes - Active, Sleep, and Deep Sleep. Transitions between these modes is handled by the
device depending on the operating conditions.
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CCG3PA-NFET
CCG3PA-NFET Programming and Bootloading
CCG3PA-NFET is offered in two combinations:
1. A programmable version where the base Firmware for the device is available in EZ-PD CCGx Power Software Development
2. A preprogrammed version where the device is already programmed with a base Firmware. The customer however can configure
selected parameters using EZ-PD™ Configuration Utility
There are two ways to program application firmware into a CCG3PA-NFET device:
1. Programming the Device Flash over SWD Interface (Programmable Version)
2. Application Firmware Update over CC Interface (Programmable Version)
The CCG3PA-NFET programmable devices are programmed over SWD interface during development or during the manufacturing
process of the end product. Once the end product is manufactured, the application firmware can be updated via the CC bootloader
interface.
Programming the Device Flash over SWD Interface (Programmable Version)
CCG3PA-NFET family of devices can be programmed using the SWD interface. Cypress provides a programming kit (CY8CKIT-002
MiniProg3 Kit) called MiniProg3 and PSoC Programmer Software which can be used to program the flash as well as debug firmware.
The flash is programmed by downloading the information from a hex file. This hex file is a binary file generated as an output of building
the firmware project in PSoC Creator Software. Click here for more information on how to use the MiniProg3 programmer. There are
many third party programmers that support mass programming in a manufacturing environment.
As shown in the block diagram in Figure 4, the SWD_0_DAT and SWD_0_CLK pins are connected to the host programmer’s SWDIO
(data) and SWDCLK (clock) pins respectively. During SWD programming, the CCG3PA-NFET device has to be powered by the host
programmer by connecting its VTARG (power supply to the target device) to VDDD pin of CCG3PA-NFET device.
The CCG3PA-NFET device family has the XRES pin. it can programmed using Reset Mode if XRES is used. It can be programmed
using Power Cycle mode if XRES is not used. Contact Cypress for further details on CYPD3XXX Programming Specifications.
Figure 4. Connecting the Programmer to CYPD317X CCG3PA-NFET Device
CCG3PA-NFET
Programming Hardware
VTARG
SWDCLK
SWDIO
XRES
VDDD
VCCD
SWD_0_CLK
SWD_0_DAT
XRES
C2
C1
GND
VGND
GND
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CCG3PA-NFET
Application Firmware Update over CC Interface (Programmable Version)
For bootloading CCG3PA-NFET applications, the CY4532 CCG3PA EVK can be used to send programming and configuration data
as Cypress specific Vendor Defined Messages (VDMs) over the CC line. The CY4532 CCG3PA EVK’s Power Board is connected to
the system containing CCG3PA-NFET device on one end and a Windows PC running the EZ-PD Configuration Utility as shown in
Figure 5 on the other end to bootload the CCG3PA-NFET device.
Figure 5. Application Firmware Update over CC Interface
USB-Serial interface
USB Mini-B
I2C
PC running
EZ-PD
configuration utility
CYPD317x
device to be
bootloaded
CC line
cable
CC interface
Type-C
receptacle
Cypress CY4532 kit power board
Mini-B
receptacle
Application Firmware (FW) update feature over CC interface is intended for use during development and manufacturing. Cypress
strongly recommends customers to use the EZ-PD Configuration Utility to turn off the Application FW Update over CC interface in the
firmware that is updated into CCG3PA-NFET’s flash before mass production. This prevents unauthorized firmware from being updated
over CC-interface in the field. Refer to the knowledge base article KBA230192 on how to configure this in EZ-PD Configuration Utility.
If you desire to retain the Application Firmware update over CC interface feature post-production for on-field firmware updates, contact
Cypress Sales for further guidelines.
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CCG3PA-NFET
Electrical Specifications
Absolute Maximum Ratings
Table 2. Absolute Maximum Ratings[2]
Parameter
VBUS_IN_MAX
Description
Min
–
Typ
–
Max
Unit
Details/Conditions
Maximum input supply voltage
Maximum supply voltage
24
–
VDDD_MAX
VGPIO_ABS
VCC_PIN_ABS
IGPIO_ABS
ESD_HBM
ESD_CDM
I_LU
–
–
6
–
–
–
–
–
–
–
V
GPIO voltage
–0.5
–
–
VDDD + 0.5
Maximum voltage on CC1, CC2 voltage
Current per GPIO
–
24
25
–
–
–
mA
V
Electrostatic discharge human body model
Electrostatic discharge charged device model
Pin current for latch-up
2200
500
–100
–
–
–
–
100
mA
Device-Level Specifications
Table 3. DC Specifications
Spec ID
Parameter
Description
Min
Typ Max Unit
Details/Conditions
VDDD output for 5.5 V ≤ VBUS_IN
≤ 21.5 V
SID.PWR.1
VDDD_REG
4.6
5.0 5.4
ILOAD = 0-50 mA
VDDD output for 3.3 V ≤ VBUS_IN VBUS_IN
≤ 5.5 V
SID.PWR.2
VDDD_MIN
–
–
V
- 0.3
3.3
–
SID.PWR.4
SID.PWR.6
SID.PWR.8
SID.PWR.9
VBUS_IN
VCCD
Cefc
Power supply input voltage
Output voltage for core logic
Bypass capacitor for VCCD
Decoupling capacitor for VDDD
–
1.8
1
21.5
–
–
–
0.8
1.8
1.2
4.7
X5R ceramic or better
Cexc
–
µF
Decoupling capacitor for
VBUS_IN
Decoupling capacitor required near
the IC pin.
SID.PWR.10
Cexv
–
1
–
VBUS_IN = 5 V, TA = 25 °C,
CC1/CC2 in TX or RX (USB-PD
communication is active)
Active current from VBUS_IN in
Type-C attached state
SID.PWR.15
IDD_A
–
6.5
–
VBUS_IN = 5 V, TA = 25 °C,
Type-C attached, CPU OFF,
PWM/EA/ADC/UVOVblocksON.CC,
Watchdog Timer (WDT) Wakeup ON
Sleep current from VBUS_IN in
Type-C attached state
SID.PWR.16
IDD_S_UA
–
–
2.5
–
–
mA
VBUS_IN = 5 V, TA = 25 °C,
Type-C unattached, CPU OFF, UVOV
block ON, WDT Wakeup ON
Deep Sleep current from
SID.PWR#16_A I_DS_UA
0.75
VBUS_IN (Type-C unattached)
Table 4. AC Specifications
Spec ID
SID.PWR.14
SID.PWR.14A
Parameter
Description
Min Typ Max Unit
Details/Conditions
Tsleep
Wakeup from Sleep mode
–
–
0
–
–
µs
µs
–
–
Tdeepsleep Wakeup from Deep Sleep mode
35
Note
2. Usage of the absolute maximum conditions listed in Table 2 may cause permanent damage to the device. Exposure to absolute maximum conditions for extended
periods of time may affect device reliability. The maximum storage temperature is 150 °C in compliance with JEDEC Standard JESD22-A103, High Temperature
Storage Life. When used below absolute maximum conditions but above normal operating conditions, the device may not operate to specification.
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CCG3PA-NFET
Functional Block Specifications
Table 5. ADC Specifications
Spec ID
DC Specifications
SID.ADC.1
Parameter
Description
Min
Typ
Max
Unit Details/Conditions
Resolution
ADC resolution
–
8
–
–
Bits
–
Reference voltage =
VREF_ADC1
SID.ADC.2
SYS.ADC.3
SYS.ADC.4
INL
INL
DNL
–2.5
2.5
Integral nonlinearity
Reference voltage =
VREF_ADC2
–1.5
–2.5
–
–
1.5
2.5
LSB Reference voltage =
VREF_ADC1
Differential nonlinearity
Gain error
Reference voltage =
VREF_ADC2
SYS.ADC.5
SYS.ADC.6
DNL
–1.5
–1.5
–
–
1.5
1.5
Gain Error
–
Reference voltage
generated from
VDDD
SYS.ADC.7
SYS.ADC.8
VREF_ADC1
VREF_ADC2
VDDDmin
–
VDDDmax
ADC reference voltage
V
Reference voltage
generate from
bandgap
1.96
2.0
2.04
AC Specifications
Rate of change of sampled voltage
signal
Guaranteed by
design
SID.ADC.9
Slew_Max
–
–
3
V/ms
Table 6. Error Amplifier
Spec ID
Parameter
Description
Min
Typ
Max
Unit Details/Conditions
DC Specifications
SID.DC.VR.1
VR
VBUS voltage regulation accuracy
Off-state EA_OUT current
–
–
± 3
2.2
± 5
10
%
–
–
SID.DC.VR.2
Ika_off
µA
Current through EA_OUT pin when
in Sink mode for optocoupler appli-
cation
SID.DC.VR.3
Ika_on
–
–
5
mA
–
Differential nonlinearity of NMOS
DAC
SID.DC.VR.4
DNL_ndac
INL_ndac
–1
–
1
–
LSB
%
SID.DC.VR.5
SID.DC.VR.6
Integral nonlinearity of NMOS DAC
–1.5
–8
–
–
1.5
8
–
–
Gain_error_ndac Gain error of NMOS DAC
Differential nonlinearity of PMOS
SID.DC.VR.7
DNL_pdac
DAC
–0.5
–
0.5
–
LSB
%
SID.DC.VR.8
SID.DC.VR.9
INL_pdac
Integral nonlinearity of PMOS DAC
–1
–8
–
–
1
8
–
–
Gain_error_pdac Gain error of PMOS DAC
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CCG3PA-NFET
Table 7. LSCSA, SCP
Spec ID
Parameter
Description
Min
Typ
Max
Unit
Details/Conditions
DC Specifications
SID.LSCSA.1
Cin_inp
CSP input capacitance
–
–
–
10
15
pF
–
–
CSA accuracy with
5 mV < Vsense < 10 mV
SID.LSCSA.2
SID.LSCSA.3
SID.LSCSA.4
SID.LSCSA.5
SID.LSCSA.6
Csa_Acc1
–15
CSA accuracy with
10 mV < Vsense < 15 mV
Csa_Acc2
Csa_Acc3
SCP_6A
SCP_10A
Av
–10
–5
5.4
9
–
–
10
5
%
A
–
–
CSA accuracy with
15 mV < Vsense
Short circuit trip point with
threshold set to 6A
6
6.6
11
Rsense = 5 mΩ
Short circuit trip point with
threshold set to 10A
10
–
CSA gain values supported:
5,10, 20, 35, 50, 75, 125, 150
SID.LSCSA.8
5
150
–
AC Specifications
DelayfromOCPthresholdtripto
external NFET gate turn off
SID.LSCSA.AC.1 Tocp_gate
SID.LSCSA.AC.2 Tscp_gate
–
–
4
20
–
–
Delay from SCPthreshold trip to
external NFET gate turn off
1 nF NFET gate
capacitance
3.1
µs
Delay from SCPthreshold trip to
SID.LSCSA.AC.3 Tscp_gate_1 external NFET power gate turn
3 nF NFET gate
capacitance
–
7.5
–
off
Table 8. VBUS UV, OV
Spec ID
Parameter
Description
Min
Typ
Max
Unit
Details/Conditions
DC Specifications
Over-Voltage threshold
Accuracy, 4 V to 11 V
SID.UVOV.1
SID.UVOV.2
SID.UVOV.3
SID.UVOV.4
SID.UVOV.5
VTHOV1
VTHOV2
VTHUV1
VTHUV2
VTHUV3
VTHUV4
–3
–3.2
–4
–
–
–
–
–
–
3
3.2
4
–
–
–
–
–
–
Over-Voltage threshold
Accuracy, 11 V to 21.5 V
Under-Voltage threshold
Accuracy, 3 V to 3.3 V
%
Under-Voltage threshold
Accuracy, 3.3 V to 4.0 V
–3.5
–3
3.5
3
Under-Voltage threshold
Accuracy, 4.0 V to 11 V
Under-Voltage threshold
Accuracy, 11 V to 21.5 V
SID.UVOV.6
–2.9
2.9
AC Specifications
Delay from OV threshold trip to
external NFET Power Gate Turn
off
SID.UVOV.AC.1 Tov_gate
–
–
50
µs
–
Document Number: 002-30172 Rev. *A
Page 13 of 24
CCG3PA-NFET
Table 9. PD Transceiver
Spec ID
Parameter
Description
Min
Typ
Max
Unit
Details/Conditions
DC Specifications
Downstream facing port (DFP)
CC termination for default USB
power
SID.PD.1
Rp_std
64
80
96
–
DFP CC termination for 1.5 A
USB power
µA
SID.PD.2
SID.PD.3
SID.PD.4
Rp_1.5A
Rp_3.0A
Vgndoffset
166
304
180
330
–
194
356
500
–
–
DFP CC termination for 3.0 A
USB power
Ground offset tolerated by
BMC receiver
Relative to remote BMC
transmitter
–500
mV
Table 10. VBUS Discharge
Spec ID
Parameter
Description
Min
Typ
Max
Unit
Details/Conditions
DC Specifications
20 V NMOS ON resistance
for discharge strength = 1
SID.VBUS.DISC.1 R1
SID.VBUS.DISC.2 R2
SID.VBUS.DISC.3 R4
SID.VBUS.DISC.4 R8
SID.VBUS.DISC.5 R16
500
250
125
62.5
31.25
–
–
–
–
–
–
–
2000
1000
500
250
125
10
20 V NMOS ON resistance
for discharge strength = 2
20 V NMOS ON resistance
for discharge strength = 4
Ω
Measured at 0.5 V
20 V NMOS ON resistance
for discharge strength = 8
20 V NMOS ON resistance
for discharge strength = 16
Error percentage of final
VBUS value
When VBUS is discharged to
5 V
SID.VBUS.DISC.6 Vbus_stop_error
%
Table 11. VBUS NFET Gate Driver
Spec ID
Parameter
Description
Min
Typ
Max
Unit
Details/Conditions
DC Specifications
Gate to Source overdrive
during NFET ON condition
SID.GD.1
GD_VGS
4.5
–
5.75
0.57
10
2
V
Vbus_in = 21.5 V
–
Resistance when pull-down
is enabled to turn off
external NFET
SID.GD.2
GD_Rpd
kΩ
AC Specifications
AC.GD.1
V
BUS_ctrl Low to High (1 V to
Ton
Toff
VBUS + 1 V) with 3nF
external capacitance
2
–
5
7
10
–
ms VBUS_IN = 5 V
VBUS_ctrl High to Low (90%
to 10%) with 3nF external
capacitance
AC.GD.2
µs
VBUS_IN = 21.5 V
Document Number: 002-30172 Rev. *A
Page 14 of 24
CCG3PA-NFET
Table 12. High-Voltage Regulator
Spec ID
Parameter
Description
Min
Typ
Max
Unit
Details/Conditions
DC Specifications
VBUS_INvoltagedetect
threshold
SID.VREG.1
SID.VREG.2
VOLTAGE_DETECT
Tstart
1.7
–
2.1
50
2.4
V
–
Total start-up time for
the regulator supply
outputs
From VBUS reaching
Voltage_detect level to 95%
of final value
200
µs
I/O Specifications
Table 13. I/O Specifications
Spec ID
Parameter
Description
Min
Typ
Max
Unit
Details/Conditions
DC Specifications
SID.GIO.1
SID.GIO.2
SID.GIO.3
SID.GIO.4
SID.GIO.5
I_LU
Latch-up current limits
Pull-up resistor value
Pull-down resistor value
Input leakage current
–140
3.5
3.5
–
–
140
8.5
8.5
2
mA
kΩ
nA
–
RPU
RPD
IIL
5.6
5.6
–
–
–
CPIN_A
–
7.8
3
22
Capacitance on DP/DM lines
Max pin capacitance
pF
Capacitance on all GPIOs,
except DP/DM lines
SID.GIO.6
CPIN
–
7
VDDD
0.6
–
SID.GIO.7
SID.GIO.8
SID.GIO.9
Voh_3V
Output voltage high level
Output voltage low level
Input voltage high threshold
–
–
–
–
0.6
–
Ioh = –4 mA
Iol = 10 mA
–
Vol_3V
–
0.7 *
VDDD
Vih_CMOS
V
0.3 *
VDDD
SID.GIO.10 Vil_CMOS
SID.GIO.11 Vih_TTL
Input voltage low threshold
LVTTL input
–
–
–
2
–
–
–
–
–
–
–
SID.GIO.12 Vil_TTL
SID.GIO.13 Vhysttl
0.8
–
Input hysteresis LVTTL
Input hysteresis CMOS
100
mV
µA
0.05 *
VDDD
SID.GIO.14 Vhyscmos
SID.GIO.15 IDIODE
–
–
–
–
–
Current through protection
diode to VDDD/VSS
–
100
Document Number: 002-30172 Rev. *A
Page 15 of 24
CCG3PA-NFET
Table 13. I/O Specifications (continued)
Spec ID Parameter
Description
Min
2
Typ
–
Max
12
Unit
Details/Conditions
SID.GIO.16 TriseF
SID.GIO.17 TfallF
SID.GIO.18 TriseS
SID.GIO.19 TfallS
Rise time in fast strong mode
Fall time in fast strong mode
Risetimeinslowstrongmode
Fall time in slow strong mode
2
–
12
ns
10
10
–
60
–
60
Cload = 25 pF
GPIO Fout;
SID.GIO.20 FGPIO_OUT1
SID.GIO.21 FGPIO_OUT2
SID.GIO.22 FGPIO_IN
3 V ≤ VDDD ≤ 5.5 V;
–
7
–
–
–
16
–
Fast strong mode.
GPIO Fout;
3V ≤ VDDD ≤ 5.5 V;
Slow strong mode.
MHz
GPIO input operating
frequency;
3 V ≤ VDDD ≤ 5.5 V
16
–
–
System Resources Specifications
Table 14. Power-On Reset (POR) Specifications
Spec ID
SID.POR.1
SID.POR.2
Parameter
VRISEIPOR
VFALLIPOR
Description
POR rising trip voltage
POR falling trip voltage
Min
Typ
Max
Unit
Details/Conditions
0.8
0.7
–
–
1.5
1.4
–
–
V
Brown-out-detect (BOD) trip
voltage active/ sleep modes
SID.POR.3
VFALLPPOR
1.48
–
1.62
–
Table 15. Flash Macro Specifications
Spec ID
Parameter
Description
Min
Typ
Max
Unit
Details/Conditions
SID.MEM#1
FLASH_ERASE Row erase time
15.5
-40 °C to +85 °C TA,
ALL VDDD
–
–
SID.MEM#2
SID.MEM#5
FLASH_WRITE Row (Block) write time
(erase & program)
20
7
-40 °C to +85 °C TA,
ALL VDDD
–
–
ms
FLASH_ROW_ Row program time after
25 °C to 55 °C,
ALL VDDD
–
–
–
–
–
–
PGM
erase
SID178
SID180
TBULKERASE Bulk erase time (32k Bytes)
35
–
–
–
TDEVPROG
FRET1
Total device program time
7.5
secs
–
SID182
Flash retention, TA ≤ 55 °C,
100 K P/E cycles
20
–
–
–
SID182A
SID182A
FRET2
Flash retention, TA ≤ 85 °C,
10 K P/E cycles
10
3
–
–
years
–
–
FRET3
Flash retention, TA ≤
105 °C, 10 K P/E cycles
Document Number: 002-30172 Rev. *A
Page 16 of 24
CCG3PA-NFET
Table 16. SWD Specifications
Spec ID
SID.SWD#1
SID.SWD#2
SID.SWD#3
SID.SWD#4
SID.SWD#5
Parameter
F_swdclk1
Description
3 V <= VDDD <= 5.5 V
T = 1/f SWDCLK
T = 1/f SWDCLK
T = 1/f SWDCLK
T = 1/f SWDCLK
Min
Typ
–
Max
Unit
Details/Conditions
–
0.25*T
0.25*T
–
14
MHz
–
T_swdi_setup
T_swdi_hold
T_swdo_valid
T_swdo_hold
–
–
–
–
–
–
–
–
0.50*T
–
ns
–
1
–
Document Number: 002-30172 Rev. *A
Page 17 of 24
CCG3PA-NFET
Ordering Information
Table 17. CCG3PA-NFET Ordering Information
MPN
Application
Package Type
Si ID
2B02
2B03
2B04
2B05
CYPD3172-24LQXQ
CYPD3172P-24LQXQ
CYPD3173-24LQXQ
CYPD3173P-24LQXQ
Power Adapter based on Opto Coupler Feedback (Pre programmed)
Power Adapter based on Opto Coupler Feedback (Programmable)
Power Adapter based on Direct Feedback (Pre programmed)
Power Adapter based on Direct Feedback (Programmable)
24-Pin QFN
Ordering Code Definitions
XX
X
CY PD
X
−
XX XX
X
X
XX
X
X
T = Tape and Reel
ES (Optional Field) = Pre-production Engineering samples only.
Non orderable.
Temperature Range: Q = Extended Industrial (-40 ºC to +105 ºC)
X = Pb-free
Package Type: LQ = QFN
Number of pins in the package
P = Programmable
Application and Feature Combination Designation
Number of Type-C Ports: 1 = 1 Port
Product Type: 3 = Third Generation
Marketing Code: PD = Power Delivery product family
Company ID: CY = Cypress
Document Number: 002-30172 Rev. *A
Page 18 of 24
CCG3PA-NFET
Packaging
Table 18. Package Characteristics
Parameter
TA
Description
Conditions
Min
–40
–40
–
Typ
25
25
–
Max
105
Unit
Operating ambient temperature
Operating junction temperature
Package θJA
Extended Industrial
°C
TJ
120
TJA
TJC
19.98
4.78
–
°C/W
Package θJC
–
–
Table 19. Solder Reflow Peak Temperature
Maximum Time within 5 °C
of Peak Temperature
Package
Maximum Peak Temperature
24-pin QFN
260 °C
30 seconds
Table 20. Package Moisture Sensitivity Level (MSL), IPC/JEDEC J-STD-2
Package
MSL
24-pin QFN
MSL 3
Document Number: 002-30172 Rev. *A
Page 19 of 24
CCG3PA-NFET
Figure 6. 24-pin QFN Package Outline
002-16934 *C
Document Number: 002-30172 Rev. *A
Page 20 of 24
CCG3PA-NFET
Table 21. Acronyms Used in this Document (continued)
Acronyms
Acronym
NMOS
NVIC
opamp
OCP
OVP
OTP
Description
N-type metal-oxide-semiconductor
nested vectored interrupt controller
operational amplifier
Table 21. Acronyms Used in this Document
Acronym
ADC
API
Description
analog-to-digital converter
application programming interface
advanced RISC machine, a CPU architecture
constant current
overcurrent protection
overvoltage protection
over-temperature protection
printed circuit board
Arm®
CC
CC
configuration channel
PCB
CV
constant voltage
PD
power delivery
BOD
BMC
CPU
Brown out Detect
PGA
PHY
programmable gain amplifier
physical layer
biphase mark code
central processing unit
PMOS
POR
PPS
P-type metal-oxide-semiconductor
power-on reset
cyclic redundancy check, an error-checking
protocol
CRC
CrCM
CS
critical conduction mode
current sense
programmable power supply
precise power-on reset
Programmable System-on-Chip™
pulse-width modulator
random-access memory
reduced-instruction-set computing
root-mean-square
PRES
PSoC®
PWM
RAM
RISC
RMS
RTC
DCM
DFP
discontinuous conduction mode
downstream facing port
digital input/output, GPIO with only digital
capabilities, no analog. See GPIO.
DIO
DRP
dual role port
electrically erasable programmable read-only
memory
EEPROM
real-time clock
RX
receive
a USB cable that includes an IC that reports cable
characteristics (e.g., current rating) to the Type-C
ports
EMCA
SAR
successive approximation register
I2C serial clock
SCL
EMI
ESD
FPB
FS
electromagnetic interference
electrostatic discharge
flash patch and breakpoint
full-speed
SCP
short circuit protection
I2C serial data
SDA
S/H
sample and hold
Serial Peripheral Interface, a communications
protocol
SPI
GPIO
IC
general-purpose input/output
integrated circuit
SR
synchronous rectifier
static random access memory
serial wire debug, a test protocol
transmit
IDE
integrated development environment
SRAM
SWD
TX
I2C, or IIC Inter-Integrated Circuit, a communications protocol
ILO
internal low-speed oscillator, see also IMO
internal main oscillator, see also ILO
input/output, see also GPIO
low-side current sense amplifier
low-voltage detect
IMO
I/O
a new standard with a slimmer USB connector and
a reversible cable, capable of sourcing up to 100 W
of power
Type-C
LSCSA
LVD
LVTTL
MCU
NC
Universal Asynchronous Transmitter Receiver, a
communications protocol
UART
USB
low-voltage transistor-transistor logic
microcontroller unit
Universal Serial Bus
USB input/output, CCG5 pins used to connect to a
USB port
USBIO
UVP
no connect
undervoltage protection
NMI
nonmaskable interrupt
Document Number: 002-30172 Rev. *A
Page 21 of 24
CCG3PA-NFET
Table 21. Acronyms Used in this Document (continued)
Document Conventions
Acronym
Description
Units of Measure
WDT
watchdog timer
Table 22. Units of Measure
USB input/output, CCG5 pins used to connect to a
USB port
USBIO
Symbol
°C
Unit of Measure
XRES
ZCD
external reset I/O pin
zero crossing detect
degrees Celsius
hertz
Hz
KB
kHz
kΩ
Mbps
MHz
MΩ
Msps
µA
1024 bytes
kilohertz
kilo ohm
megabits per second
megahertz
mega-ohm
megasamples per second
microampere
microfarad
microsecond
microvolt
µF
µs
µV
µW
mA
ms
mV
nA
microwatt
milliampere
millisecond
millivolt
nanoampere
nanosecond
ohm
ns
Ω
pF
picofarad
ppm
ps
parts per million
picosecond
second
s
sps
V
samples per second
volt
Document Number: 002-30172 Rev. *A
Page 22 of 24
CCG3PA-NFET
Document History Page
Document Title: CCG3PA-NFET, USB Type-C Port Controller
Document Number: 002-30172
Revision
ECN
Submission Date
Description of Change
**
6890477
06/01/2020
Initial release.
Updated datasheet status from Advance to Final.
Added Note [1] for USB PD 3.0 PPS Power Adapter in Applications.
Updated text in OTP.
Updated error amplifier constant voltage regulation from 21.5 V to 21 V in FB, EA_OUT,
CC_COMP_GPIO2.
*A
6960049
10/16/2020
Added text in Application Firmware Update over CC Interface (Programmable Version).
Updated text in CCG3PA-NFET Programming and Bootloading.
Updated Typ values and details/conditions for SID.PWR.15, SID.PWR.16, and
SID.PWR#16_A in Table 3.
Document Number: 002-30172 Rev. *A
Page 23 of 24
CCG3PA-NFET
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
®
Products
PSoC Solutions
Arm® Cortex® Microcontrollers
cypress.com/arm
cypress.com/automotive
cypress.com/clocks
cypress.com/interface
cypress.com/iot
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP | PSoC 6 MCU
Automotive
Cypress Developer Community
Clocks & Buffers
Interface
Community | Code Examples | Projects | Video | Blogs |
Training | Components
Internet of Things
Memory
Technical Support
cypress.com/memory
cypress.com/mcu
cypress.com/support
Microcontrollers
PSoC
cypress.com/psoc
cypress.com/pmic
cypress.com/touch
cypress.com/usb
Power Management ICs
Touch Sensing
USB Controllers
Wireless Connectivity
cypress.com/wireless
Notice regarding compliance with Universal Serial Bus specification. Cypress offers firmware and hardware solutions that are certified to comply with the Universal Serial Bus specification, USB
Type-C™ Cable and Connector Specification, and other specifications of USB Implementers Forum, Inc (USB-IF). You may use Cypress or third party software tools, including sample code, to modify
the firmware for Cypress USB products. Modification of such firmware could cause the firmware/hardware combination to no longer comply with the relevant USB-IF specification. You are solely
responsible ensuring the compliance of any modifications you make, and you must follow the compliance requirements of USB-IF before using any USB-IF trademarks or logos in connection with any
modifications you make. In addition, if Cypress modifies firmware based on your specifications, then you are responsible for ensuring compliance with any desired standard or specifications as if you
had made the modification. CYPRESS IS NOT RESPONSIBLE IN THE EVENT THAT YOU MODIFY OR HAVE MODIFIED A CERTIFIED CYPRESS PRODUCT AND SUCH MODIFIED PRODUCT
NO LONGER COMPLIES WITH THE RELEVANT USB-IF SPECIFICATIONS.
© Cypress Semiconductor Corporation, 2020. This document is the property of Cypress Semiconductor Corporation and its subsidiaries (“Cypress”). This document, including any software or firmware
included or referenced in this document (“Software”), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries worldwide. Cypress reserves all
rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other intellectual property rights. If the
Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress hereby grants you a personal,
non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to modify and reproduce the Software
solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users (either directly or indirectly through
resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as provided by Cypress, unmodified)
to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation of the Software is prohibited.
TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. No computing
device can be absolutely secure. Therefore, despite security measures implemented in Cypress hardware or software products, Cypress shall have no liability arising out of any security breach, such
as unauthorized access to or use of a Cypress product. CYPRESS DOES NOT REPRESENT, WARRANT, OR GUARANTEE THAT CYPRESS PRODUCTS, OR SYSTEMS CREATED USING
CYPRESS PRODUCTS, WILL BE FREE FROM CORRUPTION, ATTACK, VIRUSES, INTERFERENCE, HACKING, DATA LOSS OR THEFT, OR OTHER SECURITY INTRUSION (collectively,
“Security Breach”). Cypress disclaims any liability relating to any Security Breach, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from any Security
Breach. In addition, the products described in these materials may contain design defects or errors known as errata which may cause the product to deviate from published specifications. To the
extent permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of
any product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes.
It is the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. “High-Risk
Device” means any device or system whose failure could cause personal injury, death, or property damage. Examples of High-Risk Devices are weapons, nuclear installations, surgical implants, and
other medical devices. “Critical Component” means any component of a High-Risk Device whose failure to perform can be reasonably expected to cause, directly or indirectly, the failure of the High-Risk
Device, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from any use of
a Cypress product as a Critical Component in a High-Risk Device. You shall indemnify and hold Cypress, its directors, officers, employees, agents, affiliates, distributors, and assigns harmless from
and against all claims, costs, damages, and expenses, arising out of any claim, including claims for product liability, personal injury or death, or property damage arising from any use of a Cypress
product as a Critical Component in a High-Risk Device. Cypress products are not intended or authorized for use as a Critical Component in any High-Risk Device except to the limited extent that (i)
Cypress's published data sheet for the product explicitly states Cypress has qualified the product for use in a specific High-Risk Device, or (ii) Cypress has given you advance written authorization to
use the product as a Critical Component in the specific High-Risk Device and you have signed a separate indemnification agreement.
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in
the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Document Number: 002-30172 Rev. *A
Revised October 16, 2020
Page 24 of 24
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500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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