CYPM1115-48LQXIT_技术文档

CYPM1115, CYPM1116

EZ-PD™ PMG1-B1 USB Type-C Buck-boost

controller

Single-port

General description

EZ-PD™ PMG1-B1 is a highly integrated single-port USB Type-C Power Delivery (PD) solution with integrated

buck-boost controllers. It complies to the latest USB Type-C and PD specifications. EZ-PD™ PMG1-B1 has

integrated gate drivers for VBUS NFET on the consumer path for sink application. It also includes

hardware-controlled protection features on the VBUS. EZ-PD™ PMG1-B1 supports a wide input voltage range

(4 to 24 V with 40 V tolerance) and programmable switching frequency (150 to 600 kHz) in an integrated PD

solution.

EZ-PD™ PMG1-B1 is the most programmable USB-PD solution with on-chip 32-bit Arm® Cortex®-M0 processor,

128-KB flash, 16-KB RAM and 32-KB ROM that leaves most flash available for user application use. It also includes

various analog and digital peripherals such as ADC, PWMs and timers.

Applications

• Cordless power tool charger

• Wireless speakers

• Portable electronics

Features

USB-PD

• Supports one USB-PD port

• Supports latest USB-PD 3.1

• Extended data messaging

Type-C

• Configurable resistors R_Pand R_D

• VBUS NFET gate driver

• Integrated 100-mW VCONN power supply and control

1x buck-boost controller

• 150 kHz to 600 kHz switching frequency

• 5.5 to 24 V input, 40 V tolerant

• 3.3 to 21.5 V output

• Supports selectable pulse skipping mode (PSM) and forced continuous conduction mode (FCCM)

• Supports soft start

• Programmable spread spectrum frequency modulation for low EMI

• Supports current sensing for constant current control

1x legacy/proprietary charging block

• Supports Apple charging 2.4A and USB BC 1.2

Datasheet

www.infineon.com

Please read the Important Notice and Warnings at the end of this document

page 1

002-35400 Rev. *D

2022-12-19

EZ-PD™ PMG1-B1 USB Type-C Buck-boost controller

Single-port

Features

System-level fault protection

• VBUS overvoltage protection (OVP), and undervoltage protection (UVP)

• VBUS to CC short protection

• VOUT UVP, OVP, and OCP

• Supports over-temperature protection through integrated ADC circuit and internal temperature sensor

• Supports connector and board temperature measurement using external thermistors

32-bit MCU subsystem

• 48-MHz Arm® Cortex®-M0 CPU

• 128-KB Flash

• 16-KB SRAM

• 32-KB ROM

Peripherals and GPIOs

• Up to 21 GPIOs including two over-voltage GPIOs

• 2x 8-bit ADC

• 8x 16-bit Timer/Counter/PWMs (TCPWM)

• 1x 12-bit ADC

Communication interfaces

• 3x SCBs (I²C/SPI/UART/LIN)

Clocks and oscillators

• Integrated oscillator eliminating the need for an external clock

Power supply

• 4 to 24 V input (40 V tolerant)

• 3.3 to 21.5 V output

• Integrated LDO capable of 5 V, 75 mA

• Standby regulator of 3 V, 10 mA

Packages

• 48-pin QFN

• Supports ambient temperature range (–40°C to +105°C) with 125°C operating junction temperature

Datasheet

2

002-35400 Rev. *D

2022-12-19

EZ-PD™ PMG1-B1 USB Type-C Buck-boost controller

Single-port

Functional block diagram

VBUS_C

Current Sense

Amplifier (CSA),

Slope

Slew Rate Control

NGATE Driver

Error

Amplifier

(CV)

Error

Amplifier

(CC)

GDRV (Buck)

High-Side

Low-Side

GDRV (Boost)

High-Side CSA

High-Side

Low-Side

Voltage/Current

Monitoring

VBUS_IN VBUS_C

Discharge Discharge

Driver (HSDR) Driver (LSDR)

Driver (HSDR)

Driver (LSDR)

Compensation

OCP, SCP, OVP,

UVP

Zero Crossing

Detect (ZCD)

Charge

Control

Zero Crossing

Detect (ZCD)

Charge

Control

CC

Reference

HV

Regulator

(4-24V)

Reference

and IDAC

VIN

VDDD

VCCD

I/O Matrix

GPIO11

Pulse-Width

Modulator

(PWM)

12-bit SAR

ADC

MCU Subsystem

GPIO12

Cortex^®-M0

LV

Regulator

(1.8-5V)

GPIO13

GPIO14

GPIO15

GPIO7

Flash

(128KB)

SROM

(32KB)

SRAM

(16KB)

8-bit ADC

GPIO

Analog

Regulator

VDDD

GPIO8

TCPWM

Timer/Pulse

Width Modulator

GPIO10

GPIO6

GPIO20

GPIO19

GPIO2

GPIO3

GPIO18

GPIO9

GPIO5

GPIO16

GPIO17

CC1

CC2

EZ-PD™ PMG1-B1

I2C/SPI/

UART/LIN

(Master or

Slave)

BMC

PHY

VCONN

Charger

Detect

GPIO0

GPIO1

POR/

RESET

XRES

GND

Datasheet

3

002-35400 Rev. *D

2022-12-19

EZ-PD™ PMG1-B1 USB Type-C Buck-boost controller

Single-port

Block diagram

Color Key:Power Modes

Active/Sleep

EZ-PD™ PMG1-B1 MCU

CYPM1115/CYPM1116

Deep Sleep

System Resources

Power

Clocks

Sleep Control

ILO IMO

Clock Control

WDT

POR

PWRSYS

WIC

REF

Reset

Reset Control

XRES

Programmable Analog

1x 12-bits

SAR MUX

SAR ADC

CPU Subsystem

USB PD Subsystem

SWD/TC

Cortex®-M0+

48 MHz

FAST MUL

NVIC, IRQMUX

SPCIF

Flash

128 KB

Read Accelerator

SRAM

16 KB

SRAM Controller

ROM

32 KB

ROM Controller

Datasheet

4

002-35400 Rev. *D

2022-12-19

EZ-PD™ PMG1-B1 USB Type-C Buck-boost controller

Single-port

Table of contents

General description ...........................................................................................................................1

Applications......................................................................................................................................1

Features ...........................................................................................................................................1

Functional block diagram...................................................................................................................3

Block diagram...................................................................................................................................4

Table of contents...............................................................................................................................5

1 Functional overview .......................................................................................................................6

1.1 MCU subsystem.......................................................................................................................................................6

1.2 USBPD subsystem...................................................................................................................................................6

1.3 Buck-boost subsystem ...........................................................................................................................................8

1.4 Buck-boost controller operation regions ............................................................................................................10

1.5 Analog blocks ........................................................................................................................................................12

1.6 Integrated digital blocks.......................................................................................................................................12

1.7 I/O subsystem .......................................................................................................................................................13

1.8 System resources..................................................................................................................................................14

2 Power subsystem..........................................................................................................................15

2.1 VIN under-voltage lockout (UVLO) .......................................................................................................................16

2.2 Using external VDDD supply.................................................................................................................................16

2.3 Power modes ........................................................................................................................................................16

3 Pin list .........................................................................................................................................17

4 EZ-PD™ PMG1-B1 programming .....................................................................................................21

4.1 Programming the device flash over SWD interface.............................................................................................21

5 Applications .................................................................................................................................22

6 Electrical specifications.................................................................................................................23

6.1 Absolute maximum ratings ..................................................................................................................................23

6.2 Device-level specifications ...................................................................................................................................24

6.3 Digital peripherals.................................................................................................................................................27

6.4 System resources..................................................................................................................................................29

7 Ordering information ....................................................................................................................36

7.1 Ordering code definition ......................................................................................................................................36

8 Packaging ....................................................................................................................................37

8.1 Package diagram ..................................................................................................................................................37

9 Acronyms.....................................................................................................................................38

10 Document conventions................................................................................................................39

10.1 Units of measure .................................................................................................................................................39

Revision history ..............................................................................................................................40

Datasheet

5

002-35400 Rev. *D

2022-12-19

EZ-PD™ PMG1-B1 USB Type-C Buck-boost controller

Single-port

Functional overview

1

Functional overview

MCU subsystem

CPU

1.1

1.1.1

The Cortex®-M0 in EZ-PD™ PMG1-B1 devices is a 32-bit MCU, which is optimized for low-power operation with

extensive clock gating. It mostly uses 16-bit instructions and executes a subset of the Thumb-2 instruction set. It

also includes a hardware multiplier, which provides a 32-bit result in one cycle. It includes an interrupt controller

(the NVIC block) with 32 interrupt inputs and a wakeup interrupt controller (WIC), which can wake the processor

up from Deep Sleep mode.

1.1.2

Flash ROM and SRAM

EZ-PD™ PMG1-B1 devices have 128-KB flash and 32-KB ROM for non-volatile storage. ROM stores libraries for

authentication and device drivers such as I²C, SPI, and so on. Flash provides the flexibility to store code for any

customer feature and allows firmware upgrades to meet the latest USB power delivery specifications and appli-

cation needs.

The 16-KB RAM is used under software control to store the temporary status of system variables and parameters.

A supervisory ROM that contains boot and configuration routines is provided.

1.2

USBPD subsystem

This subsystem provides the interface to the Type-C USB port. This subsystem comprises:

• USBPD physical layer

• VCONN switches and 100mW VCONN source

• Undervoltage protection (UVP), overvoltage protection (OVP) on VBUS

• Output high-side current sense amplifier (HS CSA)

• VBUS discharge control

• Gate driver for VBUS consumer NFET

• Charger detection block for legacy charging (for example: BC1.2, Apple charging, and so on)

• Short-circuit protection (SCP)

• VBUS to CC SCP

1.2.1

USBPD physical layer

The USBPD subsystem contains the USBPD physical layer block and supporting circuits. The USBPD physical

layer consists of a transmitter and receiver that communicate BMC encoded data over the CC channel per the PD

3.1 standard. All communication is half-duplex. The physical layer or PHY implements collision avoidance to

minimize communication errors on the channel. The USBPD block includes all termination resistors (R_pand R_d)

and their switches as required by the USB Type-C spec. R_pand R_dresistors are required to implement connection

detection, plug orientation detection and for the establishment of the USB source/sink roles. The R_presistor is

implemented as a current source.

The PMG1-B1 device family along with the accompanying firmware is fully complaint with revision 3.1 of the USB

Power delivery specification. The device supports programmable power supply (PPS) operation at all valid

voltages from 3.3 to 21 V.

EZ-PD™ PMG1-B1 devices support R_punder HW control in unconnected (standby) state to minimize standby

power.

EZ-PD™ PMG1-B1 devices support USBPD extended messages containing data of up to 260 bytes. The extended

messages are larger than expected by USBPD 2.0 hardware. As per the USBPD protocol specification, USBPD 3.1

compliant devices implement a chunking mechanism; messages are limited to revision 2.0 sizes unless both

source and sink confirm and negotiate compatibility with longer message lengths.

Datasheet

6

002-35400 Rev. *D

2022-12-19

EZ-PD™ PMG1-B1 USB Type-C Buck-boost controller

Single-port

Functional overview

1.2.2

VCONN switches

EZ-PD™ PMG1-B1’ internal LDO voltage regulator is capable of powering a 100 mW VCONN supply for electroni-

cally marked cable assemblies (EMCA), VCONN-powered devices (VPD), and VCONN-powered accessories (VPA)

as defined in the USB Type-C specification. All circuitry including VCONN switches and overcurrent protection is

integrated in the device. In the event the VCONN current exceeds the VCONN OCP limit, EZ-PD™ PMG1-B1 can be

configured to shut down the Type-C port after a certain number of user configurable retries. The port can be

re-enabled after a physical disconnect.

1.2.3

VBUS UVP and OVP

VBUS under-voltage and overvoltage faults are monitored using internal resistor dividers. The fault thresholds

and response times are user configurable. In the event of a UVP or OVP, EZ-PD™ PMG1-B1 can be configured to

shut down the Type-C port after a certain number of user configurable retries. The port can be re-enabled after

a physical disconnect followed by re-connect.

1.2.4

VOUT OCP and SCP

VOUT overcurrent and short-circuit faults are monitored using internal CSAs. Similar to OVP and UVP, the OCP

and SCP fault thresholds and response times are configurable as well. In the event of OCP or SCP, PMG1-B1 can

be configured to shut down the buck-boost controller.

1.2.5

HS-CSA for VOUT

EZ-PD™ PMG1-B1 device family supports VOUT current measurement and control using an external resistor

(5 mΩ) in series with the VOUT path. The voltage drop across this resistor is used to measure the average output

current. The same resistor is also used to sense and precisely control the output current in the constant current

mode of operation.

1.2.6

VBUS discharge control

The chip supports high-voltage (21.5 V) VBUS discharge circuitry. Upon the detection of device disconnection,

faults, or hard resets, the chip will discharge the output VBUS terminals to vSafe5V and/or vSafe0V within the time

limits specified in the USBPD specification.

1.2.7

Gate driver for VBUS consumer NFET

EZ-PD™ PMG1-B1 devices have an integrated high-voltage gate driver to drive the gate of an external high-side

NFET on the VBUS consumer path. The gate driver drives the load switch that controls the connection between

VBUS_C and CSPI. VBUS_CTRL is the output of this gate driver. To turn off the external NFET, the gate driver drives

VBUS_CTRL low to 0 V. To turn on the external NFET, it drives the gate to VBUS_C + 8 V. There is an optional slow

turn-on feature which reduces the high-current spikes on the output. For a typical gate capacitance of 3 nF, a slow

turn-on time of 2 to 10 ms is configurable using firmware.

1.2.8

Legacy charge detection and support

EZ-PD™ PMG1-B1 implements battery charger emulation and detection (source and sink) for USB BC.1.2, legacy

Apple charging, Qualcomm quick charge 2.0/3.0/4.0/5.0, and Samsung AFC protocols.

1.2.9

VBUS to CC short protection

CC pins have integrated protection from accidental shorts to high-voltage VBUS and VBAT. EZ-PD™ PMG1-B1

devices can handle up to 24 V external voltage on its CC pins without damage. In the event, an overvoltage is

detected on the CC pin, it can be configured to shut down the Type-C port completely. The port will resume

normal operation once the CC voltage detected is within normal range.

Datasheet

7

002-35400 Rev. *D

2022-12-19

EZ-PD™ PMG1-B1 USB Type-C Buck-boost controller

Single-port

Functional overview

1.3

Buck-boost subsystem

The buck-boost subsystem in EZ-PD™ PMG1-B1 devices can be configured to operate in buck-boost mode,

buck-only mode or boost-only mode. While buck-boost mode requires four external switching FETs, buck-only

and boost-only modes require only two FETs. Figure 1 shows the buck-boost subsystem’s main external compo-

nents and connections.

5 m

V_IN

V_OUT

CSR1

CSR2

VDDD

CYPM1115/16

Figure 1

Buck-boost schematic showing external components

Buck-boost subsystem in EZ-PD™ PMG1-B1 devices have the following key functional blocks:

• High-side (cycle-by-cycle) CSA

• High-side and low-side gate driver

• Pulse-width modulator (PWM)

• Error amplifier (EA)

1.3.1

High-side (cycle-by-cycle) CSA

EZ-PD™ PMG1-B1 device’s buck-boost controller implements peak current control in both boost and buck modes.

A high-side CSA is used for peak current sensing through an external resistor (5 mΩ; see CSR1 in Figure 1) placed

in series with the buck control FET. This CSA has a high bandwidth and a very wide common mode range. This

CSR is connected to the CSA block through pins CSPI and CSNI as shown in Figure 1. This block implements slope

compensation to avoid sub-harmonic oscillation for the internal current loop. In addition to peak current

sensing, it provides a current limit comparator for shutting off the buck-boost converter if the current hits an

upper threshold which is programmable.

Datasheet

8

002-35400 Rev. *D

2022-12-19

EZ-PD™ PMG1-B1 USB Type-C Buck-boost controller

Single-port

Functional overview

1.3.2

High-side gate driver and low-side gate driver (HG/LG)

EZ-PD™ PMG1-B1’ buck-boost controller provides four N-channel MOSFET gate drivers: two floating high-side

gate drivers at the HG1 and HG2 pins, and two ground referenced low-side drivers at the LG1 and LG2 pin. The

high-side gate drivers drive the high-side external FET with a nominal VGS of 5 V. The high-side gate driver has a

programmable drive strength to drive external FET. An external capacitor and schottky diode form a bootstrap

network to collect and store the high voltage source (VIN + ~5 V for HG1 and VOUT + ~5 V for HG2) needed to drive

the high-side FET. The low-side gate driver drives the low-side external FET with a nominal VGS of 5 V using energy

sourced from EZ-PD™ PMG1-B1’ internal LDO regulator and stored in the capacitor between PVDD and PGND.

Low-side gate driver has programmable drive strength to drive external FET. In addition to drive strength, the

high-side gate driver and the low-side gate driver have programmable options for deadtime control and

zero-crossing levels. High-side gate driver and low-side gate driver blocks include zero-crossing detector (ZCD)

to implement discontinuous-conduction mode (DCM) mode with diode emulation.

The gate drivers for the switching FETs function at their nominal drive voltage levels (5 V) provided the VIN voltage

is between 4.5 V and 24 V.

1.3.3

Error amplifier (EA)

EZ-PD™ PMG1-B1’ buck-boost controller contains two EAs for output voltage and current regulation. The EA is a

trans-conductance type amplifier with single compensation pin (COMP) to ground for both the voltage and

current loops. In voltage regulation, the output voltage is compared with the internal reference voltage and the

output of EA is fed to the PWM block. In current regulation, the average current is sensed by VOUT high-side CSA

through the external resistor. The output of the VOUT CSA is compared with an internal reference in EA block and

EA output is fed to the PWM block. EZ-PD™ PMG1-B1 firmware configures and controls the integrated program-

mable EA circuit for achieving the required VOUT voltage output from the power section.

1.3.4

Pulse-width modulator (PWM)

EZ-PD™ PMG1-B1 device family’s PWM block generates the control signals for the gate drivers driving the external

FETs in peak current mode control. There are many programmable options for minimum/maximum pulse width,

minimum/maximum period, frequency and pulse skip levels to optimize the system design.

EZ-PD™ PMG1-B1 devices have two firmware-selectable operating modes to optimize efficiency and reduce

losses under light load conditions: PSM and FCCM.

1.3.5

Pulse skipping mode (PSM)

In pulse skipping mode, the controller reduces the total number of switching pulses without reducing the active

switching frequency by working in “bursts” of normal nominal-frequency switching interspersed with intervals

without switching. The output voltage thus increases during a switching burst and decreases during a quiet

interval. This mode results in minimal losses at the cost of higher output voltage ripple. When in this mode,

EZ-PD™ PMG1-B1 devices monitor the voltage across the buck or boost sync FET to detect when the inductor

current reaches zero; when this occurs, the EZ-PD™ PMG1-B1 devices switch off the buck or boost sync FET to

prevent reverse current flow from the output capacitors (i.e. diode emulation mode). Several parameters of this

mode are programmable through firmware, allowing the user to strike their own balance between light load

efficiency and output ripple.

1.3.6

Forced continuous conduction mode (FCCM)

In FCCM mode, the nominal switching frequency is maintained at all times, with the inductor current going below

zero (i.e. “backwards” or from the output to the input) for a portion of the switching cycle as necessary to

maintain the output voltage and current. This keeps the output voltage ripple to a minimum at the cost of

light-load efficiency.

Datasheet

9

002-35400 Rev. *D

2022-12-19

EZ-PD™ PMG1-B1 USB Type-C Buck-boost controller

Single-port

Functional overview

1.4

Buck-boost controller operation regions

The input-side CSA's output is compared with the output of the EA to determine the pulse width of the PWM. PWM

block compares the input voltage and output voltage to determine the buck, boost, and buck-boost regions. The

switching time/period of the four gate drivers (HG1, LG1, HG2, LG2) depends upon the region in which the block

is operating as well as the mode such as DCM or FCCM. The exact VIN vs VOUT thresholds for transitions into and

out of each region are adjustable in firmware including the hysteresis.

1.4.1

Buck region operation (VIN >> VOUT)

When the VIN voltage is significantly higher than the required VOUT voltage, EZ-PD™ PMG1-B1 devices operate in

the buck region. In this region, the boost side FETs are inactivated, with the boost control FET (connected to LG2)

turned off and the boost sync FET (connected to HG2) turned on. The buck side FETs are controlled as a buck

converter with synchronous rectification as shown in Figure 2.

ON

HG1

(Buck

Control)

OFF

ON

LG1

(Buck

Sync)

OFF

ON

LG2

(Boost

Control)

OFF

ON

HG2

(Boost

Sync)

OFF

Inductor

Current

0

t

Figure 2

Buck operation waveforms

1.4.2

Boost region operation (VIN << VOUT)

When the VIN voltage is significantly lower than the required VOUT voltage, EZ-PD™ PMG1-B1 devices operate in

the boost region. In this region, the buck side FETs are inactivated, with the sync FET turned off and the buck

control FET turned on. The boost side FETs are controlled as a boost converter with synchronous rectification as

shown in Figure 3.

ON

HG1

(Buck

Control)

OFF

ON

LG1

(Buck

Sync)

OFF

ON

LG2

(Boost

Control)

OFF

ON

OFF

Inductor

Current

0

t

Figure 3

Boost operation waveforms

Datasheet

10

002-35400 Rev. *D

2022-12-19

EZ-PD™ PMG1-B1 USB Type-C Buck-boost controller

Single-port

Functional overview

1.4.3

Buck-boost region 1 operation (VIN ~> VOUT)

When the VIN voltage is slightly higher than the required VOUT voltage, EZ-PD™ PMG1-B1 devices operate in the

buck-boost region 1. In this region, the boost side works at a fixed 20% duty cycle (programmable) while the buck

side (LG1 / HG1) duty cycle is modulated to control the output voltage. All four FETs are switching every cycle in

this operating region as shown in Figure 4.

ON

HG1

(Buck

Control)

OFF

ON

LG1

(Buck

Sync)

OFF

ON

LG2

(Boost

Control)

OFF

ON

HG2

(Boost

Sync)

OFF

Inductor

Current

0

t

Figure 4

Buck-boost region 1 (VIN ~> VOUT) operation waveforms

1.4.4

Buck-boost region 2 operation (VIN ~< VOUT)

When the VIN voltage is slightly lower than the required VOUT voltage, EZ-PD™ PMG1-B1 devices operate in the

buck-boost region 2. In this region, the buck side works at a fixed 80% duty cycle (programmable) while the boost

side (LG2) duty cycle is modulated to control the output voltage. All four FETs are switching every cycle in this

operating region as shown in Figure 5.

ON

HG1

(Buck

Control)

OFF

ON

LG1

(Buck

Sync)

OFF

ON

LG2

(Boost

Control)

OFF

ON

HG2

(Boost

Sync)

OFF

Inductor

Current

0

t

Figure 5

Buck-boost region 2 (VIN ~< VOUT) operation waveforms

Datasheet

11

002-35400 Rev. *D

2022-12-19

EZ-PD™ PMG1-B1 USB Type-C Buck-boost controller

Single-port

Functional overview

1.4.5

Switching frequency and spread spectrum

EZ-PD™ PMG1-B1 devices offer programmable switching frequency between 150 kHz and 600 kHz. The controller

supports spread spectrum clocking within the operating frequency range in all operating modes. Spread

spectrum is essential for charging applications to meet EMC/EMI requirements by spreading emissions caused

by switching over a wide spectrum instead of a fixed frequency, thereby reducing the peak energy at any

particular frequency. Both the switching frequency and the spread spectrum span are firmware programmable.

1.5

Analog blocks

ADC

1.5.1

EZ-PD™ PMG1-B1 devices have two 8-bit SAR ADCs and one 12-it SAR ADC. The 8-bit SAR ADCs are used for general

purpose A/D conversion applications in the chip. The 12-bit SAR ADC is used for battery monitoring applications.

All ADCs can be accessed from the GPIOs through an on-chip analog mux. See Table 25 for detailed specifications

of the 8-bit ADCs. See Table 26 and Table 27 for detailed specifications of the 12-bit ADC.

1.6

Integrated digital blocks

1.6.1

Serial communication block (SCB)

EZ-PD™ PMG1-B1 devices have three SCB blocks that can be configured for I²C, SPI, UART or LIN. These blocks

implement full multi-master and slave I²C interfaces capable of multi-master arbitration. This I²C implemen-

tation is compliant with the standard Philips I²C specification v3.0. These blocks operate at speeds of up to 1

Mbps and have flexible buffering options to reduce interrupt overhead and latency for the CPU. The SCB blocks

support 8-byte deep FIFOs for receive and transmit, which, by increasing the time given for the CPU to read data,

greatly reduces the need for clock stretching caused by the CPU not having read data on time. The I²C port I/Os

for SCB0 are overvoltage tolerant (OVT). The I²C ports for SCB1-2 are not OVT tolerant.

1.6.2

Timer, counter, pulse-width modulator (TCPWM)

The TCPWM block of EZ-PD™ PMG1-B1 devices support eight timers or counters or pulse-width modulators.

These timers are available for internal timer use by firmware or for providing PWM-based functions on the GPIOs.

Datasheet

12

002-35400 Rev. *D

2022-12-19

EZ-PD™ PMG1-B1 USB Type-C Buck-boost controller

Single-port

Functional overview

1.7

I/O subsystem

The EZ-PD™ PMG1-B1 devices have 21 GPIOs including the I²C and SWD pins which can also be used as GPIOs. The

GPIO block implements the following:

• Eight output drive modes

- Input only

- Weak pull-up with strong pull-down

- Strong pull-up with weak pull-down

- Open drain with strong pull-down

- Open drain with strong pull-up

- Strong pull-up with strong pull-down

- Disabled

- Weak pull-up with weak pull-down

• Input threshold select (CMOS or LVTTL)

• Individual control of input and output disables

• Hold mode for latching previous state (used for retaining I/O state in Deep Sleep mode)

• Selectable slew rates for dV/dt related noise control

• OVT on one pair of GPIOs

During power-on and reset, the blocks are forced to the disable state so as not to crowbar any inputs and/or cause

excess turn-on current. A multiplexing network known as a high-speed I/O matrix (HSIOM) is used to multiplex

between various signals that may connect to an I/O pin. Pin locations for fixed-function peripherals such as USB

Type-C port are also fixed in order to reduce internal multiplexing complexity. Data output registers and pin state

register store, respectively, the values to be driven on the pins and the states of the pins themselves.

The configuration of the pins can be done by the programming of registers through software for each digital I/O

port. Every I/O pin can generate an interrupt if so enabled and each I/O port has an interrupt request (IRQ) and

interrupt service routine (ISR) vector associated with it.

The I/O ports can retain their state during Deep Sleep mode or remain ON. If the operation is restored using reset,

then the pins shall go the high-Z state. If operation is restored by an interrupt event, then the pin drivers shall

retain their state until firmware chooses to change it. The IOs (on data bus) do not draw current on power down.

Datasheet

13

002-35400 Rev. *D

2022-12-19

EZ-PD™ PMG1-B1 USB Type-C Buck-boost controller

Single-port

Functional overview

1.8

System resources

1.8.1

Watchdog timer (WDT)

EZ-PD™ PMG1-B1 devices have a WDT running from the internal low-speed oscillator (ILO). This allows watchdog

operation during Deep Sleep and generate a watchdog reset (WDR) if not serviced before the timeout occurs. The

WDR is recorded in the Reset Cause register.

1.8.2

Reset

EZ-PD™ PMG1-B1 devices can be reset from a variety of sources including a software reset. Reset events are

asynchronous and guarantee reversion to a known state. The reset cause is recorded in a register, which is

preserved through reset and allows application firmware to determine the cause of the reset. XRES pin is the

dedicated pin for asserting an external hardware reset.

1.8.3

Clock system

EZ-PD™ PMG1-B1 devices have a fully integrated clock with no external crystal required. EZ-PD™ PMG1-B1

device’s clock system is responsible for providing clocks to all sub-systems that require clocks (SCB and PD) and

for switching between different clock sources.

The HFCLK signal can be divided down as shown to generate synchronous clocks for the digital peripherals. The

clock dividers have 8-bit, 16-bit and 16-bit fractional divide capability. The 16-bit capability allows a lot of

flexibility in generating fine-grained frequency values. The clock dividers generate either enabled clocks (that is,

1 in N clocking where N = Divisor) or an approximately 50% duty cycle clock (exactly 50% for even divisors, one

clock difference in the high and low values for odd divisors).

In Figure 6, PERXYZ_CLK represents the clocks for different peripherals.

IMO

HFCLK

Pre-divider

ILO

LFCLK

HFCLK

Prescaler

SYSCLK

HALFSYSCLK

/2

Peripheral

dividers

PERXYZ_CLK

Figure 6

Clocking architecture of EZ-PD™ PMG1-B1 devices

1.8.4

Internal main oscillator (IMO) clock source

The IMO is the primary source of internal clocking in EZ-PD™ PMG1-B1 devices. IMO default frequency for

EZ-PD™ PMG1-B1 devices is 48 MHz2%.

1.8.5

ILO clock source

The ILO is a very low power, relatively inaccurate, oscillator, which is primarily used to generate clocks for

peripheral operation in USB Suspend (Deep Sleep) mode.

Datasheet

14

002-35400 Rev. *D

2022-12-19

EZ-PD™ PMG1-B1 USB Type-C Buck-boost controller

Single-port

Power subsystem

2

Power subsystem

Figure 7 shows an overview of the power subsystem architecture for EZ-PD™ PMG1-B1 devices. The power

subsystem of EZ-PD™ PMG1-B1 devices operate from VIN supply which can vary from 4 to 24 V. The V_DDDpin, the

output of an internal 5 V LDO, gets input from V_INsupply. When input supply to the IC is from CSN0, the standby

regulator provides 3 V to V_DDD. The current capability of the V_DDDpin is up to 75 mA including internal as well as

external loads (applicable only if supply is from V_IN). EZ-PD™ PMG1-B1 devices have two different power modes:

Active and Deep Sleep, transitions between which are managed by the power system. The V_CCDpin, the output

of the core (1.8 V) regulator, is brought out for connecting a 0.1-µF capacitor for the regulator stability only. This

pin is not supported as a power supply for external load.

PVDD

PGND

Buck-Boost

Low-side Driver

0.1µF

VDDD

LDO

VIN

4.7µF

Standby

Regulator

CSNO

VBUS_C

NGDO

CC1

CC2

Core Regulator

(SRSS-Lite)

VCCD

1µF

CC

Tx/Rx

GPIOs

Core

GND

Figure 7

Power system requirement block diagram^[1]

Note

1. It is recommended to tie PGND and GND together in the layout for better EMI performance.

Datasheet

15

002-35400 Rev. *D

2022-12-19

EZ-PD™ PMG1-B1 USB Type-C Buck-boost controller

Single-port

Power subsystem

2.1

VIN under-voltage lockout (UVLO)

EZ-PD™ PMG1-B1 supports UVLO to allow the device to shut down when the input voltage is below the reliable

level. It guarantees predictable behavior when the device is up and running.

2.2

Using external VDDD supply

By default, external VDDD is not supported for EZ-PD™ PMG1-B1 devices. However, usage of external VDDD supply

can be enabled using firmware. The prerequisite for enabling external forcing of VDDD is to always maintain VIN

higher than VDDD.

2.3

Power modes

The power modes of the device accessible and observable by the user are listed in Table 1.

Table 1

Power modes

Description

Mode

Power is valid and XRES is not asserted. An internal reset source is asserted or Sleep controller is

sequencing the system out of reset

RESET

ACTIVE

SLEEP

Power is valid and CPU is executing instructions.

Power is valid and CPU is not executing instructions. All logic that is not operating is clock gated to save

power.

Main regulator and most hard-IP are shut off. Deep Sleep regulator powers logic, but only low-frequency

clock is available.

DEEP SLEEP

XRES

Power is valid and XRES is asserted. Core is powered down.

Datasheet

16

002-35400 Rev. *D

2022-12-19

EZ-PD™ PMG1-B1 USB Type-C Buck-boost controller

Single-port

Pin list

3

Pin list

Table 2

48-QFN package pinout

Absolute

Pin #

Pin name

Description

minimum (V)

maximum (V)

Boosted power supply of the buck high-side gate driver. Bootstrap

capacitor node.

1

2

BST1

–

Connect Schottky diode from VDDD to BST1. Also, connect a bootstrap

capacitor from this pin to SW1.

PVDD+0.5^{[2, 3]}

Buck high-side gate driver output.

Connect to the buck (input) side control (high-side) FET gate. Use a wide

trace to minimize inductance of this connection. Absolute min and max

are with respect to SW1 pin.

HG1

-0.5

Negative power rail of the buck high-side gate driver.

This is also connected to one input terminal of ZCD of buck low-side gate

driver.

3

4

SW1

LG1

-0.7

-0.5

35

Connect to the switch node (inductor) on the buck (input) side. Use a short

and wide trace to minimize the inductance and resistance of this

connection.

Buck low-side gate driver output. Connect to the buck (input) side sync

(low-side) FET gate. Use a wide trace to minimize inductance of this

connection.

PVDD+0.5^[2]

Ground of low-side gate driver. This is also connected to one input

terminal of ZCD of buck low-side gate driver. Connect directly to the port’s

board ground plane.

5

6

7

PGND

PVDD

LG2

-0.3

–

0.3

Supply of low-side gate driver. Connect to VDDD. Use 1 μF and 0.1 μF

VDDD

bypass capacitors as close to the EZ-PD™ PMG1-B1 IC as possible.

Boost low-side gate driver output. Connect to the boost (output) side

control (low-side) FET gate. Use a wide trace to minimize inductance of

this connection.

-0.5

PVDD+0.5^[2]

Output of the buck-boost converter. This is also connected to one input

terminal of reverse current protection of boost high-side gate driver.

Connect to the boost sync (high-side) FET’s drain. Use a dedicated (Kelvin)

trace for this connection.

8

9

VOUT

SW2

Negative power rail of the boost high-side gate driver. This is also

connected to one input terminal of reverse current protection of boost

high-side gate driver.

-0.3

24

Connect to the switch node (inductor) on the boost (output) side. Use a

short and wide trace to minimize the inductance and resistance of this

connection.

Boost high-side gate driver output. Connect to the boost (output) side

sync (high-side) FET gate. Use a wide trace to minimize inductance of this

connection.

10

11

HG2

-0.5

–

PVDD+0.5^[2]

Boosted power supply of the boost high-side gate driver. Bootstrap

capacitor node. Connect Schottky diode from V_DDDto BST2. Also, connect

a bootstrap capacitor from this pin to SW2.

BST2

12

13

VBUS_CTRL

COMP

32

VBUS NFET gate driver output. Connect to the provider NFET’s gate.

-0.5

EA output pin. Connect a compensation network to GND. Contact Infineon

for assistance in designing the compensation network.

PVDD+0.5^[2]

Type-C connector VBUS voltage. Connect to the Type-C connector’s VBUS

pin.

14

15

16

VBUS_C

VOUT_EA

CSNO

Input of feedback voltage of EA from converter output

-0.3

24

Negative input of output current sensing amplifier.

Connect to negative terminal of the output current sense resistor.

Positive input of output CSA. Connect to positive terminal of the output

current sense resistor.

17

CSPO

Notes

2. Max voltage must not exceed 6 V.

3. Max absolute voltage w.r.t GND must not exceed 40 V.

Datasheet

17

002-35400 Rev. *D

2022-12-19

EZ-PD™ PMG1-B1 USB Type-C Buck-boost controller

Single-port

Pin list

Table 2

48-QFN package pinout (continued)

Absolute

Pin #

Pin name

Description

minimum (V)

maximum (V)

Type-C connector configuration channel 2. Connect directly to the CC2 pin

on the port’s Type-C connector. Also, connect a 390-pF capacitor to

ground.

18

19

CC2

-0.5

24

Type-C connector configuration channel 1. Connect directly to the CC1 pin

on the port’s Type-C connector. Also, connect a 390-pF capacitor to

ground.

CC1

22

40

VDDD

XRES

–

6

5-V LDO output. Connect a 1-μF ceramic bypass capacitor to this pin.

-0.5

PVDD+0.5^[2]

External reset – active low. Contains a 3.5-kΩ to 8.5-kΩ internal pull-up.

43

44

45

46

47

48

GND

VDDD

VCCD

VIN

–

6

–

Chip ground. Connect to the exposed pad (EPAD).

–

5-V LDO output. Connect a 10-μF bypass capacitor to this pin.

1.8-V core LDO output. Connect a 0.1-μF bypass capacitor to ground.

Do not connect anything else to this pin.

4 to 24 V input supply. Connect a ceramic bypass capacitor to GND close

to this pin.

Positive input of input CSA. Connect to the positive terminal of the input

current sense resistor. Use a dedicated (Kelvin) connection.

CSPI

-0.3

–

40

–

Negative input of input CSA. Connect to the negative terminal of the input

current sense resistor. Use a dedicated (Kelvin) connection.

CSNI

-

EPAD

Exposed ground pad. Connect directly to pin 36 and pin 22.

Notes

2. Max voltage must not exceed 6 V.

3. Max absolute voltage w.r.t GND must not exceed 40 V.

Datasheet

18

002-35400 Rev. *D

2022-12-19

EZ-PD™ PMG1-B1 USB Type-C Buck-boost controller

Single-port

Pin list

1

2

3

4

BST1

HG1

SW1

36

35

34

33

GPIO8

GPIO7

GPIO6

GPIO5

LG1

5

6

7

8

PGND

PVDD

LG2

VOUT

SW2

32

31

30

29

28

27

26

25

GPIO19

GPIO18

GPIO17

GPIO16

GPIO15

GPIO14

GPIO13

GPIO4

EPAD

9

10

11

12

HG2

BST2

VBUS_CTRL

Figure 8

48-QFN pinout

Datasheet

20

002-35400 Rev. *D

2022-12-19

EZ-PD™ PMG1-B1 USB Type-C Buck-boost controller

Single-port

EZ-PD™ PMG1-B1 programming

4

EZ-PD™ PMG1-B1 programming

Program the application firmware into a EZ-PD™ PMG1-B1 device by programming the device flash over SWD

interface.

4.1

Programming the device flash over SWD interface

The EZ-PD™ PMG1-B1 family of devices can be programmed using the SWD interface. Infineon provides

programming hardware called CY8CKIT-005 MiniProg4 kit, which can be used to program the flash as well as

debug firmware. The flash is programmed by downloading the information from a hex file.

As shown in the block diagram in Figure 9, the SWD_DAT and SWD_CLK pins are connected to the host

programmer’s SWDIO (data) and SWDCLK (clock) pins respectively. During SWD programming, the device can be

powered by the host programmer by connecting its VTARG (power supply to the target device) to VDDD pins of

EZ-PD™ PMG1-B1 device. If the EZ-PD™ PMG1-B1 device is powered using an onboard power supply, it can be

programmed using the “reset programming” option. For more details, refer the CCGx (CYPDxxxx) programming

specifications.

3.3V

V_DD

Host Programmer

VTARG

CYPM1115/16

VDDD

10µF

1µF

0.1µF

SWDCLK

SWDIO

XRES

SWD_CLK

SWD_DAT

XRES

V_CCD

0.1µF

GND

Figure 9

Connecting the programmer to CYPM1115/16 device

Datasheet

21

002-35400 Rev. *D

2022-12-19

EZ-PD™ PMG1-B1 USB Type-C Buck-boost controller

Single-port

Applications

5

Applications

Figure 10 shows a typical power tool sink application block diagram using the EZ-PD™ PMG1-B1 device. In this

application, EZ-PD™ PMG1-B1 is always in DRP role supporting the charging of the sink. It negotiates the power

with the connected sink and uses the integrated buck-boost controller to supply the required voltage and

current.

EZ-PD™ PMG1-B1 measures various temperatures using external NTC thermistors. EZ-PD™ PMG1-B1 throttles the

output power based on temperature and/or shuts off the power under critical conditions. It also monitors the

battery voltage and lowers the output power if the battery voltage is lower than the user-configured threshold.

When no load is connected to the USB Type-C port, EZ-PD™ PMG1-B1 remains in standby mode without switching

on the buck-boost controller.

5.0 V to 20.0 V, up to 5.0 A

100 W max

TYPEC_VBUS_IN

Current Monitoring for SCP, OCP, CC Regulation

m

IFX NFET

IFX PFET

V_BAT+ve

V_BUS

5

m

5

IFX NFET

S

D

S

D

G

50k

5

Cell battery

S

D

S

D

VBAT_

CHARGE_

EN_

VDDD

S

PMG1-S0

VDDD

Cell Voltage

monitoring

GPIO4

VBUS_C

Current Sense

Amplifier (CSA),

Slope

Slew Rate Control

NGATE Driver

Error

Amplifier

(CV)

Error

Amplifier

(CC)

GDRV (Buck)

GDRV (Boost)

High-Side CSA

High-Side

Low-Side

High-Side

Low-Side

Voltage/Current

Monitoring

OCP, SCP, OVP,

UVP

VBUS_IN VBUS_C

Discharge Discharge

Driver (HSDR) Driver (LSDR)

Driver (HSDR)

Driver (LSDR)

Compensation

Zero Crossing

Detect (ZCD)

Charge

Control

Zero Crossing

Detect (ZCD)

Charge

Control

CC

Reference

HV

Regulator

(4-24V)

VIN

VDDD

VCCD

Reference

and IDAC

I/O Matrix

GPIO11

Pulse-Width

Modulator

(PWM)

AIN4

AIN3

12-bit SAR

ADC

MCU Subsystem

GPIO12

Cortex-M0

AIN2

LV Regulator

(1.8-5V)

GPIO13

GPIO14

GPIO15

GPIO7

Flash

(128KB)

SROM

(32KB)

SRAM

(16KB)

8-bit ADC

GPIO

AIN1

AIN0

VDDD

Analog

ADC_EN

EN_BAT_TH_SNS

BAT_TH_SNS

ID_SNS

Regulator

TCPWM

Timer/Pulse Width

Modulator

GPIO8

CC1

CC2

VDDD

BMC

PHY

I2C/SPI/UART/

LIN

(Master or

Slave)

GPIO10

VCONN

2.2k 2.2k

GPIO6

GPIO20

GPIO19

GPIO2

GPIO3

GPIO18

GPIO9

GPIO5

GPIO16

GPIO17

EZ-PD™ PMG1-B1

I2C_CLK

DP

Charger

Detect

DM

I2C_SDA

NTCP0

GND

NTCP1

SOURCE OUTPUT OCP FLAG

SOURCE OUTPUT V_SELECT

P2.3 SMD (NC)

POR/

RESET

SWD_DAT

SWD_CLK

GND

XRES / PMG1-B1_XRES

Figure 10

EZ-PD™ PMG1-B1 battery pack charging solution diagram

Datasheet

22

002-35400 Rev. *D

2022-12-19

EZ-PD™ PMG1-B1 USB Type-C Buck-boost controller

Single-port

Electrical specifications

6

Electrical specifications

6.1

Table 4

Absolute maximum ratings

Absolute maximum ratings^[5]

Parameter

Description

Min Typ

Max

Unit Details/conditions

V

Maximum input supply voltage

40

IN_MAX

V

Maximum supply voltage relative to V

DDD_MAX

SS

6

V

–

5V_MAX

SS

V

Max V

(P0/P1) voltage relative to V

V

–

BUS_C_MAX

CC_PIN_ABS

BUS_C

SS

24

V

Max voltage on CC1 and CC2 pins

Inputs to GPIO

V

+ 0.5

DDD

GPIO_ABS

–0.5

V

OVT GPIO voltage

6

GPIO_OVT_ABS

–

I

Maximum current per GPIO

–25

25

GPIO_ABS

mA

V

GPIO injection current, max for V > V

,

Absolute max,

IH

DDD

I

–0.5

0.5

GPIO_INJECTION

and min for V < V

current injected per pin

IL

SS

ESD_HBM

Electrostatic discharge human body model 2000

All pins

–

Electrostatic discharge charged device

Charged device model

ESD

ESD_CDM

LU

500

model

Pin current for latch-up

Junction temperature

–100

–40

100

125

mA

°C

–

T

J

Note

4. The standard compliance will not be performed on this demonstration hardware. Customers are responsible for their

final end product compliance.

5. Usage above the absolute maximum conditions listed in Table 5 may cause permanent damage to the device. Exposure

to absolute maximum conditions for extended periods of time may affect device reliability. The maximum storage

temperature is 150°C in compliance with JEDEC Standard JESD22-A103, high temperature storage life. When used below

absolute maximum conditions but above normal operating conditions, the device may not operate to specification.

Datasheet

23

002-35400 Rev. *D

2022-12-19

EZ-PD™ PMG1-B1 USB Type-C Buck-boost controller

Single-port

Electrical specifications

6.2

Device-level specifications

All specifications are valid for –40°C ≤ T_A≤ 105°C and T_J≤ 125°C, except where noted. Specifications are valid for

3.0 to 5.5 V except where noted.

6.2.1

DC specifications

Table 5

DC Specifications (operating conditions)

Spec ID

Parameter Description

Min

Typ Max Unit Details/conditions

SID.PWR#1

V

Input supply voltage

4.0

IN

24

Buck-boost operating input

supply voltage

SID.PWR#1A

SID.PWR#2

V

IN_BB

4.5

VDDD output with

V

4.6

DDD_REG

VIN 5.5 to 24 V, max load = 75 mA

–

5.5

VDDD output with

VIN 4.5 to 5.5 V,

SID.PWR#2A V

V

-0.7

IN

V

–

DDD_BYPASS

max load = 75 mA

VDDD output with VIN 4 to 4.5 V,

max load = 20 mA

SID.PWR#3

SID.PWR#20

SID.PWR#5

V

V - 0.2

–

21.5

–

DDD_MIN

IN

VBUS

VBUS_C valid range

3.3

–

Regulated output voltage

(for core logic)

V

1.8

100

10

CCD

External regulator voltage

bypass for VCCD

SID.PWR#16

SID.PWR#17

SID.PWR#18

C

80

–

120

nF

µF

EFC_VCCD

EXC_VDDD

Power supply decoupling

C

X5R ceramic

capacitor for V

DDD

Bootstrap supply capacitor

(BST1, BST2)

C

0.1

EXV

T = 25°C, VIN = 12 V. CC IO IN

A

–

transmit or receive, no I/O

sourcing current, No VCONN

Supply current at 0.4 MHz

switching frequency

SID.PWR#24

I

50

mA load current, CPU at 24 MHz,

PD port active. Buck-boost

converter on, 3-nF gate driver

capacitance.

DD_ACT

Deep Sleep mode

Type-C not attached,

V

= 12 V. CC wakeup on,

CC enabled for wakeup.

IN

SID_DS1

SID_DS2

I

Type-C not connected,

Source mode.

80

50

R connection should be

DD_DS1

DD_DS2

p

enabled for the PD port.

–

µA

T = 25°C.

A

USBPD disabled. Wake-up

V

= 12 V, GPIO wake-up

from GPIO. T = 25°C.

IN

A

All faults disabled.

Datasheet

24

002-35400 Rev. *D

2022-12-19

EZ-PD™ PMG1-B1 USB Type-C Buck-boost controller

Single-port

Electrical specifications

6.2.2

Table 6

Spec ID

CPU

CPU specifications

Parameter Description

Min

Typ Max Unit Details/conditions

–40°C ≤ T ≤ +105°C,

A

SID.CLK#4

F

CPU input frequency

–

48

–

MHz

µs

CPU

all V

DDD

–

SID.PWR#19

SYS.XRES#5

T

Wake-up from Deep Sleep mode

External reset pulse width

35

–

DEEPSLEEP

T

5

–

XRES

–

Power-up to “Ready to Accept

SYS.FES#1

5

25

ms

2

_PWR_RDY

I C/CC command”

6.2.3

GPIO

Table 7

GPIO DC specifications

Spec ID

Parameter Description

Min

Typ

Max

Unit Details/conditions

SID.GIO#9

SID.GIO#10

SID.GIO#11

SID.GIO#12

V

Input voltage high threshold

Input voltage low threshold

LVTTL input

0.7 × V

–

0.3 × V

–

IH_CMOS

DDD

CMOS input

V

–

2.0

–

IL_CMOS

DDD

V

IH_TTL

–40°C ≤ TA ≤ +105°C

V

LVTTL input

0.8

–

V

IL_TTL

I

= –4 mA,

OH

SID.GIO#7

V

Output voltage high level

V

– 0.6

–

OH_3V

DDD

–40°C ≤ T ≤ +105°C

A

I

= 10 mA,

OL

SID.GIO#8

SID.GIO#2

SID.GIO#3

V

Output voltage low level

–

0.6

8.5

OL_3V

–40°C ≤ T ≤ +105°C

A

Rpu

Pull-up resistor when enabled

3.5

5.6

k –40°C ≤ T ≤ +105°C

A

Pull-down resistor when

enabled

Rpd

Input leakage current

(absolute value)

SID.GIO#4

SID.GIO#5

SID.GIO#6

I

2

22

7

nA +25 °C T , 3-V V

A DDD

IL

–

–40°C ≤ T ≤ +105°C,

A

C

Max pin capacitance

–

capacitance on DP, DM

pins

PIN_A

pF

–40°C ≤ T ≤ +105°C,

A

C

Max pin capacitance

3

–

all V , all other I/Os

DDD

Input hysteresis, LVTTL,

SID.GIO#13

SID.GIO#14

V

100

V

–

> 2.7 V

DDD

HYSTTL

V

> 2.7 V

DDD

–

mV

V

Input hysteresis CMOS

0.1 × V

HYSCMOS

DDD

Table 8

GPIO AC specifications

Parameter Description

Spec ID

Min

Typ Max Unit Details/conditions

SID.GIO#16

SID.GIO#17

SID.GIO#18

SID.GIO#19

T

Rise time in fast strong mode

Fall time in fast strong mode

Rise time in slow strong mode

Fall time in slow strong mode

RISEF

FALLF

RISES

FALLS

2

12

ns

60

T

10

C

= 25 pF,

load

–40°C ≤ T ≤ +105°C

A

–

GPIO F ; 3.0 V V

5.5 V.

OUT

DDD

SID.GIO#20

SID.GIO#21

SID.GIO#22

F

16

7

GPIO_OUT1

GPIO_OUT2

Fast strong mode.

GPIO F ; 3.0 V V

5.5 V.

OUT

DDD

–

MHz

Slow strong mode.

GPIO input operating

frequency; 3.0 V V

F

16

–40°C ≤ T ≤ +105°C

A

GPIO_IN

5.5 V.

DDD

Datasheet

25

002-35400 Rev. *D

2022-12-19

EZ-PD™ PMG1-B1 USB Type-C Buck-boost controller

Single-port

Electrical specifications

Table 9

Spec ID

GPIO OVT DC specifications

Parameter

Description

Min

Typ Max Unit Details/conditions

Max / min current in

GPIO_20VT latch up

current limits

to any input or

SID.GPIO_20VT_GIO#4

GPIO_20VT_I_LU

-140

140 mA

output, pin-to-pin,

pin-to-supply

GPIO_20VT pull-up

resistor value

SID.GPIO_20VT_GIO#5

SID.GPIO_20VT_GIO#6

GPIO_20VT_RPU

GPIO_20VT_RPD

8.5

–40°C ≤ T ≤ +105°C,

A

3.5

–

kΩ

GPIO_20VT

pull-down resistor

value

all V

DDD

8.5

2

GPIO_20VT input

leakage current

(absolute value)

SID.GPIO_20VT_GIO#16

GPIO_20VT_IIL

nA +25°C T , 3-V V

A DDD

GPIO_20VT pin

capacitance

–40°C ≤ T ≤ +105°C,

A

SID.GPIO_20VT_GIO#17

SID.GPIO_20VT_GIO#33

SID.GPIO_20VT_GIO#36

GPIO_20VT_CPIN

GPIO_20VT_Voh

GPIO_20VT_Vol

10

–

pF

all V

DDD

–

GPIO_20VT output

voltage high level

VDDD-0.6

I

= -4 mA

= 8 mA

OH

OL

GPIO_20VT output

voltage low level

–

2

0.6

–

V

GPIO_20VT LVTTL

input

SID.GPIO_20VT_GIO#41 GPIO_20VT_Vih_LVTTL

SID.GPIO_20VT_GIO#42 GPIO_20VT_Vil_LVTTL

SID.GPIO_20VT_GIO#43 GPIO_20VT_Vhysttl

GPIO_20VT LVTTL

input

–40°C ≤ T ≤ +105°C,

A

–

0.8

–

all V

DDD

GPIO_20VT input

hysteresis LVTTL

100

mV

GPIO_20VT

V (GPIO_20VT pin) >

DDD

SID.GPIO_20VT_GIO#45 GPIO_20VT_ITOT_GPIO maximum total sink

pin current to ground

–

95 mA

V

Table 10

Spec ID

GPIO OVT AC specifications

Parameter

Description

Min Typ Max Unit Details/conditions

GPIO_20VT rise time in

fast strong mode

SID.GPIO_20VT_70

GPIO_20VT_TriseF

GPIO_20VT_TfallF

GPIO_20VT_TriseS

GPIO_20VT_TfallS

1

15

70

GPIO_20VT fall time in

fast strong mode

SID.GPIO_20VT_71

ns

GPIO_20VT rise time in

slow strong mode

SID.GPIO_20VT_GIO#46

SID.GPIO_20VT_GIO#47

10

GPIO_20VT fall time in

slow strong mode

All V , C

= 25 pF

DDD load

–

GPIO_20VT GPIO Fout;

SID.GPIO_20VT_GIO#48 GPIO_20VT_FGPIO_OUT1 3 V  V

 5.5 V.

33

7

DDD

Fast strong mode.

GPIO_20VT GPIO Fout;

SID.GPIO_20VT_GIO#50 GPIO_20VT_FGPIO_OUT3 3 VV 5.5V.

–

MHz

DDD

Slow strong mode.

GPIO_20VT GPIO input

SID.GPIO_20VT_GIO#52 GPIO_20VT_FGPIO_IN operating frequency;

8

All V

DDD

3 V V

5.5 V

DDD

Datasheet

26

002-35400 Rev. *D

2022-12-19

EZ-PD™ PMG1-B1 USB Type-C Buck-boost controller

Single-port

Electrical specifications

6.2.4

XRES

Table 11

XRES DC specifications

Spec ID

Parameter Description

Min

0.7 × V

Typ

Max

Unit Details/conditions

Input voltage high

SID.XRES#1

SID.XRES#2

SID.XRES#3

SID.XRES#4

V

–

IH_XRES

DDD

threshold on XRES pin

V

CMOS input

–

Input voltage low

V

–

0.3 × V

IL_XRES

IN_XRES

HYSXRES

DDD

threshold on XRES pin

Input capacitance on

XRES pin

C

–

7

–

pF

Input voltage hysteresis

on XRES pin

V

0.05 × V

mV

DDD

6.3

Digital peripherals

The following specifications apply to the timer/counter/PWM peripherals in the timer mode.

6.3.1

Pulse-width modulation (PWM) for GPIO pins

Table 12

PWM AC specifications

Spec ID

Parameter Description

Operating frequency

Min Typ Max Unit Details/conditions

SID.TCPWM.1 TCPWM

–

Fc

MHz Fc max = CLK_SYS

FREQ

Minimum possible width of

overflow, underflow, and CC

(counter equals compare value)

outputs

SID.TCPWM.3

T

Output trigger pulse width 2/Fc

PWMEXT

–

ns

Minimum time between successive

counts

SID.TCPWM.4

SID.TCPWM.5

T

Resolution of counter

1/Fc

PWM resolution

CRES

Minimum pulse width of PWM

output

PWM

RES

6.3.2

Table 13

I²C

Fixed I²C AC specifications

Parameter Description

Spec ID

Min Typ Max Unit Details/conditions

Mbps –

SID153

F

Bit rate

–

1

I2C1

6.3.3

UART

Table 14

Fixed UART AC specifications

Spec ID

Parameter Description

Min Typ Max Unit Details/conditions

Mbps –

SID162

F

Bit rate

–

1

UART

Datasheet

27

002-35400 Rev. *D

2022-12-19

EZ-PD™ PMG1-B1 USB Type-C Buck-boost controller

Single-port

Electrical specifications

6.3.4

SPI

Table 15

Fixed SPI AC specifications

Spec ID

Parameter Description

Min Typ Max Unit Details/conditions

MHz –

SPI operating frequency

SID166

F

–

8

SPI

(master; 6X oversampling)

Table 16

Fixed SPI master mode AC specifications

Parameter Description

Spec ID

Min Typ Max Unit Details/conditions

SID167

T

MOSI valid after SClock driving edge

–

15

–

DMO

MISO valid before SClock capturing

edge

Full clock,

SID168

SID169

T

20

DSI

–

ns late MISO sampling

–

Referred to slave capturing

edge

T

Previous MOSI data hold time

0

HMO

Table 17

Spec ID

Fixed SPI slave mode AC specifications

Parameter Description

Min Typ

Max

–

Unit Details/conditions

MOSI valid before Sclock capturing

SID170

SID171

SID171A

T

40

–

DMI

edge

48 +

T

MISO valid after Sclock driving edge

T

= 1/F

CPU CPU

DSO

(3 × T

)

CPU

–

ns

MISO valid after Sclock driving edge

in ext clk mode

T

48

–

DSO_EXT

–

SID172

T

Previous MISO data hold time

SSEL valid to first SCK valid edge

0

HSO

SID172A

100

SSELSCK

6.3.5

Memory

Table 18

Flash AC specifications

Spec ID

Parameter

Description

Min Typ Max Unit Details/conditions

Row (block) write time (Erase and

SID.MEM#2

SID.MEM#1

FLASH_WRITE

20

program)

–40°C ≤ T ≤ +85°C,

A

all V

FLASH_ERASE Row erase time

15.5

7

DDD

ms

–

SID.MEM#5 FLASH_ROW_PGM Row program time after erase

SID178

SID180

T

Bulk erase time (32 KB)

35

BULKERASE

–

T

Total device program time

7.5

s

–

DEVPROG

25°C ≤ T ≤ 55°C,

A

SID.MEM#6

SID182

FLASH_

Flash write endurance

100k

20

cycles

ENPB

all V

DDD

Flash retention, T ≤ 55°C,

A

F

–

RET1

100K P/E cycles

years –

Flash retention, T ≤ 85°C,

A

SID182A

F

10

RET2

10K P/E cycles

Datasheet

28

002-35400 Rev. *D

2022-12-19

EZ-PD™ PMG1-B1 USB Type-C Buck-boost controller

Single-port

Electrical specifications

6.4

System resources

6.4.1

Power-on-reset (POR) with brown out

Table 19

Imprecise power-on reset (IPOR)

Spec ID

Parameter

Description

Min Typ Max Unit Details/conditions

Power-on reset (POR) rising trip

voltage

SID185

SID186

V

0.80

0.70

1.50

1.4

RISEIPOR

FALLIPOR

–40°C ≤T ≤ +105°C,

A

–

V

all V

DDD

POR falling trip voltage

Table 20

Spec ID

Precise POR

Parameter

Description

Min Typ Max Unit Details/conditions

Brown-out detect (BOD) trip

voltage in Active/Sleep modes

SID190

SID192

V

1.48

1.1

1.62

1.5

FALLPPOR

–40°C ≤T ≤ +105°C,

A

–

V

all V

DDD

BOD trip voltage in Deep Sleep

mode

V

FALLDPSLP

6.4.2

SWD interface

Table 21

SWD interface specifications

Spec ID

Parameter

Description

Min

Typ

Max Unit Details/conditions

SID.SWD#1

SID.SWD#2

SID.SWD#3

SID.SWD#4

SID.SWD#5

F_SWDCLK1 3.0 V  V

T_SWDI_SETUP

 5.5 V

–

14

MHz –

DDIO

0.25 × T

–

T_SWDI_HOLD

–

T = 1/f SWDCLK

ns

–

T_SWDO_VALID

T_SWDO_HOLD

–

1

0.50 × T

–

6.4.3

Internal main oscillator

Table 22

IMO AC specifications

Spec ID

Parameter

Description

Min Typ Max Unit Details/conditions

Frequency variation at 48 MHz

(trimmed)

3.0 V ≤ V

< 5.5 V.

DDD

A

SID.CLK#13

F

±2

%

IMOTOL

–40°C ≤ T ≤ 105°C

–

SID226

T

IMO start-up time

IMO frequency

7

µs

STARTIMO

–40°C ≤ T ≤ +105°C,

A

all V

DDD

SID.CLK#1

F

24

48

MHz

IMO

6.4.4

Internal low-speed oscillator

Table 23

ILO AC specifications

Spec ID

SID234

Parameter

Description

Min

–

Typ Max Unit Details/conditions

T

ILO start-up time

ILO duty cycle

ILO frequency

–

2

ms

%

STARTILO1

–40°C ≤ T ≤ +105°C,

A

all V

DDD

SID238

T

40

20

50

40

60

80

ILODUTY

SID.CLK#5

F

kHz

–

ILO

Datasheet

29

002-35400 Rev. *D

2022-12-19

EZ-PD™ PMG1-B1 USB Type-C Buck-boost controller

Single-port

Electrical specifications

6.4.5

PD

Table 24

PD DC specifications

Spec ID

Parameter

vSwing

Description

Min Typ Max Unit Details/conditions

SID.DC.cc_shvt.1

SID.DC.cc_shvt.2

SID.DC.cc_shvt.3

SID.DC.cc_shvt.4

Transmitter output high voltage 1.05

1.2

0.075

75

V

vSwing_low

zDriver

Transmitter output low voltage

Transmitter output impedance

Receiver input impedance

–

33

10

W

zBmcRx

M

Source current for USB

standard advertisement

SID.DC.cc_shvt.5

SID.DC.cc_shvt.6

SID.DC.cc_shvt.7

Idac_std

Idac_1p5a

Idac_3a

64

96

Source current for 1.5A at 5 V

166

304

194

356

µA

Source current for 3A at 5 V

Pull down termination

SID.DC.cc_shvt.8

Rd

resistance when acting as UFP

(upstream facing port)

4.59

5.61

k

–

CC impedance to ground when

disabled

SID.DC.cc_shvt.10

zOPEN

108

CC voltages on DFP

side-standard USB

SID.DC.cc_shvt.11 DFP_default_0p2

0.15

0.25

SID.DC.cc_shvt.12

SID.DC.cc_shvt.13

SID.DC.cc_shvt.14

DFP_1.5A_0p4 CC voltages on DFP side-1.5A

0.35

0.75

2.45

0.45

0.85

2.75

DFP_3A_0p8

DFP_3A_2p6

CC voltages on DFP side-3A

V

CC voltages on UFP

side-standard USB

SID.DC.cc_shvt.15 UFP_default_0p66

0.61

0.7

SID.DC.cc_shvt.16 UFP_1.5A_1p23 CC voltages on UFP side-1.5A

1.16

0.3

10

1.31

0.6

SID.DC.cc_shvt.17

SID.DC.cc_shvt.18

SID.DC.cc_shvt.19

Vattach_ds

Rattach_ds

VTX_step

Deep Sleep attach threshold

Deep Sleep pull-up resistor

TX drive voltage step size

%

50

k

mV

80

120

6.4.6

Analog-to-digital converter

Table 25

ADC DC specifications

Spec ID

Parameter

Description

Min

Typ

Max

Unit Details/conditions

SID.ADC.1

Resolution ADC resolution

–

8

–

Bits –

Reference voltage generated

from bandgap.

SID.ADC.2

SID.ADC.3

SID.ADC.4

SID.ADC.5

SID.ADC.6

INL

Integral non-linearity

Differential non-linearity

–1.5

–2.5

–1.5

1.5

2.5

1.5

Reference voltage generated

LSB

DNL

from V

.

DDD

–

Reference voltage generated

from bandgap.

Gain Error Gain error

VREF_ADC1

Reference voltage generated

V

DDDmax

DDDmin

from V

.

DDD

Reference voltage of ADC

V

Reference voltage generated

from Deep Sleep reference.

VREF_ADC2

1.96

2.0

2.04

Datasheet

30

002-35400 Rev. *D

2022-12-19

EZ-PD™ PMG1-B1 USB Type-C Buck-boost controller

Single-port

Electrical specifications

Table 26

Spec ID

12-bit SAR ADC DC specifications

Parameter Description

A_RES_1 Resolution

Min

Typ Max Unit Details/conditions

SID.ADC12.DC.2

12

bits IMO/HFCLK at 48 MHz

Number of channels - single

SID.ADC12.DC.3 A_CHNLS_S

8

8 full speed

ended

Differential inputs use

adjacent I/O.

SID.ADC12.DC.4 A-CHNKS_D Number of channels - differential

SID.ADC12.DC.5 A-MONO Monotonicity

SID.ADC12.DC.6 A_GAINERR Gain error

4

–

Yes

±0.1

%

With external reference.

–

Measured with 1 V

reference.

SID.ADC12.DC.7

A_OFFSET Input offset voltage

2

1

mV

mA

SID.ADC12.DC.8

SID.ADC12.DC.9

SID.ADC12.DC.10

A_ISAR

A_VINS

A_VIND

Current consumption

Input voltage range - single ended

Input voltage range - differential

V

SS

DDD

–

SID.ADC12.DC.11 A_INRES Input resistance

SID.ADC12.DC.12 A_INCAP Input capacitance

2.2

10

kΩ

–

pF

Table 27

Spec ID

12-bit SAR ADC AC specifications

Parameter Description

Min

Typ

Max

Unit Details/conditions

SID.ADC12.AC.1

SID.ADC12.AC.2

A_PSRR

Power supply rejection ratio

70

66

–

dB

A_CMRR Common mode rejection ratio

Measured at 1 V.

Sample rate with external

A_SAMP_1

SID.ADC12.AC.3

SID.ADC12.AC.4

SID.ADC12.AC.5

SID.ADC12.AC.6

SID.ADC12.AC.7

SID.ADC12.AC.8

SID.ADC12.AC.9

SID.ADC12.AC.10

1

Msps

reference bypass cap.

Sample rate with no bypass cap.

A_SAMP_2

–

500

100

–

Reference = V

.

DD

Ksps

Sample rate with no bypass cap.

Internal reference.

A_SAMP_3

A_SNR

A_BW

Signal-to-noise and distortion

ratio (SINAD)

–

65

–

dB Fin = 10 kHz

Input bandwidth without

aliasing

A_samp/2 kHz

2

–

Integral non linearity.

DD

A_INL

-1.7

Vref = 1 to V

DD

V

= 1.71 to 5.5, 1 Msps

Integral non linearity.

= 1.71 to 3.6, 1 Msps

A_INL

LSB Vref = 1.71 to V

DD

V

DDD

-1.5

1.7

Integral non linearity.

= 1.71 to 5.5, 500 ksps

A_INL

Vref = 1 to V

DD

V

DD

Datasheet

31

002-35400 Rev. *D

2022-12-19

EZ-PD™ PMG1-B1 USB Type-C Buck-boost controller

Single-port

Electrical specifications

6.4.7

HS CSA

Table 28

HS CSA DC specifications

Spec ID

Parameter

Csa_Acc1

Csa_Acc2

Csa_Acc3

Csa_Acc4

Description

Min Typ Max Unit Details/conditions

SID.HSCSA.1

SID.HSCSA.2

SID.HSCSA.3

SID.HSCSA.4

CSA accuracy 5 mV < Vsense < 10 mV –15

15

10

5

CSA accuracy 10 mV < Vsense < 15 mV –10

CSA accuracy 15 mV < Vsense < 25 mV –5

CSA accuracy 25 mV < Vsense

–3

3

–

CSA SCP at 6A with 5-mΩ sense

SID.HSCSA.7

SID.HSCSA.8

SID.HSCSA.9

SID.HSCSA.10

Csa_SCP_Acc1

Csa_SCP_Acc2

Csa_OCP_1A

Csa_OCP_5A

resistor

%

Active mode

–10

10

CSA SCP at 10A with 5-mΩ sense

resistor

CSA OCP at 1A with 5-mΩ sense

104

123

156

137

resistor

130

CSA OCP for 5A with 5-mΩ sense

resistor

Table 29

Spec ID

HS CSA AC specifications

Parameter

Description

Min Typ Max Unit Details/conditions

Delay from SCP threshold trip to

external NFET power gate turn off

SID.HSCSA.AC.1

SID.HSCSA.AC.2

T

3.5

8

1 nF NFET gate

3 nF NFET gate

SCP_GATE

–

µs

Delay from SCP threshold trip to

external NFET power gate turn off

T

SCP_GATE_1

6.4.8

UV/OV

Table 30

UV/OV specifications

Spec ID

Parameter

Description

Min Typ Max Unit Details/conditions

Overvoltage threshold accuracy,

4 to 11 V

SID.UVOV.1

SID.UVOV.2

SID.UVOV.3

SID.UVOV.4

SID.UVOV.5

VTHOV1

–3

–3.2

–4

3

3.2

4

Overvoltage threshold accuracy,

11 to 21.5 V

VTHOV2

VTHUV1

VTHUV2

VTHUV3

Undervoltage threshold accuracy,

3 to 3.3 V

–

%

Active mode

Undervoltage threshold accuracy,

3.3 to 4.0 V

–3.5

–3

3.5

3

Undervoltage threshold accuracy,

4.0 to 21.5 V

Datasheet

32

002-35400 Rev. *D

2022-12-19

EZ-PD™ PMG1-B1 USB Type-C Buck-boost controller

Single-port

Electrical specifications

6.4.9

VCONN switch

Table 31

VCONN switch DC specifications

Spec ID

Parameter

Description

Min Typ Max Unit Details/conditions

VCONN output voltage with 20 mA

load current

DC.VCONN.1

DC.VCONN.2

DC.VCONN.3

VCONN_OUT

4.5

–

5.5

10

V

–

I

Connector side pin leakage current

µA

–

LEAK

VCONN overcurrent protection

threshold

I

22.5 30 42.5 mA

OCP

Table 32

VCONN switch AC specifications

Spec ID

Parameter

Description

Min Typ Max Unit Details/conditions

AC.VCONN.1

AC.VCONN.2

T

VCONN switch turn-on time

VCONN switch turn-off time

600

ON

–

µs

–

T

10

OFF

6.4.10

Table 33

Spec ID

V_BUS

V_BUSdischarge specifications

Parameter

Description

Min Typ Max Unit Details/conditions

20-V NMOS ON resistance for

DS = 1

SID.VBUS.DISC.1

SID.VBUS.DISC.2

SID.VBUS.DISC.3

SID.VBUS.DISC.4

SID.VBUS.DISC.5

R1

500

250

125

62.5

31.25

–

2000

1000

500

250

125

10

20-V NMOS ON resistance for

DS = 2

R2

R4

20-V NMOS ON resistance for

DS = 4



Measured at 0.5 V.

–

20-V NMOS ON resistance for

DS = 8

R8

20-V NMOS ON resistance for

DS = 16

R16

Error percentage of final VBUS

value from setting

When VBUS is discharged

to 5 V.

SID.VBUS.DISC.6 Vbus_stop_error

%

6.4.11

Voltage regulation

Table 34

Voltage regulation DC specifications

Spec ID

Parameter

Description

Min Typ Max Unit Details/conditions

SID.DC.VR.1

VOUT

CSNO output voltage range

3.3

–

21.5

V

CSNO voltage regulation

accuracy

SID.DC.VR.2

SID.DC.VR.3

VR

–

±3

±5

%

–

VIN supply below which chip

will get reset

VIN_UVLO

1.7

–

3.0

V

Table 35

Spec ID

Voltage regulator specifications

Parameter

Description

Min Typ Max Unit Details/conditions

200 µs

Total startup time for the

regulator supply outputs

SID.VREG.1

T

–

START

Datasheet

33

002-35400 Rev. *D

2022-12-19

EZ-PD™ PMG1-B1 USB Type-C Buck-boost controller

Single-port

Electrical specifications

6.4.12

Table 36

Spec ID

VBUS gate driver

VBUS gate driver DC specifications

Parameter

Description

Min Typ Max Unit Details/conditions

Gate to source overdrive during ON

condition

SID.GD.1

GD_VGS

4.5

5

10

V

NFET driver is ON

Applicable on

SID.GD.2

SID.GD.5

GD_RPD

GD_drv

Resistance when pull-down enabled

Programmable typical gate current

–

2

k VBUS_CTRL to turn

–

off external NFET.

0.3

9.75 µA

–

Table 37

Spec ID

VBUS gate driver AC specifications

Parameter

Description

Min Typ Max Unit Details/conditions

VBUS_CTRL low to high (1V to VBUS + 1 V)

with 3 nF external capacitance

SID.GD.3

SID.GD.4

T

2

–

5

7

10

–

ms CSNO = 5 V

ON

VBUS_CTRL high to low (90% to 10%)

with 3 nF external capacitance

T

µs CSNO = 21.5 V

OFF

6.4.13

PWM controller

Table 38

Buck-boost PWM controller specifications

Spec ID

Parameter

Description

Min Typ Max Unit Details/conditions

PWM.1

F

Switching frequency

150

–

600 kHz

SW

Spread spectrum frequency dithering

span

PWM.2

FSS

10

%

–

PWM.3

PWM.4

Ratio_buck_BB Buck to buck boost ratio

Ratio_boost_BB Boost to buck boost ratio

1.16

0.84

V/V

6.4.14

Table 39

Spec ID

NFET gate driver

Buck-boost NFET gate driver specifications

Parameter

Description

Min Typ Max Unit Details/conditions

Top-side gate driver on-resistance-gate

pull-up

DR.1

DR.2

DR.3

DR.4

R_HS_PU

2

Top-side gate driver on-resistance-gate

pull-down

R_HS_PD

R_LS_PU

R_LS_PD

1.5

Ω

Bottom-side gate driver on-resis-

tance-gate pull-up

2

Bottom-side gate driver on-resis-

tance-gate pull-down

1.5

–

DR.5

DR.6

DR.7

DR.8

DR.9

DR.10

Dead_HS

Dead_LS

Tr_HS

Dead time before high-side rising edge

Dead time before low-side rising edge

Top-side gate driver rise time

30

25

20

25

20

ns

Tf_HS

Top-side gate driver fall time

Tr_LS

Bottom-side gate driver rise time

Bottom-side gate driver fall time

Tf_LS

Datasheet

34

002-35400 Rev. *D

2022-12-19

EZ-PD™ PMG1-B1 USB Type-C Buck-boost controller

Single-port

Electrical specifications

6.4.15

Table 40

Spec ID

LS-SCP

LS-SCP DC specifications

Parameter Description

Min Typ Max Unit Details/conditions

Short circuit current detect

Using differential inputs

SID.LSSCP.DC.1

SCP_6A

5.4

4.5

9

6

6.6

7.5

11

@ 6A

(CSP_GPIO2, CSN_GPIO3)

Using single ended inputs

(CSP_GPIO2) and internal

ground

Short circuit current detect

@ 6A

SID.LSSCP.DC.1A SCP_6A_SE

6

A

Short circuit current detect

@10A

Using differential inputs

(CSP_GPIO2, CSN_GPIO3)

SID.LSSCP.DC.2

SCP_10A

10

Using single ended inputs

(CSP_GPIO2) and internal

ground

Short circuit current detect

@10A

SID.LSSCP.DC.2A SCP_10A_SE

7.5

10 12.5

6.4.16

Thermal

Table 41

Thermal specifications

Spec ID

Parameter Description

Min Typ Max Unit Details/conditions

120 125 130 °C

SID.OTP.1

OTP

Thermal shutdown

–

Datasheet

35

002-35400 Rev. *D

2022-12-19

EZ-PD™ PMG1-B1 USB Type-C Buck-boost controller

Single-port

Ordering information

7

Ordering information

Table 42 lists the EZ-PD™ PMG1-B1 part numbers and features.

Table 42

EZ-PD™ PMG1-B1 ordering information

Termination

Switching

frequency

MPN

Role

Package type

resistor

R R

CYPM1115-48LQXI

CYPM1116-48LQXI

P,

D

SinkandDRPpowersourcingwill

be supported

150 to 600 kHz

48-pin QFN

R R , R

D-DB

P,

D

7.1

Ordering code definition

The part numbers are of the form CYPM1ABC-DEFGHIJ where the fields are defined as follows.

Table 43

EZ-PD™ PMG1-B1 ordering code definitions

Field

CY

Description

Values

Meaning

CYPRESS prefix

Marketing code

MCU family generation

CY

PM

1

Company ID

PM

1

PM = Power Delivery MCU family

Product family generation

0

S0

1

S1, B1

S2

A

B

Family

2

3

S3

1

1-PD port

2-PD port

PD Ports

2

5

R R (no dead battery support)

P, D

C

Application specific

6

R R , R

(dead battery support)

D-DB

P,

D

DE

XX

LQ

BZ

FN

X

Number of pins in the package

QFN

FG

Package code

BGA

CSP

H

I

Lead free

Lead: X = Pb-free

Industrial

Tape and reel

Temperature range

Only for T&R

I

J

T

Datasheet

36

002-35400 Rev. *D

2022-12-19

EZ-PD™ PMG1-B1 USB Type-C Buck-boost controller

Single-port

Packaging

8

Packaging

Table 44

Parameter

Package characteristics

Description

Conditions

Min

Typ

Max

125

Unit

T

Operating junction temperature

-40

25

°C

J

Package 

–

18.81

10.1

JA

JC

JA

JC

–

°C/W

8.1

Package diagram

001-57280 *E

Figure 11

48-QFN package outline

Datasheet

37

002-35400 Rev. *D

2022-12-19

EZ-PD™ PMG1-B1 USB Type-C Buck-boost controller

Single-port

Acronyms

9

Acronyms

Table 45

Acronym

ADC

Acronyms used in this document

Description

analog-to-digital converter

Samsung adaptive fast charging

advanced RISC machine, a CPU architecture

central processing unit

AFC



Arm

CPU

CSA

current sense amplifier

DAC

digital-to-analog converter

forced continuous current/conduction mode

general-purpose input/output

high-side driver

FCCM

GPIO

HSDR

2

I C, or IIC

inter-integrated circuit, a communications protocol

current DAC

IDAC

I/O

input/output, see also GPIO

low-side driver

LSDR

MCU

OCP

OVP

microcontroller unit

overcurrent protection

overvoltage protection

PD

power delivery

POR

PSoC

PSM

PWM

RAM

SPI

power-on reset

programmable system-on-chip

pulse skipping mode

pulse-width modulator

random-access memory

serial peripheral interface, a communications protocol

static random access memory

timer/counter/PWM

SRAM

TCPWM

a new standard with a slimmer USB connector and a reversible cable, capable of sourcing up to 100 W of

power

Type-C

UART

UFP

UVP

USB

UVLO

VPA

universal asynchronous transmitter receiver, a communications protocol

upstream facing port

undervoltage protection

universal serial bus

under-voltage lockout

VCONN powered accessories

zero crossing detector

ZCD

Datasheet

38

002-35400 Rev. *D

2022-12-19

EZ-PD™ PMG1-B1 USB Type-C Buck-boost controller

Single-port

Document conventions

10

Document conventions

10.1

Units of measure

Table 46

Symbol

°C

Units of measure

Unit of measure

degrees Celsius

hertz

Hz

KB

1024 bytes

kHz

k

kilohertz

kilo ohm

Mbps

MHz

M

Msps

µA

megabits per second

megahertz

mega-ohm

megasamples per second

microampere

microfarad

µF

µs

microsecond

microvolt

µV

µW

mA

m

ms

microwatt

milliampere

milliohm

millisecond

millivolt

mV

nA

nanoampere

nanosecond

ohm

ns



pF

picofarad

ppm

ps

parts per million

picosecond

second

s

sps

samples per second

Datasheet

39

002-35400 Rev. *D

2022-12-19

EZ-PD™ PMG1-B1 USB Type-C Buck-boost controller

Single-port

Revision history

Document

Date

Description of changes

revision

*D

2022-12-19

Publish to web.

Datasheet

40

002-35400 Rev. *D

2022-12-19

Please read the Important Notice and Warnings at the end of this document

Trademarks

All referenced product or service names and trademarks are the property of their respective owners.

Please read the Important Notice and Warnings at the end of this document

IMPORTANT NOTICE

For further information on the product, technology,

delivery terms and conditions and prices please

contact your nearest Infineon Technologies office

(www.infineon.com).

Edition 2022-12-19

Published by

Infineon Technologies AG

81726 Munich, Germany

The information given in this document shall in no

event be regarded as a guarantee of conditions or

characteristics (“Beschaffenheitsgarantie”).

With respect to any examples, hints or any typical

values stated herein and/or any information

WARNINGS

regarding the application of the product, Infineon Due to technical requirements products may contain

Technologies hereby disclaims any and all dangerous substances. For information on the types

warranties and liabilities of any kind, including in question please contact your nearest Infineon

without limitation warranties of non-infringement of Technologies office.

intellectual property rights of any third party.

Except as otherwise explicitly approved by Infineon

In addition, any information given in this document Technologies in

is subject to customer’s compliance with its authorized

a written document signed by

Do you have a question about this

document?

Go to www.infineon.com/support

representatives

of

Infineon

obligations stated in this document and any Technologies, Infineon Technologies’ products may

applicable legal requirements, norms and standards not be used in any applications where a failure of the

concerning customer’s products and any use of the product or any consequences of the use thereof can

product of Infineon Technologies in customer’s reasonably be expected to result in personal injury.

applications.

Document reference

002-35400 Rev. *D

The data contained in this document is exclusively

intended for technically trained staff. It is the

responsibility of customer’s technical departments

to evaluate the suitability of the product for the

intended application and the completeness of the

product information given in this document with

respect to such application.


型号：	CYPM1115-48LQXIT
厂家：	Infineon
描述：	EZ-PD™ PMG1-B1 CYPM1115-48LQXIT因其Rp 和Rd 终端电阻和卷带包装而与众不同。它是EZ-PD™ PMG1-B1系列高度集成的单端口USB-C电力传输（PD）解决方案的一部分，集成了降压-升压控制器。控制器光电二极管
文件：	总41页 (文件大小：527K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

CYPM1115-48LQXIT [INFINEON]

相关型号：

SI9130DB

SI9135LG-T1

SI9135LG-T1-E3

SI9135_11

SI9136_11

SI9130CG-T1-E3

SI9130LG-T1-E3

SI9130_11

SI9137

SI9137DB

SI9137LG

SI9122E