CYT2B77CADQ0AZEGS [INFINEON]
TRAVEO™ T2G CYT2B7 Series;型号: | CYT2B77CADQ0AZEGS |
厂家: | Infineon |
描述: | TRAVEO™ T2G CYT2B7 Series |
文件: | 总162页 (文件大小:1424K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
CYT2B7
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4F single
General description
CYT2B7 is a family of TRAVEO™ T2G microcontrollers targeted at automotive systems such as body control units.
CYT2B7 has an Arm® Cortex®-M4 CPU for primary processing, and an Arm® Cortex®-M0+ CPU for peripheral and
security processing. These devices contain embedded peripherals supporting Controller Area Network with
Flexible Data rate (CAN FD), and Local Interconnect Network (LIN). TRAVEO™ T2G devices are manufactured on
an advanced 40-nm process. CYT2B7 incorporates a low-power flash memory, multiple high-performance analog
and digital peripherals, and enables the creation of a secure computing platform.
Features
• Dual CPU subsystem
- 160-MHz (max) 32-bit Arm® Cortex®-M4F CPU with
• Single-cycle multiply
• Single-precision floating point unit (FPU)
• Memory protection unit (MPU)
- 100-MHz (max) 32-bit Arm® Cortex® M0+ CPU with
• Single-cycle multiply
• Memory Protection Unit
- Inter-processor communication in hardware
- Three DMA controllers
• Peripheral DMA controller #0 (P-DMA0) with 89 channels
• Peripheral DMA controller #1 (P-DMA1) with 33 channels
• Memory DMA controller #0 (M-DMA0) with 4 channels
• Integrated memories
- 1088 KB of code-flash with an additional 96 KB of work-flash
• Read-While-Write (RWW) allows updating the code-flash/work-flash while executing from it
• Single- and dual-bank modes (specifically for Firmware update Over The Air [FOTA])
• Flash programming through SWD/JTAG interface
- 128 KB of SRAM with selectable retention granularity
• Crypto engine[1]
- Supports enhanced Secure Hardware Extension (eSHE) and Hardware Security Module (HSM)
- Secure boot and authentication
• Using digital signature verification
• Using fast secure boot
- AES: 128-bit blocks, 128-/192-/256-bit keys
- 3DES[2]: 64-bit blocks, 64-bit key
- Vector unit[2] supporting asymmetric key cryptography such as Rivest-Shamir-Adleman (RSA) and Elliptic
Curve (ECC)
- SHA-1/2/3[2]: SHA-512, SHA-256, SHA-160 with variable length input data
- CRC[2]: supports CCITT CRC16 and IEEE-802.3 CRC32
- True random number generator (TRNG) and pseudo random number generator (PRNG)
- Galois/Counter Mode (GCM)
• Functional safety for ASIL-B
- Memory protection unit (MPU)
- Shared memory protection unit (SMPU)
- Peripheral protection unit (PPU)
Notes
1. The Crypto engine features are available on select MPNs.
2. This feature is not available in “eSHE only” parts; for more information, refer to Ordering information.
Datasheet
www.infineon.com
Please read the Important Notice and Warnings at the end of this document
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4F single
Features
- Watchdog timer (WDT)
- Multi-counter watchdog timer (MCWDT)
- Low-voltage detector (LVD)
- Brown-out detector (BOD)
- Overvoltage detection (OVD)
- Clock supervisor (CSV)
- Hardware error correction (SECDED ECC) on all safety-critical memories (SRAM, flash)
• Low-power 2.7-v to 5.5-v operation
- Low-power Active, Sleep, Low-power Sleep, DeepSleep, and Hibernate modes for fine-grained power
management
- Configurable options for robust BOD
• Two threshold levels (2.7 V and 3.0 V) for BOD on VDDD and VDDA
• One threshold level (1.1 V) for BOD on VCCD
• Wakeup support
- Up to two pins to wakeup from Hibernate mode
- Up to 152 GPIO pins to wakeup from Sleep modes
- Event Generator, SCB, Watchdog Timer, RTC alarms to wake from DeepSleep modes
• Clock sources
- Internal main oscillator (IMO)
- Internal low-speed oscillator (ILO)
- External crystal oscillator (ECO)
- Watch crystal oscillator (WCO)
- Phase-locked loop (PLL)
- Frequency-locked loop (FLL)
• Communication interfaces
- Up to six CAN FD channels
• Increased data rate (up to 8 Mbps) compared to classic CAN, limited by physical layer topology and
transceivers
• Compliant to ISO 11898-1:2015
• Supports all the requirements of Bosch CAN FD Specification V1.0 for non-ISO CAN FD
• ISO 16845:2015 certificate available
- Up to eight runtime-reconfigurable SCB (serial communication block) channels, each configurable as I2C, SPI,
or UART
- Up to eight independent LIN channels
• LIN protocol compliant with ISO 17987
• Timers
- Up to 75 16-bit and four 32-bit timer/counter pulse-width modulator (TCPWM) blocks
• Up to 12 16-bit counters for motor control
• Up to 63 16-bit counters and four 32-bit counters for regular operations
• Supports timer, capture, quadrature decoding, pulse-width modulation (PWM), PWM with dead time (PW-
M_DT), pseudo-random PWM (PWM_PR), and shift-register (SR) modes
- Up to 11 Event Generation (EVTGEN) timers supporting cyclic wakeup from DeepSleep
• Events trigger a specific device operation (such as execution of an interrupt handler, a SAR ADC conversion,
and so on)
• Real time clock (RTC)
- Year/Month/Date, Day-of-week, Hour:Minute:Second fields
- 12- and 24-hour formats
- Automatic leap-year correction
Datasheet
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4F single
Features
• I/O
- Up to 152 Programmable I/Os
- Two I/O types
• GPIO Standard (GPIO_STD)
• GPIO Enhanced (GPIO_ENH)
• Regulators
- Generates 1.1-V nominal core supply from a 2.7-V to 5.5-V input supply
- Two types of regulators
• DeepSleep
• Core internal
• Programmable analog
- Three SAR A/D converters with up to 67 external channels (64 I/Os + 3 I/Os for motor control)
• ADC0 supports 24 logical channels, with 24 + 1 physical connections
• ADC1 supports 32 logical channels, with 32 + 1 physical connections
• ADC2 supports 8 logical channels, with 8 + 1 physical connections
• Any external channel can be connected to any logical channel in the respective SAR
- Each ADC supports 12-bit resolution and sampling rates of up to 1 Msps
- Each ADC also supports up to six internal analog inputs like
• Bandgap reference to establish absolute voltage levels
• Calibrated diode for junction temperature calculations
• Two AMUXBUS inputs and two direct connections to monitor supply levels
- Each ADC supports addressing of external multiplexers
- Each ADC has a sequencer supporting autonomous scanning of configured channels
- Synchronized sampling of all ADCs for motor-sense applications
• Smart I/O™
- Up to five Smart I/O blocks, which can perform Boolean operations on signals going to and from I/Os
- Up to 36 I/Os (GPIO_STD) supported
• Debug interface
- JTAG controller and interface compliant to IEEE-1149.1-2001
- Arm® SWD (Serial Wire Debug) port
- Supports Arm® Embedded Trace Macrocell (ETM) Trace
• Data trace using SWD
• Instruction and data trace using JTAG
• Compatible with industry-standard tools
- GHS/MULTI or IAR EWARM for code development and debugging
• Packages
- 64-LQFP, 10 × 10 × 1.7 mm (max), 0.5-mm lead pitch
- 80-LQFP, 12 × 12 × 1.7 mm (max). 0.5-mm lead pitch
- 100-LQFP, 14 × 14 × 1.7 mm (max), 0.5-mm lead pitch
- 144-LQFP, 20 × 20 × 1.7 mm (max), 0.5-mm lead pitch
- 176-LQFP, 24 × 24 × 1.7 mm (max), 0.5-mm lead pitch
Datasheet
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4F single
Table of contents
Table of contents
General description ...........................................................................................................................1
Features ...........................................................................................................................................1
Table of contents...............................................................................................................................4
1 Features list ...................................................................................................................................5
1.1 Communication peripheral instance list ...............................................................................................................6
2 Blocks and functionality..................................................................................................................7
Block diagram...................................................................................................................................7
3 Functional description ....................................................................................................................8
3.1 CPU subsystem .......................................................................................................................................................8
3.2 System resources....................................................................................................................................................9
3.3 Peripherals ............................................................................................................................................................11
3.4 I/Os.........................................................................................................................................................................14
4 CYT2B7 address map .....................................................................................................................16
5 Flash base address map.................................................................................................................17
6 Peripheral I/O map........................................................................................................................18
7 CYT2B7 clock diagram ...................................................................................................................20
8 CYT2B7 CPU start-up sequence ......................................................................................................21
9 Pin assignment .............................................................................................................................22
10 High-speed I/O matrix connections...............................................................................................32
11 Package pin list and alternate functions .......................................................................................33
12 Power pin assignments................................................................................................................39
13 Alternate function pin assignments ..............................................................................................40
14 Interrupts and wake-up assignments............................................................................................48
15 Core interrupt types....................................................................................................................57
16 Trigger multiplexer .....................................................................................................................58
17 Triggers group inputs ..................................................................................................................59
18 Triggers group outputs................................................................................................................62
19 Triggers one-to-one.....................................................................................................................63
20 Peripheral clocks ........................................................................................................................66
21 Faults.........................................................................................................................................69
22 Peripheral Protection Unit Fixed Structure Pairs ...........................................................................72
23 Bus masters................................................................................................................................83
24 Miscellaneous configuration ........................................................................................................84
25 Development support..................................................................................................................85
25.1 Documentation ...................................................................................................................................................85
25.2 Tools ....................................................................................................................................................................85
26 Electrical specifications...............................................................................................................86
26.1 Absolute maximum ratings ................................................................................................................................86
26.2 Device-level specifications .................................................................................................................................89
26.3 DC specifications.................................................................................................................................................90
26.4 Reset specifications ............................................................................................................................................94
26.5 I/O ........................................................................................................................................................................95
26.6 Analog peripherals............................................................................................................................................102
26.7 AC specifications...............................................................................................................................................107
26.8 Digital peripherals.............................................................................................................................................108
26.9 Memory..............................................................................................................................................................119
26.10 System resources............................................................................................................................................120
26.11 Debug ..............................................................................................................................................................129
26.12 Clock specifications ........................................................................................................................................131
27 Ordering information ................................................................................................................ 137
27.1 Part number nomenclature..............................................................................................................................138
Datasheet
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Table of contents
28 Packaging ................................................................................................................................ 139
29 Appendix.................................................................................................................................. 146
29.1 Bootloading or end-of-line programming .......................................................................................................146
29.2 External IP revisions..........................................................................................................................................147
30 Acronyms ................................................................................................................................. 148
31 Errata ...................................................................................................................................... 150
Revision history ............................................................................................................................ 159
Revision History Change Log....................................................................................................................................161
Datasheet
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4F single
Features list
1
Features list
Table 1-1
CYT2B7 feature list for all packages
Packages
100-LQFP
Features
64-LQFP
80-LQFP
144-LQFP
176-LQFP
CPU
Core
32-bit Arm® Cortex®-M4F CPU and 32-bit Arm® Cortex® M0+ CPU
Functional safety
Operating voltage
Core voltage
ASIL-B
2.7 V to 5.5 V
1.05 V to 1.15 V
Arm® Cortex®-M4 160 MHz (max) and Arm® Cortex®-M0+ 100 MHz (max),
related by integer frequency ratio (that is, 1:1, 1:2, 1:3, and so on)
Operating frequency
MPU, PPU
Supported
FPU
Single precision (32-bit)
DSP-MUL/DIV/MAC
Memory
Supported by Arm® Cortex®-M4F CPU
Code-flash
Work-flash
SRAM (configurable for retention)
ROM
1088 KB (960 KB + 128 KB)
96 KB (72 KB + 24 KB)
128 KB
32 KB
Communication Interfaces
CAN0 (CAN FD: Up to 8 Mbps)
CAN1 (CAN FD: Up to 8 Mbps)
CAN RAM
Serial communication block (SCB/UART)
Serial communication block (SCB/I2C)
Serial communication block (SCB/SPI)
LIN0
3 ch
2 ch
7 ch
3 ch
24 KB per instance (3 ch), 48 KB in total
8 ch
8 ch
6 ch
3 ch
6 ch
6 ch
8 ch
7 ch
8 ch
Timers
RTC
1 ch
12 ch
63 ch
4 ch
78
TCPWM (16-bit) (Motor Control)
TCPWM (16-bit)
TCPWM (32-bit)
External Interrupts
Analog
49
63
122
152
3 Units (SAR0/24, SAR1/32, SAR2/8 logical channels)
27 external 34 external 39 external
54 external 64 external
channels
channels
channels
channels
channels
12-bit, 1 Msps SAR ADC
(SAR0 11 ch, (SAR0 12 ch, (SAR0 14 ch, (SAR0 21 ch, (SAR0 24 ch,
SAR1 9 ch, SAR1 14 ch, SAR1 17 ch, SAR1 25 ch, SAR1 32 ch,
SAR2 7 ch) SAR2 8 ch)
SAR2 8 ch)
SAR2 8 ch)
SAR2 8 ch)
18 ch (6 per ADC) Internal sampling
Note
3. Enhanced Secure Hardware Extension (eSHE) and Hardware Security Module (HSM) support are enabled by third-party firmware.
Datasheet
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4F single
Features list
Table 1-1
CYT2B7 feature list for all packages (continued)
Features
Packages
100-LQFP
64-LQFP
80-LQFP
144-LQFP
176-LQFP
Motor Control Input
3 ch (synchronous sampling of one channel on each of the 3 ADCs)
Security
Flash Security (program/work read pro-
tection)
Supported
Flash Chip erase enable
eSHE/HSM
Configurable
By separate firmware[3]
System
P-DMA0 with 89 channels (16 general purpose), P-DMA1 with 33
channels (8 general purpose), and M-DMA0 with 4 channels
DMA Controller
Internal main oscillator
8 MHz
Internal low-speed oscillator
32.768 kHz (nominal)
Input frequency: 3.988 to 33.34 MHz, PLL output frequency: up to 160
MHz
Input frequency: 0.25 to 80 MHz, FLL output frequency: up to 100 MHz
PLL
FLL
Watchdog timer and multi-counter
watchdog timer
Supported
Clock supervisor
Cyclic wakeup from DeepSleep
GPIO_STD
Supported
Supported
45
59
74
118
148
GPIO_ENH
4
3 blocks,
9 I/Os
3 blocks,
14 I/Os
4 blocks,
20 I/Os
5 blocks,
29 I/Os
5 blocks,
36 I/Os
Smart I/O (Blocks)
Low-voltage detect
Maximum ambient temperature
Debug interface
Two, 26 selectable levels
105 °C for S-grade and 125 °C for E-grade
SWD/JTAG
Debug trace
Arm® Cortex®-M4 ETB size of 8 KB, Arm® Cortex® M0+ MTB size of 4 KB
1.1
Communication peripheral instance list
The following table lists the instances supported under each package for communication peripherals, based on
the minimum pins needed for the functionality.
Table 1-2
Module
Peripheral instance list
Minimum pin
functions
64-LQFP
80-LQFP
100-LQFP
144-LQFP
176-LQFP
CAN0
CAN1
LIN0
0/1/2
0/2
0/1/2/3/4/7
0/1/2
0/1/2
0/1/2/3/4/6/7
0/1/2
0/1/2
0/1/2/3/4/6/7
0/1/2
0/1/2
0/1/2
0/1/2
TX, RX
TX, RX
0/1/2/3/4/5/6/7 0/1/2/3/4/5/6/7 TX, RX
SCB/UART 0/1/2/3/4/5/7 0/1/2/3/4/5/6/7 0/1/2/3/4/5/6/7 0/1/2/3/4/5/6/7 0/1/2/3/4/5/6/7 TX, RX
SCB/I2C
SCB/SPI
0/2/3/4/5/7
0/3/4
0/1/3/4/5/7
0/1/3/4/5/7
0/1/2/3/4/5/6/7 0/1/2/3/4/5/6/7 0/1/2/3/4/5/6/7 SCL, SDA
0/1/2/3/4/5/6/7 0/1/2/3/4/5/6/7 0/1/2/3/4/5/6/7 MISO, MOSI, SCK,
SELECT0
Datasheet
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4F single
Blocks and functionality
2
Blocks and functionality
Block diagram
CPU Subsystem
CYT2B7
MXS40-HT
ASIL-B
SWJ/ETM/ITM/CTI
SWJ/MTB/CTI
CRYPTO
eCT FLASH
1088 KB Code-flash
+ 96 KB Work-flash
SRAM0
64 KB
SRAM1
64 KB
ROM
32 KB
Arm Cortex
M0+
100 MHz
AES, SHA, CRC,
TRNG, RSA,
ECC
Arm Cortex M4
160 MHz
8 KB $
Flash Controller
8 KB $
System Resources
SRAM Controller
SRAM Controller
Initiator/MMIO
ROM Controller
FPU, NVIC, MPU
MUL, NVIC, MPU
Power
Sleep Control
POR
OVD
BOD
LVD
System Interconnect (Multi Layer AHB, IPC, MPU/SMPU)
Peripheral Interconnect (MMIO,PPU)
REF
PWRSYS-HT
LDO
PCLK
Clock
Clock Control
Prog.
Analog
2xILO
IMO
WDT
ECO
CSV
FLL
SAR
ADC
(12-bit)
1xPLL
Reset
Reset Control
XRES
Test
TestMode Entry
x3
Digital DFT
Analog DFT
SARMUX
64 ch
WCO
RTC
Power Modes
Active/Sleep
LowePowerActive/Sleep
High Speed I/O Matrix, Smart I/O, Boundary Scan
5x Smart I/O
DeepSleep
Up to 148x GPIO_STD, 4x GPIO_ENH
Hibernate
I/O Subsystem
The Block diagram shows the CYT2B7 architecture, giving a simplified view of the interconnection between
subsystems and blocks. CYT2B7 has four major subsystems: CPU, system resources, peripherals, and I/O[4, 5]. The
color-coding shows the lowest power mode where the particular block is still functional.
CYT2B7 provides extensive support for programming, testing, debugging, and tracing of both hardware and
firmware.
Debug-on-chip functionality enables in-system debugging using the production device. It does not require
special interfaces, debugging pods, simulators, or emulators.
The JTAG interface is fully compatible with industry-standard third-party probes such as I-jet, J-Link, and GHS.
The debug circuits are enabled by default.
CYT2B7 provides a high level of security with robust flash protection and the ability to disable features such as
debug.
Additionally, each device interface can be permanently disabled for applications concerned with phishing
attacks from a maliciously reprogrammed device or attempts to defeat security by starting and interrupting flash
programming sequences. All programming, debug, and test interfaces are disabled when maximum device
security is enabled.
Notes
4. GPIO_STD supporting 2.7 V to 5.5 V VDDIO range.
5. GPIO_ENH supporting 2.7 V to 5.5 V VDDIO range with higher currents at lower voltages.
Datasheet
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4F single
Functional description
3
Functional description
CPU subsystem
CPU
3.1
3.1.1
The CYT2B7 CPU subsystem contains a 32-bit Arm® Cortex®-M0+ CPU with MPU, and a 32-bit Arm® Cortex®-M4F
CPU with MPU, and single-precision FPU. This subsystem also includes P-/M-DMA controllers, a cryptographic
accelerator, 1088 KB of code-flash, 96 KB of work-flash, 128 KB of SRAM, and 32 KB of ROM.
The Cortex®-M0+ CPU provides a secure, un-interruptible boot function. This guarantees that, following
completion of the boot function, system integrity is valid and privileges are enforced. Shared resources (flash,
SRAM, peripherals, and so on) can be accessed through bus arbitration, and exclusive accesses are supported by
an inter-processor communication (IPC) mechanism using hardware semaphores.
3.1.2
DMA controllers
CYT2B7 has three DMA controllers: P-DMA0 with 16 general-purpose and 73 dedicated channels, P-DMA1 with 8
general-purpose and 25 dedicated channels, and M-DMA0 with four channels. P-DMA is used for
peripheral-to-memory and memory-to-peripheral data transfers and provides low latency for a large number of
channels. Each P-DMA controller uses a single data-transfer engine that is shared by the associated channels.
General purpose channels have a rich interconnect matrix including P-DMA cross triggering which enables
demanding data-transfer scenarios. Dedicated channels have a single triggering input (such as an ADC channel)
to handle common transfer needs. M-DMA is used for memory-to-memory data transfers and provides high
memory bandwidth for a small number of channels. M-DMA uses a dedicated data-transfer engine for each
channel. They support independent accesses to peripherals using the AHB multi-layer bus.
3.1.3
Flash
CYT2B7 has 1088 KB (960 KB with a 32-KB sector size, and 128 KB with an 8-KB sector size) of code-flash with an
additional work-flash of up to 96 KB (72 KB with 2-KB sector size, and 24 KB with 128-B sectors size). Work-flash
is optimized for reprogramming many more times than code-flash. Code-flash supports Read-While-Write (RWW)
operation allowing flash to be updated while the CPU is active. Both the code-flash and work-flash areas support
dual-bank operation for over-the-air (OTA) programming.
3.1.4
SRAM
CYT2B7 has 128 KB of SRAM with two independent controllers. The first controller, SRAM0, provides DeepSleep
retention in 32-KB increments, while SRAM1 is selectable between fully retained and not retained.
3.1.5
ROM
CYT2B7 has 32-KB ROM that contains boot and configuration routines. This ROM enables secure boot and
authentication of user flash to guarantee a secure system.
3.1.6
Cryptography accelerator for security
The cryptography accelerator implements (3)DES block cipher, AES block cipher, SHA hash, cyclic redundancy
check, pseudo random number generation, true random number generation, galois/counter mode, and a vector
unit to support asymmetric key cryptography such as RSA and ECC.
Depending on the part number, this block is either completely or partially available or not available at all. See
Ordering information for more details.
Datasheet
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TRAVEO™ T2G 32-bit Automotive MCU
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Functional description
3.2
System resources
Power system
3.2.1
The power system ensures that the supply voltage levels meet the requirements of each power mode, and
provides a full-system reset when these levels are not valid. Internal power-on reset (POR) guarantees full-chip
reset during the initial power ramp.
Three Brown-Out Detection (BOD) circuits monitor the external supply voltages (VDDD, VDDA, VCCD). The BOD on
VDDD and VCCD are initially enabled and cannot be disabled. The BOD on VDDA is initially disabled and can be
enabled by the user. For the external supplies VDDD and VDDA, BOD circuits are software configurable with two
settings; a 2.7-V minimum voltage that is robust for all internal signaling and a 3.0-V minimum voltage, which is
also robust for all I/O specifications (which are guaranteed at 2.7 V). The BOD on VCCD is provided as a safety
measure and is not a robust detector.
Three overvoltage detection (OVD) circuits are provided for monitoring external supplies (VDDD, VDDA, VCCD), and
overcurrent detection circuits (OCD) for monitoring internal and external regulators. OVD thresholds on VDDD and
VDDA are configurable with two settings; a 5.0-V and 5.5-V maximum voltage. Two voltage-detection circuits are
provided to monitor the external supply voltage (VDDD) for falling and rising levels, each configurable for one of
the 26 selectable levels.
All BOD, OVD, and OCD circuits on VDDD and VCCD generate a reset, because these protect the CPUs and fault logic.
The BOD and OVD circuits on VDDA can be configured to generate either a reset, or a fault.
3.2.2
Regulators
CYT2B7 contains two regulators that provide power to the low-voltage core transistors: DeepSleep and core
internal. These regulators accept a 2.7–5.5-V VDDD supply and provide a low-noise 1.1-V supply to various parts
of the device. These regulators are automatically enabled and disabled by hardware and firmware when
switching between power modes. The core internal and core external regulators operate in active mode, and
provide power to the CPU subsystem and associated peripherals.
3.2.2.1
DeepSleep
The DeepSleep regulator is used to maintain power to a small number of blocks when in DeepSleep mode.
These blocks include the ILO and WDT timers, BOD detector, SCB0, SRAM memories, Smart I/O, and other
configuration memories. The DeepSleep regulator is enabled when in DeepSleep mode, and the core internal
regulator is disabled. It is disabled when XRES_L is asserted (LOW) and when the core internal regulator is
disabled.
3.2.2.2
Core internal
The core internal regulator supports load currents up to 150 mA, and is operational during the device start-up
(boot process), and in Active/Sleep modes.
3.2.3
Clock system
The CYT2B7 clock system provides clocks to all subsystems that require them, and glitch-free switching between
different clock sources. In addition, the clock system ensures that no metastable conditions occur.
The clock system for CYT2B7 consists of the 8-MHz IMO, two ILOs, three watchdog timers, a PLL, an FLL, five clock
supervisors (CSV), a 3.988- to 33.34 MHz ECO, and a 32.768-kHz WCO.
The clock system supports two main clock domains: CLK_HF, and CLK_LF.
• CLK_HFx are the Active mode clocks. Each can use any of the high frequency clock sources including IMO,
EXT_CLK, ECO, FLL, or PLL
• CLK_LF is a DeepSleep domain clock and provides a reference clock for the MCWDT or RTC modules. The
reference clock for the CLK_LF domain is either disabled or selectable from ILO0, ILO1, or WCO
Datasheet
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4F single
Functional description
Table 3-1
CLK_HF destinations
Name
CLK_HF0
CLK_HF1
Description
CPUSS clocks, PERI, and AHB infrastructure
Event Generator, also available in HSIOM as an output
3.2.3.3
IMO clock source
The IMO is the frequency reference in CYT2B7 when no external reference is available or enabled. The IMO
operates at a frequency of around 8 MHz.
3.2.3.4
ILO clock source
An ILO is a low-power oscillator, nominally 32.768 kHz, which generates clocks for a watchdog timer when in
DeepSleep mode. There are two ILOs to ensure clock supervisor (CSV) capability in DeepSleep mode. ILO-driven
counters can be calibrated to the IMO, WCO, or ECO to improve their accuracy. ILO1 is also used for clock super-
vision.
3.2.3.5
PLL and FLL
A PLL or FLL may be used to generate high-speed clocks from the IMO, the ECO, or EXT_CLK. The FLL provides a
much faster lock than the PLL (5 µs instead of 35 µs) in exchange for a small amount (±2%) of frequency error[6]
.
3.2.3.6
Clock supervisor (CSV)
Each CSV allows one clock (reference) to supervise the behavior of another clock (monitored). Each CSV has
counters for both the monitored and reference clocks. Parameters for each counter determine the frequency of
the reference clock as well as the upper and lower frequency limits of the monitored clock. If the frequency range
comparator detects a stopped clock or a clock outside the specified frequency range, an abnormal state is
signaled and either a reset or an interrupt is generated.
3.2.3.7
EXT_CLK
One of the two GPIO_STD I/Os can be used to provide an external clock input of up to 80 MHz. This clock can be
used as the source clock for either the PLL or FLL, or can be used directly by the CLK_HF domain.
3.2.3.8
ECO
The ECO provides high-frequency clocking using an external crystal connected to the ECO_IN and ECO_OUT pins.
It supports fundamental mode (non-overtone) quartz crystals, in the range of 3.988 to 33.34 MHz. When used in
conjunction with the PLL, it generates CPU and peripheral clocks up to device’s maximum frequency. ECO
accuracy depends on the selected crystal. If the ECO is disabled, the associated pins can be used for any of the
available I/O functions.
3.2.3.9
WCO
The WCO is a low-power, watch-crystal oscillator intended for real-time-clock applications. It requires an external
32.768-kHz crystal connected to the WCO_IN and WCO_OUT pins. The WCO can also be configured as a clock
reference for CLK_LF, which is the clock source for the MCWDT and RTC.
3.2.4
Reset
CYT2B7 can be reset from a variety of sources, including software. Reset events are asynchronous and guarantee
reversion to a known state. The reset cause (POR, BOD, OVD, overcurrent, XRES_L, WDT, MCWDT, software reset,
fault, CSV, Hibernate wakeup, debug) is recorded in a register, which is sticky through reset and allows software
to determine the cause of the reset. An XRES_L pin is available for external reset.
Note
6. Operation of reference-timed peripherals (like a UART) with an FLL-based reference is not recommended due the allowed frequency
error.
Datasheet
11
002-18043 Rev. *J
2022-09-08
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4F single
Functional description
3.2.5
Watchdog timers
CYT2B7 has one watchdog timer (WDT) and two multi-counter watchdog timers (MCWDT).
The WDT is a free-running counter clocked only by ILO0, which allows it to be used as a wakeup source from
Hibernate. Watchdog operation is possible during all power modes. To prevent a device reset from a WDT
timeout, the WDT must be serviced during a configured window. A watchdog reset is recorded in the reset cause
register.
An MCWDT is available for each of the CPU cores. These timers provide more capabilities than the WDT, and are
only available in Active, Sleep, and DeepSleep modes. These timers have multiple counters that can be used
separately or cascaded to trigger interrupts and/or resets. They are clocked from ILO0 or the WCO.
3.2.6
Power modes
CYT2B7 has the following six power modes:
• Active – all peripherals are available
• Low-Power Active (LPACTIVE) – Low-power profile of Active mode where all peripherals and the CPUs are
available, but with limited capability
• Sleep – all peripherals except the CPUs are available
• Low-Power Sleep (LPSLEEP) – Low-power profile of Sleep mode where all peripherals except the CPUs are
available, but with limited capability
• DeepSleep – only peripherals which work with CLK_LF are available
• Hibernate – the device and I/O states are frozen, the device resets on wakeup
3.3
Peripherals
3.3.1
Peripheral clock dividers
Integer and fractional clock dividers are provided for peripheral and timing purposes.
Table 3-1 Clock dividers
Divider
Count
32
16
Description
div_8
div_16
Integer divider, 8 bits
Integer divider, 16 bits
div_24_5
8
Fractional divider, 24.5 bits (24 integer bits, 5 fractional bits)
3.3.2
Peripheral protection unit
The Peripheral Protection Unit (PPU) controls and monitors unauthorized access from all masters (CPU,
P-/M-DMA, Crypto, and any enabled debug interface) to the peripherals. It allows or restricts data transfers on the
bus infrastructure. The access rules are enforced based on specific properties of a transfer, such as an address
range for the transfer and access attributes (such as read/write, user/privilege, and secure/non-secure).
Note
7. VREF_L prevents IR drops in the VSSIO and VSSA paths from impacting the measurements. VREF_L, when properly connected, reduces
or removes the impact of IR drops in the VSSIO and VSSA paths from measurements.
Datasheet
12
002-18043 Rev. *J
2022-09-08
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4F single
Functional description
3.3.3
12-bit SAR ADC
CYT2B7 contains three 1-Msps SAR ADCs. These ADCs can be clocked at up to 26.67 MHz and provide a 12-bit result
in 26 clock cycles.
The references for all three SAR ADCs come from a dedicated pair of inputs: VREFH and VREFL[7]
.
CYT2B7 devices support up to 85 logical ADC channels, and external inputs from up to 67 I/Os. Each ADC also
supports six internal connections for diagnostic and monitoring purposes. The number of ADC channels (per ADC
and package type) are listed in Table 1-1.
Each ADC has a sequencer, which autonomously cycles through the configured channels (sequencer scan) with
zero-switching overhead (that is, the aggregate sampling bandwidth, when clocked at 26.67 MHz, is equal to 1
Msps whether it is for a single channel or distributed over several channels). The sequencer switching is
controlled through a state machine or firmware. The sequencer prioritizes trigger requests, enables the
appropriate analog channel, controls ADC sampling, initiates ADC data conversion, manages results, and initiates
subsequent conversions for repetitive or group conversions without CPU intervention.
Each SAR ADC has an analog multiplexer used to connect the signals to be measured to the ADC. It has 32
GPIO_STD inputs, one special GPIO_STD input for motor-sense, and six additional inputs to measure internal
signals such as a band-gap reference, a temperature sensor, and power supplies. The device supports
synchronous sampling of one motor-sense channel on each of the three ADCs.
CYT2B7 has one temperature sensor that is shared by all three ADCs. The temperature sensor must only be
sampled by one ADC at a time. Software post processing is required to convert the temperature sensor reading
into kelvin or Celsius values.
To accommodate signals with varying source impedances and frequencies, it is possible to have different sample
times programmed for each channel. Each ADC also supports range comparison, which allows fast detection of
out-of-range values without having to wait for a sequencer scan to complete and for the CPU firmware to evaluate
the measurement for out-of-range values.
The ADCs are not usable in DeepSleep and Hibernate modes as they require a high-speed clock. The ADC input
reference voltage VREFH range is 2.7 V to VDDA and VREFL is VSSA
.
3.3.4
Timer/counter/PWM block (TCPWM)
The TCPWM block consists of 16-bit (75 channels) and 32-bit (four channels) counters with a user-programmable
period. Twelve of the 16-bit counters include extra features to support motor control operations. Each TCPWM
counter contains a capture register to record the count at the time of an event, a period register (used to either
stop or auto-reload the counter when its count is equal to the period register), and compare registers to generate
signals that are used as PWM duty-cycle outputs.
Each counter within the TCPWM block supports several functional modes such as timer, capture, quadrature,
PWM, PWM with dead-time insertion (PWM_DT, 8-bit), pseudo-random PWM (PWM_PR), and shift-register.
In motor-control applications, the counter within the TCPWM block supports enhanced quadrature mode with
features such as asymmetric PWM generation, dead-time insertion (16-bit), and association of different dead
times for PWM output signals.
The TCPWM block also provides true and complement outputs, with programmable offset between them, to
allow their use as deadband complementary PWM outputs. The TCPWM block also has a kill input (only for the
PWM mode) to force outputs to a predetermined state; for example, this may be used in motor-drive systems
when an overcurrent state is detected and the PWMs driving the FETs need to be shut off immediately (no time
for software intervention).
Datasheet
13
002-18043 Rev. *J
2022-09-08
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4F single
Functional description
3.3.5
Serial communication blocks (SCB)
CYT2B7 contains eight serial communication blocks, each configurable to support I2C, UART, or SPI.
3.3.5.10
I2C interface
An SCB can be configured to implement a full I2C master (capable of multi-master arbitration) or slave
interface. Each SCB configured for I2C can operate at speeds of up to 1 Mbps (Fast-mode Plus[8]) and has
flexible buffering options to reduce the interrupt overhead and latency of the CPU. In addition, each SCB
supports FIFO buffering for receive and transmit data, which, by increasing the time for the CPU to read the
data, reduces the need for clock stretching. The I2C interface is compatible with Standard, Fast-mode, and
Fast-mode Plus devices as specified in the NXP I2C-bus specification and user manual (UM10204). The I2C-bus
I/O is implemented with GPIO in open-drain modes[9, 10]
.
3.3.5.11
UART interface
When configured as a UART, each SCB provides a full-featured UART with maximum signaling rate determined
by the configured peripheral-clock frequency and over-sampling rate. It supports infrared interface (IrDA) and
SmartCard (ISO 7816) protocols, which are minor variants of the UART protocol. It also supports the 9-bit
multiprocessor mode that allows the addressing of peripherals connected over common Rx and Tx lines.
Common UART functions such as parity, number of stop bits, break detect, and frame error are supported.
FIFO buffering of transmit and receive data allows greater CPU service latencies to be tolerated.
The LIN protocol is supported by the UART. LIN is based on a single-master multi-slave topology. There is one
master node and multiple slave nodes on the LIN bus. The SCB UART supports only LIN slave functionality.
Compared to the dedicated LIN blocks, an SCB/UART used for LIN requires a higher level of software
interaction and increased CPU load.
3.3.5.12
SPI interface
The SPI configuration supports full Motorola SPI, TI Synchronous Serial Protocol (SSP, essentially adds a start
pulse that is used to synchronize SPI-based codecs), and National Microwire (a half-duplex form of SPI). The
SPI interface can use the FIFO. The SPI interface operates with up to a 12.5-MHz SPI Clock. SCB also supports
EZSPI[11] mode.
SCB0 supports the following additional features:
• Operable as a slave in DeepSleep mode
• I2C slave EZ (EZI2C[12]) mode with up to 256-B data buffer for multi-byte communication without CPU
intervention
• I2C slave externally-clocked operations
• Command/response mode with a 512-B data buffer for multi-byte communication without CPU intervention
3.3.6
CAN FD
CYT2B7 supports two CAN FD controller blocks, each supporting three CAN FD channels. All CAN FD controllers
are compliant with the ISO 11898-1:2015 standard; an ISO 16845:2015 certificate is available. It also implements
the time-triggered CAN (TTCAN) protocol specified in ISO 11898-4 (TTCAN protocol levels 1 and 2) completely in
hardware.
All functions concerning the handling of messages are implemented by the Rx and Tx handlers. The Rx handler
manages message acceptance filtering, transfer of received messages from the CAN core to a message RAM, and
provides receive-message status. The Tx handler is responsible for the transfer of transmit messages from the
message RAM, to the CAN core, and provides transmit-message status.
Notes
8. I/Os drive level does not support the full bus capacitance in Fast-mode Plus speeds.
9. This is not 100% compliant with the I2C-bus specification; I/Os are not over-voltage tolerant, do not support the 20-mA sink
requirement of Fast-mode Plus, and violate the leakage specification when no power is applied.
10.Only Port 0 with the slew rate control enabled meets the minimum fall time requirement.
11.The Easy SPI (EZSPI) protocol is based on the Motorola SPI operating in any mode (0, 1, 2, or 3). It allows communication between
master and slave reduces the need for CPU intervention.
12.The Easy I2C (EZI2C) protocol is a unique communication scheme built on top of the I2C protocol by Infineon. It uses a meta protocol
around the standard I2C protocol to communicate to an I2C slave using indexed memory transfers. This reduces the need for CPU
intervention.
Datasheet
14
002-18043 Rev. *J
2022-09-08
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4F single
Functional description
3.3.7
Local interconnect network (LIN)
CYT2B7 contains up to eight LIN channels. Each channel supports transmission/reception of data following the
LIN protocol according to ISO standard 17987. Each LIN channel connects to an external transceiver through a
3-pin interface (including an enable function) and supports master and slave functionality. Each channel also
supports classic and enhanced checksum, along with break detection during message reception and wake-up
signaling. Break detection, sync field, checksum calculations, and error interrupts are handled in hardware.
3.3.8
One-time-programmable (OTP) eFuse
CYT2B7 contains a 1024-bit OTP eFuse memory that can be used to store and access a unique and unalterable
identifier or serial number for each device. eFuses are also used to control the device life-cycle (manufacturing,
programming, normal operation, end-of-life, and so on) and the security state. Of the 1024 bits, 192 are available
for user purposes.
3.3.9
Event generator
The event generator supports generation of interrupts and triggers in Active mode and interrupts in DeepSleep
mode. The event generators are used to trigger a specific device operation (execution of an interrupt handler, a
SAR ADC conversion, and so on) and to provide a cyclic wakeup mechanism from DeepSleep mode. They provide
CPU-free triggers for device functions, and reduce CPU involvement in triggering device functions, thus reducing
overall power consumption and processing overhead.
3.3.10
Trigger multiplexer
CYT2B7 supports connecting various peripherals using trigger signals. Triggers are used to inform a peripheral of
the occurrence of an event or change of state. These triggers are used to affect or initiate some action in other
peripherals. The trigger multiplexer is used to route triggers from a source peripheral to a destination. Triggers
provide active logic functionality and are typically supported in Active mode.
3.4
I/Os
CYT2B7 has up to 152 programmable I/Os.
The I/Os are organized as logical entities called ports, which are a maximum of 8 bits wide. During power-on, and
reset, the I/Os are forced to the High-Z state. During the Hibernate mode, I/Os are frozen.
Every I/O can generate an interrupt (if enabled) and each port has an interrupt request (IRQ) and interrupt service
routine (ISR) associated with it.
I/O port power source mapping is listed in Table 3-1. The associated supply determines the VOH, VOL, VIH, and VIL
levels when configured for CMOS and Automotive thresholds.
Table 3-1
I/O port power source
Supply
Ports
VDDD
P0, P1, P2, P3, P4, P5, P16, P17, P18, P19, P20, P21, P22, P23
VDDIO_1
VDDIO_2
P6, P7, P8, P9[13]
P10, P11, P12, P13, P14, P15
Note
13.The I/Os in VDDIO_1 domain are referred to the VDDD domain in 64-LQFP package.
Datasheet
15
002-18043 Rev. *J
2022-09-08
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4F single
Functional description
3.4.1
Port nomenclature
Px.y describes a particular bit “y” available within an I/O port “x.”
For example, P4.2 reads “port 4, bit 2”.
Each I/O implements the following:
• Programmable drive mode
- High impedance
- Resistive pull-up
- Resistive pull-down
- Open drain with strong pull-down
- Open drain with strong pull-up
- Strong pull-up or pull-down
- Weak pull-up or pull-down
CYT2B7 has two types of programmable I/Os: GPIO standard and GPIO Enhanced.
• GPIO Standard (GPIO_STD)
Supports standard automotive signaling across the 2.7-V to 5.5-V VDDIO range. GPIO Standard I/Os have multi-
ple configurable drive levels, drive modes, and selectable input levels.
• GPIO Enhanced (GPIO_ENH)
Supports extended functionality automotive signaling across the 2.7-V to 5.5-V VDDIO range with higher cur-
rents at lower voltages (full I2C timing support, slew-rate control).
Both GPIO_STD and GPIO_ENH implement the following:
• Configurable input threshold (CMOS, TTL, or Automotive)
• Hold mode for latching previous state (used for retaining the I/O state in DeepSleep mode)
• Analog input mode (input and output buffers disabled)
3.4.2
Smart I/O
Smart I/O allows Boolean operations on signals going to the I/O from the subsystems of the chip or on signals
coming into the chip. CYT2B7 has five Smart I/O blocks. Operation can be synchronous or asynchronous and the
blocks operate in all device power modes except for the Hibernate mode.
Datasheet
16
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2022-09-08
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4F single
CYT2B7 address map
4
CYT2B7 address map
The CYT2B7 microcontroller supports the memory spaces shown in Figure 4-1.
• 1088KB (960KB + 128KB) of code-flash, used in the single- or dual-bank mode based on the associated bit in the
flash control register
- Single-bank mode - 1088KB
- Dual-bank mode - 544KB per bank
• 96KB (72KB + 24KB) of work-flash, used in the single- or dual-bank mode based on the associated bit in the flash
control register
- Single-bank mode - 96KB
- Dual-bank mode - 48KB per bank
• 32KB of secure ROM
• 128KB of SRAM (First 2 KB is reserved for internal usage)
0xFFFF FFFF
Arm System
Space
CPU & Debug Registers
0xE000 0000
0x43FF FFFF
Reserved
Peripheral
Interconnect or
Memory map
Mainly used for on-chip peripherals
e.g., AHB or APB Peripherals
0x4000 0000
Reserved
32 KB
Reserved
32 KB
Used to store manufacture specific
data like flash protection settings, trim
settings, device addresses, serial numbers,
calibration data, etc.
Alternate Flash
Supervisory Region
0x1780 7FFF
0x1780 0000
Flash Supervisory
Region
0x1700 7FFF
0x1700 0000
Reserved
0x1401 7FFF
24 KB
(128 B Small Sectors)
Work flash used for long
term data retention
0x1401 2000
0x1401 1FFF
Work flash
72 KB
(2 KB Large Sectors)
0x1400 0000
0x1010 FFFF
Reserved
128 KB
(8 KB Small Sectors)
0x100F 0000
0x100E FFFF
Mainly used for user program code
Code flash
960 KB
(32 KB Large Sectors)
0x1000 0000
0x0801 FFFF
Reserved
64 KB
General purpose RAM,
mainly used for data
SRAM1
SRAM0
0x0801 0000
0x0800 FFFF
62 KB
2 KB
0x0800 0800
0x0800 0000
Secured Boot ROM to set user specified
protection levels, trim and configuration
data, code authentication, jump to user mode etc.
Reserved
0x0000 7FFF
0x0000 0000
32 KB
ROM
Figure 4-1
CYT2B7 address map[14, 15]
Notes
14.The size representation is not up to scale.
15.First 2 KB of SRAM is reserved, not available for users. User must keep the power of first 32KB block of SRAM0 in enabled or retained
in all Active, LP Active, Sleep, LP Sleep, DeepSleep modes.
Datasheet
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2022-09-08
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4F single
Flash base address map
5
Flash base address map
Table 5-1 through Table 5-6 give information about the sector mapping of the code- and work-flash regions
along with their respective base addresses.
Table 5-1
Code-flash Address Mapping in Single Bank Mode
Large Sectors
(LS)
Small Sectors
(SS)
Code-flash Size (KB)
Large Sector Base Address
Small Sector Base Address
1088
32KB × 30
8KB × 16
0x1000 0000
0x100F 0000
Table 5-2
Work-flash Address Mapping in Single Bank Mode
Work-flash Size (KB) Large Sectors
Small Sectors
128 B × 192
Large Sector Base Address Small Sector Base Address
0x1400 0000 0x1401 2000
96
2KB × 36
Table 5-3
Code-flash Address Mapping in Dual Bank Mode (Mapping A)
First Half
LS Base
Address
First Half SecondHalf SecondHalf
Code-flash
Size (KB)
First
First
Second
Half LS
Second
Half SS
SS Base
Address
LS Base
Address
SS Base
Address
Half LS
Half SS
1088
32KB × 15
8KB × 8
32KB × 15
8KB × 8
0x1000 0000 0x1007 8000 0x1200 0000 0x1207 8000
Table 5-4
Code-flash Address Mapping in Dual Bank Mode (Mapping B)
Second
Half
Second
Half SS
Base
First Half
LS Base
Address
First Half
Code-flash
Size (KB)
First
First
Second
Half LS
Second
Half SS
SS Base
Address
Half LS
Half SS
LS Base
Address
Address
1088
32KB × 15
8KB × 8
32KB × 15
8KB × 8
0x1200 0000 0x1207 8000 0x1000 0000 0x1007 8000
Table 5-5
Work-flash Address Mapping in Dual Bank Mode (Mapping A)
Second
Half
Second
Half SS
Base
First Half
LS Base
Address
First Half
Work-flash
Size (KB)
First
First
Second
Half LS
Second
Half SS
SS Base
Address
Half LS
Half SS
LS Base
Address
Address
96
2KB × 18
128 B × 96
2KB × 18
128 B × 96 0x1400 0000 0x1400 9000 0x1500 0000 0x1500 9000
Table 5-6
Work-flash Address Mapping in Dual Bank Mode (Mapping B)
Second
Half
Second
Half SS
Base
First Half
LS Base
Address
First Half
Work-flash
Size (KB)
First
First
Second
Half LS
Second
Half SS
SS Base
Address
Half LS
Half SS
LS Base
Address
Address
96
2KB × 18
128 B × 96
2KB × 18
128 B × 96 0x1500 0000 0x1500 9000 0x1400 0000 0x1400 9000
Datasheet
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4F single
Peripheral I/O map
6
Peripheral I/O map
CYT2B7 peripheral I/O map
Table 6-1
Section
Description
Peripheral interconnect
Base Address Instances Instance Size Group Slave
0x4000 0000
Peripheral group (0, 1, 2, 3, 5, 6, 9)
Peripheral trigger group
Peripheral 1:1 trigger group
0x4000 4000
0x4000 8000
0x4000 C000
7
11
11
0x20
0x400
0x400
PERI
0
0
Peripheral interconnect, master
interface
PERI Programmable PPU
PERI Fixed PPU
Cryptography component
CPU subsystem (CPUSS)
Fault structure subsystem
Fault structures
Inter process communication
IPC structures
0x4001 0000
PERI_MS
0
1
0x4001 0000
0x4001 0800
0x4010 0000
0x4020 0000
0x4021 0000
0x4021 0000
0x4022 0000
0x4022 0000
0x4022 1000
0x4023 0000
6[16]
458
0x40
0x40
Crypto
CPUSS
1
2
0
0
FAULT
2
1
4
0x100
IPC
8
8
0x20
0x20
2
2
IPC interrupt structures
Protection
Shared memory protection unit struc-
tures
Memory protection unit structures
Flash controller
PROT
0x4023 2000
16
16
0x40
2
2
3
4
0x4023 4000
0x4024 0000
0x400
FLASHC
System Resources Subsystem Core
Registers
Clock Supervision High Frequency
Clock Supervision Reference
Frequency
Clock Supervision Low Frequency
0x4026 0000
0x4026 1400
0x4026 1710
0x4026 1720
0x4026 1730
3
1
1
1
0x10
SRSS
2
5
Clock Supervision Internal Low
Frequency
Multi Counter WDT
Free Running WDT
SRSS Backup Domain/RTC
Backup Register
P-DMA0 Controller
P-DMA0 channel structures
P-DMA1 Controller
P-DMA1 channel structures
M-DMA0 Controller
M-DMA0 channels
eFUSE Customer Data (192 bits)
0x4026 8000
0x4026 C000
0x4027 0000
0x4027 1000
0x4028 0000
0x4028 8000
0x4029 0000
0x4029 8000
0x402A 0000
0x402A 1000
0x402C 0868
2
1
0x100
BACKUP
P-DMA
2
2
2
6
7
8
4
0x04
0x40
0x40
89
33
M-DMA
2
2
9
4
6
0x100
0x04
eFUSE
10
Note
16.These six Programmable PPUs are configured by the Boot ROM and are available for the user based on the access rights. Refer to the
device specific TRM to know more about the configuration of these programmable PPUs.
Datasheet
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4F single
Peripheral I/O map
Table 6-1
CYT2B7 peripheral I/O map (continued)
Section
HSIOM
GPIO
Description
Base Address Instances Instance Size Group Slave
High-Speed I/O Matrix (HSIOM)
GPIO port control/configuration
Programmable I/O configuration
SMARTIO port configuration
Timer/Counter/PWM 0 (TCPWM0)
TCPWM0 Group #0 (16-bit)
TCPWM0 Group #1 (16-bit, Motor
control)
TCPWM0 Group #2 (32-bit)
Event generator 0 (EVTGEN0)
0x4030 0000
0x4031 0000
0x4032 0000
0x4032 0C00
0x4038 0000
0x4038 0000
24
24
0x10
0x80
3
3
0
1
SMARTIO
3
2
5
0x100
63
12
4
0x80
0x80
0x80
TCPWM
3
3
0x4038 8000
0x4039 0000
0x403F 0000
EVTGEN
LIN
3
4
Event generator 0 comparator struc-
tures
Local Interconnect Network 0 (LIN0)
LIN0 Channels
CAN0 controller
Message RAM CAN0
CAN1 controller
0x403F 0800
11
0x20
0x4050 0000
0x4050 8000
0x4052 0000
0x4053 0000
0x4054 0000
0x4055 0000
5
5
0
1
8
3
0x100
0x200
0x5FFF
0x200
TTCANFD
SCB
3
8
5
6
2
Message RAM CAN1
0x5FFF
Serial Communications Block
0x4060 0000
0x4090 0000
0x10000
0-7
(SPI/UART/I2C)
Programmable Analog Subsystem
(PASS0)
SAR0 channel controller
SAR1 channel controller
SAR2 channel controller
SAR0 channel structures
SAR1 channel structures
SAR2 channel structures
0x4090 0000
0x4090 1000
0x4090 2000
0x4090 0800
0x4090 1800
0x4090 2800
PASS0 SAR
9
0
24
32
8
0x40
0x40
0x40
Datasheet
20
002-18043 Rev. *J
2022-09-08
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4F single
CYT2B7 clock diagram
7
CYT2B7 clock diagram
IMO
EXT_CLK
ECO
WCO
ILO0
ILO1
LEGEND 1:
LEGEND 2:
ECO
LS
LS
LS
Active Domain
Prescaler
DeepSleep Domain
Hibernate Domain
LS
MUX
LS
MUX
MUX
MUX
MUX
MUX
MUX
FLL
MUX
PLL
MUX
MUX
Relationship of Monitored Clock
and Reference Clock
CLK_ILO0
WDT
RTC
MUX
CLK_BAK
Monitored Clock
CSV
CLK_
PATH0
CLK_
PATH1
CLK_
PATH2
CLK_
PATH3
CLK_REF_HF
CLK_LF
Reference Clock
CLK_ILO0
CSV
MCWDT
LEGEND 3:
MUX
MUX
MUX
One Clock Line
Multiple Clock Lines
Predivider
(1/2/4/8)
Predivider
(1/2/4/8)
Predivider
(1/2/4/8)
CSV
CSV
CLK_ILO0
CLK_LF
CLK_HF2
CSV
CSV
CSV
CLK_REF_HF
Event Generator
CLK_HF1
CLK_HF0
ROM/SRAM/FLASH
Divider
(1-256)
Divider
(1-256)
CM4
CLK_FAST
CLK_PERI
CPUSS Fast Infrastructure
Divider
(1-256)
CM0+
CLK_SLOW
CPUSS Slow Infrastructure
P-DMA / M-DMA
CRYPTO
PERI
SRSS
Divider
(1-256)
EFUSE
CLK_GR3
CLK_GR5
CPUSS(Trace Clock)
TCK/SWDCLK from a Debugger
Divider
(1-256)
IOSS
TCPWM
CAN FD
LIN
Divider
(1-256)
CLK_GR6
CLK_GR9
SCB[*]
SCB[0]
Serial interface clock
Divider
(1-256)
SAR ADC
Peripheral
Clock Dividers
PCLK_CPUSS_CLOCK_TRACE_IN
PCLK_SMARTIO[x]_CLOCK
PCLK_TCPWM[x]_CLOCKS[y]
PCLK_CANFD[x]_CLOCK_CAN[y]
PCLK_LIN_CLOCK_CH_EN[x]
PCLK_SCB[x]_CLOCK
PCLK_PASS_CLOCK_SAR[x]
Figure 7-1
CYT2B7 clock diagram
Datasheet
21
002-18043 Rev. *J
2022-09-08
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4F single
CYT2B7 CPU start-up sequence
8
CYT2B7 CPU start-up sequence
The start-up sequence is described in the following steps:
1. System Reset (@0x0000 0000)
2.CM0+ executes ROM boot (@0x0000 0004)
i. Applies trims
ii. Applies Debug Access port (DAP) access restrictions and system protection from eFuse and supervisory
flash
iii.Authenticates flash boot (only in SECURE life-cycle stage) and transfers control to it
3.CM0+ executes flash boot (from Supervisory flash @0x1700 2000)
i. Debug pins are configured as per the SWD/JTAG spec[17]
ii. Sets CM0+ vector offset register (CM0_VTOR part of the Arm® system space) to the beginning of flash
(@0x1000 0000)
iii.CM0+ branches to its Reset handler
4.CM0+ starts execution
i. Moves CM0+ vector table to SRAM (updates CM0+ vector table base)
ii. Sets CM4_VECTOR_TABLE_BASE (@0x0000 0200) to the location of CM4 vector table mentioned in flash
(specified in CM4 linker definition file)
iii.Releases CM4 from reset
iv.Continues execution of CM0+ user application
5.CM4 executes directly from either code-flash or SRAM
i. CM4 branches to its Reset handler
ii. Continues execution of CM4 user application
Note
17.Port configuration of SWD/JTAG pins will be changed from the default GPIO mode to support debugging after the boot process, refer
to Table 11-1 for pin assignments.
Datasheet
22
002-18043 Rev. *J
2022-09-08
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4F single
Pin assignment
9
Pin assignment
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
VDDD
P18.7
P18.6
P18.5
P18.4
P18.3
P18.2
P18.1
P18.0
P17.7
P17.6
P17.5
P17.4
P17.3
P17.2
P17.1
P17.0
P16.3
P16.2
P16.1
P16.0
VSSD
VDDD
P15.3
P15.2
P15.1
P15.0
P14.7
P14.6
P14.5
P14.4
P14.3
P14.2
P14.1
P14.0
P13.7
P13.6
P13.5
P13.4
P13.3
P13.2
P13.1
P13.0
VSSD
VSSD
P0.0
P0.1
P0.2
P0.3
P1.0
P1.1
P1.2
P1.3
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
VDDD
VSSD
P4.0
P4.1
P4.2
P4.3
P4.4
P5.0
P5.1
P5.2
P5.3
P5.4
P5.5
P6.0
P6.1
P6.2
P6.3
P6.4
P6.5
P6.6
P6.7
VDDD
VDDIO_1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
176-LQFP
98
97
96
95
94
93
92
91
90
89
Figure 9-1
176-LQFP pin assignment
Datasheet
23
002-18043 Rev. *J
2022-09-08
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4F single
Pin assignment
VSSD
PWM0_18/PWM0_22_N/TC0_18_TR0/TC0_22_TR1/SCB0_RX (0)/SCB7_SDA (2)/SCB0_MISO (0)/LIN1_RX P0.0
PWM0_17/PWM0_18_N/TC0_17_TR0/TC0_18_TR1/SCB0_TX (0)/SCB7_SCL (2)/SCB0_MOSI (0)/LIN1_TX P0.1
PWM0_14/PWM0_17_N/TC0_14_TR0/TC0_17_TR1/SCB0_RTS (0)/SCB0_SCL (0)/SCB0_CLK (0)/LIN1_EN/CAN0_1_TX P0.2
PWM0_13/PWM0_14_N/TC0_13_TR0/TC0_14_TR1/SCB0_CTS (0)/SCB0_SDA (0)/SCB0_SEL0 (0)/CAN0_1_RX P0.3
PWM0_12/PWM0_13_N/TC0_12_TR0/TC0_13_TR1/SCB0_SCL (1)/SCB0_MISO (1) P1.0
PWM0_11/PWM0_12_N/TC0_11_TR0/TC0_12_TR1/SCB0_SDA (1)/SCB0_MOSI (1) P1.1
PWM0_10/PWM0_11_N/TC0_10_TR0/TC0_11_TR1/SCB0_CLK (1)/TRIG_IN[0] P1.2
1
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
VDDD
2
P18.7 PWM0_50/PWM0_51_N/TC0_50_TR0/TC0_51_TR1/PWM0_H_3_N/CAN1_2_RX/TRACE_DATA_3 (0)/ADC[2]_7
P18.6 PWM0_51/PWM0_52_N/TC0_51_TR0/TC0_52_TR1/PWM0_H_3/SCB1_SEL3 (0)/CAN1_2_TX/TRACE_DATA_2 (0)/ADC[2]_6
P18.5 PWM0_52/PWM0_53_N/TC0_52_TR0/TC0_53_TR1/PWM0_H_2_N/SCB1_SEL2 (0)/TRACE_DATA_1 (0)/ADC[2]_5
P18.4 PWM0_53/PWM0_54_N/TC0_53_TR0/TC0_54_TR1/PWM0_H_2/SCB1_SEL1 (0)/TRACE_DATA_0 (0)/ADC[2]_4
P18.3 PWM0_54/PWM0_55_N/TC0_54_TR0/TC0_55_TR1/PWM0_H_1_N/SCB1_CTS (0)/SCB1_SEL0 (0)/TRACE_CLOCK (0)/ADC[2]_3
P18.2 PWM0_55/PWM0_M_7_N/TC0_55_TR0/TC0_M_7_TR1/PWM0_H_1/SCB1_RTS (0)/SCB1_SCL (0)/SCB1_CLK (0)/ADC[2]_2
P18.1 PWM0_M_7/PWM0_M_6_N/TC0_M_7_TR0/TC0_M_6_TR1/PWM0_H_0_N/SCB1_TX (0)/SCB1_SDA (0)/SCB1_MOSI (0)/FAULT_OUT_1/ADC[2]_1
P18.0 PWM0_M_6/PWM0_M_5_N/TC0_M_6_TR0/TC0_M_5_TR1/PWM0_H_0/SCB1_RX (0)/SCB1_MISO (0)/FAULT_OUT_0/ADC[2]_0
P17.7 PWM0_M_5/PWM0_M_4_N/TC0_M_5_TR0/TC0_M_4_TR1
3
4
5
6
7
8
PWM0_8/PWM0_10_N/TC0_8_TR0/TC0_10_TR1/SCB0_SEL0 (1)/TRIG_IN[1] P1.3
9
PWM0_7/PWM0_8_N/TC0_7_TR0/TC0_8_TR1/SCB7_RX (0)/SCB0_SEL1 (0)/SCB7_MISO (0)/LIN0_RX/CAN0_0_TX/SWJ_TRSTN/TRIG_IN[2] P2.0
PWM0_6/PWM0_7_N/TC0_6_TR0/TC0_7_TR1/SCB7_TX (0)/SCB7_SDA (0)/SCB0_SEL2 (0)/SCB7_MOSI (0)/LIN0_TX/CAN0_0_RX/TRIG_IN[3] P2.1
PWM0_5/PWM0_6_N/TC0_5_TR0/TC0_6_TR1/SCB7_RTS (0)/SCB7_SCL (0)/SCB0_SEL3 (0)/SCB7_CLK (0)/LIN0_EN/TRIG_IN[4] P2.2
PWM0_4/PWM0_5_N/TC0_4_TR0/TC0_5_TR1/SCB7_CTS (0)/SCB7_SEL0 (0)/LIN5_RX/TRIG_IN[5] P2.3
PWM0_3/PWM0_4_N/TC0_3_TR0/TC0_4_TR1/SCB7_SEL1 (0)/LIN5_TX/TRIG_IN[6] P2.4
PWM0_2/PWM0_3_N/TC0_2_TR0/TC0_3_TR1/SCB7_SEL2 (0)/LIN5_EN/TRIG_IN[7] P2.5
PWM0_1/PWM0_2_N/TC0_1_TR0/TC0_2_TR1/SCB6_RX (0)/SCB6_MISO (0)/TRIG_DBG[0] P3.0
PWM0_0/PWM0_1_N/TC0_0_TR0/TC0_1_TR1/SCB6_TX (0)/SCB6_SDA (0)/SCB6_MOSI (0)/TRIG_DBG[1] P3.1
PWM0_M_3/PWM0_0_N/TC0_M_3_TR0/TC0_0_TR1/SCB6_RTS (0)/SCB6_SCL (0)/SCB6_CLK (0) P3.2
PWM0_M_2/PWM0_M_3_N/TC0_M_2_TR0/TC0_M_3_TR1/SCB6_CTS (0)/SCB6_SEL0 (0) P3.3
PWM0_M_1/PWM0_M_2_N/TC0_M_1_TR0/TC0_M_2_TR1/SCB6_SEL1 (0) P3.4
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
P17.6 PWM0_M_4/PWM0_56_N/TC0_M_4_TR0/TC0_56_TR1/SCB3_SEL2 (1)
P17.5 PWM0_56/PWM0_57_N/TC0_56_TR0/TC0_57_TR1/SCB3_SEL1 (1)
P17.4 PWM0_57/PWM0_58_N/TC0_57_TR0/TC0_58_TR1/PWM0_H_3_N/SCB3_CTS (1)/SCB3_SEL0 (1)/TRIG_IN[27]
P17.3 PWM0_58/PWM0_59_N/TC0_58_TR0/TC0_59_TR1/PWM0_H_3/SCB3_RTS (1)/SCB3_SCL (1)/SCB3_CLK (1)/TRIG_IN[26]
P17.2 PWM0_59/PWM0_60_N/TC0_59_TR0/TC0_60_TR1/PWM0_H_2_N/SCB3_TX (1)/SCB3_SDA (1)/SCB3_MOSI (1)
P17.1 PWM0_60/PWM0_61_N/TC0_60_TR0/TC0_61_TR1/PWM0_H_2/SCB3_RX (1)/SCB3_MISO (1)/CAN1_1_RX
P17.0 PWM0_61/PWM0_62_N/TC0_61_TR0/TC0_62_TR1/CAN1_1_TX
P16.3 PWM0_62/PWM0_62_N/TC0_62_TR0/TC0_62_TR1/PWM0_H_1_N
P16.2 PWM0_62/PWM0_61_N/TC0_62_TR0/TC0_61_TR1/PWM0_H_1
P16.1 PWM0_61/PWM0_60_N/TC0_61_TR0/TC0_60_TR1/PWM0_H_0_N
PWM0_M_0/PWM0_M_1_N/TC0_M_0_TR0/TC0_M_1_TR1/SCB6_SEL2 (0) P3.5
P16.0 PWM0_60/PWM0_59_N/TC0_60_TR0/TC0_59_TR1/PWM0_H_0
VDDD
VSSD
VSSD
VDDD
176-TEQFP
PWM0_4/PWM0_M_0_N/TC0_4_TR0/TC0_M_0_TR1/EXT_MUX[0]_0/SCB5_RX (0)/SCB5_MISO (0)/LIN1_RX/TRIG_IN[10] P4.0
PWM0_5/PWM0_4_N/TC0_5_TR0/TC0_4_TR1/EXT_MUX[0]_1/SCB5_TX (0)/SCB5_SDA (0)/SCB5_MOSI (0)/LIN1_TX/TRIG_IN[11] P4.1
PWM0_6/PWM0_5_N/TC0_6_TR0/TC0_5_TR1/EXT_MUX[0]_2/SCB5_RTS (0)/SCB5_SCL (0)/SCB5_CLK (0)/LIN1_EN/TRIG_IN[12] P4.2
PWM0_7/PWM0_6_N/TC0_7_TR0/TC0_6_TR1/EXT_MUX[0]_EN/SCB5_CTS (0)/SCB5_SEL0 (0)/CAN0_1_TX/TRIG_IN[13] P4.3
PWM0_8/PWM0_7_N/TC0_8_TR0/TC0_7_TR1/SCB5_SEL1 (0)/CAN0_1_RX P4.4
P15.3 PWM0_59/PWM0_58_N/TC0_59_TR0/TC0_58_TR1/ADC[1]_31
P15.2 PWM0_58/PWM0_57_N/TC0_58_TR0/TC0_57_TR1/ADC[1]_30
P15.1 PWM0_57/PWM0_56_N/TC0_57_TR0/TC0_56_TR1/ADC[1]_29
P15.0 PWM0_56/PWM0_55_N/TC0_56_TR0/TC0_55_TR1/ADC[1]_28
P14.7 PWM0_55/PWM0_54_N/TC0_55_TR0/TC0_54_TR1/TRIG_IN[25]/ADC[1]_27
PWM0_9/PWM0_8_N/TC0_9_TR0/TC0_8_TR1/SCB5_SEL2 (0)/LIN7_RX P5.0
P14.6 PWM0_54/PWM0_53_N/TC0_54_TR0/TC0_53_TR1/TRIG_IN[24]/ADC[1]_26
PWM0_10/PWM0_9_N/TC0_10_TR0/TC0_9_TR1/LIN7_TX P5.1
P14.5 PWM0_53/PWM0_52_N/TC0_53_TR0/TC0_52_TR1/SCB2_SEL2 (0)/ADC[1]_25
P14.4 PWM0_52/PWM0_51_N/TC0_52_TR0/TC0_51_TR1/SCB2_SEL1 (0)/LIN6_EN/ADC[1]_24
P14.3 PWM0_51/PWM0_50_N/TC0_51_TR0/TC0_50_TR1/SCB2_CTS (0)/SCB2_SEL0 (0)/LIN6_TX/ADC[1]_23
P14.2 PWM0_50/PWM0_49_N/TC0_50_TR0/TC0_49_TR1/SCB2_RTS (0)/SCB2_SCL (0)/SCB2_CLK (0)/LIN6_RX/ADC[1]_22
P14.1 PWM0_49/PWM0_48_N/TC0_49_TR0/TC0_48_TR1/SCB2_TX (0)/SCB2_SDA (0)/SCB2_MOSI (0)/CAN1_0_RX/ADC[1]_21
P14.0 PWM0_48/PWM0_47_N/TC0_48_TR0/TC0_47_TR1/SCB2_RX (0)/SCB2_MISO (0)/CAN1_0_TX/ADC[1]_20
P13.7 PWM0_47/PWM0_M_11_N/TC0_47_TR0/TC0_M_11_TR1/TRIG_IN[23]/ADC[1]_19
P13.6 PWM0_M_11/PWM0_46_N/TC0_M_11_TR0/TC0_46_TR1/SCB3_SEL3 (0)/TRIG_IN[22]/ADC[1]_18
P13.5 PWM0_46/PWM0_M_10_N/TC0_46_TR0/TC0_M_10_TR1/SCB3_SEL2 (0)/ADC[1]_17
P13.4 PWM0_M_10/PWM0_45_N/TC0_M_10_TR0/TC0_45_TR1/SCB3_SEL1 (0)/ADC[1]_16
P13.3 PWM0_45/PWM0_M_9_N/TC0_45_TR0/TC0_M_9_TR1/EXT_MUX[2]_EN/SCB3_CTS (0)/SCB3_SEL0 (0)/ADC[1]_15
P13.2 PWM0_M_9/PWM0_44_N/TC0_M_9_TR0/TC0_44_TR1/EXT_MUX[2]_2/SCB3_RTS (0)/SCB3_SCL (0)/SCB3_CLK (0)/ADC[1]_14
P13.1 PWM0_44/PWM0_M_8_N/TC0_44_TR0/TC0_M_8_TR1/EXT_MUX[2]_1/SCB3_TX (0)/SCB3_SDA (0)/SCB3_MOSI (0)/ADC[1]_13
P13.0 PWM0_M_8/PWM0_43_N/TC0_M_8_TR0/TC0_43_TR1/EXT_MUX[2]_0/SCB3_RX (0)/SCB3_MISO (0)/ADC[1]_12
VSSD
PWM0_11/PWM0_10_N/TC0_11_TR0/TC0_10_TR1/LIN7_EN P5.2
PWM0_12/PWM0_11_N/TC0_12_TR0/TC0_11_TR1/LIN2_RX P5.3
PWM0_13/PWM0_12_N/TC0_13_TR0/TC0_12_TR1/LIN2_TX P5.4
PWM0_14/PWM0_13_N/TC0_14_TR0/TC0_13_TR1/LIN2_EN P5.5
PWM0_M_0/PWM0_14_N/TC0_M_0_TR0/TC0_14_TR1/SCB4_RX (0)/SCB4_MISO (0)/LIN3_RX/ADC[0]_0 P6.0
PWM0_0/PWM0_M_0_N/TC0_0_TR0/TC0_M_0_TR1/SCB4_TX (0)/SCB4_SDA (0)/SCB4_MOSI (0)/LIN3_TX/ADC[0]_1 P6.1
PWM0_M_1/PWM0_0_N/TC0_M_1_TR0/TC0_0_TR1/SCB4_RTS (0)/SCB4_SCL (0)/SCB4_CLK (0)/LIN3_EN/CAN0_2_TX/ADC[0]_2 P6.2
PWM0_1/PWM0_M_1_N/TC0_1_TR0/TC0_M_1_TR1/SCB4_CTS (0)/SCB4_SEL0 (0)/LIN4_RX/CAN0_2_RX/CAL_SUP_NZ/ADC[0]_3 P6.3
PWM0_M_2/PWM0_1_N/TC0_M_2_TR0/TC0_1_TR1/SCB4_SEL1 (0)/LIN4_TX/ADC[0]_4 P6.4
PWM0_2/PWM0_M_2_N/TC0_2_TR0/TC0_M_2_TR1/SCB4_SEL2 (0)/LIN4_EN/ADC[0]_5 P6.5
PWM0_M_3/PWM0_2_N/TC0_M_3_TR0/TC0_2_TR1/SCB4_SEL3 (0)/TRIG_IN[8]/ADC[0]_6 P6.6
PWM0_3/PWM0_M_3_N/TC0_3_TR0/TC0_M_3_TR1/TRIG_IN[9]/ADC[0]_7 P6.7
98
97
96
95
94
93
92
91
VDDD
90
VDDIO_1
89
Figure 9-2
176-LQFP pin assignment with alternate functions
Datasheet
24
002-18043 Rev. *J
2022-09-08
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4F single
Pin assignment
VSSD
P0.0
P0.1
P0.2
P0.3
P1.0
P1.1
P2.0
P2.1
P2.2
P2.3
P2.4
P3.0
P3.1
P3.2
P3.3
P3.4
VDDD
VSSD
P4.0
P4.1
P5.0
P5.1
P5.2
P5.3
P5.4
P6.0
P6.1
P6.2
P6.3
P6.4
P6.5
P6.6
P6.7
VDDD
VDDIO_1
1
108
107
106
105
104
103
102
101
100
99
VDDD
P18.7
P18.6
P18.5
P18.4
P18.3
P18.2
P18.1
P18.0
P17.4
P17.3
P17.2
P17.1
P17.0
P16.2
P16.1
P16.0
P15.3
P15.2
P15.1
P15.0
P14.5
P14.4
P14.3
P14.2
P14.1
P14.0
P13.7
P13.6
P13.5
P13.4
P13.3
P13.2
P13.1
P13.0
VSSD
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
98
97
96
95
94
93
92
91
144-LQFP
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
Figure 9-3
144-LQFP pin assignment
Datasheet
25
002-18043 Rev. *J
2022-09-08
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4F single
Pin assignment
VSSD
PWM0_18/PWM0_22_N/TC0_18_TR0/TC0_22_TR1/SCB0_RX (0)/SCB7_SDA (2)/SCB0_MISO (0)/LIN1_RX P0.0
PWM0_17/PWM0_18_N/TC0_17_TR0/TC0_18_TR1/SCB0_TX (0)/SCB7_SCL (2)/SCB0_MOSI (0)/LIN1_TX P0.1
PWM0_14/PWM0_17_N/TC0_14_TR0/TC0_17_TR1/SCB0_RTS (0)/SCB0_SCL (0)/SCB0_CLK (0)/LIN1_EN/CAN0_1_TX P0.2
PWM0_13/PWM0_14_N/TC0_13_TR0/TC0_14_TR1/SCB0_CTS (0)/SCB0_SDA (0)/SCB0_SEL0 (0)/CAN0_1_RX P0.3
PWM0_12/PWM0_13_N/TC0_12_TR0/TC0_13_TR1/SCB0_SCL (1)/SCB0_MISO (1) P1.0
PWM0_11/PWM0_12_N/TC0_11_TR0/TC0_12_TR1/SCB0_SDA (1)/SCB0_MOSI (1) P1.1
PWM0_7/PWM0_8_N/TC0_7_TR0/TC0_8_TR1/SCB7_RX (0)/SCB0_SEL1 (0)/SCB7_MISO (0)/LIN0_RX/CAN0_0_TX/SWJ_TRSTN/TRIG_IN[2] P2.0
PWM0_6/PWM0_7_N/TC0_6_TR0/TC0_7_TR1/SCB7_TX (0)/SCB7_SDA (0)/SCB0_SEL2 (0)/SCB7_MOSI (0)/LIN0_TX/CAN0_0_RX/TRIG_IN[3] P2.1
PWM0_5/PWM0_6_N/TC0_5_TR0/TC0_6_TR1/SCB7_RTS (0)/SCB7_SCL (0)/SCB0_SEL3 (0)/SCB7_CLK (0)/LIN0_EN/TRIG_IN[4] P2.2
PWM0_4/PWM0_5_N/TC0_4_TR0/TC0_5_TR1/SCB7_CTS (0)/SCB7_SEL0 (0)/LIN5_RX/TRIG_IN[5] P2.3
PWM0_3/PWM0_4_N/TC0_3_TR0/TC0_4_TR1/SCB7_SEL1 (0)/LIN5_TX/TRIG_IN[6] P2.4
PWM0_1/PWM0_2_N/TC0_1_TR0/TC0_2_TR1/SCB6_RX (0)/SCB6_MISO (0)/TRIG_DBG[0] P3.0
PWM0_0/PWM0_1_N/TC0_0_TR0/TC0_1_TR1/SCB6_TX (0)/SCB6_SDA (0)/SCB6_MOSI (0)/TRIG_DBG[1] P3.1
PWM0_M_3/PWM0_0_N/TC0_M_3_TR0/TC0_0_TR1/SCB6_RTS (0)/SCB6_SCL (0)/SCB6_CLK (0) P3.2
PWM0_M_2/PWM0_M_3_N/TC0_M_2_TR0/TC0_M_3_TR1/SCB6_CTS (0)/SCB6_SEL0 (0) P3.3
PWM0_M_1/PWM0_M_2_N/TC0_M_1_TR0/TC0_M_2_TR1/SCB6_SEL1 (0) P3.4
1
108
107
106
105
104
103
102
101
100
99
VDDD
2
P18.7 PWM0_50/PWM0_51_N/TC0_50_TR0/TC0_51_TR1/PWM0_H_3_N/CAN1_2_RX/TRACE_DATA_3 (0)/ADC[2]_7
P18.6 PWM0_51/PWM0_52_N/TC0_51_TR0/TC0_52_TR1/PWM0_H_3/SCB1_SEL3 (0)/CAN1_2_TX/TRACE_DATA_2 (0)/ADC[2]_6
P18.5 PWM0_52/PWM0_53_N/TC0_52_TR0/TC0_53_TR1/PWM0_H_2_N/SCB1_SEL2 (0)/TRACE_DATA_1 (0)/ADC[2]_5
P18.4 PWM0_53/PWM0_54_N/TC0_53_TR0/TC0_54_TR1/PWM0_H_2/SCB1_SEL1 (0)/TRACE_DATA_0 (0)/ADC[2]_4
P18.3 PWM0_54/PWM0_55_N/TC0_54_TR0/TC0_55_TR1/PWM0_H_1_N/SCB1_CTS (0)/SCB1_SEL0 (0)/TRACE_CLOCK (0)/ADC[2]_3
P18.2 PWM0_55/PWM0_M_7_N/TC0_55_TR0/TC0_M_7_TR1/PWM0_H_1/SCB1_RTS (0)/SCB1_SCL (0)/SCB1_CLK (0)/ADC[2]_2
P18.1 PWM0_M_7/PWM0_M_6_N/TC0_M_7_TR0/TC0_M_6_TR1/PWM0_H_0_N/SCB1_TX (0)/SCB1_SDA (0)/SCB1_MOSI (0)/FAULT_OUT_1/ADC[2]_1
P18.0 PWM0_M_6/PWM0_M_5_N/TC0_M_6_TR0/TC0_M_5_TR1/PWM0_H_0/SCB1_RX (0)/SCB1_MISO (0)/FAULT_OUT_0/ADC[2]_0
P17.4 PWM0_57/PWM0_58_N/TC0_57_TR0/TC0_58_TR1/PWM0_H_3_N/SCB3_CTS (1)/SCB3_SEL0 (1)/TRIG_IN[27]
P17.3 PWM0_58/PWM0_59_N/TC0_58_TR0/TC0_59_TR1/PWM0_H_3/SCB3_RTS (1)/SCB3_SCL (1)/SCB3_CLK (1)/TRIG_IN[26]
P17.2 PWM0_59/PWM0_60_N/TC0_59_TR0/TC0_60_TR1/PWM0_H_2_N/SCB3_TX (1)/SCB3_SDA (1)/SCB3_MOSI (1)
P17.1 PWM0_60/PWM0_61_N/TC0_60_TR0/TC0_61_TR1/PWM0_H_2/SCB3_RX (1)/SCB3_MISO (1)/CAN1_1_RX
P17.0 PWM0_61/PWM0_62_N/TC0_61_TR0/TC0_62_TR1/CAN1_1_TX
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
98
97
96
95
94
P16.2 PWM0_62/PWM0_61_N/TC0_62_TR0/TC0_61_TR1/PWM0_H_1
93
P16.1 PWM0_61/PWM0_60_N/TC0_61_TR0/TC0_60_TR1/PWM0_H_0_N
92
P16.0 PWM0_60/PWM0_59_N/TC0_60_TR0/TC0_59_TR1/PWM0_H_0
VDDD
91
P15.3 PWM0_59/PWM0_58_N/TC0_59_TR0/TC0_58_TR1/ADC[1]_31
VSSD
90
P15.2 PWM0_58/PWM0_57_N/TC0_58_TR0/TC0_57_TR1/ADC[1]_30
144-TEQFP
PWM0_4/PWM0_M_0_N/TC0_4_TR0/TC0_M_0_TR1/EXT_MUX[0]_0/SCB5_RX (0)/SCB5_MISO (0)/LIN1_RX/TRIG_IN[10] P4.0
PWM0_5/PWM0_4_N/TC0_5_TR0/TC0_4_TR1/EXT_MUX[0]_1/SCB5_TX (0)/SCB5_SDA (0)/SCB5_MOSI (0)/LIN1_TX/TRIG_IN[11] P4.1
PWM0_9/PWM0_8_N/TC0_9_TR0/TC0_8_TR1/SCB5_SEL2 (0)/LIN7_RX P5.0
89
P15.1 PWM0_57/PWM0_56_N/TC0_57_TR0/TC0_56_TR1/ADC[1]_29
88
P15.0 PWM0_56/PWM0_55_N/TC0_56_TR0/TC0_55_TR1/ADC[1]_28
87
P14.5 PWM0_53/PWM0_52_N/TC0_53_TR0/TC0_52_TR1/SCB2_SEL2 (0)/ADC[1]_25
PWM0_10/PWM0_9_N/TC0_10_TR0/TC0_9_TR1/LIN7_TX P5.1
86
P14.4 PWM0_52/PWM0_51_N/TC0_52_TR0/TC0_51_TR1/SCB2_SEL1 (0)/LIN6_EN/ADC[1]_24
P14.3 PWM0_51/PWM0_50_N/TC0_51_TR0/TC0_50_TR1/SCB2_CTS (0)/SCB2_SEL0 (0)/LIN6_TX/ADC[1]_23
P14.2 PWM0_50/PWM0_49_N/TC0_50_TR0/TC0_49_TR1/SCB2_RTS (0)/SCB2_SCL (0)/SCB2_CLK (0)/LIN6_RX/ADC[1]_22
P14.1 PWM0_49/PWM0_48_N/TC0_49_TR0/TC0_48_TR1/SCB2_TX (0)/SCB2_SDA (0)/SCB2_MOSI (0)/CAN1_0_RX/ADC[1]_21
P14.0 PWM0_48/PWM0_47_N/TC0_48_TR0/TC0_47_TR1/SCB2_RX (0)/SCB2_MISO (0)/CAN1_0_TX/ADC[1]_20
P13.7 PWM0_47/PWM0_M_11_N/TC0_47_TR0/TC0_M_11_TR1/TRIG_IN[23]/ADC[1]_19
PWM0_11/PWM0_10_N/TC0_11_TR0/TC0_10_TR1/LIN7_EN P5.2
85
PWM0_12/PWM0_11_N/TC0_12_TR0/TC0_11_TR1/LIN2_RX P5.3
84
PWM0_13/PWM0_12_N/TC0_13_TR0/TC0_12_TR1/LIN2_TX P5.4
83
PWM0_M_0/PWM0_14_N/TC0_M_0_TR0/TC0_14_TR1/SCB4_RX (0)/SCB4_MISO (0)/LIN3_RX/ADC[0]_0 P6.0
PWM0_0/PWM0_M_0_N/TC0_0_TR0/TC0_M_0_TR1/SCB4_TX (0)/SCB4_SDA (0)/SCB4_MOSI (0)/LIN3_TX/ADC[0]_1 P6.1
PWM0_M_1/PWM0_0_N/TC0_M_1_TR0/TC0_0_TR1/SCB4_RTS (0)/SCB4_SCL (0)/SCB4_CLK (0)/LIN3_EN/CAN0_2_TX/ADC[0]_2 P6.2
PWM0_1/PWM0_M_1_N/TC0_1_TR0/TC0_M_1_TR1/SCB4_CTS (0)/SCB4_SEL0 (0)/LIN4_RX/CAN0_2_RX/CAL_SUP_NZ/ADC[0]_3 P6.3
PWM0_M_2/PWM0_1_N/TC0_M_2_TR0/TC0_1_TR1/SCB4_SEL1 (0)/LIN4_TX/ADC[0]_4 P6.4
PWM0_2/PWM0_M_2_N/TC0_2_TR0/TC0_M_2_TR1/SCB4_SEL2 (0)/LIN4_EN/ADC[0]_5 P6.5
PWM0_M_3/PWM0_2_N/TC0_M_3_TR0/TC0_2_TR1/SCB4_SEL3 (0)/TRIG_IN[8]/ADC[0]_6 P6.6
PWM0_3/PWM0_M_3_N/TC0_3_TR0/TC0_M_3_TR1/TRIG_IN[9]/ADC[0]_7 P6.7
82
81
80
P13.6 PWM0_M_11/PWM0_46_N/TC0_M_11_TR0/TC0_46_TR1/SCB3_SEL3 (0)/TRIG_IN[22]/ADC[1]_18
P13.5 PWM0_46/PWM0_M_10_N/TC0_46_TR0/TC0_M_10_TR1/SCB3_SEL2 (0)/ADC[1]_17
P13.4 PWM0_M_10/PWM0_45_N/TC0_M_10_TR0/TC0_45_TR1/SCB3_SEL1 (0)/ADC[1]_16
P13.3 PWM0_45/PWM0_M_9_N/TC0_45_TR0/TC0_M_9_TR1/EXT_MUX[2]_EN/SCB3_CTS (0)/SCB3_SEL0 (0)/ADC[1]_15
P13.2 PWM0_M_9/PWM0_44_N/TC0_M_9_TR0/TC0_44_TR1/EXT_MUX[2]_2/SCB3_RTS (0)/SCB3_SCL (0)/SCB3_CLK (0)/ADC[1]_14
P13.1 PWM0_44/PWM0_M_8_N/TC0_44_TR0/TC0_M_8_TR1/EXT_MUX[2]_1/SCB3_TX (0)/SCB3_SDA (0)/SCB3_MOSI (0)/ADC[1]_13
P13.0 PWM0_M_8/PWM0_43_N/TC0_M_8_TR0/TC0_43_TR1/EXT_MUX[2]_0/SCB3_RX (0)/SCB3_MISO (0)/ADC[1]_12
VSSD
79
78
77
76
75
VDDD
74
VDDIO_1
73
Figure 9-4
144-LQFP pin assignment with alternate functions
Datasheet
26
002-18043 Rev. *J
2022-09-08
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4F single
Pin assignment
VSSD
P0.0
1
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
VDDD
P18.7
P18.6
P18.5
P18.4
P18.3
P18.2
P18.1
P18.0
P17.2
P17.1
P17.0
P14.3
P14.2
P14.1
P14.0
P13.7
P13.6
P13.5
P13.4
P13.3
P13.2
P13.1
P13.0
VSSD
2
P0.1
3
P0.2
4
P0.3
5
P2.0
6
P2.1
7
P2.2
8
P2.3
9
P3.0
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
P3.1
VDDD
VSSD
P5.0
100-LQFP
P5.1
P5.2
P5.3
P6.0
P6.1
P6.2
P6.3
P6.4
P6.5
VDDD
VDDIO_1
Figure 9-5
100-LQFP pin assignment
Datasheet
27
002-18043 Rev. *J
2022-09-08
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4F single
Pin assignment
VSSD
PWM0_18/PWM0_22_N/TC0_18_TR0/TC0_22_TR1/SCB0_RX (0)/SCB7_SDA (2)/SCB0_MISO (0)/LIN1_RX P0.0
PWM0_17/PWM0_18_N/TC0_17_TR0/TC0_18_TR1/SCB0_TX (0)/SCB7_SCL (2)/SCB0_MOSI (0)/LIN1_TX P0.1
PWM0_14/PWM0_17_N/TC0_14_TR0/TC0_17_TR1/SCB0_RTS (0)/SCB0_SCL (0)/SCB0_CLK (0)/LIN1_EN/CAN0_1_TX P0.2
PWM0_13/PWM0_14_N/TC0_13_TR0/TC0_14_TR1/SCB0_CTS (0)/SCB0_SDA (0)/SCB0_SEL0 (0)/CAN0_1_RX P0.3
PWM0_7/PWM0_8_N/TC0_7_TR0/TC0_8_TR1/SCB7_RX (0)/SCB0_SEL1 (0)/SCB7_MISO (0)/LIN0_RX/CAN0_0_TX/SWJ_TRSTN/TRIG_IN[2] P2.0
PWM0_6/PWM0_7_N/TC0_6_TR0/TC0_7_TR1/SCB7_TX (0)/SCB7_SDA (0)/SCB0_SEL2 (0)/SCB7_MOSI (0)/LIN0_TX/CAN0_0_RX/TRIG_IN[3] P2.1
PWM0_5/PWM0_6_N/TC0_5_TR0/TC0_6_TR1/SCB7_RTS (0)/SCB7_SCL (0)/SCB0_SEL3 (0)/SCB7_CLK (0)/LIN0_EN/TRIG_IN[4] P2.2
PWM0_4/PWM0_5_N/TC0_4_TR0/TC0_5_TR1/SCB7_CTS (0)/SCB7_SEL0 (0)/LIN5_RX/TRIG_IN[5] P2.3
PWM0_1/PWM0_2_N/TC0_1_TR0/TC0_2_TR1/SCB6_RX (0)/SCB6_MISO (0)/TRIG_DBG[0] P3.0
PWM0_0/PWM0_1_N/TC0_0_TR0/TC0_1_TR1/SCB6_TX (0)/SCB6_SDA (0)/SCB6_MOSI (0)/TRIG_DBG[1] P3.1
VDDD
1
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
VDDD
2
P18.7 PWM0_50/PWM0_51_N/TC0_50_TR0/TC0_51_TR1/PWM0_H_3_N/CAN1_2_RX/TRACE_DATA_3 (0)/ADC[2]_7
P18.6 PWM0_51/PWM0_52_N/TC0_51_TR0/TC0_52_TR1/PWM0_H_3/SCB1_SEL3 (0)/CAN1_2_TX/TRACE_DATA_2 (0)/ADC[2]_6
P18.5 PWM0_52/PWM0_53_N/TC0_52_TR0/TC0_53_TR1/PWM0_H_2_N/SCB1_SEL2 (0)/TRACE_DATA_1 (0)/ADC[2]_5
P18.4 PWM0_53/PWM0_54_N/TC0_53_TR0/TC0_54_TR1/PWM0_H_2/SCB1_SEL1 (0)/TRACE_DATA_0 (0)/ADC[2]_4
P18.3 PWM0_54/PWM0_55_N/TC0_54_TR0/TC0_55_TR1/PWM0_H_1_N/SCB1_CTS (0)/SCB1_SEL0 (0)/TRACE_CLOCK (0)/ADC[2]_3
P18.2 PWM0_55/PWM0_M_7_N/TC0_55_TR0/TC0_M_7_TR1/PWM0_H_1/SCB1_RTS (0)/SCB1_SCL (0)/SCB1_CLK (0)/ADC[2]_2
P18.1 PWM0_M_7/PWM0_M_6_N/TC0_M_7_TR0/TC0_M_6_TR1/PWM0_H_0_N/SCB1_TX (0)/SCB1_SDA (0)/SCB1_MOSI (0)/FAULT_OUT_1/ADC[2]_1
P18.0 PWM0_M_6/PWM0_M_5_N/TC0_M_6_TR0/TC0_M_5_TR1/PWM0_H_0/SCB1_RX (0)/SCB1_MISO (0)/FAULT_OUT_0/ADC[2]_0
P17.2 PWM0_59/PWM0_60_N/TC0_59_TR0/TC0_60_TR1/PWM0_H_2_N/SCB3_TX (1)/SCB3_SDA (1)/SCB3_MOSI (1)
P17.1 PWM0_60/PWM0_61_N/TC0_60_TR0/TC0_61_TR1/PWM0_H_2/SCB3_RX (1)/SCB3_MISO (1)/CAN1_1_RX
P17.0 PWM0_61/PWM0_62_N/TC0_61_TR0/TC0_62_TR1/CAN1_1_TX
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
VSSD
P14.3 PWM0_51/PWM0_50_N/TC0_51_TR0/TC0_50_TR1/SCB2_CTS (0)/SCB2_SEL0 (0)/LIN6_TX/ADC[1]_23
P14.2 PWM0_50/PWM0_49_N/TC0_50_TR0/TC0_49_TR1/SCB2_RTS (0)/SCB2_SCL (0)/SCB2_CLK (0)/LIN6_RX/ADC[1]_22
P14.1 PWM0_49/PWM0_48_N/TC0_49_TR0/TC0_48_TR1/SCB2_TX (0)/SCB2_SDA (0)/SCB2_MOSI (0)/CAN1_0_RX/ADC[1]_21
P14.0 PWM0_48/PWM0_47_N/TC0_48_TR0/TC0_47_TR1/SCB2_RX (0)/SCB2_MISO (0)/CAN1_0_TX/ADC[1]_20
P13.7 PWM0_47/PWM0_M_11_N/TC0_47_TR0/TC0_M_11_TR1/TRIG_IN[23]/ADC[1]_19
PWM0_9/PWM0_8_N/TC0_9_TR0/TC0_8_TR1/SCB5_SEL2 (0)/LIN7_RX P5.0
100-TEQFP
PWM0_10/PWM0_9_N/TC0_10_TR0/TC0_9_TR1/LIN7_TX P5.1
PWM0_11/PWM0_10_N/TC0_11_TR0/TC0_10_TR1/LIN7_EN P5.2
PWM0_12/PWM0_11_N/TC0_12_TR0/TC0_11_TR1/LIN2_RX P5.3
PWM0_M_0/PWM0_14_N/TC0_M_0_TR0/TC0_14_TR1/SCB4_RX (0)/SCB4_MISO (0)/LIN3_RX/ADC[0]_0 P6.0
PWM0_0/PWM0_M_0_N/TC0_0_TR0/TC0_M_0_TR1/SCB4_TX (0)/SCB4_SDA (0)/SCB4_MOSI (0)/LIN3_TX/ADC[0]_1 P6.1
PWM0_M_1/PWM0_0_N/TC0_M_1_TR0/TC0_0_TR1/SCB4_RTS (0)/SCB4_SCL (0)/SCB4_CLK (0)/LIN3_EN/CAN0_2_TX/ADC[0]_2 P6.2
PWM0_1/PWM0_M_1_N/TC0_1_TR0/TC0_M_1_TR1/SCB4_CTS (0)/SCB4_SEL0 (0)/LIN4_RX/CAN0_2_RX/CAL_SUP_NZ/ADC[0]_3 P6.3
PWM0_M_2/PWM0_1_N/TC0_M_2_TR0/TC0_1_TR1/SCB4_SEL1 (0)/LIN4_TX/ADC[0]_4 P6.4
PWM0_2/PWM0_M_2_N/TC0_2_TR0/TC0_M_2_TR1/SCB4_SEL2 (0)/LIN4_EN/ADC[0]_5 P6.5
VDDD
P13.6 PWM0_M_11/PWM0_46_N/TC0_M_11_TR0/TC0_46_TR1/SCB3_SEL3 (0)/TRIG_IN[22]/ADC[1]_18
P13.5 PWM0_46/PWM0_M_10_N/TC0_46_TR0/TC0_M_10_TR1/SCB3_SEL2 (0)/ADC[1]_17
P13.4 PWM0_M_10/PWM0_45_N/TC0_M_10_TR0/TC0_45_TR1/SCB3_SEL1 (0)/ADC[1]_16
P13.3 PWM0_45/PWM0_M_9_N/TC0_45_TR0/TC0_M_9_TR1/EXT_MUX[2]_EN/SCB3_CTS (0)/SCB3_SEL0 (0)/ADC[1]_15
P13.2 PWM0_M_9/PWM0_44_N/TC0_M_9_TR0/TC0_44_TR1/EXT_MUX[2]_2/SCB3_RTS (0)/SCB3_SCL (0)/SCB3_CLK (0)/ADC[1]_14
P13.1 PWM0_44/PWM0_M_8_N/TC0_44_TR0/TC0_M_8_TR1/EXT_MUX[2]_1/SCB3_TX (0)/SCB3_SDA (0)/SCB3_MOSI (0)/ADC[1]_13
P13.0 PWM0_M_8/PWM0_43_N/TC0_M_8_TR0/TC0_43_TR1/EXT_MUX[2]_0/SCB3_RX (0)/SCB3_MISO (0)/ADC[1]_12
VSSD
VDDIO_1
Figure 9-6
100-LQFP pin assignment with alternate functions
Datasheet
28
002-18043 Rev. *J
2022-09-08
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4F single
Pin assignment
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
VDDD
P18.7
P18.6
P18.5
P18.4
P18.3
P18.2
P18.1
P18.0
P14.1
P14.0
P13.7
P13.6
P13.5
P13.4
P13.3
P13.2
P13.1
P13.0
VSSD
VSSD
P0.0
1
2
P0.1
3
P0.2
4
P0.3
5
P2.0
6
P2.1
7
P2.2
8
P2.3
9
P5.0
10
11
12
13
14
15
16
17
18
19
20
80-LQFP
P5.1
P5.2
P5.3
P6.0
P6.1
P6.2
P6.3
P6.4
P6.5
VDDIO_1
Figure 9-7
80-LQFP pin assignment
Datasheet
29
002-18043 Rev. *J
2022-09-08
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4F single
Pin assignment
VSSD
PWM0_18/PWM0_22_N/TC0_18_TR0/TC0_22_TR1/SCB0_RX (0)/SCB7_SDA (2)/SCB0_MISO (0)/LIN1_RX P0.0
PWM0_17/PWM0_18_N/TC0_17_TR0/TC0_18_TR1/SCB0_TX (0)/SCB7_SCL (2)/SCB0_MOSI (0)/LIN1_TX P0.1
PWM0_14/PWM0_17_N/TC0_14_TR0/TC0_17_TR1/SCB0_RTS (0)/SCB0_SCL (0)/SCB0_CLK (0)/LIN1_EN/CAN0_1_TX P0.2
PWM0_13/PWM0_14_N/TC0_13_TR0/TC0_14_TR1/SCB0_CTS (0)/SCB0_SDA (0)/SCB0_SEL0 (0)/CAN0_1_RX P0.3
PWM0_7/PWM0_8_N/TC0_7_TR0/TC0_8_TR1/SCB7_RX (0)/SCB0_SEL1 (0)/SCB7_MISO (0)/LIN0_RX/CAN0_0_TX/SWJ_TRSTN/TRIG_IN[2] P2.0
PWM0_6/PWM0_7_N/TC0_6_TR0/TC0_7_TR1/SCB7_TX (0)/SCB7_SDA (0)/SCB0_SEL2 (0)/SCB7_MOSI (0)/LIN0_TX/CAN0_0_RX/TRIG_IN[3] P2.1
PWM0_5/PWM0_6_N/TC0_5_TR0/TC0_6_TR1/SCB7_RTS (0)/SCB7_SCL (0)/SCB0_SEL3 (0)/SCB7_CLK (0)/LIN0_EN/TRIG_IN[4] P2.2
PWM0_4/PWM0_5_N/TC0_4_TR0/TC0_5_TR1/SCB7_CTS (0)/SCB7_SEL0 (0)/LIN5_RX/TRIG_IN[5] P2.3
PWM0_9/PWM0_8_N/TC0_9_TR0/TC0_8_TR1/SCB5_SEL2 (0)/LIN7_RX P5.0
1
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
VDDD
2
P18.7 PWM0_50/PWM0_51_N/TC0_50_TR0/TC0_51_TR1/PWM0_H_3_N/CAN1_2_RX/TRACE_DATA_3 (0)/ADC[2]_7
P18.6 PWM0_51/PWM0_52_N/TC0_51_TR0/TC0_52_TR1/PWM0_H_3/SCB1_SEL3 (0)/CAN1_2_TX/TRACE_DATA_2 (0)/ADC[2]_6
P18.5 PWM0_52/PWM0_53_N/TC0_52_TR0/TC0_53_TR1/PWM0_H_2_N/SCB1_SEL2 (0)/TRACE_DATA_1 (0)/ADC[2]_5
P18.4 PWM0_53/PWM0_54_N/TC0_53_TR0/TC0_54_TR1/PWM0_H_2/SCB1_SEL1 (0)/TRACE_DATA_0 (0)/ADC[2]_4
P18.3 PWM0_54/PWM0_55_N/TC0_54_TR0/TC0_55_TR1/PWM0_H_1_N/SCB1_CTS (0)/SCB1_SEL0 (0)/TRACE_CLOCK (0)/ADC[2]_3
P18.2 PWM0_55/PWM0_M_7_N/TC0_55_TR0/TC0_M_7_TR1/PWM0_H_1/SCB1_RTS (0)/SCB1_SCL (0)/SCB1_CLK (0)/ADC[2]_2
P18.1 PWM0_M_7/PWM0_M_6_N/TC0_M_7_TR0/TC0_M_6_TR1/PWM0_H_0_N/SCB1_TX (0)/SCB1_SDA (0)/SCB1_MOSI (0)/FAULT_OUT_1/ADC[2]_1
P18.0 PWM0_M_6/PWM0_M_5_N/TC0_M_6_TR0/TC0_M_5_TR1/PWM0_H_0/SCB1_RX (0)/SCB1_MISO (0)/FAULT_OUT_0/ADC[2]_0
P14.1 PWM0_49/PWM0_48_N/TC0_49_TR0/TC0_48_TR1/SCB2_TX (0)/SCB2_SDA (0)/SCB2_MOSI (0)/CAN1_0_RX/ADC[1]_21
P14.0 PWM0_48/PWM0_47_N/TC0_48_TR0/TC0_47_TR1/SCB2_RX (0)/SCB2_MISO (0)/CAN1_0_TX/ADC[1]_20
P13.7 PWM0_47/PWM0_M_11_N/TC0_47_TR0/TC0_M_11_TR1/TRIG_IN[23]/ADC[1]_19
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
PWM0_10/PWM0_9_N/TC0_10_TR0/TC0_9_TR1/LIN7_TX P5.1
80-TEQFP
PWM0_11/PWM0_10_N/TC0_11_TR0/TC0_10_TR1/LIN7_EN P5.2
PWM0_12/PWM0_11_N/TC0_12_TR0/TC0_11_TR1/LIN2_RX P5.3
P13.6 PWM0_M_11/PWM0_46_N/TC0_M_11_TR0/TC0_46_TR1/SCB3_SEL3 (0)/TRIG_IN[22]/ADC[1]_18
P13.5 PWM0_46/PWM0_M_10_N/TC0_46_TR0/TC0_M_10_TR1/SCB3_SEL2 (0)/ADC[1]_17
PWM0_M_0/PWM0_14_N/TC0_M_0_TR0/TC0_14_TR1/SCB4_RX (0)/SCB4_MISO (0)/LIN3_RX/ADC[0]_0 P6.0
PWM0_0/PWM0_M_0_N/TC0_0_TR0/TC0_M_0_TR1/SCB4_TX (0)/SCB4_SDA (0)/SCB4_MOSI (0)/LIN3_TX/ADC[0]_1 P6.1
PWM0_M_1/PWM0_0_N/TC0_M_1_TR0/TC0_0_TR1/SCB4_RTS (0)/SCB4_SCL (0)/SCB4_CLK (0)/LIN3_EN/CAN0_2_TX/ADC[0]_2 P6.2
PWM0_1/PWM0_M_1_N/TC0_1_TR0/TC0_M_1_TR1/SCB4_CTS (0)/SCB4_SEL0 (0)/LIN4_RX/CAN0_2_RX/CAL_SUP_NZ/ADC[0]_3 P6.3
PWM0_M_2/PWM0_1_N/TC0_M_2_TR0/TC0_1_TR1/SCB4_SEL1 (0)/LIN4_TX/ADC[0]_4 P6.4
P13.4 PWM0_M_10/PWM0_45_N/TC0_M_10_TR0/TC0_45_TR1/SCB3_SEL1 (0)/ADC[1]_16
P13.3 PWM0_45/PWM0_M_9_N/TC0_45_TR0/TC0_M_9_TR1/EXT_MUX[2]_EN/SCB3_CTS (0)/SCB3_SEL0 (0)/ADC[1]_15
P13.2 PWM0_M_9/PWM0_44_N/TC0_M_9_TR0/TC0_44_TR1/EXT_MUX[2]_2/SCB3_RTS (0)/SCB3_SCL (0)/SCB3_CLK (0)/ADC[1]_14
P13.1 PWM0_44/PWM0_M_8_N/TC0_44_TR0/TC0_M_8_TR1/EXT_MUX[2]_1/SCB3_TX (0)/SCB3_SDA (0)/SCB3_MOSI (0)/ADC[1]_13
P13.0 PWM0_M_8/PWM0_43_N/TC0_M_8_TR0/TC0_43_TR1/EXT_MUX[2]_0/SCB3_RX (0)/SCB3_MISO (0)/ADC[1]_12
VSSD
PWM0_2/PWM0_M_2_N/TC0_2_TR0/TC0_M_2_TR1/SCB4_SEL2 (0)/LIN4_EN/ADC[0]_5 P6.5
VDDIO_1
Figure 9-8
80-LQFP pin assignment with alternate functions
Datasheet
30
002-18043 Rev. *J
2022-09-08
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4F single
Pin assignment
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
VDDD
P18.7
P18.6
P18.5
P18.4
P18.3
P18.1
P18.0
P14.2
P14.1
P14.0
P13.3
P13.2
P13.1
P13.0
VSSD
P0.0
P0.1
P0.2
P0.3
P2.0
P2.1
1
2
3
4
5
6
P5.0
P5.1
7
8
64-LQFP
9
P6.0
P6.1
P6.2
P6.3
P6.4
P6.5
10
11
12
13
14
15
16
P6.6
VDDD
Figure 9-9
64-LQFP pin assignment
Datasheet
31
002-18043 Rev. *J
2022-09-08
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4F single
Pin assignment
PWM0_18/PWM0_22_N/TC0_18_TR0/TC0_22_TR1/SCB0_RX (0)/SCB7_SDA (2)/SCB0_MISO (0)/LIN1_RX P0.0
PWM0_17/PWM0_18_N/TC0_17_TR0/TC0_18_TR1/SCB0_TX (0)/SCB7_SCL (2)/SCB0_MOSI (0)/LIN1_TX P0.1
PWM0_14/PWM0_17_N/TC0_14_TR0/TC0_17_TR1/SCB0_RTS (0)/SCB0_SCL (0)/SCB0_CLK (0)/LIN1_EN/CAN0_1_TX P0.2
PWM0_13/PWM0_14_N/TC0_13_TR0/TC0_14_TR1/SCB0_CTS (0)/SCB0_SDA (0)/SCB0_SEL0 (0)/CAN0_1_RX P0.3
PWM0_7/PWM0_8_N/TC0_7_TR0/TC0_8_TR1/SCB7_RX (0)/SCB0_SEL1 (0)/SCB7_MISO (0)/LIN0_RX/CAN0_0_TX/SWJ_TRSTN/TRIG_IN[2] P2.0
PWM0_6/PWM0_7_N/TC0_6_TR0/TC0_7_TR1/SCB7_TX (0)/SCB7_SDA (0)/SCB0_SEL2 (0)/SCB7_MOSI (0)/LIN0_TX/CAN0_0_RX/TRIG_IN[3] P2.1
PWM0_9/PWM0_8_N/TC0_9_TR0/TC0_8_TR1/SCB5_SEL2 (0)/LIN7_RX P5.0
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
VDDD
2
P18.7 PWM0_50/PWM0_51_N/TC0_50_TR0/TC0_51_TR1/PWM0_H_3_N/CAN1_2_RX/TRACE_DATA_3 (0)/ADC[2]_7
P18.6 PWM0_51/PWM0_52_N/TC0_51_TR0/TC0_52_TR1/PWM0_H_3/SCB1_SEL3 (0)/CAN1_2_TX/TRACE_DATA_2 (0)/ADC[2]_6
P18.5 PWM0_52/PWM0_53_N/TC0_52_TR0/TC0_53_TR1/PWM0_H_2_N/SCB1_SEL2 (0)/TRACE_DATA_1 (0)/ADC[2]_5
P18.4 PWM0_53/PWM0_54_N/TC0_53_TR0/TC0_54_TR1/PWM0_H_2/SCB1_SEL1 (0)/TRACE_DATA_0 (0)/ADC[2]_4
P18.3 PWM0_54/PWM0_55_N/TC0_54_TR0/TC0_55_TR1/PWM0_H_1_N/SCB1_CTS (0)/SCB1_SEL0 (0)/TRACE_CLOCK (0)/ADC[2]_3
P18.1 PWM0_M_7/PWM0_M_6_N/TC0_M_7_TR0/TC0_M_6_TR1/PWM0_H_0_N/SCB1_TX (0)/SCB1_SDA (0)/SCB1_MOSI (0)/FAULT_OUT_1/ADC[2]_1
P18.0 PWM0_M_6/PWM0_M_5_N/TC0_M_6_TR0/TC0_M_5_TR1/PWM0_H_0/SCB1_RX (0)/SCB1_MISO (0)/FAULT_OUT_0/ADC[2]_0
P14.2 PWM0_50/PWM0_49_N/TC0_50_TR0/TC0_49_TR1/SCB2_RTS (0)/SCB2_SCL (0)/SCB2_CLK (0)/LIN6_RX/ADC[1]_22
P14.1 PWM0_49/PWM0_48_N/TC0_49_TR0/TC0_48_TR1/SCB2_TX (0)/SCB2_SDA (0)/SCB2_MOSI (0)/CAN1_0_RX/ADC[1]_21
P14.0 PWM0_48/PWM0_47_N/TC0_48_TR0/TC0_47_TR1/SCB2_RX (0)/SCB2_MISO (0)/CAN1_0_TX/ADC[1]_20
P13.3 PWM0_45/PWM0_M_9_N/TC0_45_TR0/TC0_M_9_TR1/EXT_MUX[2]_EN/SCB3_CTS (0)/SCB3_SEL0 (0)/ADC[1]_15
P13.2 PWM0_M_9/PWM0_44_N/TC0_M_9_TR0/TC0_44_TR1/EXT_MUX[2]_2/SCB3_RTS (0)/SCB3_SCL (0)/SCB3_CLK (0)/ADC[1]_14
P13.1 PWM0_44/PWM0_M_8_N/TC0_44_TR0/TC0_M_8_TR1/EXT_MUX[2]_1/SCB3_TX (0)/SCB3_SDA (0)/SCB3_MOSI (0)/ADC[1]_13
P13.0 PWM0_M_8/PWM0_43_N/TC0_M_8_TR0/TC0_43_TR1/EXT_MUX[2]_0/SCB3_RX (0)/SCB3_MISO (0)/ADC[1]_12
VSSD
3
4
5
6
7
PWM0_10/PWM0_9_N/TC0_10_TR0/TC0_9_TR1/LIN7_TX P5.1
8
64-TEQFP
PWM0_M_0/PWM0_14_N/TC0_M_0_TR0/TC0_14_TR1/SCB4_RX (0)/SCB4_MISO (0)/LIN3_RX/ADC[0]_0 P6.0
PWM0_0/PWM0_M_0_N/TC0_0_TR0/TC0_M_0_TR1/SCB4_TX (0)/SCB4_SDA (0)/SCB4_MOSI (0)/LIN3_TX/ADC[0]_1 P6.1
PWM0_M_1/PWM0_0_N/TC0_M_1_TR0/TC0_0_TR1/SCB4_RTS (0)/SCB4_SCL (0)/SCB4_CLK (0)/LIN3_EN/CAN0_2_TX/ADC[0]_2 P6.2
PWM0_1/PWM0_M_1_N/TC0_1_TR0/TC0_M_1_TR1/SCB4_CTS (0)/SCB4_SEL0 (0)/LIN4_RX/CAN0_2_RX/CAL_SUP_NZ/ADC[0]_3 P6.3
PWM0_M_2/PWM0_1_N/TC0_M_2_TR0/TC0_1_TR1/SCB4_SEL1 (0)/LIN4_TX/ADC[0]_4 P6.4
9
10
11
12
13
14
15
16
PWM0_2/PWM0_M_2_N/TC0_2_TR0/TC0_M_2_TR1/SCB4_SEL2 (0)/LIN4_EN/ADC[0]_5 P6.5
PWM0_M_3/PWM0_2_N/TC0_M_3_TR0/TC0_2_TR1/SCB4_SEL3 (0)/TRIG_IN[8]/ADC[0]_6 P6.6
VDDD
Figure 9-10
64-LQFP pin assignment with alternate functions
Datasheet
32
002-18043 Rev. *J
2022-09-08
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4F single
High-speed I/O matrix connections
10
High-speed I/O matrix connections
Table 10-1
HSIOM connections reference
Name
Number
0
Description
HSIOM_SEL_GPIO
HSIOM_SEL_GPIO_DSI
HSIOM_SEL_DSI_DSI
HSIOM_SEL_DSI_GPIO
HSIOM_SEL_AMUXA
HSIOM_SEL_AMUXB
HSIOM_SEL_AMUXA_DSI
HSIOM_SEL_AMUXB_DSI
HSIOM_SEL_ACT_0
HSIOM_SEL_ACT_1
HSIOM_SEL_ACT_2
HSIOM_SEL_ACT_3
HSIOM_SEL_DS_0
HSIOM_SEL_DS_1
HSIOM_SEL_DS_2
HSIOM_SEL_DS_3
HSIOM_SEL_ACT_4
HSIOM_SEL_ACT_5
HSIOM_SEL_ACT_6
HSIOM_SEL_ACT_7
HSIOM_SEL_ACT_8
HSIOM_SEL_ACT_9
HSIOM_SEL_ACT_10
HSIOM_SEL_ACT_11
HSIOM_SEL_ACT_12
HSIOM_SEL_ACT_13
HSIOM_SEL_ACT_14
HSIOM_SEL_ACT_15
HSIOM_SEL_DS_4
HSIOM_SEL_DS_5
HSIOM_SEL_DS_6
HSIOM_SEL_DS_7
GPIO controls 'out'
Reserved
1
2
3
4
5
6
7
8
Active functionality 0
Active functionality 1
Active functionality 2
Active functionality 3
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
DeepSleep functionality 0
DeepSleep functionality 1
DeepSleep functionality 2
DeepSleep functionality 3
Active functionality 4
Active functionality 5
Active functionality 6
Active functionality 7
Active functionality 8
Active functionality 9
Active functionality 10
Active functionality 11
Active functionality 12
Active functionality 13
Active functionality 14
Active functionality 15
DeepSleep functionality 4
DeepSleep functionality 5
DeepSleep functionality 6
DeepSleep functionality 7
Datasheet
33
002-18043 Rev. *J
2022-09-08
11
Package pin list and alternate functions
Most pins have alternate functionality, as specified in Table 11-1.
Port 11 has the following additional features,
• Ability to pass full-level analog signals to the SAR without clipping to VDDD in cases where VDDD < VDDA
• Ability to simultaneously capture all three ADC signals with highest priority (ADC[0:2]_M)
• Lower noise, for the most sensitive sensors
Table 11-1
Pin selector and alternate pin functions in DeepSleep (DS) Mode, Analog, Smart I/O[21, 22]
Package
DeepSleep Mapping[20]
Name
HCon#0[18]
176-LQFP
144-LQFP
100-LQFP
80-LQFP
64-LQFP
Pin
1
HCon#14
DS #0[19]
HCon#29
HCon#30
DS #2
Analog
SMARTIO
I/O Type
GPIO_ENH
GPIO_ENH
GPIO_ENH
GPIO_ENH
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
Pin
2
Pin
2
Pin
2
Pin
2
DS #1
P0.0
P0.1
P0.2
P0.3
P1.0
P1.1
P1.2
P1.3
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P3.0
P3.1
P3.2
SCB0_MISO (0)
SCB0_MOSI (0)
SCB0_CLK (0)
SCB0_SEL0 (0)
SCB0_MISO (1)
SCB0_MOSI (1)
SCB0_CLK (1)
SCB0_SEL0 (1)
SCB0_SEL1 (0)
SCB0_SEL2 (0)
SCB0_SEL3 (0)
3
3
3
3
2
4
4
4
4
3
SCB0_SCL (0)
SCB0_SDA (0)
SCB0_SCL (1)
SCB0_SDA (1)
5
5
5
5
4
6
6
NA
NA
NA
NA
6
NA
NA
NA
NA
6
NA
NA
NA
NA
5
7
7
8
NA
NA
8
9
10
11
12
13
14
15
16
17
18
SWJ_TRSTN
9
7
7
6
10
11
12
NA
13
14
15
8
8
NA
NA
NA
NA
NA
NA
NA
9
9
NA
NA
10
11
NA
NA
NA
NA
NA
NA
Notes
18.HCon refers to High Speed I/O matrix connection reference as per Table 10-1.
19.DeepSleep ordering (DS #0, DS #1, DS #2) does not have any impact on choosing any alternate functions; the HSIOM module handles the individual alternate function assignment.
20.All port pin functions available in DeepSleep mode are also available in Active mode.
21.Refer to Table 13-2 for more information on pin multiplexer abbreviations used.
22.For any function marked with an identifier (n), the AC timing is only guaranteed within the respective group "n".
Table 11-1
Pin selector and alternate pin functions in DeepSleep (DS) Mode, Analog, Smart I/O[21, 22] (continued)
Package
100-LQFP
Pin
NA
NA
NA
NA
NA
NA
NA
NA
14
DeepSleep Mapping[20]
Name
HCon#0[18]
176-LQFP
Pin
19
144-LQFP
Pin
16
80-LQFP
Pin
NA
NA
NA
NA
NA
NA
NA
NA
10
64-LQFP
Pin
NA
NA
NA
NA
NA
NA
NA
NA
7
HCon#14
DS #0[19]
HCon#29
HCon#30
DS #2
Analog
SMARTIO
I/O Type
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
DS #1
P3.3
P3.4
P3.5
P4.0
P4.1
P4.2
P4.3
P4.4
P5.0
P5.1
P5.2
P5.3
P5.4
P5.5
P6.0
P6.1
P6.2
P6.3
P6.4
P6.5
P6.6
P6.7
P7.0
P7.1
P7.2
P7.3
P7.4
P7.5
P7.6
P7.7
P8.0
20
17
21
NA
20
24
25
21
26
NA
NA
NA
22
27
28
29
30
23
15
11
8
31
24
16
12
NA
NA
NA
NA
9
32
25
17
13
33
26
NA
NA
18
NA
NA
14
34
NA
27
35
ADC[0]_0
ADC[0]_1
ADC[0]_2
ADC[0]_3
ADC[0]_4
ADC[0]_5
ADC[0]_6
ADC[0]_7
ADC[0]_8
ADC[0]_9
ADC[0]_10
ADC[0]_11
ADC[0]_12
ADC[0]_13
ADC[0]_14
ADC[0]_15
36
28
19
15
10
37
29
20
16
11
38
30
21
17
12
39
31
22
18
13
40
32
23
19
14
41
33
NA
NA
29
NA
NA
22
15
42
34
NA
18
48
40
49
41
30
23
19
50
42
31
24
20
51
43
32
25
NA
NA
NA
NA
NA
21
52
44
33
NA
NA
NA
NA
26
53
45
34
54
46
NA
NA
35
55
47
56
48
Table 11-1
Pin selector and alternate pin functions in DeepSleep (DS) Mode, Analog, Smart I/O[21, 22] (continued)
Package
100-LQFP
Pin
36
DeepSleep Mapping[20]
Name
HCon#0[18]
176-LQFP
Pin
57
144-LQFP
Pin
49
80-LQFP
Pin
27
64-LQFP
Pin
22
HCon#14
DS #0[19]
HCon#29
HCon#30
DS #2
Analog
SMARTIO
I/O Type
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
DS #1
P8.1
P8.2
ADC[0]_16
ADC[0]_17
ADC[0]_18
ADC[0]_19
ADC[0]_20
ADC[0]_21
ADC[0]_22
ADC[0]_23
58
50
37
28
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
23
P8.3
59
51
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
38
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
29
P8.4
60
NA
52
P9.0
61
P9.1
62
53
P9.2
63
NA
NA
54
P9.3
64
P10.0
P10.1
P10.2
P10.3
P10.4
P10.5
P10.6
P10.7
P11.0
P11.1
P11.2
P12.0
P12.1
P12.2
P12.3
P12.4
P12.5
P12.6
P12.7
P13.0
P13.1
P13.2
P13.3
65
66
55
67
56
68
57
69
58
ADC[1]_0
ADC[1]_1
ADC[1]_2
ADC[1]_3
ADC[0]_M
ADC[1]_M
ADC[2]_M
ADC[1]_4
ADC[1]_5
ADC[1]_6
ADC[1]_7
ADC[1]_8
ADC[1]_9
ADC[1]_10
ADC[1]_11
ADC[1]_12
ADC[1]_13
ADC[1]_14
ADC[1]_15
70
NA
NA
NA
59
71
72
73
74
60
39
30
24
75
61
40
31
25
80
66
45
36
30
SMARTIO12_0
SMARTIO12_1
SMARTIO12_2
SMARTIO12_3
SMARTIO12_4
SMARTIO12_5
SMARTIO12_6
SMARTIO12_7
SMARTIO13_0
SMARTIO13_1
SMARTIO13_2
SMARTIO13_3
81
67
46
37
31
82
68
47
38
NA
NA
NA
NA
NA
NA
34
83
69
48
39
84
70
49
NA
NA
NA
NA
42
85
71
NA
NA
NA
52
86
NA
NA
74
87
90
91
75
53
43
35
92
76
54
44
36
93
77
55
45
37
Table 11-1
Pin selector and alternate pin functions in DeepSleep (DS) Mode, Analog, Smart I/O[21, 22] (continued)
Package
100-LQFP
Pin
56
DeepSleep Mapping[20]
Name
HCon#0[18]
176-LQFP
Pin
94
144-LQFP
Pin
78
80-LQFP
Pin
46
64-LQFP
Pin
NA
NA
NA
NA
38
HCon#14
DS #0[19]
HCon#29
HCon#30
DS #2
Analog
SMARTIO
I/O Type
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
DS #1
P13.4
P13.5
P13.6
P13.7
P14.0
P14.1
P14.2
P14.3
P14.4
P14.5
P14.6
P14.7
P15.0
P15.1
P15.2
P15.3
P16.0
P16.1
P16.2
P16.3
P17.0
P17.1
P17.2
P17.3
P17.4
P17.5
P17.6
P17.7
P18.0
P18.1
P18.2
ADC[1]_16
ADC[1]_17
ADC[1]_18
ADC[1]_19
ADC[1]_20
ADC[1]_21
ADC[1]_22
ADC[1]_23
ADC[1]_24
ADC[1]_25
ADC[1]_26
ADC[1]_27
ADC[1]_28
ADC[1]_29
ADC[1]_30
ADC[1]_31
SMARTIO13_4
SMARTIO13_5
SMARTIO13_6
SMARTIO13_7
SMARTIO14_0
SMARTIO14_1
SMARTIO14_2
SMARTIO14_3
SMARTIO14_4
SMARTIO14_5
SMARTIO14_6
SMARTIO14_7
SMARTIO15_0
SMARTIO15_1
SMARTIO15_2
SMARTIO15_3
95
79
57
47
96
80
58
48
97
81
59
49
98
82
60
50
99
83
61
51
39
100
101
102
103
104
105
106
107
108
109
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
84
62
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
52
40
85
63
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
41
86
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
64
87
NA
NA
88
89
90
91
92
93
94
NA
95
SMARTIO17_0
SMARTIO17_1
SMARTIO17_2
SMARTIO17_3
SMARTIO17_4
SMARTIO17_5
SMARTIO17_6
SMARTIO17_7
96
65
97
66
98
NA
NA
NA
NA
NA
67
99
NA
NA
NA
100
101
102
ADC[2]_0
ADC[2]_1
ADC[2]_2
68
53
42
69
54
NA
Table 11-1
Pin selector and alternate pin functions in DeepSleep (DS) Mode, Analog, Smart I/O[21, 22] (continued)
Package
100-LQFP
Pin
70
DeepSleep Mapping[20]
Name
HCon#0[18]
176-LQFP
Pin
127
128
129
130
131
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
157
158
159
160
161
162
163
164
144-LQFP
Pin
103
104
105
106
107
110
111
112
113
114
115
116
117
118
NA
80-LQFP
Pin
55
64-LQFP
Pin
43
HCon#14
DS #0[19]
HCon#29
HCon#30
DS #2
Analog
SMARTIO
I/O Type
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
DS #1
P18.3
P18.4
P18.5
P18.6
P18.7
P19.0
P19.1
P19.2
P19.3
P19.4
P20.0
P20.1
P20.2
P20.3
P20.4
P20.5
P20.6
P20.7
P21.0
P21.1
P21.2
P21.3
P21.4[24]
P21.5
P21.6
P21.7
P22.0
P22.1
P22.2
P22.3
P22.4
ADC[2]_3
ADC[2]_4
ADC[2]_5
ADC[2]_6
ADC[2]_7
71
56
44
72
57
45
73
58
46
74
59
47
77
62
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
50
78
63
79
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
64
80
NA
NA
NA
NA
NA
NA
NA
NA
NA
81
NA
NA
NA
119
120
121
122
NA
WCO_IN[23]
WCO_OUT[23]
ECO_IN[23]
ECO_OUT[23]
82
65
51
83
66
52
84
67
53
NA
90
NA
NA
NA
NA
73
NA
NA
NA
NA
59
HIBERNATE_WAKEUP[0]
128
129
NA
NA
NA
91
RTC_CAL
130
131
132
133
134
92
74
NA
NA
NA
NA
93
NA
NA
NA
94
NA
Table 11-1
Pin selector and alternate pin functions in DeepSleep (DS) Mode, Analog, Smart I/O[21, 22] (continued)
Package
DeepSleep Mapping[20]
Name
HCon#0[18]
176-LQFP
Pin
144-LQFP
Pin
100-LQFP
Pin
NA
80-LQFP
Pin
NA
64-LQFP
Pin
NA
HCon#14
DS #0[19]
HCon#29
HCon#30
DS #2
Analog
SMARTIO
I/O Type
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
DS #1
P22.5
P22.6
P22.7
P23.0
P23.1
P23.2
P23.3
P23.4
P23.5
P23.6
P23.7
165
135
166
136
NA
NA
NA
167
NA
NA
NA
NA
168
137
NA
NA
NA
169
138
NA
NA
NA
170
NA
NA
NA
NA
171
139
95
75
60
172
140
96
76
61
SWJ_SWO_TDO
173
141
97
77
62
SWJ_SWCLK_TCLK
SWJ_SWDIO_TMS
SWJ_SWDOE_TDI
174
142
98
78
63
175
143
99
79
64
HIBERNATE_WAKEUP[1]
Notes
23.I/O pins that support an oscillator function (WCO or ECO) must be configured for high-impedance if the oscillator is enabled.
24.This I/O has increased leakage to ground when the VDDD supply is below the POR threshold.
12
Power pin assignments
Table 12-1
Power pin assignments
Package
Name
Remarks
Main digital supply
64-LQFP
80-LQFP
100-LQFP
144-LQFP
176-LQFP
55, 48, 16
80, 69, 60
100, 86, 75, 24, 12
144, 124, 108, 35, 18
176, 153, 132, 110, 43, 22
VDDD
57, 56, 49, 33, 17 71, 70, 61, 41, 21, 1 88, 87, 76, 51, 27, 26, 13, 1 126, 125, 109, 73, 38, 37, 19, 1 155, 154, 133, 111, 89, 46, 45, 23, 1 Main digital ground
VSSD
NA
32
58
20
40
72
25
36
44
VDDIO_1
I/O supply for analog I/Os (except analog
I/Os on V
)
DDA
50
72
88
VDDIO_2
VCCD[25]
I/O supply for analog I/Os (except analog
I/Os on V ), P11
DDA
89, 28
127, 39
156, 47
Main regulated supply. Driven by LDO
regulator (either internal LDO or external
LDO/PMIC)
29
26
28
27
54
35
32
34
33
68
44
41
43
42
85
65
62
79
76
High reference voltage for SAR ADCs
Low reference voltage for SAR ADCs
Main analog supply for SAR ADCs
Main analog ground
VREFH
VREFL
VDDA
VSSA
XRES_L
64
78
63
77
123
152
Active LOW external reset input
Note
25.The VCCD pins must be connected together to ensure a low-impedance connection. (see the requirement in Figure 26-2)
13
Table 13-1
Alternate function pin assignments
Alternate pin functions in Active Mode[28, 29]
Active Mapping
HCon#17
[26]
[27]
Name
HCon#8
HCon#9
HCon#10
HCon#11
HCon#16
ACT#4
HCon#18
ACT#6
HCon#19
ACT#7
HCon#20
HCon#21
ACT#9
HCon#26
ACT#14
HCon#27
ACT#15
ACT#0
ACT#1
ACT#2
ACT#3
ACT#5
ACT#8
P0.0
P0.1
P0.2
P0.3
P1.0
P1.1
P1.2
P1.3
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P4.0
P4.1
P4.2
P4.3
PWM0_18
PWM0_22_N
TC0_18_TR0
TC0_22_TR1
SCB0_RX (0)
SCB0_TX (0)
SCB0_RTS (0)
SCB0_CTS (0)
SCB7_SDA (2)
SCB7_SCL (2)
LIN1_RX
PWM0_17
PWM0_14
PWM0_13
PWM0_12
PWM0_11
PWM0_10
PWM0_8
PWM0_7
PWM0_6
PWM0_5
PWM0_4
PWM0_3
PWM0_2
PWM0_1
PWM0_0
PWM0_18_N
PWM0_17_N
PWM0_14_N
PWM0_13_N
PWM0_12_N
PWM0_11_N
PWM0_10_N
PWM0_8_N
PWM0_7_N
PWM0_6_N
PWM0_5_N
PWM0_4_N
PWM0_3_N
PWM0_2_N
PWM0_1_N
PWM0_0_N
PWM0_M_3_N
PWM0_M_2_N
PWM0_M_1_N
PWM0_M_0_N
PWM0_4_N
PWM0_5_N
PWM0_6_N
TC0_17_TR0
TC0_14_TR0
TC0_13_TR0
TC0_12_TR0
TC0_11_TR0
TC0_10_TR0
TC0_8_TR0
TC0_7_TR0
TC0_6_TR0
TC0_5_TR0
TC0_4_TR0
TC0_3_TR0
TC0_2_TR0
TC0_1_TR0
TC0_0_TR0
TC0_M_3_TR0
TC0_M_2_TR0
TC0_M_1_TR0
TC0_M_0_TR0
TC0_4_TR0
TC0_5_TR0
TC0_6_TR0
TC0_7_TR0
TC0_18_TR1
TC0_17_TR1
TC0_14_TR1
TC0_13_TR1
TC0_12_TR1
TC0_11_TR1
TC0_10_TR1
TC0_8_TR1
TC0_7_TR1
TC0_6_TR1
TC0_5_TR1
TC0_4_TR1
TC0_3_TR1
TC0_2_TR1
TC0_1_TR1
TC0_0_TR1
TC0_M_3_TR1
TC0_M_2_TR1
TC0_M_1_TR1
TC0_M_0_TR1
TC0_4_TR1
TC0_5_TR1
TC0_6_TR1
LIN1_TX
LIN1_EN
CAN0_1_TX
CAN0_1_RX
TRIG_IN[0]
TRIG_IN[1]
TRIG_IN[2]
TRIG_IN[3]
TRIG_IN[4]
TRIG_IN[5]
TRIG_IN[6]
TRIG_IN[7]
SCB7_RX (0)
SCB7_TX (0)
SCB7_RTS (0)
SCB7_CTS (0)
SCB7_MISO (0)
SCB7_MOSI (0)
SCB7_CLK (0)
SCB7_SEL0 (0)
SCB7_SEL1 (0)
SCB7_SEL2 (0)
SCB6_MISO (0)
SCB6_MOSI (0)
SCB6_CLK (0)
SCB6_SEL0 (0)
SCB6_SEL1 (0)
SCB6_SEL2 (0)
SCB5_MISO (0)
SCB5_MOSI (0)
SCB5_CLK (0)
SCB5_SEL0 (0)
LIN0_RX
LIN0_TX
LIN0_EN
LIN5_RX
LIN5_TX
LIN5_EN
CAN0_0_TX
CAN0_0_RX
SCB7_SDA (0)
SCB7_SCL (0)
SCB6_RX (0)
SCB6_TX (0)
SCB6_RTS (0)
SCB6_CTS (0)
TRIG_DBG[0]
TRIG_DBG[1]
SCB6_SDA (0)
SCB6_SCL (0)
PWM0_M_3
PWM0_M_2
PWM0_M_1
PWM0_M_0
PWM0_4
EXT_MUX[0]_0
EXT_MUX[0]_1
EXT_MUX[0]_2
EXT_MUX[0]_EN
SCB5_RX (0)
SCB5_TX (0)
SCB5_RTS (0)
SCB5_CTS (0)
LIN1_RX
LIN1_TX
LIN1_EN
TRIG_IN[10]
TRIG_IN[11]
TRIG_IN[12]
TRIG_IN[13]
PWM0_5
SCB5_SDA (0)
SCB5_SCL (0)
PWM0_6
PWM0_7
CAN0_1_TX
Notes
26.High Speed I/O matrix connection (HCon) reference as per Table 10-1.
27.Active Mode ordering (ACT#0, ACT#1, and so on) does not have any impact on configuring alternate functions; the HSIOM module handles the alternate function assignments.
28.Refer to Table 13-2 for more information on pin multiplexer abbreviations used.
29.For any function marked with an identifier (n), the AC timing is only guaranteed within the respective group "n".
Table 13-1
Alternate pin functions in Active Mode[28, 29]
Active Mapping
HCon#17
[26]
[27]
Name
HCon#8
HCon#9
HCon#10
ACT#2
HCon#11
ACT#3
HCon#16
ACT#4
HCon#18
ACT#6
HCon#19
HCon#20
ACT#8
HCon#21
HCon#26
ACT#14
HCon#27
ACT#15
ACT#0
PWM0_8
ACT#1
ACT#5
ACT#7
ACT#9
P4.4
P5.0
P5.1
P5.2
P5.3
P5.4
P5.5
P6.0
P6.1
P6.2
P6.3
P6.4
P6.5
P6.6
P6.7
P7.0
P7.1
P7.2
P7.3
P7.4
P7.5
P7.6
P7.7
P8.0
P8.1
P8.2
P8.3
P8.4
P9.0
P9.1
P9.2
PWM0_7_N
TC0_8_TR0
TC0_7_TR1
SCB5_SEL1 (0)
CAN0_1_RX
PWM0_9
PWM0_8_N
TC0_9_TR0
TC0_8_TR1
SCB5_SEL2 (0)
LIN7_RX
LIN7_TX
LIN7_EN
LIN2_RX
LIN2_TX
LIN2_EN
LIN3_RX
LIN3_TX
LIN3_EN
LIN4_RX
LIN4_TX
LIN4_EN
PWM0_10
PWM0_11
PWM0_12
PWM0_13
PWM0_14
PWM0_9_N
TC0_10_TR0
TC0_11_TR0
TC0_12_TR0
TC0_13_TR0
TC0_14_TR0
TC0_M_0_TR0
TC0_0_TR0
TC0_9_TR1
PWM0_10_N
PWM0_11_N
PWM0_12_N
PWM0_13_N
PWM0_14_N
PWM0_M_0_N
PWM0_0_N
TC0_10_TR1
TC0_11_TR1
TC0_12_TR1
TC0_13_TR1
TC0_14_TR1
TC0_M_0_TR1
TC0_0_TR1
PWM0_M_0
PWM0_0
SCB4_RX (0)
SCB4_TX (0)
SCB4_RTS (0)
SCB4_CTS (0)
SCB4_MISO (0)
SCB4_MOSI (0)
SCB4_CLK (0)
SCB4_SEL0 (0)
SCB4_SEL1 (0)
SCB4_SEL2 (0)
SCB4_SEL3 (0)
SCB4_SDA (0)
SCB4_SCL (0)
PWM0_M_1
PWM0_1
TC0_M_1_TR0
TC0_1_TR0
CAN0_2_TX
CAN0_2_RX
PWM0_M_1_N
PWM0_1_N
TC0_M_1_TR1
TC0_1_TR1
CAL_SUP_NZ
PWM0_M_2
PWM0_2
TC0_M_2_TR0
TC0_2_TR0
PWM0_M_2_N
PWM0_2_N
TC0_M_2_TR1
TC0_2_TR1
PWM0_M_3
PWM0_3
TC0_M_3_TR0
TC0_3_TR0
TRIG_IN[8]
TRIG_IN[9]
PWM0_M_3_N
PWM0_3_N
TC0_M_3_TR1
TC0_3_TR1
PWM0_M_4
PWM0_15
PWM0_M_5
PWM0_16
PWM0_M_6
PWM0_17
PWM0_M_7
PWM0_18
PWM0_19
PWM0_20
PWM0_21
PWM0_22
PWM0_23
PWM0_24
PWM0_25
PWM0_26
TC0_M_4_TR0
TC0_15_TR0
TC0_M_5_TR0
TC0_16_TR0
TC0_M_6_TR0
TC0_17_TR0
TC0_M_7_TR0
TC0_18_TR0
TC0_19_TR0
TC0_20_TR0
TC0_21_TR0
TC0_22_TR0
TC0_23_TR0
TC0_24_TR0
TC0_25_TR0
TC0_26_TR0
SCB5_RX (1)
SCB5_TX (1)
SCB5_RTS (1)
SCB5_CTS (1)
SCB5_MISO (1)
SCB5_MOSI (1)
SCB5_CLK (1)
SCB5_SEL0 (1)
SCB5_SEL1 (1)
SCB5_SEL2 (1)
LIN4_RX
LIN4_TX
LIN4_EN
PWM0_M_4_N
PWM0_15_N
PWM0_M_5_N
PWM0_16_N
PWM0_M_6_N
PWM0_17_N
PWM0_M_7_N
PWM0_18_N
PWM0_19_N
PWM0_20_N
PWM0_21_N
PWM0_22_N
PWM0_23_N
PWM0_24_N
PWM0_25_N
TC0_M_4_TR1
TC0_15_TR1
TC0_M_5_TR1
TC0_16_TR1
TC0_M_6_TR1
TC0_17_TR1
TC0_M_7_TR1
TC0_18_TR1
TC0_19_TR1
TC0_20_TR1
TC0_21_TR1
TC0_22_TR1
TC0_23_TR1
TC0_24_TR1
TC0_25_TR1
SCB5_SDA (1)
SCB5_SCL (1)
TRIG_IN[16]
TRIG_IN[17]
LIN2_RX
LIN2_TX
LIN2_EN
CAN0_0_TX
CAN0_0_RX
TRIG_IN[14]
TRIG_IN[15]
TRIG_DBG[0]
TRIG_DBG[1]
Table 13-1
Alternate pin functions in Active Mode[28, 29]
Active Mapping
HCon#17
[26]
[27]
Name
HCon#8
HCon#9
HCon#10
HCon#11
HCon#16
ACT#4
HCon#18
ACT#6
HCon#19
ACT#7
HCon#20
ACT#8
HCon#21
ACT#9
HCon#26
ACT#14
HCon#27
ACT#15
ACT#0
ACT#1
ACT#2
ACT#3
ACT#5
P9.3
PWM0_27
PWM0_26_N
TC0_27_TR0
TC0_26_TR1
P10.0 PWM0_28
P10.1 PWM0_29
P10.2 PWM0_30
P10.3 PWM0_31
P10.4 PWM0_32
P10.5 PWM0_33
P10.6 PWM0_34
P10.7 PWM0_35
P11.0
PWM0_27_N
PWM0_28_N
PWM0_29_N
PWM0_30_N
PWM0_31_N
PWM0_32_N
PWM0_33_N
PWM0_34_N
TC0_28_TR0
TC0_29_TR0
TC0_30_TR0
TC0_31_TR0
TC0_32_TR0
TC0_33_TR0
TC0_34_TR0
TC0_35_TR0
TC0_27_TR1
TC0_28_TR1
TC0_29_TR1
TC0_30_TR1
TC0_31_TR1
TC0_32_TR1
TC0_33_TR1
TC0_34_TR1
SCB4_RX (1)
SCB4_TX (1)
SCB4_RTS (1)
SCB4_CTS (1)
SCB4_MISO (1)
SCB4_MOSI (1)
SCB4_CLK (1)
SCB4_SEL0 (1)
SCB4_SEL1 (1)
SCB4_SEL2 (1)
TRIG_IN[18]
TRIG_IN[19]
SCB4_SDA (1)
SCB4_SCL (1)
P11.1
P11.2
P12.0 PWM0_36
P12.1 PWM0_37
P12.2 PWM0_38
P12.3 PWM0_39
P12.4 PWM0_40
P12.5 PWM0_41
P12.6 PWM0_42
P12.7 PWM0_43
PWM0_35_N
PWM0_36_N
PWM0_37_N
PWM0_38_N
PWM0_39_N
PWM0_40_N
PWM0_41_N
PWM0_42_N
PWM0_43_N
PWM0_M_8_N
PWM0_44_N
PWM0_M_9_N
PWM0_45_N
PWM0_M_10_N
PWM0_46_N
PWM0_M_11_N
PWM0_47_N
PWM0_48_N
PWM0_49_N
TC0_36_TR0
TC0_37_TR0
TC0_38_TR0
TC0_39_TR0
TC0_40_TR0
TC0_41_TR0
TC0_42_TR0
TC0_43_TR0
TC0_M_8_TR0
TC0_44_TR0
TC0_M_9_TR0
TC0_45_TR0
TC0_M_10_TR0
TC0_46_TR0
TC0_M_11_TR0
TC0_47_TR0
TC0_48_TR0
TC0_49_TR0
TC0_50_TR0
TC0_35_TR1
TC0_36_TR1
TC0_37_TR1
TC0_38_TR1
TC0_39_TR1
TC0_40_TR1
TC0_41_TR1
TC0_42_TR1
TC0_43_TR1
TC0_M_8_TR1
TC0_44_TR1
TC0_M_9_TR1
TC0_45_TR1
TC0_M_10_TR1
TC0_46_TR1
TC0_M_11_TR1
TC0_47_TR1
TC0_48_TR1
TC0_49_TR1
CAN0_2_TX
CAN0_2_RX
TRIG_IN[20]
TRIG_IN[21]
LIN6_EN
LIN6_RX
LIN6_TX
EXT_MUX[1]_EN
EXT_MUX[1]_0
EXT_MUX[1]_1
EXT_MUX[1]_2
P13.0 PWM0_M_8
P13.1 PWM0_44
P13.2 PWM0_M_9
P13.3 PWM0_45
P13.4 PWM0_M_10
P13.5 PWM0_46
P13.6 PWM0_M_11
P13.7 PWM0_47
P14.0 PWM0_48
P14.1 PWM0_49
P14.2 PWM0_50
EXT_MUX[2]_0
EXT_MUX[2]_1
EXT_MUX[2]_2
EXT_MUX[2]_EN
SCB3_RX (0)
SCB3_TX (0)
SCB3_RTS (0)
SCB3_CTS (0)
SCB3_MISO (0)
SCB3_MOSI (0)
SCB3_CLK (0)
SCB3_SEL0 (0)
SCB3_SEL1 (0)
SCB3_SEL2 (0)
SCB3_SEL3 (0)
SCB3_SDA (0)
SCB3_SCL (0)
TRIG_IN[22]
TRIG_IN[23]
SCB2_RX (0)
SCB2_TX (0)
SCB2_RTS (0)
SCB2_MISO (0)
SCB2_MOSI (0)
SCB2_CLK (0)
CAN1_0_TX
CAN1_0_RX
SCB2_SDA (0)
SCB2_SCL (0)
LIN6_RX
Table 13-1
Alternate pin functions in Active Mode[28, 29]
Active Mapping
HCon#17
[26]
[27]
Name
HCon#8
HCon#9
HCon#10
HCon#11
HCon#16
ACT#4
HCon#18
ACT#6
HCon#19
HCon#20
HCon#21
ACT#9
HCon#26
ACT#14
HCon#27
ACT#15
ACT#0
ACT#1
ACT#2
ACT#3
ACT#5
ACT#7
ACT#8
P14.3 PWM0_51
P14.4 PWM0_52
P14.5 PWM0_53
P14.6 PWM0_54
P14.7 PWM0_55
P15.0 PWM0_56
P15.1 PWM0_57
P15.2 PWM0_58
P15.3 PWM0_59
P16.0 PWM0_60
P16.1 PWM0_61
P16.2 PWM0_62
P16.3 PWM0_62
P17.0 PWM0_61
P17.1 PWM0_60
P17.2 PWM0_59
P17.3 PWM0_58
P17.4 PWM0_57
P17.5 PWM0_56
PWM0_50_N
TC0_51_TR0
TC0_50_TR1
SCB2_CTS (0)
SCB2_SEL0 (0)
LIN6_TX
PWM0_51_N
PWM0_52_N
PWM0_53_N
PWM0_54_N
PWM0_55_N
PWM0_56_N
PWM0_57_N
PWM0_58_N
PWM0_59_N
PWM0_60_N
PWM0_61_N
PWM0_62_N
PWM0_62_N
PWM0_61_N
PWM0_60_N
PWM0_59_N
PWM0_58_N
PWM0_57_N
PWM0_56_N
PWM0_M_4_N
PWM0_M_5_N
PWM0_M_6_N
PWM0_M_7_N
PWM0_55_N
PWM0_54_N
PWM0_53_N
PWM0_52_N
PWM0_51_N
PWM0_50_N
PWM0_M_3_N
TC0_52_TR0
TC0_53_TR0
TC0_54_TR0
TC0_55_TR0
TC0_56_TR0
TC0_57_TR0
TC0_58_TR0
TC0_59_TR0
TC0_60_TR0
TC0_61_TR0
TC0_62_TR0
TC0_62_TR0
TC0_61_TR0
TC0_60_TR0
TC0_59_TR0
TC0_58_TR0
TC0_57_TR0
TC0_56_TR0
TC0_M_4_TR0
TC0_M_5_TR0
TC0_M_6_TR0
TC0_M_7_TR0
TC0_55_TR0
TC0_54_TR0
TC0_53_TR0
TC0_52_TR0
TC0_51_TR0
TC0_50_TR0
TC0_M_3_TR0
TC0_26_TR0
TC0_51_TR1
TC0_52_TR1
TC0_53_TR1
TC0_54_TR1
TC0_55_TR1
TC0_56_TR1
TC0_57_TR1
TC0_58_TR1
TC0_59_TR1
TC0_60_TR1
TC0_61_TR1
TC0_62_TR1
TC0_62_TR1
TC0_61_TR1
TC0_60_TR1
TC0_59_TR1
TC0_58_TR1
TC0_57_TR1
TC0_56_TR1
TC0_M_4_TR1
TC0_M_5_TR1
TC0_M_6_TR1
TC0_M_7_TR1
TC0_55_TR1
TC0_54_TR1
TC0_53_TR1
TC0_52_TR1
TC0_51_TR1
TC0_50_TR1
TC0_M_3_TR1
SCB2_SEL1 (0)
SCB2_SEL2 (0)
LIN6_EN
TRIG_IN[24]
TRIG_IN[25]
PWM0_H_0
PWM0_H_0_N
PWM0_H_1
PWM0_H_1_N
CAN1_1_TX
CAN1_1_RX
PWM0_H_2
SCB3_RX (1)
SCB3_TX (1)
SCB3_RTS (1)
SCB3_CTS (1)
SCB3_MISO (1)
SCB3_MOSI (1)
SCB3_CLK (1)
SCB3_SEL0 (1)
SCB3_SEL1 (1)
SCB3_SEL2 (1)
PWM0_H_2_N
PWM0_H_3
SCB3_SDA (1)
SCB3_SCL (1)
TRIG_IN[26]
TRIG_IN[27]
PWM0_H_3_N
P17.6 PWM0_M_4
P17.7 PWM0_M_5
P18.0 PWM0_M_6
P18.1 PWM0_M_7
P18.2 PWM0_55
P18.3 PWM0_54
P18.4 PWM0_53
P18.5 PWM0_52
P18.6 PWM0_51
P18.7 PWM0_50
P19.0 PWM0_M_3
P19.1 PWM0_26
PWM0_H_0
SCB1_RX (0)
SCB1_TX (0)
SCB1_RTS (0)
SCB1_CTS (0)
SCB1_MISO (0)
SCB1_MOSI (0)
SCB1_CLK (0)
SCB1_SEL0 (0)
SCB1_SEL1 (0)
SCB1_SEL2 (0)
SCB1_SEL3 (0)
FAULT_OUT_0
FAULT_OUT_1
PWM0_H_0_N
PWM0_H_1
SCB1_SDA (0)
SCB1_SCL (0)
PWM0_H_1_N
PWM0_H_2
TRACE_CLOCK (0)
TRACE_DATA_0 (0)
TRACE_DATA_1 (0)
TRACE_DATA_2 (0)
TRACE_DATA_3 (0)
FAULT_OUT_2
PWM0_H_2_N
PWM0_H_3
CAN1_2_TX
CAN1_2_RX
PWM0_H_3_N
TC0_H_0_TR0
TC0_H_0_TR1
SCB2_RX (1)
SCB2_TX (1)
SCB2_MISO (1)
SCB2_MOSI (1)
SCB2_SDA (1)
FAULT_OUT_3
Table 13-1
Alternate pin functions in Active Mode[28, 29]
Active Mapping
HCon#17
[26]
[27]
Name
HCon#8
HCon#9
HCon#10
HCon#11
HCon#16
HCon#18
ACT#6
HCon#19
HCon#20
ACT#8
HCon#21
ACT#9
HCon#26
HCon#27
ACT#15
ACT#0
ACT#1
ACT#2
ACT#3
ACT#4
ACT#5
ACT#7
ACT#14
P19.2 PWM0_27
P19.3 PWM0_28
P19.4 PWM0_29
P20.0 PWM0_30
P20.1 PWM0_49
P20.2 PWM0_48
P20.3 PWM0_47
P20.4 PWM0_46
P20.5 PWM0_45
P20.6 PWM0_44
P20.7 PWM0_43
P21.0 PWM0_42
P21.1 PWM0_41
P21.2 PWM0_40
P21.3 PWM0_39
P21.4 PWM0_38
P21.5 PWM0_37
P21.6 PWM0_36
P21.7 PWM0_35
P22.0 PWM0_34
P22.1 PWM0_33
P22.2 PWM0_32
P22.3 PWM0_31
P22.4 PWM0_30
P22.5 PWM0_29
P22.6 PWM0_28
P22.7 PWM0_27
PWM0_26_N
TC0_27_TR0
TC0_26_TR1
TC0_H_1_TR0
SCB2_RTS (1)
SCB2_CTS (1)
SCB2_SCL (1)
SCB2_CLK (1)
TRIG_IN[28]
PWM0_27_N
PWM0_28_N
PWM0_29_N
PWM0_30_N
PWM0_49_N
PWM0_48_N
PWM0_47_N
PWM0_46_N
PWM0_45_N
PWM0_44_N
PWM0_43_N
PWM0_42_N
PWM0_41_N
PWM0_40_N
PWM0_39_N
PWM0_38_N
PWM0_37_N
PWM0_36_N
PWM0_35_N
PWM0_34_N
PWM0_33_N
PWM0_32_N
PWM0_31_N
PWM0_30_N
PWM0_29_N
PWM0_28_N
PWM0_27_N
PWM0_M_8_N
PWM0_M_9_N
PWM0_M_10_N
TC0_28_TR0
TC0_29_TR0
TC0_30_TR0
TC0_49_TR0
TC0_48_TR0
TC0_47_TR0
TC0_46_TR0
TC0_45_TR0
TC0_44_TR0
TC0_43_TR0
TC0_42_TR0
TC0_41_TR0
TC0_40_TR0
TC0_39_TR0
TC0_38_TR0
TC0_37_TR0
TC0_36_TR0
TC0_35_TR0
TC0_34_TR0
TC0_33_TR0
TC0_32_TR0
TC0_31_TR0
TC0_30_TR0
TC0_29_TR0
TC0_28_TR0
TC0_27_TR0
TC0_M_8_TR0
TC0_M_9_TR0
TC0_M_10_TR0
TC0_M_11_TR0
TC0_27_TR1
TC0_28_TR1
TC0_29_TR1
TC0_30_TR1
TC0_49_TR1
TC0_48_TR1
TC0_47_TR1
TC0_46_TR1
TC0_45_TR1
TC0_44_TR1
TC0_43_TR1
TC0_42_TR1
TC0_41_TR1
TC0_40_TR1
TC0_39_TR1
TC0_38_TR1
TC0_37_TR1
TC0_36_TR1
TC0_35_TR1
TC0_34_TR1
TC0_33_TR1
TC0_32_TR1
TC0_31_TR1
TC0_30_TR1
TC0_29_TR1
TC0_28_TR1
TC0_27_TR1
TC0_M_8_TR1
TC0_M_9_TR1
TC0_M_10_TR1
TC0_H_1_TR1
TC0_H_2_TR0
TC0_H_2_TR1
TC0_H_3_TR0
TC0_H_3_TR1
SCB2_SEL0 (1)
SCB2_SEL1 (1)
SCB2_SEL2 (1)
TRIG_IN[29]
LIN5_RX
LIN5_TX
LIN5_EN
SCB1_RX (1)
SCB1_TX (1)
SCB1_RTS (1)
SCB1_CTS (1)
SCB1_MISO (1)
SCB1_MOSI (1)
SCB1_CLK (1)
SCB1_SEL0 (1)
SCB1_SEL1 (1)
SCB1_SEL2 (1)
CAN1_2_TX
CAN1_2_RX
SCB1_SDA (1)
SCB1_SCL (1)
EXT_CLK
TRIG_DBG[1]
LIN0_RX
LIN0_TX
LIN0_EN
CAL_SUP_NZ
SCB6_RX (1)
SCB6_TX (1)
SCB6_RTS (1)
SCB6_CTS (1)
SCB6_MISO (1)
SCB6_MOSI (1)
SCB6_CLK (1)
SCB6_SEL0 (1)
SCB6_SEL1 (1)
SCB6_SEL2 (1)
CAN1_1_TX
CAN1_1_RX
TRACE_DATA_0 (1)
TRACE_DATA_1 (1)
TRACE_DATA_2 (1)
TRACE_DATA_3 (1)
TRACE_CLOCK (1)
SCB6_SDA (1)
SCB6_SCL (1)
LIN7_RX
LIN7_TX
LIN7_EN
P23.0 PWM0_M_8
P23.1 PWM0_M_9
P23.2 PWM0_M_10
P23.3 PWM0_M_11
SCB7_RX (1)
SCB7_TX (1)
SCB7_RTS (1)
SCB7_CTS (1)
SCB7_MISO (1)
SCB7_MOSI (1)
SCB7_CLK (1)
SCB7_SEL0 (1)
CAN1_0_TX
CAN1_0_RX
FAULT_OUT_0
FAULT_OUT_1
FAULT_OUT_2
FAULT_OUT_3
SCB7_SDA (1)
SCB7_SCL (1)
TRIG_IN[30]
Table 13-1
Alternate pin functions in Active Mode[28, 29]
Active Mapping
HCon#17
[26]
[27]
Name
HCon#8
HCon#9
HCon#10
HCon#11
HCon#16
ACT#4
HCon#18
ACT#6
HCon#19
HCon#20
ACT#8
HCon#21
ACT#9
HCon#26
HCon#27
ACT#15
ACT#0
ACT#1
ACT#2
ACT#3
ACT#5
ACT#7
ACT#14
P23.4 PWM0_25
P23.5 PWM0_24
P23.6 PWM0_23
P23.7 PWM0_22
PWM0_M_11_N
TC0_25_TR0
TC0_M_11_TR1
SCB7_SEL1 (1)
TRIG_IN[31]
TRIG_DBG[0]
PWM0_25_N
PWM0_24_N
PWM0_23_N
TC0_24_TR0
TC0_23_TR0
TC0_22_TR0
TC0_25_TR1
TC0_24_TR1
TC0_23_TR1
SCB7_SEL2 (1)
EXT_CLK
CAL_SUP_NZ
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4F single
Alternate function pin assignments
Table 13-2
Sl. No.
Pin Mux descriptions
Pin
Module
Description
1
PWMx_y
TCPWM
TCPWM 16-bit PWM (no motor control), PWM_DT and PWM_PR
line out, x-TCPWM block, y-counter number
2
PWMx_y_N
TCPWM
TCPWM 16-bit PWM (no motor control), PWM_DT and PWM_PR
complementary line out (N), x-TCPWM block, y-counter
number
3
4
5
6
7
8
9
PWMx_M_y
TCPWM
TCPWM
TCPWM
TCPWM
TCPWM
TCPWM
TCPWM
TCPWM 16-bit PWM with motor control line out, x-TCPWM
block, y-counter number
TCPWM 16-bit PWM with motor control complementary line
out (N), x-TCPWM block, y-counter number
TCPWM 32-bit PWM, PWM_DT and PWM_PR line out, x-TCPWM
block, y-counter number
TCPWM 32-bit PWM, PWM_DT and PWM_PR complementary
line out (N), x-TCPWM block, y-counter number
TCPWM 16-bit dedicated counter input triggers, x-TCPWM
block, y-counter number, z-trigger number
TCPWM 16-bit dedicated counter input triggers with motor
control, x-TCPWM block, y-counter number, z-trigger number
TCPWM 32-bit dedicated counter input triggers, x-TCPWM
block, y-counter number, z-trigger number
PWMx_M_y_N
PWMx_H_y
PWMx_H_y_N
TCx_y_TRz
TCx_M_y_TRz
TCx_H_y_TRz
10 SCBx_RX
SCB
UART Receive, x-SCB block
11 SCBx_TX
SCB
UART Transmit, x-SCB block
12 SCBx_RTS
13 SCBx_CTS
14 SCBx_SDA
15 SCBx_SCL
16 SCBx_MISO
17 SCBx_MOSI
18 SCBx_CLK
19 SCBx_SELy
20 LINx_RX
SCB
SCB
SCB
SCB
SCB
SCB
SCB
SCB
UART Request to Send (Handshake), x-SCB block
UART Clear to Send (Handshake), x-SCB block
I2C Data line, x-SCB block
I2C Clock line, x-SCB block
SPI Master Input Slave Output, x-SCB block
SPI Master Output Slave Input, x-SCB block
SPI Serial Clock, x-SCB block
SPI Slave Select, x-SCB block, y-select line
LIN Receive line, x-LIN block
LIN
21 LINx_TX
LIN
LIN Transmit line, x-LIN block
22 LINx_EN
LIN
LIN Enable line, x-LIN block
23 CANx_y_TX
24 CANx_y_RX
25 CAL_SUP_NZ
26 FAULT_OUT_x
27 TRACE_DATA_x
28 TRACE_CLOCK
29 RTC_CAL
30 SWJ_TRSTN
31 SWJ_SWO_TDO
32 SWJ_SWCLK_TCLK
CANFD
CANFD
CPUSS
SRSS
SRSS
SRSS
SRSS RTC
SRSS
SRSS
SRSS
CAN Transmit line, x-CAN block, y-channel number
CAN Receive line, x-CAN block, y-channel number
ETAS Calibration support line
Fault output line x-0 to 3
Trace dataout line x-0 to 3
Trace clock line
RTC calibration clock input
JTAG Test reset line (Active low)
JTAG Test data output/SWO (Serial Wire Output)
JTAG Test clock/SWD clock (Serial Wire Clock)
Datasheet
47
002-18043 Rev. *J
2022-09-08
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4F single
Alternate function pin assignments
Table 13-2
Sl. No.
Pin Mux descriptions (continued)
Pin Module
SRSS
Description
33 SWJ_SWDIO_TMS
JTAG Test mode select/SWD data (Serial Wire Data
Input/Output)
34 SWJ_SWDOE_TDI
SRSS
JTAG Test data input
35 HIBERNATE_WAKEUP[x] SRSS
Hibernate wakeup line x-0 to 1
36 ADC[x]_y
37 ADC[x]_M
38 EXT_MUX[x]_y
39 EXT_MUX[x]_EN
PASS SAR
SAR, channel, x-SAR number, y-channel number
SAR motor control input, x-SAR number
External SAR MUX inputs, x-MUX number, y-MUX input 0 to 2
External SAR MUX enable line
PASS SAR
PASS SAR
PASS SAR
Datasheet
48
002-18043 Rev. *J
2022-09-08
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4F single
Interrupts and wake-up assignments
14
Interrupts and wake-up assignments
Table 14-1
Peripheral interrupt assignments and wake-up sources
Interrupt
Source
Power Mode
Description
0
1
2
3
4
5
6
7
8
cpuss_interrupts_ipc_0_IRQn
cpuss_interrupts_ipc_1_IRQn
cpuss_interrupts_ipc_2_IRQn
cpuss_interrupts_ipc_3_IRQn
cpuss_interrupts_ipc_4_IRQn
cpuss_interrupts_ipc_5_IRQn
cpuss_interrupts_ipc_6_IRQn
cpuss_interrupts_ipc_7_IRQn
cpuss_interrupts_fault_0_IRQn
cpuss_interrupts_fault_1_IRQn
cpuss_interrupts_fault_2_IRQn
cpuss_interrupts_fault_3_IRQn
srss_interrupt_backup_IRQn
srss_interrupt_mcwdt_0_IRQn
srss_interrupt_mcwdt_1_IRQn
srss_interrupt_wdt_IRQn
DeepSleep CPUSS Inter Process Communication Interrupt #0
DeepSleep CPUSS Inter Process Communication Interrupt #1
DeepSleep CPUSS Inter Process Communication Interrupt #2
DeepSleep CPUSS Inter Process Communication Interrupt #3
DeepSleep CPUSS Inter Process Communication Interrupt #4
DeepSleep CPUSS Inter Process Communication Interrupt #5
DeepSleep CPUSS Inter Process Communication Interrupt #6
DeepSleep CPUSS Inter Process Communication Interrupt #7
DeepSleep CPUSS Fault Structure #0 Interrupt
DeepSleep CPUSS Fault Structure #1 Interrupt
DeepSleep CPUSS Fault Structure #2 Interrupt
DeepSleep CPUSS Fault Structure #3 Interrupt
DeepSleep BACKUP domain Interrupt
9
10
11
12
13
14
15
16
17
18
19
DeepSleep Multi Counter Watchdog Timer #0 interrupt
DeepSleep Multi Counter Watchdog Timer #1 interrupt
DeepSleep Hardware Watchdog Timer interrupt
DeepSleep Other combined Interrupts for SRSS (LVD, CLKCAL)
DeepSleep SCB0 interrupt (DeepSleep capable)
srss_interrupt_IRQn
scb_0_interrupt_IRQn
evtgen_0_interrupt_dpslp_IRQn
ioss_interrupt_vdd_IRQn
DeepSleep Event gen DeepSleep domain interrupt
DeepSleep I/O Supply (VDDIO, VDDA, VDDD) state change Interrupt
ioss_interrupt_gpio_IRQn
Consolidated Interrupt for GPIO_STD and
20
DeepSleep
GPIO_ENH, All Ports
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
ioss_interrupts_gpio_0_IRQn
ioss_interrupts_gpio_1_IRQn
ioss_interrupts_gpio_2_IRQn
ioss_interrupts_gpio_3_IRQn
ioss_interrupts_gpio_4_IRQn
ioss_interrupts_gpio_5_IRQn
ioss_interrupts_gpio_6_IRQn
ioss_interrupts_gpio_7_IRQn
ioss_interrupts_gpio_8_IRQn
ioss_interrupts_gpio_9_IRQn
ioss_interrupts_gpio_10_IRQn
ioss_interrupts_gpio_11_IRQn
ioss_interrupts_gpio_12_IRQn
ioss_interrupts_gpio_13_IRQn
ioss_interrupts_gpio_14_IRQn
ioss_interrupts_gpio_15_IRQn
ioss_interrupts_gpio_16_IRQn
ioss_interrupts_gpio_17_IRQn
ioss_interrupts_gpio_18_IRQn
DeepSleep GPIO_ENH Port #0 Interrupt
DeepSleep GPIO_STD Port #1 Interrupt
DeepSleep GPIO_STD Port #2 Interrupt
DeepSleep GPIO_STD Port #3 Interrupt
DeepSleep GPIO_STD Port #4 Interrupt
DeepSleep GPIO_STD Port #5 Interrupt
DeepSleep GPIO_STD Port #6 Interrupt
DeepSleep GPIO_STD Port #7 Interrupt
DeepSleep GPIO_STD Port #8 Interrupt
DeepSleep GPIO_STD Port #9 Interrupt
DeepSleep GPIO_STD Port #10 Interrupt
DeepSleep GPIO_STD Port #11 Interrupt
DeepSleep GPIO_STD Port #12 Interrupt
DeepSleep GPIO_STD Port #13 Interrupt
DeepSleep GPIO_STD Port #14 Interrupt
DeepSleep GPIO_STD Port #15 Interrupt
DeepSleep GPIO_STD Port #16 Interrupt
DeepSleep GPIO_STD Port #17 Interrupt
DeepSleep GPIO_STD Port #18 Interrupt
Datasheet
49
002-18043 Rev. *J
2022-09-08
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4F single
Interrupts and wake-up assignments
Table 14-1
Peripheral interrupt assignments and wake-up sources (continued)
Interrupt
40
Source
Power Mode
Description
ioss_interrupts_gpio_19_IRQn
ioss_interrupts_gpio_20_IRQn
ioss_interrupts_gpio_21_IRQn
ioss_interrupts_gpio_22_IRQn
ioss_interrupts_gpio_23_IRQn
cpuss_interrupt_crypto_IRQn
cpuss_interrupt_fm_IRQn
cpuss_interrupts_cm4_fp_IRQn
cpuss_interrupts_cm0_cti_0_IRQn
cpuss_interrupts_cm0_cti_1_IRQn
cpuss_interrupts_cm4_cti_0_IRQn
cpuss_interrupts_cm4_cti_1_IRQn
evtgen_0_interrupt_IRQn
DeepSleep GPIO_STD Port #19 Interrupt
DeepSleep GPIO_STD Port #20 Interrupt
DeepSleep GPIO_STD Port #21 Interrupt
DeepSleep GPIO_STD Port #22 Interrupt
DeepSleep GPIO_STD Port #23 Interrupt
41
42
43
44
45
46
47
48
49
50
51
52
Active
Active
Active
Active
Active
Active
Active
Active
Crypto Accelerator Interrupt
FLASH Macro Interrupt
CM4 Floating Point operation fault
CM0+ CTI (Cross Trigger Interface) #0
CM0+ CTI #1
CM4 CTI #0
CM4 CTI #1
Event gen Active domain interrupt
canfd_0_interrupt0_IRQn
CAN0, Consolidated Interrupt #0 for all three
channels
CAN0, Consolidated Interrupt #1 for all three
channels
CAN1, Consolidated Interrupt #0 for all three
channels
CAN1, Consolidated Interrupt #1 for all three
channels
53
54
55
56
Active
Active
Active
Active
canfd_0_interrupt1_IRQn
canfd_1_interrupt0_IRQn
canfd_1_interrupt1_IRQn
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
canfd_0_interrupts0_0_IRQn
canfd_0_interrupts0_1_IRQn
canfd_0_interrupts0_2_IRQn
canfd_0_interrupts1_0_IRQn
canfd_0_interrupts1_1_IRQn
canfd_0_interrupts1_2_IRQn
canfd_1_interrupts0_0_IRQn
canfd_1_interrupts0_1_IRQn
canfd_1_interrupts0_2_IRQn
canfd_1_interrupts1_0_IRQn
canfd_1_interrupts1_1_IRQn
canfd_1_interrupts1_2_IRQn
lin_0_interrupts_0_IRQn
lin_0_interrupts_1_IRQn
lin_0_interrupts_2_IRQn
lin_0_interrupts_3_IRQn
lin_0_interrupts_4_IRQn
lin_0_interrupts_5_IRQn
lin_0_interrupts_6_IRQn
lin_0_interrupts_7_IRQn
scb_1_interrupt_IRQn
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
CAN0, Interrupt #0, Channel #0
CAN0, Interrupt #0, Channel #1
CAN0, Interrupt #0, Channel #2
CAN0, Interrupt #1, Channel #0
CAN0, Interrupt #1, Channel #1
CAN0, Interrupt #1, Channel #2
CAN1, Interrupt #0, Channel #0
CAN1, Interrupt #0, Channel #1
CAN1, Interrupt #0, Channel #2
CAN1, Interrupt #1, Channel #0
CAN1, Interrupt #1, Channel #1
CAN1, Interrupt #1, Channel #2
LIN0, Channel #0 Interrupt
LIN0, Channel #1 Interrupt
LIN0, Channel #2 Interrupt
LIN0, Channel #3 Interrupt
LIN0, Channel #4 Interrupt
LIN0, Channel #5 Interrupt
LIN0, Channel #6 Interrupt
LIN0, Channel #7 Interrupt
SCB1 Interrupt
scb_2_interrupt_IRQn
SCB2 Interrupt
Datasheet
50
002-18043 Rev. *J
2022-09-08
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4F single
Interrupts and wake-up assignments
Table 14-1
Peripheral interrupt assignments and wake-up sources (continued)
Interrupt
79
Source
scb_3_interrupt_IRQn
scb_4_interrupt_IRQn
scb_5_interrupt_IRQn
scb_6_interrupt_IRQn
scb_7_interrupt_IRQn
Power Mode
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Description
SCB3 Interrupt
SCB4 Interrupt
SCB5 Interrupt
SCB6 Interrupt
SCB7 Interrupt
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
pass_0_interrupts_sar_0_IRQn
pass_0_interrupts_sar_1_IRQn
pass_0_interrupts_sar_2_IRQn
pass_0_interrupts_sar_3_IRQn
pass_0_interrupts_sar_4_IRQn
pass_0_interrupts_sar_5_IRQn
pass_0_interrupts_sar_6_IRQn
pass_0_interrupts_sar_7_IRQn
pass_0_interrupts_sar_8_IRQn
pass_0_interrupts_sar_9_IRQn
pass_0_interrupts_sar_10_IRQn
pass_0_interrupts_sar_11_IRQn
pass_0_interrupts_sar_12_IRQn
pass_0_interrupts_sar_13_IRQn
pass_0_interrupts_sar_14_IRQn
pass_0_interrupts_sar_15_IRQn
pass_0_interrupts_sar_16_IRQn
pass_0_interrupts_sar_17_IRQn
pass_0_interrupts_sar_18_IRQn
pass_0_interrupts_sar_19_IRQn
pass_0_interrupts_sar_20_IRQn
pass_0_interrupts_sar_21_IRQn
pass_0_interrupts_sar_22_IRQn
pass_0_interrupts_sar_23_IRQn
pass_0_interrupts_sar_32_IRQn
pass_0_interrupts_sar_33_IRQn
pass_0_interrupts_sar_34_IRQn
pass_0_interrupts_sar_35_IRQn
pass_0_interrupts_sar_36_IRQn
pass_0_interrupts_sar_37_IRQn
pass_0_interrupts_sar_38_IRQn
pass_0_interrupts_sar_39_IRQn
pass_0_interrupts_sar_40_IRQn
pass_0_interrupts_sar_41_IRQn
pass_0_interrupts_sar_42_IRQn
pass_0_interrupts_sar_43_IRQn
pass_0_interrupts_sar_44_IRQn
SAR0, Logical Channel #0 Interrupt
SAR0, Logical Channel #1 Interrupt
SAR0, Logical Channel #2 Interrupt
SAR0, Logical Channel #3 Interrupt
SAR0, Logical Channel #4 Interrupt
SAR0, Logical Channel #5 Interrupt
SAR0, Logical Channel #6 Interrupt
SAR0, Logical Channel #7 Interrupt
SAR0, Logical Channel #8 Interrupt
SAR0, Logical Channel #9 Interrupt
SAR0, Logical Channel #10 Interrupt
SAR0, Logical Channel #11 Interrupt
SAR0, Logical Channel #12 Interrupt
SAR0, Logical Channel #13 Interrupt
SAR0, Logical Channel #14 Interrupt
SAR0, Logical Channel #15 Interrupt
SAR0, Logical Channel #16 Interrupt
SAR0, Logical Channel #17 Interrupt
SAR0, Logical Channel #18 Interrupt
SAR0, Logical Channel #19 Interrupt
SAR0, Logical Channel #20 Interrupt
SAR0, Logical Channel #21 Interrupt
SAR0, Logical Channel #22 Interrupt
SAR0, Logical Channel #23 Interrupt
SAR1, Logical Channel #0 Interrupt
SAR1, Logical Channel #1 Interrupt
SAR1, Logical Channel #2 Interrupt
SAR1, Logical Channel #3 Interrupt
SAR1, Logical Channel #4 Interrupt
SAR1, Logical Channel #5 Interrupt
SAR1, Logical Channel #6 Interrupt
SAR1, Logical Channel #7 Interrupt
SAR1, Logical Channel #8 Interrupt
SAR1, Logical Channel #9 Interrupt
SAR1, Logical Channel #10 Interrupt
SAR1, Logical Channel #11 Interrupt
SAR1, Logical Channel #12 Interrupt
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
Datasheet
51
002-18043 Rev. *J
2022-09-08
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4F single
Interrupts and wake-up assignments
Table 14-1
Peripheral interrupt assignments and wake-up sources (continued)
Interrupt
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
Source
Power Mode
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Description
pass_0_interrupts_sar_45_IRQn
pass_0_interrupts_sar_46_IRQn
pass_0_interrupts_sar_47_IRQn
pass_0_interrupts_sar_48_IRQn
pass_0_interrupts_sar_49_IRQn
pass_0_interrupts_sar_50_IRQn
pass_0_interrupts_sar_51_IRQn
pass_0_interrupts_sar_52_IRQn
pass_0_interrupts_sar_53_IRQn
pass_0_interrupts_sar_54_IRQn
pass_0_interrupts_sar_55_IRQn
pass_0_interrupts_sar_56_IRQn
pass_0_interrupts_sar_57_IRQn
pass_0_interrupts_sar_58_IRQn
pass_0_interrupts_sar_59_IRQn
pass_0_interrupts_sar_60_IRQn
pass_0_interrupts_sar_61_IRQn
pass_0_interrupts_sar_62_IRQn
pass_0_interrupts_sar_63_IRQn
pass_0_interrupts_sar_64_IRQn
pass_0_interrupts_sar_65_IRQn
pass_0_interrupts_sar_66_IRQn
pass_0_interrupts_sar_67_IRQn
pass_0_interrupts_sar_68_IRQn
pass_0_interrupts_sar_69_IRQn
pass_0_interrupts_sar_70_IRQn
pass_0_interrupts_sar_71_IRQn
cpuss_interrupts_dmac_0_IRQn
cpuss_interrupts_dmac_1_IRQn
cpuss_interrupts_dmac_2_IRQn
cpuss_interrupts_dmac_3_IRQn
cpuss_interrupts_dw0_0_IRQn
cpuss_interrupts_dw0_1_IRQn
cpuss_interrupts_dw0_2_IRQn
cpuss_interrupts_dw0_3_IRQn
cpuss_interrupts_dw0_4_IRQn
cpuss_interrupts_dw0_5_IRQn
cpuss_interrupts_dw0_6_IRQn
cpuss_interrupts_dw0_7_IRQn
cpuss_interrupts_dw0_8_IRQn
cpuss_interrupts_dw0_9_IRQn
cpuss_interrupts_dw0_10_IRQn
SAR1, Logical Channel #13 Interrupt
SAR1, Logical Channel #14 Interrupt
SAR1, Logical Channel #15 Interrupt
SAR1, Logical Channel #16 Interrupt
SAR1, Logical Channel #17 Interrupt
SAR1, Logical Channel #18 Interrupt
SAR1, Logical Channel #19 Interrupt
SAR1, Logical Channel #20 Interrupt
SAR1, Logical Channel #21 Interrupt
SAR1, Logical Channel #22 Interrupt
SAR1, Logical Channel #23 Interrupt
SAR1, Logical Channel #24 Interrupt
SAR1, Logical Channel #25 Interrupt
SAR1, Logical Channel #26 Interrupt
SAR1, Logical Channel #27 Interrupt
SAR1, Logical Channel #28 Interrupt
SAR1, Logical Channel #29 Interrupt
SAR1, Logical Channel #30 Interrupt
SAR1, Logical Channel #31 Interrupt
SAR2, Logical Channel #0 Interrupt
SAR2, Logical Channel #1 Interrupt
SAR2, Logical Channel #2 Interrupt
SAR2, Logical Channel #3 Interrupt
SAR2, Logical Channel #4 Interrupt
SAR2, Logical Channel #5 Interrupt
SAR2, Logical Channel #6 Interrupt
SAR2, Logical Channel #7 Interrupt
CPUSS M-DMA0, Channel #0 Interrupt
CPUSS M-DMA0, Channel #1 Interrupt
CPUSS M-DMA0, Channel #2 Interrupt
CPUSS M-DMA0, Channel #3 Interrupt
CPUSS P-DMA0, Channel #0 Interrupt
CPUSS P-DMA0, Channel #1 Interrupt
CPUSS P-DMA0, Channel #2 Interrupt
CPUSS P-DMA0, Channel #3 Interrupt
CPUSS P-DMA0, Channel #4 Interrupt
CPUSS P-DMA0, Channel #5 Interrupt
CPUSS P-DMA0, Channel #6 Interrupt
CPUSS P-DMA0, Channel #7 Interrupt
CPUSS P-DMA0, Channel #8 Interrupt
CPUSS P-DMA0, Channel #9 Interrupt
CPUSS P-DMA0, Channel #10 Interrupt
Datasheet
52
002-18043 Rev. *J
2022-09-08
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4F single
Interrupts and wake-up assignments
Table 14-1
Peripheral interrupt assignments and wake-up sources (continued)
Interrupt
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
Source
Power Mode
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Description
cpuss_interrupts_dw0_11_IRQn
cpuss_interrupts_dw0_12_IRQn
cpuss_interrupts_dw0_13_IRQn
cpuss_interrupts_dw0_14_IRQn
cpuss_interrupts_dw0_15_IRQn
cpuss_interrupts_dw0_16_IRQn
cpuss_interrupts_dw0_17_IRQn
cpuss_interrupts_dw0_18_IRQn
cpuss_interrupts_dw0_19_IRQn
cpuss_interrupts_dw0_20_IRQn
cpuss_interrupts_dw0_21_IRQn
cpuss_interrupts_dw0_22_IRQn
cpuss_interrupts_dw0_23_IRQn
cpuss_interrupts_dw0_24_IRQn
cpuss_interrupts_dw0_25_IRQn
cpuss_interrupts_dw0_26_IRQn
cpuss_interrupts_dw0_27_IRQn
cpuss_interrupts_dw0_28_IRQn
cpuss_interrupts_dw0_29_IRQn
cpuss_interrupts_dw0_30_IRQn
cpuss_interrupts_dw0_31_IRQn
cpuss_interrupts_dw0_32_IRQn
cpuss_interrupts_dw0_33_IRQn
cpuss_interrupts_dw0_34_IRQn
cpuss_interrupts_dw0_35_IRQn
cpuss_interrupts_dw0_36_IRQn
cpuss_interrupts_dw0_37_IRQn
cpuss_interrupts_dw0_38_IRQn
cpuss_interrupts_dw0_39_IRQn
cpuss_interrupts_dw0_40_IRQn
cpuss_interrupts_dw0_41_IRQn
cpuss_interrupts_dw0_42_IRQn
cpuss_interrupts_dw0_43_IRQn
cpuss_interrupts_dw0_44_IRQn
cpuss_interrupts_dw0_45_IRQn
cpuss_interrupts_dw0_46_IRQn
cpuss_interrupts_dw0_47_IRQn
cpuss_interrupts_dw0_48_IRQn
cpuss_interrupts_dw0_49_IRQn
cpuss_interrupts_dw0_50_IRQn
cpuss_interrupts_dw0_51_IRQn
cpuss_interrupts_dw0_52_IRQn
CPUSS P-DMA0, Channel #11 Interrupt
CPUSS P-DMA0, Channel #12 Interrupt
CPUSS P-DMA0, Channel #13 Interrupt
CPUSS P-DMA0, Channel #14 Interrupt
CPUSS P-DMA0, Channel #15 Interrupt
CPUSS P-DMA0, Channel #16 Interrupt
CPUSS P-DMA0, Channel #17 Interrupt
CPUSS P-DMA0, Channel #18 Interrupt
CPUSS P-DMA0, Channel #19 Interrupt
CPUSS P-DMA0, Channel #20 Interrupt
CPUSS P-DMA0, Channel #21 Interrupt
CPUSS P-DMA0, Channel #22 Interrupt
CPUSS P-DMA0, Channel #23 Interrupt
CPUSS P-DMA0, Channel #24 Interrupt
CPUSS P-DMA0, Channel #25 Interrupt
CPUSS P-DMA0, Channel #26 Interrupt
CPUSS P-DMA0, Channel #27 Interrupt
CPUSS P-DMA0, Channel #28 Interrupt
CPUSS P-DMA0, Channel #29 Interrupt
CPUSS P-DMA0, Channel #30 Interrupt
CPUSS P-DMA0, Channel #31 Interrupt
CPUSS P-DMA0, Channel #32 Interrupt
CPUSS P-DMA0, Channel #33 Interrupt
CPUSS P-DMA0, Channel #34 Interrupt
CPUSS P-DMA0, Channel #35 Interrupt
CPUSS P-DMA0, Channel #36 Interrupt
CPUSS P-DMA0, Channel #37 Interrupt
CPUSS P-DMA0, Channel #38 Interrupt
CPUSS P-DMA0, Channel #39 Interrupt
CPUSS P-DMA0, Channel #40 Interrupt
CPUSS P-DMA0, Channel #41 Interrupt
CPUSS P-DMA0, Channel #42 Interrupt
CPUSS P-DMA0, Channel #43 Interrupt
CPUSS P-DMA0, Channel #44 Interrupt
CPUSS P-DMA0, Channel #45 Interrupt
CPUSS P-DMA0, Channel #46 Interrupt
CPUSS P-DMA0, Channel #47 Interrupt
CPUSS P-DMA0, Channel #48 Interrupt
CPUSS P-DMA0, Channel #49 Interrupt
CPUSS P-DMA0, Channel #50 Interrupt
CPUSS P-DMA0, Channel #51 Interrupt
CPUSS P-DMA0, Channel #52 Interrupt
Datasheet
53
002-18043 Rev. *J
2022-09-08
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4F single
Interrupts and wake-up assignments
Table 14-1
Peripheral interrupt assignments and wake-up sources (continued)
Interrupt
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
Source
Power Mode
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Description
cpuss_interrupts_dw0_53_IRQn
cpuss_interrupts_dw0_54_IRQn
cpuss_interrupts_dw0_55_IRQn
cpuss_interrupts_dw0_56_IRQn
cpuss_interrupts_dw0_57_IRQn
cpuss_interrupts_dw0_58_IRQn
cpuss_interrupts_dw0_59_IRQn
cpuss_interrupts_dw0_60_IRQn
cpuss_interrupts_dw0_61_IRQn
cpuss_interrupts_dw0_62_IRQn
cpuss_interrupts_dw0_63_IRQn
cpuss_interrupts_dw0_64_IRQn
cpuss_interrupts_dw0_65_IRQn
cpuss_interrupts_dw0_66_IRQn
cpuss_interrupts_dw0_67_IRQn
cpuss_interrupts_dw0_68_IRQn
cpuss_interrupts_dw0_69_IRQn
cpuss_interrupts_dw0_70_IRQn
cpuss_interrupts_dw0_71_IRQn
cpuss_interrupts_dw0_72_IRQn
cpuss_interrupts_dw0_73_IRQn
cpuss_interrupts_dw0_74_IRQn
cpuss_interrupts_dw0_75_IRQn
cpuss_interrupts_dw0_76_IRQn
cpuss_interrupts_dw0_77_IRQn
cpuss_interrupts_dw0_78_IRQn
cpuss_interrupts_dw0_79_IRQn
cpuss_interrupts_dw0_80_IRQn
cpuss_interrupts_dw0_81_IRQn
cpuss_interrupts_dw0_82_IRQn
cpuss_interrupts_dw0_83_IRQn
cpuss_interrupts_dw0_84_IRQn
cpuss_interrupts_dw0_85_IRQn
cpuss_interrupts_dw0_86_IRQn
cpuss_interrupts_dw0_87_IRQn
cpuss_interrupts_dw0_88_IRQn
cpuss_interrupts_dw1_0_IRQn
cpuss_interrupts_dw1_1_IRQn
cpuss_interrupts_dw1_2_IRQn
cpuss_interrupts_dw1_3_IRQn
cpuss_interrupts_dw1_4_IRQn
cpuss_interrupts_dw1_5_IRQn
CPUSS P-DMA0, Channel #53 Interrupt
CPUSS P-DMA0, Channel #54 Interrupt
CPUSS P-DMA0, Channel #55 Interrupt
CPUSS P-DMA0, Channel #56 Interrupt
CPUSS P-DMA0, Channel #57 Interrupt
CPUSS P-DMA0, Channel #58 Interrupt
CPUSS P-DMA0, Channel #59 Interrupt
CPUSS P-DMA0, Channel #60 Interrupt
CPUSS P-DMA0, Channel #61 Interrupt
CPUSS P-DMA0, Channel #62 Interrupt
CPUSS P-DMA0, Channel #63 Interrupt
CPUSS P-DMA0, Channel #64 Interrupt
CPUSS P-DMA0, Channel #65 Interrupt
CPUSS P-DMA0, Channel #66 Interrupt
CPUSS P-DMA0, Channel #67 Interrupt
CPUSS P-DMA0, Channel #68 Interrupt
CPUSS P-DMA0, Channel #69 Interrupt
CPUSS P-DMA0, Channel #70 Interrupt
CPUSS P-DMA0, Channel #71 Interrupt
CPUSS P-DMA0, Channel #72 Interrupt
CPUSS P-DMA0, Channel #73 Interrupt
CPUSS P-DMA0, Channel #74 Interrupt
CPUSS P-DMA0, Channel #75 Interrupt
CPUSS P-DMA0, Channel #76 Interrupt
CPUSS P-DMA0, Channel #77 Interrupt
CPUSS P-DMA0, Channel #78 Interrupt
CPUSS P-DMA0, Channel #79 Interrupt
CPUSS P-DMA0, Channel #80 Interrupt
CPUSS P-DMA0, Channel #81 Interrupt
CPUSS P-DMA0, Channel #82 Interrupt
CPUSS P-DMA0, Channel #83 Interrupt
CPUSS P-DMA0, Channel #84 Interrupt
CPUSS P-DMA0, Channel #85 Interrupt
CPUSS P-DMA0, Channel #86 Interrupt
CPUSS P-DMA0, Channel #87 Interrupt
CPUSS P-DMA0, Channel #88 Interrupt
CPUSS P-DMA1, Channel #0 Interrupt
CPUSS P-DMA1, Channel #1 Interrupt
CPUSS P-DMA1, Channel #2 Interrupt
CPUSS P-DMA1, Channel #3 Interrupt
CPUSS P-DMA1, Channel #4 Interrupt
CPUSS P-DMA1, Channel #5 Interrupt
Datasheet
54
002-18043 Rev. *J
2022-09-08
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4F single
Interrupts and wake-up assignments
Table 14-1
Peripheral interrupt assignments and wake-up sources (continued)
Interrupt
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
Source
Power Mode
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Description
cpuss_interrupts_dw1_6_IRQn
cpuss_interrupts_dw1_7_IRQn
cpuss_interrupts_dw1_8_IRQn
cpuss_interrupts_dw1_9_IRQn
cpuss_interrupts_dw1_10_IRQn
cpuss_interrupts_dw1_11_IRQn
cpuss_interrupts_dw1_12_IRQn
cpuss_interrupts_dw1_13_IRQn
cpuss_interrupts_dw1_14_IRQn
cpuss_interrupts_dw1_15_IRQn
cpuss_interrupts_dw1_16_IRQn
cpuss_interrupts_dw1_17_IRQn
cpuss_interrupts_dw1_18_IRQn
cpuss_interrupts_dw1_19_IRQn
cpuss_interrupts_dw1_20_IRQn
cpuss_interrupts_dw1_21_IRQn
cpuss_interrupts_dw1_22_IRQn
cpuss_interrupts_dw1_23_IRQn
cpuss_interrupts_dw1_24_IRQn
cpuss_interrupts_dw1_25_IRQn
cpuss_interrupts_dw1_26_IRQn
cpuss_interrupts_dw1_27_IRQn
cpuss_interrupts_dw1_28_IRQn
cpuss_interrupts_dw1_29_IRQn
cpuss_interrupts_dw1_30_IRQn
cpuss_interrupts_dw1_31_IRQn
cpuss_interrupts_dw1_32_IRQn
tcpwm_0_interrupts_0_IRQn
tcpwm_0_interrupts_1_IRQn
tcpwm_0_interrupts_2_IRQn
tcpwm_0_interrupts_3_IRQn
tcpwm_0_interrupts_4_IRQn
tcpwm_0_interrupts_5_IRQn
tcpwm_0_interrupts_6_IRQn
tcpwm_0_interrupts_7_IRQn
tcpwm_0_interrupts_8_IRQn
tcpwm_0_interrupts_9_IRQn
tcpwm_0_interrupts_10_IRQn
tcpwm_0_interrupts_11_IRQn
tcpwm_0_interrupts_12_IRQn
tcpwm_0_interrupts_13_IRQn
tcpwm_0_interrupts_14_IRQn
CPUSS P-DMA1, Channel #6 Interrupt
CPUSS P-DMA1, Channel #7 Interrupt
CPUSS P-DMA1, Channel #8 Interrupt
CPUSS P-DMA1, Channel #9 Interrupt
CPUSS P-DMA1, Channel #10 Interrupt
CPUSS P-DMA1, Channel #11 Interrupt
CPUSS P-DMA1, Channel #12 Interrupt
CPUSS P-DMA1, Channel #13 Interrupt
CPUSS P-DMA1, Channel #14 Interrupt
CPUSS P-DMA1, Channel #15 Interrupt
CPUSS P-DMA1, Channel #16 Interrupt
CPUSS P-DMA1, Channel #17 Interrupt
CPUSS P-DMA1, Channel #18 Interrupt
CPUSS P-DMA1, Channel #19 Interrupt
CPUSS P-DMA1, Channel #20 Interrupt
CPUSS P-DMA1, Channel #21 Interrupt
CPUSS P-DMA1, Channel #22 Interrupt
CPUSS P-DMA1, Channel #23 Interrupt
CPUSS P-DMA1, Channel #24 Interrupt
CPUSS P-DMA1, Channel #25 Interrupt
CPUSS P-DMA1, Channel #26 Interrupt
CPUSS P-DMA1, Channel #27 Interrupt
CPUSS P-DMA1, Channel #28 Interrupt
CPUSS P-DMA1, Channel #29 Interrupt
CPUSS P-DMA1, Channel #30 Interrupt
CPUSS P-DMA1, Channel #31 Interrupt
CPUSS P-DMA1, Channel #32 Interrupt
TCPWM0 Group #0, Counter #0 Interrupt
TCPWM0 Group #0, Counter #1 Interrupt
TCPWM0 Group #0, Counter #2 Interrupt
TCPWM0 Group #0, Counter #3 Interrupt
TCPWM0 Group #0, Counter #4 Interrupt
TCPWM0 Group #0, Counter #5 Interrupt
TCPWM0 Group #0, Counter #6 Interrupt
TCPWM0 Group #0, Counter #7 Interrupt
TCPWM0 Group #0, Counter #8 Interrupt
TCPWM0 Group #0, Counter #9 Interrupt
TCPWM0 Group #0, Counter #10 Interrupt
TCPWM0 Group #0, Counter #11 Interrupt
TCPWM0 Group #0, Counter #12 Interrupt
TCPWM0 Group #0, Counter #13 Interrupt
TCPWM0 Group #0, Counter #14 Interrupt
Datasheet
55
002-18043 Rev. *J
2022-09-08
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4F single
Interrupts and wake-up assignments
Table 14-1
Peripheral interrupt assignments and wake-up sources (continued)
Interrupt
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
Source
Power Mode
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Description
tcpwm_0_interrupts_15_IRQn
tcpwm_0_interrupts_16_IRQn
tcpwm_0_interrupts_17_IRQn
tcpwm_0_interrupts_18_IRQn
tcpwm_0_interrupts_19_IRQn
tcpwm_0_interrupts_20_IRQn
tcpwm_0_interrupts_21_IRQn
tcpwm_0_interrupts_22_IRQn
tcpwm_0_interrupts_23_IRQn
tcpwm_0_interrupts_24_IRQn
tcpwm_0_interrupts_25_IRQn
tcpwm_0_interrupts_26_IRQn
tcpwm_0_interrupts_27_IRQn
tcpwm_0_interrupts_28_IRQn
tcpwm_0_interrupts_29_IRQn
tcpwm_0_interrupts_30_IRQn
tcpwm_0_interrupts_31_IRQn
tcpwm_0_interrupts_32_IRQn
tcpwm_0_interrupts_33_IRQn
tcpwm_0_interrupts_34_IRQn
tcpwm_0_interrupts_35_IRQn
tcpwm_0_interrupts_36_IRQn
tcpwm_0_interrupts_37_IRQn
tcpwm_0_interrupts_38_IRQn
tcpwm_0_interrupts_39_IRQn
tcpwm_0_interrupts_40_IRQn
tcpwm_0_interrupts_41_IRQn
tcpwm_0_interrupts_42_IRQn
tcpwm_0_interrupts_43_IRQn
tcpwm_0_interrupts_44_IRQn
tcpwm_0_interrupts_45_IRQn
tcpwm_0_interrupts_46_IRQn
tcpwm_0_interrupts_47_IRQn
tcpwm_0_interrupts_48_IRQn
tcpwm_0_interrupts_49_IRQn
tcpwm_0_interrupts_50_IRQn
tcpwm_0_interrupts_51_IRQn
tcpwm_0_interrupts_52_IRQn
tcpwm_0_interrupts_53_IRQn
tcpwm_0_interrupts_54_IRQn
tcpwm_0_interrupts_55_IRQn
tcpwm_0_interrupts_56_IRQn
TCPWM0 Group #0, Counter #15 Interrupt
TCPWM0 Group #0, Counter #16 Interrupt
TCPWM0 Group #0, Counter #17 Interrupt
TCPWM0 Group #0, Counter #18 Interrupt
TCPWM0 Group #0, Counter #19 Interrupt
TCPWM0 Group #0, Counter #20 Interrupt
TCPWM0 Group #0, Counter #21 Interrupt
TCPWM0 Group #0, Counter #22 Interrupt
TCPWM0 Group #0, Counter #23 Interrupt
TCPWM0 Group #0, Counter #24 Interrupt
TCPWM0 Group #0, Counter #25 Interrupt
TCPWM0 Group #0, Counter #26 Interrupt
TCPWM0 Group #0, Counter #27 Interrupt
TCPWM0 Group #0, Counter #28 Interrupt
TCPWM0 Group #0, Counter #29 Interrupt
TCPWM0 Group #0, Counter #30 Interrupt
TCPWM0 Group #0, Counter #31 Interrupt
TCPWM0 Group #0, Counter #32 Interrupt
TCPWM0 Group #0, Counter #33 Interrupt
TCPWM0 Group #0, Counter #34 Interrupt
TCPWM0 Group #0, Counter #35 Interrupt
TCPWM0 Group #0, Counter #36 Interrupt
TCPWM0 Group #0, Counter #37 Interrupt
TCPWM0 Group #0, Counter #38 Interrupt
TCPWM0 Group #0, Counter #39 Interrupt
TCPWM0 Group #0, Counter #40 Interrupt
TCPWM0 Group #0, Counter #41 Interrupt
TCPWM0 Group #0, Counter #42 Interrupt
TCPWM0 Group #0, Counter #43 Interrupt
TCPWM0 Group #0, Counter #44 Interrupt
TCPWM0 Group #0, Counter #45 Interrupt
TCPWM0 Group #0, Counter #46 Interrupt
TCPWM0 Group #0, Counter #47 Interrupt
TCPWM0 Group #0, Counter #48 Interrupt
TCPWM0 Group #0, Counter #49 Interrupt
TCPWM0 Group #0, Counter #50 Interrupt
TCPWM0 Group #0, Counter #51 Interrupt
TCPWM0 Group #0, Counter #52 Interrupt
TCPWM0 Group #0, Counter #53 Interrupt
TCPWM0 Group #0, Counter #54 Interrupt
TCPWM0 Group #0, Counter #55 Interrupt
TCPWM0 Group #0, Counter #56 Interrupt
Datasheet
56
002-18043 Rev. *J
2022-09-08
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4F single
Interrupts and wake-up assignments
Table 14-1
Peripheral interrupt assignments and wake-up sources (continued)
Interrupt
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
Source
Power Mode
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Description
tcpwm_0_interrupts_57_IRQn
tcpwm_0_interrupts_58_IRQn
tcpwm_0_interrupts_59_IRQn
tcpwm_0_interrupts_60_IRQn
tcpwm_0_interrupts_61_IRQn
tcpwm_0_interrupts_62_IRQn
tcpwm_0_interrupts_256_IRQn
tcpwm_0_interrupts_257_IRQn
tcpwm_0_interrupts_258_IRQn
tcpwm_0_interrupts_259_IRQn
tcpwm_0_interrupts_260_IRQn
tcpwm_0_interrupts_261_IRQn
tcpwm_0_interrupts_262_IRQn
tcpwm_0_interrupts_263_IRQn
tcpwm_0_interrupts_264_IRQn
tcpwm_0_interrupts_265_IRQn
tcpwm_0_interrupts_266_IRQn
tcpwm_0_interrupts_267_IRQn
tcpwm_0_interrupts_512_IRQn
tcpwm_0_interrupts_513_IRQn
tcpwm_0_interrupts_514_IRQn
tcpwm_0_interrupts_515_IRQn
TCPWM0 Group #0, Counter #57 Interrupt
TCPWM0 Group #0, Counter #58 Interrupt
TCPWM0 Group #0, Counter #59 Interrupt
TCPWM0 Group #0, Counter #60 Interrupt
TCPWM0 Group #0, Counter #61 Interrupt
TCPWM0 Group #0, Counter #62 Interrupt
TCPWM0 Group #1, Counter #0 Interrupt
TCPWM0 Group #1, Counter #1 Interrupt
TCPWM0 Group #1, Counter #2 Interrupt
TCPWM0 Group #1, Counter #3 Interrupt
TCPWM0 Group #1, Counter #4 Interrupt
TCPWM0 Group #1, Counter #5 Interrupt
TCPWM0 Group #1, Counter #6 Interrupt
TCPWM0 Group #1, Counter #7 Interrupt
TCPWM0 Group #1, Counter #8 Interrupt
TCPWM0 Group #1, Counter #9 Interrupt
TCPWM0 Group #1, Counter #10 Interrupt
TCPWM0 Group #1, Counter #11 Interrupt
TCPWM0 Group #2, Counter #0 Interrupt
TCPWM0 Group #2, Counter #1 Interrupt
TCPWM0 Group #2, Counter #2 Interrupt
TCPWM0 Group #2, Counter #3 Interrupt
Datasheet
57
002-18043 Rev. *J
2022-09-08
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4F single
Core interrupt types
15
Core interrupt types
Table 15-1
Core interrupt types
Interrupt
Source
CPUIntIdx0_IRQn[30]
CPUIntIdx1_IRQn[30]
CPUIntIdx2_IRQn
CPUIntIdx3_IRQn
CPUIntIdx4_IRQn
CPUIntIdx5_IRQn
CPUIntIdx6_IRQn
CPUIntIdx7_IRQn
Internal0_IRQn
Internal1_IRQn
Internal2_IRQn
Internal3_IRQn
Internal4_IRQn
Internal5_IRQn
Internal6_IRQn
Internal7_IRQn
Power Mode
DeepSleep
DeepSleep
DeepSleep
DeepSleep
DeepSleep
DeepSleep
DeepSleep
DeepSleep
Active
Description
CPU User Interrupt #0
CPU User Interrupt #1
CPU User Interrupt #2
CPU User Interrupt #3
CPU User Interrupt #4
CPU User Interrupt #5
CPU User Interrupt #6
CPU User Interrupt #7
Internal Software Interrupt #0
Internal Software Interrupt #1
Internal Software Interrupt #2
Internal Software Interrupt #3
Internal Software Interrupt #4
Internal Software Interrupt #5
Internal Software Interrupt #6
Internal Software Interrupt #7
0
1
2
3
4
5
6
7
8
9
Active
Active
Active
Active
Active
Active
Active
10
11
12
13
14
15
Note
30.User interrupt cannot be used for CM0+ application, as it is used internally by system calls. Note, this does not impact CM4 application.
Datasheet
58
002-18043 Rev. *J
2022-09-08
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4F single
Trigger multiplexer
16
Trigger multiplexer
Green numbers indicate mux group number
Orange numbers indicate 1:1 group number
16
16
8
P-DMA0: PDMA0_TR_OUT[0:15]
8
4
P-DMA1: PDMA1_TR_OUT[0:7]
8
6
P-DMA0: PDMA0_TR_IN[0:7]
0
4
M-DMA: MDMA_TR_OUT[0:3]
3:6
4
54x8 = 432
0:15
16
16
8
4
6
4
16
6
4
8
8
4
P-DMA1: PDMA1_TR_IN[0:7]
M-DMA: MDMA_TR_IN[0:3]
1
2
7:10
16:31
60x8 = 480
4x4 = 16
4
4
TCPWM[0]32: TCPWM_32_TR_OUT0[0:3]
TCPWM[0]32: TCPWM_32_TR_OUT1[0:3]
8
12
63
3
P-DMA0: PDMA0_TR_IN[8:15]
16
Mux #4 only
12
12
8
6
TCPWM[0]16M: TCPWM_16M_TR_OUT0[0:11]
TCPWM[0]16M: TCPWM_16M_TR_OUT1[0:11]
4
TCPWM[0]: TCPWM_ALL_CNT_TR_IN[0:15]
85x8 + 93x16 = 2168
63
63
TCPWM[0]16: TCPWM_16_TR_OUT0[0:62]
TCPWM[0]16: TCPWM_16_TR_OUT1[0:62]
8
0
LIN[0]: LIN0_CMD_TR_IN[0:7]
PASS[0]: PASS0_CH_TR_IN[0:23]
PASS[0]: PASS0_CH_TR_IN[32:63]
PASS[0]: PASS0_CH_TR_IN[64:71]
64
1
16
8
4
6
6
CPUSS: FAULT_TR_OUT[0:3]
CPUSS: CTI_TR_OUT[0:1]
8
3:10
11
5
TCPWM[0]: TCPWM_ALL_CNT_TR_IN[16:26]
24
32
6
122x11 = 1342
11
EVTGEN[0]: EVTGEN_TR_OUT[0:10]
HSIOM: HSIOM_IO _INPUT[0:31]
18
16
32
12
6
32
12
PASS[0]: PASS_GEN_TR_IN[0:11]
P-DMA0: PDMA0_TR_IN[25:88]
6
3
4
6
0:2
79x12 = 948
64
6
PASS[0]: PASS_GEN_TR_OUT[0:5]
PASS[0]: PASS_CH_DONE_TR_OUT[0:23]
PASS[0]: PASS_CH_DONE_TR_OUT[32:63]
PASS[0]: PASS_CH_DONE_TR_OUT[64:71]
PASS[0]: PASS_CH_RANGEVIO_TR_OUT[0:23]
PASS[0]: PASS_CH_RANGEVIO_TR_OUT[32:63]
PASS[0]: PASS_CH_RANGEVIO_TR_OUT[64:71]
64
2
3
64
12
52
TCPWM[0]16M: TCPWM0_16M_ONE_CNT_TR_IN[0:11]
TCPWM[0]16: TCPWM0_16_ONE_CNT_TR_IN[0:51]
CAN[0:1]: CAN0_DBG_TR_OUT/CAN1_DBG_TR_OUT[0:2]
CAN[0:1]: CAN0_FIFO0_TR_OUT/CAN1_FIFO0_TR_OUT[0:2]
CAN[0:1]: CAN0_FIFO1_TR_OUT/CAN1_FIFO1_TR_OUT[0:2]
18
6
9
9
4
5
P-DMA0: PDMA0_TR_IN[16:24]
P-DMA1: PDMA1_TR_IN[24:32]
CAN[0]: CAN0_TT_TR_OUT[0:2]
CAN[1]: CAN1_TT_TR_OUT[0:2]
6
CAN[0]: CAN0_TT_TR_IN[0:2]
CAN[1]: CAN1_TT_TR_IN[0:2]
6
7
6x6 = 36
3
3
3
3
6
7
P-DMA0: PDMA0_TR_OUT[16,19,22]
P-DMA1: PDMA1_TR_OUT[24,27,30]
CAN[0]: CAN0_DBG_TR_ACK[0:2]
CAN[1]: CAN1_DBG_TR_ACK[0:2]
SCB[0:7]: SCB_TX_TR_OUT
SCB[0:7]: SCB_RX_TR_OUT
SCB[0:7]: SCB_I2C_SCL_TR_OUT
24
SCB_TX_TR_OUT, SCB_RX_TR_OUT
16
2
8
P-DMA1: PDMA1_TR_IN[8:23]
CPUSS: CTI_TR_IN[0:1]
10x10 = 100
355
P-DMA0*, SCB*, CANFD*, CPUSS*, TCPWM_TR_OUT0*
222
133
5
5
1
1
All Triggers
9
TCPWM[0]: TCPWM_DEBUG_FREEZE_TR_IN
PERI: PERI_DEBUG_FREEZE_TR_IN
222x5=1110
8
1
3
PASS[0]: PASS_DEBUG_FREEZE_TR_IN
P-DMA1*, M-DMA*, PASS*, EVTGEN*, TCPWM_TR_OUT1*
SRSS: SRSS_WDT_DEBUG_FREEZE_TR_IN
SRSS: SRSS_MCWDT_DEBUG_FREEZE_TR_IN[0:1]
10
133x5=665
2
HSIOM: HSIOM_IO_OUTPUT[0:1]
Figure 16-1
Trigger multiplexer[31]
Note
31.The diagram shows only the TRIG_LABEL, final trigger formation is based on the formula TRIG_{PREFIX(IN/OUT)}_{MUX_x}_{TRIG_LA-
BEL} / TRIG_{PREFIX(IN_1TO1/OUT_1TO1)}_{x}_{TRIG_LABEL} and Table 17-1, Table 18-1, and Table 19-1.
Datasheet
59
002-18043 Rev. *J
2022-09-08
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4F single
Triggers group inputs
17
Triggers group inputs
Table 17-1
Input
Trigger inputs
Trigger Label (TRIG_LABEL)
Description
MUX Group 0: PDMA0_TR (P-DMA0_0_15 trigger multiplexer)
1:16[32]
17:24
PDMA0_TR_OUT[0:15]
Allow P-DMA0 to chain to itself, useful for triggering once per row
for 2D transfer
Cross connections from P-DMA1 to P-DMA0, Channels 0-7 are
used
PDMA1_TR_OUT[0:7]
25:28
29:32
33:34
35:38
39:54
MDMA_TR_OUT[0:3]
FAULT_TR_OUT[0:3]
CTI_TR_OUT[0:1]
EVTGEN_TR_OUT[3:6]
HSIOM_IO_INPUT[0:15]
Cross connections from M-DMA0 to P-DMA0
Allow faults to initiate data transfer for debug purposes
Trace events
EVTGEN triggers
I/O inputs
MUX Group 1: PDMA1_TR (P-DMA1 trigger multiplexer)
1:16
17:24
PDMA0_TR_OUT[0:15]
PDMA1_TR_OUT[0:7]
Allow P-DMA0 to trigger P-DMA1
Allow P-DMA1 to chain to itself, useful for triggering once per row
for 2D transfer
25:28
29:32
33:34
35:38
39:54
55:60
MDMA_TR_OUT[0:3]
FAULT_TR_OUT[0:3]
CTI_TR_OUT[0:1]
EVTGEN_TR_OUT[7:10]
HSIOM_IO_INPUT[16:31]
PASS_GEN_TR_OUT[0:5]
Allow M-DMA0 to trigger P-DMA0
Allow faults to initiate data transfer for debug purposes
Trace events
EVTGEN triggers
I/O inputs
PASS SAR events
MUX Group 2: MDMA (M-DMA0 trigger multiplexer)
1:4 MDMA_TR_OUT[0:3] Allow M-DMA0 to trigger itself
MUX Group 3: TCPWM_TO_PDMA0 (TCPWM0 to P-DMA0 trigger multiplexer)
1:4
TCPWM_32_TR_OUT0[0:3]
32-bit TCPWM0 counters
5:16
TCPWM_16M_TR_OUT0[0:11 16-bit Motor enhanced TCPWM0 counters
]
17:79
80:82
83:85
TCPWM_16_TR_OUT0[0:62] 16-bit TCPWM0 counters
CAN0_TT_TR_OUT[0:2]
CAN1_TT_TR_OUT[0:2]
CAN0 TT Sync Outputs
CAN1 TT Sync Outputs
MUX Group 4: TCPWM_OUT (TCPWM0 loop back multiplexer)
1:4
TCPWM_32_TR_OUT0[0:3]
32-bit TCPWM0 counters
5:16
TCPWM_16M_TR_OUT0[0:11 16-bit Motor enhanced TCPWM0 counters
]
17:79
80:87
88:90
91:93
TCPWM_16_TR_OUT0[0:62] 16-bit TCPWM0 counters
TCPWM_16_TR_OUT1[0:7]
CAN0_TT_TR_OUT[0:2]
CAN1_TT_TR_OUT[0:2]
Allows feedback of two signals from same counters
CAN0 TT Sync Outputs
CAN1 TT Sync Outputs
MUX Group 5: TCPWM_IN (TCPWM0 Trigger Multiplexer)
1:16
PDMA0_TR_OUT[0:15]
General purpose P-DMA0 triggers
Note
32.“a:b” depicts a range starting from ‘a’ through ‘b’.
Datasheet
60
002-18043 Rev. *J
2022-09-08
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4F single
Triggers group inputs
Table 17-1
Trigger inputs (continued)
Input
17:24
25:28
29:30
31:34
35:40
41:72
73
74
75
76
77
78
79
80
81
82
83
84
85
Trigger Label (TRIG_LABEL)
PDMA1_TR_OUT[0:7]
MDMA_TR_OUT[0:3]
CTI_TR_OUT[0:1]
FAULT_TR_OUT[0:3]
PASS_GEN_TR_OUT[0:5]
HSIOM_IO_INPUT[0:31]
SCB_TX_TR_OUT[0]
SCB_RX_TR_OUT[0]
SCB_I2C_SCL_TR_OUT[0]
SCB_TX_TR_OUT[1]
SCB_RX_TR_OUT[1]
SCB_I2C_SCL_TR_OUT[1]
SCB_TX_TR_OUT[2]
SCB_RX_TR_OUT[2]
SCB_I2C_SCL_TR_OUT[2]
SCB_TX_TR_OUT[3]
SCB_RX_TR_OUT[3]
SCB_I2C_SCL_TR_OUT[3]
SCB_TX_TR_OUT[4]
SCB_RX_TR_OUT[4]
SCB_I2C_SCL_TR_OUT[4]
SCB_TX_TR_OUT[5]
Description
General purpose P-DMA1 triggers
M-DMA0 triggers
Trace events
Fault events
PASS SAR events
I/O inputs
SCB0 TX trigger
SCB0 RX trigger
SCB0 I2C trigger
SCB1 TX trigger
SCB1 RX trigger
SCB1 I2C trigger
SCB2 TX trigger
SCB2 RX trigger
SCB2 I2C trigger
SCB3 TX trigger
SCB3 RX trigger
SCB3 I2C trigger
SCB4 TX trigger
SCB4 RX trigger
SCB4 I2C trigger
SCB5 TX trigger
SCB5 RX trigger
SCB5 I2C trigger
SCB6 TX trigger
SCB6 RX trigger
SCB6 I2C trigger
SCB7 TX trigger
SCB7 RX trigger
SCB7 I2C trigger
CAN0 M-DMA0 events
CAN0 FIFO0 events
CAN0 FIFO1 events
CAN1 M-DMA0 events
CAN1 FIFO0 events
CAN1 FIFO1 events
EVTGEN triggers
86
87
88
89
90
91
92
93
SCB_RX_TR_OUT[5]
SCB_I2C_SCL_TR_OUT[5]
SCB_TX_TR_OUT[6]
SCB_RX_TR_OUT[6]
SCB_I2C_SCL_TR_OUT[6]
SCB_TX_TR_OUT[7]
94
95
96
SCB_RX_TR_OUT[7]
SCB_I2C_SCL_TR_OUT[7]
CAN0_DBG_TR_OUT[0:2]
CAN0_FIFO0_TR_OUT[0:2]
CAN0_FIFO1_TR_OUT[0:2]
CAN1_DBG_TR_OUT[0:2]
CAN1_FIFO0_TR_OUT[0:2]
CAN1_FIFO1_TR_OUT[0:2]
EVTGEN_TR_OUT[3:10]
97:99
100:102
103:105
106:108
109:111
112:114
115:122
MUX Group 6: PASS (PASS SAR trigger multiplexer)
1:16
17:18
19:22
PDMA0_TR_OUT[0:15]
CTI_TR_OUT[0:1]
FAULT_TR_OUT[0:3]
General purpose P-DMA0 triggers
Trace events
Fault events
Datasheet
61
002-18043 Rev. *J
2022-09-08
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4F single
Triggers group inputs
Table 17-1
Trigger inputs (continued)
Input
23:25
26:31
32:63
64:67
68:79
Trigger Label (TRIG_LABEL)
EVTGEN_TR_OUT[0:2]
PASS_GEN_TR_OUT[0:5]
HSIOM_IO_INPUT[0:31]
TCPWM_32_TR_OUT1[0:3]
Description
EVTGEN triggers
PASS SAR done signals
I/O inputs
32-bit TCPWM0 counters
TCPWM_16M_TR_OUT1[0:11 16-bit Motor enhanced TCPWM0 counters
]
MUX Group 7: CAN TT sync triggers
1:3
4:6
CAN0_TT_TR_OUT[0:2]
CAN1_TT_TR_OUT[0:2]
CAN0 TT Sync Outputs
CAN1 TT Sync Outputs
MUX Group 8: DebugMain (Debug Multiplexer)
1:5
6:10
TR_GROUP9_OUTPUT[0:4] Output from debug reduction multiplexer #1
TR_GROUP10_OUTPUT[0:4] Output from debug reduction multiplexer #2
MUX Group 9: DebugReduction1 (Debug Reduction #1)
1:89
90:97
98:105
PDMA0_TR_OUT[0:88]
SCB_TX_TR_OUT[0:7]
SCB_RX_TR_OUT[0:7]
P-DMA0 triggers
SCB TTCAN tx Triggers
SCB TTCAN rx Triggers
106:113
114:116
117:119
120:122
123:125
126:128
129:131
132:134
135:137
138:139
140:143
144:147
148:159
SCB_I2C_SCL_TR_OUT[0:7] SCB I2C triggers
CAN0_DBG_TR_OUT[0:2]
CAN0_FIFO0_TR_OUT[0:2]
CAN0_FIFO1_TR_OUT[0:2]
CAN0_TT_TR_OUT[0:2]
CAN1_DBG_TR_OUT[0:2]
CAN1_FIFO0_TR_OUT[0:2]
CAN1_FIFO1_TR_OUT[0:2]
CAN1_TT_TR_OUT[0:2]
CTI_TR_OUT[0:1]
FAULT_TR_OUT[0:3]
TCPWM_32_TR_OUT0[0:3]
TCPWM_16M_TR_OUT0[0:11 16-bit Motor enhanced TCPWM0 counters
]
CAN0 P-DMA
CAN0 FIFO0
CAN0 FIFO1
CAN TT Sync Outputs
CAN1 P-DMA
CAN1 FIFO0
CAN1 FIFO1
CAN TT Sync Outputs
Trace events
Fault events
32-bit TCPWM0 counters
160:222
TCPWM_16_TR_OUT0[0:62] 16-bit TCPWM0 counters
MUX Group 10: DebugReduction2 (Debug Reduction #2)
1:33
34:37
38:41
42:53
PDMA1_TR_OUT[0:32]
MDMA_TR_OUT[0:3]
TCPWM_32_TR_OUT1[0:3]
TCPWM_16M_TR_OUT1[0:11 16-bit Motor enhanced TCPWM0 counters
]
16-bit Motor enhanced TCPWM0 counters
16-bit TCPWM0 counters
32-bit TCPWM0 counters
54:116
117:122
123:133
TCPWM_16_TR_OUT1[0:62] 16-bit TCPWM0 counters
PASS_GEN_TR_OUT[0:5]
EVTGEN_TR_OUT[0:10]
PASS SAR conversion complete events
EVTGEN Triggers
Datasheet
62
002-18043 Rev. *J
2022-09-08
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4F single
Triggers group outputs
18
Triggers group outputs
Table 18-1
Trigger outputs
Output
MUX Group 0: PDMA0_TR (P-DMA0 trigger multiplexer)
0:7 PDMA0_TR_IN[0:7]
MUX Group 1: PDMA1_TR (P-DMA1 trigger multiplexer)
0:7 PDMA1_TR_IN[0:7]
MUX Group 2: MDMA (M-DMA0 trigger multiplexer)
0:3 MDMA_TR_IN[0:3]
MUX Group 3: TCPWM_TO_PDMA0 (TCPWM0 to P-DMA0 trigger multiplexer)
0:7 PDMA0_TR_IN[8:15]
MUX Group 4: TCPWM_OUT (TCPWM0 loop back multiplexer)
0:15 TCPWM_ALL_CNT_TR_IN[0:15]
MUX Group 5: TCPWM_IN (TCPWM0 Trigger Multiplexer)
0:10 TCPWM_ALL_CNT_TR_IN[16:26]
MUX Group 6: PASS (PASS SAR trigger multiplexer)
0:11 PASS_GEN_TR_IN[0:11]
MUX Group 7: CANTT (CAN TT Sync)
Trigger Label (TRIG_LABEL)
Description
Triggers to P-DMA0[0:7]
Triggers to P-DMA1[0:7]
Triggers to M-DMA0
Triggers to P-DMA0[8:15]
All counters trigger input
Triggers to TCPWM0
Triggers to SAR ADCs
0:2
3:5
CAN0_TT_TR_IN[0:2]
CAN1_TT_TR_IN[0:2]
CAN0 TT Sync Inputs
CAN1 TT Sync Inputs
MUX Group 8: DebugMain (Debug Multiplexer)
0:1
2:3
4
5
6
HSIOM_IO_OUTPUT[0:1]
CTI_TR_IN[0:1]
PERI_DEBUG_FREEZE_TR_IN
PASS_DEBUG_FREEZE_TR_IN
SRSS_WDT_DEBUG_FREEZE_TR_IN
SRSS_MCWDT_DEBUG_-
FREEZE_TR_IN[0:1]
To HSIOM as an output
To CPU Cross Trigger system
Signal to Freeze PERI operation
Signal to Freeze SAR ADC operation
Signal to Freeze WDT operation
Signal to Freeze MCWDT operation
7:8
9
TCPWM_DEBUG_FREEZE_TR_IN
Signal to Freeze TCPWM0 operation
To main debug multiplexer
MUX Group 9: DebugReduction1 (Debug Reduction #1)
0:4 TR_GROUP8_INPUT[1:5]
MUX Group 10: DebugReduction2 (Debug Reduction #2)
0:4
TR_GROUP8_INPUT[6:10]
To main debug multiplexer
Datasheet
63
002-18043 Rev. *J
2022-09-08
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4F single
Triggers one-to-one
19
Triggers one-to-one
Table 19-1
Triggers 1:1
Input
Trigger In
Trigger Out
Description
MUX Group 0: TCPWM0 to LIN0 Triggers
0:7 TCPWM0_16_TR_OUT0[0:7]
MUX Group 1: TCPWM0 to PASS SARx direct connect
LIN0_CMD_TR_IN[0:7]
TCPWM0 (Group #0 Counter #00 to #07) to LIN0
0
1
TCPWM0_16M_TR_OUT1[0]
TCPWM0_16M_TR_OUT1[1]
TCPWM0_16M_TR_OUT1[2]
TCPWM0_16M_TR_OUT1[3]
TCPWM0_16_TR_OUT1[0:19]
PASS0_CH_TR_IN[0]
PASS0_CH_TR_IN[1]
PASS0_CH_TR_IN[2]
PASS0_CH_TR_IN[3]
PASS0_CH_TR_IN[4:23]
TCPWM0 Group #1 Counter #00 (PWM0_M_0) to SAR0 ch#0
TCPWM0 Group #1 Counter #03 (PWM0_M_3) to SAR0 ch#1
TCPWM0 Group #1 Counter #06 (PWM0_M_6) to SAR0 ch#2
TCPWM0 Group #1 Counter #09 (PWM0_M_9) to SAR0 ch#3
2
3
4:23
TCPWM0 Group #0 Counter #00 through 19 (PWM0_0 to PWM0_19) to
SAR0 ch#4 through SAR0 ch#23
24
25
TCPWM0_16M_TR_OUT1[4]
TCPWM0_16M_TR_OUT1[5]
TCPWM0_16M_TR_OUT1[6]
TCPWM0_16M_TR_OUT1[7]
TCPWM0_16_TR_OUT1[20:47]
PASS0_CH_TR_IN[32]
PASS0_CH_TR_IN[33]
PASS0_CH_TR_IN[34]
PASS0_CH_TR_IN[35]
PASS0_CH_TR_IN[36:63]
TCPWM0 Group #1 Counter #01 (PWM0_M_1) to SAR1 ch#0
TCPWM0 Group #1 Counter #04 (PWM0_M_4) to SAR1 ch#1
TCPWM0 Group #1 Counter #07 (PWM0_M_7) to SAR1 ch#2
TCPWM0 Group #1 Counter #10 (PWM0_M_10) to SAR1 ch#3
26
27
28:55
TCPWM0 Group #0 Counter #20 through 47 (PWM0_20 to PWM0_47) to
SAR1 ch#4 through SAR1 ch#31
56
57
TCPWM0_16M_TR_OUT1[8]
TCPWM0_16M_TR_OUT1[9]
TCPWM0_16M_TR_OUT1[10]
TCPWM0_16M_TR_OUT1[11]
TCPWM0_16_TR_OUT1[48:51]
PASS0_CH_TR_IN[64]
PASS0_CH_TR_IN[65]
PASS0_CH_TR_IN[66]
PASS0_CH_TR_IN[67]
PASS0_CH_TR_IN[68:71]
TCPWM0 Group #1 Counter #02 (PWM0_M_2) to SAR2 ch#0
TCPWM0 Group #1 Counter #05 (PWM0_M_5) to SAR2 ch#1
TCPWM0 Group #1 Counter #08 (PWM0_M_8) to SAR2 ch#2
TCPWM0 Group #1 Counter #11 (PWM0_M_11) to SAR2 ch#3
58
59
60:63
TCPWM0 Group #0 Counter #48 through 51 (PWM0_48 to PWM0_51) to
SAR2 ch#4 through SAR2 ch#7
MUX Group 2: PASS SARx to P-DMA0 direct connect
0:23
24:55
56:63
PASS0_CH_DONE_TR_OUT[0:23]
PASS0_CH_DONE_TR_OUT[32:63]
PASS0_CH_DONE_TR_OUT[64:71]
PDMA0_TR_IN[25:48]
PDMA0_TR_IN[49:80]
PDMA0_TR_IN[81:88]
PASS SAR0 [0:23] to P-DMA0 direct connect
PASS SAR1 [0:31] to P-DMA0 direct connect
PASS SAR2 [0:7] to P-DMA0 direct connect
MUX Group 3: PASS SARx to TCPWM0 direct connect
[33]
0
1
PASS0_CH_RANGEVIO_TR_OUT[0]
PASS0_CH_RANGEVIO_TR_OUT[1]
PASS0_CH_RANGEVIO_TR_OUT[2]
PASS0_CH_RANGEVIO_TR_OUT[3]
PASS0_CH_RANGEVIO_TR_OUT[4]
PASS0_CH_RANGEVIO_TR_OUT[5]
PASS0_CH_RANGEVIO_TR_OUT[6]
PASS0_CH_RANGEVIO_TR_OUT[7]
PASS0_CH_RANGEVIO_TR_OUT[8]
PASS0_CH_RANGEVIO_TR_OUT[9]
PASS0_CH_RANGEVIO_TR_OUT[10]
PASS0_CH_RANGEVIO_TR_OUT[11]
PASS0_CH_RANGEVIO_TR_OUT[12]
PASS0_CH_RANGEVIO_TR_OUT[13]
PASS0_CH_RANGEVIO_TR_OUT[14]
PASS0_CH_RANGEVIO_TR_OUT[15]
PASS0_CH_RANGEVIO_TR_OUT[16]
PASS0_CH_RANGEVIO_TR_OUT[17]
PASS0_CH_RANGEVIO_TR_OUT[18]
PASS0_CH_RANGEVIO_TR_OUT[19]
PASS0_CH_RANGEVIO_TR_OUT[20]
PASS0_CH_RANGEVIO_TR_OUT[21]
PASS0_CH_RANGEVIO_TR_OUT[22]
PASS0_CH_RANGEVIO_TR_OUT[23]
PASS0_CH_RANGEVIO_TR_OUT[32]
TCPWM0_16M_ONE_CNT_TR_IN[0]
TCPWM0_16M_ONE_CNT_TR_IN[3]
TCPWM0_16M_ONE_CNT_TR_IN[6]
TCPWM0_16M_ONE_CNT_TR_IN[9]
TCPWM0_16_ONE_CNT_TR_IN[0]
TCPWM0_16_ONE_CNT_TR_IN[1]
TCPWM0_16_ONE_CNT_TR_IN[2]
TCPWM0_16_ONE_CNT_TR_IN[3]
TCPWM0_16_ONE_CNT_TR_IN[4]
TCPWM0_16_ONE_CNT_TR_IN[5]
TCPWM0_16_ONE_CNT_TR_IN[6]
TCPWM0_16_ONE_CNT_TR_IN[7]
TCPWM0_16_ONE_CNT_TR_IN[8]
TCPWM0_16_ONE_CNT_TR_IN[9]
TCPWM0_16_ONE_CNT_TR_IN[10]
TCPWM0_16_ONE_CNT_TR_IN[11]
TCPWM0_16_ONE_CNT_TR_IN[12]
TCPWM0_16_ONE_CNT_TR_IN[13]
TCPWM0_16_ONE_CNT_TR_IN[14]
TCPWM0_16_ONE_CNT_TR_IN[15]
TCPWM0_16_ONE_CNT_TR_IN[16]
TCPWM0_16_ONE_CNT_TR_IN[17]
TCPWM0_16_ONE_CNT_TR_IN[18]
TCPWM0_16_ONE_CNT_TR_IN[19]
TCPWM0_16M_ONE_CNT_TR_IN[1]
SAR0 ch#0 , range violation to TCPWM0 Group #1 Counter #00 trig=2
SAR0 ch#1, range violation to TCPWM0 Group #1 Counter #03 trig=2
SAR0 ch#2, range violation to TCPWM0 Group #1 Counter #06 trig=2
SAR0 ch#3, range violation to TCPWM0 Group #1 Counter #09 trig=2
SAR0 ch#4, range violation to TCPWM0 Group #0 Counter #00 trig=2
SAR0 ch#5, range violation to TCPWM0 Group #0 Counter #01 trig=2
SAR0 ch#6, range violation to TCPWM0 Group #0 Counter #02 trig=2
SAR0 ch#7, range violation to TCPWM0 Group #0 Counter #03 trig=2
SAR0 ch#8, range violation to TCPWM0 Group #0 Counter #04 trig=2
SAR0 ch#9, range violation to TCPWM0 Group #0 Counter #05 trig=2
SAR0 ch#10, range violation to TCPWM0 Group #0 Counter #06 trig=2
SAR0 ch#11, range violation to TCPWM0 Group #0 Counter #07 trig=2
SAR0 ch#12, range violation to TCPWM0 Group #0 Counter #08 trig=2
SAR0 ch#13, range violation to TCPWM0 Group #0 Counter #09 trig=2
SAR0 ch#14, range violation to TCPWM0 Group #0 Counter #10 trig=2
SAR0 ch#15, range violation to TCPWM0 Group #0 Counter #11 trig=2
SAR0 ch#16, range violation to TCPWM0 Group #0 Counter #12 trig=2
SAR0 ch#17, range violation to TCPWM0 Group #0 Counter #13 trig=2
SAR0 ch#18, range violation to TCPWM0 Group #0 Counter #14 trig=2
SAR0 ch#19, range violation to TCPWM0 Group #0 Counter #15 trig=2
SAR0 ch#20, range violation to TCPWM0 Group #0 Counter #16 trig=2
SAR0 ch#21, range violation to TCPWM0 Group #0 Counter #17 trig=2
SAR0 ch#22, range violation to TCPWM0 Group #0 Counter #18 trig=2
SAR0 ch#23, range violation to TCPWM0 Group #0 Counter #19 trig=2
SAR1 ch#0, range violation to TCPWM0 Group #1 Counter #01 trig=2
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Note
33.Each logical channel of SAR ADC[x] can be connected to any of the SAR ADC[x]_y external pin. (x = 0, or 1, or, 2 and y=0 to max 31)
Datasheet
64
002-18043 Rev. *J
2022-09-08
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4F single
Triggers one-to-one
Table 19-1
Triggers 1:1 (continued)
Input
Trigger In
Trigger Out
Description
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
PASS0_CH_RANGEVIO_TR_OUT[33]
PASS0_CH_RANGEVIO_TR_OUT[34]
PASS0_CH_RANGEVIO_TR_OUT[35]
PASS0_CH_RANGEVIO_TR_OUT[36]
PASS0_CH_RANGEVIO_TR_OUT[37]
PASS0_CH_RANGEVIO_TR_OUT[38]
PASS0_CH_RANGEVIO_TR_OUT[39]
PASS0_CH_RANGEVIO_TR_OUT[40]
PASS0_CH_RANGEVIO_TR_OUT[41]
PASS0_CH_RANGEVIO_TR_OUT[42]
PASS0_CH_RANGEVIO_TR_OUT[43]
PASS0_CH_RANGEVIO_TR_OUT[44]
PASS0_CH_RANGEVIO_TR_OUT[45]
PASS0_CH_RANGEVIO_TR_OUT[46]
PASS0_CH_RANGEVIO_TR_OUT[47]
PASS0_CH_RANGEVIO_TR_OUT[48]
PASS0_CH_RANGEVIO_TR_OUT[49]
PASS0_CH_RANGEVIO_TR_OUT[50]
PASS0_CH_RANGEVIO_TR_OUT[51]
PASS0_CH_RANGEVIO_TR_OUT[52]
PASS0_CH_RANGEVIO_TR_OUT[53]
PASS0_CH_RANGEVIO_TR_OUT[54]
PASS0_CH_RANGEVIO_TR_OUT[55]
PASS0_CH_RANGEVIO_TR_OUT[56]
PASS0_CH_RANGEVIO_TR_OUT[57]
PASS0_CH_RANGEVIO_TR_OUT[58]
PASS0_CH_RANGEVIO_TR_OUT[59]
PASS0_CH_RANGEVIO_TR_OUT[60]
PASS0_CH_RANGEVIO_TR_OUT[61]
PASS0_CH_RANGEVIO_TR_OUT[62]
PASS0_CH_RANGEVIO_TR_OUT[63]
PASS0_CH_RANGEVIO_TR_OUT[64]
PASS0_CH_RANGEVIO_TR_OUT[65]
PASS0_CH_RANGEVIO_TR_OUT[66]
PASS0_CH_RANGEVIO_TR_OUT[67]
PASS0_CH_RANGEVIO_TR_OUT[68]
PASS0_CH_RANGEVIO_TR_OUT[69]
PASS0_CH_RANGEVIO_TR_OUT[70]
PASS0_CH_RANGEVIO_TR_OUT[71]
TCPWM0_16M_ONE_CNT_TR_IN[4]
TCPWM0_16M_ONE_CNT_TR_IN[7]
TCPWM0_16M_ONE_CNT_TR_IN[10]
TCPWM0_16_ONE_CNT_TR_IN[20]
TCPWM0_16_ONE_CNT_TR_IN[21]
TCPWM0_16_ONE_CNT_TR_IN[22]
TCPWM0_16_ONE_CNT_TR_IN[23]
TCPWM0_16_ONE_CNT_TR_IN[24]
TCPWM0_16_ONE_CNT_TR_IN[25]
TCPWM0_16_ONE_CNT_TR_IN[26]
TCPWM0_16_ONE_CNT_TR_IN[27]
TCPWM0_16_ONE_CNT_TR_IN[28]
TCPWM0_16_ONE_CNT_TR_IN[29]
TCPWM0_16_ONE_CNT_TR_IN[30]
TCPWM0_16_ONE_CNT_TR_IN[31]
TCPWM0_16_ONE_CNT_TR_IN[32]
TCPWM0_16_ONE_CNT_TR_IN[33]
TCPWM0_16_ONE_CNT_TR_IN[34]
TCPWM0_16_ONE_CNT_TR_IN[35]
TCPWM0_16_ONE_CNT_TR_IN[36]
TCPWM0_16_ONE_CNT_TR_IN[37]
TCPWM0_16_ONE_CNT_TR_IN[38]
TCPWM0_16_ONE_CNT_TR_IN[39]
TCPWM0_16_ONE_CNT_TR_IN[40]
TCPWM0_16_ONE_CNT_TR_IN[41]
TCPWM0_16_ONE_CNT_TR_IN[42]
TCPWM0_16_ONE_CNT_TR_IN[43]
TCPWM0_16_ONE_CNT_TR_IN[44]
TCPWM0_16_ONE_CNT_TR_IN[45]
TCPWM0_16_ONE_CNT_TR_IN[46]
TCPWM0_16_ONE_CNT_TR_IN[47]
TCPWM0_16M_ONE_CNT_TR_IN[2]
TCPWM0_16M_ONE_CNT_TR_IN[5]
TCPWM0_16M_ONE_CNT_TR_IN[8]
TCPWM0_16M_ONE_CNT_TR_IN[11]
TCPWM0_16_ONE_CNT_TR_IN[48]
TCPWM0_16_ONE_CNT_TR_IN[49]
TCPWM0_16_ONE_CNT_TR_IN[50]
TCPWM0_16_ONE_CNT_TR_IN[51]
SAR1 ch#1, range violation to TCPWM0 Group #1 Counter #04 trig=2
SAR1 ch#2, range violation to TCPWM0 Group #1 Counter #07 trig=2
SAR1 ch#3, range violation to TCPWM0 Group #1 Counter #10 trig=2
SAR1 ch#4, range violation to TCPWM0 Group #0 Counter #20 trig=2
SAR1 ch#5, range violation to TCPWM0 Group #0 Counter #21 trig=2
SAR1 ch#6, range violation to TCPWM0 Group #0 Counter #22 trig=2
SAR1 ch#7, range violation to TCPWM0 Group #0 Counter #23 trig=2
SAR1 ch#8, range violation to TCPWM0 Group #0 Counter #24 trig=2
SAR1 ch#9, range violation to TCPWM0 Group #0 Counter #25 trig=2
SAR1 ch#10, range violation to TCPWM0 Group #0 Counter #26 trig=2
SAR1 ch#11, range violation to TCPWM0 Group #0 Counter #27 trig=2
SAR1 ch#12, range violation to TCPWM0 Group #0 Counter #28 trig=2
SAR1 ch#13, range violation to TCPWM0 Group #0 Counter #29 trig=2
SAR1 ch#14, range violation to TCPWM0 Group #0 Counter #30 trig=2
SAR1 ch#15, range violation to TCPWM0 Group #0 Counter #31 trig=2
SAR1 ch#16, range violation to TCPWM0 Group #0 Counter #32 trig=2
SAR1 ch#17, range violation to TCPWM0 Group #0 Counter #33 trig=2
SAR1 ch#18, range violation to TCPWM0 Group #0 Counter #34 trig=2
SAR1 ch#19, range violation to TCPWM0 Group #0 Counter #35 trig=2
SAR1 ch#20, range violation to TCPWM0 Group #0 Counter #36 trig=2
SAR1 ch#21, range violation to TCPWM0 Group #0 Counter #37 trig=2
SAR1 ch#22, range violation to TCPWM0 Group #0 Counter #38 trig=2
SAR1 ch#23, range violation to TCPWM0 Group #0 Counter #39 trig=2
SAR1 ch#24, range violation to TCPWM0 Group #0 Counter #40 trig=2
SAR1 ch#25, range violation to TCPWM0 Group #0 Counter #41 trig=2
SAR1 ch#26, range violation to TCPWM0 Group #0 Counter #42 trig=2
SAR1 ch#27, range violation to TCPWM0 Group #0 Counter #43 trig=2
SAR1 ch#28, range violation to TCPWM0 Group #0 Counter #44 trig=2
SAR1 ch#29, range violation to TCPWM0 Group #0 Counter #45 trig=2
SAR1 ch#30, range violation to TCPWM0 Group #0 Counter #46 trig=2
SAR1 ch#31, range violation to TCPWM0 Group #0 Counter #47 trig=2
SAR2 ch#0, range violation to TCPWM0 Group #1 Counter #02 trig=2
SAR2 ch#1, range violation to TCPWM0 Group #1 Counter #05 trig=2
SAR2 ch#2, range violation to TCPWM0 Group #1 Counter #08 trig=2
SAR2 ch#3, range violation to TCPWM0 Group #1 Counter #11 trig=2
SAR2 ch#4, range violation to TCPWM0 Group #0 Counter #48 trig=2
SAR2 ch#5, range violation to TCPWM0 Group #0 Counter #49 trig=2
SAR2 ch#6, range violation to TCPWM0 Group #0 Counter #50 trig=2
SAR2 ch#7, range violation to TCPWM0 Group #0 Counter #51 trig=2
MUX Group 4: CAN0 to P-DMA0 Triggers
0
1
2
3
4
5
6
7
8
CAN0_DBG_TR_OUT[0]
CAN0_FIFO0_TR_OUT[0]
CAN0_FIFO1_TR_OUT[0]
CAN0_DBG_TR_OUT[1]
CAN0_FIFO0_TR_OUT[1]
CAN0_FIFO1_TR_OUT[1]
CAN0_DBG_TR_OUT[2]
CAN0_FIFO0_TR_OUT[2]
CAN0_FIFO1_TR_OUT[2]
PDMA0_TR_IN[16]
PDMA0_TR_IN[17]
PDMA0_TR_IN[18]
PDMA0_TR_IN[19]
PDMA0_TR_IN[20]
PDMA0_TR_IN[21]
PDMA0_TR_IN[22]
PDMA0_TR_IN[23]
PDMA0_TR_IN[24]
CAN0, Channel #0 P-DMA0 trigger
CAN0, Channel #0 FIFO0 trigger
CAN0, Channel #0 FIFO1 trigger
CAN0, Channel #1 P-DMA0 trigger
CAN0, Channel #1 FIFO0 trigger
CAN0, Channel #1 FIFO1 trigger
CAN0, Channel #2 P-DMA0 trigger
CAN0, Channel #2 FIFO0 trigger
CAN0, Channel #2 FIFO1 trigger
MUX Group 5: CAN1 to P-DMA1 triggers
0
1
2
3
4
CAN1_DBG_TR_OUT[0]
CAN1_FIFO0_TR_OUT[0]
CAN1_FIFO1_TR_OUT[0]
CAN1_DBG_TR_OUT[1]
CAN1_FIFO0_TR_OUT[1]
PDMA1_TR_IN[24]
PDMA1_TR_IN[25]
PDMA1_TR_IN[26]
PDMA1_TR_IN[27]
PDMA1_TR_IN[28]
CAN1, Channel #0 P-DMA01 trigger
CAN1, Channel #0 FIFO0 trigger
CAN1, Channel #0 FIFO1 trigger
CAN1, Channel #1 P-DMA1 trigger
CAN1, Channel #1 FIFO0 trigger
Datasheet
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4F single
Triggers one-to-one
Table 19-1
Triggers 1:1 (continued)
Input
Trigger In
Trigger Out
Description
CAN1, Channel #1 FIFO1 trigger
5
6
7
8
CAN1_FIFO1_TR_OUT[1]
CAN1_DBG_TR_OUT[2]
PDMA1_TR_IN[29]
PDMA1_TR_IN[30]
PDMA1_TR_IN[31]
PDMA1_TR_IN[32]
CAN1, Channel #2 P-DMA1 trigger
CAN1, Channel #2 FIFO0 trigger
CAN1, Channel #2 FIFO1 trigger
CAN1_FIFO0_TR_OUT[2]
CAN1_FIFO1_TR_OUT[2]
MUX Group 6:Acknowledge triggers from P-DMA0 to CAN0
0
1
2
PDMA0_TR_OUT[16]
PDMA0_TR_OUT[19]
PDMA0_TR_OUT[22]
CAN0_DBG_TR_ACK[0]
CAN0_DBG_TR_ACK[1]
CAN0_DBG_TR_ACK[2]
CAN0, Channel #0 P-DMA0 acknowledge
CAN0, Channel #1 P-DMA0 acknowledge
CAN0, Channel #2 P-DMA0 acknowledge
MUX Group 7: Acknowledge triggers from P-DMA1 to CAN1
0
1
2
PDMA1_TR_OUT[24]
PDMA1_TR_OUT[27]
PDMA1_TR_OUT[30]
CAN1_DBG_TR_ACK[0]
CAN1_DBG_TR_ACK[1]
CAN1_DBG_TR_ACK[2]
CAN1, Channel #0 P-DMA1 acknowledge
CAN1, Channel #1 P-DMA1 acknowledge
CAN1, Channel #2 P-DMA1 acknowledge
MUX Group 8: SCBx to P-DMA1 Triggers
0
1
SCB0_TX_TR_OUT
SCB0_RX_TR_OUT
SCB1_TX_TR_OUT
SCB1_RX_TR_OUT
SCB2_TX_TR_OUT
SCB2_RX_TR_OUT
SCB3_TX_TR_OUT
SCB3_RX_TR_OUT
SCB4_TX_TR_OUT
SCB4_RX_TR_OUT
SCB5_TX_TR_OUT
SCB5_RX_TR_OUT
SCB6_TX_TR_OUT
SCB6_RX_TR_OUT
SCB7_TX_TR_OUT
SCB7_RX_TR_OUT
PDMA1_TR_IN[8]
PDMA1_TR_IN[9]
PDMA1_TR_IN[10]
PDMA1_TR_IN[11]
PDMA1_TR_IN[12]
PDMA1_TR_IN[13]
PDMA1_TR_IN[14]
PDMA1_TR_IN[15]
PDMA1_TR_IN[16]
PDMA1_TR_IN[17]
PDMA1_TR_IN[18]
PDMA1_TR_IN[19]
PDMA1_TR_IN[20]
PDMA1_TR_IN[21]
PDMA1_TR_IN[22]
PDMA1_TR_IN[23]
SCB0 TX to P-DMA1 Trigger
SCB0 RX to P-DMA1 Trigger
SCB1 TX to P-DMA1 Trigger
SCB1 RX to P-DMA1 Trigger
SCB2 TX to P-DMA1 Trigger
SCB2 RX to P-DMA1 Trigger
SCB3 TX to P-DMA1 Trigger
SCB3 RX to P-DMA1 Trigger
SCB4 TX to P-DMA1 Trigger
SCB4 RX to P-DMA1 Trigger
SCB5 TX to P-DMA1 Trigger
SCB5 RX to P-DMA1 Trigger
SCB6 TX to P-DMA1 Trigger
SCB6 RX to P-DMA1 Trigger
SCB7 TX to P-DMA1 Trigger
SCB7 RX to P-DMA1 Trigger
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Datasheet
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4F single
Peripheral clocks
20
Peripheral clocks
Table 20-1
Peripheral clock assignments
Output
0
Destination
PCLK_CPUSS_CLOCK_TRACE_IN
PCLK_SMARTIO12_CLOCK
PCLK_SMARTIO13_CLOCK
PCLK_SMARTIO14_CLOCK
PCLK_SMARTIO15_CLOCK
PCLK_SMARTIO16_CLOCK
PCLK_CANFD0_CLOCK_CAN0
PCLK_CANFD0_CLOCK_CAN1
PCLK_CANFD0_CLOCK_CAN2
PCLK_CANFD1_CLOCK_CAN0
PCLK_CANFD1_CLOCK_CAN1
PCLK_CANFD1_CLOCK_CAN2
PCLK_LIN0_CLOCK_CH_EN0
PCLK_LIN0_CLOCK_CH_EN1
PCLK_LIN0_CLOCK_CH_EN2
PCLK_LIN0_CLOCK_CH_EN3
PCLK_LIN0_CLOCK_CH_EN4
PCLK_LIN0_CLOCK_CH_EN5
PCLK_LIN0_CLOCK_CH_EN6
PCLK_LIN0_CLOCK_CH_EN7
PCLK_SCB0_CLOCK
PCLK_SCB1_CLOCK
PCLK_SCB2_CLOCK
PCLK_SCB3_CLOCK
PCLK_SCB4_CLOCK
PCLK_SCB5_CLOCK
PCLK_SCB6_CLOCK
PCLK_SCB7_CLOCK
PCLK_PASS0_CLOCK_SAR0
PCLK_PASS0_CLOCK_SAR1
PCLK_PASS0_CLOCK_SAR2
PCLK_TCPWM0_CLOCKS0
PCLK_TCPWM0_CLOCKS1
PCLK_TCPWM0_CLOCKS2
PCLK_TCPWM0_CLOCKS3
PCLK_TCPWM0_CLOCKS4
PCLK_TCPWM0_CLOCKS5
PCLK_TCPWM0_CLOCKS6
PCLK_TCPWM0_CLOCKS7
Description
Trace clock
1
2
3
4
5
6
7
8
SMART I/O #12
SMART I/O #13
SMART I/O #14
SMART I/O #15
SMART I/O #16
CAN0, Channel #0
CAN0, Channel #1
CAN0, Channel #2
CAN1, Channel #0
CAN1, Channel #1
CAN1, Channel #2
LIN0, Channel #0
LIN0, Channel #1
LIN0, Channel #2
LIN0, Channel #3
LIN0, Channel #4
LIN0, Channel #5
LIN0, Channel #6
LIN0, Channel #7
SCB0
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
SCB1
SCB2
SCB3
SCB4
SCB5
SCB6
SCB7
SAR0
SAR1
SAR2
TCPWM0 Group #0, Counter #0
TCPWM0 Group #0, Counter #1
TCPWM0 Group #0, Counter #2
TCPWM0 Group #0, Counter #3
TCPWM0 Group #0, Counter #4
TCPWM0 Group #0, Counter #5
TCPWM0 Group #0, Counter #6
TCPWM0 Group #0, Counter #7
Datasheet
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4F single
Peripheral clocks
Table 20-1
Peripheral clock assignments (continued)
Output
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
Destination
PCLK_TCPWM0_CLOCKS8
PCLK_TCPWM0_CLOCKS9
PCLK_TCPWM0_CLOCKS10
PCLK_TCPWM0_CLOCKS11
PCLK_TCPWM0_CLOCKS12
PCLK_TCPWM0_CLOCKS13
PCLK_TCPWM0_CLOCKS14
PCLK_TCPWM0_CLOCKS15
PCLK_TCPWM0_CLOCKS16
PCLK_TCPWM0_CLOCKS17
PCLK_TCPWM0_CLOCKS18
PCLK_TCPWM0_CLOCKS19
PCLK_TCPWM0_CLOCKS20
PCLK_TCPWM0_CLOCKS21
PCLK_TCPWM0_CLOCKS22
PCLK_TCPWM0_CLOCKS23
PCLK_TCPWM0_CLOCKS24
PCLK_TCPWM0_CLOCKS25
PCLK_TCPWM0_CLOCKS26
PCLK_TCPWM0_CLOCKS27
PCLK_TCPWM0_CLOCKS28
PCLK_TCPWM0_CLOCKS29
PCLK_TCPWM0_CLOCKS30
PCLK_TCPWM0_CLOCKS31
PCLK_TCPWM0_CLOCKS32
PCLK_TCPWM0_CLOCKS33
PCLK_TCPWM0_CLOCKS34
PCLK_TCPWM0_CLOCKS35
PCLK_TCPWM0_CLOCKS36
PCLK_TCPWM0_CLOCKS37
PCLK_TCPWM0_CLOCKS38
PCLK_TCPWM0_CLOCKS39
PCLK_TCPWM0_CLOCKS40
PCLK_TCPWM0_CLOCKS41
PCLK_TCPWM0_CLOCKS42
PCLK_TCPWM0_CLOCKS43
PCLK_TCPWM0_CLOCKS44
PCLK_TCPWM0_CLOCKS45
PCLK_TCPWM0_CLOCKS46
PCLK_TCPWM0_CLOCKS47
PCLK_TCPWM0_CLOCKS48
Description
TCPWM0 Group #0, Counter #8
TCPWM0 Group #0, Counter #9
TCPWM0 Group #0, Counter #10
TCPWM0 Group #0, Counter #11
TCPWM0 Group #0, Counter #12
TCPWM0 Group #0, Counter #13
TCPWM0 Group #0, Counter #14
TCPWM0 Group #0, Counter #15
TCPWM0 Group #0, Counter #16
TCPWM0 Group #0, Counter #17
TCPWM0 Group #0, Counter #18
TCPWM0 Group #0, Counter #19
TCPWM0 Group #0, Counter #20
TCPWM0 Group #0, Counter #21
TCPWM0 Group #0, Counter #22
TCPWM0 Group #0, Counter #23
TCPWM0 Group #0, Counter #24
TCPWM0 Group #0, Counter #25
TCPWM0 Group #0, Counter #26
TCPWM0 Group #0, Counter #27
TCPWM0 Group #0, Counter #28
TCPWM0 Group #0, Counter #29
TCPWM0 Group #0, Counter #30
TCPWM0 Group #0, Counter #31
TCPWM0 Group #0, Counter #32
TCPWM0 Group #0, Counter #33
TCPWM0 Group #0, Counter #34
TCPWM0 Group #0, Counter #35
TCPWM0 Group #0, Counter #36
TCPWM0 Group #0, Counter #37
TCPWM0 Group #0, Counter #38
TCPWM0 Group #0, Counter #39
TCPWM0 Group #0, Counter #40
TCPWM0 Group #0, Counter #41
TCPWM0 Group #0, Counter #42
TCPWM0 Group #0, Counter #43
TCPWM0 Group #0, Counter #44
TCPWM0 Group #0, Counter #45
TCPWM0 Group #0, Counter #46
TCPWM0 Group #0, Counter #47
TCPWM0 Group #0, Counter #48
Datasheet
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4F single
Peripheral clocks
Table 20-1
Peripheral clock assignments (continued)
Output
80
Destination
PCLK_TCPWM0_CLOCKS49
PCLK_TCPWM0_CLOCKS50
PCLK_TCPWM0_CLOCKS51
PCLK_TCPWM0_CLOCKS52
PCLK_TCPWM0_CLOCKS53
PCLK_TCPWM0_CLOCKS54
PCLK_TCPWM0_CLOCKS55
PCLK_TCPWM0_CLOCKS56
PCLK_TCPWM0_CLOCKS57
PCLK_TCPWM0_CLOCKS58
PCLK_TCPWM0_CLOCKS59
PCLK_TCPWM0_CLOCKS60
PCLK_TCPWM0_CLOCKS61
PCLK_TCPWM0_CLOCKS62
PCLK_TCPWM0_CLOCKS256
PCLK_TCPWM0_CLOCKS257
PCLK_TCPWM0_CLOCKS258
PCLK_TCPWM0_CLOCKS259
PCLK_TCPWM0_CLOCKS260
PCLK_TCPWM0_CLOCKS261
PCLK_TCPWM0_CLOCKS262
PCLK_TCPWM0_CLOCKS263
PCLK_TCPWM0_CLOCKS264
PCLK_TCPWM0_CLOCKS265
PCLK_TCPWM0_CLOCKS266
PCLK_TCPWM0_CLOCKS267
PCLK_TCPWM0_CLOCKS512
PCLK_TCPWM0_CLOCKS513
PCLK_TCPWM0_CLOCKS514
PCLK_TCPWM0_CLOCKS515
Description
TCPWM0 Group #0, Counter #49
TCPWM0 Group #0, Counter #50
TCPWM0 Group #0, Counter #51
TCPWM0 Group #0, Counter #52
TCPWM0 Group #0, Counter #53
TCPWM0 Group #0, Counter #54
TCPWM0 Group #0, Counter #55
TCPWM0 Group #0, Counter #56
TCPWM0 Group #0, Counter #57
TCPWM0 Group #0, Counter #58
TCPWM0 Group #0, Counter #59
TCPWM0 Group #0, Counter #60
TCPWM0 Group #0, Counter #61
TCPWM0 Group #0, Counter #62
TCPWM0 Group #1, Counter #0
TCPWM0 Group #1, Counter #1
TCPWM0 Group #1, Counter #2
TCPWM0 Group #1, Counter #3
TCPWM0 Group #1, Counter #4
TCPWM0 Group #1, Counter #5
TCPWM0 Group #1, Counter #6
TCPWM0 Group #1, Counter #7
TCPWM0 Group #1, Counter #8
TCPWM0 Group #1, Counter #9
TCPWM0 Group #1, Counter #10
TCPWM0 Group #1, Counter #11
TCPWM0 Group #2, Counter #0
TCPWM0 Group #2, Counter #1
TCPWM0 Group #2, Counter #2
TCPWM0 Group #2, Counter #3
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
Datasheet
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4F single
Faults
21
Faults
Table 21-1
Fault Assignments
Fault
Source
Description
CM0+ SMPU violation
DATA0[31:0]: Violating address.
DATA1[0]: User read.
DATA1[1]: User write.
DATA1[2]: User execute.
DATA1[3]: Privileged read.
DATA1[4]: Privileged write.
DATA1[5]: Privileged execute.
DATA1[6]: Non-secure.
0
CPUSS_MPU_VIO_0
DATA1[11:8]: Master identifier.
DATA1[15:12]: Protection context identifier.
DATA1[31]: '0' MPU violation; '1': SMPU violation.
1
2
CPUSS_MPU_VIO_1
Crypto SMPU violation. See CPUSS_MPU_VIO_0 description.
CPUSS_MPU_VIO_2
CPUSS_MPU_VIO_3
CPUSS_MPU_VIO_4
CPUSS_MPU_VIO_15
CPUSS_MPU_VIO_16
P-DMA0 MPU/SMPU violation. See CPUSS_MPU_VIO_0 description.
P-DMA1 MPU/SMPU violation. See CPUSS_MPU_VIO_0 description.
M-DMA0 MPU/SMPU violation. See CPUSS_MPU_VIO_0 description.
Test Controller MPU/SMPU violation. See CPUSS_MPU_VIO_0 description.
CM4 system bus AHB-Lite interface MPU violation. See CPUSS_MPU_VIO_0 description.
3
4
15
16
CM4 code bus AHB-Lite interface MPU violation for non flash controller accesses.
See CPUSS_MPU_VIO_0 description.
17
18
CPUSS_MPU_VIO_17
CPUSS_MPU_VIO_18
CM4 code bus AHB-Lite interface MPU violation for flash controller accesses.
See CPUSS_MPU_VIO_0 description.
Peripheral protection SRAM correctable ECC violation
DATA0[10:0]: Violating address.
26
27
PERI_PERI_C_ECC
DATA1[7:0]: Syndrome of SRAM word.
PERI_PERI_NC_ECC
PERI_MS_VIO_0
Peripheral protection SRAM non-correctable ECC violation
CM0+ Peripheral Master Interface PPU violation
DATA0[31:0]: Violating address.
DATA1[0]: User read.
DATA1[1]: User write.
DATA1[2]: User execute.
DATA1[3]: Privileged read.
28
DATA1[4]: Privileged write.
DATA1[5]: Privileged execute.
DATA1[6]: Non-secure.
DATA1[11:8]: Master identifier.
DATA1[15:12]: Protection context identifier.
DATA1[31:28]: “0”: master interface, PPU violation, “1': timeout detected, “2”: bus error, other:
undefined.
PERI_MS_VIO_1
PERI_MS_VIO_2
PERI_MS_VIO_3
PERI_GROUP_VIO_0
CM4 Peripheral Master Interface PPU violation.
See PERI_MS_VIO_0 description.
29
30
31
P-DMA0 Peripheral Master Interface PPU violation.
See PERI_MS_VIO_0 description.
P-DMA1 Peripheral Master Interface PPU violation.
See PERI_MS_VIO_0 description.
Peripheral Group #0 violation.
DATA0[31:0]: Violating address.
DATA1[0]: User read.
DATA1[1]: User write.
DATA1[2]: User execute.
DATA1[3]: Privileged read.
32
DATA1[4]: Privileged write.
DATA1[5]: Privileged execute.
DATA1[6]: Non-secure.
DATA1[11:8]: Master identifier.
DATA1[15:12]: Protection context identifier.
DATA1[31:28]: “0”: decoder or peripheral bus error, other: undefined.
PERI_GROUP_VIO_1
PERI_GROUP_VIO_2
PERI_GROUP_VIO_3
PERI_GROUP_VIO_5
PERI_GROUP_VIO_6
PERI_GROUP_VIO_9
33
34
35
37
38
41
Peripheral Group #1 violation. See PERI_GROUP_VIO_0 description.
Peripheral Group #2 violation. See PERI_GROUP_VIO_0 description.
Peripheral Group #3 violation. See PERI_GROUP_VIO_0 description.
Peripheral Group #5 violation. See PERI_GROUP_VIO_0 description.
Peripheral Group #6 violation. See PERI_GROUP_VIO_0 description.
Peripheral Group #9 violation. See PERI_GROUP_VIO_0 description.
Datasheet
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4F single
Faults
Table 21-1
Fault Assignments (continued)
Fault
Source
Description
CPUSS_FLASHC_MAIN_BUS_ERROR
Flash controller main flash bus error
FAULT_DATA0[26:0]: Violating address. Append 5'b00010 as most significant bits to derive
32-bit system address.
48
49
FAULT_DATA1[11:8]: Master identifier.
CPUSS_FLASHC_MAIN_C_ECC
Flash controller main flash correctable ECC violation
DATA[26:0]: Violating address. Append 5'b00010 as most significant bits to derive 32-bit system
address.
DATA1[7:0]: Syndrome of 64-bit word (at address offset 0x00).
DATA1[15:8]: Syndrome of 64-bit word (at address offset 0x08).
DATA1[23:16]: Syndrome of 64-bit word (at address offset 0x10).
DATA1[31:24]: Syndrome of 64-bit word (at address offset 0x18).
CPUSS_FLASHC_MAIN_NC_ECC
CPUSS_FLASHC_WORK_BUS_ERROR
CPUSS_FLASHC_WORK_C_ECC
Flash controller main flash non-correctable ECC violation.
See CPUSS_FLASHC_MAIN_C_ECC description.
50
51
Flash controller work-flash bus error.
See CPUSS_FLASHC_MAIN_BUS_ERR description.
Flash controller work flash correctable ECC violation.
DATA0[26:0]: Violating address. Append 5'b00010 as most significant bits to derive 32-bit
system address.
52
53
DATA1[6:0]: Syndrome of 32-bit word.
CPUSS_FLASHC_WORK_NC_ECC
CPUSS_FLASHC_CM0_CA_C_ECC
Flash controller work-flash non-correctable ECC violation.
See CPUSS_FLASHC_WORK_C_ECC description.
Flash controller CM0+ cache correctable ECC violation.
DATA0[26:0]: Violating address.
DATA1[6:0]: Syndrome of 32-bit SRAM word (at address offset 0x0).
DATA1[14:8]: Syndrome of 32-bit SRAM word (at address offset 0x4).
DATA1[22:16]: Syndrome of 32-bit SRAM word (at address offset 0x8).
DATA1[30:24]: Syndrome of 32-bit SRAM word (at address offset 0xc).
54
CPUSS_FLASHC_CM0_CA_NC_ECC
CPUSS_FLASHC_CM4_CA_C_ECC
CPUSS_FLASHC_CM4_CA_NC_ECC
CPUSS_RAMC0_C_ECC
Flash controller CM0+ cache non-correctable ECC violation.
See CPUSS_FLASHC_CM0_CA_C_ECC description.
55
56
57
Flash controller CM4 cache correctable ECC violation.
See CPUSS_FLASHC_CM0_CA_C_ECC description.
Flash controller CM4 cache non-correctable ECC violation.
See CPUSS_FLASHC_CM0_CA_C_ECC description.
System memory controller 0 correctable ECC violation:
DATA0[31:0]: Violating address.
58
DATA1[6:0]: Syndrome of 32-bit SRAM code word.
CPUSS_RAMC0_NC_ECC
CPUSS_RAMC1_C_ECC
CPUSS_RAMC1_NC_ECC
CPUSS_CRYPTO_C_ECC
System memory controller 0 non-correctable ECC violation.
See CPUSS_RAMC0_C_ECC description.
59
60
61
System memory controller 1 correctable ECC violation.
See CPUSS_RAMC0_C_ECC description.
System memory controller 1 non-correctable ECC violation.
See CPUSS_RAMC0_C_ECC description.
Crypto memory correctable ECC violation.
DATA0[31:0]: Violating address.
DATA1[6:0]: Syndrome of Least Significant 32-bit SRAM.
DATA1[14:8]: Syndrome of Most Significant 32-bit SRAM.
64
65
70
CPUSS_CRYPTO_NC_ECC
CPUSS_DW0_C_ECC
Crypto memory non-correctable ECC violation.
See CPUSS_CRYPTO_C_ECC description.
P-DMA0 memory correctable ECC violation:
DATA0[11:0]: Violating DW SRAM address
(word address, assuming byte addressable).
DATA1[6:0]: Syndrome of 32-bit SRAM code word.
CPUSS_DW0_NC_ECC
CPUSS_DW1_C_ECC
P-DMA0 memory non-correctable ECC violation.
See CPUSS_DW0_C_ECC description.
71
72
73
P-DMA1 memory correctable ECC violation.
See CPUSS_DW0_C_ECC description.
CPUSS_DW1_NC_ECC
CPUSS_FM_SRAM_C_ECC
P-DMA1 memory non-correctable ECC violation.
See CPUSS_DW0_C_ECC description.
Flash code storage SRAM memory correctable ECC violation:
DATA0[15:0]: Address location in the eCT Flash SRAM.
DATA1[6:0]: Syndrome of 32-bit SRAM word.
74
75
CPUSS_FM_SRAM_NC_ECC
CANFD_0_CAN_C_ECC
Flash code storage SRAM memory non-correctable ECC violation:
See CPUSS_FM_SRAMC_C_ECC description.
CAN0 message buffer correctable ECC violation:
DATA0[15:0]: Violating address.
80
DATA0[22:16]: ECC violating data[38:32] from MRAM.
DATA0[27:24]: Master ID: 0-7 = CAN channel ID within mxttcanfd cluster, 8 = AHB I/F
DATA1[31:0]: ECC violating data[31:0] from MRAM.
Datasheet
71
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4F single
Faults
Table 21-1
Fault Assignments (continued)
Fault
Source
Description
CAN0 message buffer non-correctable ECC violation:
DATA0[15:0]: Violating address.
DATA0[22:16]: ECC violating data[38:32] from MRAM (not for Address Error).
DATA0[27:24]: Master ID: 0-7 = CAN channel ID within mxttcanfd cluster, 8 = AHB I/F
DATA0[30]: Write access, only possible for Address Error
DATA0[31]: Address Error: a CAN channel did an MRAM access above MRAM_SIZE
DATA1[31:0]: ECC violating data[31:0] from MRAM (not for Address Error).
81
CANFD_0_CAN_NC_ECC
CAN1 message buffer correctable ECC violation.
See CANFD_0_CAN_C_ECC description.
82
83
CANFD_1_CAN_C_ECC
CANFD_1_CAN_NC_ECC
CAN1 message buffer non-correctable ECC violation.
See CANFD_0_CAN_NC_ECC description.
Consolidated fault output for clock supervisors. Multiple CSV can detect a violation at the same
time.
DATA0[15:0]: CLK_HF* root CSV violation flags.
DATA0[24]: CLK_REF CSV violation flag (reference clock for CLK_HF CSVs)
DATA0[25]: CLK_LF CSV violation flag
90
91
SRSS_FAULT_CSV
SRSS_FAULT_SSV
DATA0[26]: CLK_HVILO CSV violation flag
Consolidated fault output for supply supervisors. Multiple CSV can detect a violation at the
same time.
DATA0[0]: BOD on VDDA
DATA[1]: OVD on VDDA
DATA[16]: LVD/HVD #1
DATA0[17]: LVD/HVD #2
Fault output for MCWDT0 (all sub-counters) Multiple counters can detect a violation at the
same time.
DATA0[0]: MCWDT sub counter 0 LOWER_LIMIT
DATA0[1]: MCWDT sub counter 0 UPPER_LIMIT
DATA0[2]: MCWDT sub counter 1 LOWER_LIMIT
DATA0[3]: MCWDT sub counter 1 UPPER_LIMIT
92
93
SRSS_FAULT_MCWDT0
SRSS_FAULT_MCWDT1
Fault output for MCWDT1 (all sub-counters).
See SRSS_FAULT_MCWDT0 description.
Datasheet
72
002-18043 Rev. *J
2022-09-08
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4F single
Peripheral Protection Unit Fixed Structure
Pairs
22
Peripheral Protection Unit Fixed Structure Pairs
Protection pair is a pair PPU structures, a master and a slave structure. The master structure protects the slave
structure, and the slave structure protects resources such as peripheral registers, or the peripheral itself.
Table 22-1
PPU Fixed Structure Pairs
Pair No.
PPU Fixed Structure Pair
Address
Size
Description
Peripheral Interconnect main
Peripheral interconnect secure
Peripheral Group #0 main
Peripheral Group #1 main
Peripheral Group #2 main
Peripheral Group #3 main
Peripheral Group #5 main
Peripheral Group #6 main
Peripheral Group #9 main
Peripheral trigger multiplexer
Crypto main
PERI_MS_PPU_FX_PERI_MAIN
PERI_MS_PPU_FX_PERI_SECURE
0x40000000
0x40002000
0x40004010
0x40004030
0x40004050
0x40004060
0x400040A0
0x400040C0
0x40004120
0x40008000
0x40100000
0x40101000
0x40102000
0x40102100
0x40102120
0x40108000
0x40200000
0x40201000
0x40202000
0x40208000
0x4020A000
0x40210000
0x40210100
0x40210200
0x40210300
0x40220000
0x40220020
0x40220040
0x40220060
0x40220080
0x402200A0
0x402200C0
0x402200E0
0x40221000
0x40221020
0x40221040
0x40221060
0x40221080
0x402210A0
0x00002000
0x00000004
0x00000004
0x00000004
0x00000004
0x00000020
0x00000020
0x00000020
0x00000020
0x00008000
0x00000400
0x00000800
0x00000100
0x00000004
0x00000004
0x00002000
0x00000400
0x00001000
0x00000200
0x00000800
0x00000800
0x00000100
0x00000100
0x00000100
0x00000100
0x00000020
0x00000020
0x00000020
0x00000020
0x00000020
0x00000020
0x00000020
0x00000020
0x00000010
0x00000010
0x00000010
0x00000010
0x00000010
0x00000010
0
1
PERI_MS_PPU_FX_PERI_GR0_GROUP
PERI_MS_PPU_FX_PERI_GR1_GROUP
PERI_MS_PPU_FX_PERI_GR2_GROUP
PERI_MS_PPU_FX_PERI_GR3_GROUP
PERI_MS_PPU_FX_PERI_GR5_GROUP
PERI_MS_PPU_FX_PERI_GR6_GROUP
PERI_MS_PPU_FX_PERI_GR9_GROUP
PERI_MS_PPU_FX_PERI_TR
2
3
4
5
6
7
8
9
PERI_MS_PPU_FX_CRYPTO_MAIN
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
PERI_MS_PPU_FX_CRYPTO_CRYPTO
PERI_MS_PPU_FX_CRYPTO_BOOT
Crypto MMIO (Memory Mapped I/O)
Crypto boot
PERI_MS_PPU_FX_CRYPTO_KEY0
Crypto Key #0
PERI_MS_PPU_FX_CRYPTO_KEY1
Crypto Key #1
PERI_MS_PPU_FX_CRYPTO_BUF
Crypto buffer
PERI_MS_PPU_FX_CPUSS_CM4
CM4 CPU core
PERI_MS_PPU_FX_CPUSS_CM0
CM0+ CPU core
PERI_MS_PPU_FX_CPUSS_BOOT[34]
PERI_MS_PPU_FX_CPUSS_CM0_INT
PERI_MS_PPU_FX_CPUSS_CM4_INT
PERI_MS_PPU_FX_FAULT_STRUCT0_MAIN
PERI_MS_PPU_FX_FAULT_STRUCT1_MAIN
PERI_MS_PPU_FX_FAULT_STRUCT2_MAIN
PERI_MS_PPU_FX_FAULT_STRUCT3_MAIN
PERI_MS_PPU_FX_IPC_STRUCT0_IPC
PERI_MS_PPU_FX_IPC_STRUCT1_IPC
PERI_MS_PPU_FX_IPC_STRUCT2_IPC
PERI_MS_PPU_FX_IPC_STRUCT3_IPC
PERI_MS_PPU_FX_IPC_STRUCT4_IPC
PERI_MS_PPU_FX_IPC_STRUCT5_IPC
PERI_MS_PPU_FX_IPC_STRUCT6_IPC
PERI_MS_PPU_FX_IPC_STRUCT7_IPC
PERI_MS_PPU_FX_IPC_INTR_STRUCT0_INTR
PERI_MS_PPU_FX_IPC_INTR_STRUCT1_INTR
PERI_MS_PPU_FX_IPC_INTR_STRUCT2_INTR
PERI_MS_PPU_FX_IPC_INTR_STRUCT3_INTR
PERI_MS_PPU_FX_IPC_INTR_STRUCT4_INTR
PERI_MS_PPU_FX_IPC_INTR_STRUCT5_INTR
CPUSS boot
CPUSS CM0+ interrupts
CPUSS CM4 interrupts
CPUSS Fault Structure #0 main
CPUSS Fault Structure #1 main
CPUSS Fault Structure #2 main
CPUSS Fault Structure #3 main
CPUSS IPC Structure #0
CPUSS IPC Structure #1
CPUSS IPC Structure #2
CPUSS IPC Structure #3
CPUSS IPC Structure #4
CPUSS IPC Structure #5
CPUSS IPC Structure #6
CPUSS IPC Structure #7
CPUSS IPC Interrupt Structure #0
CPUSS IPC Interrupt Structure #1
CPUSS IPC Interrupt Structure #2
CPUSS IPC Interrupt Structure #3
CPUSS IPC Interrupt Structure #4
CPUSS IPC Interrupt Structure #5
Note
34.Fixed PPU is configured inside the Boot and user is not allowed to change the attributes of this PPU.
Datasheet
73
002-18043 Rev. *J
2022-09-08
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4F single
Peripheral Protection Unit Fixed Structure
Pairs
Table 22-1
PPU Fixed Structure Pairs (continued)
Pair No.
PPU Fixed Structure Pair
Address
Size
Description
CPUSS IPC Interrupt Structure #6
CPUSS IPC Interrupt Structure #7
Peripheral protection SMPU main
Peripheral protection MPU #0 main
Peripheral protection MPU #14 main
Peripheral protection MPU #15 main
Flash controller main
Flash controller command
Flash controller tests
Flash controller CM0+
Flash controller CM4
Flash controller Crypto
Flash controller P-DMA0
Flash controller P-DMA1
Flash controller M-DMA0
Flash management
PERI_MS_PPU_FX_IPC_INTR_STRUCT6_INTR
PERI_MS_PPU_FX_IPC_INTR_STRUCT7_INTR
PERI_MS_PPU_FX_PROT_SMPU_MAIN
PERI_MS_PPU_FX_PROT_MPU0_MAIN
PERI_MS_PPU_FX_PROT_MPU14_MAIN
PERI_MS_PPU_FX_PROT_MPU15_MAIN
PERI_MS_PPU_FX_FLASHC_MAIN
0x402210C0
0x402210E0
0x40230000
0x40234000
0x40237800
0x40237C00
0x40240000
0x40240008
0x40240200
0x40240400
0x40240480
0x40240500
0x40240580
0x40240600
0x40240680
0x4024F000
0x4024F400
0x4024F500
0x40260000
0x40261000
0x40262000
0x40268000
0x40268100
0x40268080
0x40268180
0x4026C000
0x4026C040
0x40270000
0x40280000
0x40290000
0x40280100
0x40290100
0x40288000
0x40288040
0x40288080
0x402880C0
0x40288100
0x40288140
0x40288180
0x402881C0
0x40288200
0x40288240
0x40288280
0x402882C0
0x40288300
0x00000010
0x00000010
0x00000040
0x00000004
0x00000004
0x00000400
0x00000008
0x00000004
0x00000100
0x00000080
0x00000080
0x00000004
0x00000004
0x00000004
0x00000004
0x00000080
0x00000008
0x00000004
0x00000400
0x00001000
0x00002000
0x00000080
0x00000080
0x00000040
0x00000040
0x00000020
0x00000020
0x00010000
0x00000100
0x00000100
0x00000080
0x00000080
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
PERI_MS_PPU_FX_FLASHC_CMD
PERI_MS_PPU_FX_FLASHC_DFT
PERI_MS_PPU_FX_FLASHC_CM0
PERI_MS_PPU_FX_FLASHC_CM4
PERI_MS_PPU_FX_FLASHC_CRYPTO
PERI_MS_PPU_FX_FLASHC_DW0
PERI_MS_PPU_FX_FLASHC_DW1
PERI_MS_PPU_FX_FLASHC_DMAC
PERI_MS_PPU_FX_FLASHC_FlashMgmt[34]
PERI_MS_PPU_FX_FLASHC_MainSafety
PERI_MS_PPU_FX_FLASHC_WorkSafety
PERI_MS_PPU_FX_SRSS_GENERAL
PERI_MS_PPU_FX_SRSS_MAIN
Flash controller code-flash safety
Flash controller work-flash safety
SRSS General
SRSS main
PERI_MS_PPU_FX_SRSS_SECURE
SRSS secure
PERI_MS_PPU_FX_MCWDT0_CONFIG
PERI_MS_PPU_FX_MCWDT1_CONFIG
PERI_MS_PPU_FX_MCWDT0_MAIN
PERI_MS_PPU_FX_MCWDT1_MAIN
PERI_MS_PPU_FX_WDT_CONFIG
MCWDT #0 configuration
MCWDT #1 configuration
MCWDT #0 main
MCWDT #1 main
System WDT configuration
System WDT main
PERI_MS_PPU_FX_WDT_MAIN
PERI_MS_PPU_FX_BACKUP_BACKUP
PERI_MS_PPU_FX_DW0_DW
SRSS backup
P-DMA0 main
PERI_MS_PPU_FX_DW1_DW
P-DMA1 main
PERI_MS_PPU_FX_DW0_DW_CRC
P-DMA0 CRC
PERI_MS_PPU_FX_DW1_DW_CRC
P-DMA1 CRC
PERI_MS_PPU_FX_DW0_CH_STRUCT0_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT1_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT2_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT3_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT4_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT5_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT6_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT7_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT8_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT9_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT10_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT11_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT12_CH
P-DMA0 Channel #0
P-DMA0 Channel #1
P-DMA0 Channel #2
P-DMA0 Channel #3
P-DMA0 Channel #4
P-DMA0 Channel #5
P-DMA0 Channel #6
P-DMA0 Channel #7
P-DMA0 Channel #8
P-DMA0 Channel #9
P-DMA0 Channel #10
P-DMA0 Channel #11
P-DMA0 Channel #12
Datasheet
74
002-18043 Rev. *J
2022-09-08
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4F single
Peripheral Protection Unit Fixed Structure
Pairs
Table 22-1
PPU Fixed Structure Pairs (continued)
Pair No.
PPU Fixed Structure Pair
Address
Size
Description
P-DMA0 Channel #13
PERI_MS_PPU_FX_DW0_CH_STRUCT13_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT14_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT15_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT16_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT17_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT18_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT19_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT20_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT21_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT22_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT23_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT24_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT25_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT26_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT27_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT28_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT29_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT30_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT31_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT32_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT33_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT34_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT35_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT36_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT37_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT38_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT39_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT40_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT41_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT42_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT43_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT44_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT45_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT46_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT47_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT48_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT49_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT50_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT51_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT52_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT53_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT54_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT55_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT56_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT57_CH
0x40288340
0x40288380
0x402883C0
0x40288400
0x40288440
0x40288480
0x402884C0
0x40288500
0x40288540
0x40288580
0x402885C0
0x40288600
0x40288640
0x40288680
0x402886C0
0x40288700
0x40288740
0x40288780
0x402887C0
0x40288800
0x40288840
0x40288880
0x402888C0
0x40288900
0x40288940
0x40288980
0x402889C0
0x40288A00
0x40288A40
0x40288A80
0x40288AC0
0x40288B00
0x40288B40
0x40288B80
0x40288BC0
0x40288C00
0x40288C40
0x40288C80
0x40288CC0
0x40288D00
0x40288D40
0x40288D80
0x40288DC0
0x40288E00
0x40288E40
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
84
85
P-DMA0 Channel #14
P-DMA0 Channel #15
P-DMA0 Channel #16
P-DMA0 Channel #17
P-DMA0 Channel #18
P-DMA0 Channel #19
P-DMA0 Channel #20
P-DMA0 Channel #21
P-DMA0 Channel #22
P-DMA0 Channel #23
P-DMA0 Channel #24
P-DMA0 Channel #25
P-DMA0 Channel #26
P-DMA0 Channel #27
P-DMA0 Channel #28
P-DMA0 Channel #29
P-DMA0 Channel #30
P-DMA0 Channel #31
P-DMA0 Channel #32
P-DMA0 Channel #33
P-DMA0 Channel #34
P-DMA0 Channel #35
P-DMA0 Channel #36
P-DMA0 Channel #37
P-DMA0 Channel #38
P-DMA0 Channel #39
P-DMA0 Channel #40
P-DMA0 Channel #41
P-DMA0 Channel #42
P-DMA0 Channel #43
P-DMA0 Channel #44
P-DMA0 Channel #45
P-DMA0 Channel #46
P-DMA0 Channel #47
P-DMA0 Channel #48
P-DMA0 Channel #49
P-DMA0 Channel #50
P-DMA0 Channel #51
P-DMA0 Channel #52
P-DMA0 Channel #53
P-DMA0 Channel #54
P-DMA0 Channel #55
P-DMA0 Channel #56
P-DMA0 Channel #57
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
Datasheet
75
002-18043 Rev. *J
2022-09-08
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4F single
Peripheral Protection Unit Fixed Structure
Pairs
Table 22-1
PPU Fixed Structure Pairs (continued)
Pair No.
PPU Fixed Structure Pair
Address
Size
Description
P-DMA0 Channel #58
PERI_MS_PPU_FX_DW0_CH_STRUCT58_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT59_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT60_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT61_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT62_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT63_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT64_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT65_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT66_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT67_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT68_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT69_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT70_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT71_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT72_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT73_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT74_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT75_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT76_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT77_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT78_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT79_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT80_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT81_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT82_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT83_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT84_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT85_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT86_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT87_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT88_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT0_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT1_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT2_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT3_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT4_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT5_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT6_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT7_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT8_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT9_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT10_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT11_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT12_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT13_CH
0x40288E80
0x40288EC0
0x40288F00
0x40288F40
0x40288F80
0x40288FC0
0x40289000
0x40289040
0x40289080
0x402890C0
0x40289100
0x40289140
0x40289180
0x402891C0
0x40289200
0x40289240
0x40289280
0x402892C0
0x40289300
0x40289340
0x40289380
0x402893C0
0x40289400
0x40289440
0x40289480
0x402894C0
0x40289500
0x40289540
0x40289580
0x402895C0
0x40289600
0x40298000
0x40298040
0x40298080
0x402980C0
0x40298100
0x40298140
0x40298180
0x402981C0
0x40298200
0x40298240
0x40298280
0x402982C0
0x40298300
0x40298340
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
P-DMA0 Channel #59
P-DMA0 Channel #60
P-DMA0 Channel #61
P-DMA0 Channel #62
P-DMA0 Channel #63
P-DMA0 Channel #64
P-DMA0 Channel #65
P-DMA0 Channel #66
P-DMA0 Channel #67
P-DMA0 Channel #68
P-DMA0 Channel #69
P-DMA0 Channel #70
P-DMA0 Channel #71
P-DMA0 Channel #72
P-DMA0 Channel #73
P-DMA0 Channel #74
P-DMA0 Channel #75
P-DMA0 Channel #76
P-DMA0 Channel #77
P-DMA0 Channel #78
P-DMA0 Channel #79
P-DMA0 Channel #80
P-DMA0 Channel #81
P-DMA0 Channel #82
P-DMA0 Channel #83
P-DMA0 Channel #84
P-DMA0 Channel #85
P-DMA0 Channel #86
P-DMA0 Channel #87
P-DMA0 Channel #88
P-DMA1 Channel #0
P-DMA1 Channel #1
P-DMA1 Channel #2
P-DMA1 Channel #3
P-DMA1 Channel #4
P-DMA1 Channel #5
P-DMA1 Channel #6
P-DMA1 Channel #7
P-DMA1 Channel #8
P-DMA1 Channel #9
P-DMA1 Channel #10
P-DMA1 Channel #11
P-DMA1 Channel #12
P-DMA1 Channel #13
Datasheet
76
002-18043 Rev. *J
2022-09-08
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4F single
Peripheral Protection Unit Fixed Structure
Pairs
Table 22-1
PPU Fixed Structure Pairs (continued)
Pair No.
PPU Fixed Structure Pair
Address
Size
Description
P-DMA1 Channel #14
PERI_MS_PPU_FX_DW1_CH_STRUCT14_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT15_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT16_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT17_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT18_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT19_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT20_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT21_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT22_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT23_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT24_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT25_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT26_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT27_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT28_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT29_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT30_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT31_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT32_CH
PERI_MS_PPU_FX_DMAC_TOP
0x40298380
0x402983C0
0x40298400
0x40298440
0x40298480
0x402984C0
0x40298500
0x40298540
0x40298580
0x402985C0
0x40298600
0x40298640
0x40298680
0x402986C0
0x40298700
0x40298740
0x40298780
0x402987C0
0x40298800
0x402A0000
0x402A1000
0x402A1100
0x402A1200
0x402A1300
0x402C0000
0x402C0800
0x402F0000
0x40300000
0x40300010
0x40300020
0x40300030
0x40300040
0x40300050
0x40300060
0x40300070
0x40300080
0x40300090
0x403000A0
0x403000B0
0x403000C0
0x403000D0
0x403000E0
0x403000F0
0x40300100
0x40300110
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000010
0x00000100
0x00000100
0x00000100
0x00000100
0x00000200
0x00000200
0x00001000
0x00000008
0x00000008
0x00000008
0x00000008
0x00000008
0x00000008
0x00000008
0x00000008
0x00000008
0x00000008
0x00000008
0x00000008
0x00000008
0x00000008
0x00000008
0x00000008
0x00000008
0x00000008
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
P-DMA1 Channel #15
P-DMA1 Channel #16
P-DMA1 Channel #17
P-DMA1 Channel #18
P-DMA1 Channel #19
P-DMA1 Channel #20
P-DMA1 Channel #21
P-DMA1 Channel #22
P-DMA1 Channel #23
P-DMA1 Channel #24
P-DMA1 Channel #25
P-DMA1 Channel #26
P-DMA1 Channel #27
P-DMA1 Channel #28
P-DMA1 Channel #29
P-DMA1 Channel #30
P-DMA1 Channel #31
P-DMA1 Channel #32
M-DMA0 main
PERI_MS_PPU_FX_DMAC_CH0_CH
M-DMA0 Channel #0
M-DMA0 Channel #1
M-DMA0 Channel #2
M-DMA0 Channel #3
EFUSE control
PERI_MS_PPU_FX_DMAC_CH1_CH
PERI_MS_PPU_FX_DMAC_CH2_CH
PERI_MS_PPU_FX_DMAC_CH3_CH
PERI_MS_PPU_FX_EFUSE_CTL
PERI_MS_PPU_FX_EFUSE_DATA
EFUSE data
PERI_MS_PPU_FX_BIST
Built-in self test
PERI_MS_PPU_FX_HSIOM_PRT0_PRT
PERI_MS_PPU_FX_HSIOM_PRT1_PRT
PERI_MS_PPU_FX_HSIOM_PRT2_PRT
PERI_MS_PPU_FX_HSIOM_PRT3_PRT
PERI_MS_PPU_FX_HSIOM_PRT4_PRT
PERI_MS_PPU_FX_HSIOM_PRT5_PRT
PERI_MS_PPU_FX_HSIOM_PRT6_PRT
PERI_MS_PPU_FX_HSIOM_PRT7_PRT
PERI_MS_PPU_FX_HSIOM_PRT8_PRT
PERI_MS_PPU_FX_HSIOM_PRT9_PRT
PERI_MS_PPU_FX_HSIOM_PRT10_PRT
PERI_MS_PPU_FX_HSIOM_PRT11_PRT
PERI_MS_PPU_FX_HSIOM_PRT12_PRT
PERI_MS_PPU_FX_HSIOM_PRT13_PRT
PERI_MS_PPU_FX_HSIOM_PRT14_PRT
PERI_MS_PPU_FX_HSIOM_PRT15_PRT
PERI_MS_PPU_FX_HSIOM_PRT16_PRT
PERI_MS_PPU_FX_HSIOM_PRT17_PRT
HSIOm Port #0
HSIOm Port #1
HSIOm Port #2
HSIOm Port #3
HSIOm Port #4
HSIOm Port #5
HSIOm Port #6
HSIOm Port #7
HSIOm Port #8
HSIOm Port #9
HSIOm Port #10
HSIOm Port #11
HSIOm Port #12
HSIOm Port #13
HSIOm Port #14
HSIOm Port #15
HSIOm Port #16
HSIOm Port #17
Datasheet
77
002-18043 Rev. *J
2022-09-08
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4F single
Peripheral Protection Unit Fixed Structure
Pairs
Table 22-1
PPU Fixed Structure Pairs (continued)
Pair No.
PPU Fixed Structure Pair
Address
Size
Description
PERI_MS_PPU_FX_HSIOM_PRT18_PRT
PERI_MS_PPU_FX_HSIOM_PRT19_PRT
PERI_MS_PPU_FX_HSIOM_PRT20_PRT
PERI_MS_PPU_FX_HSIOM_PRT21_PRT
PERI_MS_PPU_FX_HSIOM_PRT22_PRT
PERI_MS_PPU_FX_HSIOM_PRT23_PRT
PERI_MS_PPU_FX_HSIOM_AMUX
0x40300120
0x40300130
0x40300140
0x40300150
0x40300160
0x40300170
0x40302000
0x40302200
0x40302240
0x40310000
0x40310080
0x40310100
0x40310180
0x40310200
0x40310280
0x40310300
0x40310380
0x40310400
0x40310480
0x40310500
0x40310580
0x40310600
0x40310680
0x40310700
0x40310780
0x40310800
0x40310880
0x40310900
0x40310980
0x40310A00
0x40310A80
0x40310B00
0x40310B80
0x40310040
0x403100C0
0x40310140
0x403101C0
0x40310240
0x403102C0
0x40310340
0x403103C0
0x40310440
0x403104C0
0x40310540
0x403105C0
0x00000008
0x00000008
0x00000008
0x00000008
0x00000008
0x00000008
0x00000010
0x00000010
0x00000004
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000020
0x00000020
0x00000020
0x00000020
0x00000020
0x00000020
0x00000020
0x00000020
0x00000020
0x00000020
0x00000020
0x00000020
HSIOm Port #18
HSIOm Port #19
HSIOm Port #20
HSIOm Port #21
HSIOm Port #22
HSIOm Port #23
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
HSIOm Analog multiplexer
HSIOm monitor
PERI_MS_PPU_FX_HSIOM_MON
PERI_MS_PPU_FX_HSIOM_ALTJTAG
PERI_MS_PPU_FX_GPIO_PRT0_PRT
PERI_MS_PPU_FX_GPIO_PRT1_PRT
PERI_MS_PPU_FX_GPIO_PRT2_PRT
PERI_MS_PPU_FX_GPIO_PRT3_PRT
PERI_MS_PPU_FX_GPIO_PRT4_PRT
PERI_MS_PPU_FX_GPIO_PRT5_PRT
PERI_MS_PPU_FX_GPIO_PRT6_PRT
PERI_MS_PPU_FX_GPIO_PRT7_PRT
PERI_MS_PPU_FX_GPIO_PRT8_PRT
PERI_MS_PPU_FX_GPIO_PRT9_PRT
PERI_MS_PPU_FX_GPIO_PRT10_PRT
PERI_MS_PPU_FX_GPIO_PRT11_PRT
PERI_MS_PPU_FX_GPIO_PRT12_PRT
PERI_MS_PPU_FX_GPIO_PRT13_PRT
PERI_MS_PPU_FX_GPIO_PRT14_PRT
PERI_MS_PPU_FX_GPIO_PRT15_PRT
PERI_MS_PPU_FX_GPIO_PRT16_PRT
PERI_MS_PPU_FX_GPIO_PRT17_PRT
PERI_MS_PPU_FX_GPIO_PRT18_PRT
PERI_MS_PPU_FX_GPIO_PRT19_PRT
PERI_MS_PPU_FX_GPIO_PRT20_PRT
PERI_MS_PPU_FX_GPIO_PRT21_PRT
PERI_MS_PPU_FX_GPIO_PRT22_PRT
PERI_MS_PPU_FX_GPIO_PRT23_PRT
PERI_MS_PPU_FX_GPIO_PRT0_CFG
PERI_MS_PPU_FX_GPIO_PRT1_CFG
PERI_MS_PPU_FX_GPIO_PRT2_CFG
PERI_MS_PPU_FX_GPIO_PRT3_CFG
PERI_MS_PPU_FX_GPIO_PRT4_CFG
PERI_MS_PPU_FX_GPIO_PRT5_CFG
PERI_MS_PPU_FX_GPIO_PRT6_CFG
PERI_MS_PPU_FX_GPIO_PRT7_CFG
PERI_MS_PPU_FX_GPIO_PRT8_CFG
PERI_MS_PPU_FX_GPIO_PRT9_CFG
PERI_MS_PPU_FX_GPIO_PRT10_CFG
PERI_MS_PPU_FX_GPIO_PRT11_CFG
HSIOm Alternate JTAG
GPIO_ENH Port #0
GPIO_STD Port #1
GPIO_STD Port #2
GPIO_STD Port #3
GPIO_STD Port #4
GPIO_STD Port #5
GPIO_STD Port #6
GPIO_STD Port #7
GPIO_STD Port #8
GPIO_STD Port #9
GPIO_STD Port #10
GPIO_STD Port #11
GPIO_STD Port #12
GPIO_STD Port #13
GPIO_STD Port #14
GPIO_STD Port #15
GPIO_STD Port #16
GPIO_STD Port #17
GPIO_STD Port #18
GPIO_STD Port #19
GPIO_STD Port #20
GPIO_STD Port #21
GPIO_STD Port #22
GPIO_STD Port #23
GPIO_ENH Port #0 configuration
GPIO_STD Port #1 configuration
GPIO_STD Port #2 configuration
GPIO_STD Port #3 configuration
GPIO_STD Port #4 configuration
GPIO_STD Port #5 configuration
GPIO_STD Port #6 configuration
GPIO_STD Port #7 configuration
GPIO_STD Port #8 configuration
GPIO_STD Port #9 configuration
GPIO_STD Port #10 configuration
GPIO_STD Port #11 configuration
Datasheet
78
002-18043 Rev. *J
2022-09-08
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4F single
Peripheral Protection Unit Fixed Structure
Pairs
Table 22-1
PPU Fixed Structure Pairs (continued)
Pair No.
PPU Fixed Structure Pair
Address
Size
Description
GPIO_STD Port #12 configuration
GPIO_STD Port #13 configuration
GPIO_STD Port #14 configuration
GPIO_STD Port #15 configuration
GPIO_STD Port #16 configuration
GPIO_STD Port #17 configuration
GPIO_STD Port #18 configuration
GPIO_STD Port #19 configuration
GPIO_STD Port #20 configuration
GPIO_STD Port #21 configuration
GPIO_STD Port #22 configuration
GPIO_STD Port #23 configuration
GPIO main
PERI_MS_PPU_FX_GPIO_PRT12_CFG
PERI_MS_PPU_FX_GPIO_PRT13_CFG
0x40310640
0x403106C0
0x40310740
0x403107C0
0x40310840
0x403108C0
0x40310940
0x403109C0
0x40310A40
0x40310AC0
0x40310B40
0x40310BC0
0x40314000
0x40315000
0x40320C00
0x40320D00
0x40320E00
0x40320F00
0x40321100
0x40380000
0x40380080
0x40380100
0x40380180
0x40380200
0x40380280
0x40380300
0x40380380
0x40380400
0x40380480
0x40380500
0x40380580
0x40380600
0x40380680
0x40380700
0x40380780
0x40380800
0x40380880
0x40380900
0x40380980
0x40380A00
0x40380A80
0x40380B00
0x40380B80
0x40380C00
0x40380C80
0x00000020
0x00000020
0x00000020
0x00000020
0x00000020
0x00000020
0x00000020
0x00000020
0x00000020
0x00000020
0x00000020
0x00000020
0x00000040
0x00000008
0x00000100
0x00000100
0x00000100
0x00000100
0x00000100
0x00000080
0x00000080
0x00000080
0x00000080
0x00000080
0x00000080
0x00000080
0x00000080
0x00000080
0x00000080
0x00000080
0x00000080
0x00000080
0x00000080
0x00000080
0x00000080
0x00000080
0x00000080
0x00000080
0x00000080
0x00000080
0x00000080
0x00000080
0x00000080
0x00000080
0x00000080
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
PERI_MS_PPU_FX_GPIO_PRT14_CFG
PERI_MS_PPU_FX_GPIO_PRT15_CFG
PERI_MS_PPU_FX_GPIO_PRT16_CFG
PERI_MS_PPU_FX_GPIO_PRT17_CFG
PERI_MS_PPU_FX_GPIO_PRT18_CFG
PERI_MS_PPU_FX_GPIO_PRT19_CFG
PERI_MS_PPU_FX_GPIO_PRT20_CFG
PERI_MS_PPU_FX_GPIO_PRT21_CFG
PERI_MS_PPU_FX_GPIO_PRT22_CFG
PERI_MS_PPU_FX_GPIO_PRT23_CFG
PERI_MS_PPU_FX_GPIO_GPIO
PERI_MS_PPU_FX_GPIO_TEST
GPIO test
PERI_MS_PPU_FX_SMARTIO_PRT12_PRT
PERI_MS_PPU_FX_SMARTIO_PRT13_PRT
PERI_MS_PPU_FX_SMARTIO_PRT14_PRT
PERI_MS_PPU_FX_SMARTIO_PRT15_PRT
PERI_MS_PPU_FX_SMARTIO_PRT17_PRT
PERI_MS_PPU_FX_TCPWM0_GRP0_CNT0_CNT
PERI_MS_PPU_FX_TCPWM0_GRP0_CNT1_CNT
PERI_MS_PPU_FX_TCPWM0_GRP0_CNT2_CNT
PERI_MS_PPU_FX_TCPWM0_GRP0_CNT3_CNT
PERI_MS_PPU_FX_TCPWM0_GRP0_CNT4_CNT
PERI_MS_PPU_FX_TCPWM0_GRP0_CNT5_CNT
PERI_MS_PPU_FX_TCPWM0_GRP0_CNT6_CNT
PERI_MS_PPU_FX_TCPWM0_GRP0_CNT7_CNT
PERI_MS_PPU_FX_TCPWM0_GRP0_CNT8_CNT
PERI_MS_PPU_FX_TCPWM0_GRP0_CNT9_CNT
PERI_MS_PPU_FX_TCPWM0_GRP0_CNT10_CNT
PERI_MS_PPU_FX_TCPWM0_GRP0_CNT11_CNT
PERI_MS_PPU_FX_TCPWM0_GRP0_CNT12_CNT
PERI_MS_PPU_FX_TCPWM0_GRP0_CNT13_CNT
PERI_MS_PPU_FX_TCPWM0_GRP0_CNT14_CNT
PERI_MS_PPU_FX_TCPWM0_GRP0_CNT15_CNT
PERI_MS_PPU_FX_TCPWM0_GRP0_CNT16_CNT
PERI_MS_PPU_FX_TCPWM0_GRP0_CNT17_CNT
PERI_MS_PPU_FX_TCPWM0_GRP0_CNT18_CNT
PERI_MS_PPU_FX_TCPWM0_GRP0_CNT19_CNT
PERI_MS_PPU_FX_TCPWM0_GRP0_CNT20_CNT
PERI_MS_PPU_FX_TCPWM0_GRP0_CNT21_CNT
PERI_MS_PPU_FX_TCPWM0_GRP0_CNT22_CNT
PERI_MS_PPU_FX_TCPWM0_GRP0_CNT23_CNT
PERI_MS_PPU_FX_TCPWM0_GRP0_CNT24_CNT
PERI_MS_PPU_FX_TCPWM0_GRP0_CNT25_CNT
SMART I/O #12
SMART I/O #13
SMART I/O #14
SMART I/O #15
SMART I/O #17
TCPWM0 Group #0, Counter #0
TCPWM0 Group #0, Counter #1
TCPWM0 Group #0, Counter #2
TCPWM0 Group #0, Counter #3
TCPWM0 Group #0, Counter #4
TCPWM0 Group #0, Counter #5
TCPWM0 Group #0, Counter #6
TCPWM0 Group #0, Counter #7
TCPWM0 Group #0, Counter #8
TCPWM0 Group #0, Counter #9
TCPWM0 Group #0, Counter #10
TCPWM0 Group #0, Counter #11
TCPWM0 Group #0, Counter #12
TCPWM0 Group #0, Counter #13
TCPWM0 Group #0, Counter #14
TCPWM0 Group #0, Counter #15
TCPWM0 Group #0, Counter #16
TCPWM0 Group #0, Counter #17
TCPWM0 Group #0, Counter #18
TCPWM0 Group #0, Counter #19
TCPWM0 Group #0, Counter #20
TCPWM0 Group #0, Counter #21
TCPWM0 Group #0, Counter #22
TCPWM0 Group #0, Counter #23
TCPWM0 Group #0, Counter #24
TCPWM0 Group #0, Counter #25
Datasheet
79
002-18043 Rev. *J
2022-09-08
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4F single
Peripheral Protection Unit Fixed Structure
Pairs
Table 22-1
PPU Fixed Structure Pairs (continued)
Pair No.
PPU Fixed Structure Pair
Address
Size
Description
TCPWM0 Group #0, Counter #26
TCPWM0 Group #0, Counter #27
TCPWM0 Group #0, Counter #28
TCPWM0 Group #0, Counter #29
TCPWM0 Group #0, Counter #30
TCPWM0 Group #0, Counter #31
TCPWM0 Group #0, Counter #32
TCPWM0 Group #0, Counter #33
TCPWM0 Group #0, Counter #34
TCPWM0 Group #0, Counter #35
TCPWM0 Group #0, Counter #36
TCPWM0 Group #0, Counter #37
TCPWM0 Group #0, Counter #38
TCPWM0 Group #0, Counter #39
TCPWM0 Group #0, Counter #40
TCPWM0 Group #0, Counter #41
TCPWM0 Group #0, Counter #42
TCPWM0 Group #0, Counter #43
TCPWM0 Group #0, Counter #44
TCPWM0 Group #0, Counter #45
TCPWM0 Group #0, Counter #46
TCPWM0 Group #0, Counter #47
TCPWM0 Group #0, Counter #48
TCPWM0 Group #0, Counter #49
TCPWM0 Group #0, Counter #50
TCPWM0 Group #0, Counter #51
TCPWM0 Group #0, Counter #52
TCPWM0 Group #0, Counter #53
TCPWM0 Group #0, Counter #54
TCPWM0 Group #0, Counter #55
TCPWM0 Group #0, Counter #56
TCPWM0 Group #0, Counter #57
TCPWM0 Group #0, Counter #58
TCPWM0 Group #0, Counter #59
TCPWM0 Group #0, Counter #60
TCPWM0 Group #0, Counter #61
TCPWM0 Group #0, Counter #62
TCPWM0 Group #1, Counter #0
TCPWM0 Group #1, Counter #1
TCPWM0 Group #1, Counter #2
TCPWM0 Group #1, Counter #3
TCPWM0 Group #1, Counter #4
TCPWM0 Group #1, Counter #5
TCPWM0 Group #1, Counter #6
TCPWM0 Group #1, Counter #7
PERI_MS_PPU_FX_TCPWM0_GRP0_CNT26_CNT
PERI_MS_PPU_FX_TCPWM0_GRP0_CNT27_CNT
PERI_MS_PPU_FX_TCPWM0_GRP0_CNT28_CNT
PERI_MS_PPU_FX_TCPWM0_GRP0_CNT29_CNT
PERI_MS_PPU_FX_TCPWM0_GRP0_CNT30_CNT
PERI_MS_PPU_FX_TCPWM0_GRP0_CNT31_CNT
PERI_MS_PPU_FX_TCPWM0_GRP0_CNT32_CNT
PERI_MS_PPU_FX_TCPWM0_GRP0_CNT33_CNT
PERI_MS_PPU_FX_TCPWM0_GRP0_CNT34_CNT
PERI_MS_PPU_FX_TCPWM0_GRP0_CNT35_CNT
PERI_MS_PPU_FX_TCPWM0_GRP0_CNT36_CNT
PERI_MS_PPU_FX_TCPWM0_GRP0_CNT37_CNT
PERI_MS_PPU_FX_TCPWM0_GRP0_CNT38_CNT
PERI_MS_PPU_FX_TCPWM0_GRP0_CNT39_CNT
PERI_MS_PPU_FX_TCPWM0_GRP0_CNT40_CNT
PERI_MS_PPU_FX_TCPWM0_GRP0_CNT41_CNT
PERI_MS_PPU_FX_TCPWM0_GRP0_CNT42_CNT
PERI_MS_PPU_FX_TCPWM0_GRP0_CNT43_CNT
PERI_MS_PPU_FX_TCPWM0_GRP0_CNT44_CNT
PERI_MS_PPU_FX_TCPWM0_GRP0_CNT45_CNT
PERI_MS_PPU_FX_TCPWM0_GRP0_CNT46_CNT
PERI_MS_PPU_FX_TCPWM0_GRP0_CNT47_CNT
PERI_MS_PPU_FX_TCPWM0_GRP0_CNT48_CNT
PERI_MS_PPU_FX_TCPWM0_GRP0_CNT49_CNT
PERI_MS_PPU_FX_TCPWM0_GRP0_CNT50_CNT
PERI_MS_PPU_FX_TCPWM0_GRP0_CNT51_CNT
PERI_MS_PPU_FX_TCPWM0_GRP0_CNT52_CNT
PERI_MS_PPU_FX_TCPWM0_GRP0_CNT53_CNT
PERI_MS_PPU_FX_TCPWM0_GRP0_CNT54_CNT
PERI_MS_PPU_FX_TCPWM0_GRP0_CNT55_CNT
PERI_MS_PPU_FX_TCPWM0_GRP0_CNT56_CNT
PERI_MS_PPU_FX_TCPWM0_GRP0_CNT57_CNT
PERI_MS_PPU_FX_TCPWM0_GRP0_CNT58_CNT
PERI_MS_PPU_FX_TCPWM0_GRP0_CNT59_CNT
PERI_MS_PPU_FX_TCPWM0_GRP0_CNT60_CNT
PERI_MS_PPU_FX_TCPWM0_GRP0_CNT61_CNT
PERI_MS_PPU_FX_TCPWM0_GRP0_CNT62_CNT
PERI_MS_PPU_FX_TCPWM0_GRP1_CNT0_CNT
PERI_MS_PPU_FX_TCPWM0_GRP1_CNT1_CNT
PERI_MS_PPU_FX_TCPWM0_GRP1_CNT2_CNT
PERI_MS_PPU_FX_TCPWM0_GRP1_CNT3_CNT
PERI_MS_PPU_FX_TCPWM0_GRP1_CNT4_CNT
PERI_MS_PPU_FX_TCPWM0_GRP1_CNT5_CNT
PERI_MS_PPU_FX_TCPWM0_GRP1_CNT6_CNT
PERI_MS_PPU_FX_TCPWM0_GRP1_CNT7_CNT
0x40380D00
0x40380D80
0x40380E00
0x40380E80
0x40380F00
0x40380F80
0x40381000
0x40381080
0x40381100
0x40381180
0x40381200
0x40381280
0x40381300
0x40381380
0x40381400
0x40381480
0x40381500
0x40381580
0x40381600
0x40381680
0x40381700
0x40381780
0x40381800
0x40381880
0x40381900
0x40381980
0x40381A00
0x40381A80
0x40381B00
0x40381B80
0x40381C00
0x40381C80
0x40381D00
0x40381D80
0x40381E00
0x40381E80
0x40381F00
0x40388000
0x40388080
0x40388100
0x40388180
0x40388200
0x40388280
0x40388300
0x40388380
0x00000080
0x00000080
0x00000080
0x00000080
0x00000080
0x00000080
0x00000080
0x00000080
0x00000080
0x00000080
0x00000080
0x00000080
0x00000080
0x00000080
0x00000080
0x00000080
0x00000080
0x00000080
0x00000080
0x00000080
0x00000080
0x00000080
0x00000080
0x00000080
0x00000080
0x00000080
0x00000080
0x00000080
0x00000080
0x00000080
0x00000080
0x00000080
0x00000080
0x00000080
0x00000080
0x00000080
0x00000080
0x00000080
0x00000080
0x00000080
0x00000080
0x00000080
0x00000080
0x00000080
0x00000080
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
Datasheet
80
002-18043 Rev. *J
2022-09-08
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4F single
Peripheral Protection Unit Fixed Structure
Pairs
Table 22-1
PPU Fixed Structure Pairs (continued)
Pair No.
PPU Fixed Structure Pair
Address
Size
Description
TCPWM0 Group #1, Counter #8
TCPWM0 Group #1, Counter #9
TCPWM0 Group #1, Counter #10
TCPWM0 Group #1, Counter #11
TCPWM0 Group #2, Counter #0
TCPWM0 Group #2, Counter #1
TCPWM0 Group #2, Counter #2
TCPWM0 Group #2, Counter #3
Event generator #0
LIN0, main
PERI_MS_PPU_FX_TCPWM0_GRP1_CNT8_CNT
PERI_MS_PPU_FX_TCPWM0_GRP1_CNT9_CNT
PERI_MS_PPU_FX_TCPWM0_GRP1_CNT10_CNT
PERI_MS_PPU_FX_TCPWM0_GRP1_CNT11_CNT
PERI_MS_PPU_FX_TCPWM0_GRP2_CNT0_CNT
PERI_MS_PPU_FX_TCPWM0_GRP2_CNT1_CNT
PERI_MS_PPU_FX_TCPWM0_GRP2_CNT2_CNT
PERI_MS_PPU_FX_TCPWM0_GRP2_CNT3_CNT
PERI_MS_PPU_FX_EVTGEN0
0x40388400
0x40388480
0x40388500
0x40388580
0x40390000
0x40390080
0x40390100
0x40390180
0x403F0000
0x40500000
0x40508000
0x40508100
0x40508200
0x40508300
0x40508400
0x40508500
0x40508600
0x40508700
0x40520000
0x40520200
0x40520400
0x40540000
0x40540200
0x40540400
0x40521000
0x40541000
0x40530000
0x40550000
0x40600000
0x40610000
0x40620000
0x40630000
0x40640000
0x40650000
0x40660000
0x40670000
0x40900000
0x40901000
0x40902000
0x40900800
0x40900840
0x40900880
0x409008C0
0x40900900
0x40900940
0x00000080
0x00000080
0x00000080
0x00000080
0x00000080
0x00000080
0x00000080
0x00000080
0x00001000
0x00000008
0x00000100
0x00000100
0x00000100
0x00000100
0x00000100
0x00000100
0x00000100
0x00000100
0x00000200
0x00000200
0x00000200
0x00000200
0x00000200
0x00000200
0x00000100
0x00000100
0x00010000
0x00010000
0x00010000
0x00010000
0x00010000
0x00010000
0x00010000
0x00010000
0x00010000
0x00010000
0x00000400
0x00000400
0x00000400
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
PERI_MS_PPU_FX_LIN0_MAIN
PERI_MS_PPU_FX_LIN0_CH0_CH
PERI_MS_PPU_FX_LIN0_CH1_CH
PERI_MS_PPU_FX_LIN0_CH2_CH
PERI_MS_PPU_FX_LIN0_CH3_CH
PERI_MS_PPU_FX_LIN0_CH4_CH
PERI_MS_PPU_FX_LIN0_CH5_CH
PERI_MS_PPU_FX_LIN0_CH6_CH
PERI_MS_PPU_FX_LIN0_CH7_CH
PERI_MS_PPU_FX_CANFD0_CH0_CH
PERI_MS_PPU_FX_CANFD0_CH1_CH
PERI_MS_PPU_FX_CANFD0_CH2_CH
PERI_MS_PPU_FX_CANFD1_CH0_CH
PERI_MS_PPU_FX_CANFD1_CH1_CH
PERI_MS_PPU_FX_CANFD1_CH2_CH
PERI_MS_PPU_FX_CANFD0_MAIN
PERI_MS_PPU_FX_CANFD1_MAIN
PERI_MS_PPU_FX_CANFD0_BUF
PERI_MS_PPU_FX_CANFD1_BUF
PERI_MS_PPU_FX_SCB0
LIN0, Channel #0
LIN0, Channel #1
LIN0, Channel #2
LIN0, Channel #3
LIN0, Channel #4
LIN0, Channel #5
LIN0, Channel #6
LIN0, Channel #7
CAN0, Channel #0
CAN0, Channel #1
CAN0, Channel #2
CAN1, Channel #0
CAN1, Channel #1
CAN1, Channel #2
CAN0 main
CAN1 main
CAN0 buffer
CAN1 buffer
SCB0
PERI_MS_PPU_FX_SCB1
SCB1
PERI_MS_PPU_FX_SCB2
SCB2
PERI_MS_PPU_FX_SCB3
SCB3
PERI_MS_PPU_FX_SCB4
SCB4
PERI_MS_PPU_FX_SCB5
SCB5
PERI_MS_PPU_FX_SCB6
SCB6
PERI_MS_PPU_FX_SCB7
SCB7
PERI_MS_PPU_FX_PASS0_SAR0_SAR
PERI_MS_PPU_FX_PASS0_SAR1_SAR
PERI_MS_PPU_FX_PASS0_SAR2_SAR
PERI_MS_PPU_FX_PASS0_SAR0_CH0_CH
PERI_MS_PPU_FX_PASS0_SAR0_CH1_CH
PERI_MS_PPU_FX_PASS0_SAR0_CH2_CH
PERI_MS_PPU_FX_PASS0_SAR0_CH3_CH
PERI_MS_PPU_FX_PASS0_SAR0_CH4_CH
PERI_MS_PPU_FX_PASS0_SAR0_CH5_CH
PASS SAR0
PASS SAR1
PASS SAR2
SAR0, Channel #0
SAR0, Channel #1
SAR0, Channel #2
SAR0, Channel #3
SAR0, Channel #4
SAR0, Channel #5
Datasheet
81
002-18043 Rev. *J
2022-09-08
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4F single
Peripheral Protection Unit Fixed Structure
Pairs
Table 22-1
PPU Fixed Structure Pairs (continued)
Pair No.
PPU Fixed Structure Pair
Address
Size
Description
SAR0, Channel #6
PERI_MS_PPU_FX_PASS0_SAR0_CH6_CH
PERI_MS_PPU_FX_PASS0_SAR0_CH7_CH
PERI_MS_PPU_FX_PASS0_SAR0_CH8_CH
PERI_MS_PPU_FX_PASS0_SAR0_CH9_CH
PERI_MS_PPU_FX_PASS0_SAR0_CH10_CH
PERI_MS_PPU_FX_PASS0_SAR0_CH11_CH
PERI_MS_PPU_FX_PASS0_SAR0_CH12_CH
PERI_MS_PPU_FX_PASS0_SAR0_CH13_CH
PERI_MS_PPU_FX_PASS0_SAR0_CH14_CH
PERI_MS_PPU_FX_PASS0_SAR0_CH15_CH
PERI_MS_PPU_FX_PASS0_SAR0_CH16_CH
PERI_MS_PPU_FX_PASS0_SAR0_CH17_CH
PERI_MS_PPU_FX_PASS0_SAR0_CH18_CH
PERI_MS_PPU_FX_PASS0_SAR0_CH19_CH
PERI_MS_PPU_FX_PASS0_SAR0_CH20_CH
PERI_MS_PPU_FX_PASS0_SAR0_CH21_CH
PERI_MS_PPU_FX_PASS0_SAR0_CH22_CH
PERI_MS_PPU_FX_PASS0_SAR0_CH23_CH
PERI_MS_PPU_FX_PASS0_SAR1_CH0_CH
PERI_MS_PPU_FX_PASS0_SAR1_CH1_CH
PERI_MS_PPU_FX_PASS0_SAR1_CH2_CH
PERI_MS_PPU_FX_PASS0_SAR1_CH3_CH
PERI_MS_PPU_FX_PASS0_SAR1_CH4_CH
PERI_MS_PPU_FX_PASS0_SAR1_CH5_CH
PERI_MS_PPU_FX_PASS0_SAR1_CH6_CH
PERI_MS_PPU_FX_PASS0_SAR1_CH7_CH
PERI_MS_PPU_FX_PASS0_SAR1_CH8_CH
PERI_MS_PPU_FX_PASS0_SAR1_CH9_CH
PERI_MS_PPU_FX_PASS0_SAR1_CH10_CH
PERI_MS_PPU_FX_PASS0_SAR1_CH11_CH
PERI_MS_PPU_FX_PASS0_SAR1_CH12_CH
PERI_MS_PPU_FX_PASS0_SAR1_CH13_CH
PERI_MS_PPU_FX_PASS0_SAR1_CH14_CH
PERI_MS_PPU_FX_PASS0_SAR1_CH15_CH
PERI_MS_PPU_FX_PASS0_SAR1_CH16_CH
PERI_MS_PPU_FX_PASS0_SAR1_CH17_CH
PERI_MS_PPU_FX_PASS0_SAR1_CH18_CH
PERI_MS_PPU_FX_PASS0_SAR1_CH19_CH
PERI_MS_PPU_FX_PASS0_SAR1_CH20_CH
PERI_MS_PPU_FX_PASS0_SAR1_CH21_CH
PERI_MS_PPU_FX_PASS0_SAR1_CH22_CH
PERI_MS_PPU_FX_PASS0_SAR1_CH23_CH
PERI_MS_PPU_FX_PASS0_SAR1_CH24_CH
PERI_MS_PPU_FX_PASS0_SAR1_CH25_CH
PERI_MS_PPU_FX_PASS0_SAR1_CH26_CH
0x40900980
0x409009C0
0x40900A00
0x40900A40
0x40900A80
0x40900AC0
0x40900B00
0x40900B40
0x40900B80
0x40900BC0
0x40900C00
0x40900C40
0x40900C80
0x40900CC0
0x40900D00
0x40900D40
0x40900D80
0x40900DC0
0x40901800
0x40901840
0x40901880
0x409018C0
0x40901900
0x40901940
0x40901980
0x409019C0
0x40901A00
0x40901A40
0x40901A80
0x40901AC0
0x40901B00
0x40901B40
0x40901B80
0x40901BC0
0x40901C00
0x40901C40
0x40901C80
0x40901CC0
0x40901D00
0x40901D40
0x40901D80
0x40901DC0
0x40901E00
0x40901E40
0x40901E80
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
SAR0, Channel #7
SAR0, Channel #8
SAR0, Channel #9
SAR0, Channel #10
SAR0, Channel #11
SAR0, Channel #12
SAR0, Channel #13
SAR0, Channel #14
SAR0, Channel #15
SAR0, Channel #16
SAR0, Channel #17
SAR0, Channel #18
SAR0, Channel #19
SAR0, Channel #20
SAR0, Channel #21
SAR0, Channel #22
SAR0, Channel #23
SAR1, Channel #0
SAR1, Channel #1
SAR1, Channel #2
SAR1, Channel #3
SAR1, Channel #4
SAR1, Channel #5
SAR1, Channel #6
SAR1, Channel #7
SAR1, Channel #8
SAR1, Channel #9
SAR1, Channel #10
SAR1, Channel #11
SAR1, Channel #12
SAR1, Channel #13
SAR1, Channel #14
SAR1, Channel #15
SAR1, Channel #16
SAR1, Channel #17
SAR1, Channel #18
SAR1, Channel #19
SAR1, Channel #20
SAR1, Channel #21
SAR1, Channel #22
SAR1, Channel #23
SAR1, Channel #24
SAR1, Channel #25
SAR1, Channel #26
Datasheet
82
002-18043 Rev. *J
2022-09-08
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4F single
Peripheral Protection Unit Fixed Structure
Pairs
Table 22-1
PPU Fixed Structure Pairs (continued)
Pair No.
PPU Fixed Structure Pair
Address
Size
Description
SAR1, Channel #27
PERI_MS_PPU_FX_PASS0_SAR1_CH27_CH
PERI_MS_PPU_FX_PASS0_SAR1_CH28_CH
PERI_MS_PPU_FX_PASS0_SAR1_CH29_CH
PERI_MS_PPU_FX_PASS0_SAR1_CH30_CH
PERI_MS_PPU_FX_PASS0_SAR1_CH31_CH
PERI_MS_PPU_FX_PASS0_SAR2_CH0_CH
PERI_MS_PPU_FX_PASS0_SAR2_CH1_CH
PERI_MS_PPU_FX_PASS0_SAR2_CH2_CH
PERI_MS_PPU_FX_PASS0_SAR2_CH3_CH
PERI_MS_PPU_FX_PASS0_SAR2_CH4_CH
PERI_MS_PPU_FX_PASS0_SAR2_CH5_CH
PERI_MS_PPU_FX_PASS0_SAR2_CH6_CH
PERI_MS_PPU_FX_PASS0_SAR2_CH7_CH
PERI_MS_PPU_FX_PASS0_TOP
0x40901EC0
0x40901F00
0x40901F40
0x40901F80
0x40901FC0
0x40902800
0x40902840
0x40902880
0x409028C0
0x40902900
0x40902940
0x40902980
0x409029C0
0x409F0000
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00000040
0x00001000
444
445
446
447
448
449
450
451
452
453
454
455
456
457
SAR1, Channel #28
SAR1, Channel #29
SAR1, Channel #30
SAR1, Channel #31
SAR2, Channel #0
SAR2, Channel #1
SAR2, Channel #2
SAR2, Channel #3
SAR2, Channel #4
SAR2, Channel #5
SAR2, Channel #6
SAR2, Channel #7
PASS0 SAR main
Datasheet
83
002-18043 Rev. *J
2022-09-08
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4F single
Bus masters
23
Bus masters
The Arbiter (part of flash controller) performs priority-based arbitration based on the master identifier. Each bus
master has a dedicated 4-bit master identifier. This master identifier is used for bus arbitration and IPC function-
ality.
Table 23-1
ID No.
Bus masters for access and protection control
Master ID
Description
Master ID for CM0+
Master ID for Crypto
0
1
2
3
4
CPUSS_MS_ID_CM0
CPUSS_MS_ID_CRYPTO
CPUSS_MS_ID_DW0
CPUSS_MS_ID_DW1
CPUSS_MS_ID_DMAC
Master ID for P-DMA 0
Master ID for P-DMA 1
Master ID for M-DMA0
Master ID for CM4
14 CPUSS_MS_ID_CM4
15 CPUSS_MS_ID_TC
Master ID for DAP Tap Controller
Datasheet
84
002-18043 Rev. *J
2022-09-08
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4F single
Miscellaneous configuration
24
Miscellaneous configuration
Table 24-1
Miscellaneous configuration for CYT2B7 devices
Number/
Configuration
Sl. No.
Description
Instances
Number of clock paths. One for each of FLL, PLL,
Direct and CSV
0
SRSS_NUM_CLKPATH
SRSS_NUM_HFROOT
4
Number of CLK_HFs present
1
2
3
4
5
6
7
8
3
8
Number of protection contexts
PERI_PC_NR
Number of programmable clocks (outputs)
Number of divide-by-8 clock dividers
Number of divide-by-16 clock dividers
Number of divide-by-24.5 clock dividers
Number of MPU regions in CM0+
Number of MPU regions in CM4
PERI_CLOCK_NR
PERI_DIV_8_NR
110
32
16
8
PERI_DIV_16_NR
PERI_DIV_24_5_NR
CPUSS_CM0P_MPU_NR
CPUSS_CM4_MPU_NR
8
8
Number of 32-bit words in the IP internal
memory buffer (to allow for a 256-B, 512-B, 1-KB,
2-KB, 4-KB, 8-KB, 16-KB, and 32-KB memory
buffer)
9
CPUSS_CRYPTO_BUFF_SIZE
CPUSS_FAULT_FAULT_NR
2048
4
Number of fault structures
10
Number of IPC structures
0 - Reserved for CM0+ access
1 - Reserved for CM4 access
2 - Reserved for DAP access
Remaining for user purposes
11
CPUSS_IPC_IPC_NR
8
Number of EZ memory bytes. This memory is
used in EZ mode, CMD_RESP mode and FIFO
mode.
12
SCB0_EZ_DATA_NR
256
Note: Only SCB0 supports EZ mode
Number of SMPU protection structures
13
14
CPUSS_PROT_SMPU_STRUCT_NR
TCPWM_TR_ONE_CNT_NR
16
3
Number of input triggers per counter, routed to
one counter
Number of input triggers routed to all counters,
based on the pin package
15
TCPWM_TR_ALL_CNT_NR
27
Number of TCPWM0 counter groups
16
17
TCPWM_GRP_NR
3
Number of counters per TCPWM0 Group #0
TCPWM_GRP_NR0_GRP_GRP_CNT_NR
63
Counter width in number of bits per TCPWM0
Group #0
18
19
20
21
22
TCPWM_GRP_NR0_CNT_GRP_CNT_WIDTH
TCPWM_GRP_NR1_GRP_GRP_CNT_NR
TCPWM_GRP_NR1_CNT_GRP_CNT_WIDTH
TCPWM_GRP_NR2_GRP_GRP_CNT_NR
TCPWM_GRP_NR2_CNT_GRP_CNT_WIDTH
16
12
16
4
Number of counters per TCPWM0 Group #1
Counter width in number of bits per TCPWM0
Group #1
Number of counters per TCPWM0 Group #2
Counter width in number of bits per TCPWM0
Group #2
32
Message RAM size in KB shared by all the
channels
23
24
CANFD0_MRAM_SIZE / CANFD1_MRAM_SIZE
EVTGEN_COMP_STRUCT_NR
24
11
Number of Event Generator comparator struc-
tures
Datasheet
85
002-18043 Rev. *J
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4F single
Development support
25
Development support
CYT2B7 has a rich set of documentation, programming tools, and online resources to assist during the devel-
opment process. Visit www.infineon.com to find out more.
25.1
Documentation
A suite of documentation supports CYT2B7 to ensure that you can find answers to your questions quickly. This
section contains a list of some of the key documents.
25.1.1
Software user guide
A step-by-step guide for using the sample driver library along with third-party IDEs such as IAR EWARM and GHS
Multi.
25.1.2
Technical reference manual
The Technical Reference Manual (TRM) contains all the technical detail needed to use a CYT2B7 device, including
a complete description of all registers. The TRM is available in the documentation section at www.infineon.com.
25.2
Tools
CYT2B7 is supported on third-party development tool ecosystems such as IAR and GHS. CYT2B7 is also supported
by Infineon programming utilities for programming, erasing, or reading using Infineon’s MiniProg4 or Segger
J-link. More details are available in the documentation section at www.infineon.com.
Datasheet
86
002-18043 Rev. *J
2022-09-08
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4F single
Electrical specifications
26
Electrical specifications
26.1
Absolute maximum ratings
Use of this device under conditions outside the min and max limits listed in Table 26-1 may cause permanent
damage to the device. Exposure to conditions within the limits of Table 26-1 but beyond those of normal
operation for extended periods of time may affect device reliability. The maximum storage temperature is 150 °C
in compliance with JEDEC Standard JESD22-A103, High Temperature Storage Life. When operated under condi-
tions within the limits of Table 26-1 but beyond those of normal operation, the device may not operate to speci-
fication.
Power considerations
The average chip-junction temperature, TJ, in °C, may be calculated using Equation 1:
TJ = TA + PD JA
Equation. 1
Where:
TA is the ambient temperature in °C.
JA is the package junction-to-ambient thermal resistance, in °C/W.
θ
PD is the sum of PINT and PIO (PD = PINT + PIO).
PINT is the chip internal power. (PINT = VDDD × IDD + VDDA × IA)
PIO represents the power dissipation on input and output pins; user determined.
For most applications, PIO < PINT and may be neglected.
On the other hand, PIO may be significant if the device is configured to continuously drive external modules
and/or memories.
Table 26-1
Absolute maximum ratings
Spec ID
Parameter
Description
Min
Typ
Max
Units
Details/Conditions
For ports 0, 1, 2, 3, 4, 5, 16,
17, 18, 19, 20, 21, 22, 23
SID10
VDDD_ABS
VDDD power supply voltage[35]
VSSD – 0.3
–
VSSD + 6.0
V
VDDIO_1 ≥ VDDD
SID10B
SID10C1
VDDIO_1_ABS
VDDIO_2_ABS
VDDIO_1 power supply voltage[35]
VDDIO_2 power supply voltage[35]
VSSD – 0.3
VSSD – 0.3
–
–
VSSD + 6.0
VSSD + 6.0
V
V
For ports 6, 7, 8, 9[36]
For ports 10, 11, 12, 13, 14,
15
SID11
SID12
SID12A
VDDA_ABS
VREFH_ABS
VREFL_ABS
VDDA analog power supply voltage[35]
Analog reference voltage, HIGH [35]
Analog reference voltage, LOW[35]
VSSA – 0.3
VSSA – 0.3
VSSA – 0.3
–
–
–
VSSA + 6.0
VSSA + 6.0
VSSA + 0.3
V
V
V
VDDIO_2 = VDDA
V
REFH VDDA + 0.3 V
For ports 0, 1, 2, 3, 4, 5, 16,
17, 18, 19, 20, 21, 22, 23
For ports 6, 7, 8, 9[36]
SID15A
SID15B
SID15C
SID16
VI0_ABS0
VI1_ABS1
VI2_ABS2
VIA_ABS
Input voltage[35]
VSSD – 0.5
VSSD – 0.5
VSSD – 0.5
VSSA – 0.3
VSSD – 0.3
VSSD – 0.3
VSSD – 0.3
–
–
–
–
–
–
–
VDDD + 0.5
VDDIO_1 + 0.5
VDDIO_2 + 0.5
VDDA + 0.3
V
V
V
V
Input voltage[35]
For ports 10, 11, 12, 13, 14,
15
Input voltage[35]
Analog input voltage[35]
Output voltage[35]
Output voltage[35]
Output voltage[35]
For ports 0, 1, 2, 3, 4, 5, 16,
17, 18, 19, 20, 21, 22, 23
For ports 6, 7, 8, 9[36]
SID17A
SID17B
SID17C
Notes
VO0_ABS0
VO1_ABS1
VO2_ABS2
VDDD + 0.3
VDDIO_1 + 0.3
VDDIO_2 + 0.3
V
V
For ports 10, 11, 12, 13, 14,
15
35.These parameters are based on the condition that VSSD = VSSA = 0.0 V.
36.The I/Os in VDDIO_1 domain are referred to the VDDD domain in 64-LQFP package.
37.A current-limiting resistor must be provided such that the current at the I/O pin does not exceed rated values at any time, including
during power transients. Refer to Figure 26-1 for more information on the recommended circuit.
38.VDDIO and VDDD must be sufficiently loaded or protected to prevent them from being pulled out of the recommended operating range
by the clamp current.
39.When the conditions of [37], [38], and SID18A/B/C/D are met, |ICLAMP_ABS| supersedes VIA_ABS and VI_ABS
.
40.The definition of “closer” depends on the package. In LQFP packaging, “closest” is determined by counting pins. For example, in a
176-LQFP package, P17.4 (pin 120) is closer to the VDDD on pin 110 than on pin 132. Ports 11 and 21 should not be used for injection
currents. The impact of injection currents is only defined for GPIO_STD/GPIO_ENH type I/Os.
Datasheet
87
002-18043 Rev. *J
2022-09-08
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4F single
Electrical specifications
Table 26-1
Absolute maximum ratings (continued)
Spec ID
Parameter
ICLAMP_ABS
Description
Maximum clamp current [37, 38, 39]
Min
Typ
Max
Units
Details/Conditions
SID18
–5
–
5
mA
Maximum positive clamp current per I/O
supply pin. Limit applies to I/O supply pin
closest to the B+ injected current[40]
+B injected DC currents are
not allowed for Ports 11 and
21.
ICLAMP_SUP-
PLY_POS_ABS
SID18A
–
–
–
–
–
–
–
–
10
10
50
50
mA
mA
mA
mA
Maximum negative clamp current per I/O
ground pin. Limit applies to I/O supply pin
closest to the B+ injected current[40]
+B injected DC currents are
not allowed for Ports 11 and
21.
ICLAMP_SUP-
PLY_NEG_ABS
SID18B
SID18C
SID18D
Maximum positive clamp current per I/O
supply, if not limited by the per supply pin
(based on SID18A).
ICLAMP_TO-
TAL_POS_ABS
Maximum negative clamp current per I/O
ground, if not limited by the per supply pin
(based on SID18B).
ICLAMP_TO-
TAL_NEG_ABS
For GPIO_STD, configured
for drive_sel<1:0>= 0b0X
SID20A
SID20B
SID20C
SID21A
SID21B
IOL1A_ABS
IOL1B_ABS
IOL1C_ABS
IOL2A_ABS
IOL2B_ABS
LOW-level maximum output current [41]
LOW-level maximum output current [41]
LOW-level maximum output current [41]
LOW-level maximum output current [41]
LOW-level maximum output current [41]
–
–
–
–
–
–
–
–
–
–
6
2
1
6
2
mA
mA
mA
mA
mA
For GPIO_STD, configured
for drive_sel<1:0>= 0b10
For GPIO_STD, configured
for drive_sel<1:0>= 0b11
For GPIO_ENH, configured
for drive_sel<1:0>= 0b0X
For GPIO_ENH, configured
for drive_sel<1:0>= 0b10
For GPIO_ENH, configured
for drive_sel<1:0>= 0b11
SID21C
SID26A
SID27A
IOL2C_ABS
LOW-level maximum output current [41]
LOW-level total output current [42]
–
–
–
–
–
–
1
mA
mA
mA
∑IOL_ABS_GPIO
IOH1A_ABS
50
–5
For GPIO_STD, configured
for drive_sel<1:0>= 0b0X
HIGH-level maximum output current [41]
For GPIO_STD, configured
for drive_sel<1:0>= 0b10
SID27B
SID27C
SID28A
SID28B
SID28C
IOH1B_ABS
IOH1C_ABS
IOH2A_ABS
IOH2B_ABS
IOH2C_ABS
HIGH-level maximum output current [41]
HIGH-level maximum output current [41]
HIGH-level maximum output current [41]
HIGH-level maximum output current [41]
HIGH-level maximum output current [41]
–
–
–
–
–
–
–
–
–
–
–2
–1
–5
–2
–1
mA
mA
mA
mA
For GPIO_STD, configured
for drive_sel<1:0>= 0b11
For GPIO_ENH, configured
for drive_sel<1:0>= 0b0X
For GPIO_ENH, configured
for drive_sel<1:0>= 0b10
For GPIO_ENH, configured
mA
mA
for drive_sel<1:0 ≥ 0b11
SID33A
SID34
SID35
SID36
SID37
SID38
∑IOH_ABS_GPIO
HIGH-level total output current [42]
Power dissipation
–
–
–
–
–
–
–
–50
1000
105
125
150
150
PD
TA
–
mW TJ should not exceed 150 °C
Ambient temperature
–40
–40
–55
–40
°C
°C
°C
°C
For S-grade devices
For E-grade devices
TA
Ambient temperature
TSTG
TJ
Storage temperature
Operating Junction temperature
Electrostatic discharge human body
model
SID39A
SID39B1
SID39B2
SID39C
VESD_HBM
VESD_CDM1
VESD_CDM2
ILU
2000
750
–
–
–
–
–
–
V
V
Electrostatic discharge charged device
model for corner pins
Electrostatic discharge charged device
model for all other pins
500
–
V
The maximum pin current the device can
tolerate before triggering a latch-up
–100
100
mA
Notes
41.The maximum output current is the peak current flowing through any one I/O.
42.The total output current is the maximum current flowing through all I/Os (GPIO_STD, and GPIO_ENH).
Datasheet
88
002-18043 Rev. *J
2022-09-08
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4F single
Electrical specifications
VDDD or VDDIO
Current
limiting
resistor
Protection
Diode
+B input
Protection
Diode
VSS
Figure 26-1
Example of a recommended circuit[43]
WARNING:
Semiconductor devices may be permanently damaged by application of stress (including, without limitation, voltage, current, or tempera-
ture) in excess of absolute maximum ratings. Do not exceed any of these ratings.
Datasheet
89
002-18043 Rev. *J
2022-09-08
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4F single
Electrical specifications
26.2
Device-level specifications
Table 26-2
Recommended operating conditions
Unit
s
V
Spec ID Parameter
Description
Min
Typ
Max
Details/Conditions
SID40
VDDD, VDDA
,
Power supply voltage[44]
2.7[45]
–
5.5[46]
VDDIO_1
VDDIO_2
,
,
SID40A VDDIO_1_EFP Power supply voltage for
3
–
–
5.5
11
V
eFuse programming[47]
SID41
Smoothing capacitor[48, 49]
3.76
µF
C
S1
VCCD
VSS
VREF_L
CS1
VSSA
Single-point connection
between analog and
digital grounds
Figure 26-2
Smoothing capacitor
Smoothing capacitor should be placed as close as possible to the VCCD pin.
Notes
43.+B is the positive battery voltage around 45 V.
44.VDDD, VDDIO_1, VDDIO_2, and VDDA do not have any sequencing limitation and can establish in any order. These supplies (except for VDDA
and VDDIO_2) are independent in voltage level. See 12-Bit SAR ADC DC Specifications when using ADC units.
45.3.0 V ±10% is supported with a lower BOD setting option for VDDD and VDDA. This setting provides robust protection for internal timing
but BOD reset occurs at a voltage below the specified operating conditions. A higher BOD setting option is available (consistent with
down to 3.0 V) and guarantees that all operating conditions are met.
46.5.0 V ±10% is supported with a higher OVD setting option for VDDD and VDDA. This setting provides robust protection for internal and
interface timing, but OVD reset occurs at a voltage above the specified operating conditions. A lower OVD setting option is available
(consistent with up to 5.0 V) and guarantees that all operating conditions are met. Voltage overshoot to a higher OVD setting range
for VDDD and VDDA is permissible, provided the duration is less than 2 hours cumulated. Note that during overshoot voltage condition
electrical parameters are not guaranteed.
47.eFuse programming must be executed with the part in a “quiet” state, with minimal activity (preferably only JTAG or a single LIN/CAN
channel on VDDD domain, no activity on VDDIO_1).
48.Smoothing capacitor, CS1 is required per chip (not per VCCD pin). The VCCD pins must be connected together to ensure a low-imped-
ance connection (see the requirement in Figure 26-2).
49.Capacitors used for power supply decoupling or filtering are operated under a continuous DC-bias. Many capacitors used with DC
power across them provide less than their target capacitance, and their capacitance is not constant across their working voltage
range. When selecting capacitors for use with this device, ensure that the selected components provide the required capacitance
under the specific operating conditions of temperature and voltage used in your design. While the temperature coefficient is normally
found within a parts catalog (such as, X7R, C0G, Y5V), the matching voltage coefficient may only be available on the component
datasheet or direct from the manufacturer. Use of components that do not provide the required capacitance under the actual
operating conditions may cause the device to operate to less than datasheet specifications.
Datasheet
90
002-18043 Rev. *J
2022-09-08
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4F single
Electrical specifications
26.3
DC specifications
Table 26-3
DC specifications, CPU current and transition time specifications
All specifications are valid for –40 °C TA 125 °C and for 2.7 V to 5.5 V except where noted.
Spec ID
SID49C1A
Parameter
Description
Min Typ
– 4
Max
9
Units
Details/Conditions
I
LP Active mode (CM4
and CM0+ at 8 MHz, all
peripherals are
mA CM0+ and CM4 clocked at 8 MHz
with IMO.
DD1_CM04_8_1A
All peripherals are disabled. No I/O
disabled)
toggling.
TYP: T = 25 °C, V
= 5.0 V, process
DDD
A
typ (TT), CM0+ and CM4 executing
Dhrystone from flash with cache
enabled
MAX: T = 25 °C, V
= 5.5 V, process
DDD
A
worst (FF), CM0+ and CM4 executing
Dhrystone from flash with cache
enabled.
SID49CA
SID49E1
SID53A1
I
LP Active mode (CM4
and CM0+ at 8 MHz, all
peripherals are
–
5
51
102
46
mA CM0+ and CM4 clocked at 8 MHz
with IMO.
DD1_CM04_8A
DD1_F160_1M
DD2_8_1
All peripherals are enabled. No I/O
toggling.
enabled)
M-DMA transferring data from code
+ work flash, P-DMA chains with
maximum trigger activity.
TYP: T = 25 °C, V
= 5.0 V, process
A
DDD
typ (TT), CM0+ and CM4 executing
Dhrystone from flash with cache
enabled
MAX: T = 125 °C, V
= 5.5 V,
DDD
A
process worst (FF), CM0+ and CM4
executing max_power.c from flash
with cache enabled.
I
Active mode (CM4 at
160 MHz, CM0+ at 80
MHz, all peripherals are
enabled)
–
39
mA PLL enabled at 160 MHz with ECO
reference.
All peripherals are enabled. No I/O
toggling.
M-DMA transferring data from code
+ work flash, P-DMA chains with
maximum trigger activity.
TYP: T = 25 °C, V
= 5.0 V, process
A
DDD
typ (TT), CM4 and CM0+ executing
Dhrystone from flash with cache
enabled.
MAX: T = 125 °C, V
= 5.5 V,
DDD
A
process worst (FF), CM4 and CM0+
executing max_power.c from flash
with cache enabled
I
All CPUs in Sleep mode
–
3
mA PLL disabled, CM4 and CM0+ are
sleeping at 8 MHz with IMO. All
peripherals, peripheral clocks,
interrupts, CSV, DMA, FLL, ECO are
disabled. No I/O toggling.
Typ: T = 25 °C, V
= 5.0 V,
A
DDD
process typ (TT)
Max: T = 125 °C, V
= 5.5 V,
DDD
A
process worst (FF)
Note
50.At cold temperature –5 °C to –40 °C, the DeepSleep to Active transition time can be higher than the max time indicated by as much as 20 µs.
Datasheet
91
002-18043 Rev. *J
2022-09-08
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4F single
Electrical specifications
Table 26-3
DC specifications, CPU current and transition time specifications (continued)
All specifications are valid for –40 °C TA 125 °C and for 2.7 V to 5.5 V except where noted.
Spec ID
Parameter
Description
Min Typ
Max
Units
Details/Conditions
SID56A
I
Average current for
cyclic wake-up
–
46
136
µA
V
= 5.5 V, T = 25 °C, 64-KB SRAM,
DDD A
DD_CWU2
ILO0 operation in DeepSleep, Smart
I/O operations with ILO0, CM0+,
CM4: Retained
operation
This is the average
current for the specified
LP Active mode and
DeepSleep mode (RTC,
WDT, and Event
TYP: process typ (TT)
MAX: process worst (FF)
This average current is achieved
under the following conditions.
1. MCU repetitively goes from
DeepSleep to LP Active with a
period of 32 ms.
generator operating).
2. One of the I/Os is toggled using
Smart I/O to activate an external
sensor connected to an analog
input of A/D in DeepSleep
3. After 200 µs delay, the CM4 wakes
up by event generator trigger to LP
Active mode with IMO and A/D
conversion is triggered by software.
4. Group A/D conversion is
performed on 5 channels with the
sampling time of 1 µs each.
5. Once the group A/D conversion is
finished, and the results fit in the
window of the range comparator,
the I/O is toggled back by software
to de-activate the sensor and the
CM4 goes back to DeepSleep.
SID59A
SID61A
I
I
64-KB SRAM retention,
ILO0 operation in
–
–
35
130
3.5
µA DeepSleep Mode (RTC, WDT, and
event generator operating, all other
peripherals are off except for
retention registers),
DD_DS64B
DD_DS64D
DeepSleep mode
T = 25 °C, CM0+, CM4: Retained
A
Typ: V
= 5.0 V, process typ (TT)
= 5.5 V, process worst (FF)
DDD
DDD
Max: V
64-KB SRAM retention,
ILO0 operation in
0.9
mA DeepSleep Mode steady state at
T = 125 °C (RTC, WDT, and event
A
DeepSleep mode
generator operating, all other
peripherals are off except for
retention registers),
CM0+, CM4: Retained
Typ: V
= 5.0 V, process typ (TT)
= 5.5 V, process worst (FF)
DDD
DDD
Max: V
Hibernate Mode
SID62
I
Hibernate Mode
Hibernate Mode
–
–
5
–
–
µA ILO0/WDT operating. All other
peripherals, and all CPUs are off.
DD_HIB1
T = 25 °C, V
= 5.5 V,
DDD
A
process typ (TT)
SID62A
I
130
µA ILO0/WDT operating. All other
DD_HIB2
peripherals, and all CPUs are off.
T = 125 °C, V
= 5.5 V,
DDD
A
process worst (FF)
Power mode transition times
SID65
t
Power down time from
Active to DeepSleep
–
–
2.5
µs When the IMO is already running
and all HFCLK roots are at least 8
MHz. HFCLK roots that are slower
than this will require additional
time to turn off.
ACT_DS
Datasheet
92
002-18043 Rev. *J
2022-09-08
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4F single
Electrical specifications
Table 26-3
DC specifications, CPU current and transition time specifications (continued)
All specifications are valid for –40 °C TA 125 °C and for 2.7 V to 5.5 V except where noted.
Spec ID
SID63
Parameter
Description
Min Typ
Max
10
Units
Details/Conditions
[50]
t
DeepSleep to Active
transition time (IMO
clock, SRAM execution)
DeepSleep to Active
transition time (IMO
clock, flash execution)
–
–
–
–
µs When using the 8-MHz IMO.
Measured from wakeup interrupt
during DeepSleep until wakeup.
µs When using the 8-MHz IMO.
Measured from wakeup interrupt
during DeepSleep until flash
execution.
µs When using the FLL to generate 96
MHz from the 8-MHz IMO. Measured
from wakeup interrupt during
DS_ACT
[50]
SID63C
SID63A
SID63D
SID63B
SID68
t
20
DS_ACT
[50]
t
t
t
t
DeepSleep to Active
transition time (FLL
clock, SRAM execution)
–
–
–
–
–
–
–
–
15
DS_ACT_FLL
DS_ACT_FLL1
DS_ACT_PLL
HVR_ACT
DeepSleep until the FLL locks.
[50]
DeepSleep to Active
transition time (FLL
clock, flash execution)
21.5
µs When using the FLL to generate 96
MHz from the 8-MHz IMO. Measured
from wakeup interrupt during
DeepSleep until flash execution.
[50]
DeepSleep to Active
transition time (PLL
clock, SRAM or flash
execution)
Release time from HV
reset (POR, BOD, OVD,
OCD, WDT, Hibernate
wakeup, or XRES_L)
release until CM0+
begins executing ROM
boot
60
µs When using the PLL to generate 96
MHz from the 8-MHz IMO. Measured
from wakeup interrupt during
DeepSleep until the PLL locks.
265
µs Without boot runtime.
Guaranteed by design
SID68A
SID68B
t
t
Release time from LV
reset (Fault, Internal
system reset, MCWDT,
or CSV) during
–
–
–
–
10
15
µs Without boot runtime.
Guaranteed by design
LVR_ACT
LVR_DS
Active/Sleep until CM0+
begins executing ROM
boot
Release time from LV
reset (Fault, or MCWDT)
during DeepSleep until
CM0+ begins executing
ROM boot
µs Without boot runtime.
Guaranteed by design
SID80A
SID80B
SID81A
t
t
t
ROM boot startup time
or wakeup time from
hibernate in NORMAL
protection state
ROM boot startup time
or wakeup time from
hibernate in SECURE
protection state
–
–
–
–
–
–
1800
2740
80
µs Guaranteed by Design, CM0+
clocked at 100 MHz (Flash boot
version 3.1.0.556 and later)
RB_N
RB_S
FB
µs Guaranteed by Design, CM0+
clocked at 100 MHz (Flash boot
version 3.1.0.556 and later)
Flash boot startup time
or wakeup time from
hibernate in
µs Guaranteed by Design,
TOC2_FLAGS=0x2CF, CM0+ clocked
at 100 MHz (Flash boot version
3.1.0.556 and later), Listen window
= 0 ms
NORMAL/SECURE
protection state
Datasheet
93
002-18043 Rev. *J
2022-09-08
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4F single
Electrical specifications
Table 26-3
DC specifications, CPU current and transition time specifications (continued)
All specifications are valid for –40 °C TA 125 °C and for 2.7 V to 5.5 V except where noted.
Spec ID
Parameter
Description
Min Typ
Max
Units
Details/Conditions
SID81B
t
Flash boot with app
authentication time in
NORMAL/SECURE
protection state
–
–
5000
µs Guaranteed by Design,
TOC2_FLAGS=0x24F, CM0+ clocked
at 100 MHz (Flash boot version
3.1.0.556 and later), Listen window
= 0 ms, Public key exponent e =
0x010001, App size is 64 KB with the
last 256 bytes being a digital
signature in RSASSA-PKCS1-v1.5
Valid for RSA2K.
FB_A
SID80A_2
SID80B_2
SID81A_2
t
t
t
ROM boot startup time
or wakeup time from
hibernate in NORMAL
protection state
ROM boot startup time
or wakeup time from
hibernate in SECURE
protection state
–
–
–
–
–
–
2930
4680
200
µs Guaranteed by Design, CM0+
clocked at 50 MHz (Flash boot
version earlier than 3.1.0.556)
RB_N_2
RB_S_2
FB_2
µs Guaranteed by Design, CM0+
clocked at 50 MHz (Flash boot
version earlier than 3.1.0.556)
Flash boot startup time
or wakeup time from
hibernate in
µs Guaranteed by Design,
TOC2_FLAGS=0x2CF, CM0+ clocked
at 50 MHz (Flash boot version
earlier than 3.1.0.556), Listen
window = 0 ms
NORMAL/SECURE
protection state
SID81B_2
t
Flash boot with app
authentication time in
NORMAL/SECURE
protection state
–
–
10000
µs Guaranteed by Design,
TOC2_FLAGS=0x24F, CM0+ clocked
at 50 MHz (Flash boot version
earlier than 3.1.0.556), Listen
window= 0 ms, Publickeyexponent
e = 0x010001, App size is 64 KB with
the last 256 bytes being a digital
signature in RSASSA-PKCS1-v1.5
Valid for RSA2K.
FB_A_2
Regulator specifications
SID600
SID601
V
Core supply voltage
1.05 1.1
1.15
150
V
CCD
I
I
I
I
Regulator operating
current in
–
–
–
–
80
1.5
–
µA Guaranteed by design
DD_ACT
Active/Sleep mode
SID602
SID604
SID603
Regulator operating
current in
20
µA Guaranteed by design
mA Without triggering OVD
DD_DPSLP
OUT
DeepSleep mode
Available regulator
output current for
operation
150
375
In-rush current
–
mA Average V
current until C
DDD
RUSH
s1
(connected to V
pin) is charged
CCD
after Active regulator is turned on
Datasheet
94
002-18043 Rev. *J
2022-09-08
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4F single
Electrical specifications
26.4
Reset specifications
All specifications are valid for –40 °C TA 125 °C and for 2.7 V to 5.5 V except where noted.
Table 26-4
XRES_L reset
Paramete
Spec ID
Description
Min
Typ
Max
Units Details/Conditions
r
XRES_L DC specifications
SID73
IDD_XRES
IDD when XRES_L asserted
–
–
0.9
mA TA = 125 °C,
VDDD = 5.5 V, process
worst (FF)
SID74
SID75
SID76
SID77
SID78
VIH
VIL
RPULLUP
CIN
VHYSXRES
Input voltage HIGH threshold 0.7 × VDDD
–
–
–
–
–
–
V
V
kΩ
pF
V
CMOS input
CMOS input
Input voltage LOW threshold
Pull-up resistor
–
7
0.3 × VDDD
20
5
–
Input capacitance
–
Input voltage hysteresis
0.05 × VDDD
XRES_L AC specifications
SID70
tXRES_ACT
–
–
265
µs Without boot
runtime.
XRES_L release to Active
transition time
Guaranteed by
design
SID71
SID72
tXRES_PW
tXRES_FT
XRES_L pulse width
Pulse suppression width
5
100
–
–
–
–
µs
ns
release
HV/LV reset
System clock
System reset
release
RESET
1
ACTIVE
4
MODES
2
3
1:
2:
3:
4:
SID68/68A/68B: Time from HV/LV reset release until CM0+ begins executing ROM boot
SID80A/80B: ROM boot code operation
SID81A/81B: Flash boot code operation
User code operation
Figure 26-3
Reset sequence
Datasheet
95
002-18043 Rev. *J
2022-09-08
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4F single
Electrical specifications
26.5
I/O
All specifications are valid for –40 °C TA 125 °C and for 2.7 V to 5.5 V except where noted.
Table 26-5
Spec ID
I/O specifications
Parameter Description
Min
Typ
Max
Units
Details/Conditions
GPIO_STD Specifications for ports P1 through P23
SID650
VOL1_GPIO_STD
Output voltage
LOW level
–
–
0.6
V
IOL = 6 mA
drive_sel<1:0> = 0b0X,
4.5 V ≤VDDD or VDDIO_1 or
VDDIO_2 ≤ 5.5 V
SID650C VOL1C_GPIO_STD
Output voltage
LOW level
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
0.4
0.4
0.4
0.4
0.4
0.4
–
V
V
V
V
V
V
V
V
V
V
V
IOL = 5 mA
drive_sel<1:0> = 0b0X,
4.5 V ≤VDDD or VDDIO_1 or
VDDIO_2 ≤ 5.5 V
SID651
SID652
VOL2_GPIO_STD
Output voltage
LOW level
IOL = 2 mA
drive_sel<1:0> = 0b0X,
2.7 V ≤VDDD or VDDIO_1 or
VDDIO_2 < 4.5 V
VOL3_GPIO_STD
Output voltage
LOW level
IOL = 1 mA
drive_sel<1:0> = 0b10,
2.7 V ≤VDDD or VDDIO_1 or
VDDIO_2 < 4.5 V
SID652C VOL3C_GPIO_STD
Output voltage
LOW level
IOL = 2 mA
drive_sel<1:0> = 0b10,
4.5 V ≤VDDD or VDDIO_1 or
VDDIO_2 ≤ 5.5 V
SID653
VOL4_GPIO_STD
Output voltage
LOW level
IOL = 0.5 mA
drive_sel<1:0> = 0b11,
2.7 V ≤VDDD or VDDIO_1 or
VDDIO_2 < 4.5 V
SID653C VOL4C_GPIO_STD
Output voltage
LOW level
IOL = 1 mA
drive_sel<1:0> = 0b11,
4.5 V ≤VDDD or VDDIO_1 or
VDDIO_2 ≤ 5.5 V
(V
or
SID654
SID655
SID656
VOH1_GPIO_STD
VOH2_GPIO_STD
VOH3_GPIO_STD
Output voltage
HIGH level
IOH = –2 mA
DDD
DDIO_1
DDIO_2)
V
or
drive_sel<1:0> = 0b0X,
2.7 V ≤VDDD or VDDIO_1 or
VDDIO_2 < 4.5 V
V
V
V
V
V
– 0.5
(V
or
or
Output voltage
HIGH level
–
IOH = –5 mA
DDD
DDIO_1
DDIO_2)
V
drive_sel<1:0> = 0b0X,
4.5 V ≤VDDD or VDDIO_1 or
VDDIO_2 ≤ 5.5 V
– 0.5
(V
or
Output voltage
HIGH level
–
IOH = –1 mA
DDD
DDIO_1
DDIO_2)
V
or
drive_sel<1:0> = 0b10,
2.7 V ≤VDDD or VDDIO_1 or
VDDIO_2 < 4.5 V
– 0.5
(V
or
or
SID656C VOH3C_GPIO_STD
Output voltage
HIGH level
–
IOH = –2 mA
DDD
DDIO_1
DDIO_2)
V
drive_sel<1:0> = 0b10,
4.5 V ≤VDDD or VDDIO_1 or
VDDIO_2 ≤ 5.5 V
– 0.5
(V
or
SID657
VOH4_GPIO_STD
Output voltage
HIGH level
–
IOH = –0.5 mA
DDD
DDIO_1
DDIO_2)
V
or
drive_sel<1:0> = 0b11,
2.7 V ≤VDDD or VDDIO_1 or
– 0.5
VDDIO_2 < 4.5 V
Datasheet
96
002-18043 Rev. *J
2022-09-08
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4F single
Electrical specifications
Table 26-5
Spec ID
I/O specifications (continued)
Parameter
Description
Min
Typ
Max
Units
Details/Conditions
(V
DDIO_1
DDIO_2)
or
SID657C VOH4C_GPIO_STD
Output voltage
HIGH level
–
–
V
IOH = –1 mA
DDD
V
or
drive_sel<1:0> = 0b11,
4.5 V ≤VDDD or VDDIO_1 or
VDDIO_2 ≤ 5.5 V
V
– 0.5
SID658
RPD_GPIO_STD
RPU_GPIO_STD
VIH_CMOS_GPI-
O_STD
Pull-down resis-
tance
25
50
100
kΩ
SID659
SID660
Pull-up resistance
Input voltage
25
0.7 × (V
DDIO_1
V
DDIO_2)
50
–
100
–
kΩ
V
DDD
HIGH threshold in or V
or
CMOS mode
SID661
SID662
SID663
VIH_TTL_GPIO_STD Input voltage
2.0
–
–
–
–
–
V
V
V
HIGH threshold in
TTL mode
0.8×(V
V
or
VIH_AUTO_GPI-
O_STD
Input voltage
HIGH threshold in
AUTO mode
DDD
DDIO_1
or
V
DDIO_2)
–
VIL_CMOS_GPI-
O_STD
Input voltage LOW
threshold in CMOS
mode
0.3 ×
DDD
DDIO_1
or
(V
or
V
V
DDIO_2)
SID664
SID665
VIL_TTL_GPIO_STD Input voltage LOW
–
–
–
–
0.8
V
V
threshold in TTL
mode
VIL_AUTO_GPIO_STD Input voltage LOW
threshold in AUTO
0.5 ×
(VDDD or
mode
V
DDIO_1 or
VDDIO_2
)
SID666
SID668
VHYST_CMOS_GPI- Hysteresis in
O_STD
0.05 × (V
or V
–
–
–
–
V
V
DDD
DDIO_1
DDIO_2)
CMOS mode
or
V
VHYST_AUTO_GPI- Hysteresis in
0.05 × (V
or V
DDD
or
AUTO mode
DDIO_1
DDIO_2)
O_STD
V
SID669
SID670
Cin_GPIO_STD
IIL_GPIO_STD
Input pin capaci-
tance
Input leakage
current
–
–
5
pF For 10 MHz and 100 MHz
–250
0.02
250
nA For GPIO_STD except
P21.0, P21.1, P21.2,
P21.3, P21.4, P23.3,
P23.4.
VDDIO_1 = VDDIO_2 = VDDD
= VDDA = 5.5 V, VSSD < VI <
VDDD, VDDIO_1, VDDIO_2
–40 °C TA 125 °C
TYP: TA = 25 °C,
VDDIO_1 = VDDIO_2 = VDDD
= VDDA = 5.0 V
Datasheet
97
002-18043 Rev. *J
2022-09-08
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4F single
Electrical specifications
Table 26-5
Spec ID
I/O specifications (continued)
Parameter
Description
Min
Typ
Max
Units
Details/Conditions
SID670C IIL_GPIO_STD_B
Input leakage
current
–700
0.02
700
nA Only for P21.0, P21.1,
P21.2, P21.3, P21.4,
P23.3, P23.4.
VDDIO_1 = VDDIO_2 = VDDD
= VDDA = 5.5 V, VSSD < VI <
VDDD, VDDIO_1, VDDIO_2
–40 °C TA 125 °C
TYP: TA = 25 °C,
VDDIO_1 = VDDIO_2 = VDDD
= VDDA = 5.0 V
SID671
SID672
SID673
tR or tF
Rise time or fall
1
1
1
–
–
–
10
20
20
ns 20-pF load,
drive_sel<1:0> = 0b00
(fast)_20_0_GPI-
time (10% to 90%
of VDDIO
)
O_STD
tR or tF
Rise time or fall
ns 50-pF load,
drive_sel<1:0> = 0b00
(fast)_50_0_GPI-
time (10% to 90%
of VDDIO
)
O_STD
tR or tF
Rise time or fall
ns 20-pF load,
(fast)_20_1_GPI-
time (10% to 90%
drive_sel<1:0> = 0b01,
guaranteed by design
of VDDIO
)
O_STD
SID674
SID675
SID676
tR or tF
Rise time or fall
1
1
–
–
–
20
20
ns 10-pF load,
(fast)_10_2_GPI-
time (10% to 90%
drive_sel<1:0> = 0b10,
guaranteed by design
of VDDIO
)
O_STD
tR or tF
Rise time or fall
ns 6-pF load,
(fast)_6_3_GPI-
time (10% to 90%
drive_sel<1:0> = 0b11,
guaranteed by design
of VDDIO
)
O_STD
tF (fast)_100_GPI- Fall time (30% to
70% of VDDIO
0.35
250
ns 10-pF to 400-pF load,
RPU = 767 Ω,
)
O_STD
drive_sel<1:0>= 0b00,
Freq = 100 kHz
SID677
tF (fast)_400_GPI- Fall time (30% to
O_STD
0.35
–
250
ns 10-pF to 400-pF load,
RPU = 350 Ω,
70% of VDDIO
)
drive_sel<1:0>= 0b00,
Freq = 400 kHz
SID678
SID679
fIN_GPIO_STD
Input frequency
–
–
–
–
100
50
MHz
fOUT_GPIO_STD0H Output frequency
fOUT_GPIO_STD0L Output frequency
fOUT_GPIO_STD1H Output frequency
MHz 20-pF load,
drive_sel<1:0>= 00,
4.5 V ≤VDDD or VDDIO_1 or
VDDIO_2 ≤ 5.5 V
MHz 20-pF load,
drive_sel<1:0>= 00,
2.7 V ≤VDDD or VDDIO_1 or
VDDIO_2 < 4.5 V
MHz 20-pF load,
drive_sel<1:0>= 01,
4.5 V ≤VDDD or VDDIO_1 or
VDDIO_2 ≤ 5.5 V
SID680
SID681
–
–
–
–
32
25
Datasheet
98
002-18043 Rev. *J
2022-09-08
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4F single
Electrical specifications
Table 26-5
I/O specifications (continued)
Parameter Description
Spec ID
Min
–
Typ
–
Max
15
Units
MHz 20-pF load,
drive_sel<1:0>= 01,
2.7 V ≤VDDD or VDDIO_1 or
DDIO_2 < 4.5 V
MHz 10-pF load,
drive_sel<1:0>= 10,
4.5 V ≤VDDD or VDDIO_1 or
DDIO_2 ≤ 5.5 V
MHz 10-pF load,
drive_sel<1:0>= 10,
2.7 V ≤VDDD or VDDIO_1 or
DDIO_2 < 4.5 V
MHz 6-pF load,
drive_sel<1:0>= 11,
Details/Conditions
SID682
fOUT_GPIO_STD1L Output frequency
fOUT_GPIO_STD2H Output frequency
fOUT_GPIO_STD2L Output frequency
fOUT_GPIO_STD3H Output frequency
fOUT_GPIO_STD3L Output frequency
V
SID683
SID684
SID685
SID686
–
–
–
–
–
–
–
–
25
15
15
10
V
V
4.5 V ≤VDDD or VDDIO_1 or
VDDIO_2 ≤ 5.5 V
MHz 6-pF load,
drive_sel<1:0>= 11,
2.7 V ≤VDDD or VDDIO_1 or
VDDIO_2 < 4.5 V
GPIO_ENH specifications only for P0
SID650A VOL1_GPIO_ENH
SID650D VOL1D_GPIO_ENH
SID651A VOL2_GPIO_ENH
SID652A VOL3_GPIO_ENH
SID652D VOL3D_GPIO_ENH
SID653A VOL4_GPIO_ENH
SID653D VOL4D_GPIO_ENH
SID654A VOH1_GPIO_ENH
SID655A VOH2_GPIO_ENH
Output voltage
–
–
–
–
–
–
–
–
–
–
0.6
0.4
0.4
0.4
0.4
0.4
0.4
–
V
V
V
V
V
V
V
V
V
IOL = 6 mA
LOW level
drive_sel<1:0> = 0b0X,
2.7 V ≤ VDDD ≤ 5.5 V
Output voltage
LOW level
–
IOL = 5 mA
drive_sel<1:0> = 0b0X,
4.5 V ≤ VDDD ≤ 5.5 V
Output voltage
LOW level
–
IOL = 2 mA, 3 mA
drive_sel<1:0> = 0b0X,
2.7 V ≤ VDDD < 4.5 V
Output voltage
LOW level
–
IOL = 1 mA
drive_sel<1:0> = 0b10,
2.7 V ≤ VDDD < 4.5 V
Output voltage
LOW level
–
IOL = 2 mA
drive_sel<1:0> = 0b10,
4.5 V ≤ VDDD ≤ 5.5 V
Output voltage
LOW level
–
IOL = 0.5 mA
drive_sel<1:0> = 0b11,
2.7 V ≤ VDDD < 4.5 V
Output voltage
LOW level
–
IOL = 1 mA
drive_sel<1:0> = 0b11,
4.5 V ≤ VDDD ≤ 5.5 V
Output voltage
HIGH level
VDDD – 0.5
VDDD – 0.5
IOL = –2 mA
drive_sel<1:0> = 0b0X,
2.7 V ≤ VDDD < 4.5 V
Output voltage
HIGH level
–
IOL = –5 mA
drive_sel<1:0> = 0b0X,
4.5 V ≤ VDDD ≤ 5.5 V
Datasheet
99
002-18043 Rev. *J
2022-09-08
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4F single
Electrical specifications
Table 26-5
Spec ID
I/O specifications (continued)
Parameter
Description
Min
Typ
Max
Units
Details/Conditions
SID656A VOH3_GPIO_ENH
Output voltage
HIGH level
VDDD – 0.5
–
–
V
IOL = –1 mA
drive_sel<1:0> = 0b10,
2.7 V ≤ VDDD < 4.5 V
SID656D VOH3D_GPIO_ENH Output voltage
HIGH level
VDDD – 0.5
VDDD – 0.5
VDDD – 0.5
25
–
–
–
–
V
V
IOL = –2 mA
drive_sel<1:0> = 0b10,
4.5 V ≤ VDDD ≤ 5.5 V
SID657A VOH4_GPIO_ENH
Output voltage
HIGH level
IOL = –0.5 mA
drive_sel<1:0> = 0b11,
2.7 V ≤ VDDD < 4.5 V
SID657D VOH4D_GPIO_ENH Output voltage
HIGH level
–
–
V
IOL = –1 mA
drive_sel<1:0> = 0b11,
4.5 V ≤ VDDD ≤ 5.5 V
SID658A RPD_GPIO_ENH
SID659A RPU_GPIO_ENH
Pull-down resis-
tance
Pull-up resistance
50
100
kΩ
25
50
100
kΩ
–
–
SID660A VIH_CMOS_GPI-
Input voltage
HIGH threshold in
CMOS mode
0.7 × VDDD
V
O_ENH
2
–
–
SID661A VIH_TTL_GPIO_ENH Input voltage
V
V
V
V
V
HIGH threshold in
TTL mode
SID662A VIH_AUTO_GPI-
Input voltage
HIGH threshold in
AUTO mode
0.8 × VDDD
–
–
–
–
–
O_ENH
SID663A VIL_CMOS_GPI-
Input voltage LOW
threshold in CMOS
mode
–
–
–
0.3 ×
VDDD
O_ENH
SID664A VIL_TTL_GPIO_ENH Input voltage LOW
0.8
threshold in TTL
mode
SID665A VIL_AUTO_GPI-
Input voltage LOW
threshold in AUTO
mode
0.5 ×
VDDD
O_ENH
SID666A VHYST_CMOS_GPI- Hysteresis in
CMOS mode
0.05 × VDDD
0.05 × VDDD
–
–
–
–
–
V
V
O_ENH
SID668A VHYST_AUTO_GPI- Hysteresis in
AUTO mode
O_ENH
SID669A Cin_GPIO_ENH
Input pin capaci-
tance
–
5
pF For 10 MHz and 100 MHz
SID670A IIL_GPIO_ENH
Input leakage
current
–350
0.055
350
nA VDDD = VDDA = 5.5 V,
V
SSD < VI < VDDD,
–40 °C ≤ TA ≤ 125 °C
TYP: TA = 25 °C,
VDDD = VDDA = 5.0 V
SID671A tR or tF
(fast)_20_0_GPI-
Rise time or fall
1
1
–
–
10
20
ns 20-pF load,
time (10% to 90%
drive_sel<1:0> = 0b00,
of VDDIO
)
O_ENH
slow = 0
ns 50-pF load,
SID672A tR or tF
(fast)_50_0_GPI-
Rise time or fall
time (10% to 90%
drive_sel<1:0> = 0b00,
slow = 0
of VDDIO
)
O_ENH
Datasheet
100
002-18043 Rev. *J
2022-09-08
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4F single
Electrical specifications
Table 26-5
Spec ID
I/O specifications (continued)
Parameter
Description
Min
Typ
Max
Units
Details/Conditions
SID673A tR or tF
Rise time or fall
1
–
20
ns 20-pF load,
(fast)_20_1_GPI-
time (10% to 90%
drive_sel<1:0> = 0b01,
slow = 0,
guaranteed by design
of VDDIO
)
O_ENH
SID674A tR or tF
Rise time or fall
1
1
–
–
–
–
20
20
ns 10-pF load,
(fast)_10_2_GPI-
time (10% to 90%
drive_sel<1:0> = 0b10,
slow = 0,
guaranteed by design
of VDDIO
)
O_ENH
SID675A tR or tF
Rise time or fall
ns 6-pF load,
(fast)_6_3_GPI-
time (10% to 90%
drive_sel<1:0> = 0b11,
slow = 0,
guaranteed by design
of VDDIO
)
O_ENH
SID676A tF_I2C
Fall time (30% to 20 × (VDDD
/
/
250
160
ns 10-pF to 400-pF load,
drive_sel<1:0> = 0b00,
slow = 1,
(slow)_GPIO_ENH 70% of VDDIO
)
5.5)
minimum RPU = 400 Ω
SID677A tR or tF
(slow)_20_GPI-
Rise time or fall
time (10% to 90%
of VDDIO
20 × (VDDD
5.5)
ns 20-pF load,
drive_sel<1:0> = 0b00,
slow = 1,
)
O_ENH
output frequency = 1
MHz
SID678A tR or tF
Rise time or fall
20 × (VDDD
5.5)
/
–
250
ns 400-pF load,
drive_sel<1:0> = 0b00,
slow = 1,
(slow)_400_GPI-
time (10% to 90%
of VDDIO
)
O_ENH
output frequency = 400
kHz
SID679A fIN_GPIO_ENH
Input frequency
–
–
–
–
100
50
MHz
SID680A fOUT_GPIO_ENH0H Output frequency
SID681A fOUT_GPIO_ENH0L Output frequency
SID682A fOUT_GPIO_ENH1H Output frequency
SID683A fOUT_GPIO_ENH1L Output frequency
SID684A fOUT_GPIO_ENH2H Output frequency
SID685A fOUT_GPIO_ENH2L Output frequency
MHz 20-pF load,
drive_sel<1:0>= 0b00,
4.5 V ≤ VDDD ≤ 5.5 V
MHz 20-pF load,
drive_sel<1:0>= 0b00,
2.7 V ≤ VDDD < 4.5 V
MHz 20-pF load,
drive_sel<1:0>= 0b01,
4.5 V ≤ VDDD ≤ 5.5 V
MHz 20-pF load,
drive_sel<1:0>= 0b01,
2.7 V ≤ VDDD < 4.5 V
MHz 10-pF load,
drive_sel<1:0>= 0b10,
4.5 V ≤ VDDD ≤ 5.5 V
MHz 10-pF load,
drive_sel<1:0>= 0b10,
2.7 V ≤ VDDD < 4.5 V
–
–
–
–
–
–
–
–
–
–
32
25
15
25
15
Datasheet
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002-18043 Rev. *J
2022-09-08
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4F single
Electrical specifications
Table 26-5
Spec ID
I/O specifications (continued)
Parameter Description
Min
–
Typ
–
Max
15
Units
MHz 6-pF load,
drive_sel<1:0>= 0b11,
4.5 V ≤ VDDD ≤ 5.5 V
MHz 6-pF load,
Details/Conditions
SID686A fOUT_GPIO_ENH3H Output frequency
SID687A fOUT_GPIO_ENH3L Output frequency
GPIO input specifications
–
–
10
drive_sel<1:0>= 0b11,
2.7 V ≤ VDDD < 4.5 V
SID98
tFT
Analog glitch filter
(pulse
–
–
–
50[51]
ns One filter per port group
ns
suppression
width)
SID99
tINT
Minimum pulse
width for GPIO
interrupt
160
–
Note
51.If longer pulse suppression width is required, use Smart I/O.
Datasheet
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002-18043 Rev. *J
2022-09-08
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4F single
Electrical specifications
26.6
Analog peripherals
All specifications are valid for –40 °C TA 125 °C and for 2.7 V to 5.5 V except where noted.
26.6.1
SAR ADC
0xFFF
0xFFE
0xFFD
Actual conversion
characteristics
1.5 LSb
1 LSb (N - 1) + 0.5 LSb
VNT
0x003
0x002
0x001
Actual conversion
characteristics
Ideal
characteristics
0.5 LSb
VREFH
VREFL
Analog input
[LSb]
[V]
Total error of digital output N = ( VNT {1 LSb × (N – 1) + 0.5 LSb} ) / 1 LSb
1 LSb (Ideal value) = (VREFH – VREFL) / 4096
N: A/D converter digital output value
V
V
V
ZT (Ideal value): VREFL + 0.5 LSb [V]
FST (Ideal value): VREFH – 1.5 LSb [V]
NT: Voltage at which the digital output changes from N – 1 to N
Figure 26-4
ADC characteristics and error definitions
12-Bit SAR ADC DC specifications
Table 26-6
Spec ID
Parameter
A_RES
A_VINS
A_VREFH
Description
SAR ADC resolution
Input voltage range
VREFH voltage range
Min
–
Typ
–
Max
12
Units
bits
V
Details/Conditions
SID100
SID101
SID102
VREFL
2.7
–
VREFH
VDDA
–
V
ADC performance degrades
when high reference is higher
than supply
[52]
SID102A A_VDDA
SID103 A_VREFL
VDDA voltage range
VREFL voltage range
2.7
–
–
5.5
V
V
VSSA
VSSA
ADC performance degrades
when low reference is lower
than ground
SID103A Vband_gap
Internal band gap reference
voltage
0.882
–
0.9
–
0.918
0.25
V
SID19A
SID19B
SID19C
CLAMP_COU-
Ratio of current collected on a
pin to the positive current
%
PLING_RA-
TIO_POS
injected into a neighboring pin
CLAMP_COU-
PLING_RA-
TIO_NEG
Ratio of current collected on a
pin to the negative current
injected into a neighboring pin
–
–
–
–
1.2
50
%
RCLAMP_INTERNAL
Internal pin resistance to
current collection point
Ω
Datasheet
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2022-09-08
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4F single
Electrical specifications
26.6.2
Calculating the impact of neighboring pins
The three ADC specifications based on SID19A, SID19B, and SID19C, can be used to calculate the pin leakage and
resulting ADC offset caused by injection current using the below formula:
ILEAK = IINJECTED × CLAMP_COUPLING_RATIO
VERROR = ILEAK × (RCLAMP_INTERNAL + RSOURCE)
Code Error = VERROR × 212 / VREF
Where:
IINJECTED is the injected current in mA.
ILEAK is the calculated leakage current in mA.
V
V
ERROR is the voltage error calculated due to leakage currents in V.
REF is the ADC reference voltage in V.
Differential linearity error
Integral linearity error
0xFFF
Ideal
characteristics
Actual conversion
characteristics
N + 1
0xFFE
0xFFD
VFST
Actual conversion
characteristics
(Measured value)
(1 LSb [N - 1] + VZT)
N
VNT
(Measured value)
0x004
0x003
0x002
0x001
N - 1
Actual conversion
characteristics
V(N +
1)T
(Measured value)
VNT
(Measured value)
Ideal
characteristics
Actual conversion
characteristics
N -2
VZT
(Measured value)
VREFL
Analog input
VREFL
Analog input
VREFH
VREFH
Integral linearity error of digital output N = (VNT
–
{1 LSb × (N
–
1) + VZT}) / 1 LSb
[LSb]
[LSb]
[V]
Differential linearity error of digital output N = (V(N + 1)T – VNT
1 LSb = (VFST – VZT ) / 4094
– 1 LSb ) / 1 LSb
VZT: Voltage for which digital output changes from 0x000 to 0x001
FST: Voltage for which digital output changes from 0xFFE to 0xFFF.
V
Figure 26-5
Integral and differential linearity errors
Note
52.VDDD must be greater than 0.8 × VDDA when ADC[2] is enabled. VDDIO_1 must be greater than 0.8 × VDDA when ADC[0] is enabled.
Datasheet
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4F single
Electrical specifications
EXTERNAL CIRCUIT
INTERNAL EQUIVALENT CIRCUIT
VDDIO
Channel selection MUX and ADC
REXT
RVIN
CVIN
CEXT
CIN
ESD Protection
REXT: Source impedance
CEXT: On-PCB capacitance
CIN: I/O pad or Input capacitance
RVIN: ADC equivalent input resistance
CVIN: ADC equivalent input capacitance
K: Constant for sampling accuracy, K = ln(abs(4096/LSbSAMPLE))
Sampling Time (tSAMPLE) requirement is shown in the following equation
tSAMPLE > K x { CVIN x ( RVIN + REXT ) + ( CIN + CEXT ) x (REXT) } [seconds]
K = value of 9.0 is recommended to get ±0.5 LSb sampling accuracy at 12-bit (LSbSAMPLE = ±0.5)
Figure 26-6
Table 26-7
ADC equivalent circuit for analog input
SAR ADC AC specifications
Spec ID Parameter
Description
Min
Typ
Max
Units Details/Conditions
SID104 VZT
Zero transition voltage
–20
–
20
mV VDDA = 2.7 V to 5.5 V,
–40 °C ≤ TA ≤ 125 °C
before offset
adjustment
SID105 VFST
Full-scale transition
voltage
–20
–
20
mV VDDA = 2.7 V to 5.5 V,
–40 °C ≤ TA ≤ 125 °C
before offset
adjustment
SID114 fADC_4P5
SID114A fADC_2P7
SID113 tS_4P5
ADC operating frequency
ADC operating frequency
Analog input sample time
2
2
412
–
–
–
26.67
13.34
–
MHz 4.5 V ≤ VDDA ≤ 5.5 V
MHz 2.7 V ≤ VDDA < 4.5 V
ns 4.5 V ≤ VDDA ≤ 5.5 V
Guaranteed by design
SID113A tS_2P7
Analog input sample time
600
2
–
–
–
–
ns 2.7 V ≤ VDDA < 4.5 V
Guaranteed by design
SID113B tS_DR_4P5
Analog input sample time
when input is from
µs 4.5 V ≤ VDDA ≤ 5.5 V
Guaranteed by design
diagnostic reference
SID113C tS_DR_2P7
Analog input sample time
when input is from
2.5
–
–
µs 2.7 V ≤ VDDA < 4.5 V
Guaranteed by design
diagnostic reference
SID113 tS_TS
D
SID106 tST_4P5
Analog input sample time
for temperature sensor
Max throughput (Sample
per second)
3
–
–
–
–
1
µs 2.7 V VDDA ≤ 5.5 V
Guaranteed by design
Msps 4.5 V ≤ VDDA ≤ 5.5 V,
80 MHz / 3 = 26.67 MHz,
11 sampling cycles,
15 conversion cycles
Datasheet
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2022-09-08
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4F single
Electrical specifications
Table 26-7
SAR ADC AC specifications (continued)
Spec ID Parameter
Description
Min
Typ
Max
Units Details/Conditions
SID106A tST_2P7
Max throughput (Sample
per second)
–
–
0.5
Msps 2.7 V ≤ VDDA < 4.5 V
80 MHz / 6 = 13.3 MHz,
11 sampling cycles,
15 conversion cycles
SID107 CVIN
SID108 RVIN1
SID108A RVIN2
SID108B RDREF1
SID108C RDREF2
ADC input sampling
capacitance
Input path ON resistance
(4.5 V to 5.5 V)
Input path ON resistance
(2.7 V to 4.5 V)
Diagnostic path ON resis-
tance (4.5 V to 5.5 V)
–
–
–
–
–
–
–
–
–
4.8
9.4
13.9
40
50
4
pF Guaranteed by design
kΩ Guaranteed by design
kΩ Guaranteed by design
kΩ Guaranteed by design
kΩ Guaranteed by design
%
–
–
Diagnostic path ON resis-
tance (2.7 V to 4.5 V)
–
SID119 ACC_RLAD Diagnostic reference
resistor ladder accuracy
SID109 A_TE
–4
–5
Total error
Total error
5
LSb VDDA = VREFH = 2.7 V to
5.5 V, VREFL = VSSA
–40 °C ≤ TA ≤ 125 °C
Total error after offset
and gain adjustment at
12 bit resolution mode
SID109A A_TEB
–12
–
12
LSb VDDA = VREFH = 2.7 V to
5.5 V, VREFL = VSSA
–40 °C ≤ TA ≤ 125 °C
Total error before
offset and gain
adjustment at 12 bit
resolution mode
SID110 A_INL
SID111 A_DNL
SID112 A_CE
Integral nonlinearity
–2.5
–0.99
–1
–
–
–
2.5
1.9
1
LSb VDDA = 2.7 V to 5.5 V,
–40 °C ≤ TA ≤ 125 °C
Differential nonlinearity
LSb VDDA = 2.7 V to 5.5 V,
–40 °C ≤ TA ≤ 125 °C
Channel-to-channel
LSb VDDA = 2.7 V to 5.5 V,
variation (for channels
connected to same ADC)
–40 °C ≤ TA ≤ 125 °C
SID115 IAIC
Analog input leakage
current
Diagnostic reference
current
Analog power supply
current while ADC is
operating
–350
70
–
350
70
nA When input pad is
selected for conversion
µA
SID116 IDIAGREF
SID117 IVDDA
–
–
360
550
µA Per enabled ADC
SID117A IVDDA_DS
SID118 IVREF
Analog power supply
current while ADC is not
operating
Analog reference voltage
current while ADC is
operating
–
–
–
21
µA Per enabled ADC
µA Per enabled ADC
360
550
Datasheet
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002-18043 Rev. *J
2022-09-08
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4F single
Electrical specifications
Table 26-7
SAR ADC AC specifications (continued)
Spec ID Parameter
Description
Min
Typ
Max
Units Details/Conditions
SID118A IVREF_LEAK Analog reference voltage
current while ADC is not
–
1.8
5
µA Per enabled ADC
operating
26.6.3
Temperature sensor
Table 26-8
Temperature sensor specifications
Spec ID Parameter
Description
Min Typ Max Units
Details/Conditions
SID201
T
Temperature sensor
accuracy 2
–5
–
5
°C
–40 °C ≤ T ≤ 150 °C
SENSACC2
J
This spec is valid when using ADC[0]
(V
), ADC[1](V
)orADC[2]
DDIO_2
DDIO_1
DDD
(V ) with the following
conditions:
a. 3.0 V ≤ V , V
or V
=
=
DDD DDIO_1
DDIO_2
DDIO_2
V
= V
≤ 3.6 V
REFH
DDA
or
b. 4.5 V ≤ V , V
or V
DDD DDIO_1
V
= V
≤ 5.5 V
REFH
DDA
SID201A
T
Temperature sensor
accuracy 3
–10
–
10
°C
–40 °C ≤ T ≤ 150 °C
J
SENSACC3
This spec is valid when using ADC[0]
(V ) or ADC[2] (V ) with the
DDIO_1
DDD
following condition:
2.7 V ≤ V
2.7 V ≤ V
or V
≤ 5.5 V and
DDD
DDA
DDIO_1
= V
≤ 5.5 V and
REFH
0.8 × V
< V
or V
DDA
DDD DDIO_1
26.6.4
Voltage divider accuracy
Table 26-9
Voltage divider accuracy
Spec ID Parameter
Description
Min Typ Max Units
Details/Conditions
SID202 VMONDIV
Uncorrected monitor
voltage divider accuracy
(measured by ADC),
compared to ideal
supply/2
–20
2
20
%
Any HV supply pad within
2.7-V–5.5-V operating range
Datasheet
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4F single
Electrical specifications
26.7
AC specifications
Unless otherwise noted, the timings are defined with the guidelines mentioned in the Figure 26-7.
Definition of rise / fall times
VDDD or VDDIO_1/2
80 %
80 %
20 %
20 %
VSSD
tR
tF
Time Reference Point Definition
VDDD or VDDIO_1/2
0.5 x VDDD or VDDIO_1/2
VSSD
Timing Reference Points
Figure 26-7
AC timings specifications
Datasheet
108
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2022-09-08
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4F single
Electrical specifications
26.8
Digital peripherals
All specifications are valid for –40 °C TA 125 °C and for 2.7 V to 5.5 V except where noted.
Table 26-10 Timer/counter/PWM (TCPWM) specifications
Spec ID Parameter
Description
Min
Typ
Max
Units
Details/Conditions
SID120 fC
TCPWM operating
frequency
–
–
100
MHz fC = peripheral clock
SID121 tPWMENEXT Inputtriggerpulsewidth 2 / fC
for all trigger events
–
–
ns Trigger Events can be Stop,
Start, Reload, Count,
Capture, or Kill depending on
which mode of operation is
selected.
SID122 tPWMEXT
Output trigger pulse
widths
2 / fC
–
–
ns Minimum possible width of
Overflow, Underflow, and
Counter = Compare (CC)
value trigger outputs
SID123 tCRES
SID124 tPWMRES
SID125 tQRES
Resolution of counter
PWM resolution
1 / fC
1 / fC
2 / fC
–
–
–
–
–
–
ns Minimum time between
successive counts
ns MinimumpulsewidthofPWM
output
ns Minimum pulse width
between Quadrature phase
inputs.
Quadrature inputs
resolution
TCPWM Timing Diagrams
Input Signal
VIH
VIL
1
2
1
2
VOH
VOL
Output Signal
1: tPWMENEXT, tQRES
2: tPWMEXT
Figure 26-8
TCPWM timing diagrams
Datasheet
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2022-09-08
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4F single
Electrical specifications
Table 26-11 Serial communication block (SCB) specifications
Spec ID Parameter
SID129 fSCB
Description
Min
–
Typ
–
Max Units Details/Conditions
100
MHz
SCB operating frequency
I2C Interface-Standard-mode
SID130
SID131
fSCL
SCL clock frequency
–
–
–
100
–
kHz
ns
tHD;STA
Hold time, START
condition
4000
SID132
SID133
SID134
tLOW
Low period of SCL
High period of SCL
4700
4000
4700
–
–
–
–
–
–
ns
ns
ns
tHIGH
tSU;STA
Setup time for a repeated
START
SID135
tHD;DAT
Data hold time, for
receiver
0
–
–
ns
SID136
SID138
SID139
SID140
tSU;DAT
tF
tSU;STO
tBUF
Data setup time
250
–
–
–
–
–
–
300
–
ns
Fall time of SCL and SDA
Setup time for STOP
ns Input and output
4000
4700
ns
ns
Bus-free time between
START and STOP
–
SID141
SID142
SID143
SID144
SID145
CB
Capacitive load for each
bus line
–
–
–
0
3
–
–
–
–
–
400
3450
3450
0.4
pF
ns
ns
tVD;DAT
tVD;ACK
VOL
Time for data signal from
SCL LOW to SDA output
Data valid acknowledge
time
LOW level output voltage
V
Open-drain at 3 mA
sink current
IOL
LOW level output current
–
mA VOL = 0.4 V
I2C Interface-Fast-mode
SID150
SID151
fSCL_F
SCL clock frequency
–
–
–
400
–
kHz
ns
tHD;STA_F
Hold time, START
condition
600
SID152
SID153
SID154
tLOW_F
Low period of SCL
High period of SCL
1300
600
–
–
–
–
–
–
ns
ns
ns
tHIGH_F
tSU;STA_F
Setup time for a repeated
START
600
SID155
tHD;DAT_F
Data hold time, for
receiver
0
–
–
ns
SID156
SID158
tSU;DAT_F
tF_F
Data setup time
100
–
–
–
ns
Fall time of SCL and SDA
20 ×
300
ns Input and output,
GPIO_ENH: slow
(VDDD / 5.5)
mode, 400 pF load
Datasheet
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4F single
Electrical specifications
Table 26-11 Serial communication block (SCB) specifications (continued)
Spec ID Parameter
Description
Min
Typ
Max Units Details/Conditions
SID158A tFA_F
Fall time of SCL and SDA
0.35
–
300
ns Input and output
GPIO_STD:
drive_sel<1:0>= 0b00
MIN: 10 pF load,
RPU = 35.41 kΩ
MAX: 400 pF load,
RPU = 350 Ω
SID159
SID160
tSU;STO_F
tBUF_F
Setup time for STOP
600
–
–
–
–
ns Input and output
ns
Bus free time between
START and STOP
1300
SID161
SID162
SID163
SID164
CB_F
Capacitive load for each
bus line
–
–
–
–
–
–
–
–
400
900
900
50
pF
ns
ns
ns
tVD;DAT_F
tVD;ACK_F
tSP_F
Time for data signal from
SCL LOW to SDA output
Data valid acknowledge
time
Pulse width of spikes that
must be suppressed by
the input filter
SID165
VOL_F
LOW level output voltage
0
–
0.4
V
Open-drain at 3 mA
sink current
SID165
SID167
IOL_F
LOW level output current
LOW level output current
3
6
–
–
–
–
mA VOL = 0.4 V
IOL2_F
mA VOL = 0.6 V[53]
I2C Interface-Fast-Plus mode
SID170
SID171
fSCL_FP
SCL clock frequency
–
–
–
1
–
MHz
ns
tHD;STA_FP
Hold time, START
condition
260
SID172
SID173
SID174
tLOW_FP
Low period of SCL
High period of SCL
500
260
260
–
–
–
–
–
–
ns
ns
ns
tHIGH_FP
tSU;STA_FP
Setup time for a repeated
START
SID175
tHD;DAT_FP
Data hold time, for
receiver
0
–
–
ns
ns
SID176
SID178
tSU;DAT_FP
tF_FP
Data setup time
50
–
–
–
Fall time of SCL and SDA
20 ×
160
ns Input and output
20-pF load
(VDDD /5.5)
GPIO_ENH: slow
mode
SID179
SID180
tSU;STO_FP
tBUF_FP
Setup time for STOP
260
500
–
–
–
–
ns Input and output
ns
Bus free time between
START and STOP
SID181
SID182
CB_FP
Capacitive load for each
bus line
–
–
–
–
20
pF
ns
tVD;DAT_FP
Time for data signal from
SCL LOW to SDA output
450
Datasheet
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4F single
Electrical specifications
Table 26-11 Serial communication block (SCB) specifications (continued)
Spec ID Parameter
Description
Min
Typ
Max Units Details/Conditions
SID183
tVD;ACK_FP
Data valid acknowledge
time
–
–
450
ns
SID184
tSP_FP
Pulse width of spikes that
must be suppressed by
the input filter
–
–
50
ns
SID186
SID187
VOL_FP
IOL_FP
LOW level output voltage
0
3
–
–
0.4
–
V
Open-drain at 3 mA
sink current
LOW level output current
mA VOL = 0.4 V[54]
SPI Interface Master (Full-clock mode: LATE_MISO_SAMPLE = 1) [Conditions: drive_sel<1:0>= 0x]
SID190
fSPI
SPI operating frequency
–
–
12.5
MHz Do not use half-clock
mode:
LATE_MISO_SAMPLE
= 0
SID191
SID192
tDMO
tDSI
SPI Master: MOSI valid
after SCLK driving edge
–
–
–
15
–
ns
ns
SPI Master: MISO valid
before SCLK capturing
edge
40
SID193
SID194
SID196
tHMO
SPI Master: Previous
MOSI data hold time
0
–
0
–
–
–
–
ns
ns
ns
tW_SCLK_H_L SPI SCLK pulse width
HIGH or LOW
0.4 × (1 /
fSPI
–
)
tDHI
SPI Master: MISO hold
time after SCLK capturing
edge
SID198
SID199
SID195
tEN_SETUP
tEN_SHOLD
CSPIM_MS
SSEL valid, before the
0.5 ×
–
–
–
–
–
ns Min is half clock
period
first SCK capturing edge
(1/fSPI
)
SSEL hold, after the last
SCK capturing edge
0.5 ×
ns Min is half clock
period
(1/fSPI
)
SPI capacitive load
–
10
pF
SPI Interface Slave (internally clocked) [Conditions: drive_sel<1:0>= 0x]
SID205
SID206
fSPI_INT
tDMI_INT
SPI operating frequency
–
5
–
–
10
–
MHz
ns
SPI Slave: MOSI Valid
before Sclock capturing
edge
SID207
tDSO_INT
SPI Slave: MISO Valid
after Sclock driving edge,
in the internal-clocked
mode
–
–
62
ns
SID208
SID209
tHSP
SPI Slave: Previous MISO
data hold time
3
–
–
–
–
ns
ns
tEN_SETUP_INT SPI Slave: SSEL valid to
first SCK valid edge
33
Notes
53.In order to drive full bus load at 400 kHz, 6 mA IOL is required at 0.6 V VOL
.
54.In order to drive full bus load at 1 MHz, 20 mA IOL is required at 0.4 V VOL. However, this device does not support it.
Datasheet
112
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2022-09-08
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4F single
Electrical specifications
Table 26-11 Serial communication block (SCB) specifications (continued)
Spec ID Parameter
Description
Min
Typ
Max Units Details/Conditions
SID210
SID211
SID212
tEN_HOLD_INT SPI Slave Select active
(LOW) from last SCLK
hold
33
–
–
–
–
ns
ns
ns
tEN_SETUP_PRE SPI Slave: from SSEL
valid, to SCK falling edge
20
20
–
–
before the first data bit
tEN_HOLD_PRE SPI Slave: from SCK
falling edge before the
first data bit, to SSEL
invalid
SID213
SID214
tEN_SETUP_CO SPI Slave: from SSEL
valid, to SCK falling edge
in the first data bit
20
20
–
–
–
–
ns
ns
tEN_HOLD_CO SPI Slave: from SCK
falling edge in the first
data bit, to SSEL invalid
SID215
SID216
SID217
tW_DIS_INT
SPI Slave Select inactive
time
40
20
20
–
–
–
–
–
–
ns
ns
ns
tW_SCLKH_INT SPI SCLK pulse width
HIGH
tW_SCLKL_INT SPI SCLK pulse width
LOW
SID218
SID219
tSIH_INT
SPI MOSI hold from SCLK
SPI capacitive load
12
–
–
–
–
ns
pF
CSPIS_INT
10
SPI Interface Slave (externally clocked) [Conditions: drive_sel<1:0>= 0x]
SID220
SID221
fSPI_EXT
tDMI_EXT
SPI operating frequency
–
5
–
–
12.5
–
MHz
ns
SPI Slave: MOSI Valid
before Sclock capturing
edge
SID222
tDSO_EXT
SPI Slave: MISO Valid
after Sclock driving edge,
in the external-clocked
mode
–
–
32
ns
SID223
SID224
SID225
tHSO_EXT
SPI Slave: Previous MISO
data hold time
3
–
–
–
–
–
–
ns
ns
ns
tEN_SETUP_EXT SPI Slave: SSEL valid to
first SCK valid edge
40
40
tEN_HOLD_EXT SPI Slave Select active
(LOW) from last SCLK
hold
SID226
SID227
SID228
SID229
tW_DIS_EXT
SPI Slave Select inactive
time
80
34
34
20
–
–
–
–
–
–
–
–
ns
ns
ns
ns
tW_SCLKH_EXT SPI SCLK pulse width
HIGH
tW_SCLKL_EXT SPI SCLK pulse width
LOW
tSIH_EXT
SPI MOSI hold from SCLK
Datasheet
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4F single
Electrical specifications
Table 26-11 Serial communication block (SCB) specifications (continued)
Spec ID Parameter
Description
Min
–
Typ
–
Max Units Details/Conditions
SID230
SID231
CSPIS_EXT
tVSS_EXT
SPI capacitive load
10
33
pF
ns
SPI Slave: MISO valid
after SSEL falling edge
(CPHA = 0)
–
–
UART Interface
SID240 fBPS
Data rate
–
–
10
Mbps
8
9
7
70%
30%
70%
70%
70%
30%
6
SDA
30%
30%
12
8
9
4
70%
70%
70%
70%
30%
70%
30%
SCL
30%
30%
30%
30%
30%
2
1
3
START condition
11
70%
30%
70%
30%
70%
70%
SDA
SCL
30%
70%
2
14
10
13
70%
70%
30%
9th clock
5
Repeated START
condition
STOP condition
START condition
1: SCL clock period = 1/fSCL
2: Hold time, START condition = tHD;STA
3: LOW period of SCL = tLOW
4: HIGH period of SCL = tHIGH
5: Setup time for a repeated START = tSU;STA
6: Data hold time, for receiver = tHD;DAT
7: Data setup time = tSU;DAT
8: Fall time of SCL and SDA = tF
9: Rise time of SCL and SDA = tR
10: Setup time for STOP = tSU;STO
11: Bus-free time between START and STOP = tBUF
12: Time for data signal from SCL LOW to SDA output = tVD;DAT
13: Data valid acknowledge time = tVD;ACK
14: Pulse width of spikes that must be suppressed by the input filter = tSP
Figure 26-9
I2C timing diagrams
Datasheet
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4F single
Electrical specifications
SPI Master Timing Diagrams (LATE_MISO_SAMPLE=1)
CPHA=0
9
SSEL
2
1
3
SCLK
(CPOL=0)
4
4
SCLK
(CPOL=1)
5
6
MISO
(input)
7
8
MOSI
(output)
1: SCLK period = 1 / fSPI
2: Enable lead time (setup)= tEN_SETUP = Depends on SPI_CTRL.SSEL_SETUP_DEL (Refer to the Register TRM)
3: Enable trail time (hold)= tEN_HOLD = Depends on SPI_CTRL.SSEL_HOLD_DEL (Refer to the Register TRM)
4: SCLK high or low time = tW_SCLK_H_L
5: Input data setup time = tDSI
6: Input data hold time = tDHI
7: Output data valid after SCLK driving edge= tDMO
8: Output data hold time= tHMO
9: SSEL high pulse width = Depends on SPI_CTRL.SSEL_INTER_FRAME_DEL (Refer to the Register TRM)
Figure 26-10 SPI master timing diagrams with LOW clock phase
Datasheet
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4F single
Electrical specifications
SPI Master Timing Diagrams (LATE_MISO_SAMPLE=1)
CPHA=1
9
SSEL
2
3
1
SCLK
(CPOL=0)
4
4
SCLK
(CPOL=1)
5
6
MISO
(input)
7
8
MOSI
(output)
1: SCLK period = 1 / fSPI
2: Enable lead time (setup) = tEN_SETUP = Depends on SPI_CTRL.SSEL_SETUP_DEL (Refer to the Register TRM)
3: Enable trail time (hold) = tEN_HOLD = Depends on SPI_CTRL.SSEL_HOLD_DEL (Refer to the Register TRM)
4: SCLK high or low time = tW_SCLK_H_L
5: Input data setup time = tDSI
6: Input data hold time = tHDI
7: Output data valid after SCLK driving edge = tDMO
8: Output data hold time = tHMO
9: SSEL high pulse width = Depends on SPI_CTRL.SSEL_INTER_FRAME_DEL (Refer to the Register TRM)
Figure 26-11 SPI master timing diagrams with HIGH clock phase
Datasheet
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4F single
Electrical specifications
SPI Slave Timing Diagrams
CPHA=0
10
SSEL
2
1
3
SCLK
(CPOL=0)
4
4
SCLK
(CPOL=1)
8
7
9
MISO
(output)
5
6
MOSI
(input)
1: SCLK period = 1 / fSPI_EXT
2: enable lead time (setup)= tEN_SETUP_EXT
3: enable trail time (hold)= tEN_HOLD_EXT
4: SCLK high or low time = tw_SCLKH_EXT = tw_SCLKL_EXT
5: input data setup time = tDMI_EXT
6: input data hold time = tSIH_EXT
7: output data valid after SCLK driving edge= tDSO_EXT
8: output data valid after SSEL falling edge (CPHA=0)= tVSS_EXT
9: output data hold time = tHSO
10: SSEL high pulse width= tDIS_EXT
Figure 26-12 SPI slave timing diagrams with LOW clock phase
Datasheet
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2022-09-08
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4F single
Electrical specifications
SPI slave Timing Diagrams
CPHA=1
9
SSEL
2
3
1
SCLK
(CPOL=0)
4
SCLK
(CPOL=1)
7
8
MISO
(output)
5
6
MOSI
(input)
1: SCLK period = 1 / fSPI_EXT
2: enable lead time (setup) = tEN_SETUP_EXT
3: enable trail time (hold) = tEN_HOLD_EXT
4: SCLK high or low time = tw_SCLKH_EXT = tw_SCLKL_EXT
5: input data setup time = tDMI_EXT
6: input data hold time = tSIH_EXT
7: output data valid after SCLK driving edge = tDSO_EXT
8: output data hold time = tHSO
9: SSEL high pulse width = tDIS_EXT
Figure 26-13 SPI slave timing diagrams with HIGH clock phase
26.8.1
LIN specifications
Table 26-12 LIN specifications
Spec ID
SID249
Parameter
fLIN
Description
Internal clock frequency to
the LIN block
Min
–
Typ Max Units Details/Conditions
–
100
MHz
SID250
SID250A BR_REF
BR_NOM
Bit rate on the LIN bus
1
1
–
–
20
kbps Guaranteed by design
Bit rate on the LIN bus (not in
standard LIN specification)
for re-flashing in LIN slave
mode
115.2 kbps Guaranteed by design
26.8.2
CAN FD specifications
Table 26-13 CAN FD specifications
Spec ID
SID630
Parameter
fHCLK
Description
System clock frequency
Min
–
Typ Max Units Details/Conditions
–
100
MHz fcclk ≤ fhclk,
Guaranteed by design
SID631
fCCLK
CAN clock frequency
–
–
100
MHz fcclk ≤ fhclk,
Guaranteed by design
Datasheet
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4F single
Electrical specifications
26.9
Memory
All specifications are valid for –40 °C TA 125 °C and for 2.7 V to 5.5 V except where noted.
Table 26-14 Flash DC specifications
Spec ID Parameter
SID260 VPE
Description
Erase and program voltage
Min Typ Max Units
2.7 5.5
Details/Conditions
–
V
Table 26-15 Flash AC specifications
Spec ID Parameter Description
Min Typ Max Units
Details/Conditions
SID257
fFO
Maximum flash memory
operation frequency
–
–
100 MHz Zero wait access to
code-flash memory up to 100
MHz
Zero wait access with cache
hit up to 160 MHz
SID254
tERS_SUS
Maximum time from erase
suspend command till erase is
indeed suspend
–
–
37.5
–
µs
SID255
SID258
tERS_RES_SUS Minimum time allowed from
erase resume to erase suspend
tBC_WF
250
–
–
–
µs Guaranteed by design
Blank check time for N-bytes of
work-flash
10 +
0.3 ×
N
µs At 100 MHz, N ≥4 and multiple
of 4, excludes system
overhead time
SID259
tSECTORERASE1 Sector erase time
(Code-flash: 32 KB)
–
–
45
15
80
5
90
ms Includes internal
preprogramming time
ms Includes internal
preprogramming time
ms Includes internal
preprogramming time
ms Includes internal
preprogramming time
µs Excludes system overhead
time
µs Excludes system overhead
time
SID259A tSECTORERASE2 Sector erase time
(Code-flash: 8 KB)
30
SID261
SID262
SID263
SID264
SID265
SID266
SID267
SID268
SID269
SID612
SID613
tSECTORERASE3 Sector erase time
(Work-flash, 2 KB)
tSECTORERASE4 Sector erase time
(Work-flash, 128 bytes)
–
160
15
–
tWRITE1
tWRITE2
tWRITE3
tWRITE4
tFRET1
64-bit write time (Code-flash)
–
30
40
60
256-bit write time (Code-flash)
–
70
4096-bit write time
(Code-flash)[55]
32-bit write time (Work-flash)
–
320 1200 µs Excludes system overhead
time
30
–
60
µs Excludes system overhead
time
Code-flash retention.
20
20
10
–
–
–
years TA (power on and off) ≤ 85 °C
1000 program/erase cycles
average
tFRET3
Work-flash retention.
–
–
years TA (power on and off) ≤ 85 °C
125,000 program/erase cycles
average
tFRET4
Work-flash retention.
–
–
years TA (power on and off) ≤ 85 °C
250,000 program/erase cycles
average
ICC_ACT2
ICC_ACT3
Program operating current
(Code or Work-flash)
Erase operating current (Code
or Work-flash)
15
15
48
48
mA VDDD = 5 V
Guaranteed by design
–
mA VDDD = 5 V
Guaranteed by design
Note
55.The code-flash includes a 'Write Buffer' of 4096-bit. If the application software writes this buffer multiple times, to get the overall write
time multiply one sector write time with the corresponding factor (say for factor 64, example, 64 x 512 B = 32 KB [one sector]).
Datasheet
119
002-18043 Rev. *J
2022-09-08
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4F single
Electrical specifications
26.10
System resources
All specifications are valid for –40 °C TA 125 °C and for 2.7 V to 5.5 V except where noted.
Table 26-16 System resources
Details/
Spec ID
Parameter
Description
Min
Typ
Max
Units
Conditions
Power-on-reset specifications
SID270 VPOR_R
SID276 VPOR_F
SID271 VPOR_H
SID272 tDLY_POR
VDDD rising voltage to deassert
POR
VDDD falling voltage to assert
POR
1.5
1.45
20
–
–
–
–
2.35
2.1
300
3
V
V
Guaranteed by
design
Level detection hysteresis
mV Guaranteed by
design
µs Guaranteed by
design
Delay between VDDD rising
through 2.3 V and an internal
deassertion of POR
–
SID273 tPOFF
SID274 POR_RR1
VDDD Power off time
100
–
–
–
–
100
µs VDDD < 1.45 V
VDDD power ramp rate with
robust BOD (BOD operation is
guaranteed)
mV/µs This ramp
supports robust
BOD
SID275 POR_RR2
VDDD power ramp rate without
robust BOD
–
–
1000
mV/µs This ramp does
not support
robust BOD
tPOFF must be
satisfied
High-voltage BOD (HV BOD) specifications
SID500 VTR_2P7_R
HV BOD 2.7 V rising detection
2.474
2.55
2.627
V
V
point for VDDD and VDDA
(default)
SID501 VTR_2P7_F
HV BOD 2.7 V falling detection 2.449 2.525 2.601
point for VDDD and VDDA
(default)
SID502 VTR_3P0_R
SID503 VTR_3P0_F
HV BOD 3.0 V rising detection
point for VDDD and VDDA
HV BOD 3.0 V falling detection
point for VDDD and VDDA
2.765
2.85
2.936
2.91
100
10
V
2.74
2.825
V
SID505 HVBOD_RR_A Power ramp rate: VDDD and
DDA (Active)
SID506 HVBOD_RR_DS Power ramp rate: VDDD and
VDDA (DeepSleep)
SID507 tDLY_ACT_HVBOD Active mode delay between
VDDD falling/rising through
–
–
–
–
–
–
mV/µs
mV/µs
V
0.5
µs Guaranteed by
design
VTR_2P7_F/R or VTR_3P0_F/R and
an internal HV BOD signal
transitioning
SID507A tDLY_ACT_HVBOD Active mode delay between
VDDA falling/rising through
–
–
1
µs Guaranteed by
design
VTR_2P7_F/R or VTR_3P0_F/R and
internal HV BOD signal transi-
tioning
Datasheet
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4F single
Electrical specifications
Table 26-16 System resources (continued)
Details/
Spec ID
Parameter
Description
Min
Typ
Max
Units
Conditions
SID507 tDLY_DS_HVBOD DeepSleep mode delay
–
–
4
µs Guaranteed by
design
B
between VDDD/VDDA
falling/rising through
VTR_2P7_F/R or VTR_3P0_F/R and
an internal HV BOD signal
transitioning
SID508 tRES_HVBOD
Response time of HV BOD,
VDDD/VDDA supply. (For
100
–
–
ns
Guaranteed by
design
falling-then-rising supply at
max ramp rate; threshold is
VTR_2P7_F or VTR_3P0_F.)
Low-voltage BOD (LV BOD) specifications
SID510 VTR_R_LVBOD
LV BOD rising detection point
for VCCD
LV BOD falling detection point 0.892
for VCCD
0.917 0.945 0.973
V
V
SID511 VTR_F_LVBOD
0.92
–
0.948
1
SID515 tDLY_ACT_LVBOD Active delay between VCCD
falling/rising through
–
µs Guaranteed by
design
VTR_R/F_LVBOD and an internal
LV BOD signal transitioning
SID515A tDLY_DS_LVBOD
DeepSleep mode delay
between VCCD falling/rising
through VTR_R/F_LVBOD and an
internal LV BOD signal transi-
tioning
Response time of LV BOD. (For
falling-then-rising supply at
max ramp rate; threshold is
VTR_F_LVBOD.)
–
–
–
12
–
µs Guaranteed by
design
SID516 tRES_LVBOD
100
ns
Guaranteed by
design
Low-voltage detector (LVD) DC specifications
SID520 VTR_2P8_F
SID521 VTR_2P9_F
SID522 VTR_3P0_F
SID523 VTR_3P1_F
SID524 VTR_3P2_F
SID525 VTR_3P3_F
SID526 VTR_3P4_F
SID527 VTR_3P5_F
SID528 VTR_3P6_F
SID529 VTR_3P7_F
LVD 2.8 V falling detection
point for VDDD
LVD 2.9 V falling detection
point for VDDD
LVD 3.0 V falling detection
point for VDDD
LVD 3.1 V falling detection
point for VDDD
LVD 3.2 V falling detection
point for VDDD
LVD 3.3 V falling detection
point for VDDD
LVD 3.4 V falling detection
point for VDDD
LVD 3.5 V falling detection
point for VDDD
Typ – 4% 2800 Typ + 4% mV
Typ – 4% 2900 Typ + 4% mV
Typ – 4% 3000 Typ + 4% mV
Typ – 4% 3100 Typ + 4% mV
Typ – 4% 3200 Typ + 4% mV
Typ – 4% 3300 Typ + 4% mV
Typ – 4% 3400 Typ + 4% mV
Typ – 4% 3500 Typ + 4% mV
Typ – 4% 3600 Typ + 4% mV
Typ – 4% 3700 Typ + 4% mV
LVD 3.6 V falling detection
point for VDDD
LVD 3.7 V falling detection
point for VDDD
Datasheet
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4F single
Electrical specifications
Table 26-16 System resources (continued)
Details/
Spec ID
Parameter
Description
Min
Typ
Max
Units
Conditions
SID530 VTR_3P8_F
SID531 VTR_3P9_F
SID532 VTR_4P0_F
SID533 VTR_4P1_F
SID534 VTR_4P2_F
SID535 VTR_4P3_F
SID536 VTR_4P4_F
SID537 VTR_4P5_F
SID538 VTR_4P6_F
SID539 VTR_4P7_F
SID540 VTR_4P8_F
SID541 VTR_4P9_F
SID542 VTR_5P0_F
SID543 VTR_5P1_F
SID544 VTR_5P2_F
SID545 VTR_5P3_F
SID546 VTR_2P8_R
SID547 VTR_2P9_R
SID548 VTR_3P0_R
SID549 VTR_3P1_R
SID550 VTR_3P2_R
SID551 VTR_3P3_R
SID552 VTR_3P4_R
SID553 VTR_3P5_R
LVD 3.8 V falling detection
point for VDDD
LVD 3.9 V falling detection
point for VDDD
LVD 4.0 V falling detection
point for VDDD
LVD 4.1 V falling detection
point for VDDD
LVD 4.2 V falling detection
point for VDDD
LVD 4.3 V falling detection
point for VDDD
LVD 4.4 V falling detection
point for VDDD
LVD 4.5 V falling detection
point for VDDD
LVD 4.6 V falling detection
point for VDDD
LVD 4.7 V falling detection
point for VDDD
LVD 4.8 V falling detection
point for VDDD
LVD 4.9 V falling detection
point for VDDD
LVD 5.0 V falling detection
point for VDDD
LVD 5.1 V falling detection
point for VDDD
LVD 5.2 V falling detection
point for VDDD
LVD 5.3 V falling detection
point for VDDD
LVD 2.8 V rising detection
point for VDDD
LVD 2.9 V rising detection
point for VDDD
LVD 3.0 V rising detection
point for VDDD
LVD 3.1 V rising detection
point for VDDD
LVD 3.2 V rising detection
point for VDDD
LVD 3.3 V rising detection
point for VDDD
LVD 3.4 V rising detection
point for VDDD
LVD 3.5 V rising detection
point for VDDD
Typ – 4% 3800 Typ + 4% mV
Typ – 4% 3900 Typ + 4% mV
Typ – 4% 4000 Typ + 4% mV
Typ – 4% 4100 Typ + 4% mV
Typ – 4% 4200 Typ + 4% mV
Typ – 4% 4300 Typ + 4% mV
Typ – 4% 4400 Typ + 4% mV
Typ – 4% 4500 Typ + 4% mV
Typ – 4% 4600 Typ + 4% mV
Typ – 4% 4700 Typ + 4% mV
Typ – 4% 4800 Typ + 4% mV
Typ – 4% 4900 Typ + 4% mV
Typ – 4% 5000 Typ + 4% mV
Typ – 4% 5100 Typ + 4% mV
Typ – 4% 5200 Typ + 4% mV
Typ – 4% 5300 Typ + 4% mV
Typ – 4% 2825 Typ + 4% mV Same as
VTR_2P8_F + 25 mV
Typ – 4% 2925 Typ + 4% mV Same as
VTR_2P9_F + 25 mV
Typ – 4% 3025 Typ + 4% mV Same as
VTR_3P0_F + 25 mV
Typ – 4% 3125 Typ + 4% mV Same as
VTR_3P1_F + 25 mV
Typ – 4% 3225 Typ + 4% mV Same as
VTR_3P2_F + 25 mV
Typ – 4% 3325 Typ + 4% mV Same as
VTR_3P3_F + 25 mV
Typ – 4% 3425 Typ + 4% mV Same as
VTR_3P4_F + 25 mV
Typ – 4% 3525 Typ + 4% mV Same as
VTR_3P5_F + 25 mV
Datasheet
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4F single
Electrical specifications
Table 26-16 System resources (continued)
Details/
Spec ID
Parameter
Description
Min
Typ
Max
Units
Conditions
SID554 VTR_3P6_R
SID555 VTR_3P7_R
SID556 VTR_3P8_R
SID557 VTR_3P9_R
SID558 VTR_4P0_R
SID559 VTR_4P1_R
SID560 VTR_4P2_R
SID561 VTR_4P3_R
SID562 VTR_4P4_R
SID563 VTR_4P5_R
SID564 VTR_4P6_R
SID565 VTR_4P7_R
SID566 VTR_4P8_R
SID567 VTR_4P9_R
SID568 VTR_5P0_R
SID569 VTR_5P1_R
SID570 VTR_5P2_R
SID571 VTR_5P3_R
SID573 LVD_RR_A
SID574 LVD_RR_DS
SID575 tDLY_ACT_LVD
LVD 3.6 V rising detection
point for VDDD
LVD 3.7 V rising detection
point for VDDD
LVD 3.8 V rising detection
point for VDDD
LVD 3.9 V rising detection
point for VDDD
LVD 4.0 V rising detection
point for VDDD
LVD 4.1 V rising detection
point for VDDD
LVD 4.2 V rising detection
point for VDDD
LVD 4.3 V rising detection
point for VDDD
LVD 4.4 V rising detection
point for VDDD
LVD 4.5 V rising detection
point for VDDD
LVD 4.6 V rising detection
point for VDDD
LVD 4.7 V rising detection
point for VDDD
LVD 4.8 V rising detection
point for VDDD
LVD 4.9 V rising detection
point for VDDD
LVD 5.0 V rising detection
point for VDDD
LVD 5.1 V rising detection
point for VDDD
Typ – 4% 3625 Typ + 4% mV Same as
VTR_3P6_F + 25 mV
Typ – 4% 3725 Typ + 4% mV Same as
VTR_3P7_F + 25 mV
Typ – 4% 3825 Typ + 4% mV Same as
VTR_3P8_F + 25 mV
Typ – 4% 3925 Typ + 4% mV Same as
VTR_3P9_F + 25 mV
Typ – 4% 4025 Typ + 4% mV Same as
VTR_4P0_F + 25 mV
Typ – 4% 4125 Typ + 4% mV Same as
VTR_4P1_F + 25 mV
Typ – 4% 4225 Typ + 4% mV Same as
VTR_4P2_F + 25 mV
Typ – 4% 4325 Typ + 4% mV Same as
VTR_4P3_F + 25 mV
Typ – 4% 4425 Typ + 4% mV Same as
VTR_4P4_F + 25 mV
Typ – 4% 4525 Typ + 4% mV Same as
VTR_4P5_F + 25 mV
Typ – 4% 4625 Typ + 4% mV Same as
VTR_4P6_F + 25 mV
Typ – 4% 4725 Typ + 4% mV Same as
VTR_4P7_F + 25 mV
Typ – 4% 4825 Typ + 4% mV Same as
VTR_4P8_F + 25 mV
Typ – 4% 4925 Typ + 4% mV Same as
VTR_4P9_F + 25 mV
Typ – 4% 5025 Typ + 4% mV Same as
VTR_5P0_F + 25 mV
Typ – 4% 5125 Typ + 4% mV Same as
VTR_5P1_F + 25 mV
LVD 5.2 V rising detection
point for VDDD
LVD 5.3 V rising detection
point for VDDD
Power ramp rate: VDDD
(Active)
Power ramp rate: VDDD
(DeepSleep)
Typ – 4% 5225 Typ + 4% mV Same as
VTR_5P2_F + 25 mV
Typ – 4% 5325 Typ + 4% mV Same as
VTR_5P3_F + 25 mV
–
–
–
–
–
–
100
10
1
mV/µs
mV/µs
Active mode delay between
VDDD falling/rising through
LVD rising/falling point and an
internal LVD signal
µs Guaranteed by
design
transitioning
Datasheet
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4F single
Electrical specifications
Table 26-16 System resources (continued)
Details/
Spec ID
Parameter
Description
Min
Typ
Max
Units
Conditions
SID575A tDLY_DS_LVD
DeepSleep mode delay
between VDDD falling/rising
through LVD rising/falling
point and an internal LVD
signal rising
–
–
4
µs Guaranteed by
design
SID576 tRES_LVD
Response time of LVD, VDDD
supply. LVD guaranteed to
generate pulse for VDDD pulse
width greater than this. (For
falling-then-rising supply at
max ramp rate; pulse width is
time below LVD falling point)
100
–
–
ns
Guaranteed by
design
High-voltage OVD (HV OVD) specifications
SID580 VTR_5P0_R
SID581 VTR_5P0_F
SID582 VTR_5P5_R
HV OVD 5.0-V rising detection
point for VDDD and VDDA
HV OVD 5.0-V falling detection 5.025
point for VDDD and VDDA
HV OVD 5.5-V rising detection
point for VDDD and VDDA
(default)
5.049 5.205 5.361
V
V
V
5.18
5.72
5.335
5.892
5.548
SID583 VTR_5P5_F
HV OVD 5.5-V falling detection 5.524 5.695 5.866
V
point for VDDD and VDDA
(default)
SID585 HVOVD_RR_A
Power ramp rate: VDDD and
VDDA (Active)
–
–
–
–
–
–
100
10
1
mV/µs
mV/µs
SID586 HVOVD_RR_DS Power ramp rate: VDDD and
VDDA (DeepSleep)
SID587 tDLY_ACT_HVOVD Active mode delay between
VDDD falling/rising through
µs Guaranteed by
design
VTR_5P0_F/R or VTR_5P5_F/R and
an internal HV OVD signal
transitioning
SID587A tDLY_ACT_H-
Active mode delay between
VDDA falling/rising through
VTR_5P0_F/R or VTR_5P5_F/R and
an internal HV OVD signal
transitioning
–
–
–
–
1.5
4
µs Guaranteed by
design
VOVD_A
SID587 tDLY_DS_HVOVD
B
DeepSleep mode delay
between VDDD/VDDA
µs Guaranteed by
design
falling/rising through
VTR_5P0_F/R or VTR_5P5_F/R and
an internal HV OVD signal
transitioning
SID588 tRES_HVOVD
Response time of HV OVD. (For
rising-then-falling supply at
max ramp rate; threshold is
VTR_5P0_R or VTR_5P5_R.)
100
–
–
ns
V
Guaranteed by
design
Low-voltage OVD (LV OVD) specifications
SID590 VTR_R_LVOVD
LV OVD rising detection point
for VCCD
1.261
1.3
1.339
Datasheet
124
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4F single
Electrical specifications
Table 26-16 System resources (continued)
Details/
Spec ID
Parameter
Description
Min
Typ
Max
Units
Conditions
SID591 VTR_F_LVOVD
LV OVD falling detection point 1.237 1.275 1.313
for VCCD
V
SID595 tDLY_ACT_LVOVD Active mode delay between
VCCD falling/rising through
–
–
–
–
1
µs Guaranteed by
design
VTR_F/R_LVOVD and an internal
LV OVD signal transitioning
SID595A tDLY_DS_LVOVD
DeepSleep mode delay
between VCCD falling/rising
through VTR_F/R_LVOVD and an
internal LV OVD signal transi-
tioning
12
µs Guaranteed by
design
SID596 tRES_LVOVD
Response time of LV OVD. (For
rising-then-falling supply at
max ramp rate; threshold is
VTR_R_LVOVD.)
100
–
–
ns
Guaranteed by
design
Overcurrent detection (OCD) specifications
SID598 IOCD
OCD range for VCCD
156
18
–
–
315
72
mA Guaranteed by
design
mA Guaranteed by
design
SID599 IOCD_DPSLP
OCD range in DeepSleep mode
VDDD
CPU and
CPU and
Peripherals
Regulators
I/O
Peripherals
Regulators
I/O
6.0 V
Reset
By HV OVD
High-Z
HV OVD rising trip
(Default: 5.548 V to
5.892 V)
Norm al
Operation
Norm al
Operation
Enable
Reset
By
XRES_L
Disable
High-Z
HV BOD rising trip
(Default: 2.474 V to
2.627 V)
Reset
By HV BOD
POR rising trip
(1.5 V to 2.35 V)
Reset
High-Z
By POR
CM OS threshold
(0.7 V)
Disable
OFF
OFF
-0.3 V
VDDD
XRES_L
LOW Level
HIGH Level
Figure 26-14 Device operations supply range
Datasheet
125
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4F single
Electrical specifications
2.3 V
VDDD
tDLY_POR
Internal reset by POR
VDDD
tPOFF
1.45 V
Figure 26-15 POR specifications
Datasheet
126
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4F single
Electrical specifications
VDDD, VDDA
VTR_2P7_R or VTR_3P0_R
VTR_2P7_F or VTR_3P0_F
Internal HV BOD signal
tDLY_ACT/DS_HVBOD
tDLY_ACT/DS_HVBOD
VDDD, VDDA
tRES_HVBOD
VTR_2P7_F or VTR_3P0_F
Figure 26-16 High-voltage BOD specifications
VCCD
VTR_R_LVBOD
VTR_F_LVBOD
Internal LV BOD signal
tDLY_ACT/DS_LVBOD
tDLY_ACT/DS_LVBOD
VCCD
tRES_LVBOD
VTR_F_LVBOD
Figure 26-17 Low-voltage BOD specifications
Datasheet
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4F single
Electrical specifications
VTR_5P0_R or VTR_5P5_R
VTR_5P0_F or VTR_5P5_F
VDDD/VDDA
Internal HV OVD signal
tDLY_ACT/DS_HVOVD
tDLY_ACT/DS_HVOVD
VTR_5P0_R or VTR_5P5_R
tRES_HVOVD
VDDD/VDDA
Figure 26-18 High-voltage OVD specifications
VTR_R_LVOVD
VTR_F_LVOVD
VCCD
Internal LV OVD signal
tDLY_ACT/DS_LVOVD
tDLY_ACT/DS_LVOVD
VTR_R_LVOVD
tRES_LVOVD
VCCD
Figure 26-19 Low-voltage OVD specifications
Datasheet
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4F single
Electrical specifications
VDDD
LVD rising detection point
LVD falling detection point
Internal LVD signal
tDLY_ACT/DS_LVD
tDLY_ACT/DS_LVD
VDDD
tRES_LVD
LVD falling detection point
Figure 26-20 LVD specifications
26.11
Debug
All specifications are valid for –40 °C TA 125 °C and for 2.7 V to 5.5 V except where noted.
26.11.1
SWD
Table 26-17 SWD interface specifications [Conditions: drive_sel<1:0>= 00]
Spec ID
SID300
SID301
SID302
SID303
SID304
Parameter
fSWDCLK
tSWDI_SETUP
tSWDI_HOLD
tSWDO_VALID
tSWDO_HOLD
Description
SWD clock input frequency
SWDI setup time
SWDI hold time
SWDO valid time
Min
Typ
–
–
–
–
Max Units Details/Conditions
–
0.25 × T
0.25 × T
–
10
MHz 2.7 V ≤ VDDD ≤ 5.5 V
ns T = 1 / fSWDCLK
ns T = 1 / fSWDCLK
ns T = 1 / fSWDCLK
ns T = 1 / fSWDCLK
–
–
0.5 × T
–
SWDO hold time
1
–
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4F single
Electrical specifications
26.11.2
JTAG
Table 26-18 JTAG AC specifications [Conditions: drive_sel<1:0>= 00]
Spec ID
SID620
SID621
SID622
SID623
SID624
SID625
SID626
SID627
Parameter
tJCKH
tJCKL
tJCP
tJSU
tJH
tJZX
tJXZ
tJCO
Description
TCK HIGH time
TCK LOW time
Min
30
30
66.7
12
12
–
Typ
–
–
–
–
–
–
–
–
Max Units
–
–
Details/Conditions
ns 30-pF load
ns 30-pF load
TCK clock period
–
–
–
30
30
30
ns 30-pF load
ns 30-pF load
ns 30-pF load
ns 30-pF load
ns 30-pF load
ns 30-pF load
TDI/TMS setup time
TDI/TMS hold time
TDO High-Z to active
TDO active to High-Z
TDO clock to output
–
–
tJCKH
tJCKL
tJCP
TCK
tJH
tJSU
TDI/TMS
tJCO
tJXZ
tJZX
TDO
Figure 26-21 JTAG timing diagram
26.11.3
Trace
Table 26-19 Trace specifications [Conditions: drive_sel<1:0>= 00]
Spec ID
SID1412A CTRACE
SID1412 tTRACE_CYC
Parameter
Description
Trace capacitive load
Trace clock period
Min
–
40
Typ
–
–
Max Units Details/Conditions
30
–
pF
ns Trace clock cycle time
for 25 MHz
SID1413 tTRACE_CLKL
SID1414 tTRACE_CLKH
Trace clock LOW pulse
width
Trace clock HIGH pulse
width
2
2
–
–
–
–
ns Clock low pulse width
ns Clock high pulse width
SID1415A tTRACE_SETUP
SID1416A tTRACE_HOLD
Trace data setup time
Trace data hold time
3
2
–
–
–
–
ns Trace data setup time
ns Trace data hold time
Datasheet
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4F single
Electrical specifications
26.12
Clock specifications
All specifications are valid for –40 °C TA 125 °C and for 2.7 V to 5.5 V except where noted.
The following is a basic requirement on the clock frequency dependency of the cores: Cortex-M0+ core should
run at an integer divider from the Cortex-M4 core clock.
Example combinations are listed in the Table 26-20.
Table 26-20 Clock requirements
Core Cortex-M4 Clock (MHz)
Core Cortex-CM0+ Clock (MHz)
160
120
100
80
80
60
100
80
Table 26-21 Root and intermediate clocks[56]
Max Frequency
Clock
Description
(MHz)
CLK_HF0
CLK_HF1
160
100
Root clock for CPUSS, PERI
Event generator (CLK_REF), Clock output on EXT_CLK pins (when used as
output)
CLK_HF2
2
CSV
CLK_FAST
160
Generated by dividing CLK_HF0, intermediate clock for CM4
Generated by clock gating CLK_PERI, intermediate clock for CM0+, Crypto,
P-DMA, M-DMA
Generated by clock gating CLK_HF0, intermediate clock for LIN, SCB, PASS, CAN,
TCPWM, IOSS, CPU trace
CLK_SLOW
CLK_PERI
100
100
Table 26-22 IMO AC specifications
Spec ID
SID310 fIMOTOL
SID311 tSTARTIMO
Parameter
Description
IMO operating frequency
IMO startup time
Min
7.92
–
Typ
8
–
Max Units Details/Conditions
8.08
7.5
MHz
µs Startup time to 90% of
final frequency
SID312 IIMO_ACT
IMO current
–
13.5
22
µA Guaranteed by design
Table 26-23 ILO AC specifications
Spec ID
SID320 fILOTRIM
SID321 tSTARTILO
Parameter
Description
ILO operating frequency
ILO startup time
Min
Typ
Max Units Details/Conditions
31.1296 32.768 34.4064 kHz
–
8
12
µs Startup time to 90%
of final frequency
SID323 IILO
ILO current
–
500
2800
nA Guaranteed by design
Note
56.Intermediate clocks that are not listed have the same limitations as that of their parent clock.
Datasheet
131
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4F single
Electrical specifications
Table 26-24 ECO specifications
Spec ID
SID330 fECO
SID332 RFDBK
Parameter
Description
Crystal frequency range
Feedback resistor value.
Min: RTRIM = 3; Max: RTRIM =
0 with 100-kΩ step size on
RTRIM
Min
3.988
100
Typ
–
–
Max Units Details/Conditions
33.34 MHz
400
kΩ Guaranteed by design
SID333 IECO3
ECO current at TJ = 150 °C
–
–
2000
µA Maximum operation
current with a 33-MHz
crystal, max 18-pF
load
SID334 tSTART_4M
4-MHz ECO startup time[57]
33-MHz ECO startup time[57]
–
–
–
–
10
1
ms
Time from set CLK_ECO_-
CONFIG.ECO_EN to 1 until
CLK_ECO_STATUS.ECO_READ
Y is set to 1 (See Clock Timing
Diagrams)
Time from set CLK_ECO_-
SID335 tSTART_33M
ms
CONFIG.ECO_EN to 1 until
CLK_ECO_STATUS.ECO_READ
Y is set to 1 (See Clock Timing
Diagrams)
VDDD
MCU
ITrim
Rf
RTrim
ECO_IN: External crystal oscillator input pin
ECO_OUT: External crystal oscillator output pin
C1, C2: Load Capacitors
ECO_IN
VSSD
C3*, C4*: Stray Capacitance of the PCB
C1
C3*
C4*
GTrim
VSSD
C2
ECO_OUT
Rd
0R
Rd
FTrim
Figure 26-22 ECO connection scheme[58]
Table 26-25 PLL specifications
Spec ID
SID340
SID341
Parameter
PLL_LOCK
Description
Time to achieve PLL lock
Output frequency from PLL
block
Min
–
11
Typ
–
–
Max Units
Details/Conditions
35
µs
f
160
MHz
PLL_OUT
SID342
PLL_LJIT1
Long term jitter
–0.25
–
0.25
ns For 125 ns
f
f
f
f
: 320 MHz
PLL_VCO
PLL_OUT
PLL_PFD
: 40 MHz to 160 MHz
: 8 MHz
: ECO
PLL_IN
SID343
PLL_LJIT2
Long term jitter
–0.5
–
0.5
ns For 500 ns
f
f
f
f
: 320 MHz
PLL_VCO
PLL_OUT
PLL_PFD
: 40 MHz to 160 MHz
: 8 MHz
: ECO
PLL_IN
Notes
57.Mainly depends on the external crystal.
58.Please refer to the family-specific Architecture TRM for more information on crystal requirements (002-19314, TRAVEO™ T2G
Automotive MCU body controller entry architecture technical reference manual).
Datasheet
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4F single
Electrical specifications
Table 26-25 PLL specifications (continued)
Spec ID
SID344
Parameter
PLL_LJIT3
Description
Long term jitter
Min
–0.5
Typ
–
Max Units
Details/Conditions
0.5
ns For 1000 ns
f
f
f
f
: 320 MHz
PLL_VCO
PLL_OUT
PLL_PFD
: 40 MHz to 160 MHz
: 8 MHz
: ECO
PLL_IN
SID345A PLL_LJIT5
Long term jitter
–0.75
–
0.75
ns For 10000 ns
f
f
f
f
: 320 MHz
PLL_VCO
PLL_OUT
PLL_PFD
: 40 MHz to 160 MHz
: 8 MHz
: ECO
PLL_IN
SID346
SID347
f
PLL input frequency
PLL operating current
3.988
–
–
740
33.34 MHz
PLL_IN
I
I
I
I
I
I
I
I
I
1110
1125
1125
780
µA
µA
µA
µA
µA
µA
µA
µA
µA
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
= 4 MHz,
PLL_160M1
IN
(f
= 160 MHz)
= 4 MHz,
OUT
PFD
VCO
OUT
= 320 MHz,
= 160 MHz
SID347A
SID347B
SID339
PLL operating current
(f = 160 MHz)
–
–
–
–
–
–
–
–
750
750
520
530
530
520
530
530
= 8 MHz,
PLL_160M2
PLL_160M3
PLL_100M1
PLL_100M2
PLL_100M3
PLL_80M1
PLL_80M2
PLL_80M3
IN
= 8 MHz,
OUT
PFD
VCO
OUT
= 320 MHz,
= 160 MHz
PLL operating current
(f = 160 MHz)
= 16 MHz,
IN
= 8 MHz,
OUT
PFD
VCO
OUT
= 320 MHz,
= 160 MHz
PLL operating current
(f = 100 MHz)
= 4 MHz,
IN
= 4 MHz,
OUT
PFD
VCO
OUT
= 200 MHz,
= 100 MHz
SID339A
SID339B
SID348
PLL operating current
(f = 100 MHz)
795
= 8 MHz,
IN
= 8 MHz,
OUT
PFD
VCO
OUT
= 200 MHz,
= 100 MHz
PLL operating current
(f = 100 MHz)
795
= 16 MHz,
IN
= 8 MHz,
OUT
PFD
VCO
OUT
= 200 MHz,
= 100 MHz
PLL operating current
(f = 80 MHz)
780
= 4 MHz,
IN
= 4 MHz,
OUT
PFD
VCO
OUT
= 240 MHz,
= 80 MHz
SID348A
SID348B
PLL operating current
(f = 80 MHz)
795
= 8 MHz,
IN
= 8 MHz,
OUT
PFD
VCO
OUT
= 240 MHz,
= 80 MHz
PLL operating current
(f = 80 MHz)
795
f
f
f
f
= 16 MHz,
IN
= 8 MHz,
OUT
PFD
VCO
OUT
= 240 MHz,
= 80 MHz
SID348C
SID349C
f
f
VCO frequency
PFD frequency
170
3.988
–
–
400
8
MHz
MHz
PLL_VCO
PLL_PFD
Datasheet
133
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4F single
Electrical specifications
Table 26-26 FLL specifications
Spec ID Parameter
Description
Min
Typ
Max Units
Details/Conditions
SID350 tFLL_WAKE
FLL wake up time
–
–
5
µs Wakeup with < 10 °C
temperature change
while in DeepSleep.
fFLL_IN = 8 MHz,
fFLL_OUT = 100 MHz, Time
from stable reference
clockuntilFLLfrequency
is within 5% of final value
SID351 fFLL_OUT
SID352 FLL_CJIT
Output frequency from FLL
block
FLL frequency accuracy
24
–1
–
–
100
1
MHz Output range of FLL
divided-by-2 output
%
This is added to the error
of the source
SID353 fFLL_IN
SID354 IFLL
Input frequency
FLL operating current
0.25
–
–
250
80
360
MHz
µA Reference clock: IMO,
CCO frequency: 200 MHz,
FLL frequency: 100 MHz,
guaranteed by design
VDDD
MCU
Rf
WCO_IN: Watch crystal oscillator input pin
WCO_OUT: Watch crystal oscillator output pin
C1, C2: Load Capacitors
WCO_IN
C3*, C4*: Stray Capacitance of the PCB
C1
C2
C3*
VSSD
VSSD
C4*
WCO_OUT
Rd
0R
Figure 26-23 WCO connection scheme[59]
Table 26-27 WCO specifications
Spec ID
Parameter
Description
Min
Typ
Max Units Details/Conditions
SID360 fWCO
Watch Crystal frequency
–
32.768
–
kHz Maximum drive level:
0.5 µW
SID361 WCO_DC
SID362 tSTART_WCO
WCO duty cycle
WCO start-up time[60]
10
–
–
–
90
1000
%
ms
For Grade-S devices
Time from set CTL.WCO_EN to
1 until STATUS.WCO_OK is set
to 1. (See Clock Timing
Diagrams)
WCO start-up time[60]
WCO current
–
–
–
1400
–
ms
For Grade-E devices
SID362E tSTART_WCOE
Time from set CTL.WCO_EN to
1 until STATUS.WCO_OK is set
to 1. (See Clock Timing
Diagrams)
SID363 IWCO
1.4
µA
Notes
59.Please refer to family-specific Architecture TRM for more information on crystal requirements (002-19314, TRAVEO™ T2G Automotive
MCU body controller entry architecture technical reference manual).
60.Mainly depends on the external crystal.
Datasheet
134
002-18043 Rev. *J
2022-09-08
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4F single
Electrical specifications
Table 26-28 External clock input specifications
Spec ID Parameter
Description
Min
Typ
Max Units Details/Conditions
SID366 fEXT
External clock input
frequency
0.25
–
80
MHz For EXT_CLK pin (all
input level settings:
CMOS, TTL,
Automotive)
SID367 EXT_DC
External clock duty cycle
45
–
55
%
26.12.1
Clock timing diagrams
ECO: 4 MHz
PLL: 160 MHz
FLL: 100 MHz
Active
CLK_ECO_CONFIG.ECO_EN
ECO_OUT
4 MHz
CLK_ECO_STATUS.ECO_READY
10 ms
CLK_PLL_CONFIG.ENABLE
CLK_PLL_STATUS.LOCKED
160 MHz
35 µs
PLL_OUTPUT
CLK_FLL_CONFIG.FLL_ENABLE
CCO is already up-and-running
CLK_FLL_STATUS.LOCKED
5 µs
100 MHz
FLL_OUTPUT
Figure 26-24 ECO to PLL or FLL diagram
Datasheet
135
002-18043 Rev. *J
2022-09-08
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4F single
Electrical specifications
WCO: 32.768 kHz
FLL: 100 MHz
Active
CTL.WCO_EN
WCO_OUT
32.768 kHz
STATUS.WCO_OK
1000 ms
CLK_FLL_CONFIG.FLL_ENABLE
CLK_FLL_STATUS.LOCKED
CCO is already up-and-running
5 µs
100 MHz
FLL_OUTPUT
Figure 26-25 WCO to FLL Diagram
Table 26-29 MCWDT timeout specifications
Spec ID
Parameter
Description
Min
Typ
Max
Units
Details/Conditions
SID410
t
Minimum MCWDT timeout
58.12
–
–
µs
When using the ILO
MCWDT1
(32.768 kHz + 5%) and
16-bit MCWDT counter
Guaranteed by design
SID411
t
Maximum MCWDT timeout
–
–
2.11
s
When using the ILO
MCWDT2
(32.768 kHz – 5%) and
16-bit MCWDT counter
Guaranteed by design
Table 26-30 WDT timeout specifications
Spec ID
Parameter
Description
Min
Typ
Max Units
Details/Conditions
SID412
t
t
t
Minimum WDT timeout
58.12
–
–
38.33
–
µs
When using the ILO
(32.768 kHz + 5%) and
32-bit WDT counter
Guaranteed by design
When using the ILO
(32.768 kHz – 5%) and
32-bit WDT counter
Guaranteed by design
WDT1
SID413
SID414
Maximum WDT timeout
Default WDT timeout
–
–
–
h
WDT2
WDT3
1000
ms When using the ILO and
32-bit WDT counter at
0x8000 (default value),
guaranteed by design
Datasheet
136
002-18043 Rev. *J
2022-09-08
27
Ordering information
The CYT2B7 microcontroller part numbers and features are listed in Table 27-1. The Arm® TAP JTAG ID is 0x6BA0 0477.
Table 27-1
CYT2B7 ordering information
Code-flash
(KB)
Work-flash
(KB)
ADC
SCB
LIN
CANFD
Temperature
Grade
[61]
Device Code
Ordering Code
Package
RAM (KB)
eSHE/HSM
JTAG ID CODE
Channels
Channels
Channels
Channels
[62]
[63]
[64]
96
[65]
S
[67]
CYT2B73BAS
CYT2B73BAE
CYT2B73BADQ0AZSGS
CYT2B73BADQ0AZEGS
CYT2B73CADQ0AZSGS
CYT2B73CADQ0AZEGS
CYT2B74BADQ0AZSGS
CYT2B74BADQ0AZEGS
CYT2B74CADQ0AZSGS
CYT2B74CADQ0AZEGS
CYT2B75BADQ0AZSGS
CYT2B75BADQ0AZEGS
CYT2B75CADQ0AZSGS
CYT2B75CADQ0AZEGS
CYT2B77BADQ0AZSGS
CYT2B77BADQ0AZEGS
CYT2B77CADQ0AZSGS
CYT2B77CADQ0AZEGS
CYT2B78BADQ0AZSGS
CYT2B78BADQ0AZEGS
CYT2B78CADQ0AZSGS
CYT2B78CADQ0AZEGS
64-LQFP
64-LQFP
64-LQFP
64-LQFP
80-LQFP
80-LQFP
80-LQFP
80-LQFP
100-LQFP
100-LQFP
100-LQFP
100-LQFP
144-LQFP
144-LQFP
144-LQFP
144-LQFP
176-LQFP
176-LQFP
176-LQFP
176-LQFP
1088
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
27
27
27
27
34
34
34
34
39
39
39
39
54
54
54
54
64
64
64
64
5
5
5
5
6
6
6
6
8
8
8
8
8
8
8
8
8
8
8
8
6
6
6
6
7
7
7
7
7
7
7
7
8
8
8
8
8
8
8
8
5
5
5
5
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
eSHE
eSHE
HSM
HSM
eSHE
eSHE
HSM
HSM
eSHE
eSHE
HSM
HSM
eSHE
eSHE
HSM
HSM
eSHE
eSHE
HSM
HSM
0x2E3C9069
[62]
[66]
1088
1088
1088
1088
1088
1088
1088
1088
1088
1088
1088
1088
1088
1088
1088
1088
1088
1088
1088
96
96
96
96
96
96
96
96
96
96
96
96
96
96
96
96
96
96
96
E
0x2E3C9069
0x2E3CA069
0x2E3CA069
0x2E3D1069
0x2E3D1069
0x2E3D2069
0x2E3D2069
0x2E3D9069
0x2E3D9069
0x2E3DA069
0x2E3DA069
0x2E3E1069
0x2E3E1069
0x2E3E2069
0x2E3E2069
0x2E3E9069
0x2E3E9069
0x2E3EA069
0x2E3EA069
CYT2B73CAS
CYT2B73CAE
S
E
S
E
S
E
S
E
S
E
S
E
S
E
S
E
S
E
[62]
CYT2B74BAS
CYT2B74BAE
[62]
CYT2B74CAS
CYT2B74CAE
[62]
CYT2B75BAS
CYT2B75BAE
[62]
CYT2B75CAS
CYT2B75CAE
[62]
CYT2B77BAS
CYT2B77BAE
[62]
CYT2B77CAS
CYT2B77CAE
[62]
CYT2B78BAS
CYT2B78BAE
[62]
CYT2B78CAS
CYT2B78CAE
Notes
61.Supported shipment types are “Tray” (default) and “Tape and Reel”. Add the character ‘T’ at the end to get the ordering code for “Tape and Reel” shipment type.
62.3DES/SHA-1/SHA-2/SHA-3/CRC/Vector unit for asymmetric cryptography features are not supported.
63.Code-flash size 1088 KB = 32 KB × 30 (Large Sectors) + 8 KB × 16 (Small Sectors)
64.Work-flash size 96 KB = 2 KB × 36 (Large Sectors) + 128 B × 192 (Small Sectors).
65.S-grade Temperature (–40 °C to 105 °C).
66.E-grade Temperature (–40 °C to 125 °C).
67.JTAG ID CODE bits 12 through 27, represents the Silicon ID of the device.
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4F single
Ordering information
27.1
Part number nomenclature
Table 27-2
Device code nomenclature
Field Description
Value
Meaning
CY
T
2
B
D
Cypress Prefix
Category
Family Name
Application
CY
T
2
B
7
TRAVEO™
TRAVEO™ T2G (Core M4)
Body
1088 KB / 96 KB / 128 KB
64-LQFP
Code-flash/Work-flash/SRAM quantity
3
4
80-LQFP
P
Packages
5
100-LQFP
7
144-LQFP
8
176-LQFP
B
C
A
S
E
eSHE – on, HSM – off, RSA - 2K
eSHE – on, HSM – on, RSA - 2K
No options
S-grade (–40 °C to 105 °C)
E-grade (–40 °C to 125 °C)
H
I
Hardware Option
Marketing Option
Temperature Grade
C
Table 27-3
Ordering code nomenclature
Field Description
Value
Meaning
CY
T
Cypress Prefix
Category
CY
T
TRAVEO™
2
B
Family Name
Application
2
B
TRAVEO™ T2G (Core M4)
Body
D
Code-flash/Work-flash/SRAM quantity
7
3
1088 KB / 96 KB / 128 KB
64 LQFP
4
80 LQFP
P
Packages
5
100 LQFP
7
144 LQFP
8
176 LQFP
B
C
A
eSHE – on, HSM – off, RSA - 2K
eSHE – on, HSM – on, RSA - 2K
No options
H
I
Hardware Option
Marketing Option
A
First revision
B
C
Second revision
Third revision
R
Revision
D
Q
0
Fourth revision
UMC (Fab 12i) Singapore
Reserved
F
X
K
Fab Location
Reserved
Package Code
AZ
S
E
ES
GS
Blank
T
LQFP
S-grade (–40 °C to 105 °C)
E-grade (–40 °C to 125 °C)
Engineering samples
Standard grade of automotive
Tray shipment
C
Q
S
Temperature Grade
Quality Grade
Shipment Type
Tape and Reel shipment
Datasheet
138
002-18043 Rev. *J
2022-09-08
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4F single
Packaging
28
Packaging
CYT2B7 is offered in the packages listed in the Table 28-1.
Table 28-1
Package Information
Package
176-LQFP
144-LQFP
100-LQFP
80-LQFP
64-LQFP
Dimensions
Contact/Lead pitch
0.5 mm
Coefficient of thermal expansion
I/O Pins
152
122
78
[70]
[71]
24 × 24 × 1.7 mm (max)
20 × 20 × 1.7 mm (max)
14 × 14 × 1.7 mm (max)
12 × 12 × 1.7 mm (max)
10 × 10 × 1.7 mm (max)
a1 = 8.5 ppm/°C, a2 = 33.8 ppm/°C
[70]
[71]
0.5 mm
a1 = 8.5 ppm/°C, a2 = 33.7 ppm/°C
[70]
[71]
0.5 mm
a1 = 8.5 ppm/°C, a2 = 33.6 ppm/°C
[70]
[71]
0.5 mm
a1 = 8.5 ppm/°C, a2 = 33.5 ppm/°C
63
[70]
[71]
0.5 mm
a1 = 8.5 ppm/°C, a2 = 33.2 ppm/°C
49
Table 28-2
Package Characteristics
Description
Parameter
Conditions
Min
Typ
Max
Units
TA
Operating ambient
temperature
S-grade
–40
–
105
°C
TA
TJ
Operating ambient
temperature
E-grade
–
–40
–
–
–
125
150
°C
°C
Operating junction
temperature
64 LQFP
80 LQFP
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
37.6
32.7
29.8
26.2
25.9
32.0
26.7
21.3
20.9
20.8
7.8
°C/Watt
°C/Watt
°C/Watt
°C/Watt
°C/Watt
°C/Watt
°C/Watt
°C/Watt
°C/Watt
°C/Watt
°C/Watt
°C/Watt
°C/Watt
°C/Watt
°C/Watt
Package thermal resistance,
[68,
RθJA
RθJB
RθJC
junction to ambient θJA
100 LQFP
144 LQFP
176 LQFP
64 LQFP
69]
80 LQFP
Package θJB
100 LQFP
144 LQFP
176 LQFP
64 LQFP
80 LQFP
6.6
Package thermal resistance,
100 LQFP
144 LQFP
176 LQFP
5.6
junction to case θJC
4.2
3.8
Notes
68.Board condition complies to JESD51-7(4 Layers)
69.Maximum value °C/Watt shown is for TA = 125 °C.
70.a1 = CTE (Coefficient of Thermal Expansion) value below Tg (ppm/°C) (Tg is glass transition temperature which is 131 °C).
71.a2 = CTE value above Tg (ppm/°C).
Datasheet
139
002-18043 Rev. *J
2022-09-08
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4F single
Packaging
Table 28-3
Package
Solder Reflow Peak Temperature, Package Moisture Sensitivity Level (MSL), IPC/JEDEC
J-STD-2
Maximum Peak Temperature
Maximum Time at Peak Temperature
(seconds)
MSL
(°C)
260
260
260
260
260
176 LQFP
144 LQFP
100 LQFP
80 LQFP
64 LQFP
30 seconds
30 seconds
30 seconds
30 seconds
30 seconds
3
3
3
3
3
Datasheet
140
002-18043 Rev. *J
2022-09-08
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4F single
Packaging
4
D
5
7
D1
132
89
89
132
133
133
88
88
E1
E
5
4
7
3
6
176
45
45
176
1
44
44
1
e
2
5 7
3
0.10
A-B
C
A-B
D
BOTTOM VIEW
0.20
C A-B D
b
0.08
C
D
8
TOP VIEW
2
A
c
9
θ
A
SEATING
PLANE
A1
0.25
A'
b
L1
10
0.08
C
SECTION A-A'
L
SIDE VIEW
DIMENSIONS
SYMBOL
MIN. NOM. MAX.
1.70
A
A1
b
0.05
0.17 0.22 0.27
0.09 0.20
0.15
c
D
26.00 BSC
24.00 BSC
0.50 BSC
D1
e
E
26.00 BSC
24.00 BSC
E1
L
0.45 0.60 0.75
1.00 REF
L1
θ
0°
8°
002-15150 *A
Figure 28-1
176-LQFP package outline
Datasheet
141
002-18043 Rev. *J
2022-09-08
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4F single
Packaging
4
4
5
D
D
5
7
7
D1
D1
108
73
73
108
109
109
72
72
E1
E
E
E1
5
7
5
7
4
4
3
3
6
C
144
144
37
37
1
36
36
1
2
5
D
7
BOTTOM VIEW
e
3
0.10
C A-B
0.20
A-B D
b
0.08
C
A-B
D
8
TOP VIEW
2
A
9
c
A
A1
SEATING
PLANE
0.25
b
L1
10
A'
SECTION A-A'
L
0.08
C
SIDE VIEW
DIMENSIONS
MIN. NOM. MAX.
1.70
SYMBOL
A
A1
b
0.05
0.17 0.22 0.27
0.09 0.20
0.15
c
D
22.00 BSC
20.00 BSC
0.50 BSC
D1
e
E
22.00 BSC
20.00 BSC
E1
L
0.45 0.60 0.75
1.00 REF
L1
002-13015 *B
Figure 28-2
144-LQFP package outline
Datasheet
142
002-18043 Rev. *J
2022-09-08
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4F single
Packaging
4
4
5
D
D
5
7
7
D1
D1
75
51
51
75
76
50
50
76
E1
E1
E
E
5
5
4
4
7
7
3
6
100
26
26
100
1
1
25
25
2
5
7
e
0.10
C
A-B
D
3
BOTTOM VIEW
0.20
C A-B D
b
8
0.08
C
A-B
D
TOP VIEW
2
A
9
A
SEATING
PLANE
c
0.25
A1
A'
b
0.08
C
L1
10
SECTION A-A'
L
SIDE VIEW
DETAIL A
NOTES :
1. ALL DIMENSIONS ARE IN MILLIMETERS.
2. DATUM PLANE H IS LOCATED AT THE BOTTOM OF THE MOLD PARTING
LINE COINCIDENT WITH WHERE THE LEAD EXITS THE BODY.
3. DATUMS A-B AND D TO BE DETERMINED AT DATUM PLANE H.
DIMENSIONS
SYMBOL
MIN. NOM. MAX.
1.70
A
A1
b
0.05
0.15
0.09
0.15
0.27
0.20
4. TO BE DETERMINED AT SEATING PLANE C.
5. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD PROTRUSION.
ALLOWABLE PROTRUSION IS 0.25mm PRE SIDE.
DIMENSIONS D1 AND E1 INCLUDE MOLD MISMATCH AND ARE DETERMINED
AT DATUM PLANE H.
6. DETAILS OF PIN 1 IDENTIFIER ARE OPTIONAL BUT MUST BE LOCATED
WITHIN THE ZONE INDICATED.
c
D
16.00 BSC
14.00 BSC
0.50 BSC
D1
e
E
16.00 BSC
14.00 BSC
7. REGARDLESS OF THE RELATIVE SIZE OF THE UPPER AND LOWER BODY
SECTIONS. DIMENSIONS D1 AND E1 ARE DETERMINED AT THE LARGEST
FEATURE OF THE BODY EXCLUSIVE OF MOLD FLASH AND GATE BURRS.
BUT INCLUDING ANY MISMATCH BETWEEN THE UPPER AND LOWER
SECTIONS OF THE MOLDER BODY.
8. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION. THE DAMBAR
PROTRUSION (S) SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED b
MAXIMUM BY MORE THAN 0.08mm. DAMBAR CANNOT BE LOCATED ON
THE LOWER RADIUS OR THE LEAD FOOT.
E1
L
0.45 0.60 0.75
1.00 REF
L1
9. THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD
BETWEEN 0.10mm AND 0.25mm FROM THE LEAD TIP.
10. A1 IS DEFINED AS THE DISTANCE FROM THE SEATING PLANE TO
THE LOWEST POINT OF THE PACKAGE BODY.
002-11500 *B
Figure 28-3
100-LQFP package outline
Datasheet
143
002-18043 Rev. *J
2022-09-08
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4F single
Packaging
4
D
D1
5
7
60
41
41
60
61
40
40
61
5
7
E1
E
4
3
6
80
21
21
80
1
20
20
1
2
5
7
D
0.10
C
C
A-B D
BOTTOM VIEW
3
e
0.08
A-B
D
b
0.20
C A-B D
8
TOP VIEW
2
A
A
SEATING
PLANE
9
c
A'
0.25
0.08
C
A1 10
L1
b
L
SIDE VIEW
SECTION A-A'
DIMENSIONS
SYMBOL
MIN. NOM. MAX.
1.70
A
A1
b
0.05
0.15
0.09
0.15
0.27
0.20
c
D
14.00 BSC.
D1
e
12.00 BSC.
0.50 BSC
E
14.00 BSC.
E1
L
12.00 BSC.
0.45 0.60 0.75
1.00 REF
L1
002-11501 *A
Figure 28-4
80-LQFP package outline
Datasheet
144
002-18043 Rev. *J
2022-09-08
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4F single
Packaging
4
D
D1
5
7
48
33
33
48
32
32
49
49
5
7
E1
E
4
3
6
17
17
64
64
1
1
16
16
2
5
7
e
A-B D
3
0.10
0.08
C
A-B
D
BOTTOM VIEW
0.20
C
C
A-B
D
8
b
TOP VIEW
2
A
9
c
A
SEATING
PLANE
b
0.25
A1
A'
SECTION A-A'
0.08
C
L1
10
L
SIDE VIEW
DIMENSIONS
SYMBOL
MIN. NOM. MAX.
1.70
A
A1
b
0.00
0.15
0.09
0.20
0.2
0.20
12.00 BSC.
7
c
D
D1
e
10.00 BSC.
0.50 BSC
E
12.00 BSC.
E1
L
10.00 BSC.
0.45 0.60 0.75
1.00 REF
L1
002-11499 *A
Figure 28-5
64-LQFP package outline
Datasheet
145
002-18043 Rev. *J
2022-09-08
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4F single
Appendix
29
Appendix
29.1
Bootloading or end-of-line programming
• Triggered at device startup, if a trigger condition is applied
• Either CAN or LIN communication may be used
• Bootloader polls for the communication on CAN or LIN at separate time frames, until the overall 300-second
timeout is reached
• If a bootloader command is received on either communication interface, the polling stops and bootloader starts
using this interface
150 ms
10 ms
10 ms
CAN,
100 Kbps
Polling
CAN,
500 Kbps
Polling
LIN,
20 Kbps
Polling
CAN,
100 Kbps
Polling
Bootloader
Stopped
….
Overall bootloading time, if no communication ( 300 s)
Figure 29-1
Table 29-1
Bootloading sequence
CAN interface details
Sl. No.
CAN interface
Configuration
1
2
3
4
5
6
7
8
9
CAN Mode
CAN Instance
CAN TX
CAN RX
CAN Transceiver NSTB / EN (Low)
CAN Transceiver EN / EN (High)
CAN RX Message ID
CAN TX Message ID
Baud
Classic CAN
CAN0, Channel#1
P0.2 / CAN0_1_TX
P0.3 / CAN0_1_RX
P23.3 (optional)
P2.1 (optional)
0x1A1
0x1B1
100 or 500 kbps alternating
VSS
CAN
Transceiver
TRAVEOTM T2G MCU
EN (Low)
NSTB
EN
EN (High)
TX
TX
RX
RX
Figure 29-2
MCU to CAN transceiver connections
Datasheet
146
002-18043 Rev. *J
2022-09-08
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4F single
Appendix
Table 29-2
LIN interface details
LIN interface
Sl. No.
Configuration
LIN0, Channel#1
Slave
1
2
LIN Type
LIN Mode
3
4
5
6
7
8
LIN Checksum Type
LIN TX
LIN RX
LIN EN / EN (High)
LIN EN (Low)
LIN TX PID
Classic
P0.1 / LIN1_TX
P0.0 / LIN1_RX
P2.1 (optional)
P23.3 (optional)
0x46
9
LIN RX PID
0x45
10
11
12
Baud
20 or 115.2 kbps
11
1 bit
Break Field Length
Break Delimiter Length
VDDD / VDDIO
LIN
Transceiver
TRAVEOTM T2G MCU
EN (Low)
EN (High)
EN
TX
RX
TX
RX
Figure 29-3
MCU to LIN transceiver connections
29.2
External IP revisions
Table 29-3
IP revisions
Module
IP
Revision
M_TTCAN IP revision: Rev.3.2.3
Cortex®-M0+-r0p1
Vendor
Bosch
Arm®
Arm®
Arm®
CANFD
mxttcanfd
armcm0p
Arm® Cortex®-M0+
Arm® Cortex®-M4
Arm® Coresight
armcm4
Cortex®-M4-r0p1
armcoresighttk
CoreSight-SoC-TM100-r3p2
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Based on Arm® Cortex®-M4F single
Acronyms
30
Acronyms
Table 30-1
Acronyms used in the Document
Acronym
A/D
Description
Analog to Digital
Acronym
JTAG
Description
Joint test action group
Low drop out regulators
ABS
Absolute
LDO
ADC
Analog to Digital converter
LIN
Local Interconnect Network, a
communications protocol
AES
Advanced encryption standard
LVD
OTA
Low voltage detection
AHB
AMBA (advanced microcontroller bus
architecture) high-performance bus,
Arm® data transfer bus
Over-the-air programming
Arm®
Advanced RISC machine, a CPU archi-
tecture
OTP
One-time programmable
Over voltage detection
ASIL
BOD
Automotive safety integrity level
Brown-out detection
OVD
P-DMA
Peripheral-Direct Memory Access
same as DW
CAN FD
CMOS
Controller Area Network with Flexible
Data rate
PLL
Phase-locked loop
Complementary metal-oxide-semicon-
ductor
POR
Power-on reset
CPU
CRC
Central Processing Unit
PPU
Peripheral protection unit
Cyclic redundancy check, an
error-checking protocol
PRNG
Pseudorandom number generator
CSV
CTI
Clock supervisor
PWM
Pulse-width modulation
Microcontroller Unit
Cross trigger interface
Data encryption standard
Design-For-Test
MCU
DES
DFT
DW
MCWDT
M-DMA
MISO
Multi-counter watchdog timer
Memory-Direct Memory Access
SPI Master-in slave-out
Memory mapped I/O
Datawire same as P-DMA
ECC
Error correcting code/Elliptical curve
cryptography
MMIO
ECO
ETM
External crystal oscillator
Embedded Trace Macrocell
MOSI
MPU
MTB
MUL
MUX
NVIC
RAM
RISC
ROM
RSA
SPI Master-out slave-in
Memory protection unit
Micro trace buffer
EVTGEN Event Generator
FLL
Frequency-locked loop
Multiplier
FPU
GHS
GPIO
HSM
I/O
Floating point unit
Multiplexer
Green Hills tool chain with Multi IDE
General purpose input/output
Hardware security module
Input/output
Nested vectored interrupt controller
Random access memory
Reduced-instruction-set computing
Read only memory
I2C
Inter-Integrated Circuit, a communica-
tions protocol
Rivest-Shamir-Adleman Public Key
Encryption Algorithm
ILO
Internal low-speed oscillator
Internal main oscillator
RTC
SAR
Real-time clock
IMO
Successive approximation register
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Based on Arm® Cortex®-M4F single
Acronyms
Table 30-1
Acronyms used in the Document (continued)
Acronym
IOSS
Description
Input/output sub-system
Inter-processor communication
Infrared interface
Acronym
Description
Serial communication block
I2C serial clock
SCB
IPC
SCL
IrDA
SDA
I2C serial data
IRQ
Interrupt request
SECDED
Single error correction, double error
detection
SHA
SHE
SMPU
SPI
Secure hash algorithm
TCPWM
TTL
Timer/Counter Pulse-width modulator
Transistor-transistor logic
Secure hardware extension
Shared memory protection unit
TRNG
True random number generator
Serial peripheral interface, a communica- UART
tions protocol
Universal Asynchronous Transmitter
Receiver
SRAM
SWD
SWJ
Static random access memory
Serial wire debug
WCO
WDT
Watch crystal oscillator
Watchdog timer reset
Serial wire JTAG
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Based on Arm® Cortex®-M4F single
Errata
31
Errata
This section describes the errata for the CYT2B7 product family. Details include errata trigger conditions, scope of impact, available
workaround, and silicon revision applicability. Contact your local Infineon Sales Representative if you have questions.
Part Numbers Affected
Part Number
All CYT2B7 parts
CYT2B7 Qualification Status
Production samples
Datasheet
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Based on Arm® Cortex®-M4F single
Errata
CYT2B7 Errata Summary
The following table defines the errata applicability to available CYT2B7 family devices.
Errata
ID
Silicon
Rev.
Items
CYT2B7
Fix Status
[1.] Crypto LSL1, LSR1, LSL1_WITH_CARRY, &
LSR1_WITH_CARRY instructions may work
incorrectly in certain scenarios
No silicon fix planned. Use
workaround.
53
42
67
68
69
96
97
No silicon fix planned. Use
workaround.
[2] Crypto MEM_BUF may be corrupted
[3] ConfigureFmInterrupt API assumes a
parameter with 8 bytes boundary, but actual
boundary is 4 bytes
No silicon fix planned. Use
workaround.
[4] SMPU/MPU/PPU protection region size is
No silicon fix planned. Use
workaround.
limited to 2 GB
[5] DirectExecute API may return error if
called with arguments placed in SRAM
memory
No silicon fix planned. Use
workaround.
[6] CAN FD RX FIFO top pointer feature does
No silicon fix planned. Use
workaround.
not function as expected
[7] CAN FD debug message handling state
machine does not reset to Idle state when
CANFD_CH_CCCR.INIT is set
[8] TPIU Peripheral ID mismatch
No silicon fix planned. Use
workaround.
CYT2B73BADQ0AZSGS
CYT2B73BADQ0AZEGS
CYT2B73CADQ0AZSGS
CYT2B73CADQ0AZEGS
CYT2B74BADQ0AZSGS
CYT2B74BADQ0AZEGS
CYT2B74CADQ0AZSGS
CYT2B74CADQ0AZEGS
CYT2B75BADQ0AZSGS
CYT2B75BADQ0AZEGS
CYT2B75CADQ0AZSGS
CYT2B75CADQ0AZEGS
CYT2B77BADQ0AZSGS
CYT2B77BADQ0AZEGS
CYT2B77CADQ0AZSGS
CYT2B77CADQ0AZEGS
CYT2B78BADQ0AZSGS
CYT2B78BADQ0AZEGS
CYT2B78CADQ0AZSGS
CYT2B78CADQ0AZEGS
98
No fix planned
[9] Limitation of the memory hole in SCB
No silicon fix planned. Use
workaround
124
register space
No silicon fix planned. Use
workaround
[10] WDT service can be missed
129
147
[11] CAN FD controller message order
No silicon fix planned. Use
workaround
inversion when transmitting from dedicated
Tx Buffers configured with same Message ID
D
[12] CAN FD incomplete description of
Dedicated Tx Buffers and Tx Queue related
to transmission from multiple buffers
configured with the same Message ID
[13]Misleading status is returned for Flash
and eFuse system calls, if there are pending
NC ECC faults in SRAM controller #0
No silicon fix planned. Use
workaround. TRM was
updated.
167
175
No silicon fix planned. TRM
will be updated.
No silicon fix planned. TRM
will be updated.
[14]WDT reset causes loss of SRAM retention
176
185
No silicon fix planned.
TRM will be updated.
[15]Crypto ECC errors may be set after boot
with application authentication
Will be fixed to update the
Flash
settings,
via
Manufacturing
Test
Program Update for Code
Flash setting; this fix is
transferred to
[16]Incomplete erase of Code Flash cells could
happen Erase Suspend / Erase Resume is
used along with Erase Sector operation in
Non-Blocking mode
198
199
TRAVEO™ T2G devices
during Infineon Factory
Test Flow. Fixed devices
will be identified by
Device Date Code, which
is marked on every
TRAVEO™ T2G device.
No silicon fix planned.
TRM will be updated.
[17]Limitation for keeping the port state from
peripheral IP after wakeup from DeepSleep
Datasheet
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4F single
Errata
1. Crypto LSL1, LSR1, LSL1_WITH_CARRY, & LSR1_WITH_CARRY instructions may work incorrectly in certain scenarios
Problem Definition
LSL1, LSR1, LSL1_WITH_CARRY, & LSR1_WITH_CARRY instructions should ignore the value in IW[3:0] (shift
by 1 instruction does not use these fields). But because of a HW issue, shift does not work if the register data
field, pointed by IW[3:0], is ‘0’ (destination data is same as source data).
Parameters Affected
Trigger Condition(s)
Scope of Impact
Workaround
NA
Using LSL1, LSR1, LSL1_WITH_CARRY, & LSR1_WITH_CARRY instructions
The shift does not happen (destination data is same as source data).
IW[3:0] should be pointed to a dummy register where the data field of the register is non-zero value
(rsrc0->data[12:0]).
Since stack pointer(r15) points to a non-zero value (to use the LSL1 instruction you must have allocated at
least one register, so that SP will not be zero), it is safe to use r15 as rsrc0.
static __forceinline void LSL1 (int rdst, int rsrc1)
{
AHB_WRITE_W (MMIO_CRYPTO_INSTR_FF_WR, (CRYPTO_VU_LSL_OPC << 24)
| (rdst << 12)
| (rsrc1 << 4)
| 15);
}
This software workaround applies to other instructions such as LSR1, LSL1_WITH_CARRY & LSR1_WITH_-
CARRY as well.
Fix Status
No silicon fix planned. Use workaround.
2. Crypto MEM_BUF may be corrupted
Problem Definition
The SRAM in the Crypto block is 8 KB but the address decode is wired to create four 8-KB images of the SRAM
within a 32-KB address space. Writes to memory space above the initial 8-KB image will corrupt SRAM
contents.
Parameters Affected
Trigger Condition(s)
Scope of Impact
Workaround
NA
Any write to address between 0x40108000 and 0x4010FFFF
CRYPTO MEM_BUF may be corrupted
The software should ensure that there is no access beyond 8 KB MEM_BUF address range from either MMIO
writes or address overflows while executing Crypto operations
Fix Status
No silicon fix planned. Use workaround.
3. ConfigureFmInterrupt API assumes a parameter with 8 bytes boundary, but actual boundary is 4 bytes
Problem Definition
STATUS_ADDR_PROTECTED will be returned if the ConfigureFmInterrupt API is called with arguments
stored in SRAM with 4-byte boundary (available SRAM or protected boundary SRAM).
Parameters Affected
Trigger Condition(s)
NA
Call ConfigureFmInterrupt API with arguments stored in SRAM at 4 bytes boundary of available SRAM or
protected boundary of SRAM.
Scope of Impact
Workaround
Fix Status
ConfigureFmInterrupt API will fail by returning STATUS_ADDR_PROTECTED error status when called with
argument having 4 bytes boundary of available SRAM or protected boundary of SRAM.
Allow 4 bytes margin (that is, assume that the API parameter size is 8 and store the arguments) for Config-
ureFmInterrupt API parameter.
No silicon fix planned. Use workaround.
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4F single
Errata
4. SMPU/MPU/PPU protection region size is limited to 2 GB
Problem Definition
If SMPU/MPU/PPU protection block size is configured for 4 GB (PROT_SMPU_SMPU_-
STRUCT_ATT0.REGION.SIZE = 31), then during protection check in SROM, the value of the internal uint32
variable will overflow (4G = 0x1 0000 0000). Therefore, SROM assumes the protection size equals zero, and
no protection will be applied.
Parameters Affected
Trigger Condition(s)
Scope of Impact
NA
Configure SMPU/MPU/PPU to protect with region size equal to 4 GB or the region size with value 31u.
If SMPU/MPU/PPU is configured to protect region size of 4 GB, then SROM software does not apply any
protection as per the request.
Workaround
Fix Status
Use two protection blocks of region size equal to 2 GB if 4-GB region size protection is required.
No silicon fix planned. Use workaround.
5. DirectExecute API may return error if called with arguments placed in SRAM memory
Problem Definition
If DirectExecute API is called in the master PC (other than PC0 or PC1) with arguments in
SRAM_SCRATCH_ADDR, then the API will return STATUS_ADDR_PROTECTED.
Parameters Affected
Trigger Condition(s)
Scope of Impact
NA
Call DirectExecute API with arguments in SRAM_SCRATCH_ADDR and master PC configured > 1.
DirectExecute API, if called with master PC configured > 1 and arguments in SRAM_SCRATCH_ADDR, the
API will return STATUS_ADDR_PROTECTED.
Workaround
Fix Status
Call DirectExecute API with master PC0 or PC1, if arguments are stored in SRAM memory.
No silicon fix planned. Use workaround.
6. CAN FD RX FIFO top pointer feature does not function as expected
Problem Definition
The RX FIFO top pointer function calculates the address for received messages in Message RAM by
hardware. This address should restart back from the start address after reading all messages of RX FIFO n
size (n: 0 or 1). However, the address does not restart from the start address when the RX FIFO n size is set
to 1 (CANFD_CH_RXFnC.FnS = 0x01). This results in CPU/DMA reading messages from the wrong address
in Message RAM.
Parameters Affected
Trigger Condition(s)
Scope of Impact
NA
RX FIFO top pointer function is used when RX FIFO n size is set to 1 element (CANFD_CH_RXFnC.FnS = 0x01).
Received message cannot be correctly read by using the RX FIFO top pointer function, when the RX FIFO
n size is set to 1 element.
Workaround
Any of the following:
1) Set RX FIFO n size to 2 or more when using the RX FIFO top pointer function.
2) Do not use the RX FIFO top pointer function when RX FIFO n size is set to 1 element. Instead of reading
received messages from the RX FIFO top pointer, read directly from the Message RAM.
Fix Status
No silicon fix planned. Use workaround.
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4F single
Errata
7. CAN FD debug message handling state machine does not reset to Idle state when CANFD_CH_CCCR.INIT is set
Problem Definition
If either of the CANFD_CH_CCCR.INIT bits is set by the Host or when the M_TTCAN module enters BusOff
state, the debug message handling state machine stays in its current state instead of being reset to Idle
state. Configuring the CANFD_CH_CCCR.CCE bit does not change CANFD_CH_RXF1S.DMS.
Parameters Affected
Trigger Condition(s)
Scope of Impact
NA
Either of the CANFD_CH_CCCR.INIT bits is set by the Host or when the M_TTCAN module enters BusOff state.
The errata is limited to the use case when the Debug on CAN functionality is active. Normal operation of
the CAN module is not affected, in which case the debug message handling state machine always remains
in Idle state. In the described use case, the debug message handling state machine is stopped and remains
in the current state signaled by the CANFD_CH_RXF1S.DMS bit. If CANFD_CH_RXF1S.DMS is set to 0b11, the
DMA request remains active.
Workaround
Fix Status
In case the debug message handling state machine stops while CANFD_CH_RXF1S.DMS is 0b01 or 0b10, it
can be reset to Idle state by hardware reset or by reception of debug messages after CANFD_CH_CCCR.INIT
is reset to zero.
No silicon fix planned. Use workaround.
8. TPIU Peripheral ID mismatch
Problem Definition
Parameters Affected
Trigger Condition(s)
Scope of Impact
Workaround
TPIU peripheral ID indicates that it is M3-TPIU instead of M4-TPIU.
NA
When the debugger reads PID registers for component identification.
The only impact is that the debuggers read the TPIU as M3-TPIU.
No specific workaround required. Debuggers can use trace features.
No fix planned
Fix Status
9. Limitation of the memory hole in SCB register space
Problem Definition
The memory hole [offset address: 0x1000 to 0xFFFF] inside the SCB register space is not aligned to the below
defined spec. Since the offset address bits [15:12] are ignored and treated as 4'b0000, write/read access to
the offset address [0x1000 to 0xFFFF] will actually happen to [0x0000 to 0x0FFF].
- Access to address gaps in mapped memory space: writes are ignored and any read returns a zero.
Parameters Affected
Trigger Condition(s)
Scope of Impact
NA
Access to the memory hole [offset address: 0x1000 to 0xFFFF] in SCB register space
The memory hole [offset address: 0x1000 to 0xFFFF] in the SCB register space is not aligned to other IP
registers.
Workaround
Fix Status
Do not access to the memory hole [offset address: 0x1000 to 0xFFFF] in SCB register space.
No fix planned
Datasheet
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Based on Arm® Cortex®-M4F single
Errata
10. WDT service can be missed
Problem Definition
If WDT service happens within 4 ILO clock cycles before DeepSleep entry, it clears the counter but does not
fully complete an internal handshake. A service after DeepSleep wakeup may then be missed if it occurs
less than 2 ILO clock cycles after the processor resumes clocking. After this time, the internal handshake is
complete and servicing works normally.
Parameters Affected
Trigger Condition(s)
NA
Service WDT within 4 ILO clock cycles before DeepSleep entry and within 2 ILO clock cycles of processor
clock resuming
Scope of Impact
Workaround
WDT service after DeepSleep wakeup may be ignored and WDT continues counting.
This can cause unintended WARN_ACTION or UPPER_ACTION, including interrupt, fault, and/or reset.
Wait 130 µs or more after DeepSleep wakeup. (For example, to measure 130 µs, software can read WDT_CNT
register at wake up and make sure that WDT_CNT was incremented of 4 units before servicing WDT).
Afterwards, write '1' to WDT service (WDT_SERVICE.SERVICE) after waiting until WDT service
(WDT_SERVICE.SERVICE) reads '0'.
Fix Status
No silicon fix planned. Use workaround.
11. CAN FD controller message order inversion when transmitting from dedicated Tx Buffers configured with same Message ID
Problem Definition
Configuration:
Several Tx buffers are configured with the same Message ID. Transmission of these Tx buffers is requested
sequentially with a delay between the individual Tx requests.
Expected behavior:
When multiple Tx buffers that are configured with the same Message ID have pending Tx requests, they
shall be transmitted in ascending order of their Tx buffer numbers. The Tx buffer with the lowest buffer
number and pending Tx request is transmitted first.
Observed behavior:
It may happen, depending on the delay between the individual Tx requests, that in the case where multiple
Tx buffers are configured with the same Message ID, the Tx buffers are not transmitted in order of the Tx
buffer number (lowest number first).
Parameters Affected
Trigger Condition(s)
Scope of Impact
NA
When multiple Tx buffers, configured with the same Message ID, have pending Tx requests.
In the case described it is possible that Tx buffers configured with the same Message ID and pending Tx
request are not transmitted with the lowest Tx buffer number first (message order inversion).
Workaround
Any of the following:
1) First write the group of Tx message with the same Message ID to the Message RAM and later request
transmission of all these messages concurrently by a single write access to CANFDx_CHy_TXBAR. Before
requesting a group of Tx messages with this Message ID, ensure that no message with this Message ID has
a pending Tx request.
2) Use the Tx FIFO instead of dedicated Tx buffers for the transmission of several messages with the same
Message ID in a specific order.
Applications not able to use workaround #1 or #2 can implement a counter within the data section of their
messages sent with same ID in order to allow the recipients to determine the correct sending sequence.
Fix Status
No silicon fix planned. Use workaround.
Datasheet
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4F single
Errata
12. CAN FD incomplete description of Dedicated Tx Buffers and Tx Queue related to transmission from multiple
buffers configured with the same Message ID
Problem Definition
The following are the updated description in Sections "Dedicated Tx Buffers" and "Tx Queue" of
the Architecture TRM related to the transmission from multiple buffers configured with the same
Message ID.
Dedicated Tx buffers
- TRM statement: If multiple Tx buffers are configured with the same Message ID, the Tx Buffer with
the lowest buffer number is transmitted first.
- Enhancement: These Tx buffers shall be requested in ascending order with the lowest buffer
number first. Alternatively all Tx buffers configured with the same Message ID can be requested
simultaneously by a single write access to CANFDx_CHy_TXBAR.
Tx Queue
- TRM statement: If multiple queue buffers are configured with the same Message ID, the queue
buffer with the lowest buffer number is transmitted first.
- Replacement: If multiple Tx Queue buffers are configured with the same Message ID, the trans-
mission order depends on numbers of the buffers where the messages were stored for trans-
mission. As these buffer numbers depend on the then current states of the PUT Index, a prediction
of the transmission order is not possible.
- TRM statement: An Add Request cyclically increments the Put Index to the next free Tx Buffer.
- Replacement: The PUT Index always points to that free buffer of the Tx Queue with the lowest
number.
Parameters Affected NA
Trigger Condition(s) Using multiple dedicated Tx Buffers or Tx Queue Buffers configured with the same Message ID.
Scope of Impact
In the case the dedicated Tx Buffers with the same Message ID are not requested in ascending
order or at the same time or in case of multiple Tx Queue Buffers with the same Message ID, it
cannot be guaranteed, that these messages are transmitted in ascending order with lowest buffer
number first.
Workaround
In case a defined order of transmission is required the Tx FIFO shall be used for transmission of
messages with the same Message ID. Alternatively dedicated Tx Buffers with the same Message ID
shall be requested in ascending order with lowest buffer number first or by a single write access
to CANFDx_CHy_TXBAR. Alternatively a single Tx Buffer can be used to transmit those messages
one after the other.
Fix Status
No silicon fix planned. Use workaround. TRM was updated accordingly.
13.Misleading status is returned for Flash and eFuse system calls, if there are pending NC ECC faults in SRAM
controller #0
Problem Definition
Flash and eFuse system calls will return misleading status of 0xF0000005 (“Page is write
protected”) even for non-protected row, or 0xF0000002 (“Invalid eFuse address”) for valid eFuse
address in case of pending NC ECC faults in SRAM controller #0.
Parameters Affected Return status of Flash and eFuse system calls.
Trigger Condition(s) NC ECC fault(s) pending in SRAM controller #0 and SWPUs are populated in the design.
Scope of Impact
Flash and eFuse system calls will not work until the NC ECC fault(s) pending in SRAM controller #0
is/are properly handled.
Workaround
If the NC ECC fault(s) are not due to HW malfunction (i.e. if the faults are due to usage of
non-initialized SRAM or improper SRAM initialization), then clearing of these pending faults will
resolve the issue.
Fix Status
No silicon fix planned. TRM will be updated.
Datasheet
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4F single
Errata
14.WDT reset causes loss of SRAM retention
Problem Definition
The “Reset Cause Distribution” table in the Architecture TRM shows that the WDT reset can retain
SRAM if there is an orderly shutdown of the SRAM only during a warning interrupt. However, this
is wrong. WDT reset causes loss of SRAM retention.
Parameters Affected
Trigger Condition(s)
Scope of Impact
Workaround
NA
WDT reset
WDT reset causes loss of SRAM retention.
None
Fix Status
No silicon fix planned. TRM will be updated.
15.Crypto ECC errors may be set after boot with application authentication
Problem Definition
Due to the improper initialization of the Crypto memory buffer, Crypto ECC errors may be set
after boot with application authentication. In spite of the Crypto ECC errors, the result of the
authentication is reliable.
Parameters Affected
Trigger Condition(s)
Scope of Impact
Workaround
N/A
Boot device with application authentication.
Crypto ECC errors may be set after boot with application authentication.
Clear or ignore Crypto ECC errors which were generated during boot with application authentication.
No silicon fix planned. TRM will be updated.
Fix Status
16.Incomplete erase of Code Flash cells could happen Erase Suspend / Erase Resume is used along with Erase Sector
operation in Non-Blocking mode
Problem Definition
Code Flash memory can be erased in “Non-Blocking” mode; a Non-Blocking mode supported
option allow users to suspend an ongoing erase sector operation. When an ongoing erase
operation is interrupted using “Erase Suspend” and “Erase Resume”, Flash cells may not have
been erased completely, even after the erase operation complete is indicated by FLASH-
C_STATUS register. Only Code Flash is impacted by this issue, Work Flash and Supervisory Flash
(SFlash) are not impacted.
Parameters Affected
Trigger Condition(s)
N/A
Using EraseSector System Call in Non-Blocking mode for CM0+ to erase Code Flash and the
ongoing erase operation is interrupted using EraseSuspend and EraseResume System calls.
Scope of Impact
When Code Flash sectors are erased in Non-Blocking mode and the ongoing erase operation is
interrupted by Erase Suspend / Erase Resume, it cannot be guaranteed that the Code Flash cells
are fully erased. Any read on the Code Flash area after the erase is complete or read on the
programmed data after ProgramRow is complete can trigger ECC errors.
Workaround
Use any of the following:
1) User can use Non-Blocking mode for EraseSector, but must not interrupt the erase operation
using Erase Suspend / Erase Resume.
2) If a Code Flash sector erase operation is interrupted using Erase Suspend / Erase Resume, then
erase the same sector again without Erase Suspend / Erase Resume before reading the sector or
programming the sector.
Fix Status
Will be fixed to update the Flash settings, via Manufacturing Test Program Update for Code Flash
setting; this fix is transferred to TRAVEO™ T2G devices during Infineon Factory Test Flow. Fixed
devices will be identified by Device Date Code, which is marked on every TRAVEO™ T2G device.
Datasheet
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4F single
Errata
17.Limitation for keeping the port state from peripheral IP after wakeup from DeepSleep
Problem Definition
The port state is not retained when the port selects peripheral IP (except for LIN or CAN FD) and
MCU wakes up from DeepSleep.
Parameters Affected
Trigger Condition(s)
Scope of Impact
Workaround
N/A
The port selects peripherals (except for LIN or CAN-FD) and MCU wakes up from DeepSleep.
Unexpected port output change might affect user system.
If the port selects peripherals (except for LIN or CAN FD), and the port output value needed to be
maintained after wakeup from DeepSleep, set HSIOM_PRTx_PORT_SEL.IOy_SEL = 0 (GPIO)
before DeepSleep and set the required output value in GPIO configuration registers. After
wakeup, change HSIOM_PRTx_PORT_SEL.IOy_SEL back to the peripheral module as needed.
Fix Status
No silicon fix planned. TRM will be updated to add above workaround.
Datasheet
158
002-18043 Rev. *J
2022-09-08
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4F single
Revision history
Revision history
Document
Date
Description of changes
revision
**
02/10/2017 Advance datasheet
*A
03/31/2017 Extensive rewrite of all sections for better clarity
Updated Features.
Minor corrections in Features list.
Updated Blocks and functionality.
Updated Functional description.
Updated Memory Map to clarify single and dual bank mode functionality.
Updated Electrical specifications.
Added the following timing diagrams in Electrical specifications:
*B
09/11/2017
Reset, TCPWM, SCB (I2C, SPI), Crystal Connection Scheme, SAR ADC, System
Resources, and JTAG.
Updated Ordering information.
Updated Packaging to include two formats:
- Without alternate functions
- With alternate functions
Updated Package Characteristics.
Updated Ordering information.
Updated title to “CYT2B5/B7 Datasheet 32-bit Arm® Cortex®-M4F Microcon-
troller TRAVEO™ T2G Family”.
*C
*D
02/12/2018
Updated Electrical specifications.
Updated SPI Diagrams.
Added ADC equivalent circuit for analog input.
Updated Features list and Peripheral I/O map.
Updated Pin assignment.
Updated Alternate function pin assignments
Updated Functional description.
Updated Trigger multiplexer and Interrupts and wake-up assignments.
Added General P-DMA descriptions, Clock Dividers, and GPIO power port
09/27/2018
source information.
Updated Clock diagram
Added HSIOM connections reference table and references to it in alternate
pin assignment. Update Electrical specifications.
Updated Design Review.
Added Errata.
Updated Features, Features list, and Functional description.
Updated Peripheral I/O map.
Updated Alternate function pin assignments
Updated Interrupts and wake-up assignments and Core interrupt types.
Updated Trigger Groups and Peripheral clocks.
Updated Peripheral Protection Unit Fixed Structure Pairs.
Updated Bus masters.
*E
07/25/2019
Updated Miscellaneous configuration.
Updated Reset Sequence, ADC, and SPI Diagrams.
Updated Table 26-21 and Table 26-24.
Updated Ordering information and Packaging.
Updated Appendix.
Datasheet
159
002-18043 Rev. *J
2022-09-08
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4F single
Revision history
Document
Date
Description of changes
revision
Updated SRAM in CYT2B7 address map.
Updated PLL and FLL in Functional description.
Updated Programmable PPU and SCB in Peripheral I/O map.
Updated Package Characteristics.
*F
11/26/2019
Updated affected MPNs in Errata.
Updated sample revision in Ordering information.
Added eSHE footnote on page 1.
Updated Block diagram.
Updated SCB/UART content in Functional description.
Added note for VCCD in Power pin assignments.
Added Pin Mux descriptions.
*G
*H
04/23/2020
Updated Fault Assignments table with detailed descriptions.
Added JTAG ID and package support footnotes in Ordering information.
Removed CM7 from Part number nomenclature.
Updated Packaging.
Updated Errata.
Updated Features list.
Updated Clock system.
Updated Electrical specifications.
06/29/2020 Updated Ordering information.
Updated Appendix.
For details, refer to Revision History Change Log.
Updated Features list.
Updated Communication peripheral instance list.
Updated High-speed I/O matrix connections.
Updated Alternate function pin assignments.
Updated Faults.
*I
10/13/2021 Updated Electrical specifications.
Updated Part number nomenclature.
Updated Appendix.
Added Errata.
For details, refer to Rev *I updates in the Revision History Change Log.
Updated Electrical specifications.
09/08/2022 Updated Errata.
For details, refer to Rev *J updates in the Revision History Change Log.
*J
Datasheet
160
002-18043 Rev. *J
2022-09-08
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M4F single
Revision history
Revision History Change Log
Rev. *J Section Updates
Section
Change Description
Current Spec (Rev. *I)
New Spec (Rev. *J)
Reason for change
26.10 System
resources
Updated Figure 26-14
OVD, BOD
HV OVD, HV BOD
Improvement
XRES_L: Hight Level (left side) / Low Level (right XRES_L: LOW Level (left side) / HIGH Level (right side)
side)
31. Errata
Added errata
-
Added errata ID 175, 176, 185, 198, 199
Added errata
Rev *J Electrical Specification Updates
Section
Change description
Current spec (Rev *I)
New spec (Rev *J)
Reason for change
SID200 (Temperature
Sensor accuracy 1)
All
Temperature Sensor accuracy 1
(none)
Merged to SID201
SID201 (Temperature
Sensor accuracy 2)
Description
Details/Conditions
- 40 °C =< TJ < 150 °C
- 40 °C =< TJ =< 150 °C
Merged with SID200
This spec is valid when using ADC[0]
This spec is valid when using ADC[0]
(VDDIO_1), ADC[1] (VDDIO_2) or ADC[2] (VDDD) (VDDIO_1), ADC[1] (VDDIO_2) or ADC[2]
with the following conditions:
(VDDD) with the following conditions:
a. 3.0 V =< VDDD, VDDIO_1 or VDDIO_2 = VDDA a. 3.0 V =< VDDD, VDDIO_1 or VDDIO_2 =
= VREFH =< 3.6 V
or
VDDA = VREFH =< 3.6 V
or
b. 4.5 V =< VDDD, VDDIO_1 or VDDIO_2 = VDDA b. 4.5 V =< VDDD, VDDIO_1 or VDDIO_2 =
= VREFH =< 5.5 V
VDDA = VREFH =< 5.5 V
SID40
Updated Note
[47]: 5.0 V ±10% is supported with a higher OVD [47]: 5.0 V ±10%is supported with ahigher Corrected
setting option for VDDD and VDDA. This setting OVD setting option for VDDD and VDDA.
(Power supply voltage)
provides robust protection for internal and
interface timing, but OVD reset occurs at a
This setting provides robust protection
for internal and interface timing, but OVD
voltage above the specified operating condi- reset occurs at a voltage above the
tions. A lower OVD setting option is available specified operating conditions. A lower
(consistent with up to 5.0 V) and guarantees
that all operating conditions are met.
OVD setting option is available
(consistent with up to 5.0 V) and
guarantees that all operating conditions
are met. Voltage overshoot to a higher
OVD setting range for VDDD and VDDA is
permissible, provided the duration is less
than 2 hours cumulated. Note that during
overshoot voltage condition electrical
parameters are not guaranteed.
SID18
Updated Note
[39]: When the conditions of [42], [43], and… [39]: When the conditions of [37], [38],
and...
Corrected
Datasheet
161
002-18043 Rev. *J
2022-09-08
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