CYT2B93BACQ0AZSGS_技术文档

CYT2B9

TRAVEO™ T2G 32-bit Automotive MCU

Based on Arm® Cortex®-M4F single

General description

CYT2B9 is a family of TRAVEO™ T2G microcontrollers targeted at automotive systems such as body control units.

CYT2B9 has an Arm® Cortex®-M4 CPU for primary processing, and an Arm® Cortex®-M0+ CPU for peripheral and

security processing. These devices contain embedded peripherals supporting Controller Area Network with

Flexible Data rate (CAN FD), Local Interconnect Network (LIN), and Clock Extension Peripheral Interface (CXPI).

TRAVEO™ T2G devices are manufactured on an advanced 40-nm process. CYT2B9 incorporates a low-power flash

memory, multiple high-performance analog and digital peripherals, and enables the creation of a secure

computing platform.

Features

• Dual CPU subsystem

- 160-MHz (max) 32-bit Arm® Cortex®-M4F CPU with

• Single-cycle multiply

• Single-precision floating point unit (FPU)

• Memory protection unit (MPU)

- 100-MHz (max) 32-bit Arm® Cortex® M0+ CPU with

• Single-cycle multiply

• Memory protection unit

- Inter-processor communication in hardware

- Three DMA controllers

• Peripheral DMA controller #0 (P-DMA0) with 92 channels

• Peripheral DMA controller #1 (P-DMA1) with 44 channels

• Memory DMA controller #0 (M-DMA0) with 4 channels

• Integrated memories

- 2112-KB of code-flash with an additional 128-KB of work-flash

• Read-While-Write (RWW) allows updating the code-flash/work-flash while executing code from it

• Single- and dual-bank modes (specifically for Firmware update Over The Air [FOTA])

• Flash programming through SWD/JTAG interface

- 256-KB of SRAM with selectable retention granularity

• Crypto engine^[1]

- Supports Enhanced Secure Hardware Extension (eSHE) and Hardware Security Module (HSM)

- Secure boot and authentication

• Using digital signature verification

• Using fast secure boot

- AES: 128-bit blocks, 128-/192-/256-bit keys

- 3DES^[2]: 64-bit blocks, 64-bit key

- Vector unit^[2]supporting asymmetric key cryptography such as Rivest-Shamir-Adleman (RSA) and Elliptic

Curve (ECC)

- SHA-1/2/3^[2]: SHA-512, SHA-256, SHA-160 with variable length input data

- CRC^[2]: supports CCITT CRC16 and IEEE-802.3 CRC32

- True random number generator (TRNG) and pseudo random number generator (PRNG)

- Galois/Counter Mode (GCM)

• Functional safety for ASIL-B

- Memory Protection Unit (MPU)

Notes

1. Crypto engine features are available on select MPNs.

2. This feature is not available in “eSHE only” parts. For more information, see Ordering Information.

Datasheet

www.infineon.com

Please read the Important Notice and Warnings at the end of this document

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TRAVEO™ T2G 32-bit Automotive MCU

Based on Arm® Cortex®-M4F single

Features

- Shared Memory Protection Unit (SMPU)

- Peripheral Protection Unit (PPU)

- Watchdog timer (WDT)

- Multi-counter watchdog timer (MCWDT)

- Low-voltage detector (LVD)

- Brown-out detector (BOD)

- Overvoltage detection (OVD)

- Clock supervisor (CSV)

- Hardware error correction (SECDED ECC) on all safety-critical memories (SRAM, flash)

• Low-power 2.7-V to 5.5-V operation

- Low-power Active, Sleep, Low-power Sleep, DeepSleep, and Hibernate modes for fine-grained power

management

- Configurable options for robust BOD

• Two threshold levels (2.7 V and 3.0 V) for BOD on V_DDDand V_DDA

• One threshold level (1.1 V) for BOD on V_CCD

• Wakeup support

- Up to two pins to wakeup from Hibernate mode

- Up to 152 GPIO pins to wakeup from Sleep modes

- Event Generator, SCB, Watchdog Timer, RTC alarms to wake from DeepSleep modes

• Clock sources

- Internal Main Oscillator (IMO)

- Internal Low-Speed Oscillator (ILO)

- External Crystal Oscillator (ECO)

- Watch Crystal Oscillator (WCO)

- Phase-Locked Loop (PLL)

- Frequency-Locked Loop (FLL)

• Communication interfaces

- Up to eight CAN FD channels

• Increased data rate (up to 8 Mbps) compared to classic CAN, limited by physical layer topology and

transceivers

• Compliant to ISO 11898-1:2015

• Supports all the requirements of Bosch CAN FD Specification V1.0 for non-ISO CAN FD

• ISO 16845:2015 certificate available

- Up to eight runtime-reconfigurable SCB (serial communication block) channels, each configurable as I²C, SPI,

or UART

- Up to 12 independent LIN channels

• LIN protocol compliant with ISO 17987

- Up to four CXPI channels with data rate up to 20 kbps

• Timers

- Up to 75 16-bit and eight 32-bit timer/counter pulse-width modulator (TCPWM) blocks

• Up to 12 16-bit counters for motor control

• Up to 63 16-bit counters and eight 32-bit counters for regular operations

• Supports timer, capture, quadrature decoding, pulse-width modulation (PWM), PWM with dead time (PW-

M_DT), pseudo-random PWM (PWM_PR), and shift-register (SR) modes

- Up to 11 Event Generation (EVTGEN) timers supporting cyclic wakeup from DeepSleep

• Events trigger a specific device operation (such as execution of an interrupt handler, a SAR ADC conversion,

and so on)

Datasheet

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TRAVEO™ T2G 32-bit Automotive MCU

Based on Arm® Cortex®-M4F single

Features

• Real time clock (RTC)

- Year/Month/Date, Day-of-week, Hour:Minute:Second fields

- Supports both 12- and 24-hour formats

- Automatic leap-year correction

• I/O

- Up to 152 programmable I/Os

- Two I/O types

• GPIO Standard (GPIO_STD)

• GPIO Enhanced (GPIO_ENH)

• Regulators

- Generates 1.1-V nominal core supply from a 2.7-V to 5.5-V input supply

- Two types of regulators

• DeepSleep

• Core internal

• Programmable analog

- Three SAR A/D converters with up to 67 external channels (64 I/Os + 3 I/Os for motor control)

• ADC0 supports 24 logical channels, with 24 + 1 physical connections

• ADC1 supports 32 logical channels, with 32 + 1 physical connections

• ADC2 supports 8 logical channels, with 8 + 1 physical connections

• Any external channel can be connected to any logical channel in the respective SAR

- Each ADC supports 12-bit resolution and sampling rates of up to 1 Msps

- Each ADC also supports up to six internal analog inputs such as:

• Bandgap reference to establish absolute voltage levels

• Calibrated diode for junction temperature calculations

• Two AMUXBUS inputs and two direct connections to monitor supply levels

- Each ADC supports addressing of external multiplexers

- Each ADC has a sequencer supporting autonomous scanning of configured channels

- Synchronized sampling of all ADCs for motor-sense applications

• Smart I/O

- Up to five Smart I/O blocks, which can perform Boolean operations on signals going to and from I/Os

- Up to 36 I/Os (GPIO_STD) supported

• Debug interface

- JTAG controller and interface compliant to IEEE-1149.1-2001

- Arm® SWD (serial wire debug) port

- Supports Arm® Embedded Trace Macrocell (ETM) Trace

• Data trace using SWD

• Instruction and data trace using JTAG

• Compatible with industry-standard tools

- GHS/MULTI or IAR EWARM for code development and debugging

• Packages

- 64-LQFP, 10 × 10 × 1.7 mm (max), 0.5-mm lead pitch

- 80-LQFP, 12 × 12 × 1.7 mm (max). 0.5-mm lead pitch

- 100-LQFP, 14 × 14 × 1.7 mm (max), 0.5-mm lead pitch

- 144-LQFP, 20 × 20 × 1.7 mm (max), 0.5-mm lead pitch

- 176-LQFP, 24 × 24 × 1.7 mm (max), 0.5-mm lead pitch

Datasheet

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Based on Arm® Cortex®-M4F single

Table of contents

1 Features list .................................................................................................................................. 5

1.1 Communication peripheral instance list....................................................................................................... 6

2 Blocks and functionality ................................................................................................................ 7

3 Block diagram ............................................................................................................................... 7

4 Functional description ................................................................................................................... 8

4.1 CPU subsystem............................................................................................................................................... 8

4.2 System resources ........................................................................................................................................... 9

4.3 Peripherals.................................................................................................................................................... 11

4.4 I/Os................................................................................................................................................................ 15

5 CYT2B9 address map ................................................................................................................... 17

6 Flash base address map ................................................................................................................18

7 Peripheral I/O map .......................................................................................................................19

8 CYT2B9 clock diagram ..................................................................................................................21

9 CYT2B9 CPU start-up sequence ......................................................................................................22

10 Pin assignment ...........................................................................................................................23

11 High-Speed I/O matrix connections ..............................................................................................33

12 Package pin list and alternate functions .......................................................................................34

13 Power pin assignments ...............................................................................................................40

14 Alternate function pin assignments .............................................................................................41

15 Interrupts and wake-up assignments ...........................................................................................49

16 Core interrupt types ...................................................................................................................59

17 Trigger multiplexer ....................................................................................................................60

18 Triggers group inputs .................................................................................................................61

19 Triggers group outputs ...............................................................................................................64

20 Triggers one-to-one ....................................................................................................................65

21 Peripheral clocks ........................................................................................................................69

22 Faults ........................................................................................................................................73

23 Peripheral protection unit fixed structure pairs ............................................................................76

24 Bus masters ...............................................................................................................................87

25 Miscellaneous configuration ........................................................................................................88

26 Development support .................................................................................................................89

26.1 Documentation .......................................................................................................................................... 89

26.2 Tools............................................................................................................................................................ 89

27 Electrical specifications ............................................................................................................. 90

27.1 Absolute maximum ratings........................................................................................................................ 90

27.2 Device-level specifications......................................................................................................................... 93

27.3 DC specifications ........................................................................................................................................ 94

27.4 Reset specifications.................................................................................................................................... 98

27.5 I/O................................................................................................................................................................ 99

27.6 Analog peripherals ................................................................................................................................... 105

27.7 AC specifications ...................................................................................................................................... 112

27.8 Digital peripherals.................................................................................................................................... 112

27.9 Memory ..................................................................................................................................................... 124

27.10 System resources ................................................................................................................................... 125

27.11 Clock specifications................................................................................................................................ 136

28 Ordering Information ...............................................................................................................142

28.1 Part number nomenclature ...................................................................................................................... 142

29 Packaging ................................................................................................................................ 145

30 Appendix ................................................................................................................................. 152

30.1 Bootloading or end-of-line programming ............................................................................................... 152

30.2 External IP revisions.................................................................................................................................. 153

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Table of contents

31 Acronyms ................................................................................................................................ 154

32 Errata ...................................................................................................................................... 156

Revision history ............................................................................................................................ 162

Revision History Change Log ............................................................................................................................ 163

Datasheet

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Based on Arm® Cortex®-M4F single

Features list

1

Features list

Table 1-1

CYT2B9 feature list for all packages

Package

100-LQFP

Features

64-LQFP

80-LQFP

144-LQFP

176-LQFP

CPU

Core

32-bit Arm® Cortex®-M4F CPU and 32-bit Arm® Cortex® M0+ CPU

Functional safety

Operating voltage

Core voltage

ASIL-B

2.7 V to 5.5 V

1.05 V to 1.15 V

Arm® Cortex®-M4 160 MHz (max) and Arm® Cortex®-M0+ 100 MHz (max),

related by integer frequency ratio (that is, 1:1, 1:2, 1:3, and so on)

Operating frequency

MPU, PPU

Supported

FPU

Single precision (32-bit)

DSP-MUL/DIV/MAC

Memory

Supported by Arm® Cortex®-M4F CPU

Code-flash

Work-flash

SRAM (configurable for retention)

ROM

2112 KB (1984 KB + 128 KB)

128 KB (96 KB + 32 KB)

256 KB

32 KB

Communication interfaces

CAN0 (CAN FD: Up to 8 Mbps)

CAN1 (CAN FD: Up to 8 Mbps)

CAN RAM

Serial communication block (SCB/UART)

Serial communication block (SCB/I²C)

Serial communication block (SCB/SPI)

LIN0

3 ch

6 ch

4 ch

2 ch

7 ch

4 ch

32 KB per instance (4 ch), 64 KB in total

8 ch

3 ch

7 ch

2 ch

6 ch

3 ch

8 ch

9 ch

12 ch

CXPI controller

4 ch

Timers

RTC

1 ch

12 ch

63 ch

8 ch

78

TCPWM (16-bit) (Motor Control)

TCPWM (16-bit)

TCPWM (32-bit)

External interrupts

Analog

49

63

122

152

3 Units (SAR0/24, SAR1/32, SAR2/8 logical channels)

27 external

channels

34 external

channels

39 external

channels

54 external

channels

64 external

channels

(SAR0 11 ch,

SAR1 9 ch,

SAR2 7 ch)

(SAR0 12 ch,

(SAR0 14 ch,

(SAR0 21 ch,

(SAR0 24 ch,

SAR1 32 ch,

SAR2 8 ch)

12-bit, 1 Msps SAR ADC

SAR1 14 ch, SAR117ch, SAR2 SAR1 25 ch, SAR2

SAR2 8 ch)

8 ch)

18 ch (6 per ADC) Internal sampling

Note

3. Enhanced Secure Hardware Extension (eSHE) and Hardware Security Module (HSM) support are enabled by third-party firmware.

Datasheet

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TRAVEO™ T2G 32-bit Automotive MCU

Based on Arm® Cortex®-M4F single

Features list

Table 1-1

CYT2B9 feature list for all packages (continued)

Features

Package

64-LQFP

80-LQFP

100-LQFP

144-LQFP

176-LQFP

Motor control input

3 ch (synchronous sampling of one channel on each of the 3 ADCs)

Security

Flash Security (program/work read pro-

tection)

Supported

Flash Chip erase enable

eSHE/HSM

Configurable

By separate firmware^[3]

System

P-DMA0 with 92 channels (16 general purpose), P-DMA1 with 44

channels (8 general purpose), and M-DMA0 with 4 channels

DMA controller

Internal main oscillator

8 MHz

Internal low-speed oscillator

32.768 kHz (nominal)

Input frequency: 3.988 to 33.34 MHz, PLL output frequency: up to 160

MHz

Input frequency: 0.25 to 80 MHz, FLL output frequency: up to 100 MHz

PLL

FLL

Watchdog timer and multi-counter

Watchdog timer

Supported

Clock supervisor

Cyclic wakeup

GPIO_STD

Supported

45

59

74

118

148

GPIO_ENH

4

3 blocks,

9 I/Os

3 blocks,

14 I/Os

4 blocks,

20 I/Os

5 blocks,

29 I/Os

5 blocks,

36 I/Os

Smart I/O (Blocks)

Low-voltage detect

Maximum ambient temperature

Debug interface

Two, 26 selectable levels

105 °C for S-grade and 125 °C for E-grade

SWD/JTAG

Debug trace

Arm® Cortex®-M4 ETB size of 8 KB, Arm® Cortex® M0+ MTB size of 4 KB

1.1

Communication peripheral instance list

The following table lists the instances supported under each package for communication peripherals, based on

the minimum pins needed for the functionality.

Table 1

Peripheral instance list

Module

CXPI

CAN0

CAN1

LIN0

64-LQFP

0/1

0/1/2

0/2

80-LQFP

0/1/2

100-LQFP

0/1/2/3

144-LQFP

0/1/2/3

176-LQFP

0/1/2/3

Minimum pin functions

TX, RX

0/1/2/3

0/1/2/3/4/7/9 0/1/2/3/4/6/7/8 0/1/2/3/4/6/7/8 0/1/2/3/4/5/6/7/ 0/1/2/3/4/5/6/7 TX, RX

/9 /9 8/9/10/11 /8/9/10/11

SCB/

UART

2

0/1/2/3/4/5/7 0/1/2/3/4/5/6/7 0/1/2/3/4/5/6/7 0/1/2/3/4/5/6/7 0/1/2/3/4/5/6/7 TX, RX

SCB/I C 0/2/3/4/5/7

SCB/SPI 0/3/4

0/1/3/4/5/7

0/1/2/3/4/5/6/7 0/1/2/3/4/5/6/7 0/1/2/3/4/5/6/7 SCL, SDA

0/1/2/3/4/5/6/7 0/1/2/3/4/5/6/7 0/1/2/3/4/5/6/7 MISO, MOSI, SCK,

SELECT0

Datasheet

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TRAVEO™ T2G 32-bit Automotive MCU

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Blocks and functionality

2

Blocks and functionality

Block diagram

CPU Subsystem

CYT2B9

SWJ/MTB/CTI

MXS40-HT

ASIL-B

SWJ/ETM/ITM/CTI

CRYPTO

eCT Flash

2112 KB Code-flash +

128 KB Work-flash

SRAM0

128 KB

SRAM1

128 KB

ROM

32 KB

Arm Cortex

M0+

100 MHz

AES, SHA, CRC,

TRNG, RSA,

ECC

Arm Cortex M4

160 MHz

8 KB $

System Resources

SRAM Controller

Initiator/MMIO

ROM Controller

FPU, NVIC, MPU

FLASH Controller

MUL, NVIC, MPU

Power

Sleep Control

POR

OVD

BOD

LVD

System Interconnect (Multi Layer AHB, IPC, MPU/SMPU)

Peripheral Interconnect (MMIO, PPU)

REF

PWRSYS-HT

LDO

PCLK

Clock

Clock Control

Prog.

Analog

2xILO

IMO

WDT

ECO

CSV

FLL

SAR

ADC

(12-bit)

1xPLL

Reset

Reset Control

XRES

Test

TestMode Entry

x3

Digital DFT

Analog DFT

SARMUX

64 ch

WCO

RTC

Power Modes

Active/Sleep

LowePowerActive/Sleep

High-Speed I/O Matrix, Smart I/O, Boundary Scan

5x Smart I/O

DeepSleep

Up to 148x GPIO_STD, 4x GPIO_ENH

Hibernate

I/O Subsystem

The Block diagram shows the CYT2B9 architecture, giving a simplified view of the interconnection between

subsystems and blocks. CYT2B9 has four major subsystems: CPU, system resources, peripherals, and I/O^{[4, 5]}. The

color-coding shows the lowest power mode where the particular block is still functional.

CYT2B9 provides extensive support for programming, testing, debugging, and tracing of both hardware and

firmware.

Debug-on-chip functionality enables in-system debugging using the production device. It does not require

special interfaces, debugging pods, simulators, or emulators.

The JTAG interface is fully compatible with industry-standard third-party probes such as I-jet, J-Link, and GHS.

The debug circuits are enabled by default.

CYT2B9 provides a high level of security with robust flash protection and the ability to disable features such as

debug.

Additionally, each device interface can be permanently disabled for applications concerned with phishing

attacks from a maliciously reprogrammed device or attempts to defeat security by starting and interrupting flash

programming sequences. All programming, debug, and test interfaces are disabled when maximum device

security is enabled.

Notes

4. GPIO_STD supporting 2.7 V to 5.5 V V_DDIOrange.

5. GPIO_ENH supporting 2.7 V to 5.5 V V_DDIOrange with higher currents at lower voltages.

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TRAVEO™ T2G 32-bit Automotive MCU

Based on Arm® Cortex®-M4F single

Functional description

3

Functional description

CPU subsystem

CPU

3.1

3.1.1

The CYT2B9 CPU subsystem contains a 32-bit Arm® Cortex®-M0+ CPU with MPU, and a 32-bit Arm® Cortex®-M4F

CPU with MPU, and single-precision FPU. This subsystem also includes P-/M-DMA controllers, a cryptographic

accelerator, 2112 KB of code-flash, 128 KB of work-flash, 256 KB of SRAM, and 32 KB of ROM.

The Cortex-M0+ CPU provides a secure, un-interruptible boot function. This guarantees that, following

completion of the boot function, system integrity is valid and privileges are enforced. Shared resources (flash,

SRAM, peripherals, and so on) can be accessed through bus arbitration, and exclusive accesses are supported by

an inter-processor communication (IPC) mechanism using hardware semaphores.

3.1.2

DMA controllers

CYT2B9 has three DMA controllers: P-DMA0 with 16 general-purpose and 76 dedicated channels, P-DMA1 with 8

general-purpose and 36 dedicated channels, and M-DMA0 with four channels. P-DMA is used for

peripheral-to-memory and memory-to-peripheral data transfers and provides low latency for a large number of

channels. Each P-DMA controller uses a single data-transfer engine that is shared by the associated channels.

General-purpose channels have a rich interconnect matrix including P-DMA cross-triggering, which enables

demanding data-transfer scenarios. Dedicated channels have a single triggering input (such as an ADC channel)

to handle common transfer needs. M-DMA is used for memory-to-memory data transfers and provides high

memory bandwidth for a small number of channels. M-DMA uses a dedicated data-transfer engine for each

channel. They support independent accesses to peripherals using the AHB multi-layer bus.

3.1.3

Flash

CYT2B9 has 2112 KB (1984 KB with a 32-KB sector size, and 128 KB with an 8-KB sector size) of code-flash with an

additional work-flash of up to 128 KB (96 KB with 2-KB sector size, and 32 KB with 128-B sectors size). Work-flash

is optimized for reprogramming many more times than code-flash. Code-flash supports Read-While-Write (RWW)

operation allowing flash to be updated while the CPU is active. Both the code-flash and work-flash areas support

dual-bank operation for over-the-air (OTA) programming.

3.1.4

SRAM

CYT2B9 has 256 KB of SRAM with two independent controllers. The first controller SRAM0 provides DeepSleep

retention in 32-KB increments while SRAM1 is selectable between fully retained and not retained.

3.1.5

ROM

CYT2B9 has 32-KB ROM that contains boot and configuration routines. This ROM enables secure boot and authen-

tication of user flash to guarantee a secure system.

3.1.6

Cryptography accelerator for security

The cryptography accelerator implements (3)DES block cipher, AES block cipher, SHA hash, cyclic redundancy

check, pseudo random number generation, true random number generation, galois/counter mode, and a vector

unit to support asymmetric key cryptography such as RSA and ECC.

Depending on the part number, this block is either completely or partially available or not available at all. See

Ordering Information for more details.

Datasheet

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Functional description

3.2

System resources

Power system

3.2.1

The power system ensures that the supply voltage levels meet the requirements of each power mode, and

provides a full-system reset when these levels are not valid. Internal power-on reset (POR) guarantees full-chip

reset during the initial power ramp.

Three BOD circuits monitor the external supply voltages (V_DDD, V_DDA, V_CCD). The BOD on V_DDDand V_CCDare initially

enabled and cannot be disabled. The BOD on V_DDAis initially disabled and can be enabled by the user. For the

external supplies V_DDDand V_DDA, BOD circuits are software configurable with two settings; a 2.7-V minimum

voltage that is robust for all internal signaling and a 3.0-V minimum voltage, which is also robust for all I/O

specifications (which are guaranteed at 2.7 V). The BOD on V_CCDis provided as a safety measure and is not a

robust detector.

Three OVD circuits are provided for monitoring external supplies (V_DDD, V_DDA, V_CCD), and overcurrent detection

circuits (OCD) for monitoring internal and external regulators. OVD thresholds on V_DDDand V_DDAare configurable

with two settings; a 5.0-V and 5.5-V maximum voltage.

Two voltage detection circuits are provided to monitor the external supply voltage (V_DDD) for falling and rising

levels, each configurable for one of the 26 selectable levels.

All BOD, OVD, and OCD circuits on V_DDDand V_CCDgenerate a reset, because these protect the CPUs and fault logic.

The BOD and OVD circuits on V_DDAcan be configured to generate either a reset, or a fault.

3.2.2

Regulators

CYT2B9 contains two regulators that provide power to the low-voltage core transistors: DeepSleep and core

internal. These regulators accept a 2.7–5.5-V V_DDDsupply and provide a low-noise 1.1-V supply to various parts

of the device. These regulators are automatically enabled and disabled by hardware and firmware when

switching between power modes. The core internal regulators operate in Active mode, and provide power to the

CPU subsystem and associated peripherals.

3.2.2.1

DeepSleep

The DeepSleep regulator is used to maintain power to a small number of blocks when in DeepSleep mode. These

blocks include the ILO and WDT timers, BOD detector, SCB0, SRAM memories, Smart I/O, and other configuration

memories. The DeepSleep regulator is enabled when in DeepSleep mode, and the core internal regulator is

disabled. It is disabled when XRES_L is asserted (LOW) and when the core internal regulator is disabled.

3.2.2.2

Core internal

The core internal regulator supports load currents up to 150 mA, and is operational during device startup (boot

process), and in Active/Sleep modes.

3.2.3

Clock system

The CYT2B9 clock system provides clocks to all subsystems that require them, and glitch-free switching between

different clock sources. In addition, the clock system ensures that no metastable conditions occur.

The clock system for CYT2B9 consists of the 8-MHz IMO, two ILOs, three watchdog timers, a PLL, an FLL, five clock

supervisors (CSV), a 3.988- to 33.34-MHz ECO, and a 32.768-kHz WCO.

The clock system supports two main clock domains: CLK_HF and CLK_LF.

• CLK_HFx are the active domain clocks. Each can use any of the high-frequency clock sources including IMO,

EXT_CLK, ECO, FLL, or PLL.

• CLK_LF is a DeepSleep domain clock and provides source for MCWDT or RTC modules. The reference clock for

the CLK_LF domain is selectable from ILO0, ILO1, WCO, or disabled.

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Based on Arm® Cortex®-M4F single

Functional description

Table 3-1

Name

CLK_HF destinations

Description

CLK_HF0

CLK_HF1

CPUSS clocks, PERI, and AHB infrastructure

Event Generator, also available in HSIOM as an output

3.2.3.1

IMO clock source

The IMO is the frequency reference in CYT2B9 when no external reference is available or enabled. The IMO

operates at a frequency of around 8 MHz.

3.2.3.2

ILO clock source

An ILO is a low-power oscillator, nominally 32.768 kHz, which generates clocks for a watchdog timer when in

DeepSleep mode. There are two ILOs to ensure CSV (clock supervisor) capability in DeepSleep mode. ILO-driven

counters can be calibrated to the IMO, WCO, or ECO to improve their accuracy. ILO1 is also used for clock super-

vision.

3.2.3.3

PLL and FLL

A PLL or FLL may be used to generate high-speed clocks from the IMO, the ECO, or EXT_CLK. The FLL provides a

much faster lock than the PLL (5 µs instead of 35 µs) in exchange for a small amount (±2%) of frequency error^[6]

.

3.2.3.4

Clock supervisor

Each clock supervisor (CSV) allows one clock (reference) to supervise the behavior of another clock (monitored).

Each CSV has counters for both the monitored and reference clocks. Parameters for each counter determine the

frequency of the reference clock as well as the upper and lower frequency limits of the monitored clock. If the

frequency range comparator detects a stopped clock or a clock outside the specified frequency range, an

abnormal state is signaled and either a reset or an interrupt is generated.

3.2.3.5

EXT_CLK

One of two GPIO_STD I/Os can be used to provide an external clock input of up to 80 MHz. This clock can be used

as the source clock for either the PLL or FLL, or can be used directly by the CLK_HF domain.

3.2.3.6

ECO

The ECO provides high-frequency clocking using an external crystal connected to the ECO_IN and ECO_OUT pins.

It supports fundamental mode (non-overtone) quartz crystals, in the range of 3.988 to 33.34 MHz. When used in

conjunction with the PLL, it generates CPU and peripheral clocks up to device’s maximum frequency. ECO

accuracy depends on the selected crystal. If the ECO is disabled, the associated pins can be used for any of the

available I/O functions.

3.2.3.7

WCO

The WCO is a low-power, watch-crystal oscillator intended for real-time-clock applications. It requires an external

32.768-kHz crystal connected to the WCO_IN and WCO_OUT pins. The WCO can also be configured as a clock

reference for CLK_LF, which is the clock source for the MCWDT and RTC.

Note

6. Operation of reference-timed peripherals (like a UART) with an FLL-based reference is not recommended due the allowed frequency

error.

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TRAVEO™ T2G 32-bit Automotive MCU

Based on Arm® Cortex®-M4F single

Functional description

3.2.4

Reset

CYT2B9 can be reset from a variety of sources, including software. Reset events are asynchronous and guarantee

reversion to a known state. The reset cause (POR, BOD, OVD, overcurrent, XRES_L, WDT, MCWDT, software reset,

fault, CSV, Hibernate wakeup, debug) is recorded in a register, which is sticky through reset and allows software

to determine the cause of the reset. An XRES_L pin is available for external reset.

3.2.5

Watchdog timers

CYT2B9 has one watchdog timer (WDT) and two multi-counter watchdog timers (MCWDT).

The WDT is a free-running counter clocked only by ILO0, which allows it to be used as a wakeup source from

Hibernate. This allows watchdog operation during all power modes and needs to be serviced during a configured

window, otherwise generates a watchdog reset, if not serviced before the timeout occurs. A watchdog reset is

recorded in the Reset Cause register.

An MCWDT is available for each of the CPU cores. These timers provide more capabilities than the WDT, and are

only available in the Active, Sleep, and DeepSleep modes. These timers have multiple counters that can be used

separately or cascaded to trigger interrupts and/or resets. They are clocked from ILO0 or the WCO.

3.2.6

Power modes

CYT2B9 has six different power modes:

• Active – All peripherals are available

• Low-Power Active (LPACTIVE) – Low-power profile of Active mode where all peripherals and the CPUs are

available, but with limited capability

• Sleep – All peripherals except the CPUs are available

• Low-Power Sleep (LPSLEEP) – Low-power profile of Sleep mode where all peripherals except the CPUs are

available, but with limited capability

• DeepSleep – Only peripherals which work with CLK_LF are available

• Hibernate – the device and I/O states are frozen, the device resets on wakeup

3.3

Peripherals

3.3.1

Peripheral clock dividers

Integer and fractional clock dividers are provided for peripheral and timing purposes.

Table 3-1

Clock dividers

Count

Divider

div_8

div_16

Description

32

16

8

Integer divider, 8 bits

Integer divider, 16 bits

Fractional divider, 24.5 bits (24 integer bits, 5 fractional bits)

div_24_5

3.3.2

Peripheral protection unit

The Peripheral Protection Unit (PPU) controls and monitors unauthorized access from all masters (CPU,

P-/M-DMA, Crypto, and any enabled debug interface) to the peripherals. It allows or restricts data transfers on the

bus infrastructure. The access rules are enforced based on specific properties of a transfer, such as an address

range for the transfer and access attributes (such as read/write, user/privilege, and secure/non-secure).

Datasheet

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TRAVEO™ T2G 32-bit Automotive MCU

Based on Arm® Cortex®-M4F single

Functional description

3.3.3

12-bit SAR ADC

CYT2B9 contains three 1-Msps SAR ADCs. These ADCs can be clocked at up to 26.67 MHz and provide a 12-bit result

in 26 clock cycles.

The references for all three SAR ADCs comes from a dedicated pair of inputs: VREFH and VREFL^[7]

.

CYT2B9 devices support up to 85 logical ADC channels, and external inputs from up to 67 I/Os. Each ADC also

supports six internal connections for diagnostic and monitoring purposes. The number of ADC channels (per ADC

and package type) are listed in Table 1-1.

Each ADC has a sequencer, which autonomously cycles through the configured channels (sequencer scan) with

zero-switching overhead (that is, the aggregate sampling bandwidth, when clocked at 26.67 MHz, is equal to 1

Msps whether it is for a single channel or distributed over several channels). The sequencer switching is

controlled through a state machine or firmware. The sequencer prioritizes trigger requests, enables the

appropriate analog channel, controls ADC sampling, initiates ADC data conversion, manages results, and initiates

subsequent conversions for repetitive or group conversions without CPU intervention.

Each SAR ADC has an analog multiplexer used to connect the signals to be measured to the ADC. It has 32

GPIO_STD inputs, one special GPIO_STD input for motor-sense, and six additional inputs to measure internal

signals such as a band-gap reference, a temperature sensor, and power supplies. The device supports

synchronous sampling of one motor-sense channel on each of the three ADCs.

CYT2B9 has one temperature sensor that is shared by all three ADCs. The temperature sensor must only be

sampled by one ADC at a time. Software post processing is required to convert the temperature sensor reading

into kelvin or Celsius values.

To accommodate signals with varying source impedances and frequencies, it is possible to have different sample

times programmed for each channel. Each ADC also supports range comparison, which allows fast detection of

out-of-range values without having to wait for a sequencer scan to complete and for the CPU firmware to evaluate

the measurement for out-of-range values.

The ADCs are not usable in DeepSleep and Hibernate modes as they require a high-speed clock. The ADC input

reference voltage VREFH range is 2.7 V to V_DDAand VREFL is V_SSA

.

3.3.4

Timer/counter/PWM block (TCPWM)

The TCPWM block consists of 16-bit (75 channels) and 32-bit (eight channels) counters with user-programmable

period. Twelve of the 16-bit counters include extra features to support motor control operations. Each TCPWM

counter contains a capture register to record the count at the time of an event, a period register (used to either

stop or auto-reload the counter when its count is equal to the period register), and compare registers to generate

signals that are used as PWM duty-cycle outputs.

Each counter within the TCPWM block supports several functional modes such as timer, capture, quadrature,

PWM, PWM with dead-time insertion (PWM_DT, 8-bit), pseudo-random PWM (PWM_PR), and shift-register.

In motor-control applications, the counter within the TCPWM block supports enhanced quadrature mode with

features such as asymmetric PWM generation, dead-time insertion (16-bit), and association of different dead

times for PWM output signals.

The TCPWM block also provides true and complement outputs, with programmable offset between them, to

allow their use as deadband complementary PWM outputs. The TCPWM block also has a kill input (only for the

PWM mode) to force outputs to a predetermined state; for example, this may be used in motor-drive systems

when an overcurrent state is detected and the PWMs driving the FETs need to be shut off immediately (no time

for software intervention).

Note

7. VREF_L prevents IR drops in the VSSIO and VSSA paths from impacting the measurements. VREF_L, when properly connected, reduces

or removes the impact of IR drops in the VSSIO and VSSA paths from measurements.

Datasheet

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TRAVEO™ T2G 32-bit Automotive MCU

Based on Arm® Cortex®-M4F single

Functional description

3.3.5

Serial communication blocks (SCB)

CYT2B9 contains eight serial communication blocks, each configurable to support I²C, UART, or SPI.

• I²C interface

An SCB can be configured to implement a full I²C master (capable of multi-master arbitration) or slave

interface. Each SCB configured for I²C can operate at speeds of up to 1 Mbps (Fast-mode Plus^[8]) and has

flexible buffering options to reduce the interrupt overhead and latency of the CPU. In addition, each SCB

supports FIFO buffering for receive and transmit data, which, by increasing the time for the CPU to read the

data, reduces the need for clock stretching. The I²C interface is compatible with Standard, Fast-mode, and

Fast-mode Plus devices as specified in the NXP I²C-bus specification and user manual (UM10204). The I²C-bus

I/O is implemented with GPIO in open-drain modes^{[9, 10]}

.

• UART interface

When configured as a UART, each SCB provides a full-featured UART with maximum signaling rate determined

by the configured peripheral-clock frequency and over-sampling rate. It supports infrared interface (IrDA) and

SmartCard (ISO 7816) protocols, which are minor variants of the UART protocol. It also supports the 9-bit

multiprocessor mode that allows the addressing of peripherals connected over common Rx and Tx lines.

Common UART functions such as parity, number of stop bits, break detect, and frame error are supported.

FIFO buffering of transmit and receive data allows greater CPU service latencies to be tolerated.

The LIN protocol is supported by the UART. LIN is based on a single-master multi-slave topology. There is one

master node and multiple slave nodes on the LIN bus. The SCB UART supports only LIN slave functionality.

Compared to the dedicated LIN blocks, an SCB/UART used for LIN requires a higher level of software

interaction and increased CPU load.

• SPI interface

The SPI configuration supports full Motorola SPI, TI Synchronous Serial Protocol (SSP, essentially adds a start

pulse that is used to synchronize SPI-based codecs), and National Microwire (a half-duplex form of SPI). The

SPI interface can use the FIFO. The SPI interface operates with up to a 12.5-MHz SPI Clock. SCB also supports

EZSPI^[11]mode.

SCB0 supports the following additional features:

• Operable as a slave in DeepSleep mode

• I²C slave EZ (EZI2C^[12]) mode with up to 256-B data buffer for multi-byte communication without CPU

intervention

• I²C slave externally-clocked operations

• Command/response mode with a 512-B data buffer for multi-byte communication without CPU intervention

3.3.6

CAN FD

CYT2B9 supports two CAN FD controller blocks, each supporting four CAN FD channel. All CAN FD controllers are

compliant with the ISO 11898-1:2015 standard; an ISO 16845:2015 certificate is available. It also implements the

time-triggered CAN (TTCAN) protocol specified in ISO 11898-4 (TTCAN protocol levels 1 and 2) completely in

hardware. All functions concerning the handling of messages are implemented by the Rx and Tx handlers. The Rx

handler manages message acceptance filtering, transfer of received messages from the CAN core to a message

RAM, and provides receive-message status. The Tx handler is responsible for the transfer of transmit messages

from the message RAM, to the CAN core, and provides transmit-message status.

Notes

8. I/Os drive level does not support the full bus capacitance in Fast-mode Plus speeds.

9. This is not 100 percent compliant with the I²C-bus specification; I/Os are not high-voltage compliant, do not support the 20-mA sink

requirement of Fast-mode Plus, and violate the leakage specification when no power is applied.

10.Only Port 0 with the slow feature enabled meets the minimum fall time requirement.

11.The Easy SPI (EZSPI) protocol is based on the Motorola SPI operating in any mode (0, 1, 2, or 3). It allows communication between

master and slave, and reduces the need for CPU intervention.

12.The Easy I²C (EZI2C) protocol is a unique communication scheme built on top of the I²C protocol by Infineon. It uses a meta protocol

around the standard I²C protocol to communicate to an I²C slave using indexed memory transfers. This reduces the need for CPU

intervention.

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TRAVEO™ T2G 32-bit Automotive MCU

Based on Arm® Cortex®-M4F single

Functional description

3.3.7

Local interconnect network (LIN)

CYT2B9 contains up to 12 LIN channels. Each channel supports transmission/reception of data following the LIN

protocol according to ISO standard 17987. Each LIN channel connects to an external transceiver through a 3-pin

interface (including an enable function) and supports master and slave functionality. Each channel also supports

classic and enhanced checksum, along with break detection during message reception and wake-up signaling.

Break detection, sync field, checksum calculations, and error interrupts are handled in hardware.

3.3.8

Clock extension peripheral interface (CXPI)

CYT2B9 contains up to four CXPI channels compliant with JASO D015 and ISO standard 20794 including the

controller specification.

Each channel supports:

• Master and slave functionality

• Polling and event trigger method for both normal and long frames

• Non-return to zero (NRZ) and PWM signaling modes

• Collision resolution and carries sense multiple access

• Wakeup pulse generation and detection

• CRC8 and CRC16 for both normal and long frames

• Error detection

• Dedicated FIFO (16 B) for transmit and receive

3.3.9

One-time-programmable (OTP) eFuse

CYT2B9 devices contain a 1024-bit OTP eFuse memory that can be used to store and access a unique and

unalterable identifier or serial number for each device. eFuses are also used to control the device life-cycle

(manufacturing, programming, normal operation, end-of-life, and so on) and the security state. Of the 1024 bits,

192 are available for user purposes.

3.3.10

Event generator

The event generator supports generation of interrupts and triggers in the Active mode and interrupts in the

DeepSleep mode. The event generators are used to trigger a specific device function (execution of an interrupt

handler, a SAR ADC conversion, and so on) and to provide a cyclic wakeup mechanism from the DeepSleep mode.

They provide CPU-free triggers for device functions, and reduce CPU involvement in triggering device functions,

thus reducing overall power consumption and processing overhead.

3.3.11

Trigger multiplexer

CYT2B9 supports connecting various peripherals using trigger signals. Triggers are used to inform a peripheral of

the occurrence of an event or change of state. These triggers are used to affect or initiate some action in other

peripherals. The trigger multiplexer is used to route triggers from a source peripheral to a destination. Triggers

provide active logic functionality and are typically supported in the Active mode.

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TRAVEO™ T2G 32-bit Automotive MCU

Based on Arm® Cortex®-M4F single

Functional description

3.4

I/Os

CYT2B9 has up to 152 programmable I/Os.

The I/Os are organized as logical entities called ports, which are a maximum of 8 bits wide. During power-on, and

reset, the I/Os are forced to the High-Z state. During the Hibernate mode, I/Os are frozen.

Every I/O can generate an interrupt (if enabled) and each port has an interrupt request (IRQ) and interrupt service

routine (ISR) associated with it.

The I/O port power source mapping is listed in Table 3-2. The associated supply determines the V_OH, V_OL, V_IH, and

V_ILlevels when configured for CMOS and Automotive thresholds.

Table 3-2

Supply

I/O port power source

Ports

VDDD

VDDIO_1

VDDIO_2

P0, P1, P2, P3, P4, P5, P16, P17, P18, P19, P20, P21, P22, P23

P6, P7, P8, P9^[13]

P10, P11, P12, P13, P14, P15

3.4.1

Port nomenclature

Px.y describes a particular bit “y” available within an I/O port “x.”

For example, P4.2 reads “port 4, bit 2”.

Each I/O implements the following:

• Programmable drive mode

- High impedance

- Resistive pull-up

- Resistive pull-down

- Open drain with strong pull-down

- Open drain with strong pull-up

- Strong pull-up or pull-down

- Weak pull-up or pull-down

CYT2B9 has two types of programmable I/Os: GPIO Standard and GPIO Enhanced.

3.4.2

GPIO Standard (GPIO_STD)

Supports standard automotive signaling across the 2.7-V to 5.5-V V_DDIOrange. GPIO Standard I/Os have multiple

configurable drive levels, drive modes, and selectable input levels.

3.4.3

GPIO Enhanced (GPIO_ENH)

Supports extended functionality automotive signaling across the 2.7-V to 5.5-V V_DDIOrange with higher currents

at lower voltages (full I²C timing support, slew-rate control).

Both GPIO_STD and GPIO_ENH implement the following:

• Configurable input threshold (CMOS, TTL, or Automotive)

• Hold mode for latching previous state (used for retaining the I/O state in DeepSleep mode)

• Analog input mode (input and output buffers disabled)

Note

13.The I/Os in VDDIO_1 domain refer to the VDDD domain in 64-LQFP package.

Datasheet

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TRAVEO™ T2G 32-bit Automotive MCU

Based on Arm® Cortex®-M4F single

Functional description

3.4.4

Smart I/O

Smart I/O allows Boolean operations on signals going to the I/O from the subsystems of the chip or on signals

coming into the chip. CYT2B9 has five Smart I/O blocks. Operation can be synchronous or asynchronous and the

blocks operate in all device power modes except for the Hibernate mode.

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CYT2B9 address map

4

CYT2B9 address map

The CYT2B9 microcontroller supports the memory spaces shown in Figure 4-1:

• 2112 KB (1984 KB + 128 KB) of code-flash, used in the single- or dual-bank mode based on the associated bit in

the flash control register

- Single-bank mode - 2112 KB

- Dual-bank mode - 1056 KB per bank

• 128 KB (96 KB + 32 KB) of work-flash, used in the single- or dual-bank mode based on the associated bit in the

flash control register

- Single-bank mode - 128 KB

- Dual-bank mode - 64 KB per bank

• 32 KB of secure ROM

• 256 KB of SRAM (First 2 KB is reserved for internal usage)

0xFFFF FFFF

Arm System

CPU & Debug Registers

Space

0xE000 0000

Reserved

0x43FF FFFF

Peripheral

Interconnect or

Memory map

Mainly used for on-chip peripherals

e.g., AHB or APB Peripherals

0x4000 0000

Reserved

Alternate Flash

Supervisory Region

0x1780 7FFF

0x1780 0000

Used to store manufacture specific

data like flash protection settings, trim

settings, device addresses, serial numbers,

calibration data, etc.

32 KB

Reserved

32 KB

Flash Supervisory

Region

0x1700 7FFF

0x1700 0000

Reserved

0x1401 FFFF

32 KB

(128 B Small Sectors)

Work flash used for long

term data retention

0x1401 8000

0x1401 7FFF

Work flash

96 KB

(2 KB Large Sectors)

0x1400 0000

0x1020 FFFF

Reserved

128 KB

(8 KB Small Sectors)

0x101F 0000

0x101E FFFF

Mainly used for user program code

Code flash

1984 KB

(32 KB Large Sectors)

0x1000 0000

0x0803 FFFF

Reserved

128 KB

SRAM1

SRAM0

General purpose RAM,

mainly used for data

0x0802 0000

0x0801 FFFF

126 KB

0x0800 0800

0x0800 0000

2 KB

Secured Boot ROM to set user specified

protection levels, trim and configuration

data, code authentication, jump to user mode etc.

Reserved

32 KB

0x0000 7FFF

0x0000 0000

ROM

Figure 4-1

CYT2B9 address map^{[14, 15]}

Notes

14.The size representation is not up to scale.

15.First 2KB of SRAM is reserved, not available for users. User must keep the power of first 32KB block of SRAM0 in enabled or retained in

all Active, LP Active, Sleep, LP Sleep, DeepSleep modes.

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Flash base address map

5

Flash base address map

Table 5-1 through Table 5-6 give information about the sector mapping of the code- and work-flash regions

along with their respective base addresses.

Table 5-1

Code-flash Address Mapping in Single Bank Mode

Large Sectors Small Sectors

Code-flashSize(KB)

Large Sector Base Address

Small Sector Base Address

(LS)

(SS)

2112

32 KB × 62

8 KB × 16

0x1000 0000

0x101F 0000

Table 5-2

Work-flash Address Mapping in Single Bank Mode

Work-flash Size (KB) Large Sectors Small Sectors

128 2 KB × 48 128 B × 256

Large Sector Base Address

Small Sector Base Address

0x1400 0000

0x1401 8000

Table 5-3

Code-flash Address Mapping in Dual Bank Mode (Mapping A)

Second

Half

Second

Half SS

Base

First Half

LS Base

Address

First Half

Code-flash

Size (KB)

First

Second

Half LS

Second

Half SS

SS Base

Address

Half LS

Half SS

LS Base

Address

2112

32 KB × 31

8KB × 8

32 KB × 31

8 KB × 8 0x1000 0000 0x100F 8000 0x1200 0000 0x120F 8000

Table 5-4

Code-flash Address Mapping in Dual Bank Mode (Mapping B)

Second

Half

Second

Half SS

Base

First Half

LS Base

Address

First Half

Code-flash

Size (KB)

First

Second

Half LS

Second

Half SS

SS Base

Address

Half LS

Half SS

LS Base

Address

2112

32 KB × 31

8 KB × 8

32 KB × 31

8 KB × 8 0x1200 0000 0x120F 8000 0x1000 0000 0x100F 8000

Table 5-5

Work-flash Address Mapping in Dual Bank Mode (Mapping A)

Second

Half

Second

Half SS

Base

First Half

LS Base

Address

First Half

Work-flash

Size (KB)

First

Second

Half LS

Second

Half SS

SS Base

Address

Half LS

Half SS

LS Base

Address

128

2 KB × 24 128 B × 128 2 KB × 24 128 B × 128 0x1400 0000 0x1400 C000 0x1500 0000 0x1500 C000

Table 5-6

Work-flash Address Mapping in Dual Bank Mode (Mapping B)

Second

Half

Second

Half SS

Base

First Half

LS Base

Address

First Half

SS Base

Address

Work-flash

Size (KB)

First

Second

Half LS

Second

Half SS

Half LS

Half SS

LS Base

Address

128

2 KB × 24 128 B × 128 2 KB × 24 128 B × 128 0x1500 0000 0x1500 C000 0x1400 0000 0x1400 C000

Datasheet

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Peripheral I/O map

6

Peripheral I/O map

CYT2B9 Peripheral I/O Map

Description

Table 6-1

Base

Instance

Size

Section

Instances

Group Slave

Address

Peripheral interconnect

Peripheral group (0, 1, 2, 3, 5, 6, 9)

Peripheral trigger group

Peripheral 1:1 trigger group

Peripheral interconnect, master interface

PERI Programmable PPU

PERI Fixed PPU

Cryptography component

CPU subsystem (CPUSS)

Fault structure subsystem

Fault structures

0x4000 0000

0x4000 4000

0x4000 8000

0x4000 C000

0x4001 0000

0x4001 0800

0x4010 0000

0x4020 0000

0x4021 0000

0x4022 0000

0x4022 1000

0x4023 0000

7

11

0x20

0x400

PERI

0

PERI_MS

6^[16]

487

0x40

0

1

Crypto

CPUSS

1

2

0

FAULT

2

1

4

0x100

Inter process communication

IPC structures

IPC interrupt structures

Protection

IPC

8

0x20

2

PROT

Shared memory protection unit structures 0x4023 2000

16

0x40

0x400

2

3

4

Memory protection unit structures

Flash controller

0x4023 4000

0x4024 0000

FLASHC

System Resources Sub-System Core

Registers

0x4026 0000

Clock Supervision High Frequency

Clock Supervision Reference Frequency

Clock Supervision Low Frequency

Clock Supervision Internal Low Frequency 0x4026 1730

Multi Counter WDT

Free Running WDT

SRSS Backup Domain/RTC

Backup Register

P-DMA0 Controller

P-DMA0 channel structures

P-DMA1 Controller

P-DMA1 channel structures

M-DMA0 Controller

M-DMA0 channels

eFuse Customer Data (192 bits)

High-Speed I/O Matrix (HSIOM)

GPIO port control/configuration

0x4026 1400

0x4026 1710

0x4026 1720

3

1

2

1

0x10

SRSS

2

5

0x4026 8000

0x4026 C000

0x4027 0000

0x4027 1000

0x4028 0000

0x4028 8000

0x4029 0000

0x4029 8000

0x402A 0000

0x402A 1000

0x402C 0868

0x4030 0000

0x4031 0000

0x100

BACKUP

P-DMA

2

6

7

8

9

4

0x04

0x40

92

44

M-DMA

4

6

24

0x100

0x04

0x10

0x80

eFuse

HSIOM

GPIO

2

3

10

0

1

Note

16.These six Programmable PPUs are configured by the Boot ROM and are available for the user based on the access

rights. Refer to the device specific TRM to know more about the configuration of these programmable PPUs.

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Peripheral I/O map

Table 6-1

Section

CYT2B9 Peripheral I/O Map (continued)

Base

Instance

Size

Description

Instances

Group Slave

Address

Programmable I/O configuration

SMART I/O port configuration

Timer/Counter/PWM 0 (TCPWM0)

TCPWM0 Group #0 (16-bit)

TCPWM0 Group #1 (16-bit, Motor control)

TCPWM0 Group #2 (32-bit)

Event generator 0 (EVTGEN0)

Event generator 0 comparator structures

Local Interconnect Network 0 (LIN0)

LIN0 Channels

0x4032 0000

0x4032 0C00

0x4038 0000

0x4038 8000

0x4039 0000

0x403F 0000

0x403F 0800

0x4050 0000

0x4050 8000

SMARTIO

3

2

5

0x100

63

12

4

0x80

TCPWM

3

EVTGEN

LIN

3

5

4

0

11

12

0x20

0x100

Clock Extension Peripheral Interface 0

(CXPI0)

0x4051 0000

CXPI

5

1

2

CXPI0 Channels

CAN0 controller

Message RAM CAN0

CAN1 controller

Message RAM CAN1

0x4051 8000

0x4052 0000

0x4053 0000

0x4054 0000

0x4055 0000

4

0x100

0x200

0x7FFF

0x200

TTCANFD

SCB

4

8

5

6

3

0x7FFF

Serial Communications Block

0x4060 0000

0x10000

0-7

(SPI/UART/I²C)

Programmable Analog Subsystem (PASS0) 0x4090 0000

SAR0 channel controller

SAR1 channel controller

SAR2 channel controller

SAR0 channel structures

SAR1 channel structures

SAR2 channel structures

0x4090 0000

0x4090 1000

0x4090 2000

0x4090 0800

0x4090 1800

0x4090 2800

SAR PASS

9

0

24

32

8

0x40

Datasheet

21

002-22825 Rev. *J

2022-09-08

TRAVEO™ T2G 32-bit Automotive MCU

Based on Arm® Cortex®-M4F single

CYT2B9 clock diagram

7

CYT2B9 clock diagram

IMO

EXT_CLK

ECO

WCO

ILO0

ILO1

LEGEND 1:

LEGEND 2:

ECO

LS

Active Domain

Prescaler

DeepSleep Domain

Hibernate Domain

LS

MUX

LS

MUX

FLL

MUX

PLL

MUX

Relationship of Monitored Clock

and Reference Clock

CLK_ILO0

WDT

RTC

MUX

CLK_BAK

Monitored Clock

CSV

CLK_

PATH0

CLK_

PATH1

CLK_

PATH2

CLK_

PATH3

CLK_REF_HF

CLK_LF

Reference Clock

CLK_ILO0

CSV

MCWDT

LEGEND 3:

MUX

One Clock Line

Multiple Clock Lines

Predivider

(1/2/4/8)

Predivider

(1/2/4/8)

Predivider

(1/2/4/8)

CSV

CLK_ILO0

CLK_LF

CLK_HF2

CSV

CLK_REF_HF

Event Generator

CLK_HF1

CLK_HF0

ROM/SRAM/FLASH

Divider

(1-256)

Divider

(1-256)

CM4

CLK_FAST

CLK_PERI

CPUSS Fast Infrastructure

Divider

(1-256)

CM0+

CLK_SLOW

CPUSS Slow Infrastructure

P-DMA / M-DMA

CRYPTO

PERI

SRSS

Divider

(1-256)

EFUSE

CLK_GR3

CLK_GR5

CPUSS(Trace Clock)

TCK/SWDCLK from a Debugger

Divider

(1-256)

IOSS

TCPWM

CAN FD

LIN

Divider

(1-256)

CXPI

CLK_GR6

CLK_GR9

SCB[*]

SCB[0]

SAR ADC

Serial interface clock

Divider

(1-256)

Peripheral

Clock Dividers

PCLK_CPUSS_CLOCK_TRACE_IN

PCLK_SMARTIO[x]_CLOCK

PCLK_TCPWM[x]_CLOCKS[y]

PCLK_CANFD[x]_CLOCK_CAN[y]

PCLK_LIN_CLOCK_CH_EN[x]

PCLK_CXPI_CLOCK_CH_EN[x]

PCLK_SCB[x]_CLOCK

PCLK_PASS_CLOCK_SAR[x]

Figure 7-1

CYT2B9 clock diagram

Datasheet

22

002-22825 Rev. *J

2022-09-08

TRAVEO™ T2G 32-bit Automotive MCU

Based on Arm® Cortex®-M4F single

CYT2B9 CPU start-up sequence

8

CYT2B9 CPU start-up sequence

The following steps describe the start-up sequence:

1. System Reset (@0x0000 0000)

2. CM0+ executes ROM boot (@0x0000 0004)

i. Applies trims

ii. Applies Debug Access port (DAP) access restrictions and system protection from eFuse and supervisory

flash

iii.Authenticates flash boot (only in SECURE life-cycle stage) and transfers control to it

3. CM0+ executes flash boot (from Supervisory flash @0x1700 2000)

i. Debug pins are configured as per the SWD/JTAG spec^[17]

ii. Sets CM0+ vector offset register (CM0_VTOR part of the Arm® system space) to the beginning of flash

(@0x1000 0000)

iii.CM0+ branches to its Reset handler

4. CM0+ starts execution

i. Moves CM0+ vector table to SRAM (updates CM0+ vector table base)

ii. Sets CM4_VECTOR_TABLE_BASE (@0x0000 0200) to the location of CM4 vector table mentioned in flash

(specified in CM4 linker definition file)

iii.Releases CM4 from reset

iv.Continues execution of CM0+ user application

5. CM4 executes directly from either code-flash or SRAM

i. CM4 branches to its Reset handler

ii. Continues execution of CM4 user application

Note

17.Port configuration of SWD/JTAG pins will be changed from the default GPIO mode to support debugging after the boot process, see

Table 11-1 for pin assignments.

Datasheet

23

002-22825 Rev. *J

2022-09-08

TRAVEO™ T2G 32-bit Automotive MCU

Based on Arm® Cortex®-M4F single

Pin assignment

9

Pin assignment

132

131

130

129

128

127

126

125

124

123

122

121

120

119

118

117

116

115

114

113

112

111

110

109

108

107

106

105

104

103

102

101

100

99

VDDD

P18.7

P18.6

P18.5

P18.4

P18.3

P18.2

P18.1

P18.0

P17.7

P17.6

P17.5

P17.4

P17.3

P17.2

P17.1

P17.0

P16.3

P16.2

P16.1

P16.0

VSSD

VDDD

P15.3

P15.2

P15.1

P15.0

P14.7

P14.6

P14.5

P14.4

P14.3

P14.2

P14.1

P14.0

P13.7

P13.6

P13.5

P13.4

P13.3

P13.2

P13.1

P13.0

VSSD

P0.0

P0.1

P0.2

P0.3

P1.0

P1.1

P1.2

P1.3

P2.0

P2.1

P2.2

P2.3

P2.4

P2.5

P3.0

P3.1

P3.2

P3.3

P3.4

P3.5

VDDD

VSSD

P4.0

P4.1

P4.2

P4.3

P4.4

P5.0

P5.1

P5.2

P5.3

P5.4

P5.5

P6.0

P6.1

P6.2

P6.3

P6.4

P6.5

P6.6

P6.7

VDDD

VDDIO_1

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

176-LQFP

98

97

96

95

94

93

92

91

90

89

Figure 9-1

176-LQFP pin assignment

Datasheet

24

002-22825 Rev. *J

2022-09-08

TRAVEO™ T2G 32-bit Automotive MCU

Based on Arm® Cortex®-M4F single

Pin assignment

VSSD

PWM0_18/PWM0_22_N/TC0_18_TR0/TC0_22_TR1/SCB0_RX (0)/SCB7_SDA (2)/SCB0_MISO (0)/LIN1_RX P0.0

PWM0_17/PWM0_18_N/TC0_17_TR0/TC0_18_TR1/SCB0_TX (0)/SCB7_SCL (2)/SCB0_MOSI (0)/LIN1_TX P0.1

PWM0_14/PWM0_17_N/TC0_14_TR0/TC0_17_TR1/SCB0_RTS (0)/SCB0_SCL (0)/SCB0_CLK (0)/LIN1_EN/CAN0_1_TX P0.2

PWM0_13/PWM0_14_N/TC0_13_TR0/TC0_14_TR1/SCB0_CTS (0)/SCB0_SDA (0)/SCB0_SEL0 (0)/CAN0_1_RX P0.3

PWM0_12/PWM0_13_N/TC0_12_TR0/TC0_13_TR1/PWM0_H_4/SCB0_SCL (1)/SCB0_MISO (1) P1.0

PWM0_11/PWM0_12_N/TC0_11_TR0/TC0_12_TR1/PWM0_H_5/SCB0_SDA (1)/SCB0_MOSI (1) P1.1

PWM0_10/PWM0_11_N/TC0_10_TR0/TC0_11_TR1/PWM0_H_6/SCB0_CLK (1)/TRIG_IN[0] P1.2

PWM0_8/PWM0_10_N/TC0_8_TR0/TC0_10_TR1/PWM0_H_7/SCB0_SEL0 (1)/TRIG_IN[1] P1.3

PWM0_7/PWM0_8_N/TC0_7_TR0/TC0_8_TR1/TC0_H_4_TR0/SCB7_RX (0)/SCB0_SEL1 (0)/SCB7_MISO (0)/LIN0_RX/CAN0_0_TX/SWJ_TRSTN/TRIG_IN[2] P2.0

PWM0_6/PWM0_7_N/TC0_6_TR0/TC0_7_TR1/TC0_H_5_TR0/SCB7_TX (0)/SCB7_SDA (0)/SCB0_SEL2 (0)/SCB7_MOSI (0)/LIN0_TX/CAN0_0_RX/TRIG_IN[3] P2.1

PWM0_5/PWM0_6_N/TC0_5_TR0/TC0_6_TR1/TC0_H_6_TR0/SCB7_RTS (0)/SCB7_SCL (0)/SCB0_SEL3 (0)/SCB7_CLK (0)/LIN0_EN/TRIG_IN[4] P2.2

PWM0_4/PWM0_5_N/TC0_4_TR0/TC0_5_TR1/TC0_H_7_TR0/SCB7_CTS (0)/SCB7_SEL0 (0)/LIN5_RX/TRIG_IN[5] P2.3

PWM0_3/PWM0_4_N/TC0_3_TR0/TC0_4_TR1/PWM0_H_4_N/SCB7_SEL1 (0)/LIN5_TX/TRIG_IN[6] P2.4

PWM0_2/PWM0_3_N/TC0_2_TR0/TC0_3_TR1/PWM0_H_5_N/SCB7_SEL2 (0)/LIN5_EN/TRIG_IN[7] P2.5

PWM0_1/PWM0_2_N/TC0_1_TR0/TC0_2_TR1/PWM0_H_6_N/SCB6_RX (0)/SCB6_MISO (0)/CAN0_3_TX/TRIG_DBG[0] P3.0

PWM0_0/PWM0_1_N/TC0_0_TR0/TC0_1_TR1/PWM0_H_7_N/SCB6_TX (0)/SCB6_SDA (0)/SCB6_MOSI (0)/CAN0_3_RX/TRIG_DBG[1] P3.1

PWM0_M_3/PWM0_0_N/TC0_M_3_TR0/TC0_0_TR1/TC0_H_4_TR1/SCB6_RTS (0)/SCB6_SCL (0)/SCB6_CLK (0) P3.2

PWM0_M_2/PWM0_M_3_N/TC0_M_2_TR0/TC0_M_3_TR1/TC0_H_5_TR1/SCB6_CTS (0)/SCB6_SEL0 (0) P3.3

PWM0_M_1/PWM0_M_2_N/TC0_M_1_TR0/TC0_M_2_TR1/TC0_H_6_TR1/SCB6_SEL1 (0) P3.4

PWM0_M_0/PWM0_M_1_N/TC0_M_0_TR0/TC0_M_1_TR1/TC0_H_7_TR1/SCB6_SEL2 (0) P3.5

VDDD

1

132

131

130

129

128

127

126

125

124

123

122

121

120

119

118

117

116

115

114

113

112

111

110

109

108

107

106

105

104

103

102

101

100

99

VDDD

2

P18.7 PWM0_50/PWM0_51_N/TC0_50_TR0/TC0_51_TR1/PWM0_H_3_N/CAN1_2_RX/TRACE_DATA_3 (0)/ADC[2]_7

P18.6 PWM0_51/PWM0_52_N/TC0_51_TR0/TC0_52_TR1/PWM0_H_3/SCB1_SEL3 (0)/CAN1_2_TX/TRACE_DATA_2 (0)/ADC[2]_6

P18.5 PWM0_52/PWM0_53_N/TC0_52_TR0/TC0_53_TR1/PWM0_H_2_N/SCB1_SEL2 (0)/TRACE_DATA_1 (0)/ADC[2]_5

P18.4 PWM0_53/PWM0_54_N/TC0_53_TR0/TC0_54_TR1/PWM0_H_2/SCB1_SEL1 (0)/TRACE_DATA_0 (0)/ADC[2]_4

P18.3 PWM0_54/PWM0_55_N/TC0_54_TR0/TC0_55_TR1/PWM0_H_1_N/SCB1_CTS (0)/SCB1_SEL0 (0)/TRACE_CLOCK (0)/ADC[2]_3

P18.2 PWM0_55/PWM0_M_7_N/TC0_55_TR0/TC0_M_7_TR1/PWM0_H_1/SCB1_RTS (0)/SCB1_SCL (0)/SCB1_CLK (0)/ADC[2]_2

P18.1 PWM0_M_7/PWM0_M_6_N/TC0_M_7_TR0/TC0_M_6_TR1/PWM0_H_0_N/SCB1_TX (0)/SCB1_SDA (0)/SCB1_MOSI (0)/FAULT_OUT_1/ADC[2]_1

P18.0 PWM0_M_6/PWM0_M_5_N/TC0_M_6_TR0/TC0_M_5_TR1/PWM0_H_0/SCB1_RX (0)/SCB1_MISO (0)/FAULT_OUT_0/ADC[2]_0

P17.7 PWM0_M_5/PWM0_M_4_N/TC0_M_5_TR0/TC0_M_4_TR1

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

P17.6 PWM0_M_4/PWM0_56_N/TC0_M_4_TR0/TC0_56_TR1/SCB3_SEL2 (1)

P17.5 PWM0_56/PWM0_57_N/TC0_56_TR0/TC0_57_TR1/SCB3_SEL1 (1)

P17.4 PWM0_57/PWM0_58_N/TC0_57_TR0/TC0_58_TR1/PWM0_H_3_N/SCB3_CTS (1)/SCB3_SEL0 (1)/TRIG_IN[27]

P17.3 PWM0_58/PWM0_59_N/TC0_58_TR0/TC0_59_TR1/PWM0_H_3/SCB3_RTS (1)/SCB3_SCL (1)/SCB3_CLK (1)/TRIG_IN[26]

P17.2 PWM0_59/PWM0_60_N/TC0_59_TR0/TC0_60_TR1/PWM0_H_2_N/SCB3_TX (1)/SCB3_SDA (1)/SCB3_MOSI (1)

P17.1 PWM0_60/PWM0_61_N/TC0_60_TR0/TC0_61_TR1/PWM0_H_2/SCB3_RX (1)/SCB3_MISO (1)/CAN1_1_RX

P17.0 PWM0_61/PWM0_62_N/TC0_61_TR0/TC0_62_TR1/CAN1_1_TX

P16.3 PWM0_62/PWM0_62_N/TC0_62_TR0/TC0_62_TR1/PWM0_H_1_N

P16.2 PWM0_62/PWM0_61_N/TC0_62_TR0/TC0_61_TR1/PWM0_H_1/LIN11_EN

P16.1 PWM0_61/PWM0_60_N/TC0_61_TR0/TC0_60_TR1/PWM0_H_0_N/LIN11_TX

P16.0 PWM0_60/PWM0_59_N/TC0_60_TR0/TC0_59_TR1/PWM0_H_0/LIN11_RX

VSSD

VDDD

176-TEQFP

PWM0_4/PWM0_M_0_N/TC0_4_TR0/TC0_M_0_TR1/EXT_MUX[0]_0/SCB5_RX (0)/SCB5_MISO (0)/LIN1_RX/TRIG_IN[10] P4.0

PWM0_5/PWM0_4_N/TC0_5_TR0/TC0_4_TR1/EXT_MUX[0]_1/SCB5_TX (0)/SCB5_SDA (0)/SCB5_MOSI (0)/LIN1_TX/TRIG_IN[11] P4.1

PWM0_6/PWM0_5_N/TC0_6_TR0/TC0_5_TR1/EXT_MUX[0]_2/SCB5_RTS (0)/SCB5_SCL (0)/SCB5_CLK (0)/LIN1_EN/TRIG_IN[12] P4.2

PWM0_7/PWM0_6_N/TC0_7_TR0/TC0_6_TR1/EXT_MUX[0]_EN/SCB5_CTS (0)/SCB5_SEL0 (0)/CAN0_1_TX/TRIG_IN[13] P4.3

PWM0_8/PWM0_7_N/TC0_8_TR0/TC0_7_TR1/SCB5_SEL1 (0)/CAN0_1_RX P4.4

P15.3 PWM0_59/PWM0_58_N/TC0_59_TR0/TC0_58_TR1/TC0_H_7_TR1/ADC[1]_31

P15.2 PWM0_58/PWM0_57_N/TC0_58_TR0/TC0_57_TR1/TC0_H_7_TR0/CXPI1_EN/ADC[1]_30

P15.1 PWM0_57/PWM0_56_N/TC0_57_TR0/TC0_56_TR1/TC0_H_6_TR1/CAN1_3_RX/CXPI1_TX/ADC[1]_29

P15.0 PWM0_56/PWM0_55_N/TC0_56_TR0/TC0_55_TR1/TC0_H_6_TR0/CAN1_3_TX/CXPI1_RX/ADC[1]_28

P14.7 PWM0_55/PWM0_54_N/TC0_55_TR0/TC0_54_TR1/TC0_H_5_TR1/CXPI2_EN/TRIG_IN[25]/ADC[1]_27

P14.6 PWM0_54/PWM0_53_N/TC0_54_TR0/TC0_53_TR1/TC0_H_5_TR0/CXPI2_TX/TRIG_IN[24]/ADC[1]_26

P14.5 PWM0_53/PWM0_52_N/TC0_53_TR0/TC0_52_TR1/TC0_H_4_TR1/SCB2_SEL2 (0)/CXPI2_RX/ADC[1]_25

P14.4 PWM0_52/PWM0_51_N/TC0_52_TR0/TC0_51_TR1/TC0_H_4_TR0/SCB2_SEL1 (0)/LIN6_EN/ADC[1]_24

P14.3 PWM0_51/PWM0_50_N/TC0_51_TR0/TC0_50_TR1/PWM0_H_7_N/SCB2_CTS (0)/SCB2_SEL0 (0)/LIN6_TX/ADC[1]_23

P14.2 PWM0_50/PWM0_49_N/TC0_50_TR0/TC0_49_TR1/PWM0_H_7/SCB2_RTS (0)/SCB2_SCL (0)/SCB2_CLK (0)/LIN6_RX/ADC[1]_22

P14.1 PWM0_49/PWM0_48_N/TC0_49_TR0/TC0_48_TR1/PWM0_H_6_N/SCB2_TX (0)/SCB2_SDA (0)/SCB2_MOSI (0)/CAN1_0_RX/ADC[1]_21

P14.0 PWM0_48/PWM0_47_N/TC0_48_TR0/TC0_47_TR1/PWM0_H_6/SCB2_RX (0)/SCB2_MISO (0)/CAN1_0_TX/ADC[1]_20

P13.7 PWM0_47/PWM0_M_11_N/TC0_47_TR0/TC0_M_11_TR1/PWM0_H_5_N/CXPI2_EN/TRIG_IN[23]/ADC[1]_19

P13.6 PWM0_M_11/PWM0_46_N/TC0_M_11_TR0/TC0_46_TR1/PWM0_H_5/SCB3_SEL3 (0)/LIN8_EN/CXPI2_TX/TRIG_IN[22]/ADC[1]_18

P13.5 PWM0_46/PWM0_M_10_N/TC0_46_TR0/TC0_M_10_TR1/PWM0_H_4_N/SCB3_SEL2 (0)/LIN8_TX/CXPI2_RX/ADC[1]_17

P13.4 PWM0_M_10/PWM0_45_N/TC0_M_10_TR0/TC0_45_TR1/PWM0_H_4/SCB3_SEL1 (0)/LIN8_RX/ADC[1]_16

P13.3 PWM0_45/PWM0_M_9_N/TC0_45_TR0/TC0_M_9_TR1/EXT_MUX[2]_EN/SCB3_CTS (0)/SCB3_SEL0 (0)/ADC[1]_15

P13.2 PWM0_M_9/PWM0_44_N/TC0_M_9_TR0/TC0_44_TR1/EXT_MUX[2]_2/SCB3_RTS (0)/SCB3_SCL (0)/SCB3_CLK (0)/LIN3_EN/CXPI1_EN/ADC[1]_14

P13.1 PWM0_44/PWM0_M_8_N/TC0_44_TR0/TC0_M_8_TR1/EXT_MUX[2]_1/SCB3_TX (0)/SCB3_SDA (0)/SCB3_MOSI (0)/LIN3_TX/CXPI1_TX/ADC[1]_13

P13.0 PWM0_M_8/PWM0_43_N/TC0_M_8_TR0/TC0_43_TR1/EXT_MUX[2]_0/SCB3_RX (0)/SCB3_MISO (0)/LIN3_RX/CXPI1_RX/ADC[1]_12

VSSD

PWM0_9/PWM0_8_N/TC0_9_TR0/TC0_8_TR1/SCB5_SEL2 (0)/LIN7_RX P5.0

PWM0_10/PWM0_9_N/TC0_10_TR0/TC0_9_TR1/LIN7_TX P5.1

PWM0_11/PWM0_10_N/TC0_11_TR0/TC0_10_TR1/LIN7_EN P5.2

PWM0_12/PWM0_11_N/TC0_12_TR0/TC0_11_TR1/LIN2_RX P5.3

PWM0_13/PWM0_12_N/TC0_13_TR0/TC0_12_TR1/LIN2_TX P5.4

PWM0_14/PWM0_13_N/TC0_14_TR0/TC0_13_TR1/LIN2_EN P5.5

PWM0_M_0/PWM0_14_N/TC0_M_0_TR0/TC0_14_TR1/SCB4_RX (0)/SCB4_MISO (0)/LIN3_RX/ADC[0]_0 P6.0

PWM0_0/PWM0_M_0_N/TC0_0_TR0/TC0_M_0_TR1/SCB4_TX (0)/SCB4_SDA (0)/SCB4_MOSI (0)/LIN3_TX/ADC[0]_1 P6.1

PWM0_M_1/PWM0_0_N/TC0_M_1_TR0/TC0_0_TR1/SCB4_RTS (0)/SCB4_SCL (0)/SCB4_CLK (0)/LIN3_EN/CAN0_2_TX/ADC[0]_2 P6.2

PWM0_1/PWM0_M_1_N/TC0_1_TR0/TC0_M_1_TR1/SCB4_CTS (0)/SCB4_SEL0 (0)/LIN4_RX/CAN0_2_RX/CAL_SUP_NZ/ADC[0]_3 P6.3

PWM0_M_2/PWM0_1_N/TC0_M_2_TR0/TC0_1_TR1/SCB4_SEL1 (0)/LIN4_TX/ADC[0]_4 P6.4

PWM0_2/PWM0_M_2_N/TC0_2_TR0/TC0_M_2_TR1/SCB4_SEL2 (0)/LIN4_EN/ADC[0]_5 P6.5

PWM0_M_3/PWM0_2_N/TC0_M_3_TR0/TC0_2_TR1/SCB4_SEL3 (0)/TRIG_IN[8]/ADC[0]_6 P6.6

PWM0_3/PWM0_M_3_N/TC0_3_TR0/TC0_M_3_TR1/TRIG_IN[9]/ADC[0]_7 P6.7

98

97

96

95

94

93

92

91

VDDD

90

VDDIO_1

89

Figure 9-2

176-LQFP pin assignment with alternate functions

Datasheet

25

002-22825 Rev. *J

2022-09-08

TRAVEO™ T2G 32-bit Automotive MCU

Based on Arm® Cortex®-M4F single

Pin assignment

VSSD

P0.0

P0.1

P0.2

P0.3

P1.0

P1.1

P2.0

P2.1

P2.2

P2.3

P2.4

P3.0

P3.1

P3.2

P3.3

P3.4

VDDD

VSSD

P4.0

P4.1

P5.0

P5.1

P5.2

P5.3

P5.4

P6.0

P6.1

P6.2

P6.3

P6.4

P6.5

P6.6

P6.7

VDDD

VDDIO_1

1

108

107

106

105

104

103

102

101

100

99

VDDD

P18.7

P18.6

P18.5

P18.4

P18.3

P18.2

P18.1

P18.0

P17.4

P17.3

P17.2

P17.1

P17.0

P16.2

P16.1

P16.0

P15.3

P15.2

P15.1

P15.0

P14.5

P14.4

P14.3

P14.2

P14.1

P14.0

P13.7

P13.6

P13.5

P13.4

P13.3

P13.2

P13.1

P13.0

VSSD

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

98

97

96

95

94

93

92

91

144-LQFP

90

89

88

87

86

85

84

83

82

81

80

79

78

77

76

75

74

73

Figure 9-3

144-LQFP pin assignment