CYT4BFCCHDQ0BZSGS [INFINEON]
TRAVEO™ T2G CYT4BF Series;
| 型号： | CYT4BFCCHDQ0BZSGS |
| 厂家： | 
Infineon |
| 描述： | TRAVEO™ T2G CYT4BF Series |
| 文件： | 总218页 (文件大小：2570K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CYT4BF
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
General description
CYT4BF is a family of TRAVEO™ T2G microcontrollers targeted at automotive systems such as high-end
body-control units. CYT4BF has two Arm® Cortex®-M7 CPUs for primary processing, and an Arm® Cortex®-M0+ CPU
for peripheral and security processing. These devices contain embedded peripherals supporting Controller Area
Network with Flexible Data rate (CAN FD), Local Interconnect Network (LIN), Gigabit Ethernet, and FlexRay.
TRAVEO™ T2G devices are manufactured on an advanced 40-nm process. CYT4BF incorporates a low-power flash
memory, multiple high-performance analog and digital peripherals, and enables the creation of a secure
computing platform.
Features
• CPU subsystem
- Two 350-MHz 32-bit Arm® Cortex®-M7 CPUs, each with
• Single-cycle multiply
• Single/double-precision floating point unit (FPU)
• 16-KB data cache, 16-KB instruction cache
• Memory protection unit (MPU)
• 16-KB instruction and 16-KB data tightly-coupled memories (TCM)
- 100-MHz 32-bit Arm® Cortex® M0+ CPU with
• Single-cycle multiply
• Memory protection unit (MPU)
- Inter-processor communication in hardware
- Three DMA controllers
• Peripheral DMA controller #0 (P-DMA0) with 143 channels
• Peripheral DMA controller #1 (P-DMA1) with 65 channels
• Memory DMA controller (M-DMA0) with 8 channels
• Integrated memories
- 8384 KB of code-flash with an additional 256 KB of work-flash
• Read-While-Write (RWW) allows updating the code-flash/work-flash while executing from it
• Single- and dual-bank modes (specifically for Firmware update Over The Air [FOTA])
• Flash programming through SWD/JTAG interface
- 1024-KB of SRAM with selectable retention granularity
• Cryptography engine
- Supports Enhanced Secure Hardware Extension (eSHE) and Hardware Security Module (HSM)
- Secure boot and authentication
• Using digital signature verification
• Using fast secure boot
- AES: 128-bit blocks, 128-/192-/256-bit keys
- 3DES: 64-bit blocks, 64-bit key
- Vector unit supporting asymmetric key cryptography such as Rivest-Shamir-Adleman (RSA) and Elliptic Curve
(ECC)
- SHA-1/2/3: SHA-512, SHA-256, SHA-160 with variable length input data
- CRC: supports CCITT CRC16 and IEEE-802.3 CRC32
- True random number generator (TRNG) and pseudo random number generator (PRNG)
- Galois/Counter Mode (GCM)
Datasheet
www.infineon.com
Please read the Important Notice and Warnings at the end of this document
page1
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Features
• Functional safety for ASIL-B
- Memory protection unit (MPU)
- Shared memory protection unit (SMPU)
- Peripheral protection unit (PPU)
- Watchdog timer (WDT)
- Multi-counter watchdog timer (MCWDT)
- Low-voltage detector (LVD)
- Brown-out detection (BOD)
- Over-voltage detection (OVD)
- Clock supervisor (CSV)
- Hardware error correction (SECDED ECC) on all safety-critical memories (SRAM, flash, TCM)
• Low-Power 2.7-V to 5.5-V operation
- Low-power Active, Sleep, Low-power Sleep, DeepSleep, and Hibernate modes for fine-grained power
management
- Configurable options for robust BOD
• Two threshold levels (2.7 V and 3.0 V) for BOD on VDDD and VDDA
• One threshold level (1.1 V) for BOD on VCCD
• Wakeup
- Up to two pins to wake from Hibernate mode
- Up to 240 GPIO pins to wake from Sleep modes
- Event Generator, SCB, watchdog timer, RTC alarms to wake from DeepSleep modes
• Clocks
- Internal main oscillator (IMO)
- Internal low-speed oscillator (ILO)
- External crystal oscillator (ECO)
- Watch crystal oscillator (WCO)
- Phase-locked loop (PLL)
- Frequency-locked loop (FLL)
• Communication interfaces
- Up to 10 CAN FD channels
• Increased data rate (up to 8 Mbps) compared to classic CAN, limited by physical layer topology and
transceivers
• Compliant to ISO 11898-1:2015
• Supports all the requirements of Bosch CAN FD Specification V1.0 for non-ISO CAN FD
• ISO 16845:2015 certificate available
- Up to 11 runtime-reconfigurable SCB (serial communication block) channels, each configurable as I2C, SPI,
or UART
- Up to 20 independent LIN channels
• LIN protocol compliant with ISO 17987
- Up to two 10/100/1000 Mbps Ethernet MAC interfaces conforming to IEEE-802.3az
• Supports the following PHY interfaces:
Media-independent interface (MII)
Reduced media-independent interface (RMII)
Gigabit media-independent interface (GMII)
Reduced gigabit media-independent interface (RGMII)
• Compliant with IEEE-802.1BA Audio Video Bridging (AVB)
• Compliant with IEEE-1588 Precision Time Protocol (PTP)
- FlexRay interface (V2.1) configurable for single or dual data-channels for fault tolerance, supporting data rates
up to 10 Mbps
Datasheet
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Based on Arm® Cortex®-M7 dual
Features
• External memory interface
- One SPI (single, dual, quad, or octal) or HYPERBUS™ interface
- On-the-fly encryption and decryption
- Execute-In-Place (XIP) from external memory
• SDHC interface
- One Secure Digital High Capacity (SDHC) interface supporting embedded MultiMediaCard (eMMC), Secure
Digital (SD), or SDIO (Secure Digital Input Output)
• Compliant to eMMC 5.1, SD 6.0, and SDIO 4.10 specifications
- Data rates up to SD High Speed 50 MHz, or eMMC 52 MHz DDR
• Audio interface
- Three Inter-IC Sound (I2S) Interfaces for connecting digital audio devices
- I2S, left justified, or time division multiplexed (TDM) audio formats
- Independent transmit or receive operation, each in master or slave mode
• Timers
- Up to 102 16-bit and 16 32-bit timer/counter pulse-width modulator (TCPWM) blocks
• Up to 15 16-bit counters for motor control
• Up to 87 16-bit counters and 16 32-bit counters for regular operations
• Supports timer, capture, quadrature decoding, pulse-width modulation (PWM), PWM with dead time
(PWM_DT), pseudo-random PWM (PWM_PR), and shift-register (SR) modes
- Up to 16 Event Generation (EVTGEN) timers supporting cyclic wakeup from DeepSleep
• Events trigger a specific device operation (such as execution of an interrupt handler, a SAR ADC conversion,
and so on)
• Real time clock (RTC)
- Year/Month/Date, Day-of-week, Hour:Minute:Second fields
- 12- and 24-hour formats
- Automatic leap-year correction
• I/O
- Up to 240 programmable I/Os
- Three I/O types
• GPIO Standard (GPIO_STD)
• GPIO Enhanced (GPIO_ENH)
• High-Speed I/O Standard (HSIO_STD)
• Regulators
- Generates a 1.1-V nominal core supply from a 2.7-V to 5.5-V input supply
- Three regulators:
• DeepSleep
• Core internal
• Core external
• Programmable analog
- Three SAR A/D converters with up to 99 external channels (96 I/Os + 3 I/Os for motor control)
• Each ADC supports 32 logical channels, with 32 + 1 physical connections. Any external channel can be
connected to any logical channel in the respective SAR.
- Each ADC supports 12-bit resolution and sampling rates of up to 1 Msps
- Each ADC also supports six internal analog inputs like
• Bandgap reference to establish absolute voltage levels
• Calibrated diode for junction temperature calculations
• Two AMUXBUS inputs and two direct connections to monitor supply levels
Datasheet
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Features
- Each ADC supports addressing of external multiplexers
- Each ADC has a sequencer supporting autonomous scanning of configured channels
- Synchronized sampling of all ADCs for motor-sense applications
• Smart I/O
- Up to five Smart I/O blocks, which can perform Boolean operations on signals going to and from I/Os
- Up to 36 I/Os (GPIO_STD) supported
• Debug interface
- JTAG controller and interface compliant to IEEE-1149.1-2001
- Arm® SWD (serial wire debug) port
- Supports Arm® Embedded Trace Macrocell (ETM) Trace
• Data trace using SWD
• Instruction and data trace using JTAG
• Compatible with industry-standard tools
- GHS MULTI or IAR EWARM for code development and debugging
• Packages
- 176-TEQFP, 24 × 24 × 1.7 mm (max), 0.5-mm lead pitch
- 272-BGA, 16 × 16 × 1.7 mm (max), 0.8-mm ball pitch
- 320-BGA, 17 × 17 × 1.7 mm (max), 0.8-mm ball pitch
Datasheet
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Table of contents
Table of contents
General description ...........................................................................................................................1
Features ...........................................................................................................................................1
Table of contents...............................................................................................................................5
1 Features list ...................................................................................................................................6
1.1 Communication peripheral instance list ...............................................................................................................8
2 Blocks and functionality..................................................................................................................9
Architecture block diagram ................................................................................................................9
3 Functional description ..................................................................................................................10
3.1 CPU subsystem .....................................................................................................................................................10
3.1.1 CPU .....................................................................................................................................................................10
3.1.2 DMA controllers..................................................................................................................................................10
3.1.3 Flash ...................................................................................................................................................................10
3.1.4 SRAM...................................................................................................................................................................10
3.1.5 ROM ....................................................................................................................................................................10
3.1.6 Cryptography accelerator for security..............................................................................................................10
3.2 System resources..................................................................................................................................................11
3.2.1 Power system.....................................................................................................................................................11
3.2.2 Regulators ..........................................................................................................................................................11
3.2.3 Clock system ......................................................................................................................................................13
3.2.4 Reset ...................................................................................................................................................................14
3.2.5 Watchdog timer..................................................................................................................................................14
3.2.6 Power modes .....................................................................................................................................................14
3.3 Peripherals ............................................................................................................................................................15
3.3.1 Peripheral clock dividers ...................................................................................................................................15
3.3.2 Peripheral protection unit.................................................................................................................................15
3.3.3 12-bit SAR ADC ...................................................................................................................................................15
3.3.4 Timer/counter/PWM (TCPWM) block ................................................................................................................16
3.3.5 Serial communication blocks (SCB)..................................................................................................................16
3.3.6 CAN FD ................................................................................................................................................................17
3.3.7 Local interconnect network (LIN) .....................................................................................................................17
3.3.8 FlexRay interface................................................................................................................................................17
3.3.9 Ethernet MAC......................................................................................................................................................17
3.3.10 External memory interface..............................................................................................................................17
3.3.11 SDHC interface .................................................................................................................................................18
3.3.12 Audio interface.................................................................................................................................................18
3.3.13 One-time-programmable (OTP) eFuse ...........................................................................................................18
3.3.14 Event generator ...............................................................................................................................................18
3.3.15 Trigger multiplexer ..........................................................................................................................................18
3.4 I/Os.........................................................................................................................................................................18
3.4.1 Port nomenclature.............................................................................................................................................19
3.4.2 GPIO Standard (GPIO_STD)...............................................................................................................................19
3.4.3 GPIO Enhanced (GPIO_ENH) .............................................................................................................................19
3.4.4 HSIO Standard (HSIO_STD)...............................................................................................................................19
3.4.5 Smart I/O ............................................................................................................................................................19
4 CYT4BF address map .....................................................................................................................20
5 Flash base address map.................................................................................................................22
6 Peripheral I/O map........................................................................................................................23
7 CYT4BF clock diagram ...................................................................................................................25
8 CYT4BF CPU start-up sequence ......................................................................................................26
9 Pin assignment .............................................................................................................................27
10 High-speed I/O matrix connections...............................................................................................31
Datasheet
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Table of contents
11 Package pin list and alternate functions .......................................................................................32
12 Power pin assignments................................................................................................................40
13 Alternate function pin assignments ..............................................................................................41
13.1 Pin function description .....................................................................................................................................50
14 Interrupts and wake-up assignments............................................................................................53
15 Core interrupt types....................................................................................................................66
16 Trigger multiplexer .....................................................................................................................67
17 Triggers group inputs ..................................................................................................................68
18 Triggers group outputs................................................................................................................73
19 Triggers one-to-one.....................................................................................................................74
20 Peripheral clocks ........................................................................................................................80
21 Faults.........................................................................................................................................85
22 Peripheral protection unit fixed structure pairs.............................................................................88
23 Bus masters.............................................................................................................................. 104
24 Miscellaneous configuration ...................................................................................................... 105
25 Development support................................................................................................................ 107
25.1 Documentation .................................................................................................................................................107
25.1.1 Software User Guide ......................................................................................................................................107
25.1.2 Technical Reference Manual .........................................................................................................................107
25.2 Tools ..................................................................................................................................................................107
26 Electrical specifications............................................................................................................. 108
26.1 Absolute maximum ratings ..............................................................................................................................108
26.2 Device-level specifications ...............................................................................................................................112
26.3 DC specifications...............................................................................................................................................113
26.4 Reset specifications ..........................................................................................................................................118
26.5 I/O ......................................................................................................................................................................120
26.6 Analog peripherals............................................................................................................................................126
26.6.1 SAR ADC..........................................................................................................................................................126
26.6.2 Calculating the impact of neighboring pins .................................................................................................127
26.6.3 Temperature sensor ......................................................................................................................................131
26.6.4 Voltage divider accuracy ...............................................................................................................................131
26.7 AC specifications...............................................................................................................................................132
26.8 Digital peripherals.............................................................................................................................................133
26.9 Memory..............................................................................................................................................................144
26.10 System resources............................................................................................................................................146
26.10.1 SWD interface ..............................................................................................................................................158
26.11 Clock specifications ........................................................................................................................................160
26.12 Clock timing diagrams..................................................................................................................................169
26.13 Ethernet specifications...................................................................................................................................171
26.14 SDHC specifications........................................................................................................................................176
26.15 FlexRay specifications ....................................................................................................................................181
26.16 Audio subsystem specifications.....................................................................................................................182
26.17 Serial memory interface specifications .........................................................................................................188
27 Ordering information ................................................................................................................ 195
27.1 Part number nomenclature..............................................................................................................................196
28 Packaging ................................................................................................................................ 198
29 Appendix.................................................................................................................................. 203
29.1 Bootloading or end-of-line programming .......................................................................................................203
29.2 External IP revisions..........................................................................................................................................205
30 Acronyms ................................................................................................................................. 206
31 Errata ...................................................................................................................................... 208
Datasheet
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Table of contents
Revision history ............................................................................................................................ 214
Revision history change log............................................................................................................ 216
Datasheet
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Features list
1
Features list
Table 1-1
CYT4BF feature list for all packages
Packages
272-BGA
Features
176-TEQFP
320-BGA
CPU
Core
Two 32-bit Arm® Cortex®-M7 CPUs and a 32-bit Arm® Cortex® M0+ CPU
Functional safety
Operating voltage
Operating voltage for HSIO_STD
Core voltage
ASIL-B
2.7 V to 5.5 V
2.7 V to 3.6 V
1.05 V to 1.15 V
Not supported
Arm® Cortex®-M7 350 MHz (max for each) and Arm® Cortex®-M0+ 100
MHz (max)
Operating frequency
MPU, PPU
Supported
FPU
Supports both single (32-bit) and double (64-bit) precision
Supported by Arm® Cortex®-M7 CPUs
DSP-MUL/DIV/MAC
TCM
16-KB instruction and 16-KB data for each Cortex®-M7 CPU
Memory
Code-flash
Work-flash
SRAM (configurable for retention)
ROM
8384 KB (8128 KB + 256 KB)
256 KB (192 KB + 64 KB)
1024 KB
64 KB
Communication interfaces
CAN0 (CAN-FD: Up to 8 Mbps)
CAN1 (CAN-FD: Up to 8 Mbps)
CAN RAM
5 ch
5 ch
40 KB per instance (5 ch), 80 KB in total
Serial communication block (SCB/UART)
Serial communication block (SCB/I2C)
Serial communication block (SCB/SPI)
LIN
10 ch
10 ch
10 ch
11 ch
11 ch
11 ch
20 ch
17 ch
1 ch × 10/100
2 ch (option) × 10/100/1000
ETH0: MII/RMII on
GPIO_STD,
ETH1: MII/RMII/GMII/
RGMII on HSIO_STD
ETH0: MII/RMII on
GPIO_STD,
Ethernet MAC
ETH0: MII/RMII on
GPIO_STD
ETH1: RGMII on
HSIO_STD
ETH0: RGMII on
HSIO_STD,
ETH1: RGMII on
HSIO_STD
FlexRay
1 interface of FlexRay supporting ch A and ch B (option)
Memory interfaces
eMMC/SD
SingleSPI/DualSPI/QuadSPI/OctalSPI
/ HYPERBUS™
1 ch (GPIO_STD at 26 MHz)
1 ch (GPIO_STD at 32 MHz)
1 ch (HSIO_STD at 50 MHz, GPIO_STD at 26 MHz)
1 ch (HSIO_STD at 100 MHz, GPIO_STD at 32 MHz)
Datasheet
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Features list
Table 1-1
CYT4BF feature list for all packages (continued)
Packages
272-BGA
Features
176-TEQFP
320-BGA
Timers
RTC
1 ch
TCPWM (16-bit) (Motor control)
TCPWM (16-bit)
TCPWM (32-bit)
External interrupts
Analog
15 ch (TCPWM0/3, TCPWM1/12)
87 ch (TCPWM0/3, TCPWM1/84)
16 ch (TCPWM0/3, TCPWM1/13)
220
148
240
3 Units (SAR0/32, SAR1/32, SAR2/32 logical channels)
81 external channels
(SAR0/24 ch,
96 external channels
12-bit, 1 Msps SAR ADC
SAR1/32 ch, SAR2/25
ch)
(each SAR supports 32 ch)
18 ch (6 per ADC) Internal sampling
Motor Control Input
3 ch (synchronous sampling of one channel on each of the 3 ADCs)
Security
Flash security (program/work read pro-
tection)
Supported
Flash chip erase enable
eSHE / HSM
Audio
Configurable
By separate firmware[1]
I2S / TDM
Tx 3 ch, Rx 3 ch
System
P-DMA0 with 143 channels (16 general purpose), P-DMA1 with 65
channels (8 general purpose), and M-DMA0 with 8 channels
DMA controller
Internal Main Oscillator
8 MHz
Internal Low speed Oscillator
32.768 kHz (nominal)
PLL
FLL
Input: 3.988 to 33.34 MHz, PLL output: up to 350 MHz
Input: 0.25 to 80 MHz, FLL output: up to 100 MHz
Watchdog Timer and Multi-counter
Watchdog Timer
Supported
Clock Supervisor
Cyclic wakeup from DeepSleep
GPIO_STD
Supported
Supported
144
187
4
191
45
GPIO_ENH
HSIO_STD
Not supported
29
Smart I/O (Blocks)
Low-voltage detect
Maximum ambient temperature
5 blocks, mapped through 36 I/Os
Two, 26 selectable levels
105 °C for S-grade, 125 °C for E-grade
Note
1. Enhanced Secure Hardware Extension (eSHE) and Hardware Security Module (HSM) support are enabled by third-party firmware.
Datasheet
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Based on Arm® Cortex®-M7 dual
Features list
Table 1-1
CYT4BF feature list for all packages (continued)
Features
Packages
272-BGA
SWD/JTAG
176-TEQFP
320-BGA
Debug interface
Debug trace
Arm® Cortex®-M7 ETB size of 8 KB, Arm® Cortex® M0+ MTB size of 4 KB
1.1
Communication peripheral instance list
The following table lists the instances supported under each package for communication peripherals, based on
the minimum pins needed for the functionality.
Table 1-2
Module
CAN0
CAN1
LIN0
SCB/UART
SCB/I2C
SCB/SPI
Communication peripheral instance list
176-TEQFP
0/1/2/3/4
0/1/2/3/4
0 to 16
272-BGA
0/1/2/3/4
0/1/2/3/4
0 to 19
320-BGA
0/1/2/3/4
0/1/2/3/4
0 to 19
0 to 10
0 to 10
Minimum pin functions
TX, RX
TX, RX
TX, RX
TX, RX
0 to 9
0 to 10
0 to 9
0 to 10
SCL, SDA
MISO, MOSI, SCK, SELECT0
0 to 9
0 to 10
0 to 10
Datasheet
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TRAVEO™ T2G 32-bit Automotive MCU
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Blocks and functionality
2
Blocks and functionality
Architecture block diagram
ITCM
DTCM
CPU Subsystem
ITCM
16 KB
DTCM
CYT4BF
MXS40-HT
ASIL-B
16 KB
SWJ/ETM/ITM/CTI
SWJ/MTB/CTI
eCT FLASH
8384 KB Code-flash
+ 256 KB Work-flash
SRAM0
512 KB
SRAM1
SRAM2
256 KB
CRYPTO
Arm
Cortex M0+
100 MHz
Arm Cortex M7
ROM
64 KB
AES,SHA,CRC,
TRNG,RSA,ECC
256 KB
350 MHz
B
D$I$
BS
FPU
SRAM
Controller
SRAM
Controller
SRAM
Controller
(SP/DP)
8 KB $
FLASH Controller
System Resources
16 KB
16 KB
AHBS
Initiator/MMIO
ROM Controller
MUL, NVIC, MPU
NVIC, MPU, AXI
AHBP
Power
Sleep Control
POR
OVD
BOD
LVD
System Interconnect (Multi Layer AXI/AHB, IPC, MPU/SMPU)
Peripheral Interconnect (MMIO,PPU)
REF
PWRSYS-HT
LDO
PCLK
Clock
Clock Control
Prog.
Analog
2xILO
WDT
ECO
CSV
IMO
FLL
SAR
ADC
(12-bit)
4xPLL
Reset
Reset Control
XRES
Test
TestMode Entry
x3
Digital DFT
Analog DFT
SARMUX
96 ch
WCO
RTC
Power Modes
High-Speed I/O Matrix, Smart I/O, Boundary Scan
5x Smart IO
Active/Sleep
LowePowerActive/Sleep
Up to 191x GPIO_STD, 4x GPIO_ENH, 45x HSIO_STD
DeepSleep
Hibernate
I/O Subsystem
The Architecture block diagram shows the CYT4BF architecture, giving a simplified view of the interconnection
between subsystems and blocks. CYT4BF has four major subsystems: CPU, system resources, peripherals, and
I/O[2, 3, 4]. The color-coding shows the lowest power mode where the particular block is still functional.
CYT4BF provides extensive support for programming, testing, debugging, and tracing of both hardware and
firmware.
Debug-on-chip functionality enables in-system debugging using the production device. It does not require
special interfaces, debugging pods, simulators, or emulators.
The JTAG interface is fully compatible with industry-standard third-party probes such as I-jet, J-Link, and GHS.
The debug circuits are enabled by default.
CYT4BF provides a high level of security with robust flash protection and the ability to disable features such as
debug.
Additionally, each device interface can be permanently disabled for applications concerned with phishing
attacks from a maliciously reprogrammed device or attempts to defeat security by starting and interrupting flash
programming sequences. All programming, debug, and test interfaces are disabled when maximum device
security is enabled.
Notes
2. GPIO_STD supports 2.7 V to 5.5 V VDDIO range.
3. GPIO_ENH supports 2.7 V to 5.5 V VDDIO range with higher currents at lower voltages.
4. HSIO_STD supports 2.7 V to 3.6 V VDDIO range with high-speed signalling and programmable drive strength.
Datasheet
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Based on Arm® Cortex®-M7 dual
Functional description
3
Functional description
CPU subsystem
CPU
3.1
3.1.1
The CYT4BF CPU subsystem contains a 32-bit Arm® Cortex®-M0+ CPU with MPU, and two 32-bit Arm® Cortex®-M7
CPUs, each with MPU, single/double-precision FPU, and 16-KB data and instruction caches. This subsystem also
includes P-/M-DMA controllers, a cryptographic accelerator, 8384 KB of code-flash, 256 KB of work-flash, 1024 KB
of SRAM, and 64 KB of ROM.
The Cortex-M0+ CPU provides a secure, un-interruptible boot function. This guarantees that, following
completion of the boot function, system integrity is valid and privileges are enforced. Shared resources (flash,
SRAM, peripherals, and so on) can be accessed through bus arbitration, and exclusive accesses are supported by
an inter-processor communication (IPC) mechanism using hardware semaphores.
Each Cortex-M7 CPU has 16 KB of instruction and 16 KB of data TCM with programmable read wait states. Each
TCM is clocked by the associated Cortex-M7 CPU clock.
3.1.2
DMA controllers
CYT4BF has three DMA controllers: P-DMA0 with 16 general purpose and 127 dedicated channels, P-DMA1 with 8
general purpose and 57 dedicated channels, and M-DMA0 with eight channels. P-DMA is used for
peripheral-to-memory and memory-to-peripheral data transfers and provides low latency for a large number of
channels. Each P-DMA controller uses a single data-transfer engine that is shared by the associated channels.
General purpose channels have a rich interconnect matrix including P-DMA cross triggering which enables
demanding data-transfer scenarios. Dedicated channels have a single triggering input (such as an ADC channel)
to handle common transfer needs. M-DMA is used for memory-to-memory data transfers and provides high
memory bandwidth for a small number of channels. M-DMA uses a dedicated data-transfer engine for each
channel. They support independent accesses to peripherals using the AHB multi-layer bus.
3.1.3
Flash
CYT4BF has 8384 KB (8128 KB with a 32-KB sector size, and 256 KB with an 8-KB sector size) of code-flash with an
additional work-flash of 256 KB (192 KB with a 2-KB sector size, and 64 KB with a 128-B sector size). Work-flash is
optimized for reprogramming many more times than code-flash. Code-flash supports Read-While-Write (RWW)
operation allowing flash to be updated while the CPU is active. Both the code-flash and work-flash areas support
dual-bank operation for over-the-air (OTA) programming.
3.1.4
SRAM
CYT4BF has 1024 KB of SRAM with three independent controllers. SRAM0 provides DeepSleep retention in 32-KB
increments while SRAM1/2 are selectable between fully retained and not retained.
3.1.5
ROM
CYT4BF has 64 KB of ROM that contains boot and configuration routines. This ROM enables secure boot and
authentication of user flash to guarantee a secure system.
3.1.6
Cryptography accelerator for security
The cryptography accelerator implements (3)DES block cipher, AES block cipher, SHA hash, cyclic redundancy
check, pseudo random number generation, true random number generation, galois/counter mode, and a vector
unit to support asymmetric key cryptography such as RSA and ECC.
Datasheet
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Functional description
3.2
System resources
Power system
3.2.1
The power system ensures that the supply voltage levels meet the requirements of each power mode, and
provides a full-system reset when these levels are not valid. Internal power-on reset (POR) guarantees full-chip
reset during the initial power ramp.
Three BOD circuits monitor the external supply voltages (VDDD, VDDA, VCCD). The BOD on VDDD and VCCD is initially
enabled and cannot be disabled. The BOD on VDDA is initially disabled and can be enabled by the user. For the
external supplies VDDD and VDDA, BOD circuits are software-configurable with two settings; a 2.7-V minimum
voltage that is robust for all internal signaling, and a 3.0-V minimum voltage, which is also robust for all I/O
specifications (which are guaranteed at 2.7 V). The BOD on VCCD is provided as a safety measure and is not a
robust detector.
Three over-voltage detection (OVD) circuits are provided for monitoring external supplies (VDDD, VDDA, VCCD), and
overcurrent detection circuits (OCD) for monitoring internal and external regulators. OVD thresholds on VDDD and
VDDA are configurable with two settings; a 5.0-V and 5.5-V maximum voltage.
Two voltage detection circuits are provided to monitor the external supply voltage (VDDD) for falling and rising
levels, each configurable for one of the 26 selectable levels.
All BOD, OVD, and OCD circuits on VDDD and VCCD generate a reset, because these protect the CPUs and fault logic.
The BOD and OVD circuits on VDDA can be configured to generate either a reset, or a fault.
3.2.2
Regulators
CYT4BF contains three regulators that provide power to the low-voltage core transistors: DeepSleep, core
internal, and core external. These regulators accept a 2.7-V to 5.5-V VDDD supply and provide a low-noise 1.1-V
supply to various parts of the device. These regulators are automatically enabled and disabled by hardware and
firmware when switching between power modes. The core internal and core external regulators operate in Active
mode, and provide power to the CPU subsystem and associated peripherals.
3.2.2.1
DeepSleep
The DeepSleep regulator is used to maintain power in a small number of blocks when in DeepSleep mode.
These blocks include the ILO and WDT timers, BOD detector, SCB0, SRAM memories, Smart I/O, and other
configuration memories. The DeepSleep regulator is enabled when in DeepSleep mode, and the core internal
regulator is disabled. It is disabled when XRES_L is asserted (LOW) and when the core internal regulator is
disabled.
3.2.2.2
Core internal
The core internal regulator supports load currents up to 300 mA, and is operational during device start-up
(boot process), and in Active/Sleep modes.
3.2.2.3
Core external[5]
To support worst-case loading, with both M7 CPUs and the M0+ CPU at their maximum clock frequency and all
integrated peripherals operating, a core external regulator is required, capable of load currents up to 600 mA.
While the control and monitor circuits for the core external regulator are internal to CYT4BF, the power
regulating element (NPN pass transistor, PMIC, or LDO) is external. This reduces the overall power dissipation
within the CYT4BF package, while maintaining a well-regulated core supply.
Note
5. When CYT4BF is in Hibernate mode, the GPIO used to control the core external regulator are High-Z. This may require an external
pull-up or pull-down resistor to disable the external regulator and configure it for minimum operating current.
Datasheet
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Functional description
The core external regulator may be implemented with either an external NPN pass transistor, PMIC, or linear
regulator (LDO). Each implementation requires different external components on the PCB, and different
connections to CYT4BF for both regulation and control.
Vpwr
(2.7-5.5V)
10 uF
VDDD
NPN transistor
Emitter Follower
TRAVEOTM T2G
ZXT849K
DRV_VOUT
etc
EXT_PS_CTL0
0.1Ω
1/4W
1%
EXT_PS_CTL1
Core supply rail
VCCD
CS1
Figure 3-1
Sample core external regulator with NPN transistor
2.7V – 5.5V Power rail
VDDD
Vin
Core supply rail
Switching node
VCCD
TRAVEOTM T2G
External
PMIC
CS1
R1
R2
Enable
(EN)
Feedback
DRV_VOUT
VDDD or
EXT_PS_CTL1
(FB)
Power Good
Power Good
(PG)
EXT_PS_CTL0
EXT_PS_CTL1
- PMIC EN pin polarity is HIGH for enable. PMIC PG pin polarity is HIGH for power good.
- If EN pin of PMIC does not have the internal pull-down resistor, an external pull-down resistor must be placed to keep the PMIC disabled during power-on reset.
- See the Electrical Specifications section for more information on CS1
.
- Output voltage setting resistors (R1, R2) are needed according to the selected PMIC.
Figure 3-2
Sample core external regulator with PMIC/LDO
Both the core internal and core external regulators require an external bulk storage capacitor connected to the
VCCD pin. This capacitor provides charge under the dynamic loads of the low-voltage core transistors.
Datasheet
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Functional description
3.2.3
Clock system
The CYT4BF clock system provides clocks to all subsystems that require them, and glitch-free switching between
different clock sources. In addition, the clock system ensures that no metastable conditions occur.
The clock system for CYT4BF consists of the 8-MHz IMO, two ILOs, four watchdog timers, four PLLs, an FLL, five
clock supervisors (CSV), a 8- to 33.34-MHz ECO, and a 32.768-kHz WCO.
The clock system supports three main clock domains: CLK_HF, CLK_SLOW, and CLK_LF.
• CLK_HFx are the Active mode clocks. Each can use any of the high frequency clock sources including IMO,
EXT_CLK, ECO, FLL, or PLL
• CLK_SLOW provides a reference clock for the Cortex®-CM0+ CPU, Crypto, P-/M-DMA, and other slow infra-
structure blocks of CPU subsystem
• CLK_LF is a DeepSleep domain clock and provides a reference clock for the MCWDT or RTC modules. The
reference clock for the CLK_LF domain is either disabled or selectable from ILO0, ILO1, or WCO.
Table 3-1
Name
CLK_HF destinations
Description
CLK_HF0
CLK_HF1
CLK_HF2
CLK_HF3
CLK_HF4
CLK_HF5
CLK_HF6
CPUSS (Memories, CLK_SLOW, Peripherals)
CPUSS (Cortex-M7 CPU 0, 1)
CAN FD, FlexRay, LIN, TCPWM, SCB, SAR
Event Generator
Ethernet Internal Clock
Audio Subsystem (I2S), Ethernet TSU
SDHC Interface, SMIF
3.2.3.1
IMO clock source
The IMO is the frequency reference in CYT4BF when no external reference is available or enabled. The IMO
operates at a frequency of around 8 MHz.
3.2.3.2
ILO clock source
An ILO is a low-power oscillator, nominally 32.768 kHz, which generates clocks for a watchdog timer when in
DeepSleep mode. There are two ILOs to ensure clock supervisor (CSV) capability in DeepSleep mode. ILO-driven
counters can be calibrated to the IMO, WCO, or ECO to improve their accuracy. ILO1 is also used for clock super-
vision.
3.2.3.3
PLL and FLL
A PLL (one of the two 200 MHz and two 400 MHz) or FLL may be used to generate high-speed clocks from the IMO,
ECO, or an EXT_CLK. The FLL provides a much faster lock than the PLL (5 µs instead of 45 µs) in exchange for a
small amount (±2%) of frequency error[6]. The 400-MHz PLL supports spread spectrum clock generation (SSCG)
with down spreading.
3.2.3.4
Clock supervisor
Each clock supervisor (CSV) allows one clock (reference) to supervise the behavior of another clock (monitored).
Each CSV has counters for both the monitored and reference clocks. Parameters for each counter determine the
frequency of the reference clock as well as the upper and lower frequency limits of the monitored clock. If the
frequency range comparator detects a stopped clock or a clock outside the specified frequency range, an
abnormal state is signaled and either a reset or an interrupt is generated.
Note
6. Operation of reference-timed peripherals (like a UART) with an FLL-based reference is not recommended due the allowed frequency error.
Datasheet
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Functional description
3.2.3.5
EXT_CLK
One of three GPIO_STD I/Os can be used to provide an external clock input of up to 80 MHz. This clock can be used
as the source clock for either the PLL or FLL, or can be used directly by the CLK_HF domain.
3.2.3.6
ECO
The ECO provides high-frequency clocking using an external crystal connected to the ECO_IN and ECO_OUT pins.
It supports fundamental mode (non-overtone) quartz crystals, in the range of 8 to 33.34 MHz. When used in
conjunction with the PLL, it generates CPU and peripheral clocks up to device’s maximum frequency. ECO
accuracy depends on the selected crystal. If the ECO is disabled, the associated pins can be used for any of the
available I/O functions.
3.2.3.7
WCO
The WCO is a low-power, watch-crystal oscillator intended for real-time-clock applications. It requires an external
32.768-kHz crystal connected to the WCO_IN and WCO_OUT pins. The WCO can also be configured as a clock
reference for CLK_LF, which is the clock source for the MCWDT and RTC.
3.2.4
Reset
CYT4BF can be reset from a variety of sources, including software. Most reset events are asynchronous and
guarantee reversion to a known state. The reset cause (POR, BOD, OVD, overcurrent, XRES_L, WDT, MCWDT,
software reset, fault, CSV, Hibernate wakeup, debug) is recorded in a register, which is sticky through reset and
allows software to determine the cause of the reset. An XRES_L pin is available for external reset.
3.2.5
Watchdog timer
CYT4BF has one watchdog timer (WDT) and three multi-counter watchdog timers (MCWDT).
The WDT is a free-running counter clocked only by ILO0, which allows it to be used as a wakeup source from
Hibernate. Watchdog operation is possible during all power modes. To prevent a device reset from a WDT
timeout, the WDT must be serviced during a configured window. A watchdog reset is recorded in the reset cause
register.
An MCWDT is available for each of the CPU cores. These timers provide more capabilities than the WDT, and are
only available in Active, Sleep, and DeepSleep modes. These timers have multiple counters that can be used
separately or cascaded to trigger interrupts and/or resets. They are clocked from ILO0 or the WCO.
3.2.6
Power modes
CYT4BF has six power modes.
• Active – all peripherals are available
• Low-Power Active (LPACTIVE) – Low-power profile of Active mode where all peripherals and the CPUs are
available, but with limited capability
• Sleep – all peripherals except the CPUs are available
• Low-Power Sleep (LPSLEEP) – Low-power profile of Sleep mode where all peripherals except the CPUs are
available, but with limited capability
• DeepSleep – only peripherals which work with CLK_LF are available
• Hibernate – the device and I/O states are frozen, the device resets on wakeup
Datasheet
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Functional description
3.3
Peripherals
3.3.1
Peripheral clock dividers
Integer and fractional clock dividers are provided for peripheral and timing purposes.
Table 3-2
Clock dividers - CPUSS Group (Nr. 0)
Divider type
Instances
Description
div_8
div_16
div_24_5
4
3
1
Integer divider, 8 bits
Integer divider, 16 bits
Fractional divider, 24.5 bits (24 integer bits, 5 fractional bits)
Table 3-3
Clock dividers - COMM Group (Nr. 1)
Instances
Divider type
Description
div_8
div_16
div_24_5
19
20
21
Integer divider, 8 bits
Integer divider, 16 bits
Fractional divider, 24.5 bits (24 integer bits, 5 fractional bits)
3.3.2
Peripheral protection unit
The Peripheral Protection Unit (PPU) controls and monitors unauthorized access from all masters (CPU,
P-/M-DMA, CRYPTO, and any enabled debug interface) to the peripherals. It allows or restricts data transfers on
the bus infrastructure. The access rules are enforced based on specific properties of a transfer, such as an address
range for the transfer and access attributes (such as read/write, user/privilege, and secure/non-secure).
3.3.3
12-bit SAR ADC
CYT4BF contains three 1-Msps SAR ADCs. These ADCs can be clocked at up to 26.67 MHz and provide a 12-bit result
in 26 clock cycles. The references for all three SAR ADCs come from a dedicated pair of inputs: VREFH and VREFL[7]
.
CYT4BF supports up to 117 logical ADC channels, and external inputs from up to 99 I/Os. Each ADC also supports
six internal connections for diagnostic and monitoring purposes. The number of ADC channels (per ADC and
package type) are listed in Table 1-1.
Each ADC has a sequencer, which autonomously cycles through the configured channels (sequencer scan) with
zero-switching overhead (that is, the aggregate sampling bandwidth, when clocked at 26.67 MHz, is equal to 1
Msps whether it is for a single channel or distributed over several channels). The sequencer switching is
controlled through a state machine or firmware. The sequencer prioritizes trigger requests, enables the
appropriate analog channel, controls ADC sampling, initiates ADC data conversion, manages results, and initiates
subsequent conversions for repetitive or group conversions without CPU intervention.
Each SAR ADC has an analog multiplexer used to connect the signals to be measured to the ADC. It has 32
GPIO_STD inputs, one special GPIO_STD input for motor-sense, and six additional inputs to measure internal
signals such as a band-gap reference, a temperature sensor, and power supplies. The device supports
synchronous sampling of one motor-sense channel on each of the three ADCs.
CYT4BF has one temperature sensor that is shared by all three ADCs. The temperature sensor must only be
sampled by one ADC at a time. Software post processing is required to convert the temperature sensor reading
into kelvin or Celsius values.
To accommodate signals with varying source impedances and frequencies, you can have different sample times
programmed for each channel. Each ADC also supports range comparison, which allows fast detection of
out-of-range values without having to wait for a sequencer scan to complete and for the CPU firmware to evaluate
the measurement for out-of-range values.
The ADCs are not usable in DeepSleep and Hibernate modes as they require a high-speed clock. The ADC input
reference voltage VREFH range is 2.7 V to VDDA and VREFL is VSSA
.
Note
7. VREF_L prevents IR drops in the VSSIO and VSSA paths from impacting the measurements. VREF_L, when properly connected, reduces
or removes the impact of IR drops in the VSSIO and VSSA paths from measurements.
Datasheet
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2022-10-10
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Functional description
3.3.4
Timer/counter/PWM (TCPWM) block
The TCPWM block consists of 16-bit (102 channels) and 32-bit (16 channels) counters with user-programmable
period. Fifteen of the 16-bit counters are optimized for motor-control operations. Each TCPWM counter contains
a capture register to record the count at the time of an event, a period register (used to either stop or auto-reload
the counter when its count is equal to the period register), and compare registers to generate signals that are
used as PWM duty-cycle outputs.
Each counter within the TCPWM block supports several functional modes such as timer, capture, quadrature,
PWM, PWM with dead-time insertion (PWM_DT, 8-bit), pseudo-random PWM (PWM_PR), and shift-register.
In motor-control applications, the counter within the TCPWM block supports enhanced quadrature mode with
features such as asymmetric PWM generation, dead-time insertion (16-bit), and association of different dead
times for PWM output signals.
The TCPWM block also provides true and complement outputs, with programmable offset between them, to
allow their use as deadband complementary PWM outputs. The TCPWM block also has a kill input (only for the
PWM mode) to force outputs to a predetermined state; for example, this may be used in motor-drive systems
when an overcurrent state is detected and the PWMs driving the FETs need to be shut off immediately (no time
for software intervention).
3.3.5
Serial communication blocks (SCB)
CYT4BF contains 11 serial communication blocks, each configurable to support I2C, UART, or SPI.
3.3.5.1
I2C interface
An SCB can be configured to implement a full I2C master (capable of multi-master arbitration) or slave
interface. Each SCB configured for I2C can operate at speeds of up to 1 Mbps (Fast-mode Plus) and has flexible
buffering options to reduce the interrupt overhead and latency of the CPU. In addition, each SCB supports FIFO
buffering for receive and transmit data, which, by increasing the time for the CPU to read the data, reduces the
need for clock stretching. The I2C interface is compatible with Standard, Fast-mode, and Fast-mode Plus
devices as specified in the NXP I2C-bus specification and user manual (UM10204). The I2C-bus I/O is
implemented with GPIO in open-drain modes[8, 9]
.
3.3.5.2
UART interface
When configured as a UART, each SCB provides a full-featured UART with maximum signalling rate determined
by the configured peripheral-clock frequency and over-sampling rate. It supports infrared interface (IrDA) and
SmartCard (ISO 7816) protocols, which are minor variants of the UART protocol. It also supports the 9-bit
multiprocessor mode that allows the addressing of peripherals connected over common Rx and Tx lines.
Common UART functions such as parity, number of stop bits, break detect, and frame error are supported.
FIFO buffering of transmit and receive data allows greater CPU service latencies to be tolerated.
The LIN protocol is supported by the UART. LIN is based on a single-master multi-slave topology. There is one
master node and multiple slave nodes on the LIN bus. The SCB UART supports only LIN slave functionality.
Compared to the dedicated LIN blocks, an SCB/UART used for LIN requires a higher level of software
interaction and increased CPU load.
3.3.5.3
SPI interface
The SPI configuration supports full Motorola SPI, TI Synchronous Serial Protocol (SSP, essentially adds a start
pulse that is used to synchronize SPI-based codecs), and National Microwire (a half-duplex form of SPI). The
SPI interface can use the FIFO. The SPI interface operates with up to a 12.5-MHz SPI Clock. SCB also supports
EZSPI[9] mode.
Notes
8. This is not 100% compliant with the I2C-bus specification; I/Os are not overvoltage-tolerant, do not support the 20-mA sink require-
ment of Fast-mode Plus, and violate the leakage specification when no power is applied.
9. Only Port 0 with the slew rate control enabled meets the minimum fall time requirement.
10.The Easy SPI (EZSPI) protocol is based on the Motorola SPI protocol operating in any mode (0, 1, 2, or 3). It allows communication
between master and slave while reducing the need for CPU intervention.
Datasheet
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Functional description
SCB0 supports the following additional features:
• Operable as a slave in DeepSleep mode
• I2C slave EZ (EZI2C[11]) mode with up to 256-B data buffer for multi-byte communication without CPU
intervention
• I2C slave externally-clocked operations
• Command/response mode with a 512-B data buffer for multi-byte communication without CPU intervention
3.3.6
CAN FD
CYT4BF contains two CAN FD controller blocks, each supporting five CAN FD channels. All CAN FD controllers are
compliant with the ISO 11898-1:2015 standard; an ISO 16845:2015 certificate is available. It also implements the
time-triggered CAN (TTCAN) protocol specified in ISO 11898-4 (TTCAN protocol levels 1 and 2) completely in
hardware. All functions concerning the handling of messages are implemented by the Rx and Tx handlers. The Rx
handler manages message acceptance filtering, transfer of received messages from the CAN core to a message
RAM, and provides receive-message status. The Tx handler is responsible for the transfer of transmit messages
from the message RAM to the CAN core, and provides transmit-message status.
3.3.7
Local interconnect network (LIN)
CYT4BF contains up to 20 LIN blocks. Each block supports transmission/reception of data following the LIN
protocol according to ISO standard 17987. Each LIN block connects to an external transceiver through a 3-pin
interface (including an enable function) and supports master and slave functionality. Each block also supports
classic and enhanced checksum, along with break detection during message reception and wake-up signaling.
Break detection, sync field, checksum calculations, and error interrupts are handled in hardware.
3.3.8
FlexRay interface
CYT4BF supports one FlexRay interface with channel A and an optional channel B, conforming to FlexRay
protocol specification 2.1, and supports up to a 10-Mbps data rate. Message buffers are configurable as Tx, Rx, or
RXFIFO, and are filtered based on FrameID, cycle count, and message ID.
3.3.9
Ethernet MAC
CYT4BF supports two Ethernet channels with transfer rates of 10, 100, or 1000 Mbps[12]. The input/output frames
and flow control are complaint to the Ethernet/IEEE 802.3az standard and also IEEE-1588 precision-time protocol
(PTP). CYT4BF supports half/full-duplex data transport using external PHY devices. The MAC supports glue-free
connection to PHYs through IEEE standard MII, RMII, GMII, and RGMII interfaces. The device also supports
Audio-Video Bridging (AVB). The MAC supports standard 6-byte programmable addresses.
3.3.10
External memory interface
In addition to the internal flash memory, CYT4BF supports direct connection to as much as 128-MB of external
flash or RAM memory. This connection is made through either a HYPERBUS™ or serial peripheral interface (SPI).
HYPERBUS™ allows connection to HyperFlash and HyperRAM devices, while SPI (single, dual, quad, or octal SPI)
can connect with serial flash memory. Code stored in memory connected through this interface allows
execute-in-place (XIP) operation, which does not require the instructions to be first copied to internal memory,
and on-the-fly encryption and decryption for environments requiring secure external data and code.
Notes
11.The Easy I2C (EZI2C) protocol is a unique communication scheme built on top of the I2C protocol by Cypress. It uses a meta protocol
around the standard I2C protocol to communicate to an I2C slave using indexed memory transfers. This reduces the need for CPU
intervention.
12.Only 10/100 Mbps is available in the 176-TEQFP packaged devices.
Datasheet
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Functional description
3.3.11
SDHC interface
CYT4BF supports one Secure Digital High Capacity (SDHC) interface, which conforms to Secure Digital (SD) 6.0,
Secure Digital Input Output (SDIO) 4.10, and Embedded Multimedia Card (eMMC) 5.1 specifications, along with
Host Control Interface (HCI) 4.2 specification. The interface supports System DMA (SDMA), Advance DMA (ADMA2,
ADMA3), and command queuing (CQ) features. This interface supports data rates of SD DS (Default Speed, 4-bits
at 25 MHz), SD HS (High Speed, 4-bits at 50 MHz, and eMMC 52-MHz DDR (8-bits at 52-MHz card clock).
3.3.12
Audio interface
CYT4BF supports three instances of Inter-IC Sound Bus (I2S) interface to connect to digital audio devices.
Supports I2S Left Justified (LJ), and eight-channel Time Division Multiplexed (TDM) digital audio interface
formats in both master and slave modes with independent operations in receive and transmit directions.
3.3.13
One-time-programmable (OTP) eFuse
CYT4BF contains a 1024-bit OTP eFuse memory that can be used to store and access a unique and unalterable
identifier or serial number for each device. eFuses are also used to control the device life-cycle (manufacturing,
programming, normal operation, end-of-life, and so on) and the security state. Of the 1024 bits, 192 are available
for user purposes.
3.3.14
Event generator
The event generator supports generation of interrupts and triggers in Active mode and interrupts in DeepSleep
mode. The event generators are used to trigger a specific device operation (execution of an interrupt handler, a
SAR ADC conversion, and so on) and to provide a cyclic wakeup mechanism from DeepSleep mode. They provide
CPU-free triggers for device functions, and reduce CPU involvement in triggering device functions, thus reducing
overall power consumption and processing overhead.
3.3.15
Trigger multiplexer
CYT4BF supports connecting various peripherals using trigger signals. Triggers are used to inform a peripheral of
the occurrence of an event or change of state. These triggers are used to affect or initiate some action in other
peripherals. The trigger multiplexer is used to route triggers from a source peripheral to a destination. Triggers
provide active logic functionality and are typically supported in Active mode.
3.4
I/Os
CYT4BF has up to 240 programmable I/Os.
The I/Os are organized as logical entities called ports, which are a maximum of 8 bits wide. During power-on, and
reset, the I/Os are forced to the High-Z state. During the Hibernate mode, I/Os are frozen.
Every I/O can generate an interrupt (if enabled) and each port has an interrupt request (IRQ) and interrupt service
routine (ISR) associated with it.
I/O port power source mapping is listed in Table 3-4. The associated supply determines the VOH, VOL, VIH, and VIL
levels when configured for CMOS and Automotive thresholds.
Table 3-4
I/O port power source
Supply pins
Ports
VDDD
P0, P1, P2, P3, P4, P5, P16, P17, P18, P19, P20, P21, P22, P23, P28, P29, P30, P31
VDDIO_1
VDDIO_2
VDDIO_3
VDDIO_4
P6, P7, P8, P9, P32
P10, P11, P12, P13, P14, P15
P24, P25
P26, P27, P33, P34
Datasheet
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Functional description
3.4.1
Port nomenclature
Px.y describes a particular bit “y” available within an I/O port “x.”
For example, P4.2 reads “port 4, bit 2”.
Each I/O implements the following:
• Programmable drive mode
- High impedance
- Resistive pull-up
- Resistive pull-down
- Open drain with strong pull-down
- Open drain with strong pull-up
- Strong pull-up or pull-down
- Weak pull-up or pull-down
CYT4BF has three types of programmable I/Os: GPIO Standard, GPIO Enhanced, and HSIO Standard.
3.4.2
GPIO Standard (GPIO_STD)
Supports standard automotive signaling across the 2.7-V to 5.5-V VDDIO range. GPIO Standard I/Os have multiple
configurable drive levels, drive modes, and selectable input levels.
3.4.3
GPIO Enhanced (GPIO_ENH)
Supports extended functionality automotive signaling across the 2.7-V to 5.5-V VDDIO range with higher currents
at lower voltages (full I2C timing support, slew-rate control).
Both GPIO_STD and GPIO_ENH implement the following:
• Configurable input threshold (CMOS, TTL, or Automotive)
• Hold mode for latching previous state (used for retaining the I/O state in DeepSleep mode)
• Analog input mode (input and output buffers disabled)
3.4.4
HSIO Standard (HSIO_STD)
These I/Os are optimized exclusively for high-speed signaling and do not support slew-rate control, DeepSleep
operation, POR mode control, analog connections, or non-CMOS signaling levels. HSIO_STD supports high-speed
peripherals such as QSPI, HYPERBUS™, Ethernet, and SDHC controller. HSIO_STD also supports programmable
drive strength. These I/Os are available only in Active mode and retain state in DeepSleep mode.
3.4.5
Smart I/O
Smart I/O allows Boolean operations on signals going to the I/O from the subsystems of the chip or on signals
coming into the chip. CYT4BF has five Smart I/O blocks. Operation can be synchronous or asynchronous and the
blocks operate in all device power modes except for Hibernate.
Datasheet
21
002-21617 Rev. *K
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
CYT4BF address map
4
CYT4BF address map
The CYT4BF microcontroller supports the memory spaces shown in Figure 4-1.
• 8384 KB (8128 KB + 256 KB) of code-flash, used in the single- or dual-bank mode based on the associated bit in
the flash control register
- Single-bank mode: 8384 KB
- Dual-bank mode: 4192 KB per bank
• 256 KB (192 KB + 64 KB) of work-flash, used in the single- or dual-bank mode based on the associated bit in the
flash control register
- Single-bank mode: 256 KB
- Dual-bank mode: 128 KB per bank
• 64 KB of secure ROM
• 1024 KB of SRAM (First 2 KB is reserved for internal usage)
• 16 KB of Instruction TCM for each Cortex-M7 CPU
• 16 KB of Data TCM for each Cortex-M7 CPU
• 128 MB SMIF XIP
Datasheet
22
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
CYT4BF address map
0xFFFF FFFF
Arm System
Space
CPU & Debug Registers
0xE000 0000
Reserved
0xA011 3FFF
16 KB
Core CM7_1 Data TCM
CM7_1 DTCM
CM7_1 ITCM
CM7_0 DTCM
CM7_0 ITCM
0xA011 0000
Reserved
0xA010 3FFF
16 KB
Core CM7_1 Instruction TCM
Core CM7_0 Data TCM
0xA010 0000
Reserved
0xA001 3FFF
16 KB
0xA001 0000
Reserved
0xA000 3FFF
16 KB
Core CM7_0 Instruction TCM
0xA000 0000
Reserved
0x67FF FFFF
SMIF_XIP
Serial Memory Interface XIP
128 MB
0x6000 0000
Reserved
0x43FF FFFF
Peripheral
Interconnect or
Memory map
Mainly used for on-chip peripherals;
e.g., AHB or APB peripherals
0x4000 0000
Reserved
0x280F FFFF
256 KB
SRAM2
SRAM1
0x280C 0000
General purpose RAM,
mainly used for data
0x280B FFFF
256 KB
0x2808 0000
0x2807 FFFF
510 KB
SRAM0
0x2800 0800
2 KB
0x2800 0000
Reserved
CM7 internal address map for its
Data TCM
0x2000 3FFF
0x2000 0000
16 KB
CM7 DTCM
Reserved
Used to store manufacture specific
data like flash protection settings, trim
settings, device addresses, serial numbers,
calibration data, etc.
Alternate Flash
Supervisory
0x1780 7FFF
0x1780 0000
32 KB
Reserved
32 KB
Reserved
0x1700 7FFF
0x1700 0000
Flash Supervisory
Work flash
0x1403 FFFF
64 KB
(128B Small Sectors)
0x1403 0000
Work flash used for long
term data retention
0x1402 FFFF
192 KB
(2 KB Large Sectors)
0x1400 0000
Reserved
256 KB
0x1082 FFFF
(8 KB Small Sectors)
0x107F 0000
0x107E FFFF
Code flash
ROM Mirror
8128 KB
(32 KB Large
Sectors)
Mainly used for user program code
0x1000 0000
Reserved
64 KB
Reserved
Secured Boot ROM to set user specified
protection levels, trim and configuration
data, code authentication, jump to user mode, etc.
0x0100 FFFF
0x0100 0000
0x0000 FFFF
0x0000 0000
ROM
64 KB
CM7 internal address map for its instruction TCM.
The address overlaps with portion of ROM region.
0x0000 3FFF
16 KB
CM7 ITCM
0x0000 0000
Figure 4-1
CYT4BF address map[13, 14]
Notes
13.The size representation is not up to scale.
14.First 2KB of SRAM is reserved, not available for users. User must keep the power of first 32-KB block of SRAM0 in enabled or retained in
all Active, LP Active, Sleep, LP Sleep, DeepSleep modes.
Datasheet
23
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Flash base address map
5
Flash base address map
Table 5-1 through Table 5-6 give information about the sector mapping of the code- and work-flash regions
along with their respective base addresses.
Table 5-1
Code-flash address mapping in single-bank mode
Large Sectors Small Sectors
Code-flashSize(KB)
Large Sector Base Address
Small Sector Base Address
(LS)
(SS)
8384
32 KB × 254
8 KB × 32
0x1000 0000
0x107F 0000
Table 5-2
Work-flash address mapping in single-bank mode
Work-flash Size
(KB)
Large Sectors Small Sectors
2 KB × 96 128 B × 512
Large Sector Base Address
Small Sector Base Address
256
0x1400 0000
0x1403 0000
Table 5-3
Code-flash address mapping in dual-bank mode (Mapping A)
Second
Half
Second
Half SS
Base
First Half
LS Base
Address
First Half
Code-flash
Size (KB)
First
First
Second
Half LS
Second
Half SS
SS Base
Address
Half LS
Half SS
LS Base
Address
Address
8384
32 KB × 127 8 KB × 16 32 KB × 127 8 KB × 16 0x1000 0000 0x103F 8000 0x1200 0000 0x123F 8000
Table 5-4
Code-flash address mapping in dual-bank mode (Mapping B)
Second
Half
Second
Half SS
Base
First Half
LS Base
Address
First Half
SS Base
Address
Code-flash
Size (KB)
First
First
Second
Half LS
Second
Half SS
Half LS
Half SS
LS Base
Address
Address
8384
32 KB × 127 8 KB × 16 32 KB × 127 8 KB × 16 0x1200 0000 0x123F 8000 0x1000 0000 0x103F 8000
Table 5-5
Work-flash address mapping in dual-bank mode (Mapping A)
Second
Half
Second
Half SS
Base
First Half
LS Base
Address
First Half
SS Base
Address
Work-flash
Size (KB)
First
First
Second
Half LS
Second
Half SS
Half LS
Half SS
LS Base
Address
Address
256
2 KB × 48 128 B × 256 2 KB × 48 128 B × 256 0x1400 0000 0x1401 8000 0x1500 0000 0x1501 8000
Table 5-6
Work-flash address mapping in dual-bank mode (Mapping B)
Second
Half
Second
Half SS
Base
First Half
LS Base
Address
First Half
SS Base
Address
Work-flash
Size (KB)
First
First
Second
Half LS
Second
Half SS
Half LS
Half SS
LS Base
Address
Address
256
2 KB × 48 128 B × 256 2 KB × 48 128 B × 256 0x1500 0000 0x1501 8000 0x1400 0000 0x1401 8000
Datasheet
24
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Peripheral I/O map
6
Peripheral I/O map
CYT4BF peripheral I/O map
Description
Table 6-1
Base
Instance
Size
Section
Instances
Group Slave
Address
Peripheral interconnect
Peripheral group (0, 1, 2, 3, 4, 5, 6, 8, 9)
Peripheral trigger group
Peripheral 1:1 trigger group
Peripheral interconnect, master interface
PERI Programmable PPU
0x4000 0000
0x4000 4000
0x4000 8000
0x4000 C000
0x4002 0000
0x4002 0000
0x4002 0800
0x4004 0000
0x4010 0000
0x4020 0000
0x4021 0000
0x4021 0000
0x4022 0000
0x4022 0000
0x4022 1000
0x4023 0000
0x4023 2000
0x4023 4000
0x4024 0000
0x4026 0000
0x4026 1400
0x4026 1710
0x4026 1720
0x4026 1730
0x4026 1900
0x4026 8000
0x4026 C000
0x4027 0000
0x4027 1000
0x4028 0000
0x4028 8000
0x4029 0000
0x4029 8000
0x402A 0000
0x402A 1000
0x402C 0868
0x4030 0000
0x4031 0000
9
13
14
0x40
0x400
0x400
PERI
0
0
[15]
PERI_MS
10
0x40
0x40
0x2000
0
1
PERI Fixed PPU
700
2
PERI_PCLK Peripheral Clock Groups
0
1
2
2
0
0
CRYPTO
CPUSS
Cryptography component
CPU subsystem (CPUSS)
Fault structure subsystem
Fault structures
Inter process communication
IPC structures
FAULT
2
1
4
0x100
IPC
8
8
0x20
0x20
2
2
IPC interrupt structures
Protection
PROT
Shared memory protection unit structures
Memory protection unit structures
Flash controller
System Resources Sub-System Core Registers
Clock Supervision High Frequency
Clock Supervision Reference Frequency
Clock Supervision Low Frequency
Clock Supervision Internal Low Frequency
Clock PLL 400 MHz
Multi Counter WDT
Free Running WDT
SRSS Backup Domain/RTC
Backup Register
P-DMA0 Controller
16
16
0x40
0x400
2
2
3
4
FLASHC
8
1
1
1
2
3
1
0x10
SRSS
2
5
0x10
0x100
BACKUP
P-DMA
2
2
2
2
6
7
8
9
4
0x04
0x40
0x40
P-DMA0 channel structures
P-DMA1 Controller
P-DMA1 channel structures
M-DMA0 Controller
143
65
M-DMA
M-DMA0 channels
8
6
35
35
0x100
0x04
0x10
0x80
eFUSE
HSIOM
GPIO
eFUSE Customer Data (192 bits)
High-Speed I/O Matrix (HSIOM)
GPIO port control/configuration
2
3
3
10
0
1
Note
15.These Programmable PPUs are configured by the Boot ROM and are available for the user based on the access rights. Refer to the
device-specific TRM to know more about the configuration of these programmable PPUs.
Datasheet
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Peripheral I/O map
Table 6-1
Section
CYT4BF peripheral I/O map (continued)
Base
Instance
Size
Description
Instances
Group Slave
Address
Programmable I/O configuration
SMARTIO port configuration
Timer/Counter/PWM 0 (TCPWM0)
TCPWM0 Group #0 (16-bit)
TCPWM0 Group #1 (16-bit, Motor control)
TCPWM0 Group #2 (32-bit)
Event generator 0 (EVTGEN0)
Event generator 0 comparator structures
Serial Memory Interface 0 (SMIF0)
SMIF0 Devices
Secure Digital High Capacity 0 (SDHC0)
SDHC0 Wrap
SDHC0 Core
Ethernet 0 (ETH0)
Local Interconnect Network 0 (LIN0)
LIN0 Channels
0x4032 0000
0x4032 0C00
0x4038 0000
0x4038 0000
0x4038 8000
0x4039 0000
0x403F 0000
0x403F 0800
0x4042 0000
0x4042 0800
0x4046 0000
0x4046 0000
0x4046 1000
0x4048 0000
0x4050 0000
0x4050 8000
0x4052 0000
0x4053 0000
0x4054 0000
0x4055 0000
0x4056 0000
0x4058 0000
0x4058 0000
0x4058 8000
0x4059 0000
0x4060 0000
0x4080 0000
0x4090 0000
0x4090 0000
0x4090 1000
0x4090 2000
0x4090 0800
0x4090 1800
0x4090 2800
SMARTIO
3
2
5
0x100
3
3
3
0x80
0x80
0x80
TCPWM
3
3
EVTGEN
SMIF
3
4
4
0
16
1
0x20
0x80
SDHC
4
1
ETH
LIN
2
0x10000
4
5
2
0
20
5
0x100
0x200
0x9FFF
0x200
CAN0 controller
Message RAM CAN0
CAN1 controller
Message RAM CAN1
5
1
TTCANFD
FLEXRAY
TCPWM
SCB
5
5
5
2
3
0x9FFF
FlexRay 0
Timer/Counter/PWM 1 (TCPWM1)
TCPWM1 Group #0 (16-bit)
TCPWM1 Group #1 (16-bit, Motor control)
TCPWM1 Group #2 (32-bit)
84
12
13
11
3
0x80
0x80
0x80
0x10000
0x1000
5
4
2
Serial Communications Block (SPI/UART/I C)
6
8
0-10
0-2
2
2
I S
I S Audio Subsystem
Programmable Analog Subsystem (PASS0)
SAR0 channel controller
SAR1 channel controller
SAR2 channel controller
SAR0 channel structures
SAR PASS
9
0
32
32
32
0x40
0x40
0x40
SAR1 channel structures
SAR2 channel structures
Datasheet
26
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
CYT4BF clock diagram
7
CYT4BF clock diagram
IMO
EXT_CLK
ECO
WCO
LS
ILO0
LS
ILO1
LS
ECO
Prescaler
LS
MUX
MUX
MUX
MUX
MUX
MUX
MUX
MUX
FLL
MUX
PLL400#0
MUX
PLL400#1
MUX
PLL#2
MUX
PLL#3
MUX
MUX
LS
CLK_ILO0
CLK_
PATH0
CLK_
PATH1
CLK_
PATH2
CLK_
PATH3
CLK_
PATH4
CLK_
PATH5
CLK_REF_HF
WDT
MUX
CLK_BAK
CLK_LF
RTC
CSV
CLK_ILO0
MCWDT
MUX
MUX
MUX
MUX
MUX
MUX
MUX
MUX
Predivider
(1/2/4/8)
Predivider
(1/2/4/8)
Predivider
(1/2/4/8)
Predivider
(1/2/4/8)
Predivider
(1/2/4/8)
Predivider
(1/2/4/8)
Predivider
(1/2/4/8)
Predivider
(1/2/4/8)
CLK_HF0
CLK_HF1
CLK_HF2
CLK_HF3
CLK_HF4
CLK_HF5
CLK_HF6
CLK_HF7
CSV
CSV
CSV
CSV
CSV
CSV
CSV
CSV
CSV
CSV
CLK_ILO0
CLK_LF
CLK_REF_HF
SDHC
AUDIOSS
I2S External Clock
Tx_CLK, Rx_CLK and REF_CLK to Ethernet
PHY, TSU
Ethernet
Event Generator
CLK_GR5
Divider
(1-256)
CAN FD
FLEX-RAY
LIN
Incl. PERI_GR5_SL_CTL
TCPWM[1]
CLK_GR6
Divider
(1-256)
SCB[*]
SCB[0]
Serial Interface Clock
Incl. PERI_GR6_SL_CTL
CLK_GR9
Divider
(1-256)
SAR ADC
Incl. PERI_GR9_SL_CTL
PCLK_CANFD[x]_CLOCK_CAN[y]
PCLK_FLEXRAY_CLK_FLEXRAY
PCLK_LIN_CLOCK_CH_EN[x]
PCLK_TCPWM1_CLOCKS[x]
PCLK_SCB[x]_CLOCK
Peripheral
Clock Dividers #1
PCLK_PASS_CLOCK_SAR[x]
CLK_FAST_0
CLK_FAST_1
Divider
(1-256)
CM7_0
CM7_1
Divider
(1-256)
SMIF
CLK_MEM
Divider
(1-256)
ROM/SRAM/FLASH
CPUSS Fast Infrastructure
CLK_SLOW
Divider
(1-256)
CM0+
LEGEND 1:
Active Domain
CLK_GR2
CPUSS Slow Infrastructure
P-DMA / M-DMA
CRYPTO
DeepSleep Domain
Hibernate Domain
Register
PERI_GR2_SL_CTL
CLK_PERI
CLK_GR3
LEGEND 2:
Relationship of Monitored Clock and
Reference Clock
Divider
(1-256)
Divider
(1-256)
Incl. PERI_GR3_SL_CTL
Monitored Clock
PERI
CLK_GR4
Divider
(1-256)
Incl. PERI_GR4_SL_CTL
SRSS
Reference Clock
CSV
CLK_GR8
Divider
(1-256)
EFUSE
Incl. PERI_GR8_SL_CTL
LEGEND 3:
One Clock Line
Multiple Clock Lines
IOSS
TCPWM[0]
CPUSS(DEBUG)
Peripheral
Clock Dividers #0
TCK/SWDCLK from a Debugger
CLK_TRC_DBG
Divider
(1-256)
PCLK_SMARTIO[x]_CLOCK
PCLK_TCPWM0_CLOCKS[x]
PCLK_CPUSS_CLOCK_TRACE_IN
Figure 7-1
CYT4BF clock diagram
Datasheet
27
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
CYT4BF CPU start-up sequence
8
CYT4BF CPU start-up sequence
The start-up sequence is described in the following steps:
1. System Reset (@0x0000 0000)
2. CM0+ executes ROM boot (@0x0000 0004)
i. Applies trims
ii. Applies Debug Access port (DAP) access restrictions and system protection from eFuse and supervisory
flash
iii.Authenticates flash boot (only in SECURE life-cycle stage) and transfers control to it
3. CM0+ executes flash boot (from Supervisory flash @0x1700 2000)
i. Debug pins are configured based on the SWD/JTAG spec[16]
ii. Sets CM0+ vector offset register (CM0_VTOR part of the Arm® system space) to the beginning of flash
(@0x1000 0000)
iii.CM0+ branches to its Reset handler
4. CM0+ starts execution of application
i. Moves CM0+ vector table to SRAM (updates CM0+ vector table base)
i. Sets clocks for CM7_0 (CLK_HF1) and CM7_1 (CLK_HF2)
ii. Sets CM7_0 (CM7_0_VECTOR_TABLE_BASE @0x4020 0200) and CM7_1 (CM7_1_VECTOR_TABLE_BASE
@0x4020 0600) vector tables to the respective locations, also and mentioned in flash (specified in the linker
definition file)
iii.Enables the power for both the CPU cores CM7_0 and CM7_1
iv.Disables CPU_WAIT to allow accesses from the debugger
v. Releases CM7_0 and/or CM7_1 from reset
vi.Continues execution of CM0+ user application
5. CM7_0 and/or CM7_1 executes directly from either code-flash or SRAM
i. CM7_0/CM7_1 branches to its Reset handler
ii. Continues execution of the user application
Note
16.Port configuration of SWD/JTAG pins will be changed from the default GPIO mode to support debugging after the boot process, refer
to Table 11-1 for pin assignments.
Datasheet
28
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Pin assignment
9
Pin assignment
Note: Thermal pad needs to be connected to VSSD.
VSSD
P0.0
P0.1
P0.2
P0.3
P1.0
P1.1
P1.2
P1.3
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
VDDD
VSSD
P4.0
P4.1
P4.2
P4.3
P4.4
P5.0
P5.1
P5.2
P5.3
P5.4
P5.5
P6.0
P6.1
P6.2
P6.3
P6.4
P6.5
P6.6
P6.7
VDDD
VDDIO_1
1
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
VDDD
P18.7
P18.6
P18.5
P18.4
P18.3
P18.2
P18.1
P18.0
P17.7
P17.6
P17.5
P17.4
P17.3
P17.2
P17.1
P17.0
P16.3
VSSD
VCCD
VCCD
VCCD
VDDD
P15.3
P15.2
P15.1
P15.0
P14.7
P14.6
P14.5
P14.4
P14.3
P14.2
P14.1
P14.0
P13.7
P13.6
P13.5
P13.4
P13.3
P13.2
P13.1
P13.0
VSSD
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
176-TEQFP
98
97
96
95
94
93
92
91
90
89
Figure 9-1
176-TEQFP pin assignment
Datasheet
29
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Pin assignment
VSSD
PWM1_18/PWM1_22_N/TC1_18_TR0/TC1_22_TR1/PWM0_H_0/SCB0_RX (0)/SCB7_SDA (2)/SCB0_MISO (0)/LIN1_RX P0.0
PWM1_17/PWM1_18_N/TC1_17_TR0/TC1_18_TR1/PWM0_H_0_N/SCB0_TX (0)/SCB7_SCL (2)/SCB0_MOSI (0)/LIN1_TX P0.1
PWM1_14/PWM1_17_N/TC1_14_TR0/TC1_17_TR1/TC0_H_0_TR0/SCB0_RTS (0)/SCB0_SCL (0)/SCB0_CLK (0)/SCB4_MISO (2)/LIN1_EN/CAN0_1_TX P0.2
PWM1_13/PWM1_14_N/TC1_13_TR0/TC1_14_TR1/TC0_H_0_TR1/SCB0_CTS (0)/SCB0_SDA (0)/SCB0_SEL0 (0)/SCB4_MOSI (2)/CAN0_1_RX P0.3
PWM1_12/PWM1_13_N/TC1_12_TR0/TC1_13_TR1/PWM1_H_4/SCB0_SCL (1)/SCB0_MISO (1)/SCB4_CLK (2) P1.0
PWM1_11/PWM1_12_N/TC1_11_TR0/TC1_12_TR1/PWM1_H_5/SCB0_SDA (1)/SCB0_MOSI (1)/SCB4_SEL0 (2) P1.1
PWM1_10/PWM1_11_N/TC1_10_TR0/TC1_11_TR1/PWM1_H_6/SCB0_CLK (1)/LIN0_RX/TRIG_IN[0] P1.2
1
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
VDDD
2
P18.7 PWM1_50/PWM1_51_N/TC1_50_TR0/TC1_51_TR1/TC0_M_2_TR1/ETH0_TXD_3 (0)/PWM1_H_3_N/CAN1_2_RX/TRACE_DATA_3 (0)/ADC[2]_23
P18.6 PWM1_51/PWM1_52_N/TC1_51_TR0/TC1_52_TR1/TC0_M_2_TR0/ETH0_TXD_2 (0)/PWM1_H_3/SCB1_SEL3 (0)/CAN1_2_TX/TRACE_DATA_2 (0)/ADC[2]_22
P18.5 PWM1_52/PWM1_53_N/TC1_52_TR0/TC1_53_TR1/PWM0_M_2_N/ETH0_TXD_1 (0)/PWM1_H_2_N/SCB1_SEL2 (0)/TRACE_DATA_1 (0)/ADC[2]_21
P18.4 PWM1_53/PWM1_54_N/TC1_53_TR0/TC1_54_TR1/PWM0_M_2/ETH0_TXD_0 (0)/PWM1_H_2/SCB1_SEL1 (0)/SCB3_SEL0 (2)/TRACE_DATA_0 (0)/ADC[2]_20
P18.3 PWM1_54/PWM1_55_N/TC1_54_TR0/TC1_55_TR1/ETH0_TX_CLK (0)/PWM1_H_1_N/SCB1_CTS (0)/SCB1_SEL0 (0)/SCB3_CLK (2)/TRACE_CLOCK (0)/ADC[2]_19
P18.2 PWM1_55/PWM1_M_7_N/TC1_55_TR0/TC1_M_7_TR1/ETH0_TX_ER (0)/PWM1_H_1/SCB1_RTS (0)/SCB1_SCL (0)/SCB1_CLK (0)/SCB3_MOSI (1)/ADC[2]_18
P18.1 PWM1_M_7/PWM1_M_6_N/TC1_M_7_TR0/TC1_M_6_TR1/ETH0_TX_CTL (0)/PWM1_H_0_N/SCB1_TX (0)/SCB1_SDA (0)/SCB1_MOSI (0)/SCB3_MISO (1)/FAULT_OUT_1/ADC[2]_17
P18.0 PWM1_M_6/PWM1_M_5_N/TC1_M_6_TR0/TC1_M_5_TR1/ETH0_REF_CLK (0)/PWM1_H_0/SCB1_RX (0)/SCB1_MISO (0)/LIN12_TX/FAULT_OUT_0/ADC[2]_16
P17.7 PWM1_M_5/PWM1_M_4_N/TC1_M_5_TR0/TC1_M_4_TR1/LIN15_EN/LIN12_RX/ADC[2]_15
3
4
5
6
7
8
PWM1_8/PWM1_10_N/TC1_8_TR0/TC1_10_TR1/PWM1_H_7/SCB0_SEL0 (1)/LIN0_TX/TRIG_IN[1] P1.3
9
PWM1_7/PWM1_8_N/TC1_7_TR0/TC1_8_TR1/TC1_H_4_TR0/SCB7_RX (0)/SCB0_SEL1 (0)/SCB7_MISO (0)/LIN0_RX/CAN0_0_TX/SWJ_TRSTN/TRIG_IN[2] P2.0
PWM1_6/PWM1_7_N/TC1_6_TR0/TC1_7_TR1/TC1_H_5_TR0/SCB7_TX (0)/SCB7_SDA (0)/SCB0_SEL2 (0)/SCB7_MOSI (0)/LIN0_TX/CAN0_0_RX/TRIG_IN[3] P2.1
PWM1_5/PWM1_6_N/TC1_5_TR0/TC1_6_TR1/ETH0_RX_ER (0)/TC1_H_6_TR0/SCB7_RTS (0)/SCB7_SCL (0)/SCB0_SEL3 (0)/SCB7_CLK (0)/LIN0_EN/TRIG_IN[4] P2.2
PWM1_4/PWM1_5_N/TC1_4_TR0/TC1_5_TR1/ETH0_ETH_TSU_TIMER_CMP_VAL (0)/TC1_H_7_TR0/SCB7_CTS (0)/SCB7_SEL0 (0)/LIN5_RX/TRIG_IN[5] P2.3
PWM1_3/PWM1_4_N/TC1_3_TR0/TC1_4_TR1/PWM1_H_4_N/SCB7_SEL1 (0)/LIN5_TX/TRIG_IN[6] P2.4
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
P17.6 PWM1_M_4/PWM1_56_N/TC1_M_4_TR0/TC1_56_TR1/PWM1_H_2_N/LIN15_TX/SCB3_SEL2 (1)/ADC[2]_14
P17.5 PWM1_56/PWM1_57_N/TC1_56_TR0/TC1_57_TR1/PWM1_H_2/LIN15_RX/SCB3_SEL1 (1)/ADC[2]_13
P17.4 PWM1_57/PWM1_58_N/TC1_57_TR0/TC1_58_TR1/PWM1_H_3_N/SCB3_CTS (1)/SCB3_SEL0 (1)/TRIG_IN[27]/ADC[2]_12
P17.3 PWM1_58/PWM1_59_N/TC1_58_TR0/TC1_59_TR1/PWM1_H_3/SCB3_RTS (1)/SCB3_SCL (1)/SCB3_CLK (1)/TRIG_IN[26]/ADC[2]_11
P17.2 PWM1_59/PWM1_60_N/TC1_59_TR0/TC1_60_TR1/SCB3_TX (1)/SCB3_SDA (1)/LIN11_EN/ADC[2]_10
P17.1 PWM1_60/PWM1_61_N/TC1_60_TR0/TC1_61_TR1/SCB3_RX (1)/LIN11_TX/CAN1_1_RX/ADC[2]_9
PWM1_2/PWM1_3_N/TC1_2_TR0/TC1_3_TR1/PWM1_H_5_N/SCB7_SEL2 (0)/LIN5_EN/TRIG_IN[7] P2.5
PWM1_1/PWM1_2_N/TC1_1_TR0/TC1_2_TR1/ETH0_MDIO (0)/PWM1_H_6_N/SCB6_RX (0)/SCB6_MISO (0)/CAN0_3_TX/TRIG_DBG[0] P3.0
PWM1_0/PWM1_1_N/TC1_0_TR0/TC1_1_TR1/ETH0_MDC (0)/PWM1_H_7_N/SCB6_TX (0)/SCB6_SDA (0)/SCB6_MOSI (0)/CAN0_3_RX/TRIG_DBG[1] P3.1
PWM1_M_3/PWM1_0_N/TC1_M_3_TR0/TC1_0_TR1/TC1_H_4_TR1/SCB6_RTS (0)/SCB6_SCL (0)/SCB6_CLK (0) P3.2
PWM1_M_2/PWM1_M_3_N/TC1_M_2_TR0/TC1_M_3_TR1/TC1_H_5_TR1/SCB6_CTS (0)/SCB6_SEL0 (0) P3.3
PWM1_M_1/PWM1_M_2_N/TC1_M_1_TR0/TC1_M_2_TR1/TC1_H_6_TR1/SCB6_SEL1 (0)/LIN1_RX P3.4
P17.0 PWM1_61/PWM1_62_N/TC1_61_TR0/TC1_62_TR1/LIN11_RX/CAN1_1_TX/ADC[2]_8
P16.3 PWM1_62/PWM1_62_N/TC1_62_TR0/TC1_62_TR1/PWM1_H_1_N/ADC[2]_3
VSSD
VCCD
PWM1_M_0/PWM1_M_1_N/TC1_M_0_TR0/TC1_M_1_TR1/TC1_H_7_TR1/SCB6_SEL2 (0)/LIN1_TX P3.5
VCCD
VDDD
VCCD
VSSD
VDDD
176-TEQFP
PWM1_4/PWM1_M_0_N/TC1_4_TR0/TC1_M_0_TR1/EXT_MUX[0]_0/SCB5_RX (0)/SCB5_MISO (0)/LIN1_RX/TRIG_IN[10] P4.0
PWM1_5/PWM1_4_N/TC1_5_TR0/TC1_4_TR1/EXT_MUX[0]_1/SCB5_TX (0)/SCB5_SDA (0)/SCB5_MOSI (0)/LIN1_TX/TRIG_IN[11] P4.1
PWM1_6/PWM1_5_N/TC1_6_TR0/TC1_5_TR1/EXT_MUX[0]_2/SCB5_RTS (0)/SCB5_SCL (0)/SCB5_CLK (0)/LIN1_EN/TRIG_IN[12] P4.2
PWM1_7/PWM1_6_N/TC1_7_TR0/TC1_6_TR1/EXT_MUX[0]_EN/SCB5_CTS (0)/SCB5_SEL0 (0)/CAN0_1_TX/TRIG_IN[13] P4.3
PWM1_8/PWM1_7_N/TC1_8_TR0/TC1_7_TR1/LIN15_RX/SCB5_SEL1 (0)/CAN0_1_RX P4.4
P15.3 PWM1_59/PWM1_58_N/TC1_59_TR0/TC1_58_TR1/AUDIOSS2_RX_SDI/TC1_H_7_TR1/SCB9_CTS (0)/SCB9_SEL0 (0)/ADC[1]_31
P15.2 PWM1_58/PWM1_57_N/TC1_58_TR0/TC1_57_TR1/AUDIOSS2_RX_WS/TC1_H_7_TR0/SCB9_RTS (0)/SCB9_SCL (0)/SCB9_CLK (0)/ADC[1]_30
P15.1 PWM1_57/PWM1_56_N/TC1_57_TR0/TC1_56_TR1/AUDIOSS2_RX_SCK/TC1_H_6_TR1/SCB9_TX (0)/SCB9_SDA (0)/SCB9_MOSI (0)/CAN1_3_RX/ADC[1]_29
P15.0 PWM1_56/PWM1_55_N/TC1_56_TR0/TC1_55_TR1/AUDIOSS2_CLK_I2S_IF/TC1_H_6_TR0/SCB9_RX (0)/SCB9_MISO (0)/CAN1_3_TX/ADC[1]_28
P14.7 PWM1_55/PWM1_54_N/TC1_55_TR0/TC1_54_TR1/TC1_H_5_TR1/LIN14_EN/TRIG_IN[25]/ADC[1]_27
PWM1_9/PWM1_8_N/TC1_9_TR0/TC1_8_TR1/PWM0_M_0/PWM1_H_10/LIN15_TX/SCB5_SEL2 (0)/LIN7_RX/TRIG_IN[38] P5.0
PWM1_10/PWM1_9_N/TC1_10_TR0/TC1_9_TR1/PWM0_M_0_N/PWM1_H_10_N/SCB9_SEL3 (1)/LIN7_TX/TRIG_IN[39] P5.1
PWM1_11/PWM1_10_N/TC1_11_TR0/TC1_10_TR1/TC0_M_0_TR0/TC1_H_10_TR0/LIN10_RX/LIN7_EN P5.2
PWM1_12/PWM1_11_N/TC1_12_TR0/TC1_11_TR1/TC0_M_0_TR1/TC1_H_10_TR1/LIN10_TX/LIN2_RX P5.3
PWM1_13/PWM1_12_N/TC1_13_TR0/TC1_12_TR1/LIN9_RX/PWM1_H_11/LIN2_TX P5.4
P14.6 PWM1_54/PWM1_53_N/TC1_54_TR0/TC1_53_TR1/TC1_H_5_TR0/LIN14_TX/TRIG_IN[24]/ADC[1]_26
P14.5 PWM1_53/PWM1_52_N/TC1_53_TR0/TC1_52_TR1/AUDIOSS2_TX_SDO/TC1_H_4_TR1/SCB2_SEL2 (0)/LIN14_RX/ADC[1]_25
P14.4 PWM1_52/PWM1_51_N/TC1_52_TR0/TC1_51_TR1/AUDIOSS2_TX_WS/TC1_H_4_TR0/SCB2_SEL1 (0)/LIN6_EN/ADC[1]_24
P14.3 PWM1_51/PWM1_50_N/TC1_51_TR0/TC1_50_TR1/TC0_M_1_TR1/PWM1_H_7_N/SCB2_SEL0 (0)/SCB2_CTS (0)/LIN6_TX/ADC[1]_23
P14.2 PWM1_50/PWM1_49_N/TC1_50_TR0/TC1_49_TR1/TC0_M_1_TR0/PWM1_H_7/SCB2_CLK (0)/SCB2_SCL (0)/SCB2_RTS (0)/LIN6_RX/ADC[1]_22
P14.1 PWM1_49/PWM1_48_N/TC1_49_TR0/TC1_48_TR1/PWM0_M_1_N/AUDIOSS2_TX_SCK/PWM1_H_6_N/SCB2_MOSI (0)/SCB2_SDA (0)/SCB2_TX (0)/CAN1_0_RX/ADC[1]_21
P14.0 PWM1_48/PWM1_47_N/TC1_48_TR0/TC1_47_TR1/PWM0_M_1/AUDIOSS2_MCLK/PWM1_H_6/SCB2_MISO (0)/SCB2_RX (0)/CAN1_0_TX/ADC[1]_20
P13.7 PWM1_47/PWM1_M_11_N/TC1_47_TR0/TC1_M_11_TR1/AUDIOSS1_RX_SDI/PWM1_H_5_N/TRIG_IN[23]/ADC[1]_19
P13.6 PWM1_M_11/PWM1_46_N/TC1_M_11_TR0/TC1_46_TR1/LIN8_EN/AUDIOSS1_RX_WS/PWM1_H_5/SCB3_SEL3 (0)/TRIG_IN[22]/ADC[1]_18
P13.5 PWM1_46/PWM1_M_10_N/TC1_46_TR0/TC1_M_10_TR1/LIN8_TX/AUDIOSS1_RX_SCK/PWM1_H_4_N/SCB3_SEL2 (0)/ADC[1]_17
P13.4 PWM1_M_10/PWM1_45_N/TC1_M_10_TR0/TC1_45_TR1/LIN8_RX/AUDIOSS1_CLK_I2S_IF/PWM1_H_4/LIN2_TX/SCB3_SEL1 (0)/ADC[1]_16
P13.3 PWM1_45/PWM1_M_9_N/TC1_45_TR0/TC1_M_9_TR1/AUDIOSS1_TX_SDO/EXT_MUX[2]_EN/SCB3_CTS (0)/LIN2_RX/SCB3_SEL0 (0)/ADC[1]_15
P13.2 PWM1_M_9/PWM1_44_N/TC1_M_9_TR0/TC1_44_TR1/PWM0_2/AUDIOSS1_TX_WS/EXT_MUX[2]_2/SCB3_RTS (0)/SCB3_SCL (0)/LIN3_EN/SCB3_CLK (0)/ADC[1]_14
P13.1 PWM1_44/PWM1_M_8_N/TC1_44_TR0/TC1_M_8_TR1/PWM0_2_N/AUDIOSS1_TX_SCK/EXT_MUX[2]_1/SCB3_TX (0)/SCB3_SDA (0)/LIN3_TX/SCB3_MOSI (0)/ADC[1]_13
P13.0 PWM1_M_8/PWM1_43_N/TC1_M_8_TR0/TC1_43_TR1/TC0_2_TR0/AUDIOSS1_MCLK/EXT_MUX[2]_0/SCB3_RX (0)/LIN3_RX/SCB3_MISO (0)/ADC[1]_12
VSSD
PWM1_14/PWM1_13_N/TC1_14_TR0/TC1_13_TR1/LIN9_TX/PWM1_H_11_N/LIN2_EN P5.5
PWM1_M_0/PWM1_14_N/TC1_M_0_TR0/TC1_14_TR1/PWM0_0/LIN9_EN/TC1_H_11_TR0/SCB4_RX (0)/SCB4_MISO (0)/LIN3_RX/ADC[0]_0 P6.0
PWM1_0/PWM1_M_0_N/TC1_0_TR0/TC1_M_0_TR1/TC1_H_11_TR1/SCB4_TX (0)/SCB4_SDA (0)/SCB4_MOSI (0)/LIN3_TX/ADC[0]_1 P6.1
PWM1_M_1/PWM1_0_N/TC1_M_1_TR0/TC1_0_TR1/PWM0_0_N/SDHC_CARD_MECH_WRITE_PROT (0)/PWM1_H_12/SCB4_RTS (0)/SCB4_SCL (0)/SCB4_CLK (0)/LIN3_EN/CAN0_2_TX/ADC[0]_2 P6.2
PWM1_1/PWM1_M_1_N/TC1_1_TR0/TC1_M_1_TR1/SPIHB_CLK (0)/SDHC_CARD_CMD (0)/PWM1_H_12_N/SCB4_CTS (0)/SCB4_SEL0 (0)/LIN4_RX/CAN0_2_RX/CAL_SUP_NZ/ADC[0]_3 P6.3
PWM1_M_2/PWM1_1_N/TC1_M_2_TR0/TC1_1_TR1/TC0_0_TR0/SPIHB_RWDS (0)/SDHC_CLK_CARD (0)/TC1_H_12_TR0/SCB4_SEL1 (0)/LIN4_TX/ADC[0]_4 P6.4
PWM1_2/PWM1_M_2_N/TC1_2_TR0/TC1_M_2_TR1/TC0_0_TR1/SPIHB_SEL0 (0)/SDHC_CARD_DETECT_N (0)/TC1_H_12_TR1/SCB4_SEL2 (0)/LIN4_EN/ADC[0]_5 P6.5
PWM1_M_3/PWM1_2_N/TC1_M_3_TR0/TC1_2_TR1/SCB4_SEL3 (0)/TRIG_IN[8]/ADC[0]_6 P6.6
98
97
96
95
94
93
92
PWM1_3/PWM1_M_3_N/TC1_3_TR0/TC1_M_3_TR1/TRIG_IN[9]/ADC[0]_7 P6.7
91
VDDD
90
VDDIO_1
89
Figure 9-2
176-TEQFP pin assignment with alternate functions
Datasheet
30
002-21617 Rev. *K
2022-10-10
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Pin assignment
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18
VSSD
P6.5
P6.2
P31.2 P31.0
P5.0
P4.4
P4.0
P29.5 P29.1 P29.0
P3.1
P3.2
P3.3
P3.4
P3.0
P2.4
P2.5
P2.6
P2.0
P2.1
P2.2
P2.3
P1.1
P1.2
P1.3
P1.4
P1.0
P0.2
VSSD
A
B
C
D
E
F
P6.7
P6.6
P6.3
P6.4
P6.0
P6.1
P31.1
P5.4
P5.5
P5.1
P5.2
P5.3
P30.0
P30.1
P30.2
P4.1
P4.2
P4.3
P29.6 P29.2
P29.7 P29.3
VSSD P29.4
P3.5
P3.6
P3.7
P0.3
P0.1
P0.0
P32.0 P32.1
P28.7 P28.6 P28.5
P28.4 P28.3 P28.2
P32.2 P32.3 P32.4 P32.5
P7.0
P7.2
P7.6
P9.0
P9.2
P7.1
P7.3
P7.7
P9.1
P9.3
P32.6 P32.7
P28.1 P28.0 P23.7 P23.6
P23.5 P23.4 P23.3 P22.3
P23.1 P23.0 P22.7 P22.2
P22.6 P22.5 P22.4 P22.1
VDDIO
_1
VDDIO VDDIO
P7.4
P8.0
P8.3
P7.5
P8.1
P8.4
VCCD P30.3 VDDD
P2.7
VCCD
_1
_1
P8.2
VSSD
VSSD P23.2
VDDD
G
H
J
VDDIO
_3
VSSIO
_3
VSSD VSSD VSSD
VSSD VSSD VSSD
DRV_
VSSD P21.7 P21.6
VOUT
VDDIO
_3
VSSIO
_3
VDDD
P24.0 P24.1
XRES_
P24.2 P24.3 P24.4 P25.0
P25.1 P25.2 P25.3 P25.4
P10.0 P25.5 P25.6 P25.7
P10.1 P10.2 P10.3 P10.4
P10.5 P10.6 P10.7 P11.1
VREFH
VDDA
VREFL VSSD VSSD VSSD
VDDD
P20.7 P20.6 P21.5
L
K
L
VSSD
_1
VSSD
_2
VSSIO VSSIO
_4 _4
VDDD
VSSA
P20.5 P20.4 P21.4
P11.0 VSSD
VCCD P14.5
VSSD P20.3
P20.2 P20.1 P21.2 P21.3
M
N
P
R
T
VDDIO
_2
VDDIO VDDIO
_4 _4
VDDD P16.7 VCCD
P19.4 P20.0 P21.0 P21.1
VSSD
_2
P18.7 P19.3 P19.2
P12.0 P12.1 P12.2 P11.2 VSSD P14.4 P14.7 P26.1 P26.5 P27.1 P27.5 P27.7 P16.5 VSSD P18.6 P18.5 P19.1 P19.0
P12.3 P12.4 P12.5 P13.5 P13.7 P14.3 P14.6 P26.0 P26.4 P27.0 P27.4 P27.6 P16.4 P16.6 P17.4 P18.4 P18.3 P18.2
P12.6 P12.7 P13.2 P13.4 P13.6 P14.2 P15.1 P15.3 P26.3 P26.7 P27.3 P16.1 P16.3 P17.1 P17.3 P17.6 P18.1 P18.0
VSSD P13.0 P13.1 P13.3 P14.0 P14.1 P15.0 P15.2 P26.2 P26.6 P27.2 P16.0 P16.2 P17.0 P17.2 P17.5 P17.7 VSSD
U
V
Figure 9-3
272-BGA ball map
Datasheet
31
002-21617 Rev. *K
2022-10-10
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Pin assignment
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20
VSSD
P6.2
P6.0
P5.3
P5.0
P30.1
P4.5
P4.1
P4.0
P29.2 P29.0
P3.2
P3.3
P3.4
P3.0
P3.1
P2.6
P2.2
P2.3
P2.4
P2.0
P2.1
P1.4
P1.1
P1.2
P1.3
P1.0
P0.2
P0.3
P0.0
P28.7 VSSD
A
B
C
D
E
F
P6.3
P6.5
P6.7
P6.4
P6.6
P6.1
P5.4
P5.5
P5.1
P5.2
P30.2
P4.6
P4.2
P4.3
P29.5 P29.3 P29.1
P0.1
P28.6 P28.5
VSSD
P30.3 P30.0
P29.6 VSSD
P3.6
VSSD P28.4 P28.3
P28.2 P28.1 P23.5
P23.4 P23.3 P23.2
P23.1 P23.0 P22.3
P22.5 P22.4 P22.2
P21.7 P21.6 P22.1
P32.0 P32.1
P32.3 P32.4 P32.5
P32.2
P31.2 P31.0
P4.4
P29.7 P29.4
P3.7
P3.5
P2.7
P2.5
P1.6
P1.5
P28.0
VDDIO VDDIO VDDIO VDDIO
_1 _1 _1 _1
P7.0
P7.2
P8.0
P8.3
P9.0
P7.1
P7.3
P8.1
P8.4
P9.1
P32.6
P7.4
P32.7 VCCD P31.1 VDDD VDDD
VCCD P23.6
P23.7 P22.7
VDDD P22.6
VDDD P20.7
VDDD P20.6
VDDD P20.5
VDDD P20.2
VDDD P19.4
P19.3 P19.2
P7.5
P7.7
P7.6
G
H
J
VDDIO
_3
VSSIO
_3
P8.2
VSSD VSSD VSSD VSSD VSSD
VSSD VSSD VSSD VSSD VSSD
VSSD VSSD VSSD VSSD VSSD
VSSD VSSD VSSD VSSD VSSD
DRV_
VSSD P21.5
VOUT
VDDIO
_3
VSSIO
_3
P9.2
P9.3
VDDIO
_3
VSSIO
_3
P24.0
P10.0
P10.1
VSSD P21.4 XRES_L
K
L
VDDIO
_3
VSSIO
_3
VSSD
_2
P24.1 P24.2 P24.3
P24.4 P25.0 P25.1
P25.2 P25.3 P25.4
P25.5 P25.6 P25.7
P10.4 P10.5 P10.6
P10.7 P12.0 P12.1
P12.2 P12.3 P12.4
P20.4 P20.3
P10.2 VREFH
P10.3 VDDA
VREFL VSSD VSSD VSSD VSSD VSSD
P20.1 P21.2 P21.3
P20.0 P21.0 P21.1
M
N
P
R
T
VSSIO VSSIO VSSIO
_4 _4 _4
VSSD
_1
VSSA
VSSD
VSSD
_2
P11.0
P11.1
P19.1 P19.0
VDDIO VDDIO VDDIO VDDIO
_2 _4 _4 _4
P11.2 VCCD P14.6
VDDD VDDD P17.3 VCCD P18.7
P34.7 P34.6 P34.5
P34.4 P34.3 P34.2
P34.1 P34.0 P33.7
P14.1
P14.5 P14.7 P15.3 P16.0 P16.1 P16.2 P16.3 P16.4 P17.2 P18.5 P18.6
U
V
W
Y
P12.5 P12.6 VSSD VSSD P14.0 P14.4 P15.2 P26.2 P26.5 P27.0 P27.3 P27.5 P27.7 P17.1 VSSD P18.0 P33.1 P33.3 P33.6 P33.5
P12.7 P13.1 P13.3 P13.5 P13.7 P14.3 P15.1 P26.1 P26.4 P26.7 P27.2 P27.4 P27.6 P17.0 P17.5 P17.7 P18.2 P33.0 P33.2 P33.4
VSSD P13.0 P13.2 P13.4 P13.6
P14.2 P15.0 P26.0 P26.3 P26.6 P27.1 P16.5 P16.6 P16.7 P17.4 P17.6 P18.1 P18.3 P18.4 VSSD
Figure 9-4
320-BGA ball map
Datasheet
32
002-21617 Rev. *K
2022-10-10
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
High-speed I/O matrix connections
10
High-speed I/O matrix connections
Table 10-1
HSIOM connections reference
Name
Number
0
Description
HSIOM_SEL_GPIO
HSIOM_SEL_GPIO_DSI
HSIOM_SEL_DSI_DSI
HSIOM_SEL_DSI_GPIO
HSIOM_SEL_AMUXA
HSIOM_SEL_AMUXB
HSIOM_SEL_AMUXA_DSI
HSIOM_SEL_AMUXB_DSI
HSIOM_SEL_ACT_0
HSIOM_SEL_ACT_1
HSIOM_SEL_ACT_2
HSIOM_SEL_ACT_3
HSIOM_SEL_DS_0
HSIOM_SEL_DS_1
HSIOM_SEL_DS_2
HSIOM_SEL_DS_3
HSIOM_SEL_ACT_4
HSIOM_SEL_ACT_5
HSIOM_SEL_ACT_6
HSIOM_SEL_ACT_7
HSIOM_SEL_ACT_8
HSIOM_SEL_ACT_9
HSIOM_SEL_ACT_10
HSIOM_SEL_ACT_11
HSIOM_SEL_ACT_12
HSIOM_SEL_ACT_13
HSIOM_SEL_ACT_14
HSIOM_SEL_ACT_15
HSIOM_SEL_DS_4
HSIOM_SEL_DS_5
HSIOM_SEL_DS_6
HSIOM_SEL_DS_7
GPIO controls 'out'
Reserved
1
2
3
4
5
6
7
8
Active functionality 0
Active functionality 1
Active functionality 2
Active functionality 3
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
DeepSleep functionality 0
DeepSleep functionality 1
DeepSleep functionality 2
DeepSleep functionality 3
Active functionality 4
Active functionality 5
Active functionality 6
Active functionality 7
Active functionality 8
Active functionality 9
Active functionality 10
Active functionality 11
Active functionality 12
Active functionality 13
Active functionality 14
Active functionality 15
DeepSleep functionality 4
DeepSleep functionality 5
DeepSleep functionality 6
DeepSleep functionality 7
Datasheet
33
002-21617 Rev. *K
2022-10-10
11
Package pin list and alternate functions
Most pins have alternate functionality, as specified in Table 11-1.
Port 11 has the following additional features,
• Ability to pass full-level analog signals to the SAR without clipping to VDDIO in cases where VDDIO < VDDA
• Ability to simultaneously capture all three ADC signals with highest priority (ADC[0:2]_M)
• Lower noise, for the most sensitive sensors
Table 11-1
Pin selector and alternate pin functions in DeepSleep (DS) mode, Analog, Smart I/O [20, 21]
Package
272-BGA
Pin
DeepSleep Mapping
HCon#29
Name
HCon#0[17]
I/O Type
320-BGA
Pin
176-TEQFP
HCon#14
DS #0[18, 19]
HCon#30
DS #2
Analog
SMARTIO
Pin
2
DS #1
P0.0
P0.1
P0.2
P0.3
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
GPIO_ENH
GPIO_ENH
GPIO_ENH
GPIO_ENH
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
A18
B18
B17
C17
A17
A16
B16
C16
C15
E15
F14
B18
SCB0_MISO (0)
SCB0_MOSI (0)
SCB0_CLK (0)
SCB0_SEL0 (0)
SCB0_MISO (1)
SCB0_MOSI (1)
SCB0_CLK (1)
SCB0_SEL0 (1)
B17
3
A17
4
SCB0_SCL (0)
B16
5
SCB0_SDA (0)
SCB0_SCL (1)
SCB0_SDA (1)
A16
6
A15
7
B15
8
C15
9
D15
NA
NA
NA
NA
10
11
12
13
14
15
NA
NA
NA
A15
B15
A14
B14
C14
E14
C13
E13
A14
SWJ_TRSTN
SCB0_SEL1 (0)
SCB0_SEL2 (0)
SCB0_SEL3 (0)
B14
C14
D14
B13
C13
D13
F12
Notes
17.HCon refers to High Speed I/O matrix connection reference as per Table 10-1.
18.DeepSleep ordering (DS #0, DS #1, DS #2) does not have any impact on choosing any alternate functions; the HSIOM module handles the individual alternate function assignment.
19.All port pin functions available in DeepSleep mode are also available in Active mode.
20.Refer to Table 14-1 for more information on pin multiplexer abbreviations used.
21.For any function marked with an identifier (n), the AC timing is only guaranteed within the respective group "n".
[20, 21]
Table 11-1
Pin selector and alternate pin functions in DeepSleep (DS) mode, Analog, Smart I/O (continued)
Package
272-BGA
Pin
A13
A12
B12
C12
D12
B11
C11
D11
A8
DeepSleep Mapping
HCon#29
Name
HCon#0[17]
I/O Type
320-BGA
Pin
A13
B13
A12
B12
C12
E12
C11
E11
A9
176-TEQFP
Pin
16
HCon#14
DS #0[18, 19]
HCon#30
DS #2
Analog
SMARTIO
DS #1
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
P4.0
P4.1
P4.2
P4.3
P4.4
P4.5
P4.6
P5.0
P5.1
P5.2
P5.3
P5.4
P5.5
P6.0
P6.1
P6.2
P6.3
P6.4
P6.5
P6.6
P6.7
P7.0
P7.1
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
17
18
19
20
21
NA
NA
24
A8
B8
25
B8
C8
26
C8
D8
27
E8
A7
28
A7
NA
NA
NA
29
B7
NA
A5
A6
B5
B6
30
C5
C6
31
A4
D6
32
B4
C5
33
C4
D5
34
A3
B4
35
ADC[0]_0
B3
C4
36
ADC[0]_1
ADC[0]_2
ADC[0]_3
ADC[0]_4
ADC[0]_5
ADC[0]_6
ADC[0]_7
ADC[0]_16
ADC[0]_17
A2
A3
37
B1
B3
38
B2
C3
39
C1
A2
40
C2
B2
41
D1
B1
42
F1
E1
48
F2
E2
49
[20, 21]
Table 11-1
Pin selector and alternate pin functions in DeepSleep (DS) mode, Analog, Smart I/O (continued)
Package
272-BGA
Pin
F1
DeepSleep Mapping
HCon#29
Name
HCon#0[17]
I/O Type
320-BGA
Pin
G1
G2
G3
G5
G6
H5
H1
H2
H3
J1
176-TEQFP
Pin
50
HCon#14
DS #0[18, 19]
HCon#30
DS #2
Analog
SMARTIO
DS #1
P7.2
P7.3
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
ADC[0]_18
F2
51
ADC[0]_19
ADC[0]_20
ADC[0]_21
ADC[0]_22
ADC[0]_23
P7.4
F3
52
P7.5
F4
53
P7.6
G1
54
P7.7
G2
55
P8.0
G3
56
P8.1
G4
57
ADC[0]_24
ADC[0]_25
ADC[0]_26
ADC[0]_27
ADC[0]_28
ADC[0]_29
ADC[0]_30
ADC[0]_31
P8.2
G6
58
P8.3
H3
59
P8.4
J2
H4
60
P9.0
K1
K2
J3
H1
61
P9.1
H2
62
P9.2
J1
63
P9.3
J5
J2
64
P10.0
P10.1
P10.2
P10.3
P10.4
P10.5
P10.6
P10.7
P11.0
P11.1
P11.2
P12.0
P12.1
P12.2
P12.3
P12.4
K5
L5
M1
N1
65
66
M5
N5
R1
N2
67
N3
68
N4
69
ADC[1]_0
ADC[1]_1
ADC[1]_2
ADC[1]_3
ADC[0]_M
ADC[1]_M
ADC[2]_M
ADC[1]_4
ADC[1]_5
ADC[1]_6
ADC[1]_7
ADC[1]_8
R2
P1
70
R3
P2
71
T1
P3
72
P5
M6
P4
73
P6
74
R5
R4
75
T2
R1
80
SMARTIO12_0
SMARTIO12_1
SMARTIO12_2
SMARTIO12_3
SMARTIO12_4
T3
R2
81
U1
U2
U3
R3
82
T1
83
T2
84
[20, 21]
Table 11-1
Pin selector and alternate pin functions in DeepSleep (DS) mode, Analog, Smart I/O (continued)
Package
272-BGA
Pin
T3
DeepSleep Mapping
HCon#29
Name
HCon#0[17]
I/O Type
320-BGA
Pin
V1
176-TEQFP
Pin
85
HCon#14
DS #0[18, 19]
HCon#30
DS #2
Analog
SMARTIO
DS #1
P12.5
P12.6
P12.7
P13.0
P13.1
P13.2
P13.3
P13.4
P13.5
P13.6
P13.7
P14.0
P14.1
P14.2
P14.3
P14.4
P14.5
P14.6
P14.7
P15.0
P15.1
P15.2
P15.3
P16.0
P16.1
P16.2
P16.3
P16.4
P16.5
P16.6
P16.7
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
ADC[1]_9
SMARTIO12_5
SMARTIO12_6
SMARTIO12_7
SMARTIO13_0
SMARTIO13_1
SMARTIO13_2
SMARTIO13_3
SMARTIO13_4
SMARTIO13_5
SMARTIO13_6
SMARTIO13_7
SMARTIO14_0
SMARTIO14_1
SMARTIO14_2
SMARTIO14_3
SMARTIO14_4
SMARTIO14_5
SMARTIO14_6
SMARTIO14_7
SMARTIO15_0
SMARTIO15_1
SMARTIO15_2
SMARTIO15_3
V2
U1
86
ADC[1]_10
ADC[1]_11
ADC[1]_12
ADC[1]_13
ADC[1]_14
ADC[1]_15
ADC[1]_16
ADC[1]_17
ADC[1]_18
ADC[1]_19
ADC[1]_20
ADC[1]_21
ADC[1]_22
ADC[1]_23
ADC[1]_24
ADC[1]_25
ADC[1]_26
ADC[1]_27
ADC[1]_28
ADC[1]_29
ADC[1]_30
ADC[1]_31
ADC[2]_0
ADC[2]_1
ADC[2]_2
ADC[2]_3
ADC[2]_4
ADC[2]_5
ADC[2]_6
ADC[2]_7
W1
Y2
U2
87
V2
90
W2
Y3
V3
91
U3
92
W3
Y4
V4
93
U4
94
W4
Y5
T4
95
U5
96
W5
V5
T5
97
V5
98
T5
V6
99
Y6
U6
100
101
102
103
104
105
106
107
108
109
NA
W6
V6
T6
R6
T6
N7
R7
T7
T7
R7
Y7
V7
W7
V7
U7
V8
T8
U8
T9
V12
U12
V13
U13
T13
R13
T14
N12
T10
T11
T12
T13
Y12
Y13
Y14
NA
NA
115
NA
NA
NA
NA
[20, 21]
Table 11-1
Pin selector and alternate pin functions in DeepSleep (DS) mode, Analog, Smart I/O (continued)
Package
272-BGA
Pin
DeepSleep Mapping
HCon#29
Name
HCon#0[17]
I/O Type
320-BGA
Pin
176-TEQFP
Pin
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
HCon#14
DS #0[18, 19]
HCon#30
DS #2
Analog
SMARTIO
DS #1
P17.0
P17.1
P17.2
P17.3
P17.4
P17.5
P17.6
P17.7
P18.0
P18.1
P18.2
P18.3
P18.4
P18.5
P18.6
P18.7
P19.0
P19.1
P19.2
P19.3
P19.4
P20.0
P20.1
P20.2
P20.3
P20.4
P20.5
P20.6
P20.7
P21.0
P21.1
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
W14
V14
T14
R14
Y15
V14
ADC[2]_8
SMARTIO17_0
SMARTIO17_1
SMARTIO17_2
SMARTIO17_3
SMARTIO17_4
SMARTIO17_5
SMARTIO17_6
SMARTIO17_7
U14
V15
ADC[2]_9
ADC[2]_10
ADC[2]_11
ADC[2]_12
ADC[2]_13
ADC[2]_14
ADC[2]_15
ADC[2]_16
ADC[2]_17
ADC[2]_18
ADC[2]_19
ADC[2]_20
ADC[2]_21
ADC[2]_22
ADC[2]_23
ADC[2]_24
ADC[2]_25
ADC[2]_26
ADC[2]_27
ADC[2]_28
ADC[2]_29
ADC[2]_30
ADC[2]_31
U15
T15
W15
Y16
V16
U16
V17
W16
V16
Y17
U18
U17
T18
W17
Y18
T17
Y19
T16
T15
T16
R16
P19
P18
P16
P15
N16
N18
M18
M16
L19
R16
R15
P15
R18
R17
P17
P16
N15
N16
M16
M15
M13
L16
L18
L16
L15
K16
J16
K16
K15
N17
N18
N19
N20
WCO_IN[22]
WCO_OUT[22]
[20, 21]
Table 11-1
Pin selector and alternate pin functions in DeepSleep (DS) mode, Analog, Smart I/O (continued)
Package
272-BGA
Pin
DeepSleep Mapping
HCon#29
Name
HCon#0[17]
I/O Type
320-BGA
Pin
M19
M20
K19
J19
H19
H18
H20
G20
F20
G19
G18
H16
G16
F19
F18
E20
E19
E18
D20
F16
G15
K3
176-TEQFP
Pin
149
150
151
157
158
159
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
NA
HCon#14
DS #0[18, 19]
HCon#30
DS #2
Analog
SMARTIO
DS #1
P21.2
P21.3
P21.4[23]
P21.5
P21.6
P21.7
P22.1
P22.2
P22.3
P22.4
P22.5
P22.6
P22.7
P23.0
P23.1
P23.2
P23.3
P23.4
P23.5
P23.6
P23.7
P24.0
P24.1
P24.2
P24.3
P24.4
P25.0
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
HSIO_STD
HSIO_STD
HSIO_STD
HSIO_STD
HSIO_STD
HSIO_STD
M17
M18
L17
K17
J17
ECO_IN[22]
ECO_OUT[22]
HIBERNATE_WAKEUP[0]
J16
RTC_CAL
H18
G18
F18
H17
H16
H15
G17
G16
G15
G13
F17
F16
F15
E18
E17
J3
EXT_PS_CTL0
EXT_PS_CTL1
EXT_PS_CTL2
SWJ_SWO_TDO
SWJ_SWCLK_TCLK
SWJ_SWDIO_TMS
SWJ_SWDOE_TDI
HIBERNATE_WAKEUP[1]
L1
J4
NA
L2
K1
NA
L3
K2
NA
M1
K3
NA
M2
K4
NA
Notes
22.I/O pins that support an oscillator function (WCO or ECO) must be configured for high-impedance if the oscillator is enabled.
23.This I/O has increased leakage to ground when the VDDD supply is below the POR threshold.
[20, 21]
Table 11-1
Pin selector and alternate pin functions in DeepSleep (DS) mode, Analog, Smart I/O (continued)
Package
272-BGA
Pin
L1
DeepSleep Mapping
HCon#29
Name
HCon#0[17]
I/O Type
320-BGA
Pin
M3
176-TEQFP
Pin
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
HCon#14
DS #0[18, 19]
HCon#30
DS #2
Analog
SMARTIO
DS #1
P25.1
P25.2
P25.3
P25.4
P25.5
P25.6
P25.7
P26.0
P26.1
P26.2
P26.3
P26.4
P26.5
P26.6
P26.7
P27.0
P27.1
P27.2
P27.3
P27.4
P27.5
P27.6
P27.7
P28.0
P28.1
P28.2
P28.3
P28.4
P28.5
P28.6
P28.7
HSIO_STD
HSIO_STD
HSIO_STD
HSIO_STD
HSIO_STD
HSIO_STD
HSIO_STD
HSIO_STD
HSIO_STD
HSIO_STD
HSIO_STD
HSIO_STD
HSIO_STD
HSIO_STD
HSIO_STD
HSIO_STD
HSIO_STD
HSIO_STD
HSIO_STD
HSIO_STD
HSIO_STD
HSIO_STD
HSIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
N1
L2
N2
L3
N3
L4
P1
M2
P2
M3
P3
M4
Y8
T8
W8
R8
V8
V9
Y9
U9
W9
T9
V9
R9
Y10
W10
V10
Y11
W11
V11
W12
V12
W13
V13
E16
D19
D18
C20
C19
B20
B19
A19
V10
U10
T10
R10
V11
U11
T11
R11
T12
R12
E16
E15
D18
D17
D16
C18
C17
C16
[20, 21]
Table 11-1
Pin selector and alternate pin functions in DeepSleep (DS) mode, Analog, Smart I/O (continued)
Package
272-BGA
Pin
A11
A10
B10
C10
D10
A9
DeepSleep Mapping
HCon#29
Name
HCon#0[17]
I/O Type
320-BGA
Pin
A11
B11
A10
B10
E10
B9
176-TEQFP
Pin
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
HCon#14
DS #0[18, 19]
HCon#30
DS #2
Analog
SMARTIO
DS #1
P29.0
P29.1
P29.2
P29.3
P29.4
P29.5
P29.6
P29.7
P30.0
P30.1
P30.2
P30.3
P31.0
P31.1
P31.2
P32.0
P32.1
P32.2
P32.3
P32.4
P32.5
P32.6
P32.7
P33.0
P33.1
P33.2
P33.3
P33.4
P33.5
P33.6
P33.7
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
GPIO_STD
HSIO_STD
HSIO_STD
HSIO_STD
HSIO_STD
HSIO_STD
HSIO_STD
HSIO_STD
HSIO_STD
C9
B9
E9
C9
C7
B7
A6
C7
B6
D7
C6
F7
E7
A5
F7
B5
E6
A4
D2
C1
ADC[0]_8
D3
C2
ADC[0]_9
E5
D1
ADC[0]_10
ADC[0]_11
ADC[0]_12
ADC[0]_13
ADC[0]_14
ADC[0]_15
E1
D2
E2
D3
E3
D4
F3
E3
F5
E4
W18
V17
W19
V18
W20
V20
V19
U20
NA
NA
NA
NA
NA
NA
NA
NA
[20, 21]
Table 11-1
Pin selector and alternate pin functions in DeepSleep (DS) mode, Analog, Smart I/O (continued)
Package
272-BGA
Pin
DeepSleep Mapping
HCon#29
Name
HCon#0[17]
I/O Type
320-BGA
Pin
176-TEQFP
HCon#14
DS #0[18, 19]
HCon#30
DS #2
Analog
SMARTIO
Pin
NA
NA
NA
NA
NA
NA
NA
NA
DS #1
P34.0
P34.1
P34.2
P34.3
P34.4
P34.5
P34.6
P34.7
HSIO_STD
HSIO_STD
HSIO_STD
HSIO_STD
HSIO_STD
HSIO_STD
HSIO_STD
HSIO_STD
U19
U18
T20
NA
NA
NA
T19
NA
T18
NA
R20
NA
R19
NA
R18
NA
12
Power pin assignments
Table 12-1
Power pin assignments
Package
272-BGA
Pin Name
VDDD
Remarks
320-BGA
176-TEQFP
F8, F9, H15, J15, K15, L15, M15, N15, R12, F8, H13, J13, K13, L13, N11
R13
176, 153, 132, 110, 43, 22
Main digital supply
VSSD
A1, A20, C3, C10, C18, H9, H10, H11, H12, A1, A18, D9, G7, G12, H9, H10, H11, J9, 155, 154, 133, 114, 89, 45, 23, Main digital ground
H13, J9, J10, J11, J12, J13, J18, K9, K10,
J10, J11, J15, K9, K10, K11, M7, M12,
1
K11, K12, K13, K18, L9, L10, L11, L12, L13, R5, R14, V1, V18
M9, M10, M11, M12, M13, N12, V3, V4, V15,
Y1, Y20
VSSD_1
N13
L11
NA
Digital Ground
VSSD_2
L20, P20
L18, P18
F9, F10, F11
N8
NA
Noise guard for ECO inputs
VDDIO_1
VDDIO_2
VDDIO_3
VDDIO_4
VSSIO_3
VSSIO_4
VCCD[24]
F10, F11, F12, F13
R8
44
I/O supply (except analog I/Os on VDDA
I/O supply (except analog I/Os on VDDA
)
)
88
H6, J6, K6, L6
R9, R10, R11
H8, J8, K8, L8
N9, N10, N11
F6, F15, R6, R15
H6, J6
NA
I/O supply for high speed domain#0 (HSIO_STD), P24, P25
N9, N10
H8, J8
NA
I/O supply for high speed domain#1 (HSIO_STD), P26, P27, P33, P34
NA
HSIO ground
HSIO ground
L9, L10
F6, F13, N6, N13
NA
46, 47, 111, 112, 113, 156
Main regulated supply. Driven by LDO regulator (either internal LDO or external
LDO/PMIC)
VREFH
VREFL
M6
M8
N6
K6
79
High reference voltage for SAR ADCs
Low reference voltage for SAR ADCs
Main analog supply for SAR ADCs
Main analog ground
K8
76
VDDA
L6
78
VSSA
N8
L8
77
XRES_L
DRV_VOUT
K20
J20
K18
J18
152
160
Active LOW external reset input
Dedicated external supply control pin
Note
24.The VCCD pins must be connected together to ensure a low-impedance connection. (see the requirement in Figure 27-2)
13
Table 13-1
Alternate function pin assignments
Alternate pin functions in Active mode [19, 27, 28]
Active Mapping
Pin
[25]
HCon#8
HCon#9
HCon#10
HCon#11
HCon#16
ACT #4
HCon#17
HCon#18
HCon#19
ACT #7
HCon#20
HCon#21
ACT #9
HCon#22
HCon#23
ACT #11
HCon#24
ACT #12
HCon#25
ACT #13
HCon#26
ACT #14
HCon#27
ACT #15
[26]
Name ACT #0
ACT #1
ACT #2
ACT #3
ACT #5
ACT #6
ACT #8
ACT #10
P0.0
P0.1
P0.2
P0.3
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P2.0
P2.1
P2.2
P2.3
PWM1_18
PWM1_17
PWM1_14
PWM1_13
PWM1_12
PWM1_11
PWM1_10
PWM1_8
PWM1_22_N
TC1_18_TR0
TC1_22_TR1
SCB0_RX (0)
SCB7_SDA (2)
LIN1_RX
PWM0_H_0
PWM1_18_N
PWM1_17_N
PWM1_14_N
PWM1_13_N
PWM1_12_N
PWM1_11_N
PWM1_10_N
PWM1_70_N
TC1_17_TR0
TC1_14_TR0
TC1_13_TR0
TC1_12_TR0
TC1_11_TR0
TC1_10_TR0
TC1_8_TR0
TC1_71_TR0
TC1_18_TR1
TC1_17_TR1
TC1_14_TR1
TC1_13_TR1
TC1_12_TR1
TC1_11_TR1
TC1_10_TR1
TC1_70_TR1
SCB0_TX (0)
SCB0_RTS (0)
SCB0_CTS (0)
SCB7_SCL (2)
LIN1_TX
PWM0_H_0_N
TC0_H_0_TR0
TC0_H_0_TR1
SCB4_MISO (2) LIN1_EN
SCB4_MOSI (2)
SCB4_CLK (2)
SCB4_SEL0 (2)
LIN0_RX
CAN0_1_TX
CAN0_1_RX
PWM1_H_4
PWM1_H_5
PWM1_H_6
PWM1_H_7
TRIG_IN[0]
TRIG_IN[1]
LIN0_TX
PWM1_71
SCB8_RX (1)
SCB8_TX (1)
SCB8_RTS (1)
SCB7_RX (0)
SCB7_TX (0)
SCB7_RTS (0)
SCB7_CTS (0)
SCB8_MISO (1)
SCB8_MOSI (1)
SCB8_CLK (1)
LIN8_RX
LIN8_TX
LIN8_EN
SCB8_SDA (1)
SCB8_SCL (1)
PWM1_7
PWM1_6
PWM1_5
PWM1_4
PWM1_8_N
PWM1_7_N
PWM1_6_N
PWM1_5_N
TC1_7_TR0
TC1_6_TR0
TC1_5_TR0
TC1_4_TR0
TC1_8_TR1
TC1_7_TR1
TC1_6_TR1
TC1_5_TR1
TC1_H_4_TR0
TC1_H_5_TR0
TC1_H_6_TR0
TC1_H_7_TR0
SCB7_MISO (0)
SCB7_MOSI (0)
SCB7_CLK (0)
SCB7_SEL0 (0)
LIN0_RX
LIN0_TX
LIN0_EN
LIN5_RX
CAN0_0_TX
CAN0_0_RX
TRIG_IN[2]
TRIG_IN[3]
TRIG_IN[4]
TRIG_IN[5]
SCB7_SDA (0)
SCB7_SCL (0)
ETH0_RX_ER (0)
ETH0_ETH_TSU_-
TIMER_CMP_VAL
(0)
P2.4
P2.5
P2.6
P2.7
P3.0
PWM1_3
PWM1_2
PWM1_72
PWM1_73
PWM1_1
PWM1_4_N
PWM1_3_N
PWM1_71_N
PWM1_72_N
PWM1_2_N
TC1_3_TR0
TC1_2_TR0
TC1_72_TR0
TC1_73_TR0
TC1_1_TR0
TC1_4_TR1
TC1_3_TR1
TC1_71_TR1
TC1_72_TR1
TC1_2_TR1
PWM1_H_4_N
PWM1_H_5_N
SCB7_SEL1 (0)
SCB7_SEL2 (0)
SCB8_SEL0 (1)
SCB8_SEL1 (1)
SCB6_MISO (0)
LIN5_TX
LIN5_EN
TRIG_IN[6]
TRIG_IN[7]
SCB8_CTS (1)
LIN11_RX
PWM1_H_6_N
PWM1_H_7_N
TC1_H_4_TR1
SCB6_RX (0)
SCB6_TX (0)
CAN0_3_TX
CAN0_3_RX
ETH0_MDIO (0)
ETH0_MDC (0)
TRIG_DBG
[0]
P3.1
PWM1_0
PWM1_1_N
TC1_0_TR0
TC1_1_TR1
TC1_0_TR1
SCB6_SDA (0)
SCB6_SCL (0)
SCB6_MOSI (0)
TRIG_DBG
[1]
P3.2
P3.3
P3.4
PWM1_M_3 PWM1_0_N
TC1_M_3_TR0
SCB6_RTS (0)
SCB6_CTS (0)
SCB6_CLK (0)
SCB6_SEL0 (0)
SCB6_SEL1 (0)
PWM1_M_2 PWM1_M_3_N TC1_M_2_TR0
PWM1_M_1 PWM1_M_2_N TC1_M_1_TR0
TC1_M_3_TR1 TC1_H_5_TR1
TC1_M_2_TR1 TC1_H_6_TR1
LIN1_RX
Notes
25.High Speed I/O matrix connection (HCon) reference as per Table 10-1.
26.Active Mode ordering (ACT #0, ACT #1, and so on) does not have any impact on configuring alternate functions; the HSIOM module handles the alternate function assignments.
27.Refer to Table 14-1 for more information on pin multiplexer abbreviations used.
28.For any function marked with an identifier (n), the AC timing is only guaranteed within the respective group "n".
[19, 27, 28]
Table 13-1
Alternate pin functions in Active mode (continued)
Active Mapping
Pin
[25]
HCon#8
HCon#9
ACT #1
HCon#10
ACT #2
HCon#11
ACT #3
HCon#16
ACT #4
HCon#17
ACT #5
HCon#18
ACT #6
HCon#19
HCon#20
HCon#21
ACT #9
HCon#22
ACT #10
HCon#23
ACT #11
HCon#24
ACT #12
HCon#25
ACT #13
HCon#26
ACT #14
HCon#27
ACT #15
[26]
Name ACT #0
ACT #7
ACT #8
P3.5
P3.6
P3.7
P4.0
P4.1
P4.2
P4.3
P4.4
P4.5
P4.6
P5.0
P5.1
P5.2
P5.3
P5.4
P5.5
P6.0
P6.1
P6.2
PWM1_M_0 PWM1_M_1_N TC1_M_0_TR0
TC1_M_1_TR1 TC1_H_7_TR1
TC1_73_TR1
SCB6_SEL2 (0)
LIN1_TX
PWM1_74
PWM1_75
PWM1_4
PWM1_5
PWM1_6
PWM1_7
PWM1_8
PWM1_73_N
PWM1_74_N
TC1_74_TR0
TC1_75_TR0
SCB8_SEL2 (0)
LIN11_TX CAN1_2_TX
LIN11_EN CAN1_2_RX
LIN1_RX
TC1_74_TR1
PWM1_M_0_N TC1_4_TR0
TC1_M_0_TR1 EXT_MUX[0]_0
SCB5_RX (0)
SCB5_TX (0)
SCB5_RTS (0)
SCB5_MISO (0)
SCB5_MOSI (0)
SCB5_CLK (0)
SCB5_SEL0 (0)
SCB5_SEL1 (0)
SCB9_MISO (1)
SCB9_MOSI (1)
SCB5_SEL2 (0)
SCB9_SEL3 (1)
TRIG_IN[10]
TRIG_IN[11]
TRIG_IN[12]
TRIG_IN[13]
PWM1_4_N
PWM1_5_N
PWM1_6_N
PWM1_7_N
TC1_5_TR0
TC1_6_TR0
TC1_7_TR0
TC1_8_TR0
TC1_4_TR1
TC1_5_TR1
TC1_6_TR1
TC1_7_TR1
EXT_MUX[0]_1
EXT_MUX[0]_2
SCB5_SDA (0)
SCB5_SCL (0)
LIN1_TX
LIN1_EN
EXT_MUX[0]_EN SCB5_CTS (0)
CAN0_1_TX
LIN15_RX
CAN0_1_RX
SCB9_RX (1)
SCB9_TX (1)
TRIG_IN[32]
TRIG_IN[33]
TRIG_IN[38]
TRIG_IN[39]
SCB9_SDA (1)
LIN15_TX
PWM1_9
PWM1_8_N
PWM1_9_N
PWM1_10_N
PWM1_11_N
PWM1_12_N
PWM1_13_N
TC1_9_TR0
TC1_8_TR1
TC1_9_TR1
TC1_10_TR1
TC1_11_TR1
TC1_12_TR1
TC1_13_TR1
TC1_14_TR1
PWM1_H_10
LIN7_RX
LIN7_TX
LIN7_EN
LIN2_RX
LIN2_TX
LIN2_EN
LIN3_RX
LIN3_TX
PWM0_M_0
PWM1_10
PWM1_11
PWM1_12
PWM1_13
PWM1_14
TC1_10_TR0
TC1_11_TR0
TC1_12_TR0
TC1_13_TR0
TC1_14_TR0
TC1_M_0_TR0
PWM1_H_10_N
TC1_H_10_TR0
TC1_H_10_TR1
PWM1_H_11
PWM0_M_0_N
TC0_M_0_TR0
TC0_M_0_TR1
LIN10_RX
LIN10_TX
LIN9_RX
LIN9_TX
LIN9_EN
PWM1_H_11_N
PWM1_M_0 PWM1_14_N
PWM1_0
PWM1_M_1 PWM1_0_N
TC1_H_11_TR0
SCB4_RX (0)
SCB4_TX (0)
SCB4_RTS (0)
SCB4_MISO (0)
SCB4_MOSI (0)
SCB4_CLK (0)
PWM0_0
PWM1_M_0_N TC1_0_TR0
TC1_M_1_TR0
TC1_M_0_TR1 TC1_H_11_TR1
TC1_0_TR1 PWM1_H_12
SCB4_SDA (0)
SCB4_SCL (0)
LIN3_EN
CAN0_2_TX
CAN0_2_RX
PWM0_0_N
SDHC_CARD_-
MECH_WRITE_PROT
(0)
P6.3
P6.4
P6.5
PWM1_1
PWM1_M_2 PWM1_1_N
PWM1_2 PWM1_M_2_N TC1_2_TR0
PWM1_M_3 PWM1_2_N TC1_M_3_TR0
PWM1_3 PWM1_M_3_N TC1_3_TR0
PWM1_M_4 PWM1_3_N TC1_M_4_TR0
PWM1_15 PWM1_M_4_N TC1_15_TR0
PWM1_M_5 PWM1_15_N TC1_M_5_TR0
PWM1_16 PWM1_M_5_N TC1_16_TR0
PWM1_M_1_N TC1_1_TR0
TC1_M_1_TR1 PWM1_H_12_N
TC1_1_TR1 TC1_H_12_TR0
SCB4_CTS (0)
SCB4_SEL0 (0)
SCB4_SEL1 (0)
SCB4_SEL2 (0)
SCB4_SEL3 (0)
LIN4_RX
LIN4_TX
LIN4_EN
SPIHB_CL
K (0)
SDHC_CARD_CMD (0)
CAL_SUP_
NZ
TC1_M_2_TR0
TC0_0_TR0
TC0_0_TR1
SPIHB_R
WDS (0)
SDHC_CLK_CARD (0)
TC1_M_2_TR1 TC1_H_12_TR1
SPIHB_SE
L0 (0)
SDHC_CARD_DE-
TECT_N (0)
P6.6
P6.7
P7.0
TC1_2_TR1
TC1_M_3_TR1
TC1_3_TR1
TRIG_IN[8]
TRIG_IN[9]
SCB5_RX (1)
SCB5_TX (1)
SCB5_RTS (1)
SCB5_CTS (1)
SCB5_MISO (1)
SCB5_MOSI (1)
SCB5_CLK (1)
SCB5_SEL0 (1)
LIN4_RX
LIN4_TX
LIN4_EN
PWM0_1
SPIHB_SE
L1 (0)
SDHC_CARD_IF_P-
WR_EN (0)
P7.1
P7.2
P7.3
TC1_M_4_TR1
TC1_15_TR1
TC1_M_5_TR1
SCB5_SDA (1)
SCB5_SCL (1)
SPIHB_-
SDHC_CARD_DAT_3-
TO0_0 (0)
DATA0 (0)
PWM0_1_N
TC0_1_TR0
SPIHB_-
SDHC_CARD_DAT_3-
TO0_1 (0)
DATA1 (0)
CAN0_4_TX
SPIHB_-
SDHC_CARD_DAT_3-
TO0_2 (0)
DATA2 (0)
[19, 27, 28]
Table 13-1
Alternate pin functions in Active mode (continued)
Active Mapping
Pin
[25]
HCon#8
HCon#9
ACT #1
HCon#10
HCon#11
HCon#16
ACT #4
HCon#17
ACT #5
HCon#18
ACT #6
HCon#19
HCon#20
ACT #8
HCon#21
HCon#22
HCon#23
ACT #11
HCon#24
ACT #12
HCon#25
ACT #13
HCon#26
ACT #14
HCon#27
ACT #15
[26]
Name ACT #0
ACT #2
ACT #3
ACT #7
ACT #9
ACT #10
P7.4
P7.5
PWM1_M_6 PWM1_16_N
PWM1_17
PWM1_M_7 PWM1_17_N
TC1_M_6_TR0
TC1_16_TR1
SCB5_SEL1 (1)
CAN0_4_RX
TC0_1_TR1
SPIHB_-
SDHC_CARD_DAT_3-
TO0_3 (0)
DATA3 (0)
PWM1_M_6_N TC1_17_TR0
TC1_M_7_TR0
PWM1_M_7_N TC1_18_TR0
TC1_M_6_TR1
LIN10_RX
SCB5_SEL2 (1)
PWM0_H_2
SPIHB_-
SDHC_CARD_DAT_7-
TO4_0 (0)
DATA4 (0)
P7.6
P7.7
P8.0
TC1_17_TR1
TC1_M_7_TR1
TC1_18_TR1
LIN10_TX
LIN10_EN
TRIG_IN[16]
TRIG_IN[17]
PWM1_18
PWM1_19
PWM1_18_N
PWM1_19_N
PWM1_20_N
PWM1_21_N
PWM1_22_N
TC1_19_TR0
TC1_20_TR0
TC1_21_TR0
TC1_22_TR0
TC1_23_TR0
PWM1_H_8
LIN2_RX
LIN2_TX
LIN2_EN
LIN16_RX
LIN16_TX
LIN16_EN
CAN0_0_TX
CAN0_0_RX
PWM0_H_2_N SPIHB_-
DATA5 (0)
SDHC_CARD_DAT_7-
TO4_1 (0)
P8.1
P8.2
P8.3
P8.4
PWM1_20
PWM1_21
PWM1_22
PWM1_23
TC1_19_TR1
TC1_20_TR1
TC1_21_TR1
TC1_22_TR1
PWM1_H_8_N
TC1_H_8_TR0
TC1_H_8_TR1
TC0_H_2_TR0
SPIHB_-
SDHC_CARD_DAT_7- TRIG_IN[14]
TO4_2 (0)
DATA6 (0)
TC0_H_2_TR1
SPIHB_-
SDHC_CARD_DAT_7- TRIG_IN[15]
TO4_3 (0)
DATA7 (0)
TRIG_DBG
[0]
TRIG_DBG
[1]
P9.0
P9.1
P9.2
P9.3
PWM1_24
PWM1_25
PWM1_26
PWM1_27
PWM1_23_N
PWM1_24_N
PWM1_25_N
PWM1_26_N
PWM1_27_N
PWM1_28_N
PWM1_29_N
TC1_24_TR0
TC1_25_TR0
TC1_26_TR0
TC1_27_TR0
TC1_28_TR0
TC1_29_TR0
TC1_30_TR0
TC1_23_TR1
TC1_24_TR1
TC1_25_TR1
TC1_26_TR1
TC1_27_TR1
TC1_28_TR1
TC1_29_TR1
PWM1_H_9
PWM1_H_9_N
TC1_H_9_TR0
TC1_H_9_TR1
PWM1_H_10
PWM1_H_10_N
TC1_H_10_TR0
LIN12_RX
LIN12_TX
LIN12_EN
P10.0 PWM1_28
P10.1 PWM1_29
P10.2 PWM1_30
SCB4_RX (1)
SCB4_TX (1)
SCB4_RTS (1)
SCB4_MISO (1)
SCB4_MOSI (1)
SCB4_CLK (1)
LIN7_RX
LIN7_TX
TRIG_IN[18]
TRIG_IN[19]
SCB4_SDA (1)
SCB4_SCL (1)
LIN8_RX
LIN8_TX
LIN8_EN
FLEXRAY_R
XDA
P10.3 PWM1_31
P10.4 PWM1_32
P10.5 PWM1_33
P10.6
PWM1_30_N
PWM1_31_N
PWM1_32_N
PWM1_33_N
PWM1_34_N
TC1_31_TR0
TC1_32_TR0
TC1_33_TR0
TC1_30_TR1
TC1_31_TR1
TC1_32_TR1
TC1_33_TR1
TC1_34_TR1
TC1_H_10_TR1
PWM1_H_11
SCB4_CTS (1)
SCB4_SEL0 (1)
SCB4_SEL1 (1)
SCB4_SEL2 (1)
TC1_34_TR0
FLEXRAY_T
XDA
FLEXRAY_T
XENA_N
PWM1_H_11_N
TC1_H_11_TR0
TC1_H_11_TR1
LIN13_RX
LIN13_TX
LIN13_EN
FLEXRAY_R
XDB
PWM1_34
FLEXRAY_T
XDB
P10.7 PWM1_35
TC1_35_TR0
FLEXRAY_T
XENB_N
P11.0 PWM1_61
P11.1 PWM1_60
P11.2 PWM1_59
P12.0 PWM1_36
PWM1_62_N
PWM1_61_N
PWM1_60_N
TC1_61_TR0
TC1_60_TR0
TC1_59_TR0
TC1_36_TR0
TC1_62_TR1
TC1_61_TR1
TC1_60_TR1
AUDIOSS0_MCLK
AUDIOSS0_TX_SCK
AUDIOSS0_TX_WS
SCB8_RX (0)
SCB8_TX (0)
TC1_35_TR1
SCB8_SDA (0)
SCB8_SCL (0)
SCB8_MISO (0)
SCB8_MOSI (0)
SCB8_CLK (0)
CAN0_2_TX
CAN0_2_RX
PWM0_H_1
PWM1_35
_N
AUDIOSS0_TX_SDO
TRIG_IN[20]
TRIG_IN[21]
P12.1 PWM1_37
P12.2 PWM1_38
PWM1_36_N
PWM1_37_N
TC1_37_TR0
TC1_38_TR0
TC1_36_TR1
TC1_37_TR1
LIN6_EN
LIN6_RX
PWM0_H_1_N
TC0_H_1_TR0
AUDIOSS0_-
CLK_I2S_IF
EXT_MUX[1]_EN SCB8_RTS (0)
AUDIOSS0_RX_SCK
[19, 27, 28]
Table 13-1
Alternate pin functions in Active mode (continued)
Active Mapping
Pin
[25]
HCon#8
HCon#9
HCon#10
HCon#11
HCon#16
HCon#17
HCon#18
ACT #6
HCon#19
HCon#20
HCon#21
ACT #9
HCon#22
HCon#23
ACT #11
HCon#24
ACT #12
HCon#25
HCon#26
ACT #14
HCon#27
ACT #15
[26]
Name ACT #0
ACT #1
ACT #2
ACT #3
ACT #4
ACT #5
ACT #7
ACT #8
ACT #10
ACT #13
P12.3 PWM1_39
PWM1_38_N
TC1_39_TR0
TC1_38_TR1
EXT_MUX[1]_0
SCB8_CTS (0)
SCB8_SEL0 (0)
LIN6_TX
TC0_H_1_TR1
AUDIOSS0_RX_WS
P12.4 PWM1_40
P12.5 PWM1_41
P12.6 PWM1_42
P12.7 PWM1_43
PWM1_39_N
PWM1_40_N
PWM1_41_N
PWM1_42_N
TC1_40_TR0
TC1_41_TR0
TC1_42_TR0
TC1_43_TR0
TC1_M_8_TR0
TC1_39_TR1
TC1_40_TR1
TC1_41_TR1
TC1_42_TR1
TC1_43_TR1
EXT_MUX[1]_1
EXT_MUX[1]_2
SCB8_SEL1 (0)
CAN1_1_TX
CAN1_1_RX
TC0_2_TR1
AUDIOSS0_RX_SDI
P13.0 PWM1_M_8 PWM1_43_N
P13.1 PWM1_44
P13.2 PWM1_M_9 PWM1_44_N
P13.3 PWM1_45 PWM1_M_9_N TC1_45_TR0
EXT_MUX[2]_0
SCB3_RX (0)
SCB3_TX (0)
SCB3_RTS (0)
LIN3_RX
LIN3_TX
LIN3_EN
LIN2_RX
LIN2_TX
SCB3_MISO (0) TC0_2_TR0
SCB3_MOSI (0) PWM0_2_N
SCB3_CLK (0) PWM0_2
SCB3_SEL0 (0)
AUDIOSS1_MCLK
AUDIOSS1_TX_SCK
AUDIOSS1_TX_WS
AUDIOSS1_TX_SDO
PWM1_M_8_N TC1_44_TR0
TC1_M_9_TR0
TC1_M_8_TR1 EXT_MUX[2]_1
TC1_44_TR1 EXT_MUX[2]_2
SCB3_SDA (0)
SCB3_SCL (0)
TC1_M_9_TR1 EXT_MUX[2]_EN SCB3_CTS (0)
P13.4 PWM1_M_1 PWM1_45_N
0
TC1_M_10_TR0 TC1_45_TR1
PWM1_H_4
SCB3_SEL1 (0) LIN8_RX
AUDIOSS1_-
CLK_I2S_IF
P13.5 PWM1_46
PWM1_M_10_ TC1_46_TR0
TC1_M_10_TR PWM1_H_4_N
1
SCB3_SEL2 (0) LIN8_TX
SCB3_SEL3 (0) LIN8_EN
AUDIOSS1_RX_SCK
AUDIOSS1_RX_WS
AUDIOSS1_RX_SDI
N
P13.6 PWM1_M_1 PWM1_46_N
1
TC1_M_11_TR0 TC1_46_TR1
PWM1_H_5
TRIG_IN[22]
TRIG_IN[23]
P13.7 PWM1_47
PWM1_M_11_ TC1_47_TR0
TC1_M_11_TR PWM1_H_5_N
1
N
P14.0 PWM1_48
P14.1 PWM1_49
P14.2 PWM1_50
P14.3 PWM1_51
P14.4 PWM1_52
P14.5 PWM1_53
P14.6 PWM1_54
P14.7 PWM1_55
P15.0 PWM1_56
PWM1_47_N
TC1_48_TR0
TC1_49_TR0
TC1_50_TR0
TC1_51_TR0
TC1_52_TR0
TC1_53_TR0
TC1_54_TR0
TC1_55_TR0
TC1_56_TR0
TC1_47_TR1
TC1_48_TR1
TC1_49_TR1
TC1_50_TR1
TC1_51_TR1
TC1_52_TR1
TC1_53_TR1
TC1_54_TR1
TC1_55_TR1
PWM1_H_6
SCB2_MISO (0)
SCB2_MOSI (0) SCB2_SDA (0)
SCB2_RX (0)
SCB2_TX (0)
SCB2_RTS (0)
SCB2_CTS (0)
CAN1_0_TX
CAN1_0_RX
PWM0_M_1
AUDIOSS2_MCLK
PWM1_48_N
PWM1_49_N
PWM1_50_N
PWM1_51_N
PWM1_52_N
PWM1_53_N
PWM1_54_N
PWM1_55_N
PWM1_H_6_N
PWM1_H_7
PWM0_M_1_N
TC0_M_1_TR0
TC0_M_1_TR1
AUDIOSS2_TX_SCK
SCB2_CLK (0)
SCB2_SEL0 (0)
SCB2_SEL1 (0)
SCB2_SCL (0)
LIN6_RX
LIN6_TX
LIN6_EN
PWM1_H_7_N
TC1_H_4_TR0
TC1_H_4_TR1
TC1_H_5_TR0
TC1_H_5_TR1
TC1_H_6_TR0
AUDIOSS2_TX_WS
AUDIOSS2_TX_SDO
SCB2_SEL2 (0) LIN14_RX
LIN14_TX
TRIG_IN[24]
TRIG_IN[25]
LIN14_EN
SCB9_RX (0)
SCB9_MISO (0)
CAN1_3_TX
CAN1_3_RX
AUDIOSS2_-
CLK_I2S_IF
P15.1 PWM1_57
P15.2 PWM1_58
P15.3 PWM1_59
P16.0 PWM1_60
P16.1 PWM1_61
P16.2 PWM1_62
P16.3 PWM1_62
PWM1_56_N
PWM1_57_N
PWM1_58_N
PWM1_59_N
PWM1_60_N
PWM1_61_N
PWM1_62_N
TC1_57_TR0
TC1_58_TR0
TC1_59_TR0
TC1_60_TR0
TC1_61_TR0
TC1_62_TR0
TC1_62_TR0
TC1_56_TR1
TC1_57_TR1
TC1_58_TR1
TC1_59_TR1
TC1_60_TR1
TC1_61_TR1
TC1_62_TR1
TC1_H_6_TR1
TC1_H_7_TR0
TC1_H_7_TR1
PWM1_H_0
SCB9_TX (0)
SCB9_RTS (0)
SCB9_CTS (0)
SCB9_SDA (0)
SCB9_SCL (0)
SCB9_MOSI (0)
SCB9_CLK (0)
SCB9_SEL0 (0)
SCB9_SEL1 (0)
SCB9_SEL2 (0)
SCB9_SEL3 (0)
AUDIOSS2_RX_SCK
AUDIOSS2_RX_WS
AUDIOSS2_RX_SDI
LIN11_RX
LIN11_TX
LIN11_EN
PWM1_H_0_N
PWM1_H_1
PWM1_H_1_N
[19, 27, 28]
Table 13-1
Alternate pin functions in Active mode (continued)
Active Mapping
Pin
[25]
HCon#8
HCon#9
HCon#10
HCon#11
HCon#16
ACT #4
HCon#17
ACT #5
HCon#18
ACT #6
HCon#19
ACT #7
HCon#20
ACT #8
HCon#21
ACT #9
HCon#22
ACT #10
HCon#23
ACT #11
HCon#24
ACT #12
HCon#25
ACT #13
HCon#26
ACT #14
HCon#27
ACT #15
[26]
Name ACT #0
ACT #1
ACT #2
ACT #3
P16.4 PWM1_68
PWM1_69_N
TC1_68_TR0
TC1_69_TR1
P16.5 PWM1_67
P16.6 PWM1_66
P16.7 PWM1_65
P17.0 PWM1_61
P17.1 PWM1_60
P17.2 PWM1_59
P17.3 PWM1_58
P17.4 PWM1_57
P17.5 PWM1_56
PWM1_68_N
PWM1_67_N
PWM1_66_N
PWM1_62_N
PWM1_61_N
PWM1_60_N
PWM1_59_N
PWM1_58_N
PWM1_57_N
TC1_67_TR0
TC1_66_TR0
TC1_65_TR0
TC1_61_TR0
TC1_60_TR0
TC1_59_TR0
TC1_58_TR0
TC1_57_TR0
TC1_56_TR0
TC1_M_4_TR0
TC1_68_TR1
TC1_67_TR1
TC1_66_TR1
TC1_62_TR1
TC1_61_TR1
TC1_60_TR1
TC1_59_TR1
TC1_58_TR1
TC1_57_TR1
TC1_56_TR1
TC1_M_4_TR1
LIN11_RX CAN1_1_TX
LIN11_TX CAN1_1_RX
LIN11_EN
SCB3_RX (1)
SCB3_TX (1)
SCB3_RTS (1)
SCB3_CTS (1)
SCB3_SDA (1)
SCB3_SCL (1)
PWM1_H_3
SCB3_CLK (1)
SCB3_SEL0 (1)
SCB3_SEL1 (1)
SCB3_SEL2 (1)
LIN12_RX
TRIG_IN[26]
TRIG_IN[27]
PWM1_H_3_N
PWM1_H_2
LIN15_RX
LIN15_TX
LIN15_EN
P17.6 PWM1_M_4 PWM1_56_N
PWM1_H_2_N
P17.7 PWM1_M_5 PWM1_M_4_N TC1_M_5_TR0
P18.0 PWM1_M_6 PWM1_M_5_N TC1_M_6_TR0
TC1_M_5_TR1 PWM1_H_0
TC1_M_6_TR1 PWM1_H_0_N
TC1_M_7_TR1 PWM1_H_1
SCB1_RX (0)
SCB1_TX (0)
SCB1_MISO (0)
SCB1_MOSI (0)
LIN12_TX
ETH0_REF_CLK
(0)
FAULT_O
UT_0
P18.1 PWM1_M_7 PWM1_M_6_N TC1_M_7_TR0
SCB1_SDA (0)
SCB1_SCL (0)
SCB3_MISO (1)
ETH0_TX_CTL (0)
FAULT_O
UT_1
P18.2 PWM1_55
P18.3 PWM1_54
PWM1_M_7_N TC1_55_TR0
SCB1_RTS (0)
SCB1_CTS (0)
SCB1_CLK (0)
SCB1_SEL0 (0)
SCB3_MOSI (1)
SCB3_CLK (2)
ETH0_TX_ER (0)
ETH0_TX_CLK (0)
PWM1_55_N
PWM1_54_N
PWM1_53_N
PWM1_52_N
PWM1_51_N
TC1_54_TR0
TC1_53_TR0
TC1_52_TR0
TC1_51_TR0
TC1_50_TR0
TC1_M_3_TR0
TC1_55_TR1
TC1_54_TR1
TC1_53_TR1
TC1_52_TR1
TC1_51_TR1
TC1_50_TR1
PWM1_H_1_N
PWM1_H_2
TRACE_-
CLOCK (0)
P18.4 PWM1_53
P18.5 PWM1_52
P18.6 PWM1_51
P18.7 PWM1_50
SCB1_SEL1 (0)
SCB1_SEL2 (0)
SCB1_SEL3 (0)
SCB3_SEL0 (2) PWM0_M_2
PWM0_M_2_N
ETH0_TXD_0 (0)
ETH0_TXD_1 (0)
ETH0_TXD_2 (0)
ETH0_TXD_3 (0)
ETH0_RXD_0 (0)
ETH0_RXD_1 (0)
TRACE_-
DATA_0 (0)
PWM1_H_2_N
PWM1_H_3
TRACE_-
DATA_1 (0)
CAN1_2_TX
CAN1_2_RX
CAN1_3_TX
CAN1_3_RX
TC0_M_2_TR0
TC0_M_2_TR1
TRACE_-
DATA_2 (0)
PWM1_H_3_N
TC1_H_0_TR0
TRACE_-
DATA_3 (0)
P19.0 PWM1_M_3 PWM1_50_N
SCB2_MISO (1)
SCB2_RX (1)
SCB2_TX (1)
FAULT_O
UT_2
P19.1 PWM1_26
PWM1_M_3_N TC1_26_TR0
TC1_M_3_TR1 TC1_H_0_TR1
SCB2_MOSI (1) SCB2_SDA (1)
FAULT_O
UT_3
P19.2 PWM1_27
P19.3 PWM1_28
P19.4 PWM1_29
P20.0 PWM1_30
P20.1 PWM1_49
P20.2 PWM1_48
PWM1_26_N
PWM1_27_N
PWM1_28_N
PWM1_29_N
PWM1_30_N
PWM1_49_N
TC1_27_TR0
TC1_28_TR0
TC1_29_TR0
TC1_30_TR0
TC1_49_TR0
TC1_48_TR0
TC1_26_TR1
TC1_27_TR1
TC1_28_TR1
TC1_29_TR1
TC1_30_TR1
TC1_49_TR1
TC1_H_1_TR0
TC1_H_1_TR1
TC1_H_2_TR0
TC1_H_2_TR1
TC1_H_3_TR0
TC1_H_3_TR1
SCB2_CLK (1)
SCB2_SEL0 (1)
SCB2_SEL1 (1)
SCB2_SEL2 (1)
SCB2_SCL (1)
SCB2_RTS (1)
SCB2_CTS (1)
ETH0_RXD_2 (0)
ETH0_RXD_3 (0)
TRIG_IN[28]
TRIG_IN[29]
LIN5_RX
LIN5_TX
LIN5_EN
[19, 27, 28]
Table 13-1
Alternate pin functions in Active mode (continued)
Active Mapping
Pin
[25]
HCon#8
HCon#9
HCon#10
HCon#11
HCon#16
ACT #4
HCon#17
HCon#18
ACT #6
HCon#19
HCon#20
ACT #8
HCon#21
HCon#22
ACT #10
HCon#23
ACT #11
HCon#24
ACT #12
HCon#25
ACT #13
HCon#26
ACT #14
HCon#27
ACT #15
[26]
Name ACT #0
ACT #1
ACT #2
ACT #3
ACT #5
ACT #7
ACT #9
P20.3 PWM1_47
PWM1_48_N
TC1_47_TR0
TC1_48_TR1
SCB1_RX (1)
SCB1_MISO (1)
CAN1_2_TX
P20.4 PWM1_46
P20.5 PWM1_45
P20.6 PWM1_44
P20.7 PWM1_43
P21.0 PWM1_42
P21.1 PWM1_41
P21.2 PWM1_40
PWM1_47_N
PWM1_46_N
PWM1_45_N
PWM1_44_N
PWM1_43_N
PWM1_42_N
PWM1_41_N
TC1_46_TR0
TC1_45_TR0
TC1_44_TR0
TC1_43_TR0
TC1_42_TR0
TC1_41_TR0
TC1_40_TR0
TC1_47_TR1
TC1_46_TR1
TC1_45_TR1
TC1_44_TR1
TC1_43_TR1
TC1_42_TR1
TC1_41_TR1
SCB1_TX (1)
SCB1_RTS (1)
SCB1_CTS (1)
SCB1_SDA (1)
SCB1_SCL (1)
SCB1_MOSI (1)
SCB1_CLK (1)
SCB1_SEL0 (1)
SCB1_SEL1 (1)
SCB1_SEL2 (1)
CAN1_2_RX
CAN1_4_TX
CAN1_4_RX
EXT_CLK
TRIG_DBG
[1]
P21.3 PWM1_39
P21.4 PWM1_38
P21.5 PWM1_37
PWM1_40_N
PWM1_39_N
PWM1_38_N
TC1_39_TR0
TC1_38_TR0
TC1_37_TR0
TC1_40_TR1
TC1_39_TR1
TC1_38_TR1
TC1_35_TR1
TC1_34_TR0
LIN0_RX
CAN1_1_TX
PWM1_34
PWM1_35 ETH0_RX_CTL (0)
_N
TRACE_-
DATA_0 (1)
P21.6 PWM1_36
P21.7 PWM1_35
PWM1_37_N
PWM1_36_N
TC1_36_TR0
TC1_35_TR0
TC1_37_TR1
TC1_36_TR1
LIN0_TX
LIN0_EN
LIN13_RX
LIN13_TX
SCB6_RX (1)
SCB6_TX (1)
SCB6_RTS (1)
SCB6_CTS (1)
SCB6_MISO (1)
SCB6_MOSI (1)
SCB6_CLK (1)
SCB6_SEL0 (1)
SCB6_SEL1 (1)
SCB6_SEL2 (1)
CAL_SUP_
NZ
P22.1 PWM1_33
P22.2 PWM1_32
P22.3 PWM1_31
P22.4 PWM1_30
PWM1_34_N
PWM1_33_N
PWM1_32_N
PWM1_31_N
TC1_33_TR0
TC1_32_TR0
TC1_31_TR0
TC1_30_TR0
TC1_34_TR1
TC1_33_TR1
TC1_32_TR1
TC1_31_TR1
SCB6_SDA (1)
SCB6_SCL (1)
CAN1_1_RX
TRACE_-
DATA_1 (1)
TRACE_-
DATA_2 (1)
TRACE_-
DATA_3 (1)
TRACE_-
CLOCK (1)
P22.5 PWM1_29
P22.6 PWM1_28
P22.7 PWM1_27
PWM1_30_N
PWM1_29_N
PWM1_28_N
TC1_29_TR0
TC1_28_TR0
TC1_27_TR0
TC1_M_8_TR0
TC1_30_TR1
TC1_29_TR1
TC1_28_TR1
TC1_27_TR1
PWM1_H_8
LIN7_RX
LIN7_TX
LIN7_EN
PWM1_H_8_N
TC1_H_8_TR0
TC1_H_8_TR1
LIN14_RX
LIN14_TX
P23.0 PWM1_M_8 PWM1_27_N
SCB7_RX (1)
SCB7_TX (1)
SCB7_RTS (1)
SCB7_CTS (1)
SCB2_MISO (2)
SCB7_MISO (1)
SCB7_MOSI (1)
SCB7_CLK (1)
SCB7_SEL0 (1)
SCB7_SEL1 (1)
SCB7_SEL2 (1)
CAN1_0_TX
CAN1_0_RX
FAULT_O
UT_0
P23.1 PWM1_M_9 PWM1_M_8_N TC1_M_9_TR0
TC1_M_8_TR1
SCB7_SDA (1)
SCB7_SCL (1)
FAULT_O
UT_1
P23.2 PWM1_M_1 PWM1_M_9_N TC1_M_10_TR0 TC1_M_9_TR1
0
LIN6_RX
LIN6_TX
FAULT_O
UT_2
P23.3 PWM1_M_1 PWM1_M_10_ TC1_M_11_TR0 TC1_M_10_TR
ETH0_RX_CLK (0)
TRIG_IN[30] FAULT_O
UT_3
1
N
1
P23.4 PWM1_25
PWM1_M_11_ TC1_25_TR0
N
TC1_M_11_TR PWM1_H_9
1
TRIG_IN[31] TRIG_DBG
[0]
P23.5 PWM1_24
P23.6 PWM1_23
PWM1_25_N
PWM1_24_N
TC1_24_TR0
TC1_23_TR0
TC1_25_TR1
TC1_24_TR1
PWM1_H_9_N
TC1_H_9_TR0
SCB2_MOSI (2)
SCB2_CLK (2)
LIN9_RX
LIN9_TX
[19, 27, 28]
Table 13-1
Alternate pin functions in Active mode (continued)
Active Mapping
Pin
[25]
HCon#8
HCon#9
HCon#10
HCon#11
HCon#16
HCon#17
HCon#18
ACT #6
HCon#19
ACT #7
HCon#20
ACT #8
HCon#21
ACT #9
HCon#22
ACT #10
HCon#23
HCon#24
ACT #12
HCon#25
ACT #13
HCon#26
ACT #14
HCon#27
ACT #15
[26]
Name ACT #0
ACT #1
ACT #2
ACT #3
ACT #4
ACT #5
ACT #11
P23.7 PWM1_22
PWM1_23_N
TC1_22_TR0
TC1_23_TR1
TC1_H_9_TR1
SCB2_SEL0 (2)
EXT_CLK
EXT_CLK
LIN9_EN
CAL_SUP_
NZ
P24.0
P24.1
LIN16_RX
SDHC_CARD_DE-
TECT_N (1)
SPIHB_CL
K (1)
SDHC_CARD_-
MECH_WRITE_PROT
(1)
P24.2
P24.3
P24.4
P25.0
P25.1
P25.2
P25.3
P25.4
P25.5
P25.6
P25.7
P26.0
P26.1
P26.2
P26.3
P26.4
P26.5
P26.6
P26.7
P27.0
P27.1
SPIHB_R
WDS (1)
SDHC_CLK_CARD (1)
LIN16_TX
LIN16_EN
SPIHB_SE
L0 (1)
SDHC_CARD_CMD (1)
SPIHB_SE
L1 (1)
SDHC_CARD_IF_P-
WR_EN (1)
SPIHB_-
SDHC_CARD_DAT_3-
TO0_0 (1)
DATA0 (1)
SPIHB_-
SDHC_CARD_DAT_3-
TO0_1 (1)
DATA1 (1)
SPIHB_-
SDHC_CARD_DAT_3-
TO0_2 (1)
DATA2 (1)
SPIHB_-
SDHC_CARD_DAT_3-
TO0_3 (1)
DATA3 (1)
SPIHB_-
SDHC_CARD_DAT_7-
TO4_0 (1)
DATA4 (1)
SPIHB_-
SDHC_CARD_DAT_7-
TO4_1 (1)
DATA5 (1)
SPIHB_-
SDHC_CARD_DAT_7-
TO4_2 (1)
DATA6 (1)
SPIHB_-
SDHC_CARD_DAT_7-
TO4_3 (1)
DATA7 (1)
ETH1_REF
_CLK (0)
ETH1_TX_
CTL (0)
ETH1_TX_
CLK (0)
ETH1_TXD
_0 (0)
ETH1_TXD
_1 (0)
ETH1_TXD
_2 (0)
ETH1_TXD
_3 (0)
ETH1_RXD
_0 (0)
ETH1_RXD
_1 (0)
ETH1_RXD
_2 (0)
[19, 27, 28]
Table 13-1
Alternate pin functions in Active mode (continued)
Active Mapping
Pin
[25]
HCon#8
HCon#9
ACT #1
HCon#10
ACT #2
HCon#11
ACT #3
HCon#16
ACT #4
HCon#17
ACT #5
HCon#18
ACT #6
HCon#19
ACT #7
HCon#20
ACT #8
HCon#21
ACT #9
HCon#22
ACT #10
HCon#23
ACT #11
HCon#24
ACT #12
HCon#25
ACT #13
HCon#26
ACT #14
HCon#27
ACT #15
[26]
Name ACT #0
P27.2
ETH1_RXD
_3 (0)
P27.3
P27.4
P27.5
P27.6
P27.7
ETH1_RX_
CTL (0)
ETH1_RX_
CLK (0)
ETH1_MDI
O (0)
ETH1_MD
C (0)
ETH1_ETH
_TSU_-
TIMER_C-
MP_VAL
(0)
P28.0 PWM1_63
P28.1 PWM1_64
P28.2 PWM1_65
P28.3 PWM1_66
P28.4 PWM1_67
P28.5 PWM1_68
P28.6 PWM1_69
P28.7 PWM1_70
P29.0 PWM1_76
P29.1 PWM1_77
P29.2 PWM1_78
P29.3 PWM1_79
P29.4 PWM1_80
P29.5 PWM1_81
P29.6 PWM1_82
P29.7 PWM1_83
P30.0 PWM1_83
P30.1 PWM1_82
P30.2 PWM1_81
P30.3 PWM1_80
P31.0 PWM1_79
P31.1 PWM1_78
PWM1_65_N
PWM1_63_N
PWM1_64_N
PWM1_65_N
PWM1_66_N
PWM1_67_N
PWM1_68_N
PWM1_69_N
PWM1_75_N
PWM1_76_N
PWM1_77_N
PWM1_78_N
PWM1_79_N
PWM1_80_N
PWM1_81_N
PWM1_82_N
PWM1_83_N
PWM1_83_N
PWM1_82_N
PWM1_81_N
PWM1_80_N
PWM1_79_N
TC1_63_TR0
TC1_64_TR0
TC1_65_TR0
TC1_66_TR0
TC1_67_TR0
TC1_68_TR0
TC1_69_TR0
TC1_70_TR0
TC1_76_TR0
TC1_77_TR0
TC1_78_TR0
TC1_79_TR0
TC1_80_TR0
TC1_81_TR0
TC1_82_TR0
TC1_83_TR0
TC1_83_TR0
TC1_82_TR0
TC1_81_TR0
TC1_80_TR0
TC1_79_TR0
TC1_78_TR0
TC1_65_TR1
TC1_63_TR1
TC1_64_TR1
TC1_65_TR1
TC1_66_TR1
TC1_67_TR1
TC1_68_TR1
TC1_69_TR1
TC1_75_TR1
TC1_76_TR1
TC1_77_TR1
TC1_78_TR1
TC1_79_TR1
TC1_80_TR1
TC1_81_TR1
TC1_82_TR1
TC1_83_TR1
TC1_83_TR1
TC1_82_TR1
TC1_81_TR1
TC1_80_TR1
TC1_79_TR1
PWM1_H_12
SCB10_RX (0)
SCB10_TX (0)
SCB10_MISO (0)
PWM1_H_12_N
TC1_H_12_TR0
TC1_H_12_TR1
SCB10_SDA (0) SCB10_MOSI (0) LIN17_RX
LIN17_TX
SCB10_RTS (0) SCB10_SCL (0) SCB10_CLK (0)
SCB10_CTS (0)
SCB10_SEL0 (0) LIN17_EN
SCB10_SEL1 (0) LIN18_RX
SCB10_SEL2 (0) LIN18_TX
SCB10_SEL3 (0) LIN18_EN
LIN19_RX
LIN19_TX
LIN19_EN
SCB9_RTS (1)
SCB9_CTS (1)
SCB9_SCL (1)
SCB9_CLK (1)
TRIG_IN[34]
TRIG_IN[35]
TRIG_IN[36]
TRIG_IN[37]
SCB9_SEL0 (1)
SCB9_SEL1 (1)
SCB9_SEL2 (1)
LIN16_RX
LIN16_TX CAN1_3_TX
LIN16_EN CAN1_3_RX
LIN17_RX
LIN17_TX
[19, 27, 28]
Table 13-1
Alternate pin functions in Active mode (continued)
Active Mapping
Pin
[25]
HCon#8
HCon#9
HCon#10
HCon#11
HCon#16
ACT #4
HCon#17
ACT #5
HCon#18
ACT #6
HCon#19
ACT #7
HCon#20
HCon#21
ACT #9
HCon#22
ACT #10
HCon#23
ACT #11
HCon#24
ACT #12
HCon#25
ACT #13
HCon#26
ACT #14
HCon#27
ACT #15
[26]
Name ACT #0
ACT #1
ACT #2
ACT #3
ACT #8
P31.2 PWM1_77
PWM1_78_N
TC1_77_TR0
TC1_78_TR1
LIN17_EN
P32.0 PWM1_76
P32.1 PWM1_75
P32.2 PWM1_74
P32.3 PWM1_73
P32.4 PWM1_72
P32.5 PWM1_71
P32.6 PWM1_70
P32.7 PWM1_69
P33.0
PWM1_77_N
PWM1_76_N
PWM1_75_N
PWM1_74_N
PWM1_73_N
PWM1_72_N
PWM1_71_N
PWM1_70_N
TC1_76_TR0
TC1_75_TR0
TC1_74_TR0
TC1_73_TR0
TC1_72_TR0
TC1_71_TR0
TC1_70_TR0
TC1_69_TR0
TC1_77_TR1
TC1_76_TR1
TC1_75_TR1
TC1_74_TR1
TC1_73_TR1
TC1_72_TR1
TC1_71_TR1
TC1_70_TR1
SCB10_RX (1)
SCB10_TX (1)
SCB10_MISO (1)
TRIG_IN[40]
TRIG_IN[41]
TRIG_IN[42]
TRIG_IN[43]
TRIG_IN[44]
TRIG_IN[45]
TRIG_IN[46]
TRIG_IN[47]
SCB10_SDA (1) SCB10_MOSI (1)
SCB10_RTS (1) SCB10_SCL (1) SCB10_CLK (1)
LIN18_RX
SCB10_CTS (1)
SCB10_SEL0 (1) LIN18_TX
SCB10_SEL1 (1) LIN18_EN
SCB10_SEL2 (1) LIN19_RX
LIN10_RX
LIN10_TX
LIN10_EN
SCB10_SEL3 (1) LIN19_TX CAN1_4_TX
LIN19_EN CAN1_4_RX
ETH0_REF_CLK
(1)
P33.1
ETH0_TX_CTL (1)
ETH1_TX_
ER (0)
P33.2
P33.3
ETH0_TX_CLK (1)
ETH0_TXD_0 (1)
ETH1_TXD
_4 (0)
P33.4
P33.5
P33.6
P33.7
P34.0
P34.1
P34.2
P34.3
ETH0_TXD_1 (1)
ETH0_TXD_2 (1)
ETH0_TXD_3 (1)
ETH0_RXD_0 (1)
ETH0_RXD_1 (1)
ETH0_RXD_2 (1)
ETH0_RXD_3 (1)
ETH0_RX_CTL (1)
ETH1_TXD
_5 (0)
ETH1_TXD
_6 (0)
ETH1_TXD
_7 (0)
ETH1_RXD
_4 (0)
ETH1_RXD
_5 (0)
ETH1_RXD
_6 (0)
ETH1_RXD
_7 (0)
ETH1_RX_
ER (0)
P34.4
P34.5
P34.6
P34.7
ETH0_RX_CLK (1)
ETH0_MDIO (1)
ETH0_MDC (1)
ETH0_ETH_TSU_-
TIMER_CMP_VAL
(1)
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Pin mux descriptions
14
Pin mux descriptions
Table 14-1
Pin mux descriptions
Sl.
No.
Pin
Module
Description
TCPWM 16-bit PWM (no motor control), PWM_DT and PWM_PR line out, x-TCPWM block,
y-counter number
1
PWMx_y
TCPWM
TCPWM 16-bit PWM (no motor control), PWM_DT and PWM_PR complementary line out
(N), x-TCPWM block, y-counter number
2
3
4
5
6
PWMx_y_N
PWMx_M_y
TCPWM
TCPWM
TCPWM
TCPWM
TCPWM
TCPWM 16-bit PWM with motor control line out, x-TCPWM block, y-counter number
TCPWM 16-bit PWM with motor control complementary line out (N), x-TCPWM block,
y-counter number
PWMx_M_y_N
PWMx_H_y
TCPWM 32-bit PWM, PWM_DT and PWM_PR line out, x-TCPWM block, y-counter number
TCPWM 32-bit PWM, PWM_DT and PWM_PR complementary line out (N), x-TCPWM block,
y-counter number
PWMx_H_y_N
TCPWM 16-bit dedicated counter input triggers, x-TCPWM block, y-counter number,
z-trigger number
7
8
9
TCx_y_TRz
TCPWM
TCPWM
TCPWM
TCPWM 16-bit dedicated counter input triggers with motor control, x-TCPWM block,
y-counter number, z-trigger number
TCx_M_y_TRz
TCx_H_y_TRz
TCPWM 32-bit dedicated counter input triggers, x-TCPWM block, y-counter number,
z-trigger number
10 SCBx_RX
SCB
SCB
UART Receive, x-SCB block
11 SCBx_TX
UART Transmit, x-SCB block
12 SCBx_RTS
13 SCBx_CTS
14 SCBx_SDA
15 SCBx_SCL
16 SCBx_MISO
17 SCBx_MOSI
18 SCBx_CLK
19 SCBx_SELy
20 LINx_RX
SCB
UART Request to Send (Handshake), x-SCB block
UART Clear to Send (Handshake), x-SCB block
SCB
2
SCB
I C Data line, x-SCB block
2
SCB
I C Clock line, x-SCB block
SCB
SPI Master Input Slave Output, x-SCB block
SPI Master Output Slave Input, x-SCB block
SPI Serial Clock, x-SCB block
SCB
SCB
SCB
SPI Slave Select, x-SCB block, y-select line
LIN Receive line, x-LIN block
LIN
21 LINx_TX
LIN
LIN Transmit line, x-LIN block
22 LINx_EN
LIN
LIN Enable line, x-LIN block
23 CANx_y_TX
24 CANx_y_RX
25 SPIHB_CLK
26 SPIHB_RWDS
27 SPIHB_SELx
28 SPIHB_DATAx
29 ETHx_RX_ER
CANFD
CANFD
SMIF
SMIF
SMIF
SMIF
Ethernet
CAN Transmit line, x-CAN block, y-channel number
CAN Receive line, x-CAN block, y-channel number
SMIF interface clock
SMIF (SPI/HYPERBUS™) read-write-data-strobe line
SMIF (SPI/HYPERBUS™) memory select line, x-select line number
SMIF (SPI/HYPERBUS™) memory data read and write line, x-0 to 7 data lines
Ethernet receive error indication line, x-ETH module number
ETHx_ETH_TSU_TIMER_C-
MP_VAL
30
Ethernet
Ethernet time stamp unit timer compare indication line, x-ETH module number
31 ETHx_MDIO
32 ETHx_MDC
Ethernet
Ethernet
Ethernet
Ethernet
Ethernet
Ethernet
Ethernet
Ethernet
Ethernet
Ethernet management data input/output (MDIO) interface to PHY, x-ETH module number
Ethernet management data clock (MDC) line, x-ETH module number
Ethernet reference clock line, x-ETH module number
33 ETHx_REF_CLK
34 ETHx_TX_CTL
35 ETHx_TX_ER
36 ETHx_TX_CLK
37 ETHx_TXD_y
38 ETHx_RXD_y
39 ETHx_RX_CTL
Ethernet transmit control line, x-ETH module number
Ethernet transmit error indication line, x-ETH module number
Ethernet transmit clock line, x-ETH module number
Ethernet transmit data line, x-ETH module number, y-transmit channel number
Ethernet receive data line, x-ETH module number, y-receive channel number
Ethernet receive control line, x-ETH module number
Datasheet
53
002-21617 Rev. *K
2022-10-10
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Pin mux descriptions
Table 14-1
Pin mux descriptions (continued)
Sl.
Pin
Module
Ethernet
SDHC
Description
Ethernet receive clock line, x-ETH module number
SDHC mechanical write protect
No.
40 ETHx_RX_CLK
SDHC_CARD_-
41
MECH_WRITE_PROT
42 SDHC_CARD_CMD
43 SDHC_CLK_CARD
44 SDHC_CARD_DETECT_N
45 SDHC_CARD_IF_PWR_EN
46 SDHC_CARD_DAT_3TO0_x
47 SDHC_CARD_DAT_7TO4_x
48 AUDIOSSx_MCLK
49 AUDIOSSx_TX_SCK
50 AUDIOSSx_TX_WS
51 AUDIOSSx_TX_SDO
52 AUDIOSSx_CLK_I2S_IF
53 AUDIOSSx_RX_SCK
54 AUDIOSSx_RX_WS
55 AUDIOSSx_RX_SDI
56 FLEXRAY_RXDx
SDHC
SDHC
SDHC command line
SDHC clock line
SDHC
SDHC interface insertion or removal detection line
SDHC interface power cycle line
SDHC
SDHC
SDHC lower 4-bits of the data
SDHC
SDHC upper 4-bits of the data in 8-bit mode
AudioSS master clock out, x-AudioSS block
I2S serial clock for transmitter, x-AudioSS block
I2S word select for transmitter, x-AudioSS block
I2S serial data output for transmitter, x-AudioSS block
I2S clock supplied from external I2S bus host, x-AudioSS block
I2S serial clock for receiver, x-AudioSS block
I2S word select for receiver, x-AudioSS block
I2S serial data input for receiver, x-AudioSS block
FlexRay data receive line, x-module channel reference A or B
FlexRay data transmit line, x-module channel reference A or B
FlexRay transmit enable line, x-module channel reference A or B
ETAS Calibration support line
AUDIOSS
AUDIOSS
AUDIOSS
AUDIOSS
AUDIOSS
AUDIOSS
AUDIOSS
AUDIOSS
FlexRay
FlexRay
FlexRay
System
SRSS
57 FLEXRAY_TXDx
58 FLEXRAY_TXENx_N
59 CAL_SUP_NZ
60 FAULT_OUT_x
Fault output line x-0 to 3
61 TRACE_DATA_x
SRSS
Trace dataout line x-0 to 3
62 TRACE_CLOCK
SRSS
Trace clock line
63 RTC_CAL
SRSS RTC
SRSS
RTC calibration clock input
64 SWJ_TRSTN
JTAG Test reset line (Active low)
65 SWJ_SWO_TDO
SRSS
JTAG Test data output/SWO (Serial Wire Output)
JTAG Test clock/SWD clock (Serial Wire Clock)
JTAG Test mode select/SWD data (Serial Wire Data Input/Output)
JTAG Test data input
66 SWJ_SWCLK_TCLK
67 SWJ_SWDIO_TMS
68 SWJ_SWDOE_TDI
69 HIBERNATE_WAKEUP[x]
70 EXT_CLK
SRSS
SRSS
SRSS
SRSS
Hibernate wakeup line x-0 to 3
SRSS
External clock input
REGHC control line, Transistor mode/Positive terminal of the current sense resistor, PMIC
mode/Power good input from PMIC
71 EXT_PS_CTL0
72 EXT_PS_CTL1
73 EXT_PS_CTL2
SRSS REGHC
SRSS REGHC
SRSS REGHC
REGHC control line, Transistor mode/Negative terminal of the current sense resistor,
PMIC mode/Enable output for PMIC
REGHC control line, Transistor mode/unused, PMIC mode/Reset threshold adjustment
for some PMICs
74 ADC[x]_y
PASS SAR
PASS SAR
PASS SAR
PASS SAR
SAR, channel, x-SAR number, y-channel number
SAR motor control input, x-SAR number
75 ADC[x]_M
76 EXT_MUX[x]_y
77 EXT_MUX[x]_EN
External SAR MUX inputs, x-MUX number, y-MUX input 0 to 2
External SAR MUX enable line
Datasheet
54
002-21617 Rev. *K
2022-10-10
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Interrupts and wake-up assignments
15
Interrupts and wake-up assignments
Table 15-1
Peripheral interrupt assignments and wake-up sources
Interrupt
0
Source
Power Mode
DeepSleep
DeepSleep
DeepSleep
DeepSleep
DeepSleep
DeepSleep
DeepSleep
DeepSleep
DeepSleep
DeepSleep
DeepSleep
DeepSleep
DeepSleep
DeepSleep
DeepSleep
DeepSleep
DeepSleep
DeepSleep
DeepSleep
DeepSleep
DeepSleep
DeepSleep
DeepSleep
DeepSleep
DeepSleep
DeepSleep
DeepSleep
DeepSleep
DeepSleep
DeepSleep
DeepSleep
DeepSleep
DeepSleep
DeepSleep
DeepSleep
DeepSleep
DeepSleep
DeepSleep
DeepSleep
DeepSleep
DeepSleep
DeepSleep
DeepSleep
Description
CPUSS Inter Process Communication Interrupt #0
CPUSS Inter Process Communication Interrupt #1
CPUSS Inter Process Communication Interrupt #2
CPUSS Inter Process Communication Interrupt #3
CPUSS Inter Process Communication Interrupt #4
CPUSS Inter Process Communication Interrupt #5
CPUSS Inter Process Communication Interrupt #6
CPUSS Inter Process Communication Interrupt #7
CPUSS Fault Structure #0 Interrupt
CPUSS Fault Structure #1 Interrupt
CPUSS Fault Structure #2 Interrupt
CPUSS Fault Structure #3 Interrupt
BACKUP domain Interrupt
cpuss_interrupts_ipc_0_IRQn
1
cpuss_interrupts_ipc_1_IRQn
2
cpuss_interrupts_ipc_2_IRQn
3
cpuss_interrupts_ipc_3_IRQn
4
cpuss_interrupts_ipc_4_IRQn
5
cpuss_interrupts_ipc_5_IRQn
6
cpuss_interrupts_ipc_6_IRQn
7
cpuss_interrupts_ipc_7_IRQn
8
cpuss_interrupts_fault_0_IRQn
cpuss_interrupts_fault_1_IRQn
cpuss_interrupts_fault_2_IRQn
cpuss_interrupts_fault_3_IRQn
srss_interrupt_backup_IRQn
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
srss_interrupt_mcwdt_0_IRQn
srss_interrupt_mcwdt_1_IRQn
srss_interrupt_mcwdt_2_IRQn
srss_interrupt_wdt_IRQn
Multi Counter Watchdog Timer #0 interrupt
Multi Counter Watchdog Timer #1 interrupt
Multi Counter Watchdog Timer #2 interrupt
Hardware Watchdog Timer interrupt
Other combined Interrupts for SRSS (LVD, CLKCAL)
SCB0 interrupt (DeepSleep capable)
Event gen DeepSleep domain interrupt
I/O Supply (VDDIO, VDDA, VDDD) state change Interrupt
Consolidated Interrupt for GPIO_STD and GPIO_ENH, all ports
GPIO_ENH Port #0 Interrupt
srss_interrupt_IRQn
scb_0_interrupt_IRQn
evtgen_0_interrupt_dpslp_IRQn
ioss_interrupt_vdd_IRQn
ioss_interrupt_gpio_dpslp_IRQn
ioss_interrupts_gpio_dpslp_0_IRQn
ioss_interrupts_gpio_dpslp_1_IRQn
ioss_interrupts_gpio_dpslp_2_IRQn
ioss_interrupts_gpio_dpslp_3_IRQn
ioss_interrupts_gpio_dpslp_4_IRQn
ioss_interrupts_gpio_dpslp_5_IRQn
ioss_interrupts_gpio_dpslp_6_IRQn
ioss_interrupts_gpio_dpslp_7_IRQn
ioss_interrupts_gpio_dpslp_8_IRQn
ioss_interrupts_gpio_dpslp_9_IRQn
ioss_interrupts_gpio_dpslp_10_IRQn
ioss_interrupts_gpio_dpslp_11_IRQn
ioss_interrupts_gpio_dpslp_12_IRQn
ioss_interrupts_gpio_dpslp_13_IRQn
ioss_interrupts_gpio_dpslp_14_IRQn
ioss_interrupts_gpio_dpslp_15_IRQn
ioss_interrupts_gpio_dpslp_16_IRQn
ioss_interrupts_gpio_dpslp_17_IRQn
ioss_interrupts_gpio_dpslp_18_IRQn
ioss_interrupts_gpio_dpslp_19_IRQn
ioss_interrupts_gpio_dpslp_20_IRQn
GPIO_STD Port #1 Interrupt
GPIO_STD Port #2 Interrupt
GPIO_STD Port #3 Interrupt
GPIO_STD Port #4 Interrupt
GPIO_STD Port #5 Interrupt
GPIO_STD Port #6 Interrupt
GPIO_STD Port #7 Interrupt
GPIO_STD Port #8 Interrupt
GPIO_STD Port #9 Interrupt
GPIO_STD Port #10 Interrupt
GPIO_STD Port #11 Interrupt
GPIO_STD Port #12 Interrupt
GPIO_STD Port #13 Interrupt
GPIO_STD Port #14 Interrupt
GPIO_STD Port #15 Interrupt
GPIO_STD Port #16 Interrupt
GPIO_STD Port #17 Interrupt
GPIO_STD Port #18 Interrupt
GPIO_STD Port #19 Interrupt
GPIO_STD Port #20 Interrupt
Datasheet
55
002-21617 Rev. *K
2022-10-10
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Interrupts and wake-up assignments
Table 15-1
Peripheral interrupt assignments and wake-up sources (continued)
Interrupt
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
Source
Power Mode
DeepSleep
DeepSleep
DeepSleep
DeepSleep
DeepSleep
DeepSleep
DeepSleep
DeepSleep
Active
Description
GPIO_STD Port #21 Interrupt
ioss_interrupts_gpio_dpslp_21_IRQn
ioss_interrupts_gpio_dpslp_22_IRQn
ioss_interrupts_gpio_dpslp_23_IRQn
ioss_interrupts_gpio_dpslp_28_IRQn
ioss_interrupts_gpio_dpslp_29_IRQn
ioss_interrupts_gpio_dpslp_30_IRQn
ioss_interrupts_gpio_dpslp_31_IRQn
ioss_interrupts_gpio_dpslp_32_IRQn
ioss_interrupts_gpio_act_IRQn
ioss_interrupts_gpio_act_24_IRQn
ioss_interrupts_gpio_act_25_IRQn
ioss_interrupts_gpio_act_26_IRQn
ioss_interrupts_gpio_act_27_IRQn
ioss_interrupts_gpio_act_33_IRQn
ioss_interrupts_gpio_act_34_IRQn
cpuss_interrupt_crypto_IRQn
cpuss_interrupt_fm_IRQn
GPIO_STD Port #22 Interrupt
GPIO_STD Port #23 Interrupt
GPIO_STD Port #28 Interrupt
GPIO_STD Port #29 Interrupt
GPIO_STD Port #30 Interrupt
GPIO_STD Port #31 Interrupt
GPIO_STD Port #32 Interrupt
Consolidated Interrupt for HSIO_STD, All Ports
HSIO_STD Port #24 Interrupt
HSIO_STD Port #25 Interrupt
HSIO_STD Port #26 Interrupt
HSIO_STD Port #27 Interrupt
HSIO_STD Port #33 Interrupt
HSIO_STD Port #34 Interrupt
CRYPTO Accelerator Interrupt
Flash Macro Interrupt
Active
Active
Active
Active
Active
Active
Active
Active
cpuss_interrupts_cm7_0_fp_IRQn
cpuss_interrupts_cm7_1_fp_IRQn
cpuss_interrupts_cm0_cti_0_IRQn
cpuss_interrupts_cm0_cti_1_IRQn
cpuss_interrupts_cm7_0_cti_0_IRQn
cpuss_interrupts_cm7_0_cti_1_IRQn
cpuss_interrupts_cm7_1_cti_0_IRQn
cpuss_interrupts_cm7_1_cti_1_IRQn
evtgen_0_interrupt_IRQn
Active
CM7_0 Floating Point operation fault
CM7_1 Floating Point operation fault
CM0+ CTI (Cross Trigger Interface) #0
CM0+ CTI #1
Active
Active
Active
Active
CM7_0 CTI #0
Active
CM7_0 CTI #1
Active
CM7_1 CTI #0
Active
CM7_1 CTI #1
Active
Event gen Active domain Interrupt
CAN0, Consolidated Interrupt #0 for all five channels
CAN0, Consolidated Interrupt #1 for all five channels
CAN1, Consolidated Interrupt #0 for all five channels
CAN1, Consolidated Interrupt #1 for all five channels
CAN0, Interrupt #0, Channel #0
CAN0, Interrupt #0, Channel #1
CAN0, Interrupt #0, Channel #2
CAN0, Interrupt #0, Channel #3
CAN0, Interrupt #0, Channel #4
CAN0, Interrupt #1, Channel #0
CAN0, Interrupt #1, Channel #1
CAN0, Interrupt #1, Channel #2
CAN0, Interrupt #1, Channel #3
CAN0, Interrupt #1, Channel #4
CAN1, Interrupt #0, Channel #0
CAN1, Interrupt #0, Channel #1
CAN1, Interrupt #0, Channel #2
CAN1, Interrupt #0, Channel #3
CAN1, Interrupt #0, Channel #4
canfd_0_interrupt0_IRQn
Active
canfd_0_interrupt1_IRQn
Active
canfd_1_interrupt0_IRQn
Active
canfd_1_interrupt1_IRQn
Active
canfd_0_interrupts0_0_IRQn
Active
canfd_0_interrupts0_1_IRQn
Active
canfd_0_interrupts0_2_IRQn
Active
canfd_0_interrupts0_3_IRQn
Active
canfd_0_interrupts0_4_IRQn
Active
canfd_0_interrupts1_0_IRQn
Active
canfd_0_interrupts1_1_IRQn
Active
canfd_0_interrupts1_2_IRQn
Active
canfd_0_interrupts1_3_IRQn
Active
canfd_0_interrupts1_4_IRQn
Active
canfd_1_interrupts0_0_IRQn
Active
canfd_1_interrupts0_1_IRQn
Active
canfd_1_interrupts0_2_IRQn
Active
canfd_1_interrupts0_3_IRQn
Active
canfd_1_interrupts0_4_IRQn
Active
Datasheet
56
002-21617 Rev. *K
2022-10-10
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Interrupts and wake-up assignments
Table 15-1
Peripheral interrupt assignments and wake-up sources (continued)
Interrupt
88
Source
canfd_1_interrupts1_0_IRQn
canfd_1_interrupts1_1_IRQn
canfd_1_interrupts1_2_IRQn
canfd_1_interrupts1_3_IRQn
canfd_1_interrupts1_4_IRQn
lin_0_interrupts_0_IRQn
lin_0_interrupts_1_IRQn
lin_0_interrupts_2_IRQn
lin_0_interrupts_3_IRQn
lin_0_interrupts_4_IRQn
lin_0_interrupts_5_IRQn
lin_0_interrupts_6_IRQn
lin_0_interrupts_7_IRQn
lin_0_interrupts_8_IRQn
lin_0_interrupts_9_IRQn
lin_0_interrupts_10_IRQn
lin_0_interrupts_11_IRQn
lin_0_interrupts_12_IRQn
lin_0_interrupts_13_IRQn
lin_0_interrupts_14_IRQn
lin_0_interrupts_15_IRQn
lin_0_interrupts_16_IRQn
lin_0_interrupts_17_IRQn
lin_0_interrupts_18_IRQn
lin_0_interrupts_19_IRQn
scb_1_interrupt_IRQn
Power Mode
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Description
CAN1, Interrupt #1, Channel #0
89
CAN1, Interrupt #1, Channel #1
CAN1, Interrupt #1, Channel #2
CAN1, Interrupt #1, Channel #3
CAN1, Interrupt #1, Channel #4
LIN0, Channel #0 Interrupt
LIN0, Channel #1 Interrupt
LIN0, Channel #2 Interrupt
LIN0, Channel #3 Interrupt
LIN0, Channel #4 Interrupt
LIN0, Channel #5 Interrupt
LIN0, Channel #6 Interrupt
LIN0, Channel #7 Interrupt
LIN0, Channel #8 Interrupt
LIN0, Channel #9 Interrupt
LIN0, Channel #10 Interrupt
LIN0, Channel #11 Interrupt
LIN0, Channel #12 Interrupt
LIN0, Channel #13 Interrupt
LIN0, Channel #14 Interrupt
LIN0, Channel #15 Interrupt
LIN0, Channel #16 Interrupt
LIN0, Channel #17 Interrupt
LIN0, Channel #18 Interrupt
LIN0, Channel #19 Interrupt
SCB1 Interrupt
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
scb_2_interrupt_IRQn
SCB2 Interrupt
scb_3_interrupt_IRQn
SCB3 Interrupt
scb_4_interrupt_IRQn
SCB4 Interrupt
scb_5_interrupt_IRQn
SCB5 Interrupt
scb_6_interrupt_IRQn
SCB6 Interrupt
scb_7_interrupt_IRQn
SCB7 Interrupt
scb_8_interrupt_IRQn
SCB8 Interrupt
scb_9_interrupt_IRQn
SCB9 Interrupt
scb_10_interrupt_IRQn
SCB10 Interrupt
pass_0_interrupts_sar_0_IRQn
pass_0_interrupts_sar_1_IRQn
pass_0_interrupts_sar_2_IRQn
pass_0_interrupts_sar_3_IRQn
pass_0_interrupts_sar_4_IRQn
pass_0_interrupts_sar_5_IRQn
pass_0_interrupts_sar_6_IRQn
pass_0_interrupts_sar_7_IRQn
pass_0_interrupts_sar_8_IRQn
pass_0_interrupts_sar_9_IRQn
SAR0, Logical Channel #0 Interrupt
SAR0, Logical Channel #1 Interrupt
SAR0, Logical Channel #2 Interrupt
SAR0, Logical Channel #3 Interrupt
SAR0, Logical Channel #4 Interrupt
SAR0, Logical Channel #5 Interrupt
SAR0, Logical Channel #6 Interrupt
SAR0, Logical Channel #7 Interrupt
SAR0, Logical Channel #8 Interrupt
SAR0, Logical Channel #9 Interrupt
Datasheet
57
002-21617 Rev. *K
2022-10-10
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Interrupts and wake-up assignments
Table 15-1
Peripheral interrupt assignments and wake-up sources (continued)
Interrupt
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
Source
Power Mode
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Description
SAR0, Logical Channel #10 Interrupt
SAR0, Logical Channel #11 Interrupt
SAR0, Logical Channel #12 Interrupt
SAR0, Logical Channel #13 Interrupt
SAR0, Logical Channel #14 Interrupt
SAR0, Logical Channel #15 Interrupt
SAR0, Logical Channel #16 Interrupt
SAR0, Logical Channel #17 Interrupt
SAR0, Logical Channel #18 Interrupt
SAR0, Logical Channel #19 Interrupt
SAR0, Logical Channel #20 Interrupt
SAR0, Logical Channel #21 Interrupt
SAR0, Logical Channel #22 Interrupt
SAR0, Logical Channel #23 Interrupt
SAR0, Logical Channel #24 Interrupt
SAR0, Logical Channel #25 Interrupt
SAR0, Logical Channel #26 Interrupt
SAR0, Logical Channel #27 Interrupt
SAR0, Logical Channel #28 Interrupt
SAR0, Logical Channel #29 Interrupt
SAR0, Logical Channel #30 Interrupt
SAR0, Logical Channel #31 Interrupt
SAR1, Logical Channel #0 Interrupt
SAR1, Logical Channel #1 Interrupt
SAR1, Logical Channel #2 Interrupt
SAR1, Logical Channel #3 Interrupt
SAR1, Logical Channel #4 Interrupt
SAR1, Logical Channel #5 Interrupt
SAR1, Logical Channel #6 Interrupt
SAR1, Logical Channel #7 Interrupt
SAR1, Logical Channel #8 Interrupt
SAR1, Logical Channel #9 Interrupt
SAR1, Logical Channel #10 Interrupt
SAR1, Logical Channel #11 Interrupt
SAR1, Logical Channel #12 Interrupt
SAR1, Logical Channel #13 Interrupt
SAR1, Logical Channel #14 Interrupt
SAR1, Logical Channel #15 Interrupt
SAR1, Logical Channel #16 Interrupt
SAR1, Logical Channel #17 Interrupt
SAR1, Logical Channel #18 Interrupt
SAR1, Logical Channel #19 Interrupt
SAR1, Logical Channel #20 Interrupt
SAR1, Logical Channel #21 Interrupt
SAR1, Logical Channel #22 Interrupt
pass_0_interrupts_sar_10_IRQn
pass_0_interrupts_sar_11_IRQn
pass_0_interrupts_sar_12_IRQn
pass_0_interrupts_sar_13_IRQn
pass_0_interrupts_sar_14_IRQn
pass_0_interrupts_sar_15_IRQn
pass_0_interrupts_sar_16_IRQn
pass_0_interrupts_sar_17_IRQn
pass_0_interrupts_sar_18_IRQn
pass_0_interrupts_sar_19_IRQn
pass_0_interrupts_sar_20_IRQn
pass_0_interrupts_sar_21_IRQn
pass_0_interrupts_sar_22_IRQn
pass_0_interrupts_sar_23_IRQn
pass_0_interrupts_sar_24_IRQn
pass_0_interrupts_sar_25_IRQn
pass_0_interrupts_sar_26_IRQn
pass_0_interrupts_sar_27_IRQn
pass_0_interrupts_sar_28_IRQn
pass_0_interrupts_sar_29_IRQn
pass_0_interrupts_sar_30_IRQn
pass_0_interrupts_sar_31_IRQn
pass_0_interrupts_sar_32_IRQn
pass_0_interrupts_sar_33_IRQn
pass_0_interrupts_sar_34_IRQn
pass_0_interrupts_sar_35_IRQn
pass_0_interrupts_sar_36_IRQn
pass_0_interrupts_sar_37_IRQn
pass_0_interrupts_sar_38_IRQn
pass_0_interrupts_sar_39_IRQn
pass_0_interrupts_sar_40_IRQn
pass_0_interrupts_sar_41_IRQn
pass_0_interrupts_sar_42_IRQn
pass_0_interrupts_sar_43_IRQn
pass_0_interrupts_sar_44_IRQn
pass_0_interrupts_sar_45_IRQn
pass_0_interrupts_sar_46_IRQn
pass_0_interrupts_sar_47_IRQn
pass_0_interrupts_sar_48_IRQn
pass_0_interrupts_sar_49_IRQn
pass_0_interrupts_sar_50_IRQn
pass_0_interrupts_sar_51_IRQn
pass_0_interrupts_sar_52_IRQn
pass_0_interrupts_sar_53_IRQn
pass_0_interrupts_sar_54_IRQn
Datasheet
58
002-21617 Rev. *K
2022-10-10
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Interrupts and wake-up assignments
Table 15-1
Peripheral interrupt assignments and wake-up sources (continued)
Interrupt
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
Source
Power Mode
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Description
SAR1, Logical Channel #23 Interrupt
SAR1, Logical Channel #24 Interrupt
SAR1, Logical Channel #25 Interrupt
SAR1, Logical Channel #26 Interrupt
SAR1, Logical Channel #27 Interrupt
SAR1, Logical Channel #28 Interrupt
SAR1, Logical Channel #29 Interrupt
SAR1, Logical Channel #30 Interrupt
SAR1, Logical Channel #31 Interrupt
SAR2, Logical Channel #0 Interrupt
SAR2, Logical Channel #1 Interrupt
SAR2, Logical Channel #2 Interrupt
SAR2, Logical Channel #3 Interrupt
SAR2, Logical Channel #4 Interrupt
SAR2, Logical Channel #5 Interrupt
SAR2, Logical Channel #6 Interrupt
SAR2, Logical Channel #7 Interrupt
SAR2, Logical Channel #8 Interrupt
SAR2, Logical Channel #9 Interrupt
SAR2, Logical Channel #10 Interrupt
SAR2, Logical Channel #11 Interrupt
SAR2, Logical Channel #12 Interrupt
SAR2, Logical Channel #13 Interrupt
SAR2, Logical Channel #14 Interrupt
SAR2, Logical Channel #15 Interrupt
SAR2, Logical Channel #16 Interrupt
SAR2, Logical Channel #17 Interrupt
SAR2, Logical Channel #18 Interrupt
SAR2, Logical Channel #19 Interrupt
SAR2, Logical Channel #20 Interrupt
SAR2, Logical Channel #21 Interrupt
SAR2, Logical Channel #22 Interrupt
SAR2, Logical Channel #23 Interrupt
SAR2, Logical Channel #24 Interrupt
SAR2, Logical Channel #25 Interrupt
SAR2, Logical Channel #26 Interrupt
SAR2, Logical Channel #27 Interrupt
SAR2, Logical Channel #28 Interrupt
SAR2, Logical Channel #29 Interrupt
SAR2, Logical Channel #30 Interrupt
SAR2, Logical Channel #31 Interrupt
CPUSS M-DMA0, Channel #0 Interrupt
CPUSS M-DMA0, Channel #1 Interrupt
CPUSS M-DMA0, Channel #2 Interrupt
CPUSS M-DMA0, Channel #3 Interrupt
pass_0_interrupts_sar_55_IRQn
pass_0_interrupts_sar_56_IRQn
pass_0_interrupts_sar_57_IRQn
pass_0_interrupts_sar_58_IRQn
pass_0_interrupts_sar_59_IRQn
pass_0_interrupts_sar_60_IRQn
pass_0_interrupts_sar_61_IRQn
pass_0_interrupts_sar_62_IRQn
pass_0_interrupts_sar_63_IRQn
pass_0_interrupts_sar_64_IRQn
pass_0_interrupts_sar_65_IRQn
pass_0_interrupts_sar_66_IRQn
pass_0_interrupts_sar_67_IRQn
pass_0_interrupts_sar_68_IRQn
pass_0_interrupts_sar_69_IRQn
pass_0_interrupts_sar_70_IRQn
pass_0_interrupts_sar_71_IRQn
pass_0_interrupts_sar_72_IRQn
pass_0_interrupts_sar_73_IRQn
pass_0_interrupts_sar_74_IRQn
pass_0_interrupts_sar_75_IRQn
pass_0_interrupts_sar_76_IRQn
pass_0_interrupts_sar_77_IRQn
pass_0_interrupts_sar_78_IRQn
pass_0_interrupts_sar_79_IRQn
pass_0_interrupts_sar_80_IRQn
pass_0_interrupts_sar_81_IRQn
pass_0_interrupts_sar_82_IRQn
pass_0_interrupts_sar_83_IRQn
pass_0_interrupts_sar_84_IRQn
pass_0_interrupts_sar_85_IRQn
pass_0_interrupts_sar_86_IRQn
pass_0_interrupts_sar_87_IRQn
pass_0_interrupts_sar_88_IRQn
pass_0_interrupts_sar_89_IRQn
pass_0_interrupts_sar_90_IRQn
pass_0_interrupts_sar_91_IRQn
pass_0_interrupts_sar_92_IRQn
pass_0_interrupts_sar_93_IRQn
pass_0_interrupts_sar_94_IRQn
pass_0_interrupts_sar_95_IRQn
cpuss_interrupts_dmac_0_IRQn
cpuss_interrupts_dmac_1_IRQn
cpuss_interrupts_dmac_2_IRQn
cpuss_interrupts_dmac_3_IRQn
Datasheet
59
002-21617 Rev. *K
2022-10-10
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Interrupts and wake-up assignments
Table 15-1
Peripheral interrupt assignments and wake-up sources (continued)
Interrupt
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
Source
Power Mode
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Description
CPUSS M-DMA0, Channel #4 Interrupt
CPUSS M-DMA0, Channel #5 Interrupt
CPUSS M-DMA0, Channel #6 Interrupt
CPUSS M-DMA0, Channel #7 Interrupt
CPUSS P-DMA0, Channel #0 Interrupt
CPUSS P-DMA0, Channel #1 Interrupt
CPUSS P-DMA0, Channel #2 Interrupt
CPUSS P-DMA0, Channel #3 Interrupt
CPUSS P-DMA0, Channel #4 Interrupt
CPUSS P-DMA0, Channel #5 Interrupt
CPUSS P-DMA0, Channel #6 Interrupt
CPUSS P-DMA0, Channel #7 Interrupt
CPUSS P-DMA0, Channel #8 Interrupt
CPUSS P-DMA0, Channel #9 Interrupt
CPUSS P-DMA0, Channel #10 Interrupt
CPUSS P-DMA0, Channel #11 Interrupt
CPUSS P-DMA0, Channel #12 Interrupt
CPUSS P-DMA0, Channel #13 Interrupt
CPUSS P-DMA0, Channel #14 Interrupt
CPUSS P-DMA0, Channel #15 Interrupt
CPUSS P-DMA0, Channel #16 Interrupt
CPUSS P-DMA0, Channel #17 Interrupt
CPUSS P-DMA0, Channel #18 Interrupt
CPUSS P-DMA0, Channel #19 Interrupt
CPUSS P-DMA0, Channel #20 Interrupt
CPUSS P-DMA0, Channel #21 Interrupt
CPUSS P-DMA0, Channel #22 Interrupt
CPUSS P-DMA0, Channel #23 Interrupt
CPUSS P-DMA0, Channel #24 Interrupt
CPUSS P-DMA0, Channel #25 Interrupt
CPUSS P-DMA0, Channel #26 Interrupt
CPUSS P-DMA0, Channel #27 Interrupt
CPUSS P-DMA0, Channel #28 Interrupt
CPUSS P-DMA0, Channel #29 Interrupt
CPUSS P-DMA0, Channel #30 Interrupt
CPUSS P-DMA0, Channel #31 Interrupt
CPUSS P-DMA0, Channel #32 Interrupt
CPUSS P-DMA0, Channel #33 Interrupt
CPUSS P-DMA0, Channel #34 Interrupt
CPUSS P-DMA0, Channel #35 Interrupt
CPUSS P-DMA0, Channel #36 Interrupt
CPUSS P-DMA0, Channel #37 Interrupt
CPUSS P-DMA0, Channel #38 Interrupt
CPUSS P-DMA0, Channel #39 Interrupt
CPUSS P-DMA0, Channel #40 Interrupt
cpuss_interrupts_dmac_4_IRQn
cpuss_interrupts_dmac_5_IRQn
cpuss_interrupts_dmac_6_IRQn
cpuss_interrupts_dmac_7_IRQn
cpuss_interrupts_dw0_0_IRQn
cpuss_interrupts_dw0_1_IRQn
cpuss_interrupts_dw0_2_IRQn
cpuss_interrupts_dw0_3_IRQn
cpuss_interrupts_dw0_4_IRQn
cpuss_interrupts_dw0_5_IRQn
cpuss_interrupts_dw0_6_IRQn
cpuss_interrupts_dw0_7_IRQn
cpuss_interrupts_dw0_8_IRQn
cpuss_interrupts_dw0_9_IRQn
cpuss_interrupts_dw0_10_IRQn
cpuss_interrupts_dw0_11_IRQn
cpuss_interrupts_dw0_12_IRQn
cpuss_interrupts_dw0_13_IRQn
cpuss_interrupts_dw0_14_IRQn
cpuss_interrupts_dw0_15_IRQn
cpuss_interrupts_dw0_16_IRQn
cpuss_interrupts_dw0_17_IRQn
cpuss_interrupts_dw0_18_IRQn
cpuss_interrupts_dw0_19_IRQn
cpuss_interrupts_dw0_20_IRQn
cpuss_interrupts_dw0_21_IRQn
cpuss_interrupts_dw0_22_IRQn
cpuss_interrupts_dw0_23_IRQn
cpuss_interrupts_dw0_24_IRQn
cpuss_interrupts_dw0_25_IRQn
cpuss_interrupts_dw0_26_IRQn
cpuss_interrupts_dw0_27_IRQn
cpuss_interrupts_dw0_28_IRQn
cpuss_interrupts_dw0_29_IRQn
cpuss_interrupts_dw0_30_IRQn
cpuss_interrupts_dw0_31_IRQn
cpuss_interrupts_dw0_32_IRQn
cpuss_interrupts_dw0_33_IRQn
cpuss_interrupts_dw0_34_IRQn
cpuss_interrupts_dw0_35_IRQn
cpuss_interrupts_dw0_36_IRQn
cpuss_interrupts_dw0_37_IRQn
cpuss_interrupts_dw0_38_IRQn
cpuss_interrupts_dw0_39_IRQn
cpuss_interrupts_dw0_40_IRQn
Datasheet
60
002-21617 Rev. *K
2022-10-10
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Interrupts and wake-up assignments
Table 15-1
Peripheral interrupt assignments and wake-up sources (continued)
Interrupt
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
Source
Power Mode
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Description
CPUSS P-DMA0, Channel #41 Interrupt
CPUSS P-DMA0, Channel #42 Interrupt
CPUSS P-DMA0, Channel #43 Interrupt
CPUSS P-DMA0, Channel #44 Interrupt
CPUSS P-DMA0, Channel #45 Interrupt
CPUSS P-DMA0, Channel #46 Interrupt
CPUSS P-DMA0, Channel #47 Interrupt
CPUSS P-DMA0, Channel #48 Interrupt
CPUSS P-DMA0, Channel #49 Interrupt
CPUSS P-DMA0, Channel #50 Interrupt
CPUSS P-DMA0, Channel #51 Interrupt
CPUSS P-DMA0, Channel #52 Interrupt
CPUSS P-DMA0, Channel #53 Interrupt
CPUSS P-DMA0, Channel #54 Interrupt
CPUSS P-DMA0, Channel #55 Interrupt
CPUSS P-DMA0, Channel #56 Interrupt
CPUSS P-DMA0, Channel #57 Interrupt
CPUSS P-DMA0, Channel #58 Interrupt
CPUSS P-DMA0, Channel #59 Interrupt
CPUSS P-DMA0, Channel #60 Interrupt
CPUSS P-DMA0, Channel #61 Interrupt
CPUSS P-DMA0, Channel #62 Interrupt
CPUSS P-DMA0, Channel #63 Interrupt
CPUSS P-DMA0, Channel #64 Interrupt
CPUSS P-DMA0, Channel #65 Interrupt
CPUSS P-DMA0, Channel #66 Interrupt
CPUSS P-DMA0, Channel #67 Interrupt
CPUSS P-DMA0, Channel #68 Interrupt
CPUSS P-DMA0, Channel #69 Interrupt
CPUSS P-DMA0, Channel #70 Interrupt
CPUSS P-DMA0, Channel #71 Interrupt
CPUSS P-DMA0, Channel #72 Interrupt
CPUSS P-DMA0, Channel #73 Interrupt
CPUSS P-DMA0, Channel #74 Interrupt
CPUSS P-DMA0, Channel #75 Interrupt
CPUSS P-DMA0, Channel #76 Interrupt
CPUSS P-DMA0, Channel #77 Interrupt
CPUSS P-DMA0, Channel #78 Interrupt
CPUSS P-DMA0, Channel #79 Interrupt
CPUSS P-DMA0, Channel #80 Interrupt
CPUSS P-DMA0, Channel #81 Interrupt
CPUSS P-DMA0, Channel #82 Interrupt
CPUSS P-DMA0, Channel #83 Interrupt
CPUSS P-DMA0, Channel #84 Interrupt
CPUSS P-DMA0, Channel #85 Interrupt
cpuss_interrupts_dw0_41_IRQn
cpuss_interrupts_dw0_42_IRQn
cpuss_interrupts_dw0_43_IRQn
cpuss_interrupts_dw0_44_IRQn
cpuss_interrupts_dw0_45_IRQn
cpuss_interrupts_dw0_46_IRQn
cpuss_interrupts_dw0_47_IRQn
cpuss_interrupts_dw0_48_IRQn
cpuss_interrupts_dw0_49_IRQn
cpuss_interrupts_dw0_50_IRQn
cpuss_interrupts_dw0_51_IRQn
cpuss_interrupts_dw0_52_IRQn
cpuss_interrupts_dw0_53_IRQn
cpuss_interrupts_dw0_54_IRQn
cpuss_interrupts_dw0_55_IRQn
cpuss_interrupts_dw0_56_IRQn
cpuss_interrupts_dw0_57_IRQn
cpuss_interrupts_dw0_58_IRQn
cpuss_interrupts_dw0_59_IRQn
cpuss_interrupts_dw0_60_IRQn
cpuss_interrupts_dw0_61_IRQn
cpuss_interrupts_dw0_62_IRQn
cpuss_interrupts_dw0_63_IRQn
cpuss_interrupts_dw0_64_IRQn
cpuss_interrupts_dw0_65_IRQn
cpuss_interrupts_dw0_66_IRQn
cpuss_interrupts_dw0_67_IRQn
cpuss_interrupts_dw0_68_IRQn
cpuss_interrupts_dw0_69_IRQn
cpuss_interrupts_dw0_70_IRQn
cpuss_interrupts_dw0_71_IRQn
cpuss_interrupts_dw0_72_IRQn
cpuss_interrupts_dw0_73_IRQn
cpuss_interrupts_dw0_74_IRQn
cpuss_interrupts_dw0_75_IRQn
cpuss_interrupts_dw0_76_IRQn
cpuss_interrupts_dw0_77_IRQn
cpuss_interrupts_dw0_78_IRQn
cpuss_interrupts_dw0_79_IRQn
cpuss_interrupts_dw0_80_IRQn
cpuss_interrupts_dw0_81_IRQn
cpuss_interrupts_dw0_82_IRQn
cpuss_interrupts_dw0_83_IRQn
cpuss_interrupts_dw0_84_IRQn
cpuss_interrupts_dw0_85_IRQn
Datasheet
61
002-21617 Rev. *K
2022-10-10
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Interrupts and wake-up assignments
Table 15-1
Peripheral interrupt assignments and wake-up sources (continued)
Interrupt
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
Source
Power Mode
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Description
CPUSS P-DMA0, Channel #86 Interrupt
CPUSS P-DMA0, Channel #87 Interrupt
CPUSS P-DMA0, Channel #88 Interrupt
CPUSS P-DMA0, Channel #89 Interrupt
CPUSS P-DMA0, Channel #90 Interrupt
CPUSS P-DMA0, Channel #91 Interrupt
CPUSS P-DMA0, Channel #92 Interrupt
CPUSS P-DMA0, Channel #93 Interrupt
CPUSS P-DMA0, Channel #94 Interrupt
CPUSS P-DMA0, Channel #95 Interrupt
CPUSS P-DMA0, Channel #96 Interrupt
CPUSS P-DMA0, Channel #97 Interrupt
CPUSS P-DMA0, Channel #98 Interrupt
CPUSS P-DMA0, Channel #99 Interrupt
CPUSS P-DMA0, Channel #100 Interrupt
CPUSS P-DMA0, Channel #101 Interrupt
CPUSS P-DMA0, Channel #102 Interrupt
CPUSS P-DMA0, Channel #103 Interrupt
CPUSS P-DMA0, Channel #104 Interrupt
CPUSS P-DMA0, Channel #105 Interrupt
CPUSS P-DMA0, Channel #106 Interrupt
CPUSS P-DMA0, Channel #107 Interrupt
CPUSS P-DMA0, Channel #108 Interrupt
CPUSS P-DMA0, Channel #109 Interrupt
CPUSS P-DMA0, Channel #110 Interrupt
CPUSS P-DMA0, Channel #111 Interrupt
CPUSS P-DMA0, Channel #112 Interrupt
CPUSS P-DMA0, Channel #113 Interrupt
CPUSS P-DMA0, Channel #114 Interrupt
CPUSS P-DMA0, Channel #115 Interrupt
CPUSS P-DMA0, Channel #116 Interrupt
CPUSS P-DMA0, Channel #117 Interrupt
CPUSS P-DMA0, Channel #118 Interrupt
CPUSS P-DMA0, Channel #119 Interrupt
CPUSS P-DMA0, Channel #120 Interrupt
CPUSS P-DMA0, Channel #121 Interrupt
CPUSS P-DMA0, Channel #122 Interrupt
CPUSS P-DMA0, Channel #123 Interrupt
CPUSS P-DMA0, Channel #124 Interrupt
CPUSS P-DMA0, Channel #125 Interrupt
CPUSS P-DMA0, Channel #126 Interrupt
CPUSS P-DMA0, Channel #127 Interrupt
CPUSS P-DMA0, Channel #128 Interrupt
CPUSS P-DMA0, Channel #129 Interrupt
CPUSS P-DMA0, Channel #130 Interrupt
cpuss_interrupts_dw0_86_IRQn
cpuss_interrupts_dw0_87_IRQn
cpuss_interrupts_dw0_88_IRQn
cpuss_interrupts_dw0_89_IRQn
cpuss_interrupts_dw0_90_IRQn
cpuss_interrupts_dw0_91_IRQn
cpuss_interrupts_dw0_92_IRQn
cpuss_interrupts_dw0_93_IRQn
cpuss_interrupts_dw0_94_IRQn
cpuss_interrupts_dw0_95_IRQn
cpuss_interrupts_dw0_96_IRQn
cpuss_interrupts_dw0_97_IRQn
cpuss_interrupts_dw0_98_IRQn
cpuss_interrupts_dw0_99_IRQn
cpuss_interrupts_dw0_100_IRQn
cpuss_interrupts_dw0_101_IRQn
cpuss_interrupts_dw0_102_IRQn
cpuss_interrupts_dw0_103_IRQn
cpuss_interrupts_dw0_104_IRQn
cpuss_interrupts_dw0_105_IRQn
cpuss_interrupts_dw0_106_IRQn
cpuss_interrupts_dw0_107_IRQn
cpuss_interrupts_dw0_108_IRQn
cpuss_interrupts_dw0_109_IRQn
cpuss_interrupts_dw0_110_IRQn
cpuss_interrupts_dw0_111_IRQn
cpuss_interrupts_dw0_112_IRQn
cpuss_interrupts_dw0_113_IRQn
cpuss_interrupts_dw0_114_IRQn
cpuss_interrupts_dw0_115_IRQn
cpuss_interrupts_dw0_116_IRQn
cpuss_interrupts_dw0_117_IRQn
cpuss_interrupts_dw0_118_IRQn
cpuss_interrupts_dw0_119_IRQn
cpuss_interrupts_dw0_120_IRQn
cpuss_interrupts_dw0_121_IRQn
cpuss_interrupts_dw0_122_IRQn
cpuss_interrupts_dw0_123_IRQn
cpuss_interrupts_dw0_124_IRQn
cpuss_interrupts_dw0_125_IRQn
cpuss_interrupts_dw0_126_IRQn
cpuss_interrupts_dw0_127_IRQn
cpuss_interrupts_dw0_128_IRQn
cpuss_interrupts_dw0_129_IRQn
cpuss_interrupts_dw0_130_IRQn
Datasheet
62
002-21617 Rev. *K
2022-10-10
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Interrupts and wake-up assignments
Table 15-1
Peripheral interrupt assignments and wake-up sources (continued)
Interrupt
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
Source
Power Mode
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Description
CPUSS P-DMA0, Channel #131 Interrupt
CPUSS P-DMA0, Channel #132 Interrupt
CPUSS P-DMA0, Channel #133 Interrupt
CPUSS P-DMA0, Channel #134 Interrupt
CPUSS P-DMA0, Channel #135 Interrupt
CPUSS P-DMA0, Channel #136 Interrupt
CPUSS P-DMA0, Channel #137 Interrupt
CPUSS P-DMA0, Channel #138 Interrupt
CPUSS P-DMA0, Channel #139 Interrupt
CPUSS P-DMA0, Channel #140 Interrupt
CPUSS P-DMA0, Channel #141 Interrupt
CPUSS P-DMA0, Channel #142 Interrupt
CPUSS P-DMA1, Channel #0 Interrupt
CPUSS P-DMA1, Channel #1 Interrupt
CPUSS P-DMA1, Channel #2 Interrupt
CPUSS P-DMA1, Channel #3 Interrupt
CPUSS P-DMA1, Channel #4 Interrupt
CPUSS P-DMA1, Channel #5 Interrupt
CPUSS P-DMA1, Channel #6 Interrupt
CPUSS P-DMA1, Channel #7 Interrupt
CPUSS P-DMA1, Channel #8 Interrupt
CPUSS P-DMA1, Channel #9 Interrupt
CPUSS P-DMA1, Channel #10 Interrupt
CPUSS P-DMA1, Channel #11 Interrupt
CPUSS P-DMA1, Channel #12 Interrupt
CPUSS P-DMA1, Channel #13 Interrupt
CPUSS P-DMA1, Channel #14 Interrupt
CPUSS P-DMA1, Channel #15 Interrupt
CPUSS P-DMA1, Channel #16 Interrupt
CPUSS P-DMA1, Channel #17 Interrupt
CPUSS P-DMA1, Channel #18 Interrupt
CPUSS P-DMA1, Channel #19 Interrupt
CPUSS P-DMA1, Channel #20 Interrupt
CPUSS P-DMA1, Channel #21 Interrupt
CPUSS P-DMA1, Channel #22 Interrupt
CPUSS P-DMA1, Channel #23 Interrupt
CPUSS P-DMA1, Channel #24 Interrupt
CPUSS P-DMA1, Channel #25 Interrupt
CPUSS P-DMA1, Channel #26 Interrupt
CPUSS P-DMA1, Channel #27 Interrupt
CPUSS P-DMA1, Channel #28 Interrupt
CPUSS P-DMA1, Channel #29 Interrupt
CPUSS P-DMA1, Channel #30 Interrupt
CPUSS P-DMA1, Channel #31 Interrupt
CPUSS P-DMA1, Channel #32 Interrupt
cpuss_interrupts_dw0_131_IRQn
cpuss_interrupts_dw0_132_IRQn
cpuss_interrupts_dw0_133_IRQn
cpuss_interrupts_dw0_134_IRQn
cpuss_interrupts_dw0_135_IRQn
cpuss_interrupts_dw0_136_IRQn
cpuss_interrupts_dw0_137_IRQn
cpuss_interrupts_dw0_138_IRQn
cpuss_interrupts_dw0_139_IRQn
cpuss_interrupts_dw0_140_IRQn
cpuss_interrupts_dw0_141_IRQn
cpuss_interrupts_dw0_142_IRQn
cpuss_interrupts_dw1_0_IRQn
cpuss_interrupts_dw1_1_IRQn
cpuss_interrupts_dw1_2_IRQn
cpuss_interrupts_dw1_3_IRQn
cpuss_interrupts_dw1_4_IRQn
cpuss_interrupts_dw1_5_IRQn
cpuss_interrupts_dw1_6_IRQn
cpuss_interrupts_dw1_7_IRQn
cpuss_interrupts_dw1_8_IRQn
cpuss_interrupts_dw1_9_IRQn
cpuss_interrupts_dw1_10_IRQn
cpuss_interrupts_dw1_11_IRQn
cpuss_interrupts_dw1_12_IRQn
cpuss_interrupts_dw1_13_IRQn
cpuss_interrupts_dw1_14_IRQn
cpuss_interrupts_dw1_15_IRQn
cpuss_interrupts_dw1_16_IRQn
cpuss_interrupts_dw1_17_IRQn
cpuss_interrupts_dw1_18_IRQn
cpuss_interrupts_dw1_19_IRQn
cpuss_interrupts_dw1_20_IRQn
cpuss_interrupts_dw1_21_IRQn
cpuss_interrupts_dw1_22_IRQn
cpuss_interrupts_dw1_23_IRQn
cpuss_interrupts_dw1_24_IRQn
cpuss_interrupts_dw1_25_IRQn
cpuss_interrupts_dw1_26_IRQn
cpuss_interrupts_dw1_27_IRQn
cpuss_interrupts_dw1_28_IRQn
cpuss_interrupts_dw1_29_IRQn
cpuss_interrupts_dw1_30_IRQn
cpuss_interrupts_dw1_31_IRQn
cpuss_interrupts_dw1_32_IRQn
Datasheet
63
002-21617 Rev. *K
2022-10-10
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Interrupts and wake-up assignments
Table 15-1
Peripheral interrupt assignments and wake-up sources (continued)
Interrupt
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
Source
Power Mode
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Description
CPUSS P-DMA1, Channel #33 Interrupt
CPUSS P-DMA1, Channel #34 Interrupt
CPUSS P-DMA1, Channel #35 Interrupt
CPUSS P-DMA1, Channel #36 Interrupt
CPUSS P-DMA1, Channel #37 Interrupt
CPUSS P-DMA1, Channel #38 Interrupt
CPUSS P-DMA1, Channel #39 Interrupt
CPUSS P-DMA1, Channel #40 Interrupt
CPUSS P-DMA1, Channel #41 Interrupt
CPUSS P-DMA1, Channel #42 Interrupt
CPUSS P-DMA1, Channel #43 Interrupt
CPUSS P-DMA1, Channel #44 Interrupt
CPUSS P-DMA1, Channel #45 Interrupt
CPUSS P-DMA1, Channel #46 Interrupt
CPUSS P-DMA1, Channel #47 Interrupt
CPUSS P-DMA1, Channel #48 Interrupt
CPUSS P-DMA1, Channel #49 Interrupt
CPUSS P-DMA1, Channel #50 Interrupt
CPUSS P-DMA1, Channel #51 Interrupt
CPUSS P-DMA1, Channel #52 Interrupt
CPUSS P-DMA1, Channel #53 Interrupt
CPUSS P-DMA1, Channel #54 Interrupt
CPUSS P-DMA1, Channel #55 Interrupt
CPUSS P-DMA1, Channel #56 Interrupt
CPUSS P-DMA1, Channel #57 Interrupt
CPUSS P-DMA1, Channel #58 Interrupt
CPUSS P-DMA1, Channel #59 Interrupt
CPUSS P-DMA1, Channel #60 Interrupt
CPUSS P-DMA1, Channel #61 Interrupt
CPUSS P-DMA1, Channel #62 Interrupt
CPUSS P-DMA1, Channel #63 Interrupt
CPUSS P-DMA1, Channel #64 Interrupt
TCPWM1 Group #0, Counter #0 Interrupt
TCPWM1 Group #0, Counter #1 Interrupt
TCPWM1 Group #0, Counter #2 Interrupt
TCPWM1 Group #0, Counter #3 Interrupt
TCPWM1 Group #0, Counter #4 Interrupt
TCPWM1 Group #0, Counter #5 Interrupt
TCPWM1 Group #0, Counter #6 Interrupt
TCPWM1 Group #0, Counter #7 Interrupt
TCPWM1 Group #0, Counter #8 Interrupt
TCPWM1 Group #0, Counter #9 Interrupt
TCPWM1 Group #0, Counter #10 Interrupt
TCPWM1 Group #0, Counter #11 Interrupt
TCPWM1 Group #0, Counter #12 Interrupt
cpuss_interrupts_dw1_33_IRQn
cpuss_interrupts_dw1_34_IRQn
cpuss_interrupts_dw1_35_IRQn
cpuss_interrupts_dw1_36_IRQn
cpuss_interrupts_dw1_37_IRQn
cpuss_interrupts_dw1_38_IRQn
cpuss_interrupts_dw1_39_IRQn
cpuss_interrupts_dw1_40_IRQn
cpuss_interrupts_dw1_41_IRQn
cpuss_interrupts_dw1_42_IRQn
cpuss_interrupts_dw1_43_IRQn
cpuss_interrupts_dw1_44_IRQn
cpuss_interrupts_dw1_45_IRQn
cpuss_interrupts_dw1_46_IRQn
cpuss_interrupts_dw1_47_IRQn
cpuss_interrupts_dw1_48_IRQn
cpuss_interrupts_dw1_49_IRQn
cpuss_interrupts_dw1_50_IRQn
cpuss_interrupts_dw1_51_IRQn
cpuss_interrupts_dw1_52_IRQn
cpuss_interrupts_dw1_53_IRQn
cpuss_interrupts_dw1_54_IRQn
cpuss_interrupts_dw1_55_IRQn
cpuss_interrupts_dw1_56_IRQn
cpuss_interrupts_dw1_57_IRQn
cpuss_interrupts_dw1_58_IRQn
cpuss_interrupts_dw1_59_IRQn
cpuss_interrupts_dw1_60_IRQn
cpuss_interrupts_dw1_61_IRQn
cpuss_interrupts_dw1_62_IRQn
cpuss_interrupts_dw1_63_IRQn
cpuss_interrupts_dw1_64_IRQn
tcpwm_1_interrupts_0_IRQn
tcpwm_1_interrupts_1_IRQn
tcpwm_1_interrupts_2_IRQn
tcpwm_1_interrupts_3_IRQn
tcpwm_1_interrupts_4_IRQn
tcpwm_1_interrupts_5_IRQn
tcpwm_1_interrupts_6_IRQn
tcpwm_1_interrupts_7_IRQn
tcpwm_1_interrupts_8_IRQn
tcpwm_1_interrupts_9_IRQn
tcpwm_1_interrupts_10_IRQn
tcpwm_1_interrupts_11_IRQn
tcpwm_1_interrupts_12_IRQn
Datasheet
64
002-21617 Rev. *K
2022-10-10
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Interrupts and wake-up assignments
Table 15-1
Peripheral interrupt assignments and wake-up sources (continued)
Interrupt
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
Source
Power Mode
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Description
tcpwm_1_interrupts_13_IRQn
tcpwm_1_interrupts_14_IRQn
tcpwm_1_interrupts_15_IRQn
tcpwm_1_interrupts_16_IRQn
tcpwm_1_interrupts_17_IRQn
tcpwm_1_interrupts_18_IRQn
tcpwm_1_interrupts_19_IRQn
tcpwm_1_interrupts_20_IRQn
tcpwm_1_interrupts_21_IRQn
tcpwm_1_interrupts_22_IRQn
tcpwm_1_interrupts_23_IRQn
tcpwm_1_interrupts_24_IRQn
tcpwm_1_interrupts_25_IRQn
tcpwm_1_interrupts_26_IRQn
tcpwm_1_interrupts_27_IRQn
tcpwm_1_interrupts_28_IRQn
tcpwm_1_interrupts_29_IRQn
tcpwm_1_interrupts_30_IRQn
tcpwm_1_interrupts_31_IRQn
tcpwm_1_interrupts_32_IRQn
tcpwm_1_interrupts_33_IRQn
tcpwm_1_interrupts_34_IRQn
tcpwm_1_interrupts_35_IRQn
tcpwm_1_interrupts_36_IRQn
tcpwm_1_interrupts_37_IRQn
tcpwm_1_interrupts_38_IRQn
tcpwm_1_interrupts_39_IRQn
tcpwm_1_interrupts_40_IRQn
tcpwm_1_interrupts_41_IRQn
tcpwm_1_interrupts_42_IRQn
tcpwm_1_interrupts_43_IRQn
tcpwm_1_interrupts_44_IRQn
tcpwm_1_interrupts_45_IRQn
tcpwm_1_interrupts_46_IRQn
tcpwm_1_interrupts_47_IRQn
tcpwm_1_interrupts_48_IRQn
tcpwm_1_interrupts_49_IRQn
tcpwm_1_interrupts_50_IRQn
tcpwm_1_interrupts_51_IRQn
tcpwm_1_interrupts_52_IRQn
tcpwm_1_interrupts_53_IRQn
tcpwm_1_interrupts_54_IRQn
tcpwm_1_interrupts_55_IRQn
tcpwm_1_interrupts_56_IRQn
tcpwm_1_interrupts_57_IRQn
TCPWM1 Group #0, Counter #13 Interrupt
TCPWM1 Group #0, Counter #14 Interrupt
TCPWM1 Group #0, Counter #15 Interrupt
TCPWM1 Group #0, Counter #16 Interrupt
TCPWM1 Group #0, Counter #17 Interrupt
TCPWM1 Group #0, Counter #18 Interrupt
TCPWM1 Group #0, Counter #19 Interrupt
TCPWM1 Group #0, Counter #20 Interrupt
TCPWM1 Group #0, Counter #21 Interrupt
TCPWM1 Group #0, Counter #22 Interrupt
TCPWM1 Group #0, Counter #23 Interrupt
TCPWM1 Group #0, Counter #24 Interrupt
TCPWM1 Group #0, Counter #25 Interrupt
TCPWM1 Group #0, Counter #26 Interrupt
TCPWM1 Group #0, Counter #27 Interrupt
TCPWM1 Group #0, Counter #28 Interrupt
TCPWM1 Group #0, Counter #29 Interrupt
TCPWM1 Group #0, Counter #30 Interrupt
TCPWM1 Group #0, Counter #31 Interrupt
TCPWM1 Group #0, Counter #32 Interrupt
TCPWM1 Group #0, Counter #33 Interrupt
TCPWM1 Group #0, Counter #34 Interrupt
TCPWM1 Group #0, Counter #35 Interrupt
TCPWM1 Group #0, Counter #36 Interrupt
TCPWM1 Group #0, Counter #37 Interrupt
TCPWM1 Group #0, Counter #38 Interrupt
TCPWM1 Group #0, Counter #39 Interrupt
TCPWM1 Group #0, Counter #40 Interrupt
TCPWM1 Group #0, Counter #41 Interrupt
TCPWM1 Group #0, Counter #42 Interrupt
TCPWM1 Group #0, Counter #43 Interrupt
TCPWM1 Group #0, Counter #44 Interrupt
TCPWM1 Group #0, Counter #45 Interrupt
TCPWM1 Group #0, Counter #46 Interrupt
TCPWM1 Group #0, Counter #47 Interrupt
TCPWM1 Group #0, Counter #48 Interrupt
TCPWM1 Group #0, Counter #49 Interrupt
TCPWM1 Group #0, Counter #50 Interrupt
TCPWM1 Group #0, Counter #51 Interrupt
TCPWM1 Group #0, Counter #52 Interrupt
TCPWM1 Group #0, Counter #53 Interrupt
TCPWM1 Group #0, Counter #54 Interrupt
TCPWM1 Group #0, Counter #55 Interrupt
TCPWM1 Group #0, Counter #56 Interrupt
TCPWM1 Group #0, Counter #57 Interrupt
Datasheet
65
002-21617 Rev. *K
2022-10-10
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Interrupts and wake-up assignments
Table 15-1
Peripheral interrupt assignments and wake-up sources (continued)
Interrupt
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
Source
Power Mode
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Description
tcpwm_1_interrupts_58_IRQn
tcpwm_1_interrupts_59_IRQn
tcpwm_1_interrupts_60_IRQn
tcpwm_1_interrupts_61_IRQn
tcpwm_1_interrupts_62_IRQn
tcpwm_1_interrupts_63_IRQn
tcpwm_1_interrupts_64_IRQn
tcpwm_1_interrupts_65_IRQn
tcpwm_1_interrupts_66_IRQn
tcpwm_1_interrupts_67_IRQn
tcpwm_1_interrupts_68_IRQn
tcpwm_1_interrupts_69_IRQn
tcpwm_1_interrupts_70_IRQn
tcpwm_1_interrupts_71_IRQn
tcpwm_1_interrupts_72_IRQn
tcpwm_1_interrupts_73_IRQn
tcpwm_1_interrupts_74_IRQn
tcpwm_1_interrupts_75_IRQn
tcpwm_1_interrupts_76_IRQn
tcpwm_1_interrupts_77_IRQn
tcpwm_1_interrupts_78_IRQn
tcpwm_1_interrupts_79_IRQn
tcpwm_1_interrupts_80_IRQn
tcpwm_1_interrupts_81_IRQn
tcpwm_1_interrupts_82_IRQn
tcpwm_1_interrupts_83_IRQn
tcpwm_0_interrupts_0_IRQn
tcpwm_0_interrupts_1_IRQn
tcpwm_0_interrupts_2_IRQn
tcpwm_1_interrupts_256_IRQn
tcpwm_1_interrupts_257_IRQn
tcpwm_1_interrupts_258_IRQn
tcpwm_1_interrupts_259_IRQn
tcpwm_1_interrupts_260_IRQn
tcpwm_1_interrupts_261_IRQn
tcpwm_1_interrupts_262_IRQn
tcpwm_1_interrupts_263_IRQn
tcpwm_1_interrupts_264_IRQn
tcpwm_1_interrupts_265_IRQn
tcpwm_1_interrupts_266_IRQn
tcpwm_1_interrupts_267_IRQn
tcpwm_0_interrupts_256_IRQn
tcpwm_0_interrupts_257_IRQn
tcpwm_0_interrupts_258_IRQn
tcpwm_1_interrupts_512_IRQn
TCPWM1 Group #0, Counter #58 Interrupt
TCPWM1 Group #0, Counter #59 Interrupt
TCPWM1 Group #0, Counter #60 Interrupt
TCPWM1 Group #0, Counter #61 Interrupt
TCPWM1 Group #0, Counter #62 Interrupt
TCPWM1 Group #0, Counter #63 Interrupt
TCPWM1 Group #0, Counter #64 Interrupt
TCPWM1 Group #0, Counter #65 Interrupt
TCPWM1 Group #0, Counter #66 Interrupt
TCPWM1 Group #0, Counter #67 Interrupt
TCPWM1 Group #0, Counter #68 Interrupt
TCPWM1 Group #0, Counter #69 Interrupt
TCPWM1 Group #0, Counter #70 Interrupt
TCPWM1 Group #0, Counter #71 Interrupt
TCPWM1 Group #0, Counter #72 Interrupt
TCPWM1 Group #0, Counter #73 Interrupt
TCPWM1 Group #0, Counter #74 Interrupt
TCPWM1 Group #0, Counter #75 Interrupt
TCPWM1 Group #0, Counter #76 Interrupt
TCPWM1 Group #0, Counter #77 Interrupt
TCPWM1 Group #0, Counter #78 Interrupt
TCPWM1 Group #0, Counter #79 Interrupt
TCPWM1 Group #0, Counter #80 Interrupt
TCPWM1 Group #0, Counter #81 Interrupt
TCPWM1 Group #0, Counter #82 Interrupt
TCPWM1 Group #0, Counter #83 Interrupt
TCPWM0 Group #0, Counter #0 Interrupt
TCPWM0 Group #0, Counter #1 Interrupt
TCPWM0 Group #0, Counter #2 Interrupt
TCPWM1 Group #1, Counter #0 Interrupt
TCPWM1 Group #1, Counter #1 Interrupt
TCPWM1 Group #1, Counter #2 Interrupt
TCPWM1 Group #1, Counter #3 Interrupt
TCPWM1 Group #1, Counter #4 Interrupt
TCPWM1 Group #1, Counter #5 Interrupt
TCPWM1 Group #1, Counter #6 Interrupt
TCPWM1 Group #1, Counter #7 Interrupt
TCPWM1 Group #1, Counter #8 Interrupt
TCPWM1 Group #1, Counter #9 Interrupt
TCPWM1 Group #1, Counter #10 Interrupt
TCPWM1 Group #1, Counter #11 Interrupt
TCPWM0 Group #1, Counter #0 Interrupt
TCPWM0 Group #1, Counter #1 Interrupt
TCPWM0 Group #1, Counter #2 Interrupt
TCPWM1 Group #2, Counter #0 Interrupt
Datasheet
66
002-21617 Rev. *K
2022-10-10
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Interrupts and wake-up assignments
Table 15-1
Peripheral interrupt assignments and wake-up sources (continued)
Interrupt
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
Source
Power Mode
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Description
TCPWM1 Group #2, Counter #1 Interrupt
TCPWM1 Group #2, Counter #2 Interrupt
TCPWM1 Group #2, Counter #3 Interrupt
TCPWM1 Group #2, Counter #4 Interrupt
TCPWM1 Group #2, Counter #5 Interrupt
TCPWM1 Group #2, Counter #6 Interrupt
TCPWM1 Group #2, Counter #7 Interrupt
TCPWM1 Group #2, Counter #8 Interrupt
TCPWM1 Group #2, Counter #9 Interrupt
TCPWM1 Group #2, Counter #10 Interrupt
TCPWM1 Group #2, Counter #11 Interrupt
TCPWM1 Group #2, Counter #12 Interrupt
TCPWM0 Group #2, Counter #0 Interrupt
TCPWM0 Group #2, Counter #1 Interrupt
TCPWM0 Group #2, Counter #2 Interrupt
FlexRay0 interrupt #0
tcpwm_1_interrupts_513_IRQn
tcpwm_1_interrupts_514_IRQn
tcpwm_1_interrupts_515_IRQn
tcpwm_1_interrupts_516_IRQn
tcpwm_1_interrupts_517_IRQn
tcpwm_1_interrupts_518_IRQn
tcpwm_1_interrupts_519_IRQn
tcpwm_1_interrupts_520_IRQn
tcpwm_1_interrupts_521_IRQn
tcpwm_1_interrupts_522_IRQn
tcpwm_1_interrupts_523_IRQn
tcpwm_1_interrupts_524_IRQn
tcpwm_0_interrupts_512_IRQn
tcpwm_0_interrupts_513_IRQn
tcpwm_0_interrupts_514_IRQn
flexray_0_interrupt0_IRQn
flexray_0_interrupt1_IRQn
FlexRay0 interrupt #1
smif_0_interrupt_IRQn
SMIF0 (QSPI) interrupt
eth_0_interrupt_eth_IRQn
Ethernet0 interrupt
eth_0_interrupt_eth_q2_IRQn
eth_0_interrupt_eth_q1_IRQn
eth_1_interrupt_eth_IRQn
Ethernet0 interrupt for dma_priority_queue2
Ethernet0 interrupt for dma_priority_queue1
Ethernet1 interrupt
eth_1_interrupt_eth_q2_IRQn
eth_1_interrupt_eth_q1_IRQn
sdhc_0_interrupt_general_IRQn
sdhc_0_interrupt_wakeup_IRQn
audioss_0_interrupt_i2s_IRQn
audioss_1_interrupt_i2s_IRQn
audioss_2_interrupt_i2s_IRQn
Ethernet1 interrupt for dma_priority_queue2
Ethernet1 interrupt for dma_priority_queue1
SDHC0 general interrupt
SDHC0 wakeup interrupt
AUDIOSS I2S0 interrupt
AUDIOSS I2S1 interrupt
AUDIOSS I2S2 interrupt
Datasheet
67
002-21617 Rev. *K
2022-10-10
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Core interrupt types
16
Core interrupt types
Table 16-1
Core interrupt types
Source
Interrupt
Power Mode
DeepSleep
DeepSleep
DeepSleep
DeepSleep
DeepSleep
DeepSleep
DeepSleep
DeepSleep
Active
Active
Active
Active
Active
Active
Active
Active
Description
CPU User Interrupt #0
CPU User Interrupt #1
CPU User Interrupt #2
CPU User Interrupt #3
CPU User Interrupt #4
CPU User Interrupt #5
CPU User Interrupt #6
CPU User Interrupt #7
Internal Software Interrupt #0
Internal Software Interrupt #1
Internal Software Interrupt #2
Internal Software Interrupt #3
Internal Software Interrupt #4
Internal Software Interrupt #5
Internal Software Interrupt #6
Internal Software Interrupt #7
0
1
2
3
4
5
6
7
8
CPUIntIdx0_IRQn[29]
CPUIntIdx1_IRQn[29]
CPUIntIdx2_IRQn
CPUIntIdx3_IRQn
CPUIntIdx4_IRQn
CPUIntIdx5_IRQn
CPUIntIdx6_IRQn
CPUIntIdx7_IRQn
Internal0_IRQn
Internal1_IRQn
Internal2_IRQn
Internal3_IRQn
Internal4_IRQn
Internal5_IRQn
Internal6_IRQn
Internal7_IRQn
9
10
11
12
13
14
15
Note
29.User interrupt cannot be used for CM0+ application, as it is used internally by system calls. Note, this does not impact CM7
application.
Datasheet
68
002-21617 Rev. *K
2022-10-10
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Trigger multiplexer
17
Trigger multiplexer
Green number in mux means Mux TriggerGroupNr.
[0:31]
[0:15]
[0:7]
[0:4]
[0:4]
1
[1:32]
[33:48]
[49:56]
[57:61]
[62:66]
[67]
P-DMA0: PDMA0_TR_OUT[0:142]
P-DMA1: PDMA1_TR_OUT[0:64]
M-DMA: MDMA_TR_OUT[0:7]
[0:16]
0
P-DMA0: PDMA0_TR_IN[0:15]
[0:23]
[0:3]
[68:91]
[92:95]
HSIOM: HSIOM_IO_INPUT[0:47]
CPUSS: FAULT_TR_OUT[0:3]
[0:2]
[0:2]
[1:3]
[4:6]
TCPWM[0]16: TCPWM0_16_TR_OUT0[0:2]
TCPWM[0]16M: TCPWM0_16M_TR_OUT0[0:2]
TCPWM[0]32: TCPWM0_32_TR_OUT0[0:2]
TCPWM[1]16: TCPWM1_16_TR_OUT0[0:83]
TCPWM[1]16M: TCPWM1_16M_TR_OUT0[0:11]
TCPWM[1]32: TCPWM1_32_TR_OUT0[0:12]
PASS: PASS_GEN_TR_OUT[0:5]
[0:2]
[7:9]
[0:29]
[0:11]
[0:12]
[0:5]
[10:39]
[40:51]
[52:64]
[65:70]
[71:72]
[73:76]
[0:16]
1
P-DMA0: PDMA0_TR_IN[16:31]
[0:1]
CPUSS: CTI_TR_OUT[0:1]
[0:3]
EVTGEN: EVTGEN_TR_OUT[0:15]
[0:15]
[0:31]
[1:16]
[17:48]
[0:16]
[0:7]
P-DMA1: PDMA1_TR_IN[0:15]
M-DMA: MDMA_TR_IN[0:7]
[30:83]
[24:47]
[49:102]
[103:126]
2
3
[0:2]
[0:2]
[1:3]
[4:6]
FLEXRAY: FLEXRAY_TT_TR_OUT
[0:31]
[0:15]
[0:7]
[0:2]
[0:2]
[0:2]
[0:15]
[0:5]
[0:6]
1
[1:32]
[33:48]
[49:56]
[57:59]
[60:62]
[63:65]
[66:81]
[82:87]
[88:94]
[95]
[0:11]
TCPWM[0]: TCPWM0_ALL_CNT_TR_IN[0:11]
4
SMIF: SMIF_TX_TR_OUT
SMIF: SMIF_RX_TR_OUT
1
[96]
AUDIOSS[0]: I2S0_TX_TR_OUT
AUDIOSS[0]: I2S0_RX_TR_OUT
:
[0],[0],...,[2],[2]
[97:102]
AUDIOSS[2]: I2S2_TX_TR_OUT
AUDIOSS[2]: I2S2_RX_TR_OUT
[0:2]
[0:2]
[0:2]
[0:83]
[0:11]
[0:12]
[0:4]
[0:4]
[0:4]
[0:4]
[0:4]
[0:4]
[0:4]
[0:4]
1
[1:3]
[4:6]
[7:9]
[10:93]
[94:105]
[106:118]
[119:123]
[124:128]
[129:133]
[134:138]
[139:143]
[144:148]
[149:153]
[154:158]
[159]
CAN[0]: CAN0_DBG_TR_OUT[0:4]
CAN[0]: CAN0_FIFO0_TR_OUT[0:4]
CAN[0]: CAN0_FIFO1_TR_OUT[0:4]
CAN[1]: CAN1_DBG_TR_OUT[0:4]
CAN[1]: CAN1_FIFO0_TR_OUT[0:4]
CAN[1]: CAN1_FIFO1_TR_OUT[0:4]
CAN[0]: CAN0_TT_TR_OUT[0:4]
CAN[1]: CAN1_TT_TR_OUT[0:4]
[0:11]
5
TCPWM[1]: TCPWM1_ALL_CNT_TR_IN[0:11]
[4:11]
[160:167]
[0:15]
[1:16]
[17]
1
1
SCB[0]: SCB_TX_TR_OUT[0]
SCB[0]: SCB_RX_TR_OUT[0]
[18]
1
[19]
SCB[0]: SCB_I2C_SCL_TR_OUT[0]
(repeat from [1] to [9])
27
1
[20:46]
[47]
SCB[10]: SCB_TX_TR_OUT[10]
SCB[10]: SCB_RX_TR_OUT[10]
SCB[10]: SCB_I2C_SCL_TR_OUT[10]
FLEXRAY: FLEXRAY_IBUF_TR_OUT
FLEXRAY: FLEXRAY_OBUF_TR_OUT
1
[48]
[0:28]
6
TCPWM[1]: TCPWM1_ALL_CNT_TR_IN[12:40]
1
[49]
1
[50]
1
[51]
[0:5]
[0:47]
[0:1]
[0:3]
[52:57]
[58:105]
[106:107]
[108:111]
[0:31]
[0:11]
[0:12]
[0:7]
[1:32]
[33:44]
[45:57]
[58:65]
[66:68]
[0:11]
PASS: PASS_GEN_TR_IN[0:11]
7
8
[12:14]
[0:4]
[0:4]
1
[1:5]
[6:10]
[11]
[0:4]
[5:9]
[10]
CAN[0]: CAN0_TT_TR_IN[0:4]
CAN[1]: CAN1_TT_TR_IN[0:4]
FLEXRAY: FLEXRAY_TT_TR_IN
[0]
[1]
HSIOM: HSIOM_IO_OUTPUT[0]
HSIOM: HSIOM_IO_OUTPUT[1]
[2:3]
[4]
CPUSS: CTI_TR_IN[0:1]
PERI: PERI_DEBUG_FREEZE_TR_IN
[1:5]
[6:10]
[5]
TR_GROUP10_OUTPUT[0:4]
TR_GROUP11_OUTPUT[0:4]
TR_GROUP12_OUTPUT[0:4]
PASS: PASS_DEBUG_FREEZE_TR_IN
SRSS: SRSS_WDT_DEBUG_FREEZE_TR_IN
SRSS: SRSS_MCWDT_DEBUG_FREEZE_TR_IN[2]
SRSS: SRSS_MCWDT_DEBUG_FREEZE_TR_IN[1]
SRSS: SRSS_MCWDT_DEBUG_FREEZE_TR_IN[0]
TCPWM[0]: TCPWM0_DEBUG_FREEZE_TR_IN
TCPWM[1]: TCPWM1_DEBUG_FREEZE_TR_IN
[6]
9
[11:15]
[7]
[8]
[9]
[10]
[11]
[0:142]
[0:10]
[0:10]
[0:10]
[0:4]
[1:143]
[144:154]
[155:165]
[166:176]
[177:181]
[182:186]
[187:191]
[192:196]
[197:201]
[202:206]
[207:211]
[212:216]
[217:218]
[219:222]
[223:238]
[0:4]
[0:4]
[0:4]
[0:4]
TR_GROUP9_INPUT[1:5]
10
[0:4]
[0:4]
[0:4]
[0:4]
[0:1]
[0:3]
[0:15]
[0:12]
[1:13]
[14:16]
[17:28]
[29:31]
[32:115]
[116:118]
[119]
[0:2]
[0:11]
[0:2]
[0:83]
[0:2]
1
[0:4]
11
TR_GROUP9_INPUT[6:10]
1
[120]
1
[121]
1
1
[122]
[123]
[0],[0],...,[2],[2]
[0:47]
[124:129]
[130:177]
[0:64]
[0:7]
[1:65]
[66:73]
[0:2]
[74:76]
TCPWM[0]16: TCPWM0_16_TR_OUT1[0:2]
TCPWM[0]16M: TCPWM0_16M_TR_OUT1[0:2]
TCPWM[0]32: TCPWM0_32_TR_OUT1[0:2]
TCPWM[1]16: TCPWM1_16_TR_OUT1[0:84]
TCPWM[1]16M: TCPWM1_16M_TR_OUT1[0:11]
TCPWM[1]32: TCPWM1_32_TR_OUT1[0:13]
[0:2]
[77:79]
[0:2]
[80:82]
[0:4]
12
TR_GROUP9_INPUT[11:15]
[0:83]
[0:11]
[0:12]
[0:5]
[83:166]
[167:178]
[179:191]
[192:197]
Figure 17-1
Trigger multiplexer group[30]
Note
30.The diagram shows only the TRIG_LABEL; the final trigger formation is based on the formula
TRIG_{PREFIX(IN/OUT)}_{MUX_x}_{TRIG_LABEL} and the information provided in Table 18-1, and Table 19-1.
Datasheet
69
002-21617 Rev. *K
2022-10-10
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Triggers group inputs
18
Triggers group inputs
Table 18-1
Input
Trigger inputs
Trigger
Description
MUX Group 0: P-DMA0 trigger multiplexer
1:32[31] PDMA0_TR_OUT[0:31]
Allow P-DMA0 to chain to itself. Channels 0 - 31 are dedicated for
chaining
33:48
PDMA1_TR_OUT[0:15]
Cross connections from P-DMA1 to P-DMA0, Channels 0-15 are
used
49:56
57:61
62:66
67
68:91
92:95
MDMA_TR_OUT[0:7]
CAN0_TT_TR_OUT[0:4]
CAN1_TT_TR_OUT[0:4]
FLEXRAY_TT_TR_OUT
HSIOM_IO_INPUT[0:23]
FAULT_TR_OUT[0:3]
Cross connections from M-DMA0 to P-DMA0
CAN0 Time Trigger Sync Outputs
CAN1 Time Trigger Sync Outputs
FlexRay0 timer trigger
I/O Inputs
Fault events
MUX Group 1: TCPWM to P-DMA0 trigger multiplexer
1:3
4:6
7:9
10:39
40:51
52:64
65:70
71:72
73:76
TCPWM0_16_TR_OUT0[0:2]
TCPWM0_16M_TR_OUT0[0:2]
TCPWM0_32_TR_OUT0[0:2]
TCPWM1_16_TR_OUT0[0:29]
16-bit TCPWM0 counters
16-bit Motor enhanced TCPWM0 counters
32-bit TCPWM0 counters
16-bit TCPWM1 counters
TCPWM1_16M_TR_OUT0[0:11] 16-bit Motor enhanced TCPWM1 counters
TCPWM1_32_TR_OUT0[0:12]
PASS_GEN_TR_OUT[0:5]
CTI_TR_OUT[0:1]
32-bit TCPWM1 counters
PASS SAR events
Trace events
EVTGEN_TR_OUT[0:3]
Event generator triggers
MUX Group 2: P-DMA1 trigger multiplexer
1:16
PDMA1_TR_OUT[0:15]
Allow P-DMA1 to chain to itself. Channels 0–15 are dedicated for
chaining
17:48
PDMA0_TR_OUT[0:31]
Cross connections from P-DMA0 to P-DMA1, channels 0–31 are
used.
49:102 TCPWM1_16_TR_OUT0[30:83] 16-bit TCPWM1 counters
103:126 HSIOM_IO_INPUT[24:47]
I/O Inputs
MUX Group 3: M-DMA0 trigger multiplexer
1:3
4:6
TCPWM0_16_TR_OUT0[0:2]
TCPWM0_16M_TR_OUT0[0:2]
16-bit TCPWM0 counters
16-bit Motor enhanced TCPWM0 counters
MUX Group 4: TCPWM0 Loop back trigger multiplexer
1:32
PDMA0_TR_OUT[0:31]
PDMA1_TR_OUT[0:15]
MDMA_TR_OUT[0:7]
TCPWM0_16_TR_OUT0[0:2]
TCPWM0_16M_TR_OUT0[0:2]
TCPWM0_32_TR_OUT0[0:2]
General-purpose P-DMA0 triggers
General-purpose P-DMA1 triggers
M-DMA0 triggers
16-bit TCPWM0 counters
16-bit motor enhanced TCPWM0 counters
32-bit TCPWM0 counters
33:48
49:56
57:59
60:62
63:65
Note
31.“x:y” depicts a range starting from ‘x’ through ‘y’.
Datasheet
70
002-21617 Rev. *K
2022-10-10
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Triggers group inputs
Table 18-1
Trigger inputs (continued)
Input
66:81
82:87
88:94
95
Trigger
TCPWM1_16_TR_OUT0[0:15]
TCPWM1_16M_TR_OUT0[0:5]
TCPWM1_32_TR_OUT0[0:6]
SMIF_TX_TR_OUT
Description
16-bit TCPWM1 counters
16-bit motor enhanced TCPWM1 counters
32-bit TCPWM1 counters
SMIF0 TX trigger
96
97
98
99
100
101
102
SMIF_RX_TR_OUT
I2S0_TX_TR_OUT
I2S0_RX_TR_OUT
I2S1_TX_TR_OUT
I2S1_RX_TR_OUT
I2S2_TX_TR_OUT
I2S2_RX_TR_OUT
SMIF0 RX trigger
I2S0 TX trigger
I2S0 RX trigger
I2S1 TX trigger
I2S1 RX trigger
I2S2 TX trigger
I2S2 RX trigger
MUX Group 5: TCPWM1 Loop back trigger multiplexer
1:3
4:6
7:9
TCPWM0_16_TR_OUT0[0:2]
TCPWM0_16M_TR_OUT0[0:2]
TCPWM0_32_TR_OUT0[0:2]
TCPWM1_16_TR_OUT0[0:83]
16-bit TCPWM0 counters
16-bit motor enhanced TCPWM0 counters
32-bit TCPWM0 counters
10:93
16-bit TCPWM1 counters
94:105 TCPWM1_16M_TR_OUT0[0:11] 16-bit Motor enhanced TCPWM1 counters
106:118 TCPWM1_32_TR_OUT0[0:12]
119:123 CAN0_DBG_TR_OUT[0:4]
124:128 CAN0_FIFO0_TR_OUT[0:4]
129:133 CAN0_FIFO1_TR_OUT[0:4]
134:138 CAN1_DBG_TR_OUT[0:4]
139:143 CAN1_FIFO0_TR_OUT[0:4]
144:148 CAN1_FIFO1_TR_OUT[0:4]
149:153 CAN0_TT_TR_OUT[0:4]
154:158 CAN1_TT_TR_OUT[0:4]
32-bit TCPWM1 counters
CAN0 M-DMA0 events
CAN0 FIFO0 events
CAN0 FIFO1 events
CAN1 M-DMA0 events
CAN1 FIFO0 events
CAN1 FIFO1 events
CAN0 TT sync outputs
CAN1 TT sync outputs
FlexRay0 timer trigger
Event generator triggers
159
FLEXRAY_TT_TR_OUT
160:167 EVTGEN_TR_OUT[4:11]
MUX Group 6: TCPWM1 trigger Multiplexer
1:16
17
18
19
20
21
22
23
24
25
26
27
TCPWM1_16_TR_OUT1[0:15]
SCB_TX_TR_OUT[0]
SCB_RX_TR_OUT[0]
SCB_I2C_SCL_TR_OUT[0]
SCB_TX_TR_OUT[1]
SCB_RX_TR_OUT[1]
SCB_I2C_SCL_TR_OUT[1]
SCB_TX_TR_OUT[2]
SCB_RX_TR_OUT[2]
SCB_I2C_SCL_TR_OUT[2]
SCB_TX_TR_OUT[3]
SCB_RX_TR_OUT[3]
16-bit TCPWM1 counters
SCB0 TX trigger
SCB0 RX trigger
SCB0 I2C trigger
SCB1 TX trigger
SCB1 RX trigger
SCB1 I2C trigger
SCB2 TX trigger
SCB2 RX trigger
SCB2 I2C trigger
SCB3 TX trigger
SCB3 RX trigger
Datasheet
71
002-21617 Rev. *K
2022-10-10
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Triggers group inputs
Table 18-1
Trigger inputs (continued)
Input
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
Trigger
SCB_I2C_SCL_TR_OUT[3]
SCB_TX_TR_OUT[4]
SCB_RX_TR_OUT[4]
SCB_I2C_SCL_TR_OUT[4]
SCB_TX_TR_OUT[5]
SCB_RX_TR_OUT[5]
SCB_I2C_SCL_TR_OUT[5]
SCB_TX_TR_OUT[6]
SCB_RX_TR_OUT[6]
SCB_I2C_SCL_TR_OUT[6]
SCB_TX_TR_OUT[7]
SCB_RX_TR_OUT[7]
SCB_I2C_SCL_TR_OUT[7]
SCB_TX_TR_OUT[8]
SCB_RX_TR_OUT[8]
SCB_I2C_SCL_TR_OUT[8]
SCB_TX_TR_OUT[9]
Description
SCB3 I2C trigger
SCB4 TX trigger
SCB4 RX trigger
SCB4 I2C trigger
SCB5 TX trigger
SCB5 RX trigger
SCB5 I2C trigger
SCB6 TX trigger
SCB6 RX trigger
SCB6 I2C trigger
SCB7 TX trigger
SCB7 RX trigger
SCB7 I2C trigger
SCB8 TX trigger
SCB8 RX trigger
SCB8 I2C trigger
SCB9 TX trigger
SCB9 RX trigger
SCB9 I2C trigger
SCB10 TX trigger
SCB10 RX trigger
SCB10 I2C trigger
FlexRay IBUF trigger
FlexRay OBUF trigger
PASS SAR ADC events
I/O Inputs
SCB_RX_TR_OUT[9]
SCB_I2C_SCL_TR_OUT[9]
SCB_TX_TR_OUT[10]
SCB_RX_TR_OUT[10]
SCB_I2C_SCL_TR_OUT[10]
FLEXRAY_IBUF_TR_OUT
FLEXRAY_OBUF_TR_OUT
PASS_GEN_TR_OUT[0:5]
52:57
58:105 HSIOM_IO_INPUT[0:47]
106:107 CTI_TR_IN[0:1]
108:111 FAULT_TR_OUT[0:3]
MUX Group 7: PASS trigger multiplexer
CPUSS CTI Trace events
Fault events
1:31
PDMA0_TR_OUT[0:31]
General purpose P-DMA0 triggers
32:44
45:57
58:65
66:68
TCPWM1_16M_TR_OUT0[0:11] 16-bit Motor enhanced TCPWM1 counters
TCPWM1_32_TR_OUT0[0:12]
HSIOM_IO_INPUT[0:7]
32-bit TCPWM1 counters
I/O Inputs
EVTGEN_TR_OUT[12:14]
Event generator triggers
MUX Group 8: CAN and FLEXRAY TT Sync
1:5
6:10
11
CAN0_TT_TR_OUT[0:4]
CAN1_TT_TR_OUT[0:4]
FLEXRAY_TT_TR_OUT
CAN0 TT sync outputs
CAN1 TT sync outputs
FlexRay timer trigger
MUX Group 9: Debug multiplexer
1:5
6:10
TR_GROUP10_OUTPUT[0:4]
TR_GROUP11_OUTPUT[0:4]
Output from debug reduction multiplexer #1
Output from debug reduction multiplexer #2
Datasheet
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Triggers group inputs
Table 18-1
Trigger inputs (continued)
Input
Trigger
Description
11:15
TR_GROUP12_OUTPUT[0:4]
Output from debug reduction multiplexer #3
MUX Group 10: Debug Reduction #1
1:143 PDMA0_TR_OUT[0:142]
General purpose P-DMA0 triggers
SCB TX triggers
SCB RX triggers
SCB I2C triggers
CAN0 M-DMA0
CAN0 FIFO0
CAN0 FIFO1
CAN0 TT sync outputs
CAN1 M-DMA0
CAN1 FIFO0
144:154 SCB_TX_TR_OUT[0:10]
155:165 SCB_RX_TR_OUT[0:10]
166:176 SCB_I2C_SCL_TR_OUT[0:10]
177:181 CAN0_DBG_TR_OUT[0:4]
182:186 CAN0_FIFO0_TR_OUT[0:4]
187:191 CAN0_FIFO1_TR_OUT[0:4]
192:196 CAN0_TT_TR_OUT[0:4]
197:201 CAN1_DBG_TR_OUT[0:4]
202:206 CAN1_FIFO0_TR_OUT[0:4]
207:211 CAN1_FIFO1_TR_OUT[0:4]
212:216 CAN1_TT_TR_OUT[0:4]
217:218 CTI_TR_OUT[0:1]
CAN1 FIFO1
CAN1 TT sync outputs
CPUSS CTI trace events
Fault events
219:222 FAULT_TR_OU[0:3]
223:238 EVTGEN_TR_OUT[0:15]
MUX Group 11: Debug Reduction #2
EVTGEN triggers
1:13
14:16
17:28
29:31
TCPWM1_32_TR_OUT0[0:12]
TCPWM0_32_TR_OUT0[0:2]
TCPWM1_16M_TR_OUT0[0:11] 16-bit Motor enhanced TCPWM1 counters
32-bit TCPWM1 counters
32-bit TCPWM0 counters
TCPWM0_16M_TR_OUT0[0:2]
16-bit Motor enhanced TCPWM0 counters
16-bit TCPWM1 counters
16-bit TCPWM0 counters
SMIF TX trigger
32:115 TCPWM1_16_TR_OUT0[0:83]
116:118 TCPWM0_16_TR_OUT0[0:2]
119
120
121
122
123
124
125
126
127
128
129
SMIF_TX_TR_OUT
SMIF_RX_TR_OUT
FLEXRAY_TT_TR_OUT
FLEXRAY_IBUF_TR_OUT
FLEXRAY_OBUF_TR_OUT
I2S0_TX_TR_OUT
I2S0_RX_TR_OUT
I2S1_TX_TR_OUT
I2S1_RX_TR_OUT
I2S2_TX_TR_OUT
SMIF RX trigger
FlexRay time trigger output
FlexRay M-DMA0 trans request
FlexRay M-DMA0 trans request
I2S0 TX trigger
I2S0 RX trigger
I2S1 TX trigger
I2S1 RX trigger
I2S2 TX trigger
I2S2_RX_TR_OUT
I2S2 RX trigger
130:177 HSIOM_IO_INPUT[0:47]
I/O inputs
MUX Group 12: Debug Reduction #3
1:65
66:73
74:76
77:79
PDMA1_TR_OUT[0:64]
MDMA_TR_OUT[0:7]
TCPWM0_16_TR_OUT1[0:2]
TCPWM0_16M_TR_OUT1[0:2]
General purpose P-DMA1 triggers
M-DMA0 triggers
16-bit TCPWM0 counters
16-bit Motor enhanced TCPWM0 counters
Datasheet
73
002-21617 Rev. *K
2022-10-10
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Triggers group inputs
Table 18-1
Trigger inputs (continued)
Input
Trigger
Description
80:82
TCPWM0_32_TR_OUT1[0:2]
32-bit TCPWM0 counters
16-bit TCPWM1 counters
83:166 TCPWM1_16_TR_OUT1[0:83]
167:178 TCPWM1_16M_TR_OUT1[0:11] 16-bit Motor enhanced TCPWM1 counters
179:191 TCPWM1_32_TR_OUT1[0:12]
192:197 PASS_GEN_TR_OUT[0:5]
32-bit TCPWM1 counters
PASS SAR ADC events
Datasheet
74
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2022-10-10
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Triggers group outputs
19
Triggers group outputs
Table 19-1
Trigger outputs
Output
MUX Group 0: P-DMA0 trigger multiplexer
0:15 PDMA0_TR_IN[0:15]
MUX Group 1: TCPWM to P-DMA0 trigger multiplexer
0:15 PDMA0_TR_IN[16:31]
MUX Group 2: P-DMA1 trigger multiplexer
0:15 PDMA1_TR_IN[0:15]
MUX Group 3: M-DMA0 trigger multiplexer
0:7 M-DMA_TR_IN[0:7]
MUX Group 4: TCPWM0 Loop back trigger multiplexer
0:11 TCPWM0_ALL_CNT_TR_IN[0:11]
MUX Group 5: TCPWM1 Loop back trigger multiplexer
0:11 TCPWM1_ALL_CNT_TR_IN[0:11]
MUX Group 6: TCPWM1 trigger Multiplexer
Trigger
Description
Triggers to P-DMA0[0:15]
Triggers to P-DMA0[16:31]
Triggers to P-DMA1
Triggers to M-DMA0
Triggers to TCPWM0
Triggers to TCPWM1
Triggers to TCPWM1
Triggers to PASS SAR ADCs
0:28
TCPWM1_ALL_CNT_TR_IN[12:40]
MUX Group 7: PASS trigger multiplexer
0:11
PASS_GEN_TR_IN[0:11]
MUX Group 8: CAN and FLEXRAY TT Sync
0:4
5:9
10
CAN0_TT_TR_IN[0:4]
CAN1_TT_TR_IN[0:4]
FLEXRAY_TT_TR_IN
CAN0 TT Sync Inputs
CAN1 TT Sync Inputs
FlexRay TT Inputs
MUX Group 9: Debug multiplexer
0
1
HSIOM_IO_OUTPUT[0]
HSIOM_IO_OUTPUT[1]
To HSIOM as an output
To HSIOM as an output
2:3
4
5
CTI_TR_IN[0:1]
To the Cross Trigger system
Signal to Freeze PERI operation
Signal to Freeze SAR ADC operation
Signal to Freeze WDT operation
PERI_DEBUG_FREEZE_TR_IN
PASS_DEBUG_FREEZE_TR_IN
SRSS_WDT_DEBUG_FREEZE_TR_IN
6
SRSS_MCWDT_DEBUG_-
FREEZE_TR_IN[2]
SRSS_MCWDT_DEBUG_-
FREEZE_TR_IN[1]
SRSS_MCWDT_DEBUG_-
FREEZE_TR_IN[0]
7
8
9
Signal to Freeze MCWDT2 operation
Signal to Freeze MCWDT1 operation
Signal to Freeze MCWDT0 operation
10
11
TCPWM0_DEBUG_FREEZE_TR_IN
TCPWM1_DEBUG_FREEZE_TR_IN
Signal to Freeze TCPWM0 operation
Signal to Freeze TCPWM1 operation
MUX Group 10: Debug Reduction #1
0:4
TR_GROUP9_INPUT[1:5]
To main debug multiplexer
To main debug multiplexer
To main debug multiplexer
MUX Group 11: Debug Reduction #2
0:4
TR_GROUP9_INPUT[6:10]
MUX Group 12: Debug Reduction #3
0:4
TR_GROUP9_INPUT[11:15]
Datasheet
75
002-21617 Rev. *K
2022-10-10
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Triggers one-to-one
20
Triggers one-to-one
One-To-One TriggerGroupNr = 0
P-DMA0: PDMA0_TR_IN[32]
CAN[0]: CAN0_DBG_TR_OUT[0]
CAN[0]: CAN0_FIFO0_TR_OUT[0]
CAN[0]: CAN0_FIFO1_TR_OUT[0]
CAN[0]: CAN0_DBG_TR_OUT[1]
CAN[0]: CAN0_FIFO0_TR_OUT[1]
CAN[0]: CAN0_FIFO1_TR_OUT[1]
CAN[0]: CAN0_DBG_TR_OUT[2]
CAN[0]: CAN0_FIFO0_TR_OUT[2]
CAN[0]: CAN0_FIFO1_TR_OUT[2]
CAN[0]: CAN0_DBG_TR_OUT[3]
CAN[0]: CAN0_FIFO0_TR_OUT[3]
CAN[0]: CAN0_FIFO1_TR_OUT[3]
CAN[0]: CAN0_DBG_TR_OUT[4]
CAN[0]: CAN0_FIFO0_TR_OUT[4]
CAN[0]: CAN0_FIFO1_TR_OUT[4]
P-DMA0: PDMA0_TR_IN[33]
P-DMA0: PDMA0_TR_IN[34]
P-DMA0: PDMA0_TR_IN[35]
P-DMA0: PDMA0_TR_IN[36]
P-DMA0: PDMA0_TR_IN[37]
P-DMA0: PDMA0_TR_IN[38]
P-DMA0: PDMA0_TR_IN[39]
P-DMA0: PDMA0_TR_IN[40]
P-DMA0: PDMA0_TR_IN[41]
P-DMA0: PDMA0_TR_IN[42]
P-DMA0: PDMA0_TR_IN[43]
P-DMA0: PDMA0_TR_IN[44]
P-DMA0: PDMA0_TR_IN[45]
P-DMA0: PDMA0_TR_IN[46]
One-To-One TriggerGroupNr = 1
PASS[0]: PASS0_CH_DONE_TO_PDMA0[0:31]
PASS[0]: PASS0_CH_DONE_TO_PDMA0[32:63]
PASS[0]: PASS0_CH_DONE_TO_PDMA0[64:95]
P-DMA0: PDMA0_TR_IN[47:78]
P-DMA0: PDMA0_TR_IN[79:110]
P-DMA0: PDMA0_TR_IN[111:142]
One-To-One TriggerGroupNr = 2
SCB[0]: SCB0_TX_TR_OUT
SCB[0]: SCB0_RX_TR_OUT
…
P-DMA1: PDMA1_TR_IN[16]
P-DMA1: PDMA1_TR_IN[17]
…
…
…
SCB[10]: SCB10_TX_TR_OUT
SCB[10]: SCB10_RX_TR_OUT
P-DMA1: PDMA1_TR_IN[36]
P-DMA1: PDMA1_TR_IN[37]
One-To-One TriggerGroupNr = 3
SMIF: SMIF_TX_TR_OUT
SMIF: SMIF_RX_TR_OUT
P-DMA1: PDMA1_TR_IN[53]
P-DMA1: PDMA1_TR_IN[54]
One-To-One TriggerGroupNr = 4
CAN[1]: CAN1_DBG_TR_OUT[0]
CAN[1]: CAN1_FIFO0_TR_OUT[0]
CAN[1]: CAN1_FIFO1_TR_OUT[0]
CAN[1]: CAN1_DBG_TR_OUT[1]
CAN[1]: CAN1_FIFO0_TR_OUT[1]
CAN[1]: CAN1_FIFO1_TR_OUT[1]
CAN[1]: CAN1_DBG_TR_OUT[2]
CAN[1]: CAN1_FIFO0_TR_OUT[2]
CAN[1]: CAN1_FIFO1_TR_OUT[2]
CAN[1]: CAN1_DBG_TR_OUT[3]
CAN[1]: CAN1_FIFO0_TR_OUT[3]
CAN[1]: CAN1_FIFO1_TR_OUT[3]
CAN[1]: CAN1_DBG_TR_OUT[4]
CAN[1]: CAN1_FIFO0_TR_OUT[4]
CAN[1]: CAN1_FIFO1_TR_OUT[4]
P-DMA1: PDMA1_TR_IN[38]
P-DMA1: PDMA1_TR_IN[39]
P-DMA1: PDMA1_TR_IN[40]
P-DMA1: PDMA1_TR_IN[41]
P-DMA1: PDMA1_TR_IN[42]
P-DMA1: PDMA1_TR_IN[43]
P-DMA1: PDMA1_TR_IN[44]
P-DMA1: PDMA1_TR_IN[45]
P-DMA1: PDMA1_TR_IN[46]
P-DMA1: PDMA1_TR_IN[47]
P-DMA1: PDMA1_TR_IN[48]
P-DMA1: PDMA1_TR_IN[49]
P-DMA1: PDMA1_TR_IN[50]
P-DMA1: PDMA1_TR_IN[51]
P-DMA1: PDMA1_TR_IN[52]
One-To-One TriggerGroupNr = 5
AUDIO: AUDIO0_TX_TR_OUT
AUDIO: AUDIO0_RX_TR_OUT
AUDIO: AUDIO1_TX_TR_OUT
AUDIO: AUDIO1_RX_TR_OUT
AUDIO: AUDIO2_TX_TR_OUT
AUDIO: AUDIO2_RX_TR_OUT
P-DMA1: PDMA1_TR_IN[55]
P-DMA1: PDMA1_TR_IN[56]
P-DMA1: PDMA1_TR_IN[57]
P-DMA1: PDMA1_TR_IN[58]
P-DMA1: PDMA1_TR_IN[59]
P-DMA1: PDMA1_TR_IN[60]
One-To-One TriggerGroupNr = 6
PASS[0]: PASS0_CH_RANGEVIO_TR_OUT[0:3]
PASS[0]: PASS0_CH_RANGEVIO_TR_OUT[4:31]
PASS[0]: PASS0_CH_RANGEVIO_TR_OUT[32:35]
PASS[0]: PASS0_CH_RANGEVIO_TR_OUT[36:63]
PASS[0]: PASS0_CH_RANGEVIO_TR_OUT[64:67]
PASS[0]: PASS0_CH_RANGEVIO_TR_OUT[68:95]
TCPWM[1]16M: TCPWM1_16M_ONE_CNT_TR_IN[0,3,6,9]
TCPWM[1]16: TCPWM1_16_ONE_CNT_TR_IN[0:27]
TCPWM[1]16M: TCPWM1_16M_ONE_CNT_TR_IN[1,4,7,10]
TCPWM[1]16: TCPWM1_16_ONE_CNT_TR_IN[28:55]
TCPWM[1]16M: TCPWM1_16M_ONE_CNT_TR_IN[2,5,8,11]
TCPWM[1]16: TCPWM1_16_ONE_CNT_TR_IN[56:83]
One-To-One TriggerGroupNr = 7
TCPWM[1]16M: TCPWM1_16M_TR_OUT1[0,3,6,9]
TCPWM[1]16: TCPWM1_16_TR_OUT1[0:27]
TCPWM[1]16M: TCPWM1_16M_TR_OUT1[1,4,7,10]
TCPWM[1]16: TCPWM1_16_TR_OUT1[28:55]
PASS[0]: PASS0_CH_TR_IN[0..3]
PASS[0]: PASS0_CH_TR_IN[4:31]
PASS[0]: PASS0_CH_TR_IN[32:35]
PASS[0]: PASS0_CH_TR_IN[36:63]
TCPWM[1]16M: TCPWM1_16M_TR_OUT1[2,5,8,11]
TCPWM[1]16: TCPWM1_16_TR_OUT1[56:83]
PASS[0]: PASS0_CH_TR_IN[64:67]
PASS[0]: PASS0_CH_TR_IN[68:95]
One-To-One TriggerGroupNr = 8
P-DMA1: PDMA1_TR_OUT[38]
P-DMA1: PDMA1_TR_OUT[41]
P-DMA1: PDMA1_TR_OUT[44]
P-DMA1: PDMA1_TR_OUT[47]
P-DMA1: PDMA1_TR_OUT[50]
CAN[1]: CAN1_DBG_TR_ACK[0]
CAN[1]: CAN1_DBG_TR_ACK[1]
CAN[1]: CAN1_DBG_TR_ACK[2]
CAN[1]: CAN1_DBG_TR_ACK[3]
CAN[1]: CAN1_DBG_TR_ACK[4]
One-To-One TriggerGroupNr = 9
P-DMA0: PDMA0_TR_OUT[32]
P-DMA0: PDMA0_TR_OUT[35]
P-DMA0: PDMA0_TR_OUT[38]
P-DMA0: PDMA0_TR_OUT[41]
P-DMA0: PDMA0_TR_OUT[44]
CAN[0]: CAN0_DBG_TR_ACK[0]
CAN[0]: CAN0_DBG_TR_ACK[1]
CAN[0]: CAN0_DBG_TR_ACK[2]
CAN[0]: CAN0_DBG_TR_ACK[3]
CAN[0]: CAN0_DBG_TR_ACK[4]
One-To-One TriggerGroupNr = 10
LIN[0]: LIN0_CMD_TR_IN[0:19]
TCPWM[1]16: TCPWM1_16_TR_OUT0[0:19]
One-To-One TriggerGroupNr = 11
FLEXRAY: FLEXRAY_IBF_TR_OUT
FLEXRAY: FLEXRAY_OBF_TR_OUT
P-DMA1: PDMA1_TR_IN[61]
P-DMA1: PDMA1_TR_IN[62]
One-To-One TriggerGroupNr = 12
P-DMA1: PDMA1_TR_OUT[61]
P-DMA1: PDMA1_TR_OUT[62]
P-DMA1: PDMA1_TR_IN[63]
P-DMA1: PDMA1_TR_IN[64]
One-To-One TriggerGroupNr = 13
P-DMA1: PDMA1_TR_OUT[63]
P-DMA1: PDMA1_TR_OUT[64]
FLEXRAY: FLEXRAY_IBF_TR_IN
FLEXRAY: FLEXRAY_OBF_TR_IN
Figure 20-1
Triggers one-to-one[32]
Note
32.The diagram shows only the TRIG_LABEL; the final trigger formation is based on the formula TRIG_{PREFIX(IN_1TO1/OUT_1-
TO1)}_{x}_{TRIG_LABEL} and the information provided in Table 20-1 on page 77.
Datasheet
76
002-21617 Rev. *K
2022-10-10
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Triggers one-to-one
Table 20-1
Triggers 1:1
Input
Trigger In
Trigger Out
Description
MUX Group 0: CAN0 to P-DMA0 Triggers
0
1
CAN0_DBG_TR_OUT[0]
CAN0_FIFO0_TR_OUT[0]
CAN0_FIFO1_TR_OUT[0]
CAN0_DBG_TR_OUT[1]
CAN0_FIFO0_TR_OUT[1]
CAN0_FIFO1_TR_OUT[1]
CAN0_DBG_TR_OUT[2]
CAN0_FIFO0_TR_OUT[2]
CAN0_FIFO1_TR_OUT[2]
CAN0_DBG_TR_OUT[3]
CAN0_FIFO0_TR_OUT[3]
CAN0_FIFO1_TR_OUT[3]
CAN0_DBG_TR_OUT[4]
CAN0_FIFO0_TR_OUT[4]
CAN0_FIFO1_TR_OUT[4]
PDMA0_TR_IN[32]
CAN0, Channel #0 P-DMA0 trigger
PDMA0_TR_IN[33]
PDMA0_TR_IN[34]
PDMA0_TR_IN[35]
PDMA0_TR_IN[36]
PDMA0_TR_IN[37]
PDMA0_TR_IN[38]
PDMA0_TR_IN[39]
PDMA0_TR_IN[40]
PDMA0_TR_IN[41]
PDMA0_TR_IN[42]
PDMA0_TR_IN[43]
PDMA0_TR_IN[44]
PDMA0_TR_IN[45]
PDMA0_TR_IN[46]
CAN0, Channel #0 FIFO0 trigger
CAN0, Channel #0 FIFO1 trigger
CAN0, Channel #1 P-DMA0 trigger
CAN0, Channel #1 FIFO0 trigger
CAN0, Channel #1 FIFO1 trigger
CAN0, Channel #2 P-DMA0 trigger
CAN0, Channel #2 FIFO0 trigger
CAN0, Channel #2 FIFO1 trigger
CAN0, Channel #3 P-DMA0 trigger
CAN0, Channel #3 FIFO0 trigger
CAN0, Channel #3 FIFO1 trigger
CAN0, Channel #4 P-DMA0 trigger
CAN0, Channel #4 FIFO0 trigger
CAN0, Channel #4 FIFO1 trigger
2
3
4
5
6
7
8
9
10
11
12
13
14
MUX Group 1: PASS SARx to P-DMA0 direct connect
0:31
32:63
64:95
PASS0_CH_DONE_TR_OUT[0:31]
PASS0_CH_DONE_TR_OUT[32:63]
PASS0_CH_DONE_TR_OUT[64:95]
PDMA0_TR_IN[47:78]
PDMA0_TR_IN[79:110]
PDMA0_TR_IN[111:142]
PASS SAR0 [0:31] to P-DMA0 direct connect
PASS SAR1 [0:31] to P-DMA0 direct connect
PASS SAR2 [0:31] to P-DMA0 direct connect
MUX Group 2: SCBx to P-DMA1 Triggers
0
1
SCB0_TX_TR_OUT
SCB0_RX_TR_OUT
SCB1_TX_TR_OUT
SCB1_RX_TR_OUT
SCB2_TX_TR_OUT
SCB2_RX_TR_OUT
SCB3_TX_TR_OUT
SCB3_RX_TR_OUT
SCB4_TX_TR_OUT
SCB4_RX_TR_OUT
SCB5_TX_TR_OUT
SCB5_RX_TR_OUT
SCB6_TX_TR_OUT
SCB6_RX_TR_OUT
SCB7_TX_TR_OUT
SCB7_RX_TR_OUT
SCB8_TX_TR_OUT
SCB8_RX_TR_OUT
SCB9_TX_TR_OUT
SCB9_RX_TR_OUT
SCB10_TX_TR_OUT
SCB10_RX_TR_OUT
PDMA1_TR_IN[16]
PDMA1_TR_IN[17]
PDMA1_TR_IN[18]
PDMA1_TR_IN[19]
PDMA1_TR_IN[20]
PDMA1_TR_IN[21]
PDMA1_TR_IN[22]
PDMA1_TR_IN[23]
PDMA1_TR_IN[24]
PDMA1_TR_IN[25]
PDMA1_TR_IN[26]
PDMA1_TR_IN[27]
PDMA1_TR_IN[28]
PDMA1_TR_IN[29]
PDMA1_TR_IN[30]
PDMA1_TR_IN[31]
PDMA1_TR_IN[32]
PDMA1_TR_IN[33]
PDMA1_TR_IN[34]
PDMA1_TR_IN[35]
PDMA1_TR_IN[36]
PDMA1_TR_IN[37]
SCB0 to P-DMA1 Trigger
SCB0 to P-DMA1 Trigger
SCB1 to P-DMA1 Trigger
SCB1 to P-DMA1 Trigger
SCB2 to P-DMA1 Trigger
SCB2 to P-DMA1 Trigger
SCB3 to P-DMA1 Trigger
SCB3 to P-DMA1 Trigger
SCB4 to P-DMA1 Trigger
SCB4 to P-DMA1 Trigger
SCB5 to P-DMA1 Trigger
SCB5 to P-DMA1 Trigger
SCB6 to P-DMA1 Trigger
SCB6 to P-DMA1 Trigger
SCB7 to P-DMA1 Trigger
SCB7 to P-DMA1 Trigger
SCB8 to P-DMA1 Trigger
SCB8 to P-DMA1 Trigger
SCB9 to P-DMA1 Trigger
SCB9 to P-DMA1 Trigger
SCB10 to P-DMA1 Trigger
SCB10 to P-DMA1 Trigger
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
Datasheet
77
002-21617 Rev. *K
2022-10-10
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Triggers one-to-one
Table 20-1
Triggers 1:1 (continued)
Input
Trigger In
Trigger Out
Description
MUX Group 3: SMIF0 to P-DMA1 Triggers
0
1
SMIF_TX_TR_OUT
SMIF_RX_TR_OUT
PDMA1_TR_IN[53]
SMIF0 to P-DMA1 Trigger
SMIF0 to P-DMA1 Trigger
PDMA1_TR_IN[54]
MUX Group 4: CAN1 to P-DMA1 triggers
0
1
CAN1_DBG_TR_OUT[0]
CAN1_FIFO0_TR_OUT[0]
CAN1_FIFO1_TR_OUT[0]
CAN1_DBG_TR_OUT[1]
CAN1_FIFO0_TR_OUT[1]
CAN1_FIFO1_TR_OUT[1]
CAN1_DBG_TR_OUT[2]
CAN1_FIFO0_TR_OUT[2]
CAN1_FIFO1_TR_OUT[2]
CAN1_DBG_TR_OUT[3]
CAN1_FIFO0_TR_OUT[3]
CAN1_FIFO1_TR_OUT[3]
CAN1_DBG_TR_OUT[4]
CAN1_FIFO0_TR_OUT[4]
PDMA1_TR_IN[38]
PDMA1_TR_IN[39]
PDMA1_TR_IN[40]
PDMA1_TR_IN[41]
PDMA1_TR_IN[42]
PDMA1_TR_IN[43]
PDMA1_TR_IN[44]
PDMA1_TR_IN[45]
PDMA1_TR_IN[46]
PDMA1_TR_IN[47]
PDMA1_TR_IN[48]
PDMA1_TR_IN[49]
PDMA1_TR_IN[50]
PDMA1_TR_IN[51]
PDMA1_TR_IN[52]
CAN1 Channel #0 P-DMA1 trigger
CAN1 Channel #0 FIFO0 trigger
CAN1 Channel #0 FIFO1 trigger
CAN1 Channel #1 P-DMA1 trigger
CAN1 Channel #1 FIFO0 trigger
CAN1 Channel #1 FIFO1 trigger
CAN1 Channel #2 P-DMA1 trigger
CAN1 Channel #2 FIFO0 trigger
CAN1 Channel #2 FIFO1 trigger
CAN1 Channel #3 P-DMA1 trigger
CAN1 Channel #3 FIFO0 trigger
CAN1 Channel #3 FIFO1 trigger
CAN1 Channel #4 P-DMA1 trigger
CAN1 Channel #4 FIFO0 trigger
CAN1 Channel #4 FIFO1 trigger
2
3
4
5
6
7
8
9
10
11
12
13
14
CAN1_FIFO1_TR_OUT[4]
2
MUX Group 5: I Sx to P-DMA1 Triggers
2
0
1
2
3
4
5
AUDIO0_TX_TR_OUT
AUDIO0_RX_TR_OUT
AUDIO1_TX_TR_OUT
AUDIO1_RX_TR_OUT
AUDIO2_TX_TR_OUT
AUDIO2_RX_TR_OUT
PDMA1_TR_IN[55]
PDMA1_TR_IN[56]
PDMA1_TR_IN[57]
PDMA1_TR_IN[58]
PDMA1_TR_IN[59]
PDMA1_TR_IN[60]
I S0 TX to P-DMA1 trigger
2
I S0 RX to P-DMA1 trigger
2
I S1 TX to P-DMA1 trigger
2
I S1 RX to P-DMA1 trigger
2
I S2 TX to P-DMA1 trigger
2
I S2 RX to P-DMA1 trigger
MUX Group 6: PASS SARx to TCPWM1 direct connect
[33]
0
1
PASS0_CH_RANGEVIO_TR_OUT[0]
PASS0_CH_RANGEVIO_TR_OUT[1]
PASS0_CH_RANGEVIO_TR_OUT[2]
PASS0_CH_RANGEVIO_TR_OUT[3]
PASS0_CH_RANGEVIO_TR_OUT[4]
PASS0_CH_RANGEVIO_TR_OUT[5]
PASS0_CH_RANGEVIO_TR_OUT[6]
PASS0_CH_RANGEVIO_TR_OUT[7]
PASS0_CH_RANGEVIO_TR_OUT[8]
PASS0_CH_RANGEVIO_TR_OUT[9]
PASS0_CH_RANGEVIO_TR_OUT[10]
PASS0_CH_RANGEVIO_TR_OUT[11]
PASS0_CH_RANGEVIO_TR_OUT[12]
PASS0_CH_RANGEVIO_TR_OUT[13]
PASS0_CH_RANGEVIO_TR_OUT[14]
TCPWM1_16M_ONE_CNT_TR_IN[0] SAR0 ch#0 , range violation to TCPWM1 Group #1 Counter #00 trig = 2
TCPWM1_16M_ONE_CNT_TR_IN[3] SAR0 ch#1, range violation to TCPWM1 Group #1 Counter #03 trig = 2
TCPWM1_16M_ONE_CNT_TR_IN[6] SAR0 ch#2, range violation to TCPWM1 Group #1 Counter #06 trig = 2
TCPWM1_16M_ONE_CNT_TR_IN[9] SAR0 ch#3, range violation to TCPWM1 Group #1 Counter #09 trig = 2
2
3
4
TCPWM1_16_ONE_CNT_TR_IN[0]
TCPWM1_16_ONE_CNT_TR_IN[1]
TCPWM1_16_ONE_CNT_TR_IN[2]
TCPWM1_16_ONE_CNT_TR_IN[3]
TCPWM1_16_ONE_CNT_TR_IN[4]
TCPWM1_16_ONE_CNT_TR_IN[5]
TCPWM1_16_ONE_CNT_TR_IN[6]
TCPWM1_16_ONE_CNT_TR_IN[7]
TCPWM1_16_ONE_CNT_TR_IN[8]
TCPWM1_16_ONE_CNT_TR_IN[9]
TCPWM1_16_ONE_CNT_TR_IN[10]
SAR0 ch#4, range violation to TCPWM1 Group #0 Counter #00 trig = 2
SAR0 ch#5, range violation to TCPWM1 Group #0 Counter #01 trig = 2
SAR0 ch#6, range violation to TCPWM1 Group #0 Counter #02 trig = 2
SAR0 ch#7, range violation to TCPWM1 Group #0 Counter #03 trig = 2
SAR0 ch#8, range violation to TCPWM1 Group #0 Counter #04 trig = 2
SAR0 ch#9, range violation to TCPWM1 Group #0 Counter #05 trig = 2
SAR0 ch#10, range violation to TCPWM1 Group #0 Counter #06 trig = 2
SAR0 ch#11, range violation to TCPWM1 Group #0 Counter #07 trig = 2
SAR0 ch#12, range violation to TCPWM1 Group #0 Counter #08 trig = 2
SAR0 ch#13, range violation to TCPWM1 Group #0 Counter #09 trig = 2
SAR0 ch#14, range violation to TCPWM1 Group #0 Counter #10 trig = 2
5
6
7
8
9
10
11
12
13
14
Note
33.Each logical channel of SAR ADC[x] can be connected to any of the SAR ADC[x]_y external pin. (x = 0, or 1, or, 2 and y=0 to max 31)
Datasheet
78
002-21617 Rev. *K
2022-10-10
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Triggers one-to-one
Table 20-1
Triggers 1:1 (continued)
Input
Trigger In
Trigger Out
Description
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
PASS0_CH_RANGEVIO_TR_OUT[15]
PASS0_CH_RANGEVIO_TR_OUT[16]
TCPWM1_16_ONE_CNT_TR_IN[11]
SAR0 ch#15, range violation to TCPWM1 Group #0 Counter #11 trig = 2
TCPWM1_16_ONE_CNT_TR_IN[12]
TCPWM1_16_ONE_CNT_TR_IN[13]
TCPWM1_16_ONE_CNT_TR_IN[14]
TCPWM1_16_ONE_CNT_TR_IN[15]
TCPWM1_16_ONE_CNT_TR_IN[16]
TCPWM1_16_ONE_CNT_TR_IN[17]
TCPWM1_16_ONE_CNT_TR_IN[18]
TCPWM1_16_ONE_CNT_TR_IN[19]
TCPWM1_16_ONE_CNT_TR_IN[20]
TCPWM1_16_ONE_CNT_TR_IN[21]
TCPWM1_16_ONE_CNT_TR_IN[22]
TCPWM1_16_ONE_CNT_TR_IN[23]
TCPWM1_16_ONE_CNT_TR_IN[24]
TCPWM1_16_ONE_CNT_TR_IN[25]
TCPWM1_16_ONE_CNT_TR_IN[26]
TCPWM1_16_ONE_CNT_TR_IN[27]
SAR0 ch#16, range violation to TCPWM1 Group #0 Counter #12 trig = 2
SAR0 ch#17, range violation to TCPWM1 Group #0 Counter #13 trig = 2
SAR0 ch#18, range violation to TCPWM1 Group #0 Counter #14 trig = 2
SAR0 ch#19, range violation to TCPWM1 Group #0 Counter #15 trig = 2
SAR0 ch#20, range violation to TCPWM1 Group #0 Counter #16 trig = 2
SAR0 ch#21, range violation to TCPWM1 Group #0 Counter #17 trig = 2
SAR0 ch#22, range violation to TCPWM1 Group #0 Counter #18 trig = 2
SAR0 ch#23, range violation to TCPWM1 Group #0 Counter #19 trig = 2
SAR0 ch#24, range violation to TCPWM1 Group #0 Counter #20 trig = 2
SAR0 ch#25, range violation to TCPWM1 Group #0 Counter #21 trig = 2
SAR0 ch#26, range violation to TCPWM1 Group #0 Counter #22 trig = 2
SAR0 ch#27, range violation to TCPWM1 Group #0 Counter #23 trig = 2
SAR0 ch#28, range violation to TCPWM1 Group #0 Counter #24 trig = 2
SAR0 ch#29, range violation to TCPWM1 Group #0 Counter #25 trig = 2
SAR0 ch#30, range violation to TCPWM1 Group #0 Counter #26 trig = 2
SAR0 ch#31, range violation to TCPWM1 Group #0 Counter #27 trig = 2
PASS0_CH_RANGEVIO_TR_OUT[17]
PASS0_CH_RANGEVIO_TR_OUT[18]
PASS0_CH_RANGEVIO_TR_OUT[19]
PASS0_CH_RANGEVIO_TR_OUT[20]
PASS0_CH_RANGEVIO_TR_OUT[21]
PASS0_CH_RANGEVIO_TR_OUT[22]
PASS0_CH_RANGEVIO_TR_OUT[23]
PASS0_CH_RANGEVIO_TR_OUT[24]
PASS0_CH_RANGEVIO_TR_OUT[25]
PASS0_CH_RANGEVIO_TR_OUT[26]
PASS0_CH_RANGEVIO_TR_OUT[27]
PASS0_CH_RANGEVIO_TR_OUT[28]
PASS0_CH_RANGEVIO_TR_OUT[29]
PASS0_CH_RANGEVIO_TR_OUT[30]
PASS0_CH_RANGEVIO_TR_OUT[31]
PASS0_CH_RANGEVIO_TR_OUT[32]
PASS0_CH_RANGEVIO_TR_OUT[33]
PASS0_CH_RANGEVIO_TR_OUT[34]
PASS0_CH_RANGEVIO_TR_OUT[35]
PASS0_CH_RANGEVIO_TR_OUT[36]
PASS0_CH_RANGEVIO_TR_OUT[37]
PASS0_CH_RANGEVIO_TR_OUT[38]
PASS0_CH_RANGEVIO_TR_OUT[39]
PASS0_CH_RANGEVIO_TR_OUT[40]
PASS0_CH_RANGEVIO_TR_OUT[41]
PASS0_CH_RANGEVIO_TR_OUT[42]
PASS0_CH_RANGEVIO_TR_OUT[43]
PASS0_CH_RANGEVIO_TR_OUT[44]
PASS0_CH_RANGEVIO_TR_OUT[45]
PASS0_CH_RANGEVIO_TR_OUT[46]
PASS0_CH_RANGEVIO_TR_OUT[47]
PASS0_CH_RANGEVIO_TR_OUT[48]
PASS0_CH_RANGEVIO_TR_OUT[49]
PASS0_CH_RANGEVIO_TR_OUT[50]
PASS0_CH_RANGEVIO_TR_OUT[51]
PASS0_CH_RANGEVIO_TR_OUT[52]
PASS0_CH_RANGEVIO_TR_OUT[53]
PASS0_CH_RANGEVIO_TR_OUT[54]
PASS0_CH_RANGEVIO_TR_OUT[55]
PASS0_CH_RANGEVIO_TR_OUT[56]
PASS0_CH_RANGEVIO_TR_OUT[57]
PASS0_CH_RANGEVIO_TR_OUT[58]
PASS0_CH_RANGEVIO_TR_OUT[59]
TCPWM1_16M_ONE_CNT_TR_IN[1] SAR1 ch#0, range violation to TCPWM1 Group #1 Counter #01 trig = 2
TCPWM1_16M_ONE_CNT_TR_IN[4] SAR1 ch#1, range violation to TCPWM1 Group #1 Counter #04 trig = 2
TCPWM1_16M_ONE_CNT_TR_IN[7] SAR1 ch#2, range violation to TCPWM1 Group #1 Counter #07 trig = 2
TCPWM1_16M_ONE_CNT_TR_IN[10] SAR1 ch#3, range violation to TCPWM1 Group #1 Counter #10 trig = 2
TCPWM1_16_ONE_CNT_TR_IN[28]
TCPWM1_16_ONE_CNT_TR_IN[29]
TCPWM1_16_ONE_CNT_TR_IN[30]
TCPWM1_16_ONE_CNT_TR_IN[31]
TCPWM1_16_ONE_CNT_TR_IN[32]
TCPWM1_16_ONE_CNT_TR_IN[33]
TCPWM1_16_ONE_CNT_TR_IN[34]
TCPWM1_16_ONE_CNT_TR_IN[35]
TCPWM1_16_ONE_CNT_TR_IN[36]
TCPWM1_16_ONE_CNT_TR_IN[37]
TCPWM1_16_ONE_CNT_TR_IN[38]
TCPWM1_16_ONE_CNT_TR_IN[39]
TCPWM1_16_ONE_CNT_TR_IN[40]
TCPWM1_16_ONE_CNT_TR_IN[41]
TCPWM1_16_ONE_CNT_TR_IN[42]
TCPWM1_16_ONE_CNT_TR_IN[43]
TCPWM1_16_ONE_CNT_TR_IN[44]
TCPWM1_16_ONE_CNT_TR_IN[45]
TCPWM1_16_ONE_CNT_TR_IN[46]
TCPWM1_16_ONE_CNT_TR_IN[47]
TCPWM1_16_ONE_CNT_TR_IN[48]
TCPWM1_16_ONE_CNT_TR_IN[49]
TCPWM1_16_ONE_CNT_TR_IN[50]
TCPWM1_16_ONE_CNT_TR_IN[51]
SAR1 ch#4, range violation to TCPWM1 Group #0 Counter #28 trig = 2
SAR1 ch#5, range violation to TCPWM1 Group #0 Counter #29 trig = 2
SAR1 ch#6, range violation to TCPWM1 Group #0 Counter #30 trig = 2
SAR1 ch#7, range violation to TCPWM1 Group #0 Counter #31 trig = 2
SAR1 ch#8, range violation to TCPWM1 Group #0 Counter #32 trig = 2
SAR1 ch#9, range violation to TCPWM1 Group #0 Counter #33 trig = 2
SAR1 ch#10, range violation to TCPWM1 Group #0 Counter #34 trig = 2
SAR1 ch#11, range violation to TCPWM1 Group #0 Counter #35 trig = 2
SAR1 ch#12, range violation to TCPWM1 Group #0 Counter #36 trig = 2
SAR1 ch#13, range violation to TCPWM1 Group #0 Counter #37 trig = 2
SAR1 ch#14, range violation to TCPWM1 Group #0 Counter #38 trig = 2
SAR1 ch#15, range violation to TCPWM1 Group #0 Counter #39 trig = 2
SAR1 ch#16, range violation to TCPWM1 Group #0 Counter #40 trig = 2
SAR1 ch#17, range violation to TCPWM1 Group #0 Counter #41 trig = 2
SAR1 ch#18, range violation to TCPWM1 Group #0 Counter #42 trig = 2
SAR1 ch#19, range violation to TCPWM1 Group #0 Counter #43 trig = 2
SAR1 ch#20, range violation to TCPWM1 Group #0 Counter #44 trig = 2
SAR1 ch#21, range violation to TCPWM1 Group #0 Counter #45 trig = 2
SAR1 ch#22, range violation to TCPWM1 Group #0 Counter #46 trig = 2
SAR1 ch#23, range violation to TCPWM1 Group #0 Counter #47 trig = 2
SAR1 ch#24, range violation to TCPWM1 Group #0 Counter #48 trig = 2
SAR1 ch#25, range violation to TCPWM1 Group #0 Counter #49 trig = 2
SAR1 ch#26, range violation to TCPWM1 Group #0 Counter #50 trig = 2
SAR1 ch#27, range violation to TCPWM1 Group #0 Counter #51 trig = 2
Datasheet
79
002-21617 Rev. *K
2022-10-10
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Triggers one-to-one
Table 20-1
Triggers 1:1 (continued)
Input
Trigger In
Trigger Out
Description
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
PASS0_CH_RANGEVIO_TR_OUT[60]
PASS0_CH_RANGEVIO_TR_OUT[61]
TCPWM1_16_ONE_CNT_TR_IN[52]
SAR1 ch#28, range violation to TCPWM1 Group #0 Counter #52 trig = 2
TCPWM1_16_ONE_CNT_TR_IN[53]
TCPWM1_16_ONE_CNT_TR_IN[54]
TCPWM1_16_ONE_CNT_TR_IN[55]
SAR1 ch#29, range violation to TCPWM1 Group #0 Counter #53 trig = 2
SAR1 ch#30, range violation to TCPWM1 Group #0 Counter #54 trig = 2
SAR1 ch#31, range violation to TCPWM1 Group #0 Counter #55 trig = 2
PASS0_CH_RANGEVIO_TR_OUT[62]
PASS0_CH_RANGEVIO_TR_OUT[63]
PASS0_CH_RANGEVIO_TR_OUT[64]
PASS0_CH_RANGEVIO_TR_OUT[65]
PASS0_CH_RANGEVIO_TR_OUT[66]
PASS0_CH_RANGEVIO_TR_OUT[67]
PASS0_CH_RANGEVIO_TR_OUT[68]
PASS0_CH_RANGEVIO_TR_OUT[69]
PASS0_CH_RANGEVIO_TR_OUT[70]
PASS0_CH_RANGEVIO_TR_OUT[71]
PASS0_CH_RANGEVIO_TR_OUT[72]
PASS0_CH_RANGEVIO_TR_OUT[73]
PASS0_CH_RANGEVIO_TR_OUT[74]
PASS0_CH_RANGEVIO_TR_OUT[75]
PASS0_CH_RANGEVIO_TR_OUT[76]
PASS0_CH_RANGEVIO_TR_OUT[77]
PASS0_CH_RANGEVIO_TR_OUT[78]
PASS0_CH_RANGEVIO_TR_OUT[79]
PASS0_CH_RANGEVIO_TR_OUT[80]
PASS0_CH_RANGEVIO_TR_OUT[81]
PASS0_CH_RANGEVIO_TR_OUT[82]
PASS0_CH_RANGEVIO_TR_OUT[83]
PASS0_CH_RANGEVIO_TR_OUT[84]
PASS0_CH_RANGEVIO_TR_OUT[85]
PASS0_CH_RANGEVIO_TR_OUT[86]
PASS0_CH_RANGEVIO_TR_OUT[87]
PASS0_CH_RANGEVIO_TR_OUT[88]
PASS0_CH_RANGEVIO_TR_OUT[89]
PASS0_CH_RANGEVIO_TR_OUT[90]
PASS0_CH_RANGEVIO_TR_OUT[91]
PASS0_CH_RANGEVIO_TR_OUT[92]
PASS0_CH_RANGEVIO_TR_OUT[93]
PASS0_CH_RANGEVIO_TR_OUT[94]
PASS0_CH_RANGEVIO_TR_OUT[95]
TCPWM1_16M_ONE_CNT_TR_IN[2] SAR2 ch#0, range violation to TCPWM1 Group #1 Counter #02 trig = 2
TCPWM1_16M_ONE_CNT_TR_IN[5] SAR2 ch#1, range violation to TCPWM1 Group #1 Counter #05 trig = 2
TCPWM1_16M_ONE_CNT_TR_IN[8] SAR2 ch#2, range violation to TCPWM1 Group #1 Counter #08 trig = 2
TCPWM1_16M_ONE_CNT_TR_IN[11] SAR2 ch#3, range violation to TCPWM1 Group #1 Counter #11 trig = 2
TCPWM1_16_ONE_CNT_TR_IN[56]
TCPWM1_16_ONE_CNT_TR_IN[57]
TCPWM1_16_ONE_CNT_TR_IN[58]
TCPWM1_16_ONE_CNT_TR_IN[59]
TCPWM1_16_ONE_CNT_TR_IN[60]
TCPWM1_16_ONE_CNT_TR_IN[61]
TCPWM1_16_ONE_CNT_TR_IN[62]
TCPWM1_16_ONE_CNT_TR_IN[63]
TCPWM1_16_ONE_CNT_TR_IN[64]
TCPWM1_16_ONE_CNT_TR_IN[65]
TCPWM1_16_ONE_CNT_TR_IN[66]
TCPWM1_16_ONE_CNT_TR_IN[67]
TCPWM1_16_ONE_CNT_TR_IN[68]
TCPWM1_16_ONE_CNT_TR_IN[69]
TCPWM1_16_ONE_CNT_TR_IN[70]
TCPWM1_16_ONE_CNT_TR_IN[71]
TCPWM1_16_ONE_CNT_TR_IN[72]
TCPWM1_16_ONE_CNT_TR_IN[73]
TCPWM1_16_ONE_CNT_TR_IN[74]
TCPWM1_16_ONE_CNT_TR_IN[75]
TCPWM1_16_ONE_CNT_TR_IN[76]
TCPWM1_16_ONE_CNT_TR_IN[77]
TCPWM1_16_ONE_CNT_TR_IN[78]
TCPWM1_16_ONE_CNT_TR_IN[79]
TCPWM1_16_ONE_CNT_TR_IN[80]
TCPWM1_16_ONE_CNT_TR_IN[81]
TCPWM1_16_ONE_CNT_TR_IN[82]
TCPWM1_16_ONE_CNT_TR_IN[83]
SAR2 ch#4, range violation to TCPWM1 Group #0 Counter #56 trig = 2
SAR2 ch#5, range violation to TCPWM1 Group #0 Counter #57 trig = 2
SAR2 ch#6, range violation to TCPWM1 Group #0 Counter #58 trig = 2
SAR2 ch#7, range violation to TCPWM1 Group #0 Counter #59 trig = 2
SAR2 ch#8, range violation to TCPWM1 Group #0 Counter #60 trig = 2
SAR2 ch#9, range violation to TCPWM1 Group #0 Counter #61 trig = 2
SAR2 ch#10, range violation to TCPWM1 Group #0 Counter #62 trig = 2
SAR2 ch#11, range violation to TCPWM1 Group #0 Counter #63 trig = 2
SAR2 ch#12, range violation to TCPWM1 Group #0 Counter #64 trig = 2
SAR2 ch#13, range violation to TCPWM1 Group #0 Counter #65 trig = 2
SAR2 ch#14, range violation to TCPWM1 Group #0 Counter #66 trig = 2
SAR2 ch#15, range violation to TCPWM1 Group #0 Counter #67 trig = 2
SAR2 ch#16, range violation to TCPWM1 Group #0 Counter #68 trig = 2
SAR2 ch#17, range violation to TCPWM1 Group #0 Counter #69 trig = 2
SAR2 ch#18, range violation to TCPWM1 Group #0 Counter #70 trig = 2
SAR2 ch#19, range violation to TCPWM1 Group #0 Counter #71 trig = 2
SAR2 ch#20, range violation to TCPWM1 Group #0 Counter #72 trig = 2
SAR2 ch#21, range violation to TCPWM1 Group #0 Counter #73 trig = 2
SAR2 ch#22, range violation to TCPWM1 Group #0 Counter #74 trig = 2
SAR2 ch#23, range violation to TCPWM1 Group #0 Counter #75 trig = 2
SAR2 ch#24, range violation to TCPWM1 Group #0 Counter #76 trig = 2
SAR2 ch#25, range violation to TCPWM1 Group #0 Counter #77 trig = 2
SAR2 ch#26, range violation to TCPWM1 Group #0 Counter #78 trig = 2
SAR2 ch#27, range violation to TCPWM1 Group #0 Counter #79 trig = 2
SAR2 ch#28, range violation to TCPWM1 Group #0 Counter #80 trig = 2
SAR2 ch#29, range violation to TCPWM1 Group #0 Counter #81 trig = 2
SAR2 ch#30, range violation to TCPWM1 Group #0 Counter #82 trig = 2
SAR2 ch#31, range violation to TCPWM1 Group #0 Counter #83 trig = 2
MUX Group 7: TCPWM1 to PASS SARx
0
1
TCPWM1_16M_TR_OUT1[0]
TCPWM1_16M_TR_OUT1[3]
TCPWM1_16M_TR_OUT1[6]
TCPWM1_16M_TR_OUT1[9]
TCPWM1_16_TR_OUT1[0:27]
PASS0_CH_TR_IN[0]
PASS0_CH_TR_IN[1]
PASS0_CH_TR_IN[2]
PASS0_CH_TR_IN[3]
PASS0_CH_TR_IN[4:31]
TCPWM1 Group #1 Counter #00 (PWM1_M_0) to SAR0 ch#0
TCPWM1 Group #1 Counter #03 (PWM1_M_3) to SAR0 ch#1
TCPWM1 Group #1 Counter #06 (PWM1_M_6) to SAR0 ch#2
TCPWM1 Group #1 Counter #09 (PWM1_M_9) to SAR0 ch#3
2
3
4:31
TCPWM1 Group #0 Counter #00 through 27 (PWM1_0 to PWM1_27) to SAR0
ch#4 through SAR0 ch#31
32
33
34
TCPWM1_16M_TR_OUT1[1]
TCPWM1_16M_TR_OUT1[4]
TCPWM1_16M_TR_OUT1[7]
PASS0_CH_TR_IN[32]
PASS0_CH_TR_IN[33]
PASS0_CH_TR_IN[34]
TCPWM1 Group #1 Counter #01 (PWM1_M_1) to SAR1 ch#0
TCPWM1 Group #1 Counter #04 (PWM1_M_4) to SAR1 ch#1
TCPWM1 Group #1 Counter #07 (PWM1_M_7) to SAR1 ch#2
Datasheet
80
002-21617 Rev. *K
2022-10-10
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Triggers one-to-one
Table 20-1
Triggers 1:1 (continued)
Input
Trigger In
Trigger Out
Description
35
TCPWM1_16M_TR_OUT1[10]
TCPWM1_16_TR_OUT1[28:55]
PASS0_CH_TR_IN[35]
TCPWM1 Group #1 Counter #10 (PWM1_M_10) to SAR1 ch#3
36:63
PASS0_CH_TR_IN[36:63]
TCPWM1 Group #0 Counter #28 through 55 (PWM1_28 to PWM1_55) to SAR1
ch#4 through SAR1 ch#31
64
65
TCPWM1_16M_TR_OUT1[2]
TCPWM1_16M_TR_OUT1[5]
TCPWM1_16M_TR_OUT1[8]
TCPWM1_16M_TR_OUT1[11]
TCPWM1_16_TR_OUT1[56:83]
PASS0_CH_TR_IN[64]
PASS0_CH_TR_IN[65]
PASS0_CH_TR_IN[66]
PASS0_CH_TR_IN[67]
PASS0_CH_TR_IN[68:95]
TCPWM1 Group #1 Counter #02 (PWM1_M_2) to SAR2 ch#0
TCPWM1 Group #1 Counter #05 (PWM1_M_5) to SAR2 ch#1
TCPWM1 Group #1 Counter #08 (PWM1_M_8) to SAR2 ch#2
TCPWM1 Group #1 Counter #11 (PWM1_M_11) to SAR2 ch#3
66
67
68:95
TCPWM1 Group #0 Counter #56 through 83 (PWM1_56 to PWM1_83) to SAR2
ch#4 through SAR2 ch#31
MUX Group 8: Acknowledge triggers from P-DMA1 to CAN1
0
1
2
3
4
PDMA1_TR_OUT[38]
PDMA1_TR_OUT[41]
PDMA1_TR_OUT[44]
PDMA1_TR_OUT[47]
PDMA1_TR_OUT[50]
CAN1_DBG_TR_ACK[0]
CAN1_DBG_TR_ACK[1]
CAN1_DBG_TR_ACK[2]
CAN1_DBG_TR_ACK[3]
CAN1_DBG_TR_ACK[4]
CAN1 Channel#0 P-DMA1 acknowledge
CAN1 Channel#1 P-DMA1 acknowledge
CAN1 Channel#2 P-DMA1 acknowledge
CAN1 Channel#3 P-DMA1 acknowledge
CAN1 Channel#4 P-DMA1 acknowledge
MUX Group 9: Acknowledge triggers from P-DMA0 to CAN0
0
1
2
3
4
PDMA0_TR_OUT[32]
PDMA0_TR_OUT[35]
PDMA0_TR_OUT[38]
PDMA0_TR_OUT[41]
PDMA0_TR_OUT[44]
CAN0_DBG_TR_ACK[0]
CAN0_DBG_TR_ACK[1]
CAN0_DBG_TR_ACK[2]
CAN0_DBG_TR_ACK[3]
CAN0_DBG_TR_ACK[4]
CAN0 Channel#0 P-DMA0 acknowledge
CAN0 Channel#1 P-DMA0 acknowledge
CAN0 Channel#2 P-DMA0 acknowledge
CAN0 Channel#3 P-DMA0 acknowledge
CAN0 Channel#4 P-DMA0 acknowledge
MUX Group 10: TCPWM1 to LIN0 triggers
0:19 TCPWM1_16_TR_OUT0[0:19]
MUX Group 11: FLEXRAY to P-DMA1 triggers
LIN0_CMD_TR_IN[0:19]
TCPWM1 (Group #0 Counter #00 to #19) to LIN0
0
1
FLEXRAY_IBF_TR_OUT
FLEXRAY_OBF_TR_OUT
PDMA1_TR_IN[61]
PDMA1_TR_IN[62]
FlexRay to P-DMA1
FlexRay to P-DMA1
MUX Group 12: P-DMA1 TO P-DMA1 triggers
0
1
PDMA1_TR_OUT[61]
PDMA1_TR_OUT[62]
PDMA1_TR_IN[63]
PDMA1_TR_IN[64]
P-DMA1 to P-DMA1
P-DMA1 to P-DMA1
MUX Group 13: P-DMA1 TO FLEXRAY triggers
0
1
PDMA1_TR_OUT[63]
PDMA1_TR_OUT[64]
FLEXRAY_IBF_TR_IN
FLEXRAY_OBF_TR_IN
P-DMA1 to FlexRay
P-DMA1 to FlexRay
Datasheet
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Peripheral clocks
21
Peripheral clocks
Table 21-1
Output
Peripheral clock assignments
Destination
Description
CPUSS root clocks (Group 0)
0
1
2
3
4
5
6
7
8
PCLK_CPUSS_CLOCK_TRACE_IN
Trace clock
PCLK_SMARTIO12_CLOCK
PCLK_SMARTIO13_CLOCK
PCLK_SMARTIO14_CLOCK
PCLK_SMARTIO15_CLOCK
PCLK_SMARTIO17_CLOCK
PCLK_TCPWM0_CLOCKS0
PCLK_TCPWM0_CLOCKS1
PCLK_TCPWM0_CLOCKS2
PCLK_TCPWM0_CLOCKS256
PCLK_TCPWM0_CLOCKS257
PCLK_TCPWM0_CLOCKS258
PCLK_TCPWM0_CLOCKS512
PCLK_TCPWM0_CLOCKS513
PCLK_TCPWM0_CLOCKS514
Smart I/O #12
Smart I/O #13
Smart I/O #14
Smart I/O #15
Smart I/O #17
TCPWM0 Group #0, Counter #0
TCPWM0 Group #0, Counter #1
TCPWM0 Group #0, Counter #2
TCPWM0 Group #1, Counter #0
TCPWM0 Group #1, Counter #1
TCPWM0 Group #1, Counter #2
TCPWM0 Group #2, Counter #0
TCPWM0 Group #2, Counter #1
TCPWM0 Group #2, Counter #2
9
10
11
12
13
14
COMM root clocks (Group 1)
0
1
2
3
4
5
6
7
8
PCLK_CANFD0_CLOCK_CAN0
CAN0, Channel #0
CAN0, Channel #1
CAN0, Channel #2
CAN0, Channel #3
CAN0, Channel #4
CAN1, Channel #0
CAN1, Channel #1
CAN1, Channel #2
CAN1, Channel #3
CAN1, Channel #4
LIN0, Channel #0
LIN0, Channel #1
LIN0, Channel #2
LIN0, Channel #3
LIN0, Channel #4
LIN0, Channel #5
LIN0, Channel #6
LIN0, Channel #7
LIN0, Channel #8
LIN0, Channel #9
LIN0, Channel #10
LIN0, Channel #11
PCLK_CANFD0_CLOCK_CAN1
PCLK_CANFD0_CLOCK_CAN2
PCLK_CANFD0_CLOCK_CAN3
PCLK_CANFD0_CLOCK_CAN4
PCLK_CANFD1_CLOCK_CAN0
PCLK_CANFD1_CLOCK_CAN1
PCLK_CANFD1_CLOCK_CAN2
PCLK_CANFD1_CLOCK_CAN3
PCLK_CANFD1_CLOCK_CAN4
PCLK_LIN0_CLOCK_CH_EN0
PCLK_LIN0_CLOCK_CH_EN1
PCLK_LIN0_CLOCK_CH_EN2
PCLK_LIN0_CLOCK_CH_EN3
PCLK_LIN0_CLOCK_CH_EN4
PCLK_LIN0_CLOCK_CH_EN5
PCLK_LIN0_CLOCK_CH_EN6
PCLK_LIN0_CLOCK_CH_EN7
PCLK_LIN0_CLOCK_CH_EN8
PCLK_LIN0_CLOCK_CH_EN9
PCLK_LIN0_CLOCK_CH_EN10
PCLK_LIN0_CLOCK_CH_EN11
9
10
11
12
13
14
15
16
17
18
19
20
21
Datasheet
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Peripheral clocks
Table 21-1
Peripheral clock assignments (continued)
Destination
Output
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
Description
PCLK_LIN0_CLOCK_CH_EN12
PCLK_LIN0_CLOCK_CH_EN13
PCLK_LIN0_CLOCK_CH_EN14
PCLK_LIN0_CLOCK_CH_EN15
PCLK_LIN0_CLOCK_CH_EN16
PCLK_LIN0_CLOCK_CH_EN17
PCLK_LIN0_CLOCK_CH_EN18
PCLK_LIN0_CLOCK_CH_EN19
PCLK_SCB0_CLOCK
PCLK_SCB1_CLOCK
PCLK_SCB2_CLOCK
PCLK_SCB3_CLOCK
PCLK_SCB4_CLOCK
PCLK_SCB5_CLOCK
PCLK_SCB6_CLOCK
PCLK_SCB7_CLOCK
PCLK_SCB8_CLOCK
PCLK_SCB9_CLOCK
PCLK_SCB10_CLOCK
PCLK_FLEXRAY0_CLK_FLEXRAY
PCLK_PASS0_CLOCK_SAR0
PCLK_PASS0_CLOCK_SAR1
PCLK_PASS0_CLOCK_SAR2
PCLK_TCPWM1_CLOCKS0
PCLK_TCPWM1_CLOCKS1
PCLK_TCPWM1_CLOCKS2
PCLK_TCPWM1_CLOCKS3
PCLK_TCPWM1_CLOCKS4
PCLK_TCPWM1_CLOCKS5
PCLK_TCPWM1_CLOCKS6
PCLK_TCPWM1_CLOCKS7
PCLK_TCPWM1_CLOCKS8
PCLK_TCPWM1_CLOCKS9
PCLK_TCPWM1_CLOCKS10
PCLK_TCPWM1_CLOCKS11
PCLK_TCPWM1_CLOCKS12
PCLK_TCPWM1_CLOCKS13
PCLK_TCPWM1_CLOCKS14
PCLK_TCPWM1_CLOCKS15
PCLK_TCPWM1_CLOCKS16
PCLK_TCPWM1_CLOCKS17
LIN0, Channel #12
LIN0, Channel #13
LIN0, Channel #14
LIN0, Channel #15
LIN0, Channel #16
LIN0, Channel #17
LIN0, Channel #18
LIN0, Channel #19
SCB0
SCB1
SCB2
SCB3
SCB4
SCB5
SCB6
SCB7
SCB8
SCB9
SCB10
FlexRay0 clock
SAR0
SAR1
SAR2
TCPWM1 Group #0, Counter #0
TCPWM1 Group #0, Counter #1
TCPWM1 Group #0, Counter #2
TCPWM1 Group #0, Counter #3
TCPWM1 Group #0, Counter #4
TCPWM1 Group #0, Counter #5
TCPWM1 Group #0, Counter #6
TCPWM1 Group #0, Counter #7
TCPWM1 Group #0, Counter #8
TCPWM1 Group #0, Counter #9
TCPWM1 Group #0, Counter #10
TCPWM1 Group #0, Counter #11
TCPWM1 Group #0, Counter #12
TCPWM1 Group #0, Counter #13
TCPWM1 Group #0, Counter #14
TCPWM1 Group #0, Counter #15
TCPWM1 Group #0, Counter #16
TCPWM1 Group #0, Counter #17
Datasheet
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Peripheral clocks
Table 21-1
Peripheral clock assignments (continued)
Output
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
Destination
PCLK_TCPWM1_CLOCKS18
PCLK_TCPWM1_CLOCKS19
PCLK_TCPWM1_CLOCKS20
PCLK_TCPWM1_CLOCKS21
PCLK_TCPWM1_CLOCKS22
PCLK_TCPWM1_CLOCKS23
PCLK_TCPWM1_CLOCKS24
PCLK_TCPWM1_CLOCKS25
PCLK_TCPWM1_CLOCKS26
PCLK_TCPWM1_CLOCKS27
PCLK_TCPWM1_CLOCKS28
PCLK_TCPWM1_CLOCKS29
PCLK_TCPWM1_CLOCKS30
PCLK_TCPWM1_CLOCKS31
PCLK_TCPWM1_CLOCKS32
PCLK_TCPWM1_CLOCKS33
PCLK_TCPWM1_CLOCKS34
PCLK_TCPWM1_CLOCKS35
PCLK_TCPWM1_CLOCKS36
PCLK_TCPWM1_CLOCKS37
PCLK_TCPWM1_CLOCKS38
PCLK_TCPWM1_CLOCKS39
PCLK_TCPWM1_CLOCKS40
PCLK_TCPWM1_CLOCKS41
PCLK_TCPWM1_CLOCKS42
PCLK_TCPWM1_CLOCKS43
PCLK_TCPWM1_CLOCKS44
PCLK_TCPWM1_CLOCKS45
PCLK_TCPWM1_CLOCKS46
PCLK_TCPWM1_CLOCKS47
PCLK_TCPWM1_CLOCKS48
PCLK_TCPWM1_CLOCKS49
PCLK_TCPWM1_CLOCKS50
PCLK_TCPWM1_CLOCKS51
PCLK_TCPWM1_CLOCKS52
PCLK_TCPWM1_CLOCKS53
PCLK_TCPWM1_CLOCKS54
PCLK_TCPWM1_CLOCKS55
PCLK_TCPWM1_CLOCKS56
PCLK_TCPWM1_CLOCKS57
PCLK_TCPWM1_CLOCKS58
Description
TCPWM1 Group #0, Counter #18
TCPWM1 Group #0, Counter #19
TCPWM1 Group #0, Counter #20
TCPWM1 Group #0, Counter #21
TCPWM1 Group #0, Counter #22
TCPWM1 Group #0, Counter #23
TCPWM1 Group #0, Counter #24
TCPWM1 Group #0, Counter #25
TCPWM1 Group #0, Counter #26
TCPWM1 Group #0, Counter #27
TCPWM1 Group #0, Counter #28
TCPWM1 Group #0, Counter #29
TCPWM1 Group #0, Counter #30
TCPWM1 Group #0, Counter #31
TCPWM1 Group #0, Counter #32
TCPWM1 Group #0, Counter #33
TCPWM1 Group #0, Counter #34
TCPWM1 Group #0, Counter #35
TCPWM1 Group #0, Counter #36
TCPWM1 Group #0, Counter #37
TCPWM1 Group #0, Counter #38
TCPWM1 Group #0, Counter #39
TCPWM1 Group #0, Counter #40
TCPWM1 Group #0, Counter #41
TCPWM1 Group #0, Counter #42
TCPWM1 Group #0, Counter #43
TCPWM1 Group #0, Counter #44
TCPWM1 Group #0, Counter #45
TCPWM1 Group #0, Counter #46
TCPWM1 Group #0, Counter #47
TCPWM1 Group #0, Counter #48
TCPWM1 Group #0, Counter #49
TCPWM1 Group #0, Counter #50
TCPWM1 Group #0, Counter #51
TCPWM1 Group #0, Counter #52
TCPWM1 Group #0, Counter #53
TCPWM1 Group #0, Counter #54
TCPWM1 Group #0, Counter #55
TCPWM1 Group #0, Counter #56
TCPWM1 Group #0, Counter #57
TCPWM1 Group #0, Counter #58
Datasheet
84
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Peripheral clocks
Table 21-1
Peripheral clock assignments (continued)
Output
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
Destination
PCLK_TCPWM1_CLOCKS59
PCLK_TCPWM1_CLOCKS60
PCLK_TCPWM1_CLOCKS61
PCLK_TCPWM1_CLOCKS62
PCLK_TCPWM1_CLOCKS63
PCLK_TCPWM1_CLOCKS64
PCLK_TCPWM1_CLOCKS65
PCLK_TCPWM1_CLOCKS66
PCLK_TCPWM1_CLOCKS67
PCLK_TCPWM1_CLOCKS68
PCLK_TCPWM1_CLOCKS69
PCLK_TCPWM1_CLOCKS70
PCLK_TCPWM1_CLOCKS71
PCLK_TCPWM1_CLOCKS72
PCLK_TCPWM1_CLOCKS73
PCLK_TCPWM1_CLOCKS74
PCLK_TCPWM1_CLOCKS75
PCLK_TCPWM1_CLOCKS76
PCLK_TCPWM1_CLOCKS77
PCLK_TCPWM1_CLOCKS78
PCLK_TCPWM1_CLOCKS79
PCLK_TCPWM1_CLOCKS80
PCLK_TCPWM1_CLOCKS81
PCLK_TCPWM1_CLOCKS82
PCLK_TCPWM1_CLOCKS83
PCLK_TCPWM1_CLOCKS256
PCLK_TCPWM1_CLOCKS257
PCLK_TCPWM1_CLOCKS258
PCLK_TCPWM1_CLOCKS259
PCLK_TCPWM1_CLOCKS260
PCLK_TCPWM1_CLOCKS261
PCLK_TCPWM1_CLOCKS262
PCLK_TCPWM1_CLOCKS263
PCLK_TCPWM1_CLOCKS264
PCLK_TCPWM1_CLOCKS265
PCLK_TCPWM1_CLOCKS266
PCLK_TCPWM1_CLOCKS267
PCLK_TCPWM1_CLOCKS512
PCLK_TCPWM1_CLOCKS513
PCLK_TCPWM1_CLOCKS514
PCLK_TCPWM1_CLOCKS515
Description
TCPWM1 Group #0, Counter #59
TCPWM1 Group #0, Counter #60
TCPWM1 Group #0, Counter #61
TCPWM1 Group #0, Counter #62
TCPWM1 Group #0, Counter #63
TCPWM1 Group #0, Counter #64
TCPWM1 Group #0, Counter #65
TCPWM1 Group #0, Counter #66
TCPWM1 Group #0, Counter #67
TCPWM1 Group #0, Counter #68
TCPWM1 Group #0, Counter #69
TCPWM1 Group #0, Counter #70
TCPWM1 Group #0, Counter #71
TCPWM1 Group #0, Counter #72
TCPWM1 Group #0, Counter #73
TCPWM1 Group #0, Counter #74
TCPWM1 Group #0, Counter #75
TCPWM1 Group #0, Counter #76
TCPWM1 Group #0, Counter #77
TCPWM1 Group #0, Counter #78
TCPWM1 Group #0, Counter #79
TCPWM1 Group #0, Counter #80
TCPWM1 Group #0, Counter #81
TCPWM1 Group #0, Counter #82
TCPWM1 Group #0, Counter #83
TCPWM1 Group #1, Counter #0
TCPWM1 Group #1, Counter #1
TCPWM1 Group #1, Counter #2
TCPWM1 Group #1, Counter #3
TCPWM1 Group #1, Counter #4
TCPWM1 Group #1, Counter #5
TCPWM1 Group #1, Counter #6
TCPWM1 Group #1, Counter #7
TCPWM1 Group #1, Counter #8
TCPWM1 Group #1, Counter #9
TCPWM1 Group #1, Counter #10
TCPWM1 Group #1, Counter #11
TCPWM1 Group #2, Counter #0
TCPWM1 Group #2, Counter #1
TCPWM1 Group #2, Counter #2
TCPWM1 Group #2, Counter #3
Datasheet
85
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Peripheral clocks
Table 21-1
Peripheral clock assignments (continued)
Output
145
146
147
148
149
150
151
152
Destination
PCLK_TCPWM1_CLOCKS516
PCLK_TCPWM1_CLOCKS517
PCLK_TCPWM1_CLOCKS518
PCLK_TCPWM1_CLOCKS519
PCLK_TCPWM1_CLOCKS520
PCLK_TCPWM1_CLOCKS521
PCLK_TCPWM1_CLOCKS522
PCLK_TCPWM1_CLOCKS523
PCLK_TCPWM1_CLOCKS524
Description
TCPWM1 Group #2, Counter #4
TCPWM1 Group #2, Counter #5
TCPWM1 Group #2, Counter #6
TCPWM1 Group #2, Counter #7
TCPWM1 Group #2, Counter #8
TCPWM1 Group #2, Counter #9
TCPWM1 Group #2, Counter #10
TCPWM1 Group #2, Counter #11
TCPWM1 Group #2, Counter #12
153
Datasheet
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Faults
22
Faults
Table 22-1
Fault assignments
Fault
Source
Description
CM0+ SMPU violation
DATA0[31:0]: Violating address.
DATA1[0]: User read.
DATA1[1]: User write.
DATA1[2]: User execute.
DATA1[3]: Privileged read.
DATA1[4]: Privileged write.
DATA1[5]: Privileged execute.
DATA1[6]: Non-secure.
0
CPUSS_MPU_VIO_0
DATA1[11:8]: Master identifier.
DATA1[15:12]: Protection context identifier.
DATA1[31]: '0' MPU violation; '1': SMPU violation.
1
2
CPUSS_MPU_VIO_1
CRYPTO SMPU violation. See CPUSS_MPU_VIO_0 description.
P-DMA0 MPU/SMPU violation. See CPUSS_MPU_VIO_0 description.
P-DMA1 MPU/SMPU violation. See CPUSS_MPU_VIO_0 description.
M-DMA0 MPU/SMPU violation. See CPUSS_MPU_VIO_0 description.
SDHC MPU/SMPU violation. See CPUSS_MPU_VIO_0 description.
Ethernet0 MPU/SMPU violation. See CPUSS_MPU_VIO_0 description.
Ethernet1 MPU/SMPU violation. See CPUSS_MPU_VIO_0 description.
CM7_1 MPU/SMPU violation. See CPUSS_MPU_VIO_0 description.
CM7_0 MPU/SMPU violation. See CPUSS_MPU_VIO_0 description.
Test Controller MPU/SMPU violation. See CPUSS_MPU_VIO_0 description.
CPUSS_MPU_VIO_2
CPUSS_MPU_VIO_3
CPUSS_MPU_VIO_4
CPUSS_MPU_VIO_5
CPUSS_MPU_VIO_9
CPUSS_MPU_VIO_10
CPUSS_MPU_VIO_13
CPUSS_MPU_VIO_14
CPUSS_MPU_VIO_15
3
4
5
9
10
13
14
15
Correctable ECC error in CM7_1 TCM memory
DATA0[23:2]: Violating address.
16
17
18
CPUSS_CM7_1_TCM_C_ECC
CPUSS_CM7_1_TCM_NC_ECC
CPUSS_CM7_0_CACHE_C_ECC
DATA1[7:0]: Syndrome of code word (at address offset 0x0).
DATA1[31:30]: 0= ITCM, 2=D0TCM, 3=D1TCM
Non Correctable ECC error in CM7_1 TCM memory.
See CPUSS_CM7_1_TCM_C_ECC description.
Correctable ECC error in CM7_0 Cache memories
DATA0[16:2]: location information: Tag/Data SRAM, Way, Index and line Offset, see CM7 UGRM
IEBR0/DEBR0 description for details.
DATA0[31]: 0=Instruction cache, 1= Data cache
Non Correctable ECC error in CM7_0 Cache memories.
See CPUSS_CM7_0_CACHE_C_ECC description.
19
20
21
25
CPUSS_CM7_0_CACHE_NC_ECC
CPUSS_CM7_1_CACHE_C_ECC
CPUSS_CM7_1_CACHE_NC_ECC
PERI_MS_VIO_4
Correctable ECC error in CM7_1 Cache memories.
See CPUSS_CM7_0_CACHE_C_ECC description.
Non Correctable ECC error in CM7_1 Cache memories.
See CPUSS_CM7_0_CACHE_C_ECC description.
P-DMA1 Peripheral Master Interface PPU violation.
See PERI_MS_VIO_0 description.
Peripheral protection SRAM correctable ECC violation
DATA0[10:0]: Violating address.
26
27
PERI_PERI_C_ECC
PERI_PERI_NC_ECC
DATA1[7:0]: Syndrome of SRAM word.
Peripheral protection SRAM non-correctable ECC violation
CM0+ Peripheral Master Interface PPU violation
DATA0[31:0]: Violating address.
DATA1[0]: User read.
DATA1[1]: User write.
DATA1[2]: User execute.
DATA1[3]: Privileged read.
28
PERI_MS_VIO_0
DATA1[4]: Privileged write.
DATA1[5]: Privileged execute.
DATA1[6]: Non-secure.
DATA1[11:8]: Master identifier.
DATA1[15:12]: Protection context identifier.
DATA1[31:28]: “0”: master interface, PPU violation, “1': timeout detected, “2”: bus error, other:
undefined.
CM7_0 Peripheral Master Interface PPU violation.
See PERI_MS_VIO_0 description.
29
30
PERI_MS_VIO_1
PERI_MS_VIO_2
CM7_1 Peripheral Master Interface PPU violation.
See PERI_MS_VIO_0 description.
Datasheet
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Faults
Table 22-1
Fault assignments (continued)
Fault
Source
Description
P-DMA0 Peripheral Master Interface PPU_3 violation.
See PERI_MS_VIO_0 description.
31
PERI_MS_VIO_3
Peripheral Group #0 violation.
DATA0[31:0]: Violating address.
DATA1[0]: User read.
DATA1[1]: User write.
DATA1[2]: User execute.
DATA1[3]: Privileged read.
32
PERI_GROUP_VIO_0
DATA1[4]: Privileged write.
DATA1[5]: Privileged execute.
DATA1[6]: Non-secure.
DATA1[11:8]: Master identifier.
DATA1[15:12]: Protection context identifier.
DATA1[31:28]: “0”: decoder or peripheral bus error, other: undefined.
33
34
35
36
37
38
40
41
PERI_GROUP_VIO_1
PERI_GROUP_VIO_2
PERI_GROUP_VIO_3
PERI_GROUP_VIO_4
PERI_GROUP_VIO_5
PERI_GROUP_VIO_6
PERI_GROUP_VIO_8
PERI_GROUP_VIO_9
Peripheral Group #1 violation. See PERI_GROUP_VIO_0 description.
Peripheral Group #2 violation. See PERI_GROUP_VIO_0 description.
Peripheral Group #3 violation. See PERI_GROUP_VIO_0 description.
Peripheral Group #4 violation. See PERI_GROUP_VIO_0 description.
Peripheral Group #5 violation. See PERI_GROUP_VIO_0 description.
Peripheral Group #6 violation. See PERI_GROUP_VIO_0 description.
Peripheral Group #8 violation. See PERI_GROUP_VIO_0 description.
Peripheral Group #9 violation. See PERI_GROUP_VIO_0 description.
Flash controller main flash bus error
FAULT_DATA0[26:0]: Violating address. Append 5'b00010 as most significant bits to derive 32-bit
system address.
48
CPUSS_FLASHC_MAIN_BUS_ERR
FAULT_DATA1[11:8]: Master identifier.
Flash controller main flash correctable ECC violation
DATA[26:0]: Violating address. Append 5'b00010 as most significant bits to derive 32-bit system
address.
DATA1[7:0]: Syndrome of 64-bit word (at address offset 0x00).
DATA1[15:8]: Syndrome of 64-bit word (at address offset 0x08).
DATA1[23:16]: Syndrome of 64-bit word (at address offset 0x10).
DATA1[31:24]: Syndrome of 64-bit word (at address offset 0x18).
49
CPUSS_FLASHC_MAIN_C_ECC
Flash controller main flash non-correctable ECC violation.
See CPUSS_FLASHC_MAIN_C_ECC description.
50
51
CPUSS_FLASHC_MAIN_NC_ECC
CPUSS_FLASHC_WORK_BUS_ERR
Flash controller work-flash bus error.
See CPUSS_FLASHC_MAIN_BUS_ERR description.
Flash controller work flash correctable ECC violation.
DATA0[26:0]: Violating address. Append 5'b00010 as most significant bits to derive 32-bit system
address.
52
53
CPUSS_FLASHC_WORK_C_ECC
CPUSS_FLASHC_WORK_NC_ECC
DATA1[6:0]: Syndrome of 32-bit word.
Flash controller work-flash non-correctable ECC violation.
See CPUSS_FLASHC_WORK_C_ECC description.
Flash controller CM0+ cache correctable ECC violation.
DATA0[26:0]: Violating address.
DATA1[6:0]: Syndrome of 32-bit SRAM word (at address offset 0x0).
DATA1[14:8]: Syndrome of 32-bit SRAM word (at address offset 0x4).
DATA1[22:16]: Syndrome of 32-bit SRAM word (at address offset 0x8).
DATA1[30:24]: Syndrome of 32-bit SRAM word (at address offset 0xc).
54
CPUSS_FLASHC_CM0_CA_C_ECC
Flash controller CM0+ cache non-correctable ECC violation.
See CPUSS_FLASHC_CM0_CA_C_ECC description.
55
56
57
CPUSS_FLASHC_CM0_CA_NC_ECC
CPUSS_CM7_0_TCM_C_ECC
CPUSS_CM7_0_TCM_NC_ECC
CPU CM7_0 TCM memory correctable ECC violation.
See CPUSS_CM7_1_TCM_C_ECC description.
CPU CM7_0 TCM memory non-correctable ECC violation.
See CPUSS_CM7_1_TCM_C_ECC description.
System memory controller 0 correctable ECC violation:
DATA0[31:0]: Violating address.
58
CPUSS_RAMC0_C_ECC
DATA1[6:0]: Syndrome of 32-bit SRAM code word.
System memory controller 0 non-correctable ECC violation.
See CPUSS_RAMC0_C_ECC description.
59
60
61
CPUSS_RAMC0_NC_ECC
CPUSS_RAMC1_C_ECC
CPUSS_RAMC1_NC_ECC
System memory controller 1 correctable ECC violation.
See CPUSS_RAMC0_C_ECC description.
System memory controller 1 non-correctable ECC violation.
See CPUSS_RAMC0_C_ECC description.
Datasheet
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Faults
Table 22-1
Fault assignments (continued)
Fault
Source
Description
System memory controller 2 correctable ECC violation.
See CPUSS_RAMC0_C_ECC description.
62
63
CPUSS_RAMC2_C_ECC
System memory controller 2 non-correctable ECC violation.
See CPUSS_RAMC0_C_ECC description.
CPUSS_RAMC2_NC_ECC
CPUSS_CRYPTO_C_ECC
CPUSS_CRYPTO_NC_ECC
CPUSS_DW0_C_ECC
Crypto memory correctable ECC violation.
DATA0[31:0]: Violating address.
DATA1[6:0]: Syndrome of Least Significant 32-bit SRAM.
DATA1[14:8]: Syndrome of Most Significant 32-bit SRAM.
64
65
70
CRYPTO memory non-correctable ECC violation.
See CPUSS_CRYPTO_C_ECC description.
P-DMA0 memory correctable ECC violation:
DATA0[11:0]: Violating DW SRAM address
(word address, assuming byte addressable).
DATA1[6:0]: Syndrome of 32-bit SRAM code word.
P-DMA0 memory non-correctable ECC violation.
See CPUSS_DW0_C_ECC description.
71
72
73
CPUSS_DW0_NC_ECC
CPUSS_DW1_C_ECC
CPUSS_DW1_NC_ECC
P-DMA1 memory correctable ECC violation.
See CPUSS_DW0_C_ECC description.
P-DMA1 memory non-correctable ECC violation.
See CPUSS_DW0_C_ECC description.
Flash code storage SRAM memory correctable ECC violation:
DATA0[15:0]: Address location in the eCT Flash SRAM.
DATA1[6:0]: Syndrome of 32-bit SRAM word.
74
75
CPUSS_FM_SRAM_C_ECC
CPUSS_FM_SRAM_NC_ECC
Flash code storage SRAM memory non-correctable ECC violation:
See CPUSS_FM_SRAMC_C_ECC description.
CAN0 message buffer correctable ECC violation:
DATA0[15:0]: Violating address.
80
81
CANFD_0_CAN_C_ECC
CANFD_0_CAN_NC_ECC
DATA0[22:16]: ECC violating data[38:32] from MRAM.
DATA0[27:24]: Master ID: 0-7 = CAN channel ID within mxttcanfd cluster, 8 = AHB I/F
DATA1[31:0]: ECC violating data[31:0] from MRAM.
CAN0 message buffer non-correctable ECC violation:
DATA0[15:0]: Violating address.
DATA0[22:16]: ECC violating data[38:32] from MRAM (not for Address Error).
DATA0[27:24]: Master ID: 0-7 = CAN channel ID within mxttcanfd cluster, 8 = AHB I/F
DATA0[30]: Write access, only possible for Address Error
DATA0[31]: Address Error: a CAN channel did an MRAM access above MRAM_SIZE
DATA1[31:0]: ECC violating data[31:0] from MRAM (not for Address Error).
CAN1 message buffer correctable ECC violation.
See CANFD_0_CAN_C_ECC description.
82
83
CANFD_1_CAN_C_ECC
CANFD_1_CAN_NC_ECC
CAN1 message buffer non-correctable ECC violation.
See CANFD_0_CAN_NC_ECC description.
Consolidated fault output for clock supervisors. Multiple CSV can detect a violation at the same
time.
DATA0[15:0]: CLK_HF* root CSV violation flags.
DATA0[24]: CLK_REF CSV violation flag (reference clock for CLK_HF CSVs)
DATA0[25]: CLK_LF CSV violation flag
90
91
92
SRSS_FAULT_CSV
SRSS_FAULT_SSV
SRSS_FAULT_MCWDT0
DATA0[26]: CLK_HVILO CSV violation flag
Consolidated fault output for supply supervisors. Multiple CSV can detect a violation at the same
time.
DATA0[0]: BOD on VDDA
DATA[1]: OVD on VDDA
DATA[16]: LVD/HVD #1
DATA0[17]: LVD/HVD #2
Fault output for MCWDT0 (all sub-counters) Multiple counters can detect a violation at the same
time.
DATA0[0]: MCWDT sub counter 0 LOWER_LIMIT
DATA0[1]: MCWDT sub counter 0 UPPER_LIMIT
DATA0[2]: MCWDT sub counter 1 LOWER_LIMIT
DATA0[3]: MCWDT sub counter 1 UPPER_LIMIT
Fault output for MCWDT1 (all sub-counters).
See SRSS_FAULT_MCWDT0 description.
93
94
SRSS_FAULT_MCWDT1
SRSS_FAULT_MCWDT2
Fault output for MCWDT2 (all sub-counters).
See SRSS_FAULT_MCWDT0 description.
Datasheet
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Peripheral protection unit fixed structure pairs
23
Peripheral protection unit fixed structure pairs
Protection pair is a pair PPU structures, a master, and a slave structure. The master structure protects the slave
structure, and the slave structure protects resources such as peripheral registers, or the peripheral itself.
Table 23-1
PPU fixed structure pairs
Pair No.
PPU Fixed Structure Pair
Address
Size
Description
0
PERI_MS_PPU_FX_PERI_MAIN
PERI_MS_PPU_FX_PERI_SECURE
0x40000200
0x40002000
0x40004010
0x40004050
0x40004090
0x400040C0
0x40004100
0x40004140
0x40004180
0x40004200
0x40004240
0x40004020
0x40004060
0x400040A0
0x400040E0
0x40004120
0x40004160
0x400041A0
0x40004220
0x40004260
0x40008000
0x40030000
0x40040000
0x40100000
0x40101000
0x40102000
0x40102100
0x40102120
0x40108000
0x40200000
0x40200400
0x40201000
0x40202000
0x40208000
0x4020A000
0x4020C000
0x40210000
0x40210100
0x40210200
0x40210300
0x40220000
0x00000040 Peripheral Interconnect main
0x00000004 Peripheral interconnect secure
0x00000004 Peripheral Group #0 main
0x00000004 Peripheral Group #1 main
0x00000004 Peripheral Group #2 main
0x00000020 Peripheral Group #3 main
0x00000020 Peripheral Group #4 main
0x00000020 Peripheral Group #5 main
0x00000020 Peripheral Group #6 main
0x00000020 Peripheral Group #8 main
0x00000020 Peripheral Group #9 main
0x00000004 Peripheral Group #0 boot
0x00000004 Peripheral Group #1 boot
0x00000004 Peripheral Group #2 boot
0x00000004 Peripheral Group #3 boot
0x00000004 Peripheral Group #4 boot
0x00000004 Peripheral Group #5 boot
0x00000004 Peripheral Group #6 boot
0x00000004 Peripheral Group #8 boot
0x00000004 Peripheral Group #9 boot
0x00008000 Peripheral trigger multiplexer
0x00001000 Peripheral master slave boot
0x00004000 Peripheral clock main
0x00000400 Crypto main
1
2
PERI_MS_PPU_FX_PERI_GR0_GROUP
PERI_MS_PPU_FX_PERI_GR1_GROUP
PERI_MS_PPU_FX_PERI_GR2_GROUP
PERI_MS_PPU_FX_PERI_GR3_GROUP
PERI_MS_PPU_FX_PERI_GR4_GROUP
PERI_MS_PPU_FX_PERI_GR5_GROUP
PERI_MS_PPU_FX_PERI_GR6_GROUP
PERI_MS_PPU_FX_PERI_GR8_GROUP
PERI_MS_PPU_FX_PERI_GR9_GROUP
PERI_MS_PPU_FX_PERI_GR0_BOOT
PERI_MS_PPU_FX_PERI_GR1_BOOT
PERI_MS_PPU_FX_PERI_GR2_BOOT
PERI_MS_PPU_FX_PERI_GR3_BOOT
PERI_MS_PPU_FX_PERI_GR4_BOOT
PERI_MS_PPU_FX_PERI_GR5_BOOT
PERI_MS_PPU_FX_PERI_GR6_BOOT
PERI_MS_PPU_FX_PERI_GR8_BOOT
PERI_MS_PPU_FX_PERI_GR9_BOOT
PERI_MS_PPU_FX_PERI_TR
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
PERI_MS_PPU_FX_PERI_MS_BOOT
PERI_MS_PPU_FX_PERI_PCLK_MAIN
PERI_MS_PPU_FX_CRYPTO_MAIN
PERI_MS_PPU_FX_CRYPTO_CRYPTO
PERI_MS_PPU_FX_CRYPTO_BOOT
PERI_MS_PPU_FX_CRYPTO_KEY0
PERI_MS_PPU_FX_CRYPTO_KEY1
PERI_MS_PPU_FX_CRYPTO_BUF
0x00000800 Crypto MMIO (Memory Mapped I/O)
0x00000100 Crypto boot
0x00000004 Crypto Key #0
0x00000004 Crypto Key #1
0x00002000 Crypto buffer
PERI_MS_PPU_FX_CPUSS_CM7_0
PERI_MS_PPU_FX_CPUSS_CM7_1
PERI_MS_PPU_FX_CPUSS_CM0
0x00000400 CM7_0 CPU core
0x00000400 CM7_1 CPU core
0x00001000 CM0+ CPU core
PERI_MS_PPU_FX_CPUSS_BOOT[34]
PERI_MS_PPU_FX_CPUSS_CM0_INT
PERI_MS_PPU_FX_CPUSS_CM7_0_INT
PERI_MS_PPU_FX_CPUSS_CM7_1_INT
PERI_MS_PPU_FX_FAULT_STRUCT0_MAIN
PERI_MS_PPU_FX_FAULT_STRUCT1_MAIN
PERI_MS_PPU_FX_FAULT_STRUCT2_MAIN
PERI_MS_PPU_FX_FAULT_STRUCT3_MAIN
PERI_MS_PPU_FX_IPC_STRUCT0_IPC
0x00000200 CPUSS boot
0x00001000 CPUSS CM0+ interrupts
0x00001000 CPUSS CM7_0 interrupts
0x00001000 CPUSS CM7_1 interrupts
0x00000100 CPUSS Fault Structure #0 main
0x00000100 CPUSS Fault Structure #1 main
0x00000100 CPUSS Fault Structure #2 main
0x00000100 CPUSS Fault Structure #3 main
0x00000020 CPUSS IPC Structure #0
Datasheet
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Peripheral protection unit fixed structure pairs
Table 23-1
PPU fixed structure pairs (continued)
Pair No.
PPU Fixed Structure Pair
Address
Size
Description
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
PERI_MS_PPU_FX_IPC_STRUCT1_IPC
PERI_MS_PPU_FX_IPC_STRUCT2_IPC
PERI_MS_PPU_FX_IPC_STRUCT3_IPC
PERI_MS_PPU_FX_IPC_STRUCT4_IPC
PERI_MS_PPU_FX_IPC_STRUCT5_IPC
PERI_MS_PPU_FX_IPC_STRUCT6_IPC
PERI_MS_PPU_FX_IPC_STRUCT7_IPC
PERI_MS_PPU_FX_IPC_INTR_STRUCT0_INTR
PERI_MS_PPU_FX_IPC_INTR_STRUCT1_INTR
PERI_MS_PPU_FX_IPC_INTR_STRUCT2_INTR
PERI_MS_PPU_FX_IPC_INTR_STRUCT3_INTR
PERI_MS_PPU_FX_IPC_INTR_STRUCT4_INTR
PERI_MS_PPU_FX_IPC_INTR_STRUCT5_INTR
PERI_MS_PPU_FX_IPC_INTR_STRUCT6_INTR
PERI_MS_PPU_FX_IPC_INTR_STRUCT7_INTR
PERI_MS_PPU_FX_PROT_SMPU_MAIN
PERI_MS_PPU_FX_PROT_MPU0_MAIN
PERI_MS_PPU_FX_PROT_MPU5_MAIN
PERI_MS_PPU_FX_PROT_MPU9_MAIN
PERI_MS_PPU_FX_PROT_MPU10_MAIN
PERI_MS_PPU_FX_PROT_MPU13_MAIN
PERI_MS_PPU_FX_PROT_MPU14_MAIN
PERI_MS_PPU_FX_PROT_MPU15_MAIN
PERI_MS_PPU_FX_FLASHC_MAIN
0x40220020
0x40220040
0x40220060
0x40220080
0x402200A0
0x402200C0
0x402200E0
0x40221000
0x40221020
0x40221040
0x40221060
0x40221080
0x402210A0
0x402210C0
0x402210E0
0x40230000
0x40234000
0x40235400
0x40236400
0x40236800
0x40237400
0x40237800
0x40237C00
0x40240000
0x40240008
0x40240200
0x40240400
0x402404E0
0x40240560
0x40240580
0x40240600
0x40240680
0x40240700
0x40240780
0x4024F000
0x4024F400
0x4024F500
0x40260000
0x40261000
0x40262000
0x40268000
0x40268100
0x00000020 CPUSS IPC Structure #1
0x00000020 CPUSS IPC Structure #2
0x00000020 CPUSS IPC Structure #3
0x00000020 CPUSS IPC Structure #4
0x00000020 CPUSS IPC Structure #5
0x00000020 CPUSS IPC Structure #6
0x00000020 CPUSS IPC Structure #7
0x00000010 CPUSS IPC Interrupt Structure #0
0x00000010 CPUSS IPC Interrupt Structure #1
0x00000010 CPUSS IPC Interrupt Structure #2
0x00000010 CPUSS IPC Interrupt Structure #3
0x00000010 CPUSS IPC Interrupt Structure #4
0x00000010 CPUSS IPC Interrupt Structure #5
0x00000010 CPUSS IPC Interrupt Structure #6
0x00000010 CPUSS IPC Interrupt Structure #7
0x00000040 Peripheral protection SMPU main
0x00000004 Peripheral protection MPU #0 main
0x00000400 Peripheral protection MPU #5 main
0x00000400 Peripheral protection MPU #9 main
0x00000400 Peripheral protection MPU #10 main
0x00000004 Peripheral protection MPU #13 main
0x00000004 Peripheral protection MPU #14 main
0x00000400 Peripheral protection MPU #15 main
0x00000008 Flash controller main
PERI_MS_PPU_FX_FLASHC_CMD
0x00000004 Flash controller command
0x00000100 Flash controller tests
PERI_MS_PPU_FX_FLASHC_DFT
PERI_MS_PPU_FX_FLASHC_CM0
0x00000080 Flash controller CM0+
PERI_MS_PPU_FX_FLASHC_CM7_0
PERI_MS_PPU_FX_FLASHC_CM7_1
PERI_MS_PPU_FX_FLASHC_CRYPTO
PERI_MS_PPU_FX_FLASHC_DW0
0x00000004 Flash controller CM7_0
0x00000004 Flash controller CM7_1
0x00000004 Flash controller Crypto
0x00000004 Flash controller P-DMA0
0x00000004 Flash controller P-DMA1
0x00000004 Flash controller M-DMA0
0x00000004 Flash External AHB-Lite Master 0
0x00000080 Flash management
PERI_MS_PPU_FX_FLASHC_DW1
PERI_MS_PPU_FX_FLASHC_DMAC
PERI_MS_PPU_FX_FLASHC_SLOW0
PERI_MS_PPU_FX_FLASHC_FlashMgmt[34]
PERI_MS_PPU_FX_FLASHC_MainSafety
PERI_MS_PPU_FX_FLASHC_WorkSafety
PERI_MS_PPU_FX_SRSS_GENERAL
PERI_MS_PPU_FX_SRSS_MAIN
0x00000008 Flash controller code-flash safety
0x00000004 Flash controller work-flash safety
0x00000400 SRSS General
0x00001000 SRSS main
PERI_MS_PPU_FX_SRSS_SECURE
0x00002000 SRSS secure
PERI_MS_PPU_FX_MCWDT0_CONFIG
PERI_MS_PPU_FX_MCWDT1_CONFIG
0x00000080 MCWDT #0 configuration
0x00000080 MCWDT #1 configuration
Note
34.Fixed PPU is configured inside the Boot and user is not allowed to change the attributes of this PPU.
Datasheet
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Peripheral protection unit fixed structure pairs
Table 23-1
PPU fixed structure pairs (continued)
Pair No.
PPU Fixed Structure Pair
Address
Size
Description
83
84
PERI_MS_PPU_FX_MCWDT2_CONFIG
PERI_MS_PPU_FX_MCWDT0_MAIN
0x40268200
0x40268080
0x40268180
0x40268280
0x4026C000
0x4026C040
0x40270000
0x40280000
0x40290000
0x40280100
0x40290100
0x40288000
0x40288040
0x40288080
0x402880C0
0x40288100
0x40288140
0x40288180
0x402881C0
0x40288200
0x40288240
0x40288280
0x402882C0
0x40288300
0x40288340
0x40288380
0x402883C0
0x40288400
0x40288440
0x40288480
0x402884C0
0x40288500
0x40288540
0x40288580
0x402885C0
0x40288600
0x40288640
0x40288680
0x402886C0
0x40288700
0x40288740
0x40288780
0x402887C0
0x40288800
0x40288840
0x00000080 MCWDT #2 configuration
0x00000040 MCWDT #0 main
85
PERI_MS_PPU_FX_MCWDT1_MAIN
0x00000040 MCWDT #1 main
86
PERI_MS_PPU_FX_MCWDT2_MAIN
0x00000040 MCWDT #2 main
87
PERI_MS_PPU_FX_WDT_CONFIG
0x00000020 System WDT configuration
0x00000020 System WDT main
0x00010000 SRSS backup
88
PERI_MS_PPU_FX_WDT_MAIN
89
PERI_MS_PPU_FX_BACKUP_BACKUP
90
PERI_MS_PPU_FX_DW0_DW
0x00000100 P-DMA0 main
91
PERI_MS_PPU_FX_DW1_DW
0x00000100 P-DMA1 main
92
PERI_MS_PPU_FX_DW0_DW_CRC
0x00000080 P-DMA0 CRC
93
PERI_MS_PPU_FX_DW1_DW_CRC
0x00000080 P-DMA1 CRC
94
PERI_MS_PPU_FX_DW0_CH_STRUCT0_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT1_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT2_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT3_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT4_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT5_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT6_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT7_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT8_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT9_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT10_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT11_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT12_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT13_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT14_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT15_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT16_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT17_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT18_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT19_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT20_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT21_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT22_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT23_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT24_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT25_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT26_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT27_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT28_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT29_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT30_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT31_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT32_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT33_CH
0x00000040 P-DMA0 Channel #0
0x00000040 P-DMA0 Channel #1
0x00000040 P-DMA0 Channel #2
0x00000040 P-DMA0 Channel #3
0x00000040 P-DMA0 Channel #4
0x00000040 P-DMA0 Channel #5
0x00000040 P-DMA0 Channel #6
0x00000040 P-DMA0 Channel #7
0x00000040 P-DMA0 Channel #8
0x00000040 P-DMA0 Channel #9
0x00000040 P-DMA0 Channel #10
0x00000040 P-DMA0 Channel #11
0x00000040 P-DMA0 Channel #12
0x00000040 P-DMA0 Channel #13
0x00000040 P-DMA0 Channel #14
0x00000040 P-DMA0 Channel #15
0x00000040 P-DMA0 Channel #16
0x00000040 P-DMA0 Channel #17
0x00000040 P-DMA0 Channel #18
0x00000040 P-DMA0 Channel #19
0x00000040 P-DMA0 Channel #20
0x00000040 P-DMA0 Channel #21
0x00000040 P-DMA0 Channel #22
0x00000040 P-DMA0 Channel #23
0x00000040 P-DMA0 Channel #24
0x00000040 P-DMA0 Channel #25
0x00000040 P-DMA0 Channel #26
0x00000040 P-DMA0 Channel #27
0x00000040 P-DMA0 Channel #28
0x00000040 P-DMA0 Channel #29
0x00000040 P-DMA0 Channel #30
0x00000040 P-DMA0 Channel #31
0x00000040 P-DMA0 Channel #32
0x00000040 P-DMA0 Channel #33
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
Datasheet
92
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Peripheral protection unit fixed structure pairs
Table 23-1
PPU fixed structure pairs (continued)
Pair No.
PPU Fixed Structure Pair
Address
Size
Description
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
PERI_MS_PPU_FX_DW0_CH_STRUCT34_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT35_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT36_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT37_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT38_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT39_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT40_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT41_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT42_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT43_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT44_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT45_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT46_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT47_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT48_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT49_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT50_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT51_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT52_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT53_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT54_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT55_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT56_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT57_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT58_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT59_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT60_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT61_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT62_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT63_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT64_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT65_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT66_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT67_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT68_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT69_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT70_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT71_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT72_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT73_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT74_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT75_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT76_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT77_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT78_CH
0x40288880
0x402888C0
0x40288900
0x40288940
0x40288980
0x402889C0
0x40288A00
0x40288A40
0x40288A80
0x40288AC0
0x40288B00
0x40288B40
0x40288B80
0x40288BC0
0x40288C00
0x40288C40
0x40288C80
0x40288CC0
0x40288D00
0x40288D40
0x40288D80
0x40288DC0
0x40288E00
0x40288E40
0x40288E80
0x40288EC0
0x40288F00
0x40288F40
0x40288F80
0x40288FC0
0x40289000
0x40289040
0x40289080
0x402890C0
0x40289100
0x40289140
0x40289180
0x402891C0
0x40289200
0x40289240
0x40289280
0x402892C0
0x40289300
0x40289340
0x40289380
0x00000040 P-DMA0 Channel #34
0x00000040 P-DMA0 Channel #35
0x00000040 P-DMA0 Channel #36
0x00000040 P-DMA0 Channel #37
0x00000040 P-DMA0 Channel #38
0x00000040 P-DMA0 Channel #39
0x00000040 P-DMA0 Channel #40
0x00000040 P-DMA0 Channel #41
0x00000040 P-DMA0 Channel #42
0x00000040 P-DMA0 Channel #43
0x00000040 P-DMA0 Channel #44
0x00000040 P-DMA0 Channel #45
0x00000040 P-DMA0 Channel #46
0x00000040 P-DMA0 Channel #47
0x00000040 P-DMA0 Channel #48
0x00000040 P-DMA0 Channel #49
0x00000040 P-DMA0 Channel #50
0x00000040 P-DMA0 Channel #51
0x00000040 P-DMA0 Channel #52
0x00000040 P-DMA0 Channel #53
0x00000040 P-DMA0 Channel #54
0x00000040 P-DMA0 Channel #55
0x00000040 P-DMA0 Channel #56
0x00000040 P-DMA0 Channel #57
0x00000040 P-DMA0 Channel #58
0x00000040 P-DMA0 Channel #59
0x00000040 P-DMA0 Channel #60
0x00000040 P-DMA0 Channel #61
0x00000040 P-DMA0 Channel #62
0x00000040 P-DMA0 Channel #63
0x00000040 P-DMA0 Channel #64
0x00000040 P-DMA0 Channel #65
0x00000040 P-DMA0 Channel #66
0x00000040 P-DMA0 Channel #67
0x00000040 P-DMA0 Channel #68
0x00000040 P-DMA0 Channel #69
0x00000040 P-DMA0 Channel #70
0x00000040 P-DMA0 Channel #71
0x00000040 P-DMA0 Channel #72
0x00000040 P-DMA0 Channel #73
0x00000040 P-DMA0 Channel #74
0x00000040 P-DMA0 Channel #75
0x00000040 P-DMA0 Channel #76
0x00000040 P-DMA0 Channel #77
0x00000040 P-DMA0 Channel #78
Datasheet
93
002-21617 Rev. *K
2022-10-10
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Peripheral protection unit fixed structure pairs
Table 23-1
PPU fixed structure pairs (continued)
Pair No.
PPU Fixed Structure Pair
Address
Size
Description
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
PERI_MS_PPU_FX_DW0_CH_STRUCT79_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT80_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT81_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT82_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT83_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT84_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT85_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT86_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT87_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT88_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT89_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT90_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT91_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT92_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT93_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT94_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT95_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT96_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT97_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT98_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT99_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT100_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT101_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT102_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT103_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT104_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT105_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT106_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT107_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT108_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT109_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT110_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT111_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT112_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT113_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT114_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT115_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT116_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT117_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT118_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT119_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT120_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT121_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT122_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT123_CH
0x402893C0
0x40289400
0x40289440
0x40289480
0x402894C0
0x40289500
0x40289540
0x40289580
0x402895C0
0x40289600
0x40289640
0x40289680
0x402896C0
0x40289700
0x40289740
0x40289780
0x402897C0
0x40289800
0x40289840
0x40289880
0x402898C0
0x40289900
0x40289940
0x40289980
0x402899C0
0x40289A00
0x40289A40
0x40289A80
0x40289AC0
0x40289B00
0x40289B40
0x40289B80
0x40289BC0
0x40289C00
0x40289C40
0x40289C80
0x40289CC0
0x40289D00
0x40289D40
0x40289D80
0x40289DC0
0x40289E00
0x40289E40
0x40289E80
0x40289EC0
0x00000040 P-DMA0 Channel #79
0x00000040 P-DMA0 Channel #80
0x00000040 P-DMA0 Channel #81
0x00000040 P-DMA0 Channel #82
0x00000040 P-DMA0 Channel #83
0x00000040 P-DMA0 Channel #84
0x00000040 P-DMA0 Channel #85
0x00000040 P-DMA0 Channel #86
0x00000040 P-DMA0 Channel #87
0x00000040 P-DMA0 Channel #88
0x00000040 P-DMA0 Channel #89
0x00000040 P-DMA0 Channel #90
0x00000040 P-DMA0 Channel #91
0x00000040 P-DMA0 Channel #92
0x00000040 P-DMA0 Channel #93
0x00000040 P-DMA0 Channel #94
0x00000040 P-DMA0 Channel #95
0x00000040 P-DMA0 Channel #96
0x00000040 P-DMA0 Channel #97
0x00000040 P-DMA0 Channel #98
0x00000040 P-DMA0 Channel #99
0x00000040 P-DMA0 Channel #100
0x00000040 P-DMA0 Channel #101
0x00000040 P-DMA0 Channel #102
0x00000040 P-DMA0 Channel #103
0x00000040 P-DMA0 Channel #104
0x00000040 P-DMA0 Channel #105
0x00000040 P-DMA0 Channel #106
0x00000040 P-DMA0 Channel #107
0x00000040 P-DMA0 Channel #108
0x00000040 P-DMA0 Channel #109
0x00000040 P-DMA0 Channel #110
0x00000040 P-DMA0 Channel #111
0x00000040 P-DMA0 Channel #112
0x00000040 P-DMA0 Channel #113
0x00000040 P-DMA0 Channel #114
0x00000040 P-DMA0 Channel #115
0x00000040 P-DMA0 Channel #116
0x00000040 P-DMA0 Channel #117
0x00000040 P-DMA0 Channel #118
0x00000040 P-DMA0 Channel #119
0x00000040 P-DMA0 Channel #120
0x00000040 P-DMA0 Channel #121
0x00000040 P-DMA0 Channel #122
0x00000040 P-DMA0 Channel #123
Datasheet
94
002-21617 Rev. *K
2022-10-10
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Peripheral protection unit fixed structure pairs
Table 23-1
PPU fixed structure pairs (continued)
Pair No.
PPU Fixed Structure Pair
Address
Size
Description
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
PERI_MS_PPU_FX_DW0_CH_STRUCT124_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT125_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT126_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT127_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT128_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT129_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT130_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT131_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT132_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT133_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT134_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT135_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT136_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT137_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT138_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT139_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT140_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT141_CH
PERI_MS_PPU_FX_DW0_CH_STRUCT142_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT0_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT1_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT2_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT3_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT4_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT5_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT6_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT7_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT8_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT9_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT10_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT11_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT12_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT13_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT14_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT15_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT16_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT17_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT18_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT19_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT20_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT21_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT22_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT23_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT24_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT25_CH
0x40289F00
0x40289F40
0x40289F80
0x40289FC0
0x4028A000
0x4028A040
0x4028A080
0x4028A0C0
0x4028A100
0x4028A140
0x4028A180
0x4028A1C0
0x4028A200
0x4028A240
0x4028A280
0x4028A2C0
0x4028A300
0x4028A340
0x4028A380
0x40298000
0x40298040
0x40298080
0x402980C0
0x40298100
0x40298140
0x40298180
0x402981C0
0x40298200
0x40298240
0x40298280
0x402982C0
0x40298300
0x40298340
0x40298380
0x402983C0
0x40298400
0x40298440
0x40298480
0x402984C0
0x40298500
0x40298540
0x40298580
0x402985C0
0x40298600
0x40298640
0x00000040 P-DMA0 Channel #124
0x00000040 P-DMA0 Channel #125
0x00000040 P-DMA0 Channel #126
0x00000040 P-DMA0 Channel #127
0x00000040 P-DMA0 Channel #128
0x00000040 P-DMA0 Channel #129
0x00000040 P-DMA0 Channel #130
0x00000040 P-DMA0 Channel #131
0x00000040 P-DMA0 Channel #132
0x00000040 P-DMA0 Channel #133
0x00000040 P-DMA0 Channel #134
0x00000040 P-DMA0 Channel #135
0x00000040 P-DMA0 Channel #136
0x00000040 P-DMA0 Channel #137
0x00000040 P-DMA0 Channel #138
0x00000040 P-DMA0 Channel #139
0x00000040 P-DMA0 Channel #140
0x00000040 P-DMA0 Channel #141
0x00000040 P-DMA0 Channel #142
0x00000040 P-DMA1 Channel #0
0x00000040 P-DMA1 Channel #1
0x00000040 P-DMA1 Channel #2
0x00000040 P-DMA1 Channel #3
0x00000040 P-DMA1 Channel #4
0x00000040 P-DMA1 Channel #5
0x00000040 P-DMA1 Channel #6
0x00000040 P-DMA1 Channel #7
0x00000040 P-DMA1 Channel #8
0x00000040 P-DMA1 Channel #9
0x00000040 P-DMA1 Channel #10
0x00000040 P-DMA1 Channel #11
0x00000040 P-DMA1 Channel #12
0x00000040 P-DMA1 Channel #13
0x00000040 P-DMA1 Channel #14
0x00000040 P-DMA1 Channel #15
0x00000040 P-DMA1 Channel #16
0x00000040 P-DMA1 Channel #17
0x00000040 P-DMA1 Channel #18
0x00000040 P-DMA1 Channel #19
0x00000040 P-DMA1 Channel #20
0x00000040 P-DMA1 Channel #21
0x00000040 P-DMA1 Channel #22
0x00000040 P-DMA1 Channel #23
0x00000040 P-DMA1 Channel #24
0x00000040 P-DMA1 Channel #25
Datasheet
95
002-21617 Rev. *K
2022-10-10
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Peripheral protection unit fixed structure pairs
Table 23-1
PPU fixed structure pairs (continued)
Pair No.
PPU Fixed Structure Pair
Address
Size
Description
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
PERI_MS_PPU_FX_DW1_CH_STRUCT26_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT27_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT28_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT29_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT30_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT31_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT32_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT33_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT34_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT35_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT36_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT37_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT38_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT39_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT40_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT41_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT42_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT43_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT44_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT45_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT46_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT47_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT48_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT49_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT50_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT51_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT52_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT53_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT54_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT55_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT56_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT57_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT58_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT59_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT60_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT61_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT62_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT63_CH
PERI_MS_PPU_FX_DW1_CH_STRUCT64_CH
PERI_MS_PPU_FX_DMAC_TOP
0x40298680
0x402986C0
0x40298700
0x40298740
0x40298780
0x402987C0
0x40298800
0x40298840
0x40298880
0x402988C0
0x40298900
0x40298940
0x40298980
0x402989C0
0x40298A00
0x40298A40
0x40298A80
0x40298AC0
0x40298B00
0x40298B40
0x40298B80
0x40298BC0
0x40298C00
0x40298C40
0x40298C80
0x40298CC0
0x40298D00
0x40298D40
0x40298D80
0x40298DC0
0x40298E00
0x40298E40
0x40298E80
0x40298EC0
0x40298F00
0x40298F40
0x40298F80
0x40298FC0
0x40299000
0x402A0000
0x402A1000
0x402A1100
0x402A1200
0x402A1300
0x402A1400
0x00000040 P-DMA1 Channel #26
0x00000040 P-DMA1 Channel #27
0x00000040 P-DMA1 Channel #28
0x00000040 P-DMA1 Channel #29
0x00000040 P-DMA1 Channel #30
0x00000040 P-DMA1 Channel #31
0x00000040 P-DMA1 Channel #32
0x00000040 P-DMA1 Channel #33
0x00000040 P-DMA1 Channel #34
0x00000040 P-DMA1 Channel #35
0x00000040 P-DMA1 Channel #36
0x00000040 P-DMA1 Channel #37
0x00000040 P-DMA1 Channel #38
0x00000040 P-DMA1 Channel #39
0x00000040 P-DMA1 Channel #40
0x00000040 P-DMA1 Channel #41
0x00000040 P-DMA1 Channel #42
0x00000040 P-DMA1 Channel #43
0x00000040 P-DMA1 Channel #44
0x00000040 P-DMA1 Channel #45
0x00000040 P-DMA1 Channel #46
0x00000040 P-DMA1 Channel #47
0x00000040 P-DMA1 Channel #48
0x00000040 P-DMA1 Channel #49
0x00000040 P-DMA1 Channel #50
0x00000040 P-DMA1 Channel #51
0x00000040 P-DMA1 Channel #52
0x00000040 P-DMA1 Channel #53
0x00000040 P-DMA1 Channel #54
0x00000040 P-DMA1 Channel #55
0x00000040 P-DMA1 Channel #56
0x00000040 P-DMA1 Channel #57
0x00000040 P-DMA1 Channel #58
0x00000040 P-DMA1 Channel #59
0x00000040 P-DMA1 Channel #60
0x00000040 P-DMA1 Channel #61
0x00000040 P-DMA1 Channel #62
0x00000040 P-DMA1 Channel #63
0x00000040 P-DMA1 Channel #64
0x00000010 M-DMA0 main
PERI_MS_PPU_FX_DMAC_CH0_CH
0x00000100 M-DMA0 Channel #0
0x00000100 M-DMA0 Channel #1
0x00000100 M-DMA0 Channel #2
0x00000100 M-DMA0 Channel #3
0x00000100 M-DMA0 Channel #4
PERI_MS_PPU_FX_DMAC_CH1_CH
PERI_MS_PPU_FX_DMAC_CH2_CH
PERI_MS_PPU_FX_DMAC_CH3_CH
PERI_MS_PPU_FX_DMAC_CH4_CH
Datasheet
96
002-21617 Rev. *K
2022-10-10
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Peripheral protection unit fixed structure pairs
Table 23-1
PPU fixed structure pairs (continued)
Pair No.
PPU Fixed Structure Pair
Address
Size
Description
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
PERI_MS_PPU_FX_DMAC_CH5_CH
PERI_MS_PPU_FX_DMAC_CH6_CH
0x402A1500
0x402A1600
0x402A1700
0x402C0000
0x402C0800
0x402F0000
0x40300000
0x40300010
0x40300020
0x40300030
0x40300040
0x40300050
0x40300060
0x40300070
0x40300080
0x40300090
0x403000A0
0x403000B0
0x403000C0
0x403000D0
0x403000E0
0x403000F0
0x40300100
0x40300110
0x40300120
0x40300130
0x40300140
0x40300150
0x40300160
0x40300170
0x40300180
0x40300190
0x403001A0
0x403001B0
0x403001C0
0x403001D0
0x403001E0
0x403001F0
0x40300200
0x40300210
0x40300220
0x40302000
0x40302200
0x40302240
0x40310000
0x00000100 M-DMA0 Channel #5
0x00000100 M-DMA0 Channel #6
0x00000100 M-DMA0 Channel #7
0x00000200 EFUSE control
0x00000200 EFUSE data
PERI_MS_PPU_FX_DMAC_CH7_CH
PERI_MS_PPU_FX_EFUSE_CTL
PERI_MS_PPU_FX_EFUSE_DATA
PERI_MS_PPU_FX_BIST
0x00001000 Built-in self test
0x00000008 HSIOm Port #0
0x00000008 HSIOm Port #1
0x00000008 HSIOm Port #2
0x00000008 HSIOm Port #3
0x00000008 HSIOm Port #4
0x00000008 HSIOm Port #5
0x00000008 HSIOm Port #6
0x00000008 HSIOm Port #7
0x00000008 HSIOm Port #8
0x00000008 HSIOm Port #9
0x00000008 HSIOm Port #10
0x00000008 HSIOm Port #11
0x00000008 HSIOm Port #12
0x00000008 HSIOm Port #13
0x00000008 HSIOm Port #14
0x00000008 HSIOm Port #15
0x00000008 HSIOm Port #16
0x00000008 HSIOm Port #17
0x00000008 HSIOm Port #18
0x00000008 HSIOm Port #19
0x00000008 HSIOm Port #20
0x00000008 HSIOm Port #21
0x00000008 HSIOm Port #22
0x00000008 HSIOm Port #23
0x00000008 HSIOm Port #24
0x00000008 HSIOm Port #25
0x00000008 HSIOm Port #26
0x00000008 HSIOm Port #27
0x00000008 HSIOm Port #28
0x00000008 HSIOm Port #29
0x00000008 HSIOm Port #30
0x00000008 HSIOm Port #31
0x00000008 HSIOm Port #32
0x00000008 HSIOm Port #33
0x00000008 HSIOm Port #34
0x00000010 HSIOm Analog multiplexer
0x00000010 HSIOm monitor
0x00000004 HSIOm Alternate JTAG
0x00000040 GPIO_ENH Port #0
PERI_MS_PPU_FX_HSIOM_PRT0_PRT
PERI_MS_PPU_FX_HSIOM_PRT1_PRT
PERI_MS_PPU_FX_HSIOM_PRT2_PRT
PERI_MS_PPU_FX_HSIOM_PRT3_PRT
PERI_MS_PPU_FX_HSIOM_PRT4_PRT
PERI_MS_PPU_FX_HSIOM_PRT5_PRT
PERI_MS_PPU_FX_HSIOM_PRT6_PRT
PERI_MS_PPU_FX_HSIOM_PRT7_PRT
PERI_MS_PPU_FX_HSIOM_PRT8_PRT
PERI_MS_PPU_FX_HSIOM_PRT9_PRT
PERI_MS_PPU_FX_HSIOM_PRT10_PRT
PERI_MS_PPU_FX_HSIOM_PRT11_PRT
PERI_MS_PPU_FX_HSIOM_PRT12_PRT
PERI_MS_PPU_FX_HSIOM_PRT13_PRT
PERI_MS_PPU_FX_HSIOM_PRT14_PRT
PERI_MS_PPU_FX_HSIOM_PRT15_PRT
PERI_MS_PPU_FX_HSIOM_PRT16_PRT
PERI_MS_PPU_FX_HSIOM_PRT17_PRT
PERI_MS_PPU_FX_HSIOM_PRT18_PRT
PERI_MS_PPU_FX_HSIOM_PRT19_PRT
PERI_MS_PPU_FX_HSIOM_PRT20_PRT
PERI_MS_PPU_FX_HSIOM_PRT21_PRT
PERI_MS_PPU_FX_HSIOM_PRT22_PRT
PERI_MS_PPU_FX_HSIOM_PRT23_PRT
PERI_MS_PPU_FX_HSIOM_PRT24_PRT
PERI_MS_PPU_FX_HSIOM_PRT25_PRT
PERI_MS_PPU_FX_HSIOM_PRT26_PRT
PERI_MS_PPU_FX_HSIOM_PRT27_PRT
PERI_MS_PPU_FX_HSIOM_PRT28_PRT
PERI_MS_PPU_FX_HSIOM_PRT29_PRT
PERI_MS_PPU_FX_HSIOM_PRT30_PRT
PERI_MS_PPU_FX_HSIOM_PRT31_PRT
PERI_MS_PPU_FX_HSIOM_PRT32_PRT
PERI_MS_PPU_FX_HSIOM_PRT33_PRT
PERI_MS_PPU_FX_HSIOM_PRT34_PRT
PERI_MS_PPU_FX_HSIOM_AMUX
PERI_MS_PPU_FX_HSIOM_MON
PERI_MS_PPU_FX_HSIOM_ALTJTAG
PERI_MS_PPU_FX_GPIO_PRT0_PRT
Datasheet
97
002-21617 Rev. *K
2022-10-10
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Peripheral protection unit fixed structure pairs
Table 23-1
PPU fixed structure pairs (continued)
Pair No.
PPU Fixed Structure Pair
Address
Size
Description
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
PERI_MS_PPU_FX_GPIO_PRT1_PRT
PERI_MS_PPU_FX_GPIO_PRT2_PRT
0x40310080
0x40310100
0x40310180
0x40310200
0x40310280
0x40310300
0x40310380
0x40310400
0x40310480
0x40310500
0x40310580
0x40310600
0x40310680
0x40310700
0x40310780
0x40310800
0x40310880
0x40310900
0x40310980
0x40310A00
0x40310A80
0x40310B00
0x40310B80
0x40310C00
0x40310C80
0x40310D00
0x40310D80
0x40310E00
0x40310E80
0x40310F00
0x40310F80
0x40311000
0x40311080
0x40311100
0x40310040
0x403100C0
0x40310140
0x403101C0
0x40310240
0x403102C0
0x40310340
0x403103C0
0x40310440
0x403104C0
0x40310540
0x00000040 GPIO_STD Port #1
0x00000040 GPIO_STD Port #2
PERI_MS_PPU_FX_GPIO_PRT3_PRT
PERI_MS_PPU_FX_GPIO_PRT4_PRT
PERI_MS_PPU_FX_GPIO_PRT5_PRT
PERI_MS_PPU_FX_GPIO_PRT6_PRT
PERI_MS_PPU_FX_GPIO_PRT7_PRT
PERI_MS_PPU_FX_GPIO_PRT8_PRT
PERI_MS_PPU_FX_GPIO_PRT9_PRT
PERI_MS_PPU_FX_GPIO_PRT10_PRT
PERI_MS_PPU_FX_GPIO_PRT11_PRT
PERI_MS_PPU_FX_GPIO_PRT12_PRT
PERI_MS_PPU_FX_GPIO_PRT13_PRT
PERI_MS_PPU_FX_GPIO_PRT14_PRT
PERI_MS_PPU_FX_GPIO_PRT15_PRT
PERI_MS_PPU_FX_GPIO_PRT16_PRT
PERI_MS_PPU_FX_GPIO_PRT17_PRT
PERI_MS_PPU_FX_GPIO_PRT18_PRT
PERI_MS_PPU_FX_GPIO_PRT19_PRT
PERI_MS_PPU_FX_GPIO_PRT20_PRT
PERI_MS_PPU_FX_GPIO_PRT21_PRT
PERI_MS_PPU_FX_GPIO_PRT22_PRT
PERI_MS_PPU_FX_GPIO_PRT23_PRT
PERI_MS_PPU_FX_GPIO_PRT24_PRT
PERI_MS_PPU_FX_GPIO_PRT25_PRT
PERI_MS_PPU_FX_GPIO_PRT26_PRT
PERI_MS_PPU_FX_GPIO_PRT27_PRT
PERI_MS_PPU_FX_GPIO_PRT28_PRT
PERI_MS_PPU_FX_GPIO_PRT29_PRT
PERI_MS_PPU_FX_GPIO_PRT30_PRT
PERI_MS_PPU_FX_GPIO_PRT31_PRT
PERI_MS_PPU_FX_GPIO_PRT32_PRT
PERI_MS_PPU_FX_GPIO_PRT33_PRT
PERI_MS_PPU_FX_GPIO_PRT34_PRT
PERI_MS_PPU_FX_GPIO_PRT0_CFG
PERI_MS_PPU_FX_GPIO_PRT1_CFG
PERI_MS_PPU_FX_GPIO_PRT2_CFG
PERI_MS_PPU_FX_GPIO_PRT3_CFG
PERI_MS_PPU_FX_GPIO_PRT4_CFG
PERI_MS_PPU_FX_GPIO_PRT5_CFG
PERI_MS_PPU_FX_GPIO_PRT6_CFG
PERI_MS_PPU_FX_GPIO_PRT7_CFG
PERI_MS_PPU_FX_GPIO_PRT8_CFG
PERI_MS_PPU_FX_GPIO_PRT9_CFG
PERI_MS_PPU_FX_GPIO_PRT10_CFG
0x00000040 GPIO_STD Port #3
0x00000040 GPIO_STD Port #4
0x00000040 GPIO_STD Port #5
0x00000040 GPIO_STD Port #6
0x00000040 GPIO_STD Port #7
0x00000040 GPIO_STD Port #8
0x00000040 GPIO_STD Port #9
0x00000040 GPIO_STD Port #10
0x00000040 GPIO_STD Port #11
0x00000040 GPIO_STD Port #12
0x00000040 GPIO_STD Port #13
0x00000040 GPIO_STD Port #14
0x00000040 GPIO_STD Port #15
0x00000040 GPIO_STD Port #16
0x00000040 GPIO_STD Port #17
0x00000040 GPIO_STD Port #18
0x00000040 GPIO_STD Port #19
0x00000040 GPIO_STD Port #20
0x00000040 GPIO_STD Port #21
0x00000040 GPIO_STD Port #22
0x00000040 GPIO_STD Port #23
0x00000040 HSIO_STD Port #24
0x00000040 HSIO_STD Port #25
0x00000040 HSIO_STD Port #26
0x00000040 HSIO_STD Port #27
0x00000040 GPIO_STD Port #28
0x00000040 GPIO_STD Port #29
0x00000040 GPIO_STD Port #30
0x00000040 GPIO_STD Port #31
0x00000040 GPIO_STD Port #32
0x00000040 HSIO_STD Port #33
0x00000040 HSIO_STD Port #34
0x00000020 GPIO_ENH Port #0 configuration
0x00000020 GPIO_STD Port #1 configuration
0x00000020 GPIO_STD Port #2 configuration
0x00000020 GPIO_STD Port #3 configuration
0x00000020 GPIO_STD Port #4 configuration
0x00000020 GPIO_STD Port #5 configuration
0x00000020 GPIO_STD Port #6 configuration
0x00000020 GPIO_STD Port #7 configuration
0x00000020 GPIO_STD Port #8 configuration
0x00000020 GPIO_STD Port #9 configuration
0x00000020 GPIO_STD Port #10 configuration
Datasheet
98
002-21617 Rev. *K
2022-10-10
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Peripheral protection unit fixed structure pairs
Table 23-1
PPU fixed structure pairs (continued)
Pair No.
PPU Fixed Structure Pair
Address
Size
Description
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
PERI_MS_PPU_FX_GPIO_PRT11_CFG
PERI_MS_PPU_FX_GPIO_PRT12_CFG
0x403105C0
0x40310640
0x403106C0
0x40310740
0x403107C0
0x40310840
0x403108C0
0x40310940
0x403109C0
0x40310A40
0x40310AC0
0x40310B40
0x40310BC0
0x40310C40
0x40310CC0
0x40310D40
0x40310DC0
0x40310E40
0x40310EC0
0x40310F40
0x40310FC0
0x40311040
0x403110C0
0x40311140
0x40314000
0x40315000
0x40320C00
0x40320D00
0x40320E00
0x40320F00
0x40321100
0x40380000
0x40380080
0x40380100
0x40388000
0x40388080
0x40388100
0x40390000
0x40390080
0x40390100
0x40580000
0x40580080
0x40580100
0x40580180
0x40580200
0x00000020 GPIO_STD Port #11 configuration
0x00000020 GPIO_STD Port #12 configuration
0x00000020 GPIO_STD Port #13 configuration
0x00000020 GPIO_STD Port #14 configuration
0x00000020 GPIO_STD Port #15 configuration
0x00000020 GPIO_STD Port #16 configuration
0x00000020 GPIO_STD Port #17 configuration
0x00000020 GPIO_STD Port #18 configuration
0x00000020 GPIO_STD Port #19 configuration
0x00000020 GPIO_STD Port #20 configuration
0x00000020 GPIO_STD Port #21 configuration
0x00000020 GPIO_STD Port #22 configuration
0x00000020 GPIO_STD Port #23 configuration
0x00000020 HSIO_STD Port #24 configuration
0x00000020 HSIO_STD Port #25 configuration
0x00000020 HSIO_STD Port #26 configuration
0x00000020 HSIO_STD Port #27 configuration
0x00000020 GPIO_STD Port #28 configuration
0x00000020 GPIO_STD Port #29 configuration
0x00000020 GPIO_STD Port #30 configuration
0x00000020 GPIO_STD Port #31 configuration
0x00000020 GPIO_STD Port #32 configuration
0x00000020 HSIO_STD Port #33 configuration
0x00000020 HSIO_STD Port #34 configuration
0x00000040 GPIO main
PERI_MS_PPU_FX_GPIO_PRT13_CFG
PERI_MS_PPU_FX_GPIO_PRT14_CFG
PERI_MS_PPU_FX_GPIO_PRT15_CFG
PERI_MS_PPU_FX_GPIO_PRT16_CFG
PERI_MS_PPU_FX_GPIO_PRT17_CFG
PERI_MS_PPU_FX_GPIO_PRT18_CFG
PERI_MS_PPU_FX_GPIO_PRT19_CFG
PERI_MS_PPU_FX_GPIO_PRT20_CFG
PERI_MS_PPU_FX_GPIO_PRT21_CFG
PERI_MS_PPU_FX_GPIO_PRT22_CFG
PERI_MS_PPU_FX_GPIO_PRT23_CFG
PERI_MS_PPU_FX_GPIO_PRT24_CFG
PERI_MS_PPU_FX_GPIO_PRT25_CFG
PERI_MS_PPU_FX_GPIO_PRT26_CFG
PERI_MS_PPU_FX_GPIO_PRT27_CFG
PERI_MS_PPU_FX_GPIO_PRT28_CFG
PERI_MS_PPU_FX_GPIO_PRT29_CFG
PERI_MS_PPU_FX_GPIO_PRT30_CFG
PERI_MS_PPU_FX_GPIO_PRT31_CFG
PERI_MS_PPU_FX_GPIO_PRT32_CFG
PERI_MS_PPU_FX_GPIO_PRT33_CFG
PERI_MS_PPU_FX_GPIO_PRT34_CFG
PERI_MS_PPU_FX_GPIO_GPIO
PERI_MS_PPU_FX_GPIO_TEST
0x00000008 GPIO test
PERI_MS_PPU_FX_SMARTIO_PRT12_PRT
PERI_MS_PPU_FX_SMARTIO_PRT13_PRT
PERI_MS_PPU_FX_SMARTIO_PRT14_PRT
PERI_MS_PPU_FX_SMARTIO_PRT15_PRT
PERI_MS_PPU_FX_SMARTIO_PRT17_PRT
PERI_MS_PPU_FX_TCPWM0_GRP0_CNT0_CNT
PERI_MS_PPU_FX_TCPWM0_GRP0_CNT1_CNT
PERI_MS_PPU_FX_TCPWM0_GRP0_CNT2_CNT
PERI_MS_PPU_FX_TCPWM0_GRP1_CNT0_CNT
PERI_MS_PPU_FX_TCPWM0_GRP1_CNT1_CNT
PERI_MS_PPU_FX_TCPWM0_GRP1_CNT2_CNT
PERI_MS_PPU_FX_TCPWM0_GRP2_CNT0_CNT
PERI_MS_PPU_FX_TCPWM0_GRP2_CNT1_CNT
PERI_MS_PPU_FX_TCPWM0_GRP2_CNT2_CNT
PERI_MS_PPU_FX_TCPWM1_GRP0_CNT0_CNT
PERI_MS_PPU_FX_TCPWM1_GRP0_CNT1_CNT
PERI_MS_PPU_FX_TCPWM1_GRP0_CNT2_CNT
PERI_MS_PPU_FX_TCPWM1_GRP0_CNT3_CNT
PERI_MS_PPU_FX_TCPWM1_GRP0_CNT4_CNT
0x00000100 SMART I/O #12
0x00000100 SMART I/O #13
0x00000100 SMART I/O #14
0x00000100 SMART I/O #15
0x00000100 SMART I/O #17
0x00000080 TCPWM0 Group #0, Counter #0
0x00000080 TCPWM0 Group #0, Counter #1
0x00000080 TCPWM0 Group #0, Counter #2
0x00000080 TCPWM0 Group #1, Counter #0
0x00000080 TCPWM0 Group #1, Counter #1
0x00000080 TCPWM0 Group #1, Counter #2
0x00000080 TCPWM0 Group #2, Counter #0
0x00000080 TCPWM0 Group #2, Counter #1
0x00000080 TCPWM0 Group #2, Counter #2
0x00000080 TCPWM1 Group #0, Counter #0
0x00000080 TCPWM1 Group #0, Counter #1
0x00000080 TCPWM1 Group #0, Counter #2
0x00000080 TCPWM1 Group #0, Counter #3
0x00000080 TCPWM1 Group #0, Counter #4
Datasheet
99
002-21617 Rev. *K
2022-10-10
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Peripheral protection unit fixed structure pairs
Table 23-1
PPU fixed structure pairs (continued)
Pair No.
PPU Fixed Structure Pair
Address
Size
Description
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
PERI_MS_PPU_FX_TCPWM1_GRP0_CNT5_CNT
PERI_MS_PPU_FX_TCPWM1_GRP0_CNT6_CNT
PERI_MS_PPU_FX_TCPWM1_GRP0_CNT7_CNT
PERI_MS_PPU_FX_TCPWM1_GRP0_CNT8_CNT
PERI_MS_PPU_FX_TCPWM1_GRP0_CNT9_CNT
PERI_MS_PPU_FX_TCPWM1_GRP0_CNT10_CNT
PERI_MS_PPU_FX_TCPWM1_GRP0_CNT11_CNT
PERI_MS_PPU_FX_TCPWM1_GRP0_CNT12_CNT
PERI_MS_PPU_FX_TCPWM1_GRP0_CNT13_CNT
PERI_MS_PPU_FX_TCPWM1_GRP0_CNT14_CNT
PERI_MS_PPU_FX_TCPWM1_GRP0_CNT15_CNT
PERI_MS_PPU_FX_TCPWM1_GRP0_CNT16_CNT
PERI_MS_PPU_FX_TCPWM1_GRP0_CNT17_CNT
PERI_MS_PPU_FX_TCPWM1_GRP0_CNT18_CNT
PERI_MS_PPU_FX_TCPWM1_GRP0_CNT19_CNT
PERI_MS_PPU_FX_TCPWM1_GRP0_CNT20_CNT
PERI_MS_PPU_FX_TCPWM1_GRP0_CNT21_CNT
PERI_MS_PPU_FX_TCPWM1_GRP0_CNT22_CNT
PERI_MS_PPU_FX_TCPWM1_GRP0_CNT23_CNT
PERI_MS_PPU_FX_TCPWM1_GRP0_CNT24_CNT
PERI_MS_PPU_FX_TCPWM1_GRP0_CNT25_CNT
PERI_MS_PPU_FX_TCPWM1_GRP0_CNT26_CNT
PERI_MS_PPU_FX_TCPWM1_GRP0_CNT27_CNT
PERI_MS_PPU_FX_TCPWM1_GRP0_CNT28_CNT
PERI_MS_PPU_FX_TCPWM1_GRP0_CNT29_CNT
PERI_MS_PPU_FX_TCPWM1_GRP0_CNT30_CNT
PERI_MS_PPU_FX_TCPWM1_GRP0_CNT31_CNT
PERI_MS_PPU_FX_TCPWM1_GRP0_CNT32_CNT
PERI_MS_PPU_FX_TCPWM1_GRP0_CNT33_CNT
PERI_MS_PPU_FX_TCPWM1_GRP0_CNT34_CNT
PERI_MS_PPU_FX_TCPWM1_GRP0_CNT35_CNT
PERI_MS_PPU_FX_TCPWM1_GRP0_CNT36_CNT
PERI_MS_PPU_FX_TCPWM1_GRP0_CNT37_CNT
PERI_MS_PPU_FX_TCPWM1_GRP0_CNT38_CNT
PERI_MS_PPU_FX_TCPWM1_GRP0_CNT39_CNT
PERI_MS_PPU_FX_TCPWM1_GRP0_CNT40_CNT
PERI_MS_PPU_FX_TCPWM1_GRP0_CNT41_CNT
PERI_MS_PPU_FX_TCPWM1_GRP0_CNT42_CNT
PERI_MS_PPU_FX_TCPWM1_GRP0_CNT43_CNT
PERI_MS_PPU_FX_TCPWM1_GRP0_CNT44_CNT
PERI_MS_PPU_FX_TCPWM1_GRP0_CNT45_CNT
PERI_MS_PPU_FX_TCPWM1_GRP0_CNT46_CNT
PERI_MS_PPU_FX_TCPWM1_GRP0_CNT47_CNT
PERI_MS_PPU_FX_TCPWM1_GRP0_CNT48_CNT
PERI_MS_PPU_FX_TCPWM1_GRP0_CNT49_CNT
0x40580280
0x40580300
0x40580380
0x40580400
0x40580480
0x40580500
0x40580580
0x40580600
0x40580680
0x40580700
0x40580780
0x40580800
0x40580880
0x40580900
0x40580980
0x40580A00
0x40580A80
0x40580B00
0x40580B80
0x40580C00
0x40580C80
0x40580D00
0x40580D80
0x40580E00
0x40580E80
0x40580F00
0x40580F80
0x40581000
0x40581080
0x40581100
0x40581180
0x40581200
0x40581280
0x40581300
0x40581380
0x40581400
0x40581480
0x40581500
0x40581580
0x40581600
0x40581680
0x40581700
0x40581780
0x40581800
0x40581880
0x00000080 TCPWM1 Group #0, Counter #5
0x00000080 TCPWM1 Group #0, Counter #6
0x00000080 TCPWM1 Group #0, Counter #7
0x00000080 TCPWM1 Group #0, Counter #8
0x00000080 TCPWM1 Group #0, Counter #9
0x00000080 TCPWM1 Group #0, Counter #10
0x00000080 TCPWM1 Group #0, Counter #11
0x00000080 TCPWM1 Group #0, Counter #12
0x00000080 TCPWM1 Group #0, Counter #13
0x00000080 TCPWM1 Group #0, Counter #14
0x00000080 TCPWM1 Group #0, Counter #15
0x00000080 TCPWM1 Group #0, Counter #16
0x00000080 TCPWM1 Group #0, Counter #17
0x00000080 TCPWM1 Group #0, Counter #18
0x00000080 TCPWM1 Group #0, Counter #19
0x00000080 TCPWM1 Group #0, Counter #20
0x00000080 TCPWM1 Group #0, Counter #21
0x00000080 TCPWM1 Group #0, Counter #22
0x00000080 TCPWM1 Group #0, Counter #23
0x00000080 TCPWM1 Group #0, Counter #24
0x00000080 TCPWM1 Group #0, Counter #25
0x00000080 TCPWM1 Group #0, Counter #26
0x00000080 TCPWM1 Group #0, Counter #27
0x00000080 TCPWM1 Group #0, Counter #28
0x00000080 TCPWM1 Group #0, Counter #29
0x00000080 TCPWM1 Group #0, Counter #30
0x00000080 TCPWM1 Group #0, Counter #31
0x00000080 TCPWM1 Group #0, Counter #32
0x00000080 TCPWM1 Group #0, Counter #33
0x00000080 TCPWM1 Group #0, Counter #34
0x00000080 TCPWM1 Group #0, Counter #35
0x00000080 TCPWM1 Group #0, Counter #36
0x00000080 TCPWM1 Group #0, Counter #37
0x00000080 TCPWM1 Group #0, Counter #38
0x00000080 TCPWM1 Group #0, Counter #39
0x00000080 TCPWM1 Group #0, Counter #40
0x00000080 TCPWM1 Group #0, Counter #41
0x00000080 TCPWM1 Group #0, Counter #42
0x00000080 TCPWM1 Group #0, Counter #43
0x00000080 TCPWM1 Group #0, Counter #44
0x00000080 TCPWM1 Group #0, Counter #45
0x00000080 TCPWM1 Group #0, Counter #46
0x00000080 TCPWM1 Group #0, Counter #47
0x00000080 TCPWM1 Group #0, Counter #48
0x00000080 TCPWM1 Group #0, Counter #49
Datasheet
100
002-21617 Rev. *K
2022-10-10
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Peripheral protection unit fixed structure pairs
Table 23-1
PPU fixed structure pairs (continued)
Pair No.
PPU Fixed Structure Pair
Address
Size
Description
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
PERI_MS_PPU_FX_TCPWM1_GRP0_CNT50_CNT
PERI_MS_PPU_FX_TCPWM1_GRP0_CNT51_CNT
PERI_MS_PPU_FX_TCPWM1_GRP0_CNT52_CNT
PERI_MS_PPU_FX_TCPWM1_GRP0_CNT53_CNT
PERI_MS_PPU_FX_TCPWM1_GRP0_CNT54_CNT
PERI_MS_PPU_FX_TCPWM1_GRP0_CNT55_CNT
PERI_MS_PPU_FX_TCPWM1_GRP0_CNT56_CNT
PERI_MS_PPU_FX_TCPWM1_GRP0_CNT57_CNT
PERI_MS_PPU_FX_TCPWM1_GRP0_CNT58_CNT
PERI_MS_PPU_FX_TCPWM1_GRP0_CNT59_CNT
PERI_MS_PPU_FX_TCPWM1_GRP0_CNT60_CNT
PERI_MS_PPU_FX_TCPWM1_GRP0_CNT61_CNT
PERI_MS_PPU_FX_TCPWM1_GRP0_CNT62_CNT
PERI_MS_PPU_FX_TCPWM1_GRP0_CNT63_CNT
PERI_MS_PPU_FX_TCPWM1_GRP0_CNT64_CNT
PERI_MS_PPU_FX_TCPWM1_GRP0_CNT65_CNT
PERI_MS_PPU_FX_TCPWM1_GRP0_CNT66_CNT
PERI_MS_PPU_FX_TCPWM1_GRP0_CNT67_CNT
PERI_MS_PPU_FX_TCPWM1_GRP0_CNT68_CNT
PERI_MS_PPU_FX_TCPWM1_GRP0_CNT69_CNT
PERI_MS_PPU_FX_TCPWM1_GRP0_CNT70_CNT
PERI_MS_PPU_FX_TCPWM1_GRP0_CNT71_CNT
PERI_MS_PPU_FX_TCPWM1_GRP0_CNT72_CNT
PERI_MS_PPU_FX_TCPWM1_GRP0_CNT73_CNT
PERI_MS_PPU_FX_TCPWM1_GRP0_CNT74_CNT
PERI_MS_PPU_FX_TCPWM1_GRP0_CNT75_CNT
PERI_MS_PPU_FX_TCPWM1_GRP0_CNT76_CNT
PERI_MS_PPU_FX_TCPWM1_GRP0_CNT77_CNT
PERI_MS_PPU_FX_TCPWM1_GRP0_CNT78_CNT
PERI_MS_PPU_FX_TCPWM1_GRP0_CNT79_CNT
PERI_MS_PPU_FX_TCPWM1_GRP0_CNT80_CNT
PERI_MS_PPU_FX_TCPWM1_GRP0_CNT81_CNT
PERI_MS_PPU_FX_TCPWM1_GRP0_CNT82_CNT
PERI_MS_PPU_FX_TCPWM1_GRP0_CNT83_CNT
PERI_MS_PPU_FX_TCPWM1_GRP1_CNT0_CNT
PERI_MS_PPU_FX_TCPWM1_GRP1_CNT1_CNT
PERI_MS_PPU_FX_TCPWM1_GRP1_CNT2_CNT
PERI_MS_PPU_FX_TCPWM1_GRP1_CNT3_CNT
PERI_MS_PPU_FX_TCPWM1_GRP1_CNT4_CNT
PERI_MS_PPU_FX_TCPWM1_GRP1_CNT5_CNT
PERI_MS_PPU_FX_TCPWM1_GRP1_CNT6_CNT
PERI_MS_PPU_FX_TCPWM1_GRP1_CNT7_CNT
PERI_MS_PPU_FX_TCPWM1_GRP1_CNT8_CNT
PERI_MS_PPU_FX_TCPWM1_GRP1_CNT9_CNT
PERI_MS_PPU_FX_TCPWM1_GRP1_CNT10_CNT
0x40581900
0x40581980
0x40581A00
0x40581A80
0x40581B00
0x40581B80
0x40581C00
0x40581C80
0x40581D00
0x40581D80
0x40581E00
0x40581E80
0x40581F00
0x40581F80
0x40582000
0x40582080
0x40582100
0x40582180
0x40582200
0x40582280
0x40582300
0x40582380
0x40582400
0x40582480
0x40582500
0x40582580
0x40582600
0x40582680
0x40582700
0x40582780
0x40582800
0x40582880
0x40582900
0x40582980
0x40588000
0x40588080
0x40588100
0x40588180
0x40588200
0x40588280
0x40588300
0x40588380
0x40588400
0x40588480
0x40588500
0x00000080 TCPWM1 Group #0, Counter #50
0x00000080 TCPWM1 Group #0, Counter #51
0x00000080 TCPWM1 Group #0, Counter #52
0x00000080 TCPWM1 Group #0, Counter #53
0x00000080 TCPWM1 Group #0, Counter #54
0x00000080 TCPWM1 Group #0, Counter #55
0x00000080 TCPWM1 Group #0, Counter #56
0x00000080 TCPWM1 Group #0, Counter #57
0x00000080 TCPWM1 Group #0, Counter #58
0x00000080 TCPWM1 Group #0, Counter #59
0x00000080 TCPWM1 Group #0, Counter #60
0x00000080 TCPWM1 Group #0, Counter #61
0x00000080 TCPWM1 Group #0, Counter #62
0x00000080 TCPWM1 Group #0, Counter #63
0x00000080 TCPWM1 Group #0, Counter #64
0x00000080 TCPWM1 Group #0, Counter #65
0x00000080 TCPWM1 Group #0, Counter #66
0x00000080 TCPWM1 Group #0, Counter #67
0x00000080 TCPWM1 Group #0, Counter #68
0x00000080 TCPWM1 Group #0, Counter #69
0x00000080 TCPWM1 Group #0, Counter #70
0x00000080 TCPWM1 Group #0, Counter #71
0x00000080 TCPWM1 Group #0, Counter #72
0x00000080 TCPWM1 Group #0, Counter #73
0x00000080 TCPWM1 Group #0, Counter #74
0x00000080 TCPWM1 Group #0, Counter #75
0x00000080 TCPWM1 Group #0, Counter #76
0x00000080 TCPWM1 Group #0, Counter #77
0x00000080 TCPWM1 Group #0, Counter #78
0x00000080 TCPWM1 Group #0, Counter #79
0x00000080 TCPWM1 Group #0, Counter #80
0x00000080 TCPWM1 Group #0, Counter #81
0x00000080 TCPWM1 Group #0, Counter #82
0x00000080 TCPWM1 Group #0, Counter #83
0x00000080 TCPWM1 Group #1, Counter #0
0x00000080 TCPWM1 Group #1, Counter #1
0x00000080 TCPWM1 Group #1, Counter #2
0x00000080 TCPWM1 Group #1, Counter #3
0x00000080 TCPWM1 Group #1, Counter #4
0x00000080 TCPWM1 Group #1, Counter #5
0x00000080 TCPWM1 Group #1, Counter #6
0x00000080 TCPWM1 Group #1, Counter #7
0x00000080 TCPWM1 Group #1, Counter #8
0x00000080 TCPWM1 Group #1, Counter #9
0x00000080 TCPWM1 Group #1, Counter #10
Datasheet
101
002-21617 Rev. *K
2022-10-10
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Peripheral protection unit fixed structure pairs
Table 23-1
PPU fixed structure pairs (continued)
Pair No.
PPU Fixed Structure Pair
Address
Size
Description
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
PERI_MS_PPU_FX_TCPWM1_GRP1_CNT11_CNT
PERI_MS_PPU_FX_TCPWM1_GRP2_CNT0_CNT
PERI_MS_PPU_FX_TCPWM1_GRP2_CNT1_CNT
PERI_MS_PPU_FX_TCPWM1_GRP2_CNT2_CNT
PERI_MS_PPU_FX_TCPWM1_GRP2_CNT3_CNT
PERI_MS_PPU_FX_TCPWM1_GRP2_CNT4_CNT
PERI_MS_PPU_FX_TCPWM1_GRP2_CNT5_CNT
PERI_MS_PPU_FX_TCPWM1_GRP2_CNT6_CNT
PERI_MS_PPU_FX_TCPWM1_GRP2_CNT7_CNT
PERI_MS_PPU_FX_TCPWM1_GRP2_CNT8_CNT
PERI_MS_PPU_FX_TCPWM1_GRP2_CNT9_CNT
PERI_MS_PPU_FX_TCPWM1_GRP2_CNT10_CNT
PERI_MS_PPU_FX_TCPWM1_GRP2_CNT11_CNT
PERI_MS_PPU_FX_TCPWM1_GRP2_CNT12_CNT
PERI_MS_PPU_FX_EVTGEN0
0x40588580
0x40590000
0x40590080
0x40590100
0x40590180
0x40590200
0x40590280
0x40590300
0x40590380
0x40590400
0x40590480
0x40590500
0x40590580
0x40590600
0x403F0000
0x40420000
0x40460000
0x40480000
0x40490000
0x40500000
0x40508000
0x40508100
0x40508200
0x40508300
0x40508400
0x40508500
0x40508600
0x40508700
0x40508800
0x40508900
0x40508A00
0x40508B00
0x40508C00
0x40508D00
0x40508E00
0x40508F00
0x40509000
0x40509100
0x40509200
0x40509300
0x40520000
0x40520200
0x40520400
0x40520600
0x40520800
0x00000080 TCPWM1 Group #1, Counter #11
0x00000080 TCPWM1 Group #2, Counter #0
0x00000080 TCPWM1 Group #2, Counter #1
0x00000080 TCPWM1 Group #2, Counter #2
0x00000080 TCPWM1 Group #2, Counter #3
0x00000080 TCPWM1 Group #2, Counter #4
0x00000080 TCPWM1 Group #2, Counter #5
0x00000080 TCPWM1 Group #2, Counter #6
0x00000080 TCPWM1 Group #2, Counter #7
0x00000080 TCPWM1 Group #2, Counter #8
0x00000080 TCPWM1 Group #2, Counter #9
0x00000080 TCPWM1 Group #2, Counter #10
0x00000080 TCPWM1 Group #2, Counter #11
0x00000080 TCPWM1 Group #2, Counter #12
0x00001000 Event generator #0
0x00010000 Serial Memory Interface #0
0x00010000 Secure Digital High Capacity #0
0x00010000 Ethernet0
PERI_MS_PPU_FX_SMIF0
PERI_MS_PPU_FX_SDHC0
PERI_MS_PPU_FX_ETH0
PERI_MS_PPU_FX_ETH1
0x00010000 Ethernet1
PERI_MS_PPU_FX_LIN0_MAIN
0x00000008 LIN0, main
PERI_MS_PPU_FX_LIN0_CH0_CH
0x00000100 LIN0, Channel #0
PERI_MS_PPU_FX_LIN0_CH1_CH
0x00000100 LIN0, Channel #1
PERI_MS_PPU_FX_LIN0_CH2_CH
0x00000100 LIN0, Channel #2
PERI_MS_PPU_FX_LIN0_CH3_CH
0x00000100 LIN0, Channel #3
PERI_MS_PPU_FX_LIN0_CH4_CH
0x00000100 LIN0, Channel #4
PERI_MS_PPU_FX_LIN0_CH5_CH
0x00000100 LIN0, Channel #5
PERI_MS_PPU_FX_LIN0_CH6_CH
0x00000100 LIN0, Channel #6
PERI_MS_PPU_FX_LIN0_CH7_CH
0x00000100 LIN0, Channel #7
PERI_MS_PPU_FX_LIN0_CH8_CH
0x00000100 LIN0, Channel #8
PERI_MS_PPU_FX_LIN0_CH9_CH
0x00000100 LIN0, Channel #9
PERI_MS_PPU_FX_LIN0_CH10_CH
PERI_MS_PPU_FX_LIN0_CH11_CH
PERI_MS_PPU_FX_LIN0_CH12_CH
PERI_MS_PPU_FX_LIN0_CH13_CH
PERI_MS_PPU_FX_LIN0_CH14_CH
PERI_MS_PPU_FX_LIN0_CH15_CH
PERI_MS_PPU_FX_LIN0_CH16_CH
PERI_MS_PPU_FX_LIN0_CH17_CH
PERI_MS_PPU_FX_LIN0_CH18_CH
PERI_MS_PPU_FX_LIN0_CH19_CH
PERI_MS_PPU_FX_CANFD0_CH0_CH
PERI_MS_PPU_FX_CANFD0_CH1_CH
PERI_MS_PPU_FX_CANFD0_CH2_CH
PERI_MS_PPU_FX_CANFD0_CH3_CH
PERI_MS_PPU_FX_CANFD0_CH4_CH
0x00000100 LIN0, Channel #10
0x00000100 LIN0, Channel #11
0x00000100 LIN0, Channel #12
0x00000100 LIN0, Channel #13
0x00000100 LIN0, Channel #14
0x00000100 LIN0, Channel #15
0x00000100 LIN0, Channel #16
0x00000100 LIN0, Channel #17
0x00000100 LIN0, Channel #18
0x00000100 LIN0, Channel #19
0x00000200 CAN0, Channel #0
0x00000200 CAN0, Channel #1
0x00000200 CAN0, Channel #2
0x00000200 CAN0, Channel #3
0x00000200 CAN0, Channel #4
Datasheet
102
002-21617 Rev. *K
2022-10-10
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Peripheral protection unit fixed structure pairs
Table 23-1
PPU fixed structure pairs (continued)
Pair No.
PPU Fixed Structure Pair
Address
Size
Description
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
PERI_MS_PPU_FX_CANFD1_CH0_CH
PERI_MS_PPU_FX_CANFD1_CH1_CH
0x40540000
0x40540200
0x40540400
0x40540600
0x40540800
0x40521000
0x40541000
0x40530000
0x40550000
0x40560000
0x40600000
0x40610000
0x40620000
0x40630000
0x40640000
0x40650000
0x40660000
0x40670000
0x40680000
0x40690000
0x406A0000
0x40800000
0x40801000
0x40802000
0x40900000
0x40901000
0x40902000
0x40900800
0x40900840
0x40900880
0x409008C0
0x40900900
0x40900940
0x40900980
0x409009C0
0x40900A00
0x40900A40
0x40900A80
0x40900AC0
0x40900B00
0x40900B40
0x40900B80
0x40900BC0
0x40900C00
0x40900C40
0x00000200 CAN1, Channel #0
0x00000200 CAN1, Channel #1
0x00000200 CAN1, Channel #2
0x00000200 CAN1, Channel #3
0x00000200 CAN1, Channel #4
0x00000100 CAN0 main
0x00000100 CAN1 main
0x00010000 CAN0 buffer
0x00010000 CAN1 buffer
0x00001000 FlexRay Interface #0
0x00010000 SCB0
PERI_MS_PPU_FX_CANFD1_CH2_CH
PERI_MS_PPU_FX_CANFD1_CH3_CH
PERI_MS_PPU_FX_CANFD1_CH4_CH
PERI_MS_PPU_FX_CANFD0_MAIN
PERI_MS_PPU_FX_CANFD1_MAIN
PERI_MS_PPU_FX_CANFD0_BUF
PERI_MS_PPU_FX_CANFD1_BUF
PERI_MS_PPU_FX_FLEXRAY0
PERI_MS_PPU_FX_SCB0
PERI_MS_PPU_FX_SCB1
0x00010000 SCB1
PERI_MS_PPU_FX_SCB2
0x00010000 SCB2
PERI_MS_PPU_FX_SCB3
0x00010000 SCB3
PERI_MS_PPU_FX_SCB4
0x00010000 SCB4
PERI_MS_PPU_FX_SCB5
0x00010000 SCB5
PERI_MS_PPU_FX_SCB6
0x00010000 SCB6
PERI_MS_PPU_FX_SCB7
0x00010000 SCB7
PERI_MS_PPU_FX_SCB8
0x00010000 SCB8
PERI_MS_PPU_FX_SCB9
0x00010000 SCB9
PERI_MS_PPU_FX_SCB10
0x00010000 SCB10
PERI_MS_PPU_FX_I2S0
0x00001000 AUDIOSS I2S0
0x00001000 AUDIOSS I2S1
0x00001000 AUDIOSS I2S2
0x00000400 PASS SAR0
PERI_MS_PPU_FX_I2S1
PERI_MS_PPU_FX_I2S2
PERI_MS_PPU_FX_PASS0_SAR0_SAR
PERI_MS_PPU_FX_PASS0_SAR1_SAR
PERI_MS_PPU_FX_PASS0_SAR2_SAR
PERI_MS_PPU_FX_PASS0_SAR0_CH0_CH
PERI_MS_PPU_FX_PASS0_SAR0_CH1_CH
PERI_MS_PPU_FX_PASS0_SAR0_CH2_CH
PERI_MS_PPU_FX_PASS0_SAR0_CH3_CH
PERI_MS_PPU_FX_PASS0_SAR0_CH4_CH
PERI_MS_PPU_FX_PASS0_SAR0_CH5_CH
PERI_MS_PPU_FX_PASS0_SAR0_CH6_CH
PERI_MS_PPU_FX_PASS0_SAR0_CH7_CH
PERI_MS_PPU_FX_PASS0_SAR0_CH8_CH
PERI_MS_PPU_FX_PASS0_SAR0_CH9_CH
PERI_MS_PPU_FX_PASS0_SAR0_CH10_CH
PERI_MS_PPU_FX_PASS0_SAR0_CH11_CH
PERI_MS_PPU_FX_PASS0_SAR0_CH12_CH
PERI_MS_PPU_FX_PASS0_SAR0_CH13_CH
PERI_MS_PPU_FX_PASS0_SAR0_CH14_CH
PERI_MS_PPU_FX_PASS0_SAR0_CH15_CH
PERI_MS_PPU_FX_PASS0_SAR0_CH16_CH
PERI_MS_PPU_FX_PASS0_SAR0_CH17_CH
0x00000400 PASS SAR1
0x00000400 PASS SAR2
0x00000040 SAR0, Channel #0
0x00000040 SAR0, Channel #1
0x00000040 SAR0, Channel #2
0x00000040 SAR0, Channel #3
0x00000040 SAR0, Channel #4
0x00000040 SAR0, Channel #5
0x00000040 SAR0, Channel #6
0x00000040 SAR0, Channel #7
0x00000040 SAR0, Channel #8
0x00000040 SAR0, Channel #9
0x00000040 SAR0, Channel #10
0x00000040 SAR0, Channel #11
0x00000040 SAR0, Channel #12
0x00000040 SAR0, Channel #13
0x00000040 SAR0, Channel #14
0x00000040 SAR0, Channel #15
0x00000040 SAR0, Channel #16
0x00000040 SAR0, Channel #17
Datasheet
103
002-21617 Rev. *K
2022-10-10
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Peripheral protection unit fixed structure pairs
Table 23-1
PPU fixed structure pairs (continued)
Pair No.
PPU Fixed Structure Pair
Address
Size
Description
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
PERI_MS_PPU_FX_PASS0_SAR0_CH18_CH
PERI_MS_PPU_FX_PASS0_SAR0_CH19_CH
PERI_MS_PPU_FX_PASS0_SAR0_CH20_CH
PERI_MS_PPU_FX_PASS0_SAR0_CH21_CH
PERI_MS_PPU_FX_PASS0_SAR0_CH22_CH
PERI_MS_PPU_FX_PASS0_SAR0_CH23_CH
PERI_MS_PPU_FX_PASS0_SAR0_CH24_CH
PERI_MS_PPU_FX_PASS0_SAR0_CH25_CH
PERI_MS_PPU_FX_PASS0_SAR0_CH26_CH
PERI_MS_PPU_FX_PASS0_SAR0_CH27_CH
PERI_MS_PPU_FX_PASS0_SAR0_CH28_CH
PERI_MS_PPU_FX_PASS0_SAR0_CH29_CH
PERI_MS_PPU_FX_PASS0_SAR0_CH30_CH
PERI_MS_PPU_FX_PASS0_SAR0_CH31_CH
PERI_MS_PPU_FX_PASS0_SAR1_CH0_CH
PERI_MS_PPU_FX_PASS0_SAR1_CH1_CH
PERI_MS_PPU_FX_PASS0_SAR1_CH2_CH
PERI_MS_PPU_FX_PASS0_SAR1_CH3_CH
PERI_MS_PPU_FX_PASS0_SAR1_CH4_CH
PERI_MS_PPU_FX_PASS0_SAR1_CH5_CH
PERI_MS_PPU_FX_PASS0_SAR1_CH6_CH
PERI_MS_PPU_FX_PASS0_SAR1_CH7_CH
PERI_MS_PPU_FX_PASS0_SAR1_CH8_CH
PERI_MS_PPU_FX_PASS0_SAR1_CH9_CH
PERI_MS_PPU_FX_PASS0_SAR1_CH10_CH
PERI_MS_PPU_FX_PASS0_SAR1_CH11_CH
PERI_MS_PPU_FX_PASS0_SAR1_CH12_CH
PERI_MS_PPU_FX_PASS0_SAR1_CH13_CH
PERI_MS_PPU_FX_PASS0_SAR1_CH14_CH
PERI_MS_PPU_FX_PASS0_SAR1_CH15_CH
PERI_MS_PPU_FX_PASS0_SAR1_CH16_CH
PERI_MS_PPU_FX_PASS0_SAR1_CH17_CH
PERI_MS_PPU_FX_PASS0_SAR1_CH18_CH
PERI_MS_PPU_FX_PASS0_SAR1_CH19_CH
PERI_MS_PPU_FX_PASS0_SAR1_CH20_CH
PERI_MS_PPU_FX_PASS0_SAR1_CH21_CH
PERI_MS_PPU_FX_PASS0_SAR1_CH22_CH
PERI_MS_PPU_FX_PASS0_SAR1_CH23_CH
PERI_MS_PPU_FX_PASS0_SAR1_CH24_CH
PERI_MS_PPU_FX_PASS0_SAR1_CH25_CH
PERI_MS_PPU_FX_PASS0_SAR1_CH26_CH
PERI_MS_PPU_FX_PASS0_SAR1_CH27_CH
PERI_MS_PPU_FX_PASS0_SAR1_CH28_CH
PERI_MS_PPU_FX_PASS0_SAR1_CH29_CH
PERI_MS_PPU_FX_PASS0_SAR1_CH30_CH
0x40900C80
0x40900CC0
0x40900D00
0x40900D40
0x40900D80
0x40900DC0
0x40900E00
0x40900E40
0x40900E80
0x40900EC0
0x40900F00
0x40900F40
0x40900F80
0x40900FC0
0x40901800
0x40901840
0x40901880
0x409018C0
0x40901900
0x40901940
0x40901980
0x409019C0
0x40901A00
0x40901A40
0x40901A80
0x40901AC0
0x40901B00
0x40901B40
0x40901B80
0x40901BC0
0x40901C00
0x40901C40
0x40901C80
0x40901CC0
0x40901D00
0x40901D40
0x40901D80
0x40901DC0
0x40901E00
0x40901E40
0x40901E80
0x40901EC0
0x40901F00
0x40901F40
0x40901F80
0x00000040 SAR0, Channel #18
0x00000040 SAR0, Channel #19
0x00000040 SAR0, Channel #20
0x00000040 SAR0, Channel #21
0x00000040 SAR0, Channel #22
0x00000040 SAR0, Channel #23
0x00000040 SAR0, Channel #24
0x00000040 SAR0, Channel #25
0x00000040 SAR0, Channel #26
0x00000040 SAR0, Channel #27
0x00000040 SAR0, Channel #28
0x00000040 SAR0, Channel #29
0x00000040 SAR0, Channel #30
0x00000040 SAR0, Channel #31
0x00000040 SAR1, Channel #0
0x00000040 SAR1, Channel #1
0x00000040 SAR1, Channel #2
0x00000040 SAR1, Channel #3
0x00000040 SAR1, Channel #4
0x00000040 SAR1, Channel #5
0x00000040 SAR1, Channel #6
0x00000040 SAR1, Channel #7
0x00000040 SAR1, Channel #8
0x00000040 SAR1, Channel #9
0x00000040 SAR1, Channel #10
0x00000040 SAR1, Channel #11
0x00000040 SAR1, Channel #12
0x00000040 SAR1, Channel #13
0x00000040 SAR1, Channel #14
0x00000040 SAR1, Channel #15
0x00000040 SAR1, Channel #16
0x00000040 SAR1, Channel #17
0x00000040 SAR1, Channel #18
0x00000040 SAR1, Channel #19
0x00000040 SAR1, Channel #20
0x00000040 SAR1, Channel #21
0x00000040 SAR1, Channel #22
0x00000040 SAR1, Channel #23
0x00000040 SAR1, Channel #24
0x00000040 SAR1, Channel #25
0x00000040 SAR1, Channel #26
0x00000040 SAR1, Channel #27
0x00000040 SAR1, Channel #28
0x00000040 SAR1, Channel #29
0x00000040 SAR1, Channel #30
Datasheet
104
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Peripheral protection unit fixed structure pairs
Table 23-1
PPU fixed structure pairs (continued)
Pair No.
PPU Fixed Structure Pair
Address
Size
Description
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
PERI_MS_PPU_FX_PASS0_SAR1_CH31_CH
PERI_MS_PPU_FX_PASS0_SAR2_CH0_CH
PERI_MS_PPU_FX_PASS0_SAR2_CH1_CH
PERI_MS_PPU_FX_PASS0_SAR2_CH2_CH
PERI_MS_PPU_FX_PASS0_SAR2_CH3_CH
PERI_MS_PPU_FX_PASS0_SAR2_CH4_CH
PERI_MS_PPU_FX_PASS0_SAR2_CH5_CH
PERI_MS_PPU_FX_PASS0_SAR2_CH6_CH
PERI_MS_PPU_FX_PASS0_SAR2_CH7_CH
PERI_MS_PPU_FX_PASS0_SAR2_CH8_CH
PERI_MS_PPU_FX_PASS0_SAR2_CH9_CH
PERI_MS_PPU_FX_PASS0_SAR2_CH10_CH
PERI_MS_PPU_FX_PASS0_SAR2_CH11_CH
PERI_MS_PPU_FX_PASS0_SAR2_CH12_CH
PERI_MS_PPU_FX_PASS0_SAR2_CH13_CH
PERI_MS_PPU_FX_PASS0_SAR2_CH14_CH
PERI_MS_PPU_FX_PASS0_SAR2_CH15_CH
PERI_MS_PPU_FX_PASS0_SAR2_CH16_CH
PERI_MS_PPU_FX_PASS0_SAR2_CH17_CH
PERI_MS_PPU_FX_PASS0_SAR2_CH18_CH
PERI_MS_PPU_FX_PASS0_SAR2_CH19_CH
PERI_MS_PPU_FX_PASS0_SAR2_CH20_CH
PERI_MS_PPU_FX_PASS0_SAR2_CH21_CH
PERI_MS_PPU_FX_PASS0_SAR2_CH22_CH
PERI_MS_PPU_FX_PASS0_SAR2_CH23_CH
PERI_MS_PPU_FX_PASS0_SAR2_CH24_CH
PERI_MS_PPU_FX_PASS0_SAR2_CH25_CH
PERI_MS_PPU_FX_PASS0_SAR2_CH26_CH
PERI_MS_PPU_FX_PASS0_SAR2_CH27_CH
PERI_MS_PPU_FX_PASS0_SAR2_CH28_CH
PERI_MS_PPU_FX_PASS0_SAR2_CH29_CH
PERI_MS_PPU_FX_PASS0_SAR2_CH30_CH
PERI_MS_PPU_FX_PASS0_SAR2_CH31_CH
PERI_MS_PPU_FX_PASS0_TOP
0x40901FC0
0x40902800
0x40902840
0x40902880
0x409028C0
0x40902900
0x40902940
0x40902980
0x409029C0
0x40902A00
0x40902A40
0x40902A80
0x40902AC0
0x40902B00
0x40902B40
0x40902B80
0x40902BC0
0x40902C00
0x40902C40
0x40902C80
0x40902CC0
0x40902D00
0x40902D40
0x40902D80
0x40902DC0
0x40902E00
0x40902E40
0x40902E80
0x40902EC0
0x40902F00
0x40902F40
0x40902F80
0x40902FC0
0x409F0000
0x00000040 SAR1, Channel #31
0x00000040 SAR2, Channel #0
0x00000040 SAR2, Channel #1
0x00000040 SAR2, Channel #2
0x00000040 SAR2, Channel #3
0x00000040 SAR2, Channel #4
0x00000040 SAR2, Channel #5
0x00000040 SAR2, Channel #6
0x00000040 SAR2, Channel #7
0x00000040 SAR2, Channel #8
0x00000040 SAR2, Channel #9
0x00000040 SAR2, Channel #10
0x00000040 SAR2, Channel #11
0x00000040 SAR2, Channel #12
0x00000040 SAR2, Channel #13
0x00000040 SAR2, Channel #14
0x00000040 SAR2, Channel #15
0x00000040 SAR2, Channel #16
0x00000040 SAR2, Channel #17
0x00000040 SAR2, Channel #18
0x00000040 SAR2, Channel #19
0x00000040 SAR2, Channel #20
0x00000040 SAR2, Channel #21
0x00000040 SAR2, Channel #22
0x00000040 SAR2, Channel #23
0x00000040 SAR2, Channel #24
0x00000040 SAR2, Channel #25
0x00000040 SAR2, Channel #26
0x00000040 SAR2, Channel #27
0x00000040 SAR2, Channel #28
0x00000040 SAR2, Channel #29
0x00000040 SAR2, Channel #30
0x00000040 SAR2, Channel #31
0x00001000 PASS0 SAR main
Datasheet
105
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Bus masters
24
Bus masters
The Arbiter (part of flash controller) performs priority-based arbitration based on the master identifier. Each bus
master has a dedicated 4-bit master identifier. This master identifier is used for bus arbitration and IPC function-
ality.
Table 24-1
ID No.
Bus masters for access and protection control
Master ID
Description
0
1
CPUSS_MS_ID_CM0
Master ID for CM0+
CPUSS_MS_ID_CRYPTO
CPUSS_MS_ID_DW0
CPUSS_MS_ID_DW1
CPUSS_MS_ID_DMAC
CPUSS_MS_ID_SLOW0
CPUSS_MS_ID_FAST0
CPUSS_MS_ID_FAST1
CPUSS_MS_ID_CM7_1
CPUSS_MS_ID_CM7_0
CPUSS_MS_ID_TC
Master ID for Crypto
Master ID for P-DMA0
Master ID for P-DMA1
2
3
4
Master ID for M-DMA0
5
Master ID for External AHB-Lite Master 0 (SDHC)
Master ID for External AXI Master 0 (ETH0)
Master ID for External AXI Master 1 (ETH1)
Master ID for CM7_1
9
10
13
14
15
Master ID for CM7_0
Master ID for DAP Tap Controller
Datasheet
106
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Miscellaneous configuration
25
Miscellaneous configuration
Table 25-1
Miscellaneous configuration for CYT4BF devices
Sl. No.
Configuration
Number/Instances
Description
Number of clock paths. One for each of FLL, PLL, Direct and CSV
Number of CLK_HFs present
0
1
SRSS_NUM_CLKPATH
7
8
SRSS_NUM_HFROOT
PERI_PC_NR
Number of protection contexts
2
8
Number of asynchronous PCLK groups
3
PERI_PERI_PCLK_PCLK_GROUP_NR
2
Group 0, Number of divide-by-8 clock dividers
Group 0, Number of divide-by-16 clock dividers
Group 0, Number of divide-by-24.5 clock dividers
Group 0, Number of programmable clocks [1, 256]
Group 1, Number of divide-by-8 clock dividers
Group 1, Number of divide-by-16 clock dividers
Group 1, Number of divide-by-24.5 clock dividers
Group 1, Number of programmable clocks [1, 256]
Number of MPU regions in CM0+
4
PERI_PERI_PCLK_PCLK_GROUP_NR0_GR_DIV_8_VECT
PERI_PERI_PCLK_PCLK_GROUP_NR0_GR_DIV_16_VECT
PERI_PERI_PCLK_PCLK_GROUP_NR0_GR_DIV_24_5_VECT
PERI_PERI_PCLK_PCLK_GROUP_NR0_GR_CLOCK_VECT
PERI_PERI_PCLK_PCLK_GROUP_NR1_GR_DIV_8_VECT
PERI_PERI_PCLK_PCLK_GROUP_NR1_GR_DIV_16_VECT
PERI_PERI_PCLK_PCLK_GROUP_NR1_GR_DIV_24_5_VECT
PERI_PERI_PCLK_PCLK_GROUP_NR1_GR_CLOCK_VECT
CPUSS_CM0P_MPU_NR
4
5
3
6
1
7
15
19
20
21
154
8
8
9
10
11
12
CM7_0 Floating point unit configuration.
0 - No FPU
13
CPUSS_CM7_0_FPU_LVL
2
1 - Single precision FPU
2 - Single and Double precision FPU
Number of MPU regions in CM7_0
14
15
16
17
18
CPUSS_CM7_0_MPU_NR
16
16
16
16
16
CM7_0 Instruction cache (ICACHE) size in KB
CM7_0 Data cache size (DCACHE) in KB
CM7_0 Instruction TCM (ITCM) size in KB
CM7_0 Data TCM (DTCM) size in KB
CPUSS_CM7_0_ICACHE_SIZE
CPUSS_CM7_0_DCACHE_SIZE
CPUSS_CM7_0_ITCM_SIZE
CPUSS_CM7_0_DTCM_SIZE
CM7_1 Floating point unit configuration.
0 - No FPU
19
CPUSS_CM7_1_FPU_LVL
2
1 - Single precision FPU
2 - Single and Double precision FPU
Number of MPU regions in CM7_1
CM7_1 Instruction cache (ICACHE) size in KB
CM7_1 Data cache size (DCACHE) in KB
CM7_1 Instruction TCM (ITCM) size in KB
CM7_1 Data TCM (DTCM) size in KB
Number of P-DMA0 channels
20
21
22
23
24
25
26
27
CPUSS_CM7_1_MPU_NR
CPUSS_CM7_1_ICACHE_SIZE
CPUSS_CM7_1_DCACHE_SIZE
CPUSS_CM7_1_ITCM_SIZE
CPUSS_CM7_1_DTCM_SIZE
CPUSS_DW0_CH_NR
16
16
16
16
16
143
65
8
Number of P-DMA1 channels
CPUSS_DW1_CH_NR
Number of M-DMA0 controller channels
CPUSS_DMAC_CH_NR
Number of 32-bit words in the IP internal memory buffer (to allow for
a 256-B, 512-B, 1-KB, 2-KB, 4-KB, 8-KB, 16-KB, and 32-KB memory
buffer)
28
29
CPUSS_CRYPTO_BUFF_SIZE
CPUSS_FAULT_FAULT_NR
2048
4
Number of fault structures
Number of IPC structures
0 - Reserved for CM0+ access
1 - Reserved for CM7_0 access
2 - Reserved for CM7_1 access
3 - Reserved for DAP access
Remaining for user purposes
30
CPUSS_IPC_IPC_NR
8
Number of SMPU protection structures
31
32
CPUSS_PROT_SMPU_STRUCT_NR
SCB0_EZ_DATA_NR
16
Number of EZ memory bytes. This memory is used in EZ mode,
CMD_RESP mode and FIFO mode.
Note: Only SCB0 supports EZ mode
256
Number of input triggers per counter, routed to one counter
33
34
35
TCPWM0_TR_ONE_CNT_NR
TCPWM0_TR_ALL_CNT_NR
TCPWM0_GRP_NR
3
12
3
Number of input triggers routed to all counters, based on the pin
package
Number of TCPWM0 counter groups
Datasheet
107
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Miscellaneous configuration
Table 25-1
Miscellaneous configuration for CYT4BF devices (continued)
Sl. No.
Configuration
Number/Instances
Description
Number of counters per TCPWM0 Group #0
36
37
38
39
40
41
TCPWM0_GRP_NR0_GRP_GRP_CNT_NR
TCPWM0_GRP_NR0_CNT_GRP_CNT_WIDTH
TCPWM0_GRP_NR1_GRP_GRP_CNT_NR
TCPWM0_GRP_NR1_CNT_GRP_CNT_WIDTH
TCPWM0_GRP_NR2_GRP_GRP_CNT_NR
TCPWM0_GRP_NR2_CNT_GRP_CNT_WIDTH
3
Counter width in number of bits per TCPWM0
Group #0
16
3
Number of counters per TCPWM0 Group #1
Counter width in number of bits per TCPWM0
Group #1
16
3
Number of counters per TCPWM0 Group #2
Counter width in number of bits per TCPWM0
Group #2
32
Number of TCPWM1 counter groups
42
43
TCPWM1_GRP_NR
3
Number of counters per TCPWM1 Group #0
TCPWM1_GRP_NR0_GRP_GRP_CNT_NR
84
Counter width in number of bits per TCPWM1
Group #0
44
45
46
TCPWM1_GRP_NR0_CNT_GRP_CNT_WIDTH
TCPWM1_GRP_NR1_GRP_GRP_CNT_NR
TCPWM1_GRP_NR1_CNT_GRP_CNT_WIDTH
16
12
16
Number of counters per TCPWM1 Group #1
Counter width in number of bits per TCPWM1
Group #1
Number of counters per TCPWM1 Group #2
47
48
49
50
TCPWM1_GRP_NR2_GRP_GRP_CNT_NR
TCPWM1_GRP_NR2_CNT_GRP_CNT_WIDTH
CANFD0_MRAM_SIZE / CANFD1_MRAM_SIZE
EVTGEN_COMP_STRUCT_NR
13
32
40
16
Counter width in number of bits per TCPWM1 Group #2
Message RAM size in KB shared by all the channels
Number of Event Generator comparator structures
Datasheet
108
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Development support
26
Development support
CYT4BF has a rich set of documentation, programming tools, and online resources to assist during the devel-
opment process. Visit www.infineon.com to find out more.
26.1
Documentation
A suite of documentation supports CYT4BF to ensure that you can find answers to your questions quickly. This
section contains a list of some of the key documents.
26.1.1
Software User Guide
A step-by-step guide for using the sample driver library along with third-party IDEs such as IAR EWARM and GHS
Multi.
26.1.2
Technical Reference Manual
The Technical Reference Manual (TRM) contains all the technical detail needed to use a CYT4BF device, including
a complete description of all registers. The TRM is available in the documentation section at www.infineon.com.
26.2
Tools
CYT4BF is supported on third-party development tool ecosystems such as IAR and GHS. CYT4BF is also supported
by Cypress programming utilities for programming, erasing, or reading using Cypress’ MiniProg4 or Segger J-link.
More details are available in the documentation section at www.infineon.com.
Datasheet
109
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Electrical specifications
27
Electrical specifications
27.1
Absolute maximum ratings
Use of this device under conditions outside the Min and Max limits listed in Table 27-1 may cause permanent
damage to the device. Exposure to conditions within the limits of Table 27-1 but beyond those of normal
operation for extended periods of time may affect device reliability. The maximum storage temperature is 150 °C
in compliance with JEDEC Standard JESD22-A103, High Temperature Storage Life. When operated under condi-
tions within the limits of Table 27-1 but beyond those of normal operation, the device may not operate to speci-
fication.
Power considerations
The average chip-junction temperature, TJ, in °C, may be calculated using Equation 1:
TJ = TA + PD JA
Equation. 1
Where:
TA is the ambient temperature in °C.
JA is the package junction-to-ambient thermal resistance, in °C/W.
PD is the sum of PINT and PIO (PD = PINT + PIO).
θ
PINT is the chip internal power. (PINT = VDDD × IDD + VDDA × IA)
PIO represents the power dissipation on input and output pins; user determined.
For most applications, PIO < PINT and may be neglected.
On the other hand, PIO may be significant if the device is configured to continuously drive external modules
and/or memories.
WARNING:
• The recommended operating conditions are required to ensure the normal operation of the semiconductor
device. All of the device's electrical characteristics are guaranteed when the device is operated under these
conditions.
• Operation under any conditions other than those mentioned in the respective “Details/Conditions” may
adversely affect reliability of the device and can result in device failure.
• No guarantee is made with respect to any use, operating conditions, or combinations not represented in this
datasheet. If you want to operate the device under any condition other than those listed herein, contact the
sales representatives.
Datasheet
110
002-21617 Rev. *K
2022-10-10
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Electrical specifications
Table 27-1
Absolute maximum ratings
Details/
Conditions
Spec ID
Parameter
Description
Min
Typ
Max
Units
For ports 0, 1, 2, 3, 4, 5, 16, 17,
18, 19, 20, 21, 22, 23, 28, 29, 30,
31
[35]
SID10
V
V
power supply voltage
V
– 0.3
–
V
+ 6.0
V
DDD_ABS
DDD
SSD
SSD
[35]
[35]
[35]
[35]
SID10B
SID10C
SID10D
SID10E
SID11
V
V
V
V
V
V
V
V
V
V
power supply voltage
power supply voltage
power supply voltage
power supply voltage
V
V
– 0.3
– 0.3
–
–
–
–
–
V
V
+ 6.0
+ 6.0
V
V
V
V
V
For ports 6, 7, 8, 9, 32
For ports 10, 11, 12, 13, 14, 15
For ports 24, 25
DDIO_1_ABS
DDIO_2_ABS
DDIO_3_ABS
DDIO_4_ABS
DDA_ABS
DDIO_1
DDIO_2
DDIO_3
DDIO_4
SSD
SSD
SSD
SSD
V
V
– 0.3
– 0.3
V
V
+ 4.0
+ 4.0
SSIO_3
SSIO_4
SSIO_3
SSIO_4
For ports 26, 27, 33, 34
[35]
analog power supply voltage
V
V
– 0.3
V
V
V
+ 6.0
V
V
= V
DDIO_2 DDA
DDA
SSA
SSA
SSA
SSA
SSA
[35]
REFH
SID12
V
Analog reference voltage, HIGH
– 0.3
–
+ 6.0
V
REFH_ABS
(V
+ 0.3 V)
DDA
[35]
SID12A
SID13
V
V
Analog reference voltage, LOW
V
V
– 0.3
– 0.3
–
–
+ 0.3
V
V
REFL_ABS
CCD_ABS
SSA
[35]
V
Power supply voltage
V
+ 1.21
SSD
CCD
SSD
For ports 0, 1, 2, 3, 4, 5, 16, 17,
18, 19, 20, 21, 22, 23, 28, 29, 30,
31
[35]
SID15A
V
Input voltage
V
– 0.5
–
V + 0.5
DDD
V
I0_ABS
SSD
[35]
[35]
[35]
[35]
SID15B
SID15C
SID15D
SID15E
V
V
V
V
Input voltage
Input voltage
Input voltage
Input voltage
V
V
– 0.5
– 0.5
–
–
–
–
V
V
V
V
+ 0.5
+ 0.5
+ 0.5
+ 0.5
V
V
V
V
For ports 6, 7, 8, 9, 32
For ports 10, 11, 12, 13, 14, 15
For ports 24, 25
I1_ABS
I2_ABS
I3_ABS
I4_ABS
SSD
SSD
DDIO_1
DDIO_2
DDIO_3
DDIO_4
V
V
– 0.5
– 0.5
SSIO_3
SSIO_4
For ports 26, 27, 33, 34
For EXT_PS_CTL0 in external
PMIC/transistor mode,
EXT_PS_CTL1 in external
transistor mode.
[35]
SID15F
V
Input voltage
V
– 0.5
–
V
+ 0.5
V
I5_ABS
SSD
DDD
[35]
SID16
V
V
Analog input voltage
V
V
– 0.3
– 0.3
–
–
V
V
+ 0.3
+ 0.3
V
V
IA_ABS
SSA
DDA
For ports 0, 1, 2, 3, 4, 5, 16, 17,
18, 19, 20, 21, 22, 23, 28, 29, 30,
31
[35]
SID17A
Output voltage
O0_ABS
SSD
DDD
[35]
SID17B
SID17C
SID17D
SID17E
V
V
V
V
Output voltage
V
V
– 0.3
– 0.3
–
–
–
–
V
V
V
V
+ 0.3
+ 0.3
+ 0.3
+ 0.3
V
V
V
V
For ports 6, 7, 8, 9, 32
For ports 10, 11, 12, 13, 14, 15
For ports 24, 25
O1_ABS
O2_ABS
O3_ABS
O5_ABS
SSD
SSD
DDIO_1
DDIO_2
DDIO_3
DDIO_4
[35]
Output voltage
[35]
Output voltage
V
V
– 0.3
– 0.3
SSIO_3
SSIO_4
[35]
Output voltage
For ports 26, 27, 33, 34
For EXT_PS_CTL1/2 in
external PMIC mode,
DRV_VOUT in external
transistor mode
[35]
SID17F
SID18
V
|I
Output voltage
V
– 0.3
–
–
–
V + 0.3
DDD
V
O4_ABS
SSD
[36, 37, 38]
|
Maximum clamp current
–5
5
mA
mA
CLAMP_ABS
Maximum positive clamp current per
I/O supply pin. Limit applies to I/O
supply pin closest to the B+ injected
I
+B injected DC current is not
allowed for Ports 11 and 21.
CLAMP_SUP-
PLY_POS_ABS
SID18A
–
10
[40]
current
Maximum negative clamp current per
I/O ground pin. Limit applies to I/O
supply pin closest to the B+ injected
I
+B injected DC current is not
allowed for Ports 11 and 21.
CLAMP_SUP-
PLY_NEG_ABS
SID18B
SID18C
Notes
–
–
–
–
10
50
mA
mA
[40]
current.
Maximum positive clamp current per
I/O supply, if not limited by the per
supply pin (based on SID18A).
I
CLAMP_TO-
TAL_POS_ABS
35.These parameters are based on the condition that VSSD = VSSA = VSSIO_3 = VSSIO_4 = 0.0 V.
36.A current-limiting resistor must be provided such that the current at the I/O pin does not exceed rated values at any time, including
during power transients. Refer to Figure 27-1 for more information on the recommended circuit.
37.VDDD and VDDIO must be sufficiently loaded or protected to prevent them from being pulled out of the recommended operating range
by the clamp current.
38.When the conditions of [36], [37] and SID18A/B/C/D are met, |ICLAMP_ABS| supersedes VIA_ABS and VI_ABS.
39.The definition of “closer” depends on the package. In TEQFP packaging, “closest” is determined by counting pins. For example, in a
176-TEQFP package, P17.4 (pin 120) is closer to the VDDD on pin 110 than on pin 132. Ports 11 and 21 should not be used for injection
currents. The impact of injection currents is only defined for GPIO_STD/GPIO_ENH type I/Os. In BGA packaging, the following IO port
groups are treated as having separate supply pins: Ports 0, 1, 2, 22, 23, and 28; Ports 3, 4, 5, 29, 30, and 31; Ports 6, 7, 8, 9, and 32;
Ports 10, 12, 13, 14, 15, 26, and 27; Ports 16 and 17; Ports 18, 19, and 20.
Datasheet
111
002-21617 Rev. *K
2022-10-10
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Electrical specifications
Table 27-1
Absolute maximum ratings (continued)
Details/
Conditions
Spec ID
Parameter
Description
Min
Typ
Max
Units
Maximum negative clamp current per
I/O ground, if not limited by the per
supply pin (based on SID18B).
I
CLAMP_TO-
TAL_NEG_ABS
SID18D
–
–
50
mA
GPIO_STD, configured for
drive_sel<1:0>= 0b0X
GPIO_STD, configured for
drive_sel<1:0>= 0b10
GPIO_STD, configured for
drive_sel<1:0>= 0b11
GPIO_ENH, configured for
drive_sel<1:0>= 0b0X
GPIO_ENH, configured for
drive_sel<1:0>= 0b10
GPIO_ENH, configured for
drive_sel<1:0>= 0b11
HSIO, configured for
drive_sel<1:0>= 0b00
HSIO, configured for
drive_sel<1:0>= 0b01
[40]
SID20A
SID20B
SID20C
SID21A
SID21B
SID21C
SID22A
SID22B
SID22C
SID22D
I
I
I
I
I
I
I
I
I
I
LOW-level maximum output current
LOW-level maximum output current
LOW-level maximum output current
LOW-level maximum output current
LOW-level maximum output current
LOW-level maximum output current
LOW-level maximum output current
LOW-level maximum output current
LOW-level maximum output current
LOW-level maximum output current
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
6
2
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
OL1A_ABS
OL1B_ABS
OL1C_ABS
OL2A_ABS
OL2B_ABS
OL2C_ABS
OL3A_ABS
OL3B_ABS
OL3C_ABS
OL3D_ABS
[40]
[40]
[40]
[40]
[40]
[40]
[40]
[40]
[40]
1
6
2
1
10
2
HSIO, configured for
drive_sel<1:0>= 0b10
HSIO, configured for
drive_sel<1:0>= 0b11
1
0.5
For pin EXT_PS_CTL1 in
external PMIC mode and
[40]
SID23A
I
Sink maximum current
–
–
4
mA internal regulator mode and
pin EXT_PS_CTL2 in external
PMIC mode
OL4A_ABS
For pin EXT_PS_CTL1 in
external PMIC mode and
mA internal regulator mode and
pin EXT_PS_CTL2 in external
PMIC mode
[41]
SID23B
SID23C
I
I
Sink average current
–
–
–
–
1
OL4B_ABS
For pin DRV_VOUT in external
transistor mode
[40]
Sink maximum current
25
mA
OL4C_ABS
[44]
SID26A
SID26B
∑I
∑I
LOW-level total output current
–
–
–
–
50
85
mA
mA
OL_ABS_GPIO
OL_ABS_HSIO
[43]
LOW-level total output current
GPIO_STD, configured for
mA
[40]
SID27A
SID27B
SID27C
SID28A
SID28B
SID28C
SID29A
SID29B
SID29C
I
I
I
I
I
I
I
I
I
I
HIGH-level maximum output current
HIGH-level maximum output current
HIGH-level maximum output current
HIGH-level maximum output current
HIGH-level maximum output current
HIGH-level maximum output current
HIGH-level maximum output current
HIGH-level maximum output current
HIGH-level maximum output current
HIGH-level maximum output current
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–5
–2
OH1A_ABS
OH1B_ABS
OH1C_ABS
OH2A_ABS
OH2B_ABS
OH2C_ABS
OH3A_ABS
OH3B_ABS
OH3C_ABS
OH3D_ABS
drive_sel<1:0>= 0b0X
GPIO_STD, configured for
drive_sel<1:0>= 0b10
[40]
[40]
[40]
[40]
[40]
[40]
[40]
[40]
[40]
mA
GPIO_STD, configured for
drive_sel<1:0>= 0b11
–1
mA
GPIO_ENH, configured for
drive_sel<1:0>= 0b0X
–5
mA
GPIO_ENH, configured for
drive_sel<1:0>= 0b10
–2
mA
GPIO_ENH, configured for
drive_sel<1:0>= 0b11
–1
mA
HSIO, configured for
drive_sel<1:0>= 0b00
–10
–2
mA
HSIO, configured for
drive_sel<1:0>= 0b01
mA
HSIO, configured for
drive_sel<1:0>= 0b10
–1
mA
HSIO, configured for
drive_sel<1:0>= 0b11
SID29D
–0.5
mA
Notes
40. The maximum output current is the peak current flowing through any one I/O.
41. The average output current is defined as the value of the average current flowing through any one of the corresponding pins for a 10 ms period. The
average value is the operation current × the operation ratio. The operation current period over the average current spec should be less than 100 ns.
42. The total output current is the maximum current flowing through all GPIO_STD and GPIO_ENH I/Os.
43. The total output current is the maximum current flowing through all HSIO_STD I/Os.
Datasheet
112
002-21617 Rev. *K
2022-10-10
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Electrical specifications
Table 27-1
Absolute maximum ratings (continued)
Details/
Spec ID
Parameter
Description
Min
–
Typ
–
Max
–4
Units
Conditions
For pin EXT_PS_CTL1 in
external PMIC mode and
[40]
SID30A
SID30B
SID30C
SID30D
I
I
I
I
Source maximum current
Source maximum current
mA internal regulator mode and
pin EXT_PS_CTL2 in external
PMIC mode.
OH4A_ABS
OH4B_ABS
OH4C_ABS
OH4D_ABS
For pin DRV_VOUT in external
transistor mode.
For pin EXT_PS_CTL1 in
external PMIC mode and
mA internal regulator mode and
pin EXT_PS_CTL2 in external
PMIC mode.
[40]
–
–
–25
–1
mA
[41]
Source average current
–
–
For pin DRV_VOUT in external
transistor mode.
[41]
Source average current
–
–
–12
mA
[44]
[43]
SID33A
SID33B
SID33D
∑I
∑I
HIGH-level total output current
HIGH-level total output current
Total output power dissipation
–
–
–
–
–
–
–50
–85
307
mA
mA
mW
OH_ABS_GPIO
OH_ABS_HSIO
[44]
PIO
Power dissipation for external
PMIC/transistor mode
Power dissipation for internal regulator
mode
SID34
P
P
–
–
–
–
1000
2000
mW
mW
T
T
should not exceed 150 °C
should not exceed 150 °C
D
D
J
J
SID34A
SID35
SID36
SID37
SID38
T
T
T
T
Ambient temperature
Ambient temperature
Storage temperature
Operating Junction temperature
–40
–40
–55
–40
–
–
–
–
105
125
150
150
°C
°C
°C
°C
For S-grade devices
For E-grade devices
A
A
STG
J
Electrostatic discharge human body
model
Electrostatic discharge charged device
model for corner pins
Electrostatic discharge charged device
model for all other pins
The maximum pin current the device
can tolerate before triggering a latch-up
SID39A
SID39B1
SID39B2
SID39C
V
V
V
2000
750
–
–
–
–
–
–
V
V
ESD_HBM
ESD_CDM1
ESD_CDM2
500
–
V
I
–100
100
mA
LU
VDDD or VDDIO
Current
Protection
Diode
limiting
resistor
+B input
Protection
Diode
VSS
Example of a recommended circuit[45]
Figure 27-1
WARNING:
Semiconductor devices may be permanently damaged by application of stress (including, without limitation, voltage, current, or
temperature) in excess of absolute maximum ratings. Do not exceed any of these ratings.
Notes
44.The total output power dissipation is the maximum power dissipation flowing through all I/Os. PIO = (VDDD,VDDIO_1,VDDIO_2) ×
(|∑IOH_ABS_GPIO| + |∑IOL_ABS_GPIO|) + (VDDIO_3, VDDIO_4) × (|∑IOH_ABS_HSIO| + |∑IOL_ABS_HSIO|)
45.+B is the positive battery voltage around 45 V.
Datasheet
113
002-21617 Rev. *K
2022-10-10
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Electrical specifications
27.2
Device-level specifications
Table 27-2
Recommended operating conditions
Spec ID Parameter
Description
Min
Typ
Max
Units Details/Conditions
V
DDD, VDDA
,
SID40
VDDIO_1
,
,
Power supply voltage[46]
2.7[47]
–
5.5[48]
V
VDDIO_2
Power supply voltage for
eFuse programming[49]
SID40A
SID40B
VDDIO_1_EFP
VDDIO_3
3
–
–
5.5
3.6
V
,
Power supply voltage
2.7
V
VDDIO_4
External VCCD power
supply range when
SID40C
SID41
VCCD
CS1
External VCCD power supply
Smoothing capacitor[50, 51]
1.10
6.79
1.15
–
1.20
22
V
externally supplying
VCCD
µF
VCCD
VREF_L
CS1
VSSD
VSSA
Single-point connection
between analog and
digital grounds
Figure 27-2
Smoothing capacitor
Smoothing capacitor should be placed as close as possible to the VCCD pin.
Notes
46.V , V
, V
DDIO_2
, V
, V
, and V
do not have any sequencing limitation and can establish in any order. These supplies (except
DDD DDIO_1 DDIO_2 DDIO_3 DDIO_4
DDA
DDA
V
and V
) are independent in voltage level. See 12-Bit SAR ADC DC Specifications when using ADC units.
47.3.0 V ±10% is supported with a lower BOD setting option for V
and V . This setting provides robust protection for internal timing but
DDA
DDD
BOD reset occurs at a voltage below the specified operating conditions. A higher BOD setting option is available (consistent with down to
3.0 V) and guarantees that all operating conditions are met.
48.5.0 V ±10% is supported with a higher OVD setting option for V
and V . This setting provides robust protection for internal and interface
DDA
DDD
timing, but OVD reset occurs at a voltage above the specified operating conditions. A lower OVD setting option is available (consistent with
up to 5.0 V) and guarantees that all operating conditions are met. Voltage overshoot to a higher OVD setting range for V
and V
is
DDD
DDA
permissible, provided the duration is less than 2 hours cumulated. Note that during overshoot voltage condition electrical parameters are
not guaranteed.
49.eFuse programming must be executed with the part in a “quiet” state, with minimal activity (preferably only JTAG or a single LIN/CAN channel
on V
domain, no activity on V
).
DDD
DDIO_1
50.Smoothing capacitor, C is required per chip (not per V
pin). The V
pins must be connected together to ensure a low-impedance
CCD
S1
CCD
connection (see the requirement in Figure 27-2).
51.Capacitors used for power supply decoupling or filtering are operated under a continuous DC-bias. Many capacitors used with DC power
across them provide less than their target capacitance, and their capacitance is not constant across their working voltage range. When
selecting capacitors for use with this device, ensure that the selected components provide the required capacitance under the specific
operating conditions of temperature and voltage used in your design. While the temperature coefficient is normally found within a part’s
catalog (such as, X7R, C0G, Y5V), the matching voltage coefficient may only be available on the component datasheet or direct from the
manufacturer. Use of components that do not provide the required capacitance under the actual operating conditions may cause the device
to operate to less than datasheet specifications.
Datasheet
114
002-21617 Rev. *K
2022-10-10
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Electrical specifications
27.3
DC specifications
Table 27-3
DC specifications, CPU current, and transition time specifications
All specifications are valid for –40 °C TA 125 °C and for 2.7 V to 5.5 V except where noted.
Spec ID
Parameter
Description
Min Typ Max Units
Details/Conditions
Active/Sleep mode
CM0+ and CM7_0 clocked at 8 MHz
with IMO.
CM7_1 powered off.
All peripherals are disabled. No IO
toggling. CPUs CM7_0 and CM0+
mA executing Dhrystone from flash
with cache enabled.
V
current in internal
DDD
regulator mode, LPACTIVE
mode
I
DD_VDDD_CM0
7_8_1
SID49C1
–
10
17
(CM0+ and CM7_0 at 8 MHz, all
peripherals are disabled)
Typ: T = 25 °C, V
= 5.0 V,
A
DDD
process typ (TT)
Max: T = 25 °C, V
= 5.5 V,
A
DDD
process worst (FF)
CM0+ and CM7_0 clocked at 8 MHz
with IMO.
CM7_1 powered off.
All peripherals are enabled. No IO
toggling.
M-DMA transferring data from
code + work flash, P-DMA chains
mA with maximum trigger activity.
CPUs CM7_0 and CM0+ executing
Dhrystone from flash with cache
enabled.
V
current in internal
DDD
regulator mode, LPACTIVE
mode
I
DD_VDDD_CM0
7_8
SID49C
–
12
226
(CM0+ and CM7_0 at 8 MHz, all
peripherals are enabled)
Typ: T = 25 °C, V
= 5.0 V,
A
DDD
process typ (TT)
Max: T = 105 °C, V
= 5.5 V,
DDD
A
process worst (FF)
PLL enabled at 350 MHz with ECO
reference.
All peripherals are enabled. No IO
toggling.
CM7_1 powered off.
M-DMA transferring data from
code + work flash, P-DMA chains
mA with maximum trigger activity.
CPUs CM7_0 and CM0+ executing
Dhrystone from flash with cache
enabled.
V
current in external
CCD
PMIC/transistor mode, Active
mode (CM7_0 at
I
DD1_VC-
CD_CM7_350
SID49E1
–
155 431
350 MHz, CM0+ at 100 MHz, all
peripherals are enabled)
Typ: T = 25 °C, V
= 1.15 V,
A
CCD
process typ (TT)
Max: T = 125 °C, V
= 1.20 V,
CCD
A
process worst (FF)
Datasheet
115
002-21617 Rev. *K
2022-10-10
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Electrical specifications
Table 27-3
DC specifications, CPU current, and transition time specifications (continued)
All specifications are valid for –40 °C TA 125 °C and for 2.7 V to 5.5 V except where noted.
Spec ID
Parameter
Description
Min Typ Max Units
Details/Conditions
PLL enabled at 350 MHz with ECO
reference.
All peripherals are enabled. No IO
toggling.
CM7_1 powered off.
M-DMA transferring data from
code + work flash, P-DMA chains
mA with maximum trigger activity.
CPUs CM7_0 and CM0+ executing
Dhrystone from flash with cache
enabled.
V
current in external
DDD
PMIC/transistor mode, Active
mode (CM7_0 at
I
DD1_-
SID49E2
–
7
9
VDDD_CM7_350
350 MHz, CM0+ at 100 MHz, all
peripherals are enabled)
Typ: T = 25 °C, V
= 5.0 V,
A
DDD
process typ (TT)
Max: T = 125 °C, V
= 5.5 V,
DDD
A
process worst (FF)
PLL enabled at 350 MHz with ECO
reference.
All peripherals are enabled. No IO
toggling.
M-DMA transferring data from
code + work flash, P-DMA chains
with maximum trigger activity.
CM7 CPUs and CM0+ executing
Dhrystone from flash with cache
enabled.
V
current in external
CCD
PMIC/transistor mode, Active
mode (CM7 CPUs at 350 MHz,
CM0+ at 100 MHz, all periph-
erals are enabled)
SID50A1
I
–
209 543
mA
DD1_VCCD_F
Typ: T = 25 °C, V
= 1.15 V,
A
CCD
process typ (TT)
Max: T = 125 °C, V
= 1.20 V,
CCD
A
process worst (FF)
PLL enabled at 350 MHz with ECO
reference.
All peripherals are enabled. No IO
toggling.
M-DMA transferring data from
code + work flash, P-DMA chains
with maximum trigger activity.
CM7 CPUs and CM0+ executing
Dhrystone from flash with cache
enabled.
V
current in external
DDD
PMIC/transistor mode, Active
mode (CM7 CPUs at 350 MHz,
CM0+ at 100 MHz, all periph-
erals are enabled)
SID50A2
I
–
7
9.3
mA
DD1_VDDD_F
Typ: T = 25 °C, V
= 5.0 V,
A
DDD
process typ (TT)
Max: T = 125 °C, V
= 5.5 V,
DDD
A
process worst (FF)
IMO clocked at 8 MHz.
All peripherals, PLL, FLL,
peripheral clocks, interrupts, CSV,
DMA are disabled. No IO toggling.
V
current in internal
DDD
SID53A
I
regulator mode. CM7_1=OFF,
Other CPUs in Sleep.
–
7
218
mA
DD2_8_VDDD
Typ: T = 25 °C, V
= 5.0 V,
A
DDD
process typ (TT)
Max: T = 105 °C, V
= 5.5 V,
DDD
A
process worst (FF)
Datasheet
116
002-21617 Rev. *K
2022-10-10
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Electrical specifications
Table 27-3
DC specifications, CPU current, and transition time specifications (continued)
All specifications are valid for –40 °C TA 125 °C and for 2.7 V to 5.5 V except where noted.
Spec ID
Parameter
Description
Min Typ Max Units
Details/Conditions
T = 25 °C, 64-KB SRAM retention,
A
Event generator operates with
ILO0 in DeepSleep and LP Active,
Smart I/O operates with ILO0,
CM0+, CM7_0: Retained,
CM7_1: OFF.
Typ: V
= 5.0 V,
DDD
process typ (TT)
Max: V = 5.5 V,
DDD
process worst (FF)
This average current is achieved
under the following conditions.
1. MCU repetitively goes from
DeepSleep to LP Active with a
period of 32 ms.
Average current for cyclic
wake-up operation. This is the
average current for the
specified LPACTIVE mode and
DeepSleep mode (RTC, WDT,
and Event Generator
2. One of the I/Os is toggled using
SID58A
I
–
60
198
µA Smart I/O to activate an external
sensor connected to an analog
input of A/D in DeepSleep
DD_CWU2
operating).
3. After 200 µs delay, the CM7_0
wakes up by Event generator
trigger to LP Active mode with IMO
and A/D conversion is triggered by
software.
4. Group A/D conversion is
performed on 5 channels with the
sampling time of 1 µs each.
5. Once the group A/D conversion
is finished, and the results fit in the
window of the range comparator,
the I/O is toggled back by software
to de-activate the sensor and the
CM7_0 goes back to DeepSleep.
DeepSleep mode
DeepSleep Mode (RTC, WDT, and
event generator operating, all
other peripherals are off except for
retention registers),
64-KB SRAM retention, ILO0
operation
SID64A
I
–
–
50
176
5.5
µA CM0+, CM7_0: Retained
DD_DS64A
T = 25 °C
A
Typ: V
= 5.0 V, process typ (TT)
= 5.5 V,
DDD
Max: V
DDD
process worst (FF)
DeepSleep Mode steady state at T
= 125 °C (RTC, WDT, and event
generator operating, all other
peripherals are off except for
retention registers),
A
64 KB SRAM retention, ILO0
operation
SID64C
I
1.4
mA
DD_DS64C
CM0+, CM7_0: Retained
Typ: V
(TT)
= 5.0 V, process worst
DDD
Max: V
(FF)
= 5.5 V, process worst
DDD
Datasheet
117
002-21617 Rev. *K
2022-10-10
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Electrical specifications
Table 27-3
DC specifications, CPU current, and transition time specifications (continued)
All specifications are valid for –40 °C TA 125 °C and for 2.7 V to 5.5 V except where noted.
Spec ID
Parameter
Description
Min Typ Max Units
Details/Conditions
Hibernate mode
ILO0/WDT operating. All other
peripherals, and all CPUs are off.
SID66
I
I
Hibernate Mode
–
–
8
–
–
µA
µA
DD_HIB1
T = 25 °C, V
= 5.0 V,
DDD
A
Process typ (TT)
ILO0/WDT operating. All other
peripherals, and all CPUs are off.
SID66A
Hibernate Mode
180
DD_HIB2
T = 125 °C, V
= 5.5 V,
DDD
A
Process worst (FF)
Power mode transition times
When the IMO is already running and
all HFCLK roots are at least 8 MHz.
Power down time from Active
to DeepSleep
SID69
t
–
–
2.5
µs HFCLK roots that are slower than
this will require additional time to
turn off.
ACT_DS
When using the 8-MHz IMO.
µs Measured from wakeup interrupt
during DeepSleep until wakeup.
DeepSleep to Active transition
time (IMO clock)
[52]
SID67
t
t
–
–
–
–
10
26
DS_ACT
When using the 8-MHz IMO.
DeepSleep to Active transition
time (IMO clock, flash
execution)
Measured from wakeup interrupt
[52]
[52]
SID67C
µs
DS_ACT1
during DeepSleep until flash
execution.
When using the FLL to generate
96 MHz from the 8-MHz IMO.
µs Measured from wakeup interrupt
during DeepSleep until the FLL
locks.
When using the FLL to generate
96 MHz from the 8-MHz IMO.
µs Measured from wakeup interrupt
during DeepSleep until flash
execution.
When using the PLL to generate
96 MHz from the 8-MHz IMO.
µs Measured from wakeup interrupt
during DeepSleep until the PLL
locks.
DeepSleep to Active transition
time (FLL clock)
SID67A
SID67D
SID67B
SID68
t
t
t
t
–
–
–
–
–
–
–
–
15
26
60
DS_ACT_FLL
DS_ACT_FLL1
DS_ACT_PLL
HVR_ACT
DeepSleep to Active transition
time (FLL clock, flash
execution)
[52]
[52]
DeepSleep to Active transition
time (PLL clock)
Release time from HV reset
(POR, BOD, OVD, OCD, WDT,
Hibernate wakeup, or XRES_L)
release until CM0+ begins
executing ROM boot
Withoutbootruntime, guaranteed
265
µs
by design
Release time from LV reset
(Fault, Internal system reset,
MCWDT, or CSV) during
Without boot runtime.
µs
SID68A
SID68B
t
t
–
–
–
–
10
15
LVR_ACT
LVR_DS
Guaranteed by design
Active/Sleep until CM0+ begins
executing ROM boot
Release time from LV reset
(Fault, or MCWDT) during
DeepSleep until CM0+ begins
executing ROM boot
Without boot runtime.
µs
Guaranteed by design
Note
52.At cold temperature –5 °C to –40 °C, the DeepSleep to Active transition time can be higher than the max time indicated by as much
as 20 µs.
Datasheet
118
002-21617 Rev. *K
2022-10-10
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Electrical specifications
Table 27-3
DC specifications, CPU current, and transition time specifications (continued)
All specifications are valid for –40 °C TA 125 °C and for 2.7 V to 5.5 V except where noted.
Spec ID
Parameter
Description
Min Typ Max Units
Details/Conditions
ROM boot startup time or
wakeup time from hibernate in
NORMAL protection state
ROM boot startup time or
wakeup time from hibernate in
SECURE protection state
Guaranteed by Design, CM0+
SID80A
t
t
–
–
–
–
1640
2330
µs clocked at 100 MHz (Flash boot
version 3.1.0.554 and later)
RB_N
Guaranteed by Design, CM0+
µs clocked at 100 MHz (Flash boot
version 3.1.0.554 and later)
SID80B
RB_S
Guaranteed by Design,
TOC2_FLAGS=0x2CF, CM0+
µs clocked at 100 MHz (Flash boot
version 3.1.0.554 and later),
Listen window = 0 ms
Flash boot startup time or
wakeup time from hibernate in
NORMAL/SECURE protection
state
SID81A
SID81B
t
t
–
–
–
–
80
FB
Flash boot with app
authentication time in
NORMAL/SECURE protection
state
5000
µs Guaranteed by Design,
TOC2_FLAGS=0x24F, CM0+
clocked at 100 MHz (Flash boot
version 3.1.0.554 and later),
Listen window = 0 ms, Public key
exponent e = 0x010001, App size is
64 KB with the last 256 bytes being
a digital signature in
FB_A
RSASSA-PKCS1-v1.5
Valid for RSA2K.
ROM boot startup time or
wakeup time from hibernate in
NORMAL protection state
ROM boot startup time or
wakeup time from hibernate in
SECURE protection state
Guaranteed by design, CM0+
µs clocked at 50 MHz (Flash boot
version earlier than 3.1.0.554)
Guaranteed by design, CM0+
µs clocked at 50 MHz (Flash boot
version earlier than 3.1.0.554)
SID80A_2
SID80B_2
t
t
–
–
–
–
2640
3890
RB_N_2
RB_S_2
Guaranteed by design,
TOC2_FLAGS=0x2CF, CM0+
µs clocked at 50 MHz (Flash boot
version earlier than 3.1.0.554),
Listen window = 0 ms
Flash boot startup time or
wakeup time from hibernate in
NORMAL/SECURE protection
state
SID81A_2
SID81B_2
t
t
–
–
–
–
200
FB_2
Flash boot with app
authentication time in
NORMAL/SECURE protection
state
10000 µs Guaranteed by design,
TOC2_FLAGS=0x24F, CM0+
clocked at 50 MHz (Flash boot
version earlier than 3.1.0.554),
Listen window = 0 ms, Public key
exponent e = 0x010001, App size is
64 KB with the last 256 bytes being
a digital signature in
FB_A_2
RSASSA-PKCS1-v1.5
Valid for RSA2K.
Regulator specifications
Core supply voltage (transient
range)
Core supply voltage (static
range, no load)
Regulator operating current in
Active/Sleep mode
Regulator operating current in
DeepSleep mode
SID600
SID600A
SID601
SID602
V
V
1.05 1.1 1.15
1.075 1.1 1.125
V
V
CCD
Guaranteed by design
CCD_S
I
I
–
–
900 1500
µA Guaranteed by design
µA Guaranteed by design
DDD_ACT
DDD_DPSLP
1.5
–
20
Average V
current until C
CCD
DDD
s1
SID603
SID604
I
I
In-rush current
–
–
850
300
mA (connected to V
pin) is charged
RUSH
after Active regulator is turned on
Internal regulator output
current for operation
–
mA
ILDOUT
Datasheet
119
002-21617 Rev. *K
2022-10-10
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Electrical specifications
Table 27-3
DC specifications, CPU current, and transition time specifications (continued)
All specifications are valid for –40 °C TA 125 °C and for 2.7 V to 5.5 V except where noted.
Spec ID
Parameter
Description
Min Typ Max Units
Details/Conditions
High current regulator output
current for operation
SID605
I
–
–
600
mA Using an external pass transistor
HCROUT
Output voltage LOW level for
external PMIC enable output
(EXT_PS_CTL1)
Output voltage HIGH level for
external PMIC enable output
(EXT_PS_CTL1)
Input voltage HIGH threshold
for external PMIC power OK
input (EXT_PS_CTL0)
Input voltage LOW threshold
for external PMIC power OK
input (EXT_PS_CTL0)
SID606
SID606A
SID607
SID607A
V
V
V
–
–
0.5
V
V
V
V
I
I
= 1 mA
OL_HCR
OH_HCR
IH_HCR
IL_HCR
OL
V
–
DDD
–
–
–
–
= –1 mA
OH
0.5
0.7 ×
DDD
–
V
0.3 ×
V
V
–
V
DDD
Hysteresis for external PMIC
0.05 ×
SID607B
SID608
–
–
–
V
HYS_HCR
power OK input (EXT_PS_CTL0)
V
DDD
DRV_VOUT pin output current
to external NPN base current
See Architecture TRM for external
NPN transistor selection
I
–
9
mA
DRV_VOUT
27.4
Reset specifications
All specifications are valid for –40 °C TA 125 °C and for 2.7 V to 5.5 V except where noted.
Table 27-4 XRES_L reset
Spec ID Parameter
Description
Min
Typ
Max
Units Details/Conditions
XRES_L DC specifications
MAX: TA = 125 °C,
VDDD = 5.5 V,
SID73
IIDD_XRES
IDD when XRES_L asserted
–
–
2.5
mA
VCCD = 1.15 V,
process worst (FF)
Input voltage HIGH
threshold
Input voltage LOW
threshold
SID74
SID75
VIH
VIL
0.7 × VDDD
–
–
–
–
V
V
CMOS Input
CMOS Input
0.3 × VDDD
SID76
SID77
SID78
RPULLUP
CIN
VHYSXRES
Pull-up resistor
Input capacitance
Input voltage hysteresis
7
–
–
–
–
20
5
–
kΩ
pF
V
0.05 × VDDD
XRES_L AC specifications
Without boot
XRES_L deasserted to
Active transition time
SID70
tXRES_ACT
–
–
265
µs runtime, guaranteed
by design
SID71
SID72
tXRES_PW
tXRES_FT
XRES_L pulse width
Pulse suppression width
5
100
–
–
–
–
µs
ns
Datasheet
120
002-21617 Rev. *K
2022-10-10
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Electrical specifications
release
HV/LV reset
System clock
System reset
release
RESET
ACTIVE
4
MODES
1
2
3
1:
2:
3:
4:
SID68/68A/68B: Time from HV/LV reset release until CM0+ begins executing ROM boot
SID80A/80B: ROM boot code operation
SID81A/81B: Flash boot code operation
User code operation
Figure 27-3
Reset sequence
Datasheet
121
002-21617 Rev. *K
2022-10-10
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Electrical specifications
27.5
I/O
All specifications are valid for –40 °C TA 125 °C and for 2.7 V to 5.5 V except where noted.
Table 27-5
I/O specifications
Spec ID
Parameter
Description
Min
–
Typ
–
Max
0.6
0.4
0.4
0.4
0.4
0.4
0.4
–
Units
Details/Conditions
GPIO_STD Specifications for ports P1 through P23, P28 to P32
I
= 6 mA
OL
drive_sel<1:0> = 0b0X,
SID650
SID650C
SID651
SID652
SID652C
SID653
SID653C
SID654
SID655
SID656
SID656C
SID657
SID657C
V
V
V
V
V
V
V
V
V
V
V
V
V
Output voltage LOW level
Output voltage LOW level
Output voltage LOW level
Output voltage LOW level
Output voltage LOW level
Output voltage LOW level
Output voltage LOW level
Output voltage HIGH level
Output voltage HIGH level
Output voltage HIGH level
Output voltage HIGH level
Output voltage HIGH level
Output voltage HIGH level
V
V
V
V
V
V
V
V
V
V
V
V
V
OL1_GPIO_STD
OL1C_GPIO_STD
OL2_GPIO_STD
OL3_GPIO_STD
OL3C_GPIO_STD
OL4_GPIO_STD
OL4C_GPIO_STD
OH1_GPIO_STD
OH2_GPIO_STD
OH3_GPIO_STD
OH3C_GPIO_STD
OH4_GPIO_STD
OH4C_GPIO_STD
4.5 V ≤ V or V
or
or
or
or
or
or
or
or
or
DDD
DDIO_1
V
≤ 5.5 V
DDIO_2
I
= 5 mA
OL
drive_sel<1:0> = 0b0X,
4.5 V ≤ V or V
–
–
DDD
DDIO_1
V
≤ 5.5 V
DDIO_2
I
= 2 mA
OL
drive_sel<1:0> = 0b0X,
2.7 V ≤ V or V
–
–
DDD
DDIO_1
V
< 4.5 V
DDIO_2
I
= 1 mA
OL
drive_sel<1:0> = 0b10,
–
–
2.7 V ≤ V or V
DDIO_2
DDD
DDIO_1
V
< 4.5 V
I
= 2 mA
OL
drive_sel<1:0> = 0b10,
4.5 V ≤ V or V
–
–
DDD
DDIO_1
V
≤ 5.5 V
DDIO_2
I
= 0.5 mA
OL
drive_sel<1:0> = 0b11,
2.7 V ≤ V or V
–
–
DDD
DDIO_1
V
< 4.5 V
DDIO_2
I
= 1 mA
OL
drive_sel<1:0> = 0b11,
4.5 V ≤ V or V
–
–
DDD
DDIO_1
V
≤ 5.5 V
DDIO_2
(V
,
I
= –2 mA
OH
DDD
V
V
V
V
V
V
, or
drive_sel<1:0> = 0b0X,
2.7 V ≤ V or V
DDIO_1
–
V
) –
DDIO_2
DDD
DDIO_1
0.5
V
< 4.5 V
DDIO_2
(V
,
I
= –5 mA
OH
DDD
, or
drive_sel<1:0> = 0b0X,
4.5 V ≤ V or V
DDIO_1
–
–
V
) –
DDIO_2
DDD
DDIO_1
0.5
V
≤ 5.5 V
DDIO_2
(V
,
I
= –1 mA
OH
DDD
, or
drive_sel<1:0> = 0b10,
2.7 V ≤ (V , V , or
DDIO_1
–
–
V
) –
DDIO_2
DDD DDIO_1
0.5
V
) < 4.5 V
DDIO_2
(V
,
I
= –2 mA
OH
DDD
, or
drive_sel<1:0> = 0b10,
4.5 V ≤ (V , V , or
DDIO_1
–
–
V
) –
DDIO_2
DDD DDIO_1
0.5
V
) ≤ 5.5 V
DDIO_2
(V
,
I
= –0.5 mA
OH
DDD
, or
drive_sel<1:0> = 0b11,
2.7 V ≤ (V , V , or
DDIO_1
–
–
V
) –
DDIO_2
DDD DDIO_1
0.5
V
) < 4.5 V
DDIO_2
(V
,
I
= –1 mA
OH
DDD
, or
drive_sel<1:0> = 0b11,
4.5 V ≤ (V , V , or
DDIO_1
–
–
V
) –
DDIO_2
DDD DDIO_1
0.5
V
) ≤ 5.5 V
DDIO_2
SID658
SID659
R
R
Pull-down resistance
Pull-up resistance
25
25
50
50
100
100
kΩ
kΩ
PD_GPIO_STD
PU_GPIO_STD
0.7 × (V
,
DDD
Inputvoltage HIGHthreshold
in CMOS mode
SID660
SID661
SID662
V
V
V
V
, or
–
–
–
–
–
–
V
V
V
IH_CMOS_GPIO_STD
IH_TTL_GPIO_STD
IH_AUTO_GPIO_STD
DDIO_1
V
)
DDIO_2
Inputvoltage HIGHthreshold
in TTL mode
2.0
0.8 × (V
,
DDD
Inputvoltage HIGHthreshold
in AUTO mode
V
, or
DDIO_1
DDIO_2
V
)
Datasheet
122
002-21617 Rev. *K
2022-10-10
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Electrical specifications
Table 27-5
I/O specifications (continued)
Spec ID
Parameter
Description
Min
Typ
Max
Units
Details/Conditions
0.3 ×
Input voltage LOW threshold
in CMOS mode
(V
,
DDD
SID663
SID664
SID665
V
–
–
V
IL_CMOS_GPIO_STD
V
V
, or
DDIO_1
V
)
DDIO_2
Input voltage LOW threshold
in TTL mode
V
V
–
–
–
0.8
V
V
IL_TTL_GPIO_STD
0.5 ×
Input voltage LOW threshold
in AUTO mode
(V
DDIO_1
,
DDD
–
IL_AUTO_GPIO_STD
, or
V
)
DDIO_2
0.05 × (V
,
,
DDD
SID666
V
V
Hysteresis in CMOS mode
V
, or
–
–
V
HYST_CMOS_GPIO_STD
HYST_AUTO_GPIO_STD
DDIO_1
V
)
DDIO_2
0.05 × (V
DDD
SID668
SID669
Hysteresis in AUTO mode
Input pin capacitance
V
, or
–
–
–
5
V
DDIO_1
DDIO_2
V
)
C
–
pF
For 10 MHz and 100 MHz
in_GPIO_STD
For GPIO_STD except P21.0,
P21.1, P21.2, P21.3, P21.4, P22.1,
P22.2, P22.3, P23.3, P23.4.
V
= V
= V
= V
=
DDIO_1
DDIO_2
DDD
DDA
SID670
I
Input leakage current
–250
0.02
250
nA
5.5 V,
< V < V , V , V
DDD DDIO_1 DDIO_2
IL_GPIO_STD
V
SSD
I
–40 °C T 125 °C
A
Typ: T = 25 °C, V
= V
=
DDIO_2
A
DDIO_1
V
= V
= 5.0 V
DDD
DDA
Only for P21.0, P21.1, P21.2,
P21.3, P21.4, P22.1, P22.2, P22.3,
P23.3, P23.4.
V
= V
= V
= V
=
DDIO_1
DDIO_2
DDD
DDA
SID670C
I
Input leakage current
–700
0.02
700
nA
5.5 V,
< V < V , V , V
DDD DDIO_1 DDIO_2
IL_GPIO_STD_B
V
SSD
I
–40 °C T 125 °C
A
Typ: T = 25 °C, V
= V
=
DDIO_2
A
DDIO_1
V
= V
= 5.0 V
DDD
DDA
t
or t (fast)
Rise time or fall time (10% to
R
F
_20_0_GPI-
_50_0_GPI-
_20_1_GPI-
_10_2_GPI-
_6_3_GPI-
SID671
SID672
SID673
SID674
SID675
1
1
1
1
1
–
–
–
–
–
10
20
20
20
20
ns
ns
ns
ns
ns
20-pF load, drive_sel<1:0> = 0b00
50-pF load, drive_sel<1:0> = 0b00
20-pF load, drive_sel<1:0> = 0b01
10-pF load, drive_sel<1:0> = 0b10
6-pF load, drive_sel<1:0> = 0b11
90% of V
)
DDIO
O_STD
t
or t (fast)
Rise time or fall time (10% to
90% of V
R
F
)
DDIO
O_STD
t
or t (fast)
Rise time or fall time (10% to
90% of V
R
F
)
DDIO
O_STD
t
or t (fast)
Rise time or fall time (10% to
90% of V
R
F
)
DDIO
O_STD
t
or t (fast)
Rise time or fall time (10% to
90% of V
R
F
)
DDIO
O_STD
10-pF to 400-pF load, R = 767 Ω,
drive_sel<1:0>= 0b00,
Freq = 100 kHz
PU
Fall time (30% to 70% of
DDIO
SID676
t
t
(fast)
(fast)
0.35
–
250
ns
F
F
_100_GPIO_STD
_400_GPIO_STD
V
)
10-pF to 400-pF load, R = 350 Ω,
PU
Fall time (30% to 70% of
SID677
SID678
0.35
–
–
–
250
100
ns
drive_sel<1:0>= 0b00,
Freq = 400 kHz
V
)
DDIO
f
f
Input frequency
MHz
IN_GPIO_STD
20-pF load,
drive_sel<1:0>= 00,
SID679
SID680
Output frequency
–
–
–
–
50
32
MHz
MHz
OUT_GPIO_STD0H
4.5 V ≤ V
≤ 5.5 V
or V
or V
or V
DDD
DDIO_1
DDIO_2
DDIO_2
20-pF load,
drive_sel<1:0>= 00,
f
Output frequency
OUT_GPIO_STD0L
2.7 V ≤ V
or V
DDD
DDIO_1
< 4.5 V
Datasheet
123
002-21617 Rev. *K
2022-10-10
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Electrical specifications
Table 27-5
I/O specifications (continued)
Spec ID
Parameter
Description
Min
Typ
Max
Units
Details/Conditions
20-pF load,
drive_sel<1:0>= 01,
SID681
SID682
SID683
SID684
SID685
SID686
f
f
f
f
f
f
Output frequency
–
–
25
MHz
OUT_GPIO_STD1H
4.5 V ≤ V
≤ 5.5 V
or V
or V
or V
or V
or V
or V
or V
DDD
DDIO_1
DDIO_2
DDIO_2
DDIO_2
DDIO_2
DDIO_2
DDIO_2
20-pF load,
drive_sel<1:0>= 01,
Output frequency
Output frequency
Output frequency
Output frequency
Output frequency
–
–
–
–
–
–
–
–
–
–
15
25
15
15
10
MHz
MHz
MHz
MHz
MHz
OUT_GPIO_STD1L
OUT_GPIO_STD2H
OUT_GPIO_STD2L
OUT_GPIO_STD3H
OUT_GPIO_STD3L
2.7 V ≤ V
or V
DDD
DDIO_1
< 4.5 V
10-pF load,
drive_sel<1:0>= 10,
4.5 V ≤ V
≤ 5.5 V
or V
DDD
DDIO_1
10-pF load,
drive_sel<1:0>= 10,
2.7 V ≤ V
or V
DDD
DDIO_1
< 4.5 V
6-pF load,
drive_sel<1:0>= 11,
4.5 V ≤ V
≤ 5.5 V
or V
DDD
DDIO_1
6-pF load,
drive_sel<1:0>= 11,
2.7 V ≤ V
or V
DDD
DDIO_1
< 4.5 V
GPIO_ENH Specifications for P0
I
= 6 mA
OL
SID650A
SID650D
SID651A
SID652A
SID652D
SID653A
SID653D
SID654A
SID655A
SID656A
SID656D
SID657A
V
V
V
V
V
V
V
V
V
V
V
V
Output voltage LOW level
Output voltage LOW level
Output voltage LOW level
Output voltage LOW level
Output voltage LOW level
Output voltage LOW level
Output voltage LOW level
Output voltage HIGH level
Output voltage HIGH level
Output voltage HIGH level
Output voltage HIGH level
Output voltage HIGH level
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
0.6
0.4
0.4
0.4
0.4
0.4
0.4
–
V
V
V
V
V
V
V
V
V
V
V
V
drive_sel<1:0> = 0b0X,
2.7 V ≤ V ≤ 5.5 V
OL1_GPIO_ENH
OL1D_GPIO_ENH
OL2_GPIO_ENH
OL3_GPIO_ENH
OL3D_GPIO_ENH
OL4_GPIO_ENH
OL4D_GPIO_ENH
OH1_GPIO_ENH
OH2_GPIO_ENH
OH3_GPIO_ENH
OH3D_GPIO_ENH
OH4_GPIO_ENH
DDD
I
= 5 mA
OL
drive_sel<1:0> = 0b0X,
4.5 V ≤ V ≤ 5.5 V
DDD
I
= 2 mA
OL
drive_sel<1:0> = 0b0X,
2.7 V ≤ V < 4.5 V
DDD
I
= 1 mA
OL
drive_sel<1:0> = 0b10,
2.7 V ≤ V < 4.5 V
DDD
I
= 2 mA
OL
drive_sel<1:0> = 0b10,
4.5 V ≤ V ≤ 5.5 V
DDD
I
= 0.5 mA
OL
drive_sel<1:0> = 0b11,
2.7 V ≤ V < 4.5 V
DDD
I
= 1 mA
OL
drive_sel<1:0> = 0b11,
4.5 V ≤ V ≤ 5.5 V
DDD
I
= –2 mA
OH
V
V
V
V
V
– 0.5
drive_sel<1:0> = 0b0X,
2.7 V ≤ V < 4.5 V
DDD
DDD
DDD
DDD
DDD
DDD
I
= –5 mA
OH
– 0.5
– 0.5
– 0.5
– 0.5
–
drive_sel<1:0> = 0b0X,
4.5 V ≤ V ≤ 5.5 V
DDD
I
= –1 mA
OH
–
drive_sel<1:0> = 0b10,
2.7 V ≤ V < 4.5 V
DDD
I
= –2 mA
OH
–
drive_sel<1:0> = 0b10,
4.5 V ≤ V ≤ 5.5 V
DDD
I
= –0.5 mA
OH
–
drive_sel<1:0> = 0b11,
2.7 V ≤ V < 4.5 V
DDD
Datasheet
124
002-21617 Rev. *K
2022-10-10
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Electrical specifications
Table 27-5
I/O specifications (continued)
Spec ID
Parameter
Description
Min
– 0.5
Typ
Max
Units
Details/Conditions
= –1 mA
I
OH
SID657D
V
Output voltage HIGH level
V
–
–
V
drive_sel<1:0> = 0b11,
4.5 V ≤ V ≤ 5.5 V
OH4D_GPIO_ENH
DDD
DDD
SID658A
SID659A
R
Pull-down resistance
Pull-up resistance
25
25
50
50
100
100
kΩ
kΩ
PD_GPIO_ENH
PU_GPIO_ENH
R
Inputvoltage HIGHthreshold
in CMOS mode
SID660A
SID661A
SID662A
SID663A
SID664A
SID665A
V
V
V
V
V
V
0.7 × V
–
–
–
–
–
–
–
–
–
V
V
V
V
V
V
IH_CMOS_GPIO_ENH
IH_TTL_GPIO_ENH
IH_AUTO_GPIO_ENH
IL_CMOS_GPIO_ENH
IL_TTL_GPIO_ENH
IL_AUTO_GPIO_ENH
DDD
DDD
Inputvoltage HIGHthreshold
in TTL mode
2.0
Inputvoltage HIGHthreshold
in AUTO mode
0.8 × V
Input voltage LOW threshold
in CMOS mode
–
–
–
0.3 × V
0.8
DDD
Input voltage LOW threshold
in TTL mode
Input voltage LOW threshold
in AUTO mode
0.5 × V
DDD
SID666A
SID668A
SID669A
V
V
Hysteresis in CMOS mode
Hysteresis in AUTO mode
Input pin capacitance
0.05 × V
0.05 × V
–
–
–
–
–
–
5
V
V
HYST_CMOS_GPIO_ENH
HYST_AUTO_GPIO_ENH
DDD
DDD
C
pF
For 10 MHz and 100 MHz
in_GPIO_ENH
V
V
= V
= 5.5 V,
DDA
DDD
SSD
< V < V
I
DDD
SID670A
I
Input leakage current
–350
0.055
350
nA
–40 °C T 125 °C
IL_GPIO_ENH
A
Typ: T = 25 °C,
A
= V
V
= 5.0 V
DDD
DDA
20-pF load, drive_sel<1:0>=0b00,
slow = 0
t
or t (fast)
Rise time or fall time (10% to
R
F
_20_0_GPI-
_50_0_GPI-
_20_1_GPI-
_10_2_GPI-
_6_3_GPI-
SID671A
SID672A
SID673A
SID674A
SID675A
1
1
1
1
1
–
–
–
–
–
10
20
20
20
20
ns
ns
ns
ns
ns
90% of V
)
DDIO
O_ENH
50-pF load, drive_sel<1:0>=0b00,
slow = 0
t
or t (fast)
Rise time or fall time (10% to
90% of V
R
F
)
DDIO
O_ENH
20-pF load, drive_sel<1:0>=0b01,
slow = 0
t
or t (fast)
Rise time or fall time (10% to
90% of V
R
F
)
DDIO
O_ENH
10-pF load, drive_sel<1:0>=0b10,
slow = 0
t
or t (fast)
Rise time or fall time (10% to
90% of V
R
F
)
DDIO
O_ENH
6-pF load, drive_sel<1:0> = 0b11,
slow = 0
t
or t (fast)
Rise time or fall time (10% to
90% of V
R
F
)
DDIO
O_ENH
10-pF to 400-pF load,
drive_sel<1:0> = 0b00,
Fall time (30% to 70% of
DDIO
20 × (V
/
/
/
DDD
SID676A
SID677A
t
(slow)
–
–
250
160
ns
ns
F_I2C
_GPIO_ENH
V
)
5.5)
slow = 1, minimum R = 400 Ω
PU
20-pF load, drive_sel<1:0>=0b00,
slow = 1,
output frequency = 1 MHz
t
or t (slow)
Rise time or fall time (10% to 20 × (V
R
F
_20_GPI-
DDD
90% of V
)
DDIO
5.5)
O_ENH
400-pF load, drive_sel<1:0> =
0b00, slow = 1,
output frequency = 400 kHz
t
or t (slow)
Rise time or fall time (10% to 20 × (V
R
F
_400_GPI-
DDD
SID678A
SID679A
SID680A
–
–
–
250
100
50
ns
90% of V
)
DDIO
5.5)
O_ENH
f
f
Input frequency
–
–
MHz
IN_GPIO_ENH
20-pF load,
Output frequency
MHz drive_sel<1:0>= 0b00,
4.5 V ≤ V ≤ 5.5 V
OUT_GPIO_ENH0H
OUT_GPIO_ENH0L
OUT_GPIO_ENH1H
OUT_GPIO_ENH1L
DDD
20-pF load,
MHz drive_sel<1:0>= 0b00,
2.7 V ≤ V < 4.5 V
SID681A
SID682A
SID683A
f
f
f
Output frequency
Output frequency
Output frequency
–
–
–
–
–
–
32
25
15
DDD
20-pF load,
MHz drive_sel<1:0>= 0b01,
4.5 V ≤ V ≤ 5.5 V
DDD
20-pF load,
MHz drive_sel<1:0>= 0b01,
2.7 V ≤ V < 4.5 V
DDD
Datasheet
125
002-21617 Rev. *K
2022-10-10
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Electrical specifications
Table 27-5
I/O specifications (continued)
Spec ID
Parameter
Description
Min
Typ
Max
Units
Details/Conditions
10-pF load,
MHz drive_sel<1:0>= 0b10,
4.5 V ≤ V ≤ 5.5 V
SID684A
SID685A
SID686A
SID687A
f
f
f
f
Output frequency
–
–
25
OUT_GPIO_ENH2H
DDD
10-pF load,
MHz drive_sel<1:0>= 0b10,
2.7 V ≤ V < 4.5 V
Output frequency
Output frequency
Output frequency
–
–
–
–
–
–
15
15
10
OUT_GPIO_ENH2L
OUT_GPIO_ENH3H
OUT_GPIO_ENH3L
DDD
6-pF load,
MHz drive_sel<1:0>= 0b11,
4.5 V ≤ V ≤ 5.5 V
DDD
6-pF load,
MHz drive_sel<1:0>= 0b11,
2.7 V ≤ V < 4.5 V
DDD
HSIO Specifications for ports P24 through P27, P33, P34
I
= 4 mA,
OL
SID650B
SID651B
SID652B
SID653B
V
V
V
V
Output LOW voltage
Output LOW voltage
Output LOW voltage
Output LOW voltage
–
–
–
–
–
–
–
–
0.6
V
V
V
V
OL_GMII
drive_sel<1:0> = 0b00
I
= 0.1 mA,
OL
0.2
OL_HB_HSSPI
OL_eMMC
OL_SD
drive_sel<1:0> = 0b00
I
= 0.1 mA,
0.125 ×
DDIO_3/4
OL
V
drive_sel<1:0> = 0b00
I
= 2 mA,
0.125 ×
DDIO_3/4
OL
V
drive_sel<1:0> = 0b00
I
= 10 mA,
OL
SID654B
SID655B
SID656B
SID656E
V
V
V
V
Output LOW voltage
Output LOW voltage
Output LOW voltage
Output LOW voltage
–
–
–
–
–
–
–
–
0.4
V
V
V
V
drive_sel<1:0> = 0b00,
= 2.7 V
OL1
OL2
OL3
OL4
V
DDIO_3/4
I
= 2 mA,
OL
0.4
0.4
0.4
drive_sel<1:0> = 0b01,
= 2.7 V
V
DDIO_3/4
I
= 1 mA,
OL
drive_sel<1:0> = 0b10,
= 2.7 V
V
DDIO_3/4
I
= 0.5 mA,
OL
drive_sel<1:0> = 0b11,
V
= 2.7 V
DDIO_3/4
I
= –4 mA
V
V
V
–
–
–
OH
DDIO_3/4
SID657B
SID658B
V
V
Output HIGH voltage
Output HIGH voltage
–
–
–
–
V
V
OH_GMII
0.6
drive_sel<1:0> = 0b00
I
= –0.1 mA
OH
DDIO_3/4
OH_HB_HSSPI
0.2
drive_sel<1:0> = 0b00
DDIO_3/4
I
= –0.1 mA
OH
SID659B
SID660B
V
V
Output HIGH voltage
Output HIGH voltage
(0.25 ×
–
–
–
–
V
V
OH_eMMC
OH_SD
drive_sel<1:0> = 0b00
V
)
DDIO_3/4
V
–
DDIO_3/4
I
= –2 mA
OH
(0.25 ×
drive_sel<1:0> = 0b00
V
)
DDIO_3/4
I
= –10 mA
OH
V
V
V
V
–
DDIO_3/4
SID661B
SID662B
SID663B
SID663E
V
V
V
V
Output HIGH voltage
Output HIGH voltage
Output HIGH voltage
Output HIGH voltage
–
–
–
–
–
–
–
–
V
V
V
V
drive_sel<1:0> = 0b00,
= 2.7 V
OH1
OH2
OH3
OH3
0.5
V
DDIO_3/4
I
= –2 mA
OH
–
–
–
DDIO_3/4
drive_sel<1:0> = 0b01,
= 2.7 V
0.5
V
DDIO_3/4
I
= –1 mA
OH
DDIO_3/4
drive_sel<1:0> = 0b10,
= 2.7 V
0.5
V
DDIO_3/4
I
= –0.5 mA
OH
DDIO_3/4
drive_sel<1:0> = 0b11,
= 2.7 V
0.5
V
DDIO_3/4
SID664B
SID665B
R
R
Pull-down resistance
Pull-up resistance
25
25
50
50
100
100
kΩ
kΩ
PD
PU
Datasheet
126
002-21617 Rev. *K
2022-10-10
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Electrical specifications
Table 27-5
I/O specifications (continued)
Spec ID
Parameter
Description
Min
Typ
Max
Units
Details/Conditions
vtrip_sel<1:0> = 0b00
Input HIGH voltage for
HyperBus and HSSPI in
CMOS mode
0.7 ×
DDIO_3/4
SID666B
V
–
–
V
IH_CMOS
V
V
Input HIGH voltage for RGMII
in CMOS mode
0.8 ×
DDIO_3/4
SID667B
SID668E
SID668B
SID669B
SID669E
V
V
V
V
V
–
–
–
–
–
–
–
–
–
–
V
V
V
V
V
vtrip_sel<1:0> = 0b00
vtrip_sel<1:0> = 0b01
vtrip_sel<1:0> = 0b11
vtrip_sel<1:0> = 0b00
vtrip_sel<1:0> = 0b10
IH_RGMII
IH_TTL
Input Voltage HIGH
threshold for TTL mode
2
Input HIGH voltage for GMII
mode
1.7
IH_GMII
Input HIGH voltage for SD
and eMMC in CMOS mode
0.625 ×
DDIO_3/4
IH_SD_eMMC
IH_AUTO
V
Input Voltage HIGH
threshold in AUTO mode
0.8 ×
V
DDIO_3/4
Input LOW voltage for
HYPERBUS™ and HSSPI in
CMOS mode
0.3 ×
DDIO_3/4
SID670B
V
–
–
V
vtrip_sel<1:0> = 0b00
IL_CMOS
V
V
Input LOW voltage for RGMII
in CMOS mode
0.2 ×
DDIO_3/4
SID671B
SID672E
SID672B
SID673B
SID673E
SID674B
V
V
V
V
V
V
V
–
–
–
–
–
–
–
–
–
–
–
V
V
V
V
V
V
vtrip_sel<1:0> = 0b00
vtrip_sel<1:0> = 0b01
vtrip_sel<1:0> = 0b11
vtrip_sel<1:0> = 0b00
vtrip_sel<1:0> = 0b10
vtrip_sel<1:0> = 0b00
IL_RGMII
Input Voltage LOW threshold
for TTL mode
0.8
0.9
IL_TTL
Input LOW voltage for GMII
mode
IL_GMII
Input LOW voltage for SD and
eMMC in CMOS mode
0.25 ×
DDIO_3/4
0.5 ×
IL_SD_eMMC
IL_AUTO
V
V
Input Voltage LOW threshold
in AUTO mode
DDIO_3/4
0.05 ×
DDIO_3/4
0.05 ×
Hysteresis in CMOS mode
–
HYST_CMOS
HYST_AUTO
V
SID674F
SID675B
Hysteresis in AUTO mode
Input pin capacitance
–
–
–
5
V
vtrip_sel<1:0> = 0b10
V
DDIO_3
C
–
pF
For 10 MHz and 100 MHz
IN
V
V
= 3.6 V,
DDIO_3/4
SSIO_3/4
< V < V
I
DDIO_3/4
SID676B
I
Input leakage current
–450
1.02
450
nA
–40 °C T 125 °C
IL
A
Typ: T = 25 °C,
A
V
= 3.3 V
DDIO_3/4
SID677B
SID678B
SID679B
SID680B
SID681B
SID682B
SID683B
SID684B
SID685B
f
f
f
f
f
f
f
f
f
Input frequency
Input frequency
Input frequency
Input frequency
Input frequency
Output frequency
Output frequency
Output frequency
Output frequency
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
125
125
100
52
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
IN_GMII
IN_RGMII
IN_HB_HSSPI
IN_eMMC
50
IN_SD
125
100
52
OUT_GMII_RGMII
OUT_HB_HSSPI
OUT_eMMC
OUT_SD
50
GPIO Input Specifications
Analog glitch filter (pulse
suppression width)
[53]
SID98
SID99
t
t
–
–
–
50
ns
ns
One filter per port
FT
Minimum pulse width for
GPIO interrupt
160
t–
INT
Note
53.If a longer pulse suppression width is necessary, use Smart I/O.
Datasheet
127
002-21617 Rev. *K
2022-10-10
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Electrical specifications
27.6
Analog peripherals
All specifications are valid for –40 °C TA 125 °C and for 2.7 V to 5.5 V except where noted.
27.6.1
SAR ADC
0xFFF
Actual conversion
characteristics
1.5 LSb
0xFFE
0xFFD
1 LSb (N - 1) + 0.5 LSb
VNT
0x003
0x002
0x001
Actual conversion
characteristics
Ideal
characteristics
0.5 LSb
VREFH
VREFL
Analog input
[LSb]
[V]
Total error of digital output N = ( VNT {1 LSb × (N – 1) + 0.5 LSb} ) / 1 LSb
1 LSb (Ideal value) = (VREFH – VREFL) / 4096
N: A/D converter digital output value
VZT (Ideal value): VREFL + 0.5 LSb [V]
VFST (Ideal value): VREFH – 1.5 LSb [V]
V
NT: Voltage at which the digital output changes from N – 1 to N
Figure 27-4
ADC characteristics and error descriptions
Datasheet
128
002-21617 Rev. *K
2022-10-10
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Electrical specifications
Table 27-6
Spec ID
12-Bit SAR ADC DC specifications
Parameter
Description
Min
Typ
Max Units Details/Conditions
SAR ADC
SID100 A_RES
SID101 A_VINS
SID102A A_VDDA
–
–
12
VREFH
5.5
bits
V
resolution
Input voltage
range
VDDA voltage
range
VREFL
2.7
–
–
[54]
V
ADC performance
VREFH voltage
range
degrades when high
reference is higher than
SID102 A_VREFH
2.7
–
–
VDDA
V
supply (VDDA
)
ADC performance
degrades when low
reference is lower than
ground
VREFL voltage
range
SID103 A_VREFL
SID103A Vband_gap
VSSA
VSSA
V
V
Internal band gap 0.882 0.9
reference voltage
0.918
Ratio of current
collected on a pin
CLAMP_COUPLING_RA- to the positive
SID19A
SID19B
–
–
0.1
%
TIO_POS
current injected
intoa neighboring
pin
Ratio of current
collected on a pin
CLAMP_COUPLING_RA- to the negative
–
–
–
–
1.2
50
%
TIO_NEG
current injected
intoa neighboring
pin
Internal pin
resistance to
current collection
point
SID19C RCLAMP_INTERNAL
Ω
27.6.2
Calculating the impact of neighboring pins
The three ADC specifications based on SID19A, SID19B, and SID19C, can be used to calculate the pin leakage and
resulting ADC offset caused by injection current using the below formula:
ILEAK = IINJECTED × CLAMP_COUPLING_RATIO
VERROR = ILEAK × (RCLAMP_INTERNAL + RSOURCE)
Code Error = VERROR × 212 / VREF
Where:
IINJECTED is the injected current in mA.
I
LEAK is the calculated leakage current in mA.
VERROR is the voltage error calculated due to leakage currents in V.
REF is the ADC reference voltage in V.
V
Note
54.VDDD must be greater than 0.8 × VDDA when ADC[2] is enabled. VDDIO_1 must be greater than 0.8 × VDDA when ADC[0] is enabled.
Datasheet
129
002-21617 Rev. *K
2022-10-10
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Electrical specifications
Differential linearity error
Integral linearity error
0xFFF
Ideal
characteristics
Actual conversion
characteristics
N + 1
0xFFE
VFST
Actual conversion
characteristics
(Measured value)
(1 LSb [N - 1] + VZT)
0xFFD
N
VNT
(Measured value)
0x004
0x003
0x002
0x001
N - 1
Actual conversion
characteristics
V(N +
1)T
(Measured value)
VNT
(Measured value)
Ideal
characteristics
Actual conversion
characteristics
N -2
VZT
(Measured value)
VREFL
Analog input
VREFL
Analog input
VREFH
VREFH
Integral linearity error of digital output N = (VNT
–
{1 LSb × (N
–
1) + VZT}) / 1 LSb
[LSb]
[LSb]
[V]
Differential linearity error of digital output N = (V(N + 1)T – VNT
1 LSb = (VFST – VZT ) / 4094
– 1 LSb ) / 1 LSb
V
ZT: Voltage for which digital output changes from 0x000 to 0x001
VFST: Voltage for which digital output changes from 0xFFE to 0xFFF.
Figure 27-5
Integral and differential linearity errors
EXTERNAL CIRCUIT
INTERNAL EQUIVALENT CIRCUIT
VDDIO
Channel selection MUX and ADC
REXT
RVIN
CVIN
CEXT
CIN
ESD Protection
R
EXT: Source impedance
CEXT: On-PCB capacitance
CIN: I/O pad or Input capacitance
RVIN: ADC equivalent input resistance
CVIN: ADC equivalent input capacitance
K: Constant for sampling accuracy, K = ln(abs(4096/LSbSAMPLE))
Sampling Time (tSAMPLE) requirement is shown in the following equation
t
SAMPLE > K x { CVIN x ( RVIN + REXT ) + ( CIN + CEXT ) x (REXT) } [seconds]
K = value of 9.0 is recommended to get ±0.5 LSb sampling accuracy at 12-bit (LSbSAMPLE = ±0.5)
Figure 27-6
ADC equivalent circuit for analog input
Datasheet
130
002-21617 Rev. *K
2022-10-10
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Electrical specifications
Table 27-7
SAR ADC AC specifications
Spec ID Parameter
Description
Min
Typ
Max
Units Details/Conditions
VDDA = 2.7 V to 5.5 V,
–40 °C ≤ TA ≤ 125 °C
SID104 VZT
Zero transition voltage
–20
–
20
mV
before offset
adjustment
VDDA = 2.7 V to 5.5 V,
Full-scale transition
voltage
–40 °C ≤ TA ≤ 125 °C
SID105 VFST
–20
–
20
mV
before offset
adjustment
SID114 fADC_4P5
SID114A fADC_2P7
ADC operating frequency
ADC operating frequency
2
2
–
–
26.67
13.34
MHz 4.5 V ≤ VDDA ≤ 5.5 V
MHz 2.7 V ≤ VDDA ≤ 4.5 V
Analog input sample
time
4.5 V ≤ VDDA ≤ 5.5 V,
ns
SID113 tS_4P5
SID113A tS_2P7
412
600
–
–
–
–
guaranteed by design
(4.5 V ≤ VDDA
)
Analog input sample
time
2.7 V ≤ VDDA ≤ 4.5 V,
ns
guaranteed by design
(2.7 V ≤ VDDA
)
Analog input sample
time when input is from
diagnostic reference (4.5
4.5 V ≤ VDDA ≤ 5.5 V,
µs
SID113B tS_DR_4P5
2
–
–
guaranteed by design
V ≤ VDDA
)
Analog input sample
time when input is from
diagnostic reference (2.7
2.7 V ≤ VDDA ≤ 4.5 V,
µs
SID113C tS_DR_2P7
SID113D tS_TS
2.5
7
–
–
–
–
guaranteed by design
V ≤ VDDA
)
Analog input sample
time for temperature
sensor
µs 2.7 V VDDA 5.5 V
Guaranteed by design
4.5 V ≤ VDDA ≤ 5.5 V,
Max Throughput
80 MHz / 3 = 26.67 MHz,
SID106 tST_4P5
SID106A tST_2P7
–
–
–
–
1
Msps
(samples per second)
11 sampling cycles,
15 conversion cycles
2.7 V ≤ VDDA < 4.5 V
Max Throughput
80 MHz / 6 = 13.3 MHz,
0.5
Msps
(samples per second)
11 sampling cycles,
15 conversion cycles
ADC input sampling
capacitance
Input path ON resistance
(4.5 V to 5.5 V)
Input path ON resistance
(2.7 V to 4.5 V)
Diagnostic path ON resis-
tance (4.5 V to 5.5 V)
SID107 CVIN
–
–
–
–
–
–
–
–
4.8
9.4
13.9
40
pF Guaranteed by design
SID108 RVIN1
SID108A RVIN2
SID108B RDREF1
SID108C RDREF2
SID119 ACC_RLAD
kΩ Guaranteed by design
kΩ Guaranteed by design
kΩ Guaranteed by design
kΩ Guaranteed by design
%
–
–
Diagnostic path ON resis-
tance (2.7 V to 4.5 V)
–
50
Diagnostic reference
–4
4
resistor ladder accuracy
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Electrical specifications
Table 27-7
SAR ADC AC specifications (continued)
Spec ID Parameter
Description
Min
Typ
Max
Units Details/Conditions
VDDA = VREFH = 2.7 V to
5.5 V, VREFL = VSSA
–40 °C ≤ TA ≤ 125 °C
SID109 A_TE
Total error
–5
–
5
LSb
Total Error after offset
and gain adjustment at
12-bit resolution mode
VDDA = VREFH = 2.7 V to
5.5 V, VREFL = VSSA
–40 °C ≤ TA ≤ 125 °C
SID109A A_TEB
Total error
–12
–
12
LSb
Total error before offset
and gain adjustment at
12 bit resolution mode
VDDA = 2.7 V to 5.5 V,
SID110 A_INL
SID111 A_DNL
Integral nonlinearity
–2.5
–
–
2.5
1.9
LSb
–40 °C ≤ TA ≤ 125 °C
VDDA = 2.7 V to 5.5 V,
Differential nonlinearity –0.99
Channel to channel
LSb
–40 °C ≤ TA ≤ 125 °C
VDDA = 2.7 V to 5.5 V,
LSb
SID112 A_CE
variation (for channels
connected to same ADC)
–1
–
1
–40 °C ≤ TA ≤ 125 °C
Analog input leakage
current
Diagnostic reference
current
When input pad is
nA
SID115 IAIC
–350
–
70
–
350
70
selected for conversion
SID116 IDIAGREF
µA
Analog power supply
current while ADC is
operating
Analog power supply
current while ADC is not
operating
Analog reference voltage
current while ADC is
operating
SID117 IVDDA
SID117A IVDDA_DS
SID118 IVREF
–
–
–
–
360
1
550
21
µA Per enabled ADC
µA Per enabled ADC
µA Per enabled ADC
µA Per enabled ADC
360
1.8
550
5
Analog reference voltage
SID118A IVREF_LEAK current while ADC is not
operating
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Electrical specifications
27.6.3
Temperature sensor
Table 27-8
Temperature sensor specifications
Spec ID Parameter
Description
Min
Typ
Max Units
Details/Conditions
–40 °C ≤ T ≤ 150 °C
SID201 TSENSACC2 Temperature sensor
accuracy 2
–5
–
5
°C
J
This spec is valid when using
ADC[0] (V
), ADC[1] (V
DDD
)
DDIO_2
DDIO_1
or ADC[2] (V ) with the
following conditions:
a. 3.0 V ≤ V , V
or
DDD DDIO_1
V
= V
= V ≤ 3.6 V
REFH
DDIO_2
DDA
or
b. 4.5 V ≤ V , V
or
DDD DDIO_1
V
= V
= V
≤ 5.5 V
DDIO_2
DDA
REFH
–40 °C ≤ T ≤ 150 °C
SID201A TSENSACC3 Temperature sensor
accuracy 3
–10
–
10
°C
J
This spec is valid when using
ADC[0] (V ) or ADC[2] (V
)
DDD
DDIO_1
with the following condition:
2.7 V ≤ V or V ≤ 5.5 V and
DDD
DDIO_1
2.7 V ≤ V
= V
≤ 5.5 V and
DDA
REFH
0.8 × V
< V
or V
DDA
DDD DDIO_1
27.6.4
Voltage divider accuracy
Table 27-9
Voltage divider accuracy
Spec ID Parameter
Description
Min
Typ
Max
Units Details/Conditions
Uncorrected monitor
voltage divider accuracy
(measured by ADC),
compared to ideal
supply/2
Any HV supply pad
SID202 VMONDIV
–20
2
20
%
within 2.7 V–5.5 V
operating range
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Electrical specifications
27.7
AC specifications
Unless otherwise noted, the timings are defined with the guidelines mentioned in the Figure 27-7.
Definition of rise / fall times
VDDD or VDDIO_x
80 %
80 %
20 %
20 %
VSSD or VSSD_x or VSSIO_x
tR
tF
Time Reference Point Definition
VDDD or VDDIO_x
0.5 x VDDD or VDDIO_x
VSSD or VSSD_x or VSSIO_x
Timing Reference Points
Figure 27-7
AC timings specifications
Datasheet
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Electrical specifications
27.8
Digital peripherals
All specifications are valid for –40 °C TA 125 °C and for 2.7 V to 5.5 V except where noted.
Table 27-10 Timer/counter/PWM (TCPWM) specifications
Spec
Unit
s
Parameter
Description
Min
Typ
Max
Details/Conditions
ID
SID120 fC
TCPWM operating frequency
–
–
100
MHz fC = peripheral clock
Trigger Events can be
Stop, Start, Reload,
Input trigger pulse width for all
trigger events
Count, Capture, or Kill
SID121 tPWMENEXT
2 / fC
–
–
–
–
ns
depending on which
mode of operation is
selected.
Minimum possible
width of Overflow,
Underflow, and
SID122 tPWMEXT
Output trigger pulse widths
2 / fC
ns
Counter = Compare
(CC) value trigger
outputs
Minimum time
ns between successive
counts
SID123 tCRES
SID124 tPWMRES
SID125 tQRES
Resolution of counter
PWM resolution
1 / fC
1 / fC
2 / fC
–
–
–
–
–
–
Minimum pulse width
ns
of PWM output
Minimum pulse width
ns between Quadrature
phase inputs.
Quadrature inputs resolution
TCPWM Timing Diagrams
VIH
VIL
Input Signal
1
1
VOH
VOL
Output Signal
2
2
1: tPWMENEXT, tQRES
2: tPWMEXT
Figure 27-8
TCPWM timing diagrams
Datasheet
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Electrical specifications
Table 27-11 Serial communication block (SCB) specifications
Spec ID Parameter
Description
Min
Typ
Max Units Details/Conditions
–
–
100
MHz
SID129 fSCB
SCB operating frequency
I2C interface-Standard-mode
SID130 fSCL
SID131 tHD;STA
SID132 tLOW
SID133 tHIGH
SCL clock frequency
–
–
–
–
–
100
–
kHz
ns
Hold time, START condition
Low period of SCL
4000
4700
4000
–
ns
High period of SCL
–
ns
Setup time for a repeated
START
SID134 tSU;STA
4700
–
–
ns
SID135 tHD;DAT
SID136 tSU;DAT
SID138 tF
Data hold time, for receiver
Data setup time
0
250
–
–
–
–
–
–
–
ns
ns
Fall time of SCL and SDA
Setup time for STOP
300
–
ns Input and output
ns
SID139 tSU;STO
4000
Bus-free time between START
and STOP
SID140 tBUF
SID141 CB
4700
–
–
–
–
–
–
–
ns
pF
ns
ns
Capacitive load for each bus line
–
–
–
0
3
400
3450
3450
0.4
Time for data signal from SCL
LOW to SDA output
SID142 tVD;DAT
SID143 tVD;ACK
SID144 VOL
SID145 IOL
Data valid acknowledge time
LOW level output voltage
LOW level output current
Open-drain at 3 mA
V
sink current
–
mA VOL = 0.4 V
I2C interface-Fast-mode
SID150 fSCL_F
SID151 tHD;STA_F
SID152 tLOW_F
SID153 tHIGH_F
SCL clock frequency
–
–
–
–
–
400
–
kHz
ns
Hold time, START condition
Low period of SCL
600
1300
600
–
ns
High period of SCL
–
ns
Setup time for a repeated
START
SID154 tSU;STA_F
600
–
–
ns
SID155 tHD;DAT_F
SID156 tSU;DAT_F
Data hold time, for receiver
Data setup time
0
–
–
–
–
ns
ns
100
20 ×
Input and output,
ns GPIO_ENH: slow
mode, 400 pF load
(VDDD
/
SID158 tF_F
Fall time of SCL and SDA
–
300
5.5)
Input and output
GPIO_STD:
drive_sel<1:0>= 0b00
ns MIN: 10 pF load,
RPU = 35.41 kΩ
SID158A tFA_F
Fall time of SCL and SDA
Setup time for STOP
0.35
–
300
Max: 400 pF load,
RPU = 350 Ω
SID159 tSU;STO_F
SID160 tBUF_F
600
–
–
–
–
ns Input and output
Bus free time between START
and STOP
1300
ns
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Electrical specifications
Table 27-11 Serial communication block (SCB) specifications (continued)
Spec ID Parameter
Description
Min
Typ
Max Units Details/Conditions
SID161 CB_F
Capacitive load for each bus line
–
–
400
900
900
50
pF
ns
ns
ns
Time for data signal from SCL
LOW to SDA output
SID162 tVD;DAT_F
SID163 tVD;ACK_F
SID164 tSP_F
–
–
–
–
–
–
Data valid acknowledge time
Pulse width of spikes that must
be suppressed by the input filter
Open-drain at 3 mA
sink current
SID165 VOL_F
LOW level output voltage
0
–
0.4
V
SID166 IOL_F
SID167 IOL2_F
LOW level output current
LOW level output current
3
6
–
–
–
–
mA VOL = 0.4 V
mA VOL = 0.6 V[55]
I2C interface-Fast-Plus mode
SID170 fSCL_FP
SID171 tHD;STA_FP
SID172 tLOW_FP
SID173 tHIGH_FP
SCL clock frequency
–
–
–
–
–
1
–
–
–
MHz
ns
Hold time, START condition
Low period of SCL
260
500
260
ns
High period of SCL
ns
Setup time for a repeated
START
SID174 tSU;STA_FP
260
–
–
ns
SID175 tHD;DAT_FP
SID176 tSU;DAT_FP
Data hold time, for receiver
Data setup time
0
–
–
–
–
ns
ns
50
20 ×
Input and output
ns 20-pF load
(VDDD
/
SID178 tF_FP
Fall time of SCL and SDA
Setup time for STOP
–
160
GPIO_ENH: slow mode
5.5)
SID179 tSU;STO_FP
SID180 tBUF_FP
SID181 CB_FP
260
–
–
–
–
–
–
–
–
ns Input and output
Bus free time between START
and STOP
500
–
ns
pF
ns
ns
ns
Capacitive load for each bus line
20
450
450
50
Time for data signal from SCL
LOW to SDA output
SID182 tVD;DAT_FP
SID183 tVD;ACK_FP
SID184 tSP_FP
–
Data valid acknowledge time
–
Pulse width of spikes that must
be suppressed by the input filter
–
Open-drain at 3 mA
SID186 VOL_FP
SID187 IOL_FP
LOW level output voltage
LOW level output current
0
–
–
0.4
–
V
sink current
3[56]
mA VOL = 0.4 V[56]
SPI Interface Master (Full-clock mode: LATE_MISO_SAMPLE = 1) [Conditions: drive_sel<1:0>= 0x]
Do not use half-clock
mode:
SID190 fSPI
SPI operating frequency
–
–
12.5
MHz
LATE_MISO_SAMPLE =
0
Notes
55.In order to drive full bus load at 400 kHz, 6 mA IOL is required at 0.6 V VOL
.
56.In order to drive full bus load at 1 MHz, 20 mA IOL is required at 0.4 V VOL. However, this device does not support it.
Datasheet
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Electrical specifications
Table 27-11 Serial communication block (SCB) specifications (continued)
Spec ID Parameter
Description
Min
Typ
Max Units Details/Conditions
SPI Master: MOSI valid after
SCLK driving edge
SID191 tDMO
–
–
15
–
ns
ns
ns
SPI Master: MISO valid before
SCLK capturing edge
SID192 tDSI
SID193 tHMO
40
0
–
–
SPI Master: Previous MOSI data
hold time
–
Only for
SPI Master: Previous MOSI data
hold time
SID193A tHMOA
–3.5
–
–
–
ns SCB4_MOSI/P0.3 and
SCB4_CLK/P1.0
0.4 ×
(1 /
SPI SCLK pulse width HIGH or
LOW
SID194 tW_SCLK_H_L
–
0
ns
fSPI
)
SPI Master: MISO hold time after
SCLK capturing edge
SID196 tDHI
–
–
–
ns
SSEL valid, before the first SCK
capturing edge
0.5 ×
SID198 tEN_SETUP
–
ns Min is half clock period
(1/fSPI
)
SSEL hold, after the last SCK
capturing edge
0.5 ×
SID199 tEN_SHOLD
SID195 CSPIM_MS
–
–
–
ns Min is half clock period
pF
(1/fSPI
)
SPI capacitive load
–
10
SPI interface slave (internally clocked) [Conditions: drive_sel<1:0>= 0x]
SID205 fSPI_INT
SPI operating frequency
–
–
10
–
MHz
ns
SPI Slave: MOSI Valid before
Sclock capturing edge
SID206 tDMI_INT
5
–
SPI Slave: MISO Valid after
Sclock driving edge, in the
internal-clocked mode
SID207 tDSO_INT
SID208 tHSP
–
–
62
ns
SPI Slave: Previous MISO data
hold time
3
–
–
–
–
–
–
ns
ns
ns
tEN_SET-
SID209
SPI Slave: SSEL valid to first SCK
valid edge
33
33
UP_INT
SPI Slave Select active (LOW)
from last SCLK hold
SID210 tEN_HOLD_INT
SPI Slave: from SSEL valid, to
SCK falling edge before the first
data bit
tEN_SET-
SID211
20
20
20
20
–
–
–
–
–
–
–
–
ns
ns
ns
ns
UP_PRE
SPI Slave: from SCK falling edge
SID212 tEN_HOLD_PRE before the first data bit, to SSEL
invalid
SPI Slave: from SSEL valid, to
SID213 tEN_SETUP_CO SCK falling edge in the first data
bit
SPI Slave: from SCK falling edge
SID214 tEN_HOLD_CO in the first data bit, to SSEL
invalid
SID215 tW_DIS_INT
SPI Slave Select inactive time
40
20
20
–
–
–
–
–
–
ns
ns
ns
SID216 tW_SCLKH_INT SPI SCLK pulse width HIGH
SID217 tW_SCLKL_INT SPI SCLK pulse width LOW
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Electrical specifications
Table 27-11 Serial communication block (SCB) specifications (continued)
Spec ID Parameter
SID218 tSIH_INT
Description
SPI MOSI hold from SCLK
SPI Capacitive Load
Min
12
–
Typ
–
Max Units Details/Conditions
–
ns
pF
SID219 CSPIS_INT
–
10
SPI interface slave (externally clocked) [Conditions: drive_sel<1:0>= 0x]
SID220 fSPI_EXT
SPI operating frequency
–
–
12.5
MHz
ns
SPI Slave: MOSI Valid before
Sclock capturing edge
SID221 tDMI_EXT
5
–
–
SPI Slave: MISO Valid after
Sclock driving edge, in the
external-clocked mode
SID222 tDSO_EXT
SID223 tHSO_EXT
–
–
32
ns
SPI Slave: Previous MISO data
hold time
3
–
–
–
–
–
–
ns
ns
ns
tEN_SET-
SID224
SPI Slave: SSEL valid to first SCK
valid edge
40
40
UP_EXT
SPI Slave Select active (LOW)
from last SCLK hold
SID225 tEN_HOLD_EXT
SID226 tW_DIS_EXT
SPI Slave Select inactive time
80
34
34
20
–
–
–
–
–
–
–
–
ns
ns
ns
ns
pF
SID227 tW_SCLKH_EXT SPI SCLK pulse width HIGH
SID228 tW_SCLKL_EXT SPI SCLK pulse width LOW
–
SID229 tSIH_EXT
SID230 CSPIS_EXT
SPI MOSI hold from SCLK
SPI Capacitive Load
–
10
SPI Slave: MISO valid after SSEL
falling edge (CPHA = 0)
SID231 tVSS_EXT
–
–
33
10
ns
UART interface
SID240 fBPS
Data rate
–
–
Mbps
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TRAVEO™ T2G 32-bit Automotive MCU
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Electrical specifications
8
9
7
70%
30%
70%
70%
70%
30%
6
SDA
SCL
30%
30%
12
8
9
4
70%
70%
70%
70%
30%
70%
30%
30%
30%
30%
30%
30%
2
1
3
START condition
11
70%
30%
70%
30%
70%
70%
SDA
SCL
30%
70%
2
14
10
13
70%
70%
30%
9th clock
5
Repeated START
condition
STOP condition
START condition
1: SCL clock period = 1/fSCL
2: Hold time, START condition = tHD;STA
3: LOW period of SCL = tLOW
4: HIGH period of SCL = tHIGH
5: Setup time for a repeated START = tSU;STA
6: Data hold time, for receiver = tHD;DAT
7: Data setup time = tSU;DAT
8: Fall time of SCL and SDA = tF
9: Rise time of SCL and SDA = tR
10: Setup time for STOP = tSU;STO
11: Bus-free time between START and STOP = tBUF
12: Time for data signal from SCL LOW to SDA output = tVD;DAT
13: Data valid acknowledge time = tVD;ACK
14: Pulse width of spikes that must be suppressed by the input filter = tSP
Figure 27-9
I2C timing diagrams
Datasheet
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TRAVEO™ T2G 32-bit Automotive MCU
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Electrical specifications
SPI Master Timing Diagrams (LATE_MISO_SAMPLE=1)
CPHA=0
9
SSEL
2
1
3
SCLK
(CPOL=0)
4
4
SCLK
(CPOL=1)
5
6
MISO
(input)
7
8
MOSI
(output)
1: SCLK period = 1 / fSPI
2: Enable lead time (setup) = tEN_SETUP = Depends on SPI_CTRL.SSEL_SETUP_DEL (Refer to the Register TRM)
3: Enable trail time (hold) = tEN_HOLD = Depends on SPI_CTRL.SSEL_HOLD_DEL (Refer to the Register TRM)
4: SCLK high or low time = tW_SCLK_H_L
5: Input data setup time = tDSI
6: Input data hold time = tDHI
7: Output data valid after SCLK driving edge = tDMO
8: Output data hold time = tHMO
9: SSEL high pulse width = Depends on SPI_CTRL.SSEL_INTER_FRAME_DEL (Refer to the Register TRM)
Figure 27-10 SPI master timing diagrams with LOW clock phase
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TRAVEO™ T2G 32-bit Automotive MCU
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Electrical specifications
SPI Master Timing Diagrams (LATE_MISO_SAMPLE=1)
CPHA=1
9
SSEL
2
3
1
SCLK
(CPOL=0)
4
4
SCLK
(CPOL=1)
5
6
MISO
(input)
7
8
MOSI
(output)
1: SCLK period = 1 / fSPI
2: Enable lead time (setup) = tEN_SETUP = Depends on SPI_CTRL.SSEL_SETUP_DEL (Refer to the Register TRM)
3: Enable trail time (hold) = tEN_HOLD = Depends on SPI_CTRL.SSEL_HOLD_DEL (Refer to the Register TRM)
4: SCLK high or low time = tW_SCLK_H_L
5: Input data setup time = tDSI
6: Input data hold time = tHDI
7: Output data valid after SCLK driving edge = tDMO
8: Output data hold time = tHMO
9: SSEL high pulse width = Depends on SPI_CTRL.SSEL_INTER_FRAME_DEL (Refer to the Register TRM)
Figure 27-11 SPI master timing diagrams with HIGH clock phase
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TRAVEO™ T2G 32-bit Automotive MCU
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Electrical specifications
SPI Slave Timing Diagrams
CPHA=0
10
SSEL
2
1
3
SCLK
(CPOL=0)
4
4
SCLK
(CPOL=1)
8
7
9
MISO
(output)
5
6
MOSI
(input)
1: SCLK period = 1 / fSPI_EXT
2: enable lead time (setup) = tEN_SETUP_EXT
3: enable trail time (hold) = tEN_HOLD_EXT
4: SCLK high or low time = tw_SCLKH_EXT = tw_SCLKL_EXT
5: input data setup time = tDMI_EXT
6: input data hold time = tSIH_EXT
7: output data valid after SCLK driving edge = tDSO_EXT
8: output data valid after SSEL falling edge (CPHA=0) = tVSS_EXT
9: output data hold time = tHSO
10: SSEL high pulse width = tDIS_EXT
Figure 27-12 SPI slave timing diagrams with LOW clock phase
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TRAVEO™ T2G 32-bit Automotive MCU
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Electrical specifications
SPI slave Timing Diagrams
CPHA=1
9
SSEL
2
3
1
SCLK
(CPOL=0)
4
SCLK
(CPOL=1)
7
8
MISO
(output)
5
6
MOSI
(input)
1: SCLK period = 1 / fSPI_EXT
2: enable lead time (setup) = tEN_SETUP_EXT
3: enable trail time (hold) = tEN_HOLD_EXT
4: SCLK high or low time = tw_SCLKH_EXT = tw_SCLKL_EXT
5: input data setup time = tDMI_EXT
6: input data hold time = tSIH_EXT
7: output data valid after SCLK driving edge = tDSO_EXT
8: output data hold time = tHSO
9: SSEL high pulse width = tDIS_EXT
Figure 27-13 SPI slave timing diagrams with HIGH clock phase
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Electrical specifications
Table 27-12 CAN FD specifications
Spec ID Parameter
Description
Min
Typ Max Units Details/Conditions
fCCLK ≤ fHCLK,
,
SID630
SID631
fHCLK
fCCLK
System clock frequency
–
–
–
100
100
MHz
MHz
guaranteed by design
fCCLK ≤ fHCLK,
guaranteed by design
,
CAN clock frequency
–
Table 27-13 LIN specifications
Spec ID Parameter Description
Min
Typ
–
Max
100
20
Units Details/Conditions
MHz
Internal clock frequency to the
LIN block
BR_NOM Bit rate on the LIN bus
Bit rate on the LIN bus (not in
SID249
SID250
fLIN
–
1
–
kbps Guaranteed by design
SID250A BR_REF
standard LIN specification) for
re-flashing in LIN slave mode
1
–
115.2 kbps Guaranteed by design
Datasheet
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Electrical specifications
27.9
Memory
All specifications are valid for –40 °C TA 125 °C and for 2.7 V to 5.5 V except where noted.
Table 27-14 Flash DC specifications
Spec ID Parameter
SID260A VPE
Description
Erase and program voltage
Min
2.7
Typ Max Units
5.5
Details/Conditions
–
V
Table 27-15 Flash AC specifications
Spec ID Parameter
Description
Min Typ Max Units
Details/Conditions
Zero wait access to
code-flash memory up to
Maximum flash memory
operation frequency
SID257 fFO
–
–
100 MHz 100 MHz
Zero wait access with cache
hit up to 350 MHz
Maximum time from erase
suspend command till erase
is indeed suspend
SID254 tERS_SUS
–
250
–
–
–
–
37.5
µs
Minimum time allowed from
SID255 tERS_RES_SUS erase resume to erase
suspend
–
µs Guaranteed by design
10 +
At 100 MHz, N ≥ 4 and
Blank check time for N-bytes
SID258 tBC_WF
of work-flash
0.3 × µs multiple of 4, excludes
N
system overhead time
tSECTORE-
RASE1
tSECTORE-
RASE2
tSECTORE-
RASE3
tSECTORE-
RASE4
Sector erase time
(code-flash: 32 KB)
Includes internal
SID259
SID260
SID261
SID262
–
–
45
15
90
ms
ms
ms
ms
µs
preprogramming time
Sector erase time
Includes internal
30
(code-flash: 8 KB)
preprogramming time
Sector erase time
(work-flash, 2 KB)
Includes internal
–
80 160
preprogramming time
Sector erase time
Includes internal
–
5
15
60
70
(work-flash, 128 B)
preprogramming time
64-bit write time
(code-flash)
Excludes system overhead
SID263 tWRITE1
SID264 tWRITE2
SID265 tWRITE3
SID266 tWRITE4
SID267 tFRET1
–
30
40
time
256-bit write time
Excludes system overhead
time
–
µs
(code-flash)
4096-bit write time
(code-flash)[57]
Excludes system overhead
–
320 1200 µs
time
32-bit write time
Excludes system overhead
time
–
30
–
60
–
µs
(work-flash)
Code-flash retention.
TA (power on and off) ≤85 °C
20
years
1000 program/erase cycles
average
Work-flash retention.
125,000 program/erase
cycles
Work-flash retention.
250,000 program/erase
cycles
TA (power on and off) ≤85 °C
SID268 tFRET3
SID269 tFRET4
20
10
–
–
–
–
years
years
average
TA (power on and off) ≤85 °C
average
Note
57.The code-flash includes a 'Write Buffer' of 4096-bit. If the application software writes this buffer multiple times, to get the overall write
time multiply one sector write time with the corresponding factor (say for factor 64, example, 64 x 512 B = 32 KB [one sector]).
Datasheet
146
002-21617 Rev. *K
2022-10-10
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Electrical specifications
Table 27-15 Flash AC specifications (continued)
Spec ID Parameter
Description
Min Typ Max Units
Details/Conditions
Typ: TA = 25 °C, VDDD = 5.0 V,
VCCD = 1.15 V, process typ
(TT)
Program operating VCCD
SID612 ICC_ACT2
–
–
–
–
7
7
8
8
58
52
10
16
mA Max: TA = 125 °C,
current (code or work-flash)
VDDD = 5.5 V, VCCD = 1.2 V,
process worst (FF)
Guaranteed by design
Typ: TA = 25 °C, VDDD = 5.0 V,
VCCD = 1.15 V, process typ
(TT)
Erase operating VCCD current
(code- or work-flash)
SID613 ICC_ACT3
SID612A ICC_ACT2A
SID613A ICC_ACT3A
mA Max: TA = 125 °C,
VDDD = 5.5 V, VCCD = 1.2 V,
process worst (FF)
Guaranteed by design
Typ: TA = 25 °C, VDDD = 5.0 V,
VCCD = 1.15 V, process typ
(TT)
Program operating VDDD
mA Max: TA = 125 °C,
current (code or work-flash)
VDDD = 5.5 V, VCCD = 1.2 V,
process worst (FF)
Guaranteed by design
Typ: TA = 25 °C, VDDD = 5.0 V,
VCCD = 1.15 V, process typ
(TT)
Erase operating VDDD current
(code- or work-flash)
mA Max: TA = 125 °C,
VDDD = 5.5 V, VCCD = 1.2 V,
process worst (FF)
Guaranteed by design
Datasheet
147
002-21617 Rev. *K
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Electrical specifications
27.10
System resources
All specifications are valid for –40 °C TA 125 °C and for 2.7 V to 5.5 V except where noted.
Table 27-16 System resources
Details/
Spec ID
Parameter
Description
Min
Typ
Max Units
Conditions
Power-on reset specifications
VDDD rising voltage to de assert
POR
Guaranteed by
design
SID270 VPOR_D
1.5
–
2.35
V
VDDD falling voltage to assert
POR
Level detection hysteresis
SID276 VPOR_A
SID271 VPOR_H
1.45
20
–
–
2.1
V
300
mV
Delay between VDDD rising
through 2.3 V and internal
deassertion of POR
Guaranteed by
design
SID272 tDLY_POR
SID273 tPOFF
–
100
–
–
–
–
3
–
µs
VDDD Power off time
µs VDDD < 1.45 V
This ramp
VDDD power ramp rate with
robust BOD (BOD operation is
guaranteed)
SID274 POR_RR1
100 mV/µs supports robust
BOD
This ramp does
not support
VDDD power ramp rate without
robust BOD
SID275 POR_RR2
–
–
1000 mV/µs robust BOD
tPOFF must be
satisfied.
High-voltage BOD (HV BOD) specifications
HV BOD 2.7 V rising detection
SID500 VTR_2P7_R
SID501 VTR_2P7_F
point for VDDD and VDDA
2.474
2.55
2.627
V
V
(default)
HV BOD 2.7 V falling detection
point for VDDD and VDDA
(default)
2.449 2.525 2.601
HV BOD 3.0 V rising detection
point for VDDD and VDDA
HV BOD 3.0 V falling detection
point for VDDD and VDDA
Power ramp rate: VDDD and
VDDA (Active)
Power ramp rate: VDDD and
VDDA (DeepSleep)
SID502 VTR_3P0_R
2.765
2.74
–
2.85
2.825
–
2.936
2.91
V
V
SID503 VTR_3P0_F
SID505 HVBOD_RR_A
SID506 HVBOD_RR_DS
100 mV/µs
–
–
10
mV/µs
Active mode delay between
VDDD falling/rising through
Guaranteed by
design
SID507 tDLY_ACT_HVBOD VTR_2P7_F/R or VTR_3P0_F/R and
an internal HV BOD signal
–
–
–
–
0.5
µs
transitioning
Active mode delay between
VDDA falling/rising through
Guaranteed by
design
SID507A tDLY_ACT_HVBOD VTR_2P7_F/R or VTR_3P0_F/R and
internal HV BOD signal transi-
1
µs
tioning
Datasheet
148
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Electrical specifications
Table 27-16 System resources (continued)
Details/
Spec ID
Parameter
Description
Min
Typ
Max Units
Conditions
DeepSleep mode delay
between VDDD/VDDA
falling/rising through
VTR_2P7_F/R or VTR_3P0_F/R and
an internal HV BOD signal
transitioning
Guaranteed by
design
SID507B tDLY_DS_HVBOD
–
–
4
–
µs
ns
Response time of HV BOD,
VDDD/VDDA supply. (For
Guaranteed by
design
SID508 tRES_HVBOD
falling-then-rising supply at
max ramp rate; threshold is
100
–
VTR_2P7_F or VTR_3P0_F
)
Low-voltage BOD (LV BOD) specifications
LV BOD rising detection point
for VCCD
LV BOD falling detection point
for VCCD
SID510 VTR_R_LVBOD
SID511 VTR_F_LVBOD
0.917 0.945 0.973
0.892 0.920 0.948
V
V
Active delay between VCCD
falling/rising through
Guaranteed by
design
SID515 tDLY_ACT_LVBOD
–
–
–
–
–
1
12
–
µs
µs
ns
VTR_R/F_LVBOD and an internal
LV BOD signal transitioning
DeepSleep mode delay
between VCCD falling/rising
Guaranteed by
design
SID515A tDLY_DS_LVBOD through VTR_R/F_LVBOD and an
internal LV BOD signal transi-
tioning
Response time of LV BOD (for
falling-then-rising supply at
Guaranteed by
design
SID516 tRES_LVBOD
100
max ramp rate; threshold is
VTR_F_LVBOD
)
Low-voltage detector (LVD) DC specifications
LVD 2.8 V falling detection point Typ –
for VDDD 4%
LVD 2.9 V falling detection point Typ –
for VDDD 4%
LVD 3.0 V falling detection point Typ –
for VDDD 4%
LVD 3.1 V falling detection point Typ –
for VDDD 4%
LVD 3.2 V falling detection point Typ –
for VDDD 4%
LVD 3.3 V falling detection point Typ –
for VDDD 4%
LVD 3.4 V falling detection point Typ –
for VDDD 4%
LVD 3.5 V falling detection point Typ –
for VDDD 4%
LVD 3.6 V falling detection point Typ –
for VDDD 4%
LVD 3.7 V falling detection point Typ –
for VDDD 4%
Typ +
4%
Typ +
4%
Typ +
4%
Typ +
4%
Typ +
4%
Typ +
4%
Typ +
4%
Typ +
4%
SID520 VTR_2P8_F
SID521 VTR_2P9_F
SID522 VTR_3P0_F
SID523 VTR_3P1_F
SID524 VTR_3P2_F
SID525 VTR_3P3_F
SID526 VTR_3P4_F
SID527 VTR_3P5_F
SID528 VTR_3P6_F
SID529 VTR_3P7_F
2800
2900
3000
3100
3200
3300
3400
3500
3600
3700
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
Typ +
4%
Typ +
4%
Datasheet
149
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Electrical specifications
Table 27-16 System resources (continued)
Details/
Spec ID
Parameter
Description
Min
Typ
3800
3900
4000
4100
4200
4300
4400
4500
4600
4700
4800
4900
5000
5100
5200
5300
2825
2925
3025
3125
3225
3325
3425
3525
Max Units
Conditions
LVD 3.8 V falling detection point Typ –
Typ +
mV
SID530 VTR_3P8_F
SID531 VTR_3P9_F
SID532 VTR_4P0_F
SID533 VTR_4P1_F
SID534 VTR_4P2_F
SID535 VTR_4P3_F
SID536 VTR_4P4_F
SID537 VTR_4P5_F
SID538 VTR_4P6_F
SID539 VTR_4P7_F
SID540 VTR_4P8_F
SID541 VTR_4P9_F
SID542 VTR_5P0_F
SID543 VTR_5P1_F
SID544 VTR_5P2_F
SID545 VTR_5P3_F
SID546 VTR_2P8_R
SID547 VTR_2P9_R
SID548 VTR_3P0_R
SID549 VTR_3P1_R
SID550 VTR_3P2_R
SID551 VTR_3P3_R
SID552 VTR_3P4_R
SID553 VTR_3P5_R
for VDDD 4%
4%
LVD 3.9 V falling detection point Typ –
for VDDD 4%
LVD 4.0 V falling detection point Typ –
for VDDD 4%
LVD 4.1 V falling detection point Typ –
for VDDD 4%
LVD 4.2 V falling detection point Typ –
for VDDD 4%
LVD 4.3 V falling detection point Typ –
for VDDD 4%
LVD 4.4 V falling detection point Typ –
for VDDD 4%
LVD 4.5 V falling detection point Typ –
for VDDD 4%
LVD 4.6 V falling detection point Typ –
for VDDD 4%
LVD 4.7 V falling detection point Typ –
for VDDD 4%
LVD 4.8 V falling detection point Typ –
for VDDD 4%
LVD 4.9 V falling detection point Typ –
for VDDD 4%
LVD 5.0 V falling detection point Typ –
for VDDD 4%
LVD 5.1 V falling detection point Typ –
for VDDD 4%
LVD 5.2 V falling detection point Typ –
for VDDD 4%
LVD 5.3 V falling detection point Typ –
for VDDD 4%
LVD 2.8 V rising detection point Typ –
for VDDD 4%
LVD 2.9 V rising detection point Typ –
for VDDD 4%
LVD 3.0 V rising detection point Typ –
for VDDD 4%
LVD 3.1 V rising detection point Typ –
for VDDD 4%
LVD 3.2 V rising detection point Typ –
for VDDD 4%
LVD 3.3 V rising detection point Typ –
for VDDD 4%
LVD 3.4 V rising detection point Typ –
for VDDD 4%
LVD 3.5 V rising detection point Typ –
for VDDD 4%
Typ +
mV
4%
Typ +
mV
4%
Typ +
mV
4%
Typ +
mV
4%
Typ +
mV
4%
Typ +
mV
4%
Typ +
mV
4%
Typ +
mV
4%
Typ +
mV
4%
Typ +
mV
4%
Typ +
mV
4%
Typ +
mV
4%
Typ +
mV
4%
Typ +
mV
4%
Typ +
mV
4%
Typ +
Same as
mV
4%
VTR_2P8_F + 25 mV
Typ +
Same as
mV
4%
VTR_2P9_F + 25 mV
Typ +
Same as
mV
4%
VTR_3P0_F + 25 mV
Typ +
Same as
mV
4%
VTR_3P1_F + 25 mV
Typ +
Same as
mV
4%
VTR_3P2_F + 25 mV
Typ +
Same as
mV
4%
VTR_3P3_F + 25 mV
Typ +
Same as
mV
4%
VTR_3P4_F + 25 mV
Typ +
Same as
mV
4%
VTR_3P5_F + 25 mV
Datasheet
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2022-10-10
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Electrical specifications
Table 27-16 System resources (continued)
Details/
Spec ID
Parameter
Description
Min
Typ
3625
3725
3825
3925
4025
4125
4225
4325
4425
4525
4625
4725
4825
4925
5025
5125
5225
Max Units
Conditions
LVD 3.6 V rising detection point Typ –
Typ +
mV
Same as
SID554 VTR_3P6_R
SID555 VTR_3P7_R
SID556 VTR_3P8_R
SID557 VTR_3P9_R
SID558 VTR_4P0_R
SID559 VTR_4P1_R
SID560 VTR_4P2_R
SID561 VTR_4P3_R
SID562 VTR_4P4_R
SID563 VTR_4P5_R
SID564 VTR_4P6_R
SID565 VTR_4P7_R
SID566 VTR_4P8_R
SID567 VTR_4P9_R
SID568 VTR_5P0_R
SID569 VTR_5P1_R
SID570 VTR_5P2_R
for VDDD 4%
4%
VTR_3P6_F + 25 mV
LVD 3.7 V rising detection point Typ –
for VDDD 4%
LVD 3.8 V rising detection point Typ –
for VDDD 4%
LVD 3.9 V rising detection point Typ –
for VDDD 4%
LVD 4.0 V rising detection point Typ –
for VDDD 4%
LVD 4.1 V rising detection point Typ –
for VDDD 4%
LVD 4.2 V rising detection point Typ –
for VDDD 4%
LVD 4.3 V rising detection point Typ –
for VDDD 4%
LVD 4.4 V rising detection point Typ –
for VDDD 4%
LVD 4.5 V rising detection point Typ –
for VDDD 4%
LVD 4.6 V rising detection point Typ –
for VDDD 4%
LVD 4.7 V rising detection point Typ –
for VDDD 4%
LVD 4.8 V rising detection point Typ –
for VDDD 4%
LVD 4.9 V rising detection point Typ –
for VDDD 4%
LVD 5.0 V rising detection point Typ –
for VDDD 4%
LVD 5.1 V rising detection point Typ –
for VDDD 4%
LVD 5.2 V rising detection point Typ –
for VDDD 4%
Typ +
Same as
mV
4%
VTR_3P7_F + 25 mV
Typ +
Same as
mV
4%
VTR_3P8_F + 25 mV
Typ +
Same as
mV
4%
VTR_3P9_F + 25 mV
Typ +
Same as
mV
4%
VTR_4P0_F + 25 mV
Typ +
Same as
mV
4%
VTR_4P1_F + 25 mV
Typ +
Same as
mV
4%
VTR_4P2_F + 25 mV
Typ +
Same as
mV
4%
VTR_4P3_F + 25 mV
Typ +
Same as
mV
4%
VTR_4P4_F + 25 mV
Typ +
Same as
mV
4%
VTR_4P5_F + 25 mV
Typ +
Same as
mV
4%
VTR_4P6_F + 25 mV
Typ +
Same as
mV
4%
VTR_4P7_F + 25 mV
Typ +
Same as
mV
4%
VTR_4P8_F + 25 mV
Typ +
Same as
mV
4%
VTR_4P9_F + 25 mV
Typ +
Same as
mV
4%
VTR_5P0_F + 25 mV
Typ +
Same as
mV
4%
VTR_5P1_F + 25 mV
Typ +
Same as
mV
4%
VTR_5P2_F + 25 mV
LVD 5.3 V rising detection point Typ –
Typ +
Same as
SID571 VTR_5P3_R
SID573 LVD_RR_A
SID574 LVD_RR_DS
5325
mV
for VDDD
4%
–
4%
VTR_5P3_F + 25 mV
Power ramp rate: VDDD (Active)
–
–
100 mV/µs
Power ramp rate: VDDD
(DeepSleep)
–
10
1
mV/µs
Active mode delay between
VDDD falling/rising through LVD
rising/falling point and an
internal LVD signal
Guaranteed by
design
SID575 tDLY_ACT_LVD
–
–
µs
transitioning
Datasheet
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Electrical specifications
Table 27-16 System resources (continued)
Details/
Spec ID
Parameter
Description
Min
Typ
Max Units
Conditions
DeepSleep mode delay
between VDDD falling/rising
through LVD rising/falling point
and an internal LVD signal
transitioning
Guaranteed by
design
SID575A tDLY_DS_LVD
–
–
4
–
µs
ns
Response time of LVD, VDDD
supply. (For falling-then-rising
supply at max ramp rate;
Guaranteed by
design
SID576 tRES_LVD
100
–
threshold is LVD falling point)
High-voltage OVD specifications
HV OVD 5.0-V rising detection
SID580 VTR_5P0_R
SID581 VTR_5P0_F
5.049 5.205 5.361
V
V
point for VDDD and VDDA
HV OVD 5.0-V falling detection
point for VDDD and VDDA
HV OVD 5.5-V rising detection
point for VDDD and VDDA
(default)
HV OVD 5.5-V falling detection
point for VDDD and VDDA
(default)
5.025
5.548
5.18
5.72
5.335
5.892
SID582 VTR_5P5_R
SID583 VTR_5P5_F
V
V
5.524 5.695 5.866
Power ramp rate: VDDD and
VDDA (Active)
Power ramp rate: VDDD and
VDDA (DeepSleep)
SID585 HVOVD_RR_A
SID586 HVOVD_RR_DS
–
–
–
–
100 mV/µs
10
mV/µs
Active mode delay between
VDDD falling/rising through
SID587 tDLY_ACT_HVOVD VTR_5P0_F/R or VTR_5P5_F/R and
Guaranteed by
design
–
–
–
–
1
µs
an internal HV OVD signal
transitioning
Active mode delay between
VDDA falling/rising through
VTR_5P0_F/R or VTR_5P5_F/R and
an internal HV OVD signal
transitioning
tDLY_ACT_H-
VOVD_A
Guaranteed by
design
SID587A
1.5
4
µs
DeepSleep mode delay
between VDDD/VDDA
falling/rising through
Guaranteed by
design
SID587B tDLY_DS_HVOVD
–
–
µs
ns
VTR_5P0_F/R or VTR_5P5_F/R and
an internal HV OVD signal
transitioning
Response time of HV OVD (for
rising-then-falling supply at
max ramp rate; threshold is
Guaranteed by
design
SID588 tRES_HVOVD
100
–
–
VTR_5P0_R or VTR_5P5_R
)
Low-voltage OVD specifications
LV OVD rising detection point
for VCCD
LV OVD falling detection point
for VCCD
SID590 VTR_R_LVOVD
SID591 VTR_F_LVOVD
1.261
1.3
1.339
V
V
1.237 1.275 1.313
Datasheet
152
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2022-10-10
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Electrical specifications
Table 27-16 System resources (continued)
Details/
Spec ID
Parameter
Description
Min
Typ
Max Units
Conditions
Active mode delay between
VCCD falling/rising through
VTR_F/R_LVOVD and an internal LV
OVD signal transitioning
DeepSleep mode delay
between VCCD falling/rising
through VTR_F/R_LVOVD and an
internal LV OVD signal transi-
tioning
Guaranteed by
design
SID595 tDLY_ACT_LVOVD
SID595A tDLY_DS_LVOVD
SID596 tRES_LVOVD
–
–
1
12
–
µs
µs
ns
Guaranteed by
design
–
–
–
Response time of LV OVD. (For
rising-then-falling supply at
max ramp rate; threshold is
Guaranteed by
design
100
VTR_R_LVOVD
)
Over-current detection (OCD) specifications
Over current detection range
Guaranteed by
design
SID598A IOCD_LDO
SID598B IOCD_EXT
312
675
–
–
630
825
mA
mA
for internal Active regulator
Over current detection range
for external transistor mode
Over current detection range
for internal DeepSleep
regulator
SID599 IOCD_DPSLP
18
–
72
mA
VDDD
6.0 V
CPU and
Peripherals
CPU and
Peripherals
Regulators
I/O
Regulators
I/O
Reset
By HV OVD
High-Z
HV OVD rising trip
(Default: 5.548 V to
5.892 V)
Normal
Operation
Normal
Operation
Enable
Reset
By
XRES_L
Disable
High-Z
HV BOD rising trip
(Default: 2.474 V to
2.627 V)
Reset
By HV BOD
POR rising trip
(1.5 V to 2.35 V)
Reset
High-Z
By POR
CMOS threshold
(0.7 V)
Disable
OFF
OFF
-0.3 V
VDDD
XRES_L
LOW Level
HIGH Level
Figure 27-14 Device operations supply range
Datasheet
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Electrical specifications
2.3 V
VDDD
tDLY_POR
Internal reset by POR
VDDD
tPOFF
1.45 V
Figure 27-15 POR specifications
Datasheet
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Electrical specifications
VDDD, VDDA
VTR_2P7_R or VTR_3P0_R
VTR_2P7_F or VTR_3P0_F
Internal HV BOD signal
tDLY_ACT/DS_HVBOD
tDLY_ACT/DS_HVBOD
VDDD, VDDA
tRES_HVBOD
VTR_2P7_F or VTR_3P0_F
Figure 27-16 High-voltage BOD specifications
Datasheet
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TRAVEO™ T2G 32-bit Automotive MCU
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Electrical specifications
VCCD
VTR_R_LVBOD
VTR_F_LVBOD
Internal LV BOD signal
tDLY_ACT/DS_LVBOD
tDLY_ACT/DS_LVBOD
VCCD
tRES_LVBOD
VTR_F_LVBOD
Figure 27-17 Low-voltage BOD specifications
Datasheet
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Electrical specifications
VTR_5P0_R or VTR_5P5_R
VTR_5P0_F or VTR_5P5_F
VDDD/VDDA
Internal HV OVD signal
tDLY_ACT/DS_HVOVD
tDLY_ACT/DS_HVOVD
VTR_5P0_R or VTR_5P5_R
tRES_HVOVD
VDDD/VDDA
Figure 27-18 High-voltage OVD specifications
Datasheet
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Electrical specifications
VTR_R_LVOVD
VTR_F_LVOVD
VCCD
Internal LV OVD signal
tDLY_ACT/DS_LVOVD
tDLY_ACT/DS_LVOVD
VTR_R_LVOVD
tRES_LVOVD
VCCD
Figure 27-19 Low-voltage OVD specifications
Datasheet
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TRAVEO™ T2G 32-bit Automotive MCU
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Electrical specifications
VDDD
LVD rising detection point
LVD falling detection point
Internal LVD signal
tDLY_ACT/DS_LVD
tDLY_ACT/DS_LVD
VDDD
tRES_LVD
LVD falling detection point
Figure 27-20 LVD specifications
Datasheet
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Electrical specifications
27.10.1
SWD interface
Table 27-17 SWD interface specifications [Conditions: drive_sel<1:0>= 00]
Spec ID
SID300 fSWDCLK
SID301 tSWDI_SETUP
SID302 tSWDI_HOLD
SID303 tSWDO_VALID
SID304 tSWDO_HOLD
Parameter
Description
SWD clock input frequency
SWDI setup time
SWDI hold time
SWDO valid time
Min
–
0.25 × T
0.25 × T
Typ
–
–
–
–
Max Units Details/Conditions
10
–
–
MHz 2.7 V ≤ VDDD ≤ 5.5 V
ns T = 1 / fSWDCLK
ns T = 1 / fSWDCLK
–
1
0.5 × T ns T = 1 / fSWDCLK
ns T = 1 / fSWDCLK
SWDO hold time
–
–
Table 27-18 JTAG AC specifications [Conditions: drive_sel<1:0>= 00]
Spec ID
Parameter
Description
TCK HIGH time
TCK LOW time
Min
30
30
66.7
12
12
–
Typ
–
–
–
–
–
–
–
–
Max Units Details/Conditions
SID620 tJCKH
SID621 tJCKL
SID622 tJCP
SID623 tJSU
SID624 tJH
SID625 tJZX
SID626 tJXZ
SID627 tJCO
–
–
ns 30-pF load
ns 30-pF load
ns 30-pF load
ns 30-pF load
ns 30-pF load
ns 30-pF load
ns 30-pF load
ns 30-pF load
TCK clock period
–
–
–
TDI/TMS setup time
TDI/TMS hold time
TDO High-Z to active
TDO active to High-Z
TDO clock to output
30
30
30
–
–
tJCKH
tJCKL
tJCP
TCK
tJH
tJSU
TDI/TMS
tJCO
tJXZ
tJZX
TDO
Figure 27-21 JTAG specifications
Datasheet
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Electrical specifications
Table 27-19 Trace specifications [Conditions: drive_sel<1:0>= 00]
Spec ID
Parameter
Description
Min
Typ
Max Units Details/Conditions
SID1412A CTRACE
Trace Capacitive Load
–
–
30
pF
Trace clock cycle
time for 25 MHz
Clock low pulse
width
Clock high pulse
width
Trace data setup
time
SID1412 tTRACE_CYC
Trace clock period
40
2
–
–
–
–
ns
SID1413 tTRACE_CLKL
SID1414 tTRACE_CLKH
Trace clock LOW pulse width
Trace clock HIGH pulse width
–
–
ns
ns
ns
2
SID1415A tTRACE_SETUP Trace data setup time
3
2
–
–
–
–
SID1416A tTRACE_HOLD
Trace data hold time
ns Trace data hold time
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27.11
Clock specifications
All specifications are valid for –40 °C TA 125 °C and for 2.7 V to 5.5 V except where noted.
Table 27-20 Root and intermediate clocks[58]
Maximum permitted clock frequency setting (MHz)[59]
Max permitted
PLL/FLL Clock source: ECO[60]
Clock
clock frequency
(MHz)[59]
Source
PLL/FLL Clock source: IMO[61]
Description
Integer
200
100
100
100
350
100
100
100
100
100
125
100
SSCG
NA
NA
NA
NA
340
NA
NA
NA
NA
NA
122
NA
193
NA
NA
NA
NA
340
NA
340
NA
Fractional Integer
SSCG
NA
NA
NA
NA
326
NA
NA
NA
NA
NA
117
NA
185
NA
NA
NA
NA
326
NA
326
NA
Fractional
NA
PLL200#0
FLL
NA
NA
190
96
200
100
NA
CLK_HF0
Root clock for CPUSS, PERI
PLL200#0
FLL
NA
98
NA
NA
96
NA
PLL400#0
FLL
344
NA
333
96
330
NA
CLK_HF1
CLK_HF2
CLK_HF3
CLK_HF4
CLK_HF5
350
CM7 CPU Core#0, CM7 CPU Core#1 clock
PLL200#1
FLL
NA
98
NA
100
Peripheral clock root other than CLK_PERI
NA
96
NA
PLL200#0
FLL
NA
98
NA
100
Event generator (CLK_REF), clock output on EXT_CLK pins (when used as output)
Ethernet Channel#0, Ethernet Channel#1 internal clock
NA
96
NA
PLL400#1
FLL
122
NA
119
96
117
NA
125
PLL400#1 196.608
196.608
NA
189
96
187
NA
I2S channel#0, I2S channel#1, I2S channel#2 interface clock, Ethernet Channel#0 TSU,
Ethernet Channel#1 TSU
196.608
FLL
PLL200#0
FLL
100
200
100
NA
NA
190
96
NA
CLK_HF6
CLK_HF7
200
8
Root clock for SDHC, SMIF interface clock
NA
NA
ILO
NA
NA
333
96
NA
CSV
PLL400#0
FLL
350
100
350
100
344
NA
330
NA
CLK_FAST_0
350
Generated by clock gating CLK_HF1, CM7 CPU Core#0, intermediate clock
PLL400#0
FLL
344
NA
333
96
330
NA
CLK_FAST_1
350
Generated by clock gating CLK_HF1, CM7 CPU Core#1, intermediate clock
Notes
58. Intermediate clocks that are not listed have the same limitations as that of their parent clock.
59. Maximum clock frequency after the corresponding clock source (PLL/FLL + dividers). All internal tolerances and affects are covered by these frequencies.
60. For ECO: up to ±150 ppm uncertainty of the external clock source are tolerated by design.
61. The IMO operation frequency tolerance is included. When DeepSleep mode isn't used, maximum permitted clock frequency setting of clock source IMO case is equal to clock source ECO case.
62. CLOCK_SLOW and CLK_HF0 are related by integer frequency ratio (that is, 1:1, 1:2, 1:3, and so on).
Table 27-20 Root and intermediate clocks[58] (continued)
Maximum permitted clock frequency setting (MHz)[59]
Max permitted
clock frequency
(MHz)[59]
PLL/FLL Clock source: ECO[60]
Clock
Source
PLL/FLL Clock source: IMO[61]
Description
Integer
200
SSCG
NA
Fractional Integer
SSCG
NA
Fractional
PLL200#0
FLL
NA
NA
NA
NA
NA
NA
NA
NA
190
96
98
96
98
96
98
96
NA
NA
NA
NA
NA
NA
NA
NA
200
100
100
100
100
NA
NA
CLK_MEM
Generated by clock gating CLK_HF0, intermediate clock for SMIF, Flash, Ethernet
PLL200#0
FLL
100
NA
NA
100
NA
NA
PLL200#0
FLL
100
NA
NA
Generated by clock gating CLK_MEM, intermediate clock for CM0+, P-DMA, M-DMA,
Crypto, SMIF, SDHC
CLK_SLOW
CLK_PERI
100
NA
NA
PLL200#0
FLL
100
NA
NA
Generated by clock gating CLK_HF0, intermediate clock for IOSS, TCPWM0, CPU trace,
SMIF
100
NA
NA
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Electrical specifications
Table 27-21 Relation between CLK_HF0 and CLK_SLOW (Example)[62]
CLK_HF0 (MHz)
CLK_SLOW (MHz)
200
180
160
120
100
80
100
90
80
60
100
80
Table 27-22 IMO AC specifications
Spec ID
Parameter
Description
Min
Typ
Max Units Details/Conditions
SID310 fIMOTOL
SID311 tSTARTIMO
SID312 IIMO_ACT
IMO operating frequency
7.68
8
8.32
7.5
22
MHz
Start-up time to 90%
of final frequency
IMO start-up time
IMO current
–
–
–
µs
13.5
µA
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Electrical specifications
Table 27-23 ILO AC specifications
Spec ID
Parameter
Description
Min
Typ
Max
Units Details/Conditions
SID320 fILOTRIM
SID321 tSTARTILO
SID323 IILO
ILO operating frequency 30.47424 32.768 35.06176 kHz
Start-up timeto90%
of final frequency
ILO start-up time
ILO current
–
–
8
12
µs
500
2800
nA
Table 27-24 ECO specifications
Spec ID Parameter
Description
Min
Typ
Max Units Details/Conditions
SID330 fECO
SID332 RFDBK
Crystal frequency range
8
100
–
–
33.34 MHz
Feedback resistor value.
Min: RTRIM = 3; Max: RTRIM =
0 with 100-kΩ step size on
RTRIM
400
kΩ Guaranteed by design
Maximum operation
µA current with a 33-MHz
crystal, 18-pF load
SID333 IECO3
ECO current at TJ = 150 °C
–
–
–
–
2000
10
Time from set
CLK_ECO_-
CONFIG.ECO_EN to 1
SID334 tSTART_8M
8-MHz ECO start-up time[63]
until
ms
CLK_ECO_STATUS.ECO
_READY is set to 1 (See
Clock Timing Diagrams)
Time from set
CLK_ECO_-
CONFIG.ECO_EN to 1
ms until
SID335 tSTART_33M
33-MHz ECO start-up time[63]
–
–
1
CLK_ECO_STATUS.ECO
_READY is set to 1 (See
Clock Timing Diagrams)
VDDD
MCU
ITrim
Rf
RTrim
ECO_IN: External crystal oscillator input pin
ECO_OUT: External crystal oscillator output pin
C1, C2: Load Capacitors
ECO_IN
C3*, C4*: Stray Capacitance of the PCB
C1
C2
C3*
C4*
GTrim
VSSD
VSSD
ECO_OUT
Rd
Rd
0R
FTrim
Figure 27-22 ECO connection scheme[64]
Notes
63.Mainly depends on the external crystal.
64.Refer to the family-specific Architecture TRM for more information on crystal requirements (002-24401, TRAVEO™ T2G Automotive
MCU body controller high architecture technical reference manual).
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Electrical specifications
Table 27-25 PLL specifications
Spec ID
Parameter
Description
Min
Typ Max Units
Details/Conditions
PLL (without SSCG and fractional divider) Specifications for 200 MHz
Time from stable
reference clock until PLL
µs frequency is within 0.1%
of final value and lock
indicator is set
SID340
SID341
tPLL200_LOCK
Time to achieve PLL lock
–
–
–
35
Output frequency from PLL
block
fPLL_OUT
11
200 MHz
For 125 ns
Guaranteed by design
fPLL_VCO: 320 MHz or 400
SID342
SID343
SID344
PLL_LJIT1
PLL_LJIT2
PLL_LJIT3
Long term jitter
Long term jitter
Long term jitter
–0.25
–0.5
–
–
–
0.25
0.5
ns MHz
fPLL_OUT: 40 MHz to 200 MHz
fPLL_PFD: 8 MHz
fPLL_IN: ECO
For 500 ns
Guaranteed by design
fPLL_VCO: 320 MHz or 400
ns MHz
fPLL_OUT: 40 MHz to 200 MHz
fPLL_PFD: 8 MHz
fPLL_IN: ECO
For 1000 ns
Guaranteed by design
fPLL_VCO: 320 MHz or 400
–0.5
0.5
ns MHz
fPLL_OUT: 40 MHz to 200 MHz
fPLL_PFD: 8 MHz
fPLL_IN: ECO
For 10000 ns
Guaranteed by design
fPLL_VCO: 320 MHz or 400
SID345A1 PLL_LJIT5
Long term jitter
–0.75
–
–
0.75
ns MHz
fPLL_OUT: 40 MHz to 200 MHz
fPLL_PFD: 8 MHz
fPLL_IN: ECO
SID346
SID347
fPLL_IN
PLL input frequency
PLL operating current
(fOUT = 200 MHz)
3.988
–
33.34 MHz
IPLL_200M
0.87 1.85 mA fOUT = 200 MHz
SID348C fPLL_VCO
SID349C fPLL_PFD
VCO frequency
PFD frequency
170
3.988
–
–
400 MHz
8
MHz
PLL (with SSCG and fractional divider) specifications for 400 MHz
Time from stable
reference clock until PLL
SID340A tPLL400_LOCK
Time to achieve PLL lock
–
–
–
50
µs frequency is within 0.1%
of final value and lock
indicator is set
Programmed output
frequency from PLL Block
(spreading off)
SID341A fOUT
25
350 MHz Spreading off
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Electrical specifications
Table 27-25 PLL specifications (continued)
Spec ID
Parameter
Description
Min
25
0.5
–
Typ Max Units
Details/Conditions
Programmed output
frequency from PLL Block
(spreading on)
Spread spectrum
modulation depth
SID341B fOUT
–
–
–
340 MHz Spreading on
SID343A SPREAD_D
SID343B fSPREAD_MR
3
%
Downspread only,
triangle modulation
Spread spectrum
modulation rate
32
kHz Selected by modulation
divider from fPFD
For 125 ns
Guaranteed by design
fVCO: 800 MHz or 700 MHz
ns (spreading is off)
fIN: ECO
SID342D1 PLL400_LJIT1 Long term jitter
SID343D1 PLL400_LJIT2 Long term jitter
SID344D1 PLL400_LJIT3 Long term jitter
SID345E1 PLL400_LJIT5 Long term jitter
–0.25
–0.5
–1
–
–
–
–
0.25
0.5
1
fPFD: 4 MHz
fOUT: 100 MHz to 350 MHz
For 500 ns
Guaranteed by design
f
VCO: 800 MHz or 700 MHz
ns (spreading is off)
fIN: ECO
fPFD: 4 MHz
fOUT: 100 MHz to 350 MHz
For 1000 ns
Guaranteed by design
fVCO: 800 MHz or 700 MHz
ns (spreading is off)
fIN: ECO
fPFD: 4 MHz
fOUT: 100 MHz to 350 MHz
For 10000 ns
Guaranteed by design
fVCO: 800 MHz or 700 MHz
ns (spreading is off)
fIN: ECO
–1.5
1.5
fPFD: 4 MHz
fOUT: 100 MHz to 350 MHz
SID345A fVCO
SID346A fIN
VCO frequency
PLL input frequency
400
3.988
–
–
800 MHz
33.34 MHz
PLL operating current
(fOUT = 400 MHz)
SID347A IPLL_400M
SID348A fPFD_S
SID349A fPFD_F
–
3.988
8
1.4
–
2.2
mA fOUT = 400 MHz
PFD Frequency
20 MHz Spreading off/on
20 MHz Fractional operation
(fIN / Reference divider)
PFD Frequency
–
(fIN / Reference divider)
fPFD = 8 MHz,
fVCO = 400 MHz,
Output frequency from PLL
Block (spreading on)
fOUT = 100MHz,
SID341C fOUT_400_8S1
93
–
105 MHz
Modulation frequency:
fPFD / 512,
Modulation depth: 3%
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Electrical specifications
Table 27-25 PLL specifications (continued)
Spec ID
Parameter
Description
Min
Typ Max Units
Details/Conditions
fPFD = 8 MHz,
fVCO = 400 MHz,
fOUT = 100MHz,
Modulation frequency:
fPFD / 512,
tPLL_C-
JIT400_8S1
Cycle to cycle jitter
(spreading on)
SID342C
–710
–
–
–
710
ps
Modulation depth: 3%
fPFD = 8 MHz,
fVCO = 400 MHz,
fOUT = 100MHz,
Modulation frequency:
fPFD / 256,
Output frequency from PLL
Block (spreading on)
SID341D fOUT_400_8S2
93
105 MHz
Modulation depth: 3%
fPFD = 8 MHz,
fVCO = 400 MHz,
tPLL_C-
JIT400_8S2
Cycle to cycle jitter
(spreading on)
fOUT = 100MHz,
SID342D
–710
710
ps
Modulation frequency:
fPFD / 256,
Modulation depth: 3%
Table 27-26 FLL specifications
Spec ID Parameter
Description
Min
Typ
Max Units Details/Conditions
Wakeup with < 10 °C
temperature change
while in DeepSleep.
fFLL_IN = 8 MHz,
fFLL_OUT = 100 MHz,
SID350 tFLL_WAKE
FLL wake up time
–
–
5
µs
Time from stable
reference clock until
FLL frequency is
within 5% of final
value
Output frequency from FLL
block
Output range of FLL
divided-by-2 output
SID351 fFLL_OUT
24
–
100
MHz
This is added to the
error of the source
SID352 FLL_CJIT
SID353 fFLL_IN
FLL frequency accuracy
Input frequency
–1
–
–
1
%
0.25
80
MHz
Reference clock: IMO,
CCO frequency:
SID354 IFLL
FLL operating current
–
250
360
µA 200 MHz, FLL
frequency: 100 MHz,
guaranteed by design
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Electrical specifications
Table 27-27 WCO specifications
Spec ID
Parameter
Description
Crystal frequency
Min
–
Typ
32.768
–
Max Units Details/Conditions
Maximum drive level:
SID360 fWCO
–
kHz
%
0.5 µW
SID361 WCO_DC
WCO duty cycle
10
90
For Grade-S devices
Time from set
CTL.WCO_EN to 1
SID362 tSTART_WCO
WCO start up time[65]
WCO start-up time[65]
–
–
–
–
1000
1400
ms until
STATUS.WCO_OK is
set to 1. (See Clock
Timing Diagrams)
SID362E tSTART_WCOE
ms For Grade-E devices
Time from set
CTL.WCO_EN to 1
until
STATUS.WCO_OK is
set to 1. (See Clock
Timing Diagrams)
SID363 IWCO
WCO current
–
1.4
–
µA
VDDD
MCU
Rf
WCO_IN: Watch crystal oscillator input pin
WCO_OUT: Watch crystal oscillator output pin
C1, C2: Load Capacitors
WCO_IN
C3*, C4*: Stray Capacitance of the PCB
C1
C3*
VSSD
VSSD
C2
C4*
WCO_OUT
Rd
0R
Figure 27-23 WCO connection scheme[66]
Notes
65.Mainly depends on the external crystal.
66.Refer to the family-specific Architecture TRM for more information on crystal requirements (002-24401, TRAVEO™ T2G Automotive
MCU body controller high architecture technical reference manual).
Datasheet
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Electrical specifications
Table 27-28 External clock input specifications
Spec ID
SID366
SID367
Parameter
fEXT
EXT_DC
Description
Min
0.25
45
Typ Max Units Details/Conditions
For EXT_CLK pin (all
input level settings:
External clock input
frequency
–
–
80
55
MHz
%
CMOS, TTL,
Automotive)
External clock duty cycle
Table 27-29 MCWDT timeout specifications
Spec ID
Parameter
Description
Min
Typ Max Units Details/Conditions
When using the ILO
(32.768 kHz + 7%) and
SID410
tMCWDT1
Minimum MCWDT timeout
57
–
–
–
µs
s
16-bit MCWDT counter
Guaranteed by design
When using the ILO
(32.768 kHz – 7%) and
16-bit MCWDT counter
Guaranteed by design
SID411
tMCWDT2
Maximum MCWDT timeout
–
2.15
Table 27-30 WDT timeout specifications
Spec ID
Parameter
Description
Min
Typ
Max Units Details/Conditions
When using the ILO
(32.768 kHz + 7%) and
SID412 tWDT1
SID413 tWDT2
Minimum WDT timeout
57
–
–
µs
h
32-bit WDT counter,
guaranteed by design
When using the ILO
(32.768 kHz – 7%) and
32-bit WDT counter,
guaranteed by design
Maximum WDT timeout
Default WDT timeout
–
–
–
39.15
When using the ILO
and 32-bit WDT
SID414 tWDT3
1000
–
ms counter at 0x8000
(default value),
guaranteed by design
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Electrical specifications
27.12
Clock timing diagrams
ECO: 8 MHz
PLL: 160 MHz
FLL: 100 MHz
Active
CLK_ECO_CONFIG.ECO_EN
ECO_OUT
8 MHz
CLK_ECO_STATUS.ECO_READY
10 ms
CLK_PLL_CONFIG.ENABLE
CLK_PLL_STATUS.LOCKED
160 MHz
35 µs
PLL_OUTPUT
CLK_FLL_CONFIG.FLL_ENABLE
CCO is already up-and-running
CLK_FLL_STATUS.LOCKED
5 µs
100 MHz
FLL_OUTPUT
Figure 27-24 ECO to PLL or FLL diagram
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Electrical specifications
WCO: 32.768 kHz
FLL: 100 MHz
Active
CTL.WCO_EN
WCO_OUT
32.768 kHz
STATUS.WCO_OK
1000 ms
CLK_FLL_CONFIG.FLL_ENABLE
CLK_FLL_STATUS.LOCKED
CCO is already up-and-running
5 µs
100 MHz
FLL_OUTPUT
Figure 27-25 WCO to FLL diagram
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Based on Arm® Cortex®-M7 dual
Electrical specifications
27.13
Ethernet specifications
All specifications are valid for –40 °C TA 125 °C and for 2.7 V to 5.5 V except where noted.
Table 27-31 Ethernet specifications [Conditions: drive_sel<1:0>= 00]
Spec ID Parameter
Description
Min
Typ
Max Units Details/Conditions
Ethernet general specifications
SID368
SID369
SID370
fSYS
fAXI
VETH
System clock max frequency
AXI clock max frequency
Ethernet MAC IO supply voltage 3.0
–
–
–
–
–
100
200
3.6
MHz Guaranteed by design
MHz Guaranteed by design
V
For VDDD or VDDIO_4
For MDIO all signals
between MAC and
PHY using
SID364A CL_MD
SID364A1 CL_MH
SID364A2 CL_MG
Load capacitance
Load capacitance
Load capacitance
–
–
–
–
–
–
25
25
15
pF
GPIO_STD/HSIO_STD
For MII and RMII all
signals between MAC
and PHY using
pF
pF
pF
HSIO_STD
For MII and RMII all
signals between MAC
and PHY using
GPIO_STD
For GMII and RGMII all
signals between MAC
and PHY using
SID364B CL_GH
SID365A tRF
Load capacitance
–
–
–
–
10
2
HSIO_STD
20% to 80%, For MII,
Rise / fall time (For input pins)
ns RMII, and MDIO using
GPIO_STD/HSIO_STD
Rise / fall time (For input and
output pins)
Rise / fall time (For input and
output pins)
20% to 80%, For GMII
SID365B tRF_G
SID365B1 tRF_GM
–
–
–
–
1
ns
using HSIO_STD
20%to80%, ForRGMII
0.75
ns
using HSIO_STD
Ethernet MII specifications for GPIO_STD/HSIO_STD
–
100pp
m
MII TX/RX_CLK clock frequency
100pp
m
SID375
fTXRX_CLK
25
MHz
at 100 Mbps
DUTY_TX-
RX_CLK
SID376
SID372
SID373
SID374
TX/RX clock duty cycle
35
0.5
10
10
–
–
–
–
65
25
–
%
ns
ns
ns
MII Transmit data (TX_CTL, TXD,
TX_ER) valid after TX_CLK
MII Receive data setup to
RX_CLK rising edge
MII Receive data hold to RX_CLK
rising edge
tSKEWT
tSUR
tHOLDR
–
Ethernet RMII Specifications for GPIO_STD/HSIO_STD
–
50pp
m
RMII reference clock frequency
50pp
m
SID375A fREF_CLK
(input)
50
MHz External clock
DUTY_REF_ Duty cycle of reference clock
SID376A
35
4
–
–
65
–
%
CLK
tSU
(input)
RX_CTL, RXD[1:0], RX_ER data
setup to REF_CLK rising edge
SID377
ns
Datasheet
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Electrical specifications
Table 27-31 Ethernet specifications [Conditions: drive_sel<1:0>= 00] (continued)
Spec ID Parameter
Description
Min
Typ
Max Units Details/Conditions
RX_CTL, RXD[1:0], RX_ER, data
hold from REF_CLK rising edge
TX_CTL, TXD[1:0], data output
delay from REF_CLK rising edge
TX_CTL, TXD[1:0], data output
delay from REF_CLK rising edge
SID378
SID393
tHOLD
2
–
–
ns
tTXOUT
2
2
–
–
14.6
14
ns For GPIO_STD
ns For HSIO_STD
SID393A tTXOUT_A
Ethernet GMII Specifications for HSIO_STD
SID379
fP_REFCLK
REF_CLK clock frequency
RX_CLK clock frequency
RX_CLK clock period
–
125
125
–
MHz
MHz
–
50pp
m
7.5
2.5
–
50pp
m
SID380
fP_RXCLK
SID380A tP_RXCLK
SID380B tP_HL_RXCLK RX_CLK clock time HIGH/LOW
–
–
8.5
–
ns
ns
TX(GTX)_CLK frequency
100pp
m
SID389
fP_TXCLK
100pp 125
m
MHz
ns
(External/Internal mode)
TX(GTX)_CLK clock period
(External/Internal mode)
TX(GTX)_CLK clock time
SID389A tP_TXCLK
7.5
–
8.5
–
SID389B tP_HL_TXCLK HIGH/LOW (External/Internal
mode)
2.5
–
ns
TX_CTL, TXD, TX_ER Setup to
SID381
SID382
SID383
SID384
tSETUPT
tHOLDT
tSETUPR
tHOLDR
2.5
0.5
2
–
–
–
–
–
–
–
–
ns
ns
ns
ns
TX(GTX)_CLK rising edge
TX_CTL, TXD, TX_ER hold from
TX(GTX)_CLK rising edge
RX_CTL, RXD, RX_ER setup to
RX_CLK rising edge
RX_CTL, RXD, RX_ER hold from
RX_CLK rising edge
0
Ethernet RGMII Specifications for HSIO_STD
SID385
fCYC
REF_CLK clock frequency
–
125
125
–
MHz
MHz
TX(TXC)_CLK (External mode)
and RX(RXC)_CLK clock
frequency
TX(TXC)_CLK (External
mode)/RX(RXC)_CLK clock
period
–
50pp
m
50pp
m
SID385_1 fP_TXCRXC
SID385B tP_TXCRXC
7.2
8
–
8.8
ns
%
DUTY_TXC Duty for TX(TXC)_CLK (External
SID386B
45
55
RXC
tSKEWT
tSKEWR
mode)/RX(RXC)_CLK clock
Data to clock output skew
Data to clock input skew
SID387
SID388
–0.5
1
–
–
0.5
2.6
ns
ns
Ethernet MDIO Specifications for GPIO_STD/HSIO_STD
SID395
tMDCYC
MDC clock cycle
The minimum HIGH and LOW
times for MDC
400
160
–
–
–
–
ns
ns
SID395A tHL_MDCYC
MDIO input setup time to MDC
rising edge
SID396
tMDIS
100
–
–
ns
Datasheet
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Electrical specifications
Table 27-31 Ethernet specifications [Conditions: drive_sel<1:0>= 00] (continued)
Spec ID Parameter
Description
Min
Typ
Max Units Details/Conditions
MDIO input hold time to MDC
rising edge
MDIO output skew from MDC
rising edge
SID397
SID398
tMDIH
tMDIO
0
–
–
ns
ns
10
–
390
1
2.0 V
RX_CLK
0.8 V
2
3
RXD, RX_CTL,
RX_ER
2.0 V
0.8 V
2.0 V
0.8 V
TX_CLK
4
2.0 V
0.8 V
TXD, TX_CTL,
TX_ER
1: RX_CLK or TX_CLK cycle = 1/fTXRX_CLK
2: MII receive data setup time to RX_CLK rising edge = tSUR
3: MII receive data hold time to RX_CLK rising edge = tHOLDR
4: MII transmit data valid after TX_CLK rising edge = tSKEWT
Figure 27-26 MII timing diagram
Datasheet
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Electrical specifications
1
2.0 V
MDC
0.8 V
2
3
MDIO
2.0 V
0.8 V
2.0 V
0.8 V
MDC
4
2.0 V
0.8 V
MDIO
1: MDC clock cycle = tMDCCYC
2: MDIO input setup time to MDC rising edge = tMDIS
3: MDIO input hold time tp MDC rising edge = tMDIH
4: MDIO output skew from MDC rising edge = tMDIO
Figure 27-27 MDIO timing diagram
1
REF_CLK
1.4 V
2
3
2.0 V
0.8 V
RXD, RX_CTL,
RX_ER
4
2.0 V
0.8 V
TXD, TX_CTL
1: RMII reference clock cycle = 1/fREF_CLK
2: Data setup to REF_CLK rising edge = tSU
3: Data hold from REF_CLK rising edge = tHOLD
4: Data output delay from REF_CLK_rising edge = tTXOUT
Figure 27-28 RMII timing diagram
Datasheet
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Electrical specifications
1
1.9 V
TX_CLK or
RX_CLK
0.7 V
2
3
TXD, TX_CTL,
TX_ER or RXD,
RX_CTL,
1.9 V
0.7 V
RX_ER
1: TX_CLK or RX_CLK cycle = tP_TXCLK = tP_RXCLK
2: Data setup to TX_CLK or RX_CLK rising edge = tSETUPT or tSETUPR
3: Data hold from TX_CLK or RX_CLK rising edge = tHOLDT or tHOLDR
Figure 27-29 GMII timing diagram
1
100 %
RX_CLK,
TX_CLK
50 %
0 %
TX_CTL,
RX_CTL, TXD,
RXD
100 %
50 %
0 %
2
2
2
2
1: TX_CLK and RX_CLK clock cycle = 1/fCYC
2: Data to clock output skew = tSKEWT
Figure 27-30 RGMII Tx timing diagram
1
100 %
RX_CLK,
TX_CLK
50 %
0 %
TX_CTL,
RX_CTL, TXD,
RXD
100 %
50 %
0 %
2 2
2 2
1: TX_CLK and RX_CLK clock cycle = 1/fCYC
2: Data to clock input skew = tSKEWR
Figure 27-31 RGMII Rx timing diagram
Datasheet
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Electrical specifications
27.14
SDHC specifications
All specifications are valid for –40 °C TA 125 °C and for 2.7 V to 5.5 V except where noted.
Table 27-32 SDHC specifications
Spec ID Parameter
Description
Min Typ Max Units Details/Conditions
SDHC and eMMC specifications (the source clock must be divided by 2 or more in DDR modes)
SID801
SID802
SID803
VSDHC
IODS
tIT
SDHC IO supply voltage
I/O drive select
2.7
8
–
–
–
3.6
8
V
For VDDIO_1 or VDDIO_3
drive_sel<1:0>= 0b00
for all modes
mA
ns
Input transition time
0.7
3
SD: DS timing specifications for GPIO_STD/HSIO_STD
SID810
SID812
SID813
fLP
CD
CC
Interface clock period
–
–
–
–
25
40
40
MHz 40-ns period
I/O loading at DATA/CMD pins
I/O loading at CLK pins
40
40
pF
pF
Output setup time of CMD/DAT
prior to CLK
SID814
SID815
SID816
SID818
tOS
5.5
5.5
24
0
–
–
–
–
–
–
–
–
ns
ns
Output hold time of CMD/DAT
after CLK
tOH
tIS_LP
tIH
Input setup time of CMD/DAT
prior to CLK
Clock period - Output
delay
ns
ns
Input hold time of CMD/DAT
after CLK
SD: HS timing specifications for HSIO_STD
SID820
SID822
SID823
fLP_SD_HS
CD_SD_HS
CC_SD_HS
Interface clock period
–
–
–
–
50
40
40
MHz 20-ns period
I/O loading at DATA/CMD pins
I/O loading at CLK pins
40
40
pF
pF
Output setup time of CMD/DAT
prior to CLK
SID824
SID825
SID826
SID828
tOS_SD_HS
tOH_SD_HS
tIS_LP_SD_HS
tIH_SD_HS
6.5
2.5
4
–
–
–
–
–
–
–
–
ns
ns
Output hold time of CMD/DAT
after CLK
Input setup time of CMD/DAT
prior to CLK
Clock period less
output delay
ns
ns
Input hold time of CMD/DAT
after CLK
2.5
eMMC: BWC timing specifications for GPIO_STD/HSIO_STD
fLP_eM-
SID870
SID872
SID873
SID874
SID875
Interface clock period
–
–
–
–
–
–
26
30
30
–
MHz 38.4-ns period
MC_BWC
CD_eM-
MC_BWC
CC_eM-
MC_BWC
tOS_eM-
MC_BWC
tOH_eM-
MC_BWC
I/O loading at DATA/CMD pins
I/O loading at CLK pins
30
30
3.5
3.5
pF
pF
ns
ns
Output setup time of CMD/DAT
prior to CLK
Output hold time of CMD/DAT
after CLK
–
Datasheet
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Electrical specifications
Table 27-32 SDHC specifications (continued)
Spec ID Parameter
Description
Min Typ Max Units Details/Conditions
tIS_LP_eM-
SID876
Input setup time of CMD/DAT
prior to CLK
Clock period less
9.7
8.3
–
–
–
–
ns
ns
output delay
MC_BWC
tIH_eM-
SID878
Input hold time of CMD/DAT
after CLK
MC_BWC
eMMC: SDR timing specifications for HSIO_STD
fLP_eM-
SID880
SID882
SID883
SID884
SID885
SID886
SID888
Interface clock period
–
–
–
–
–
–
–
–
52
30
30
–
MHz 19.2-ns period
MC_SDR
CD_eM-
MC_SDR
CC_eM-
MC_SDR
tOS_eM-
MC_SDR
tOH_eM-
MC_SDR
tIS_LP_eM-
MC_SDR
tIH_eM-
MC_SDR
I/O loading at DATA/CMD pins
I/O loading at CLK pins
30
pF
pF
ns
ns
30
Output setup time of CMD/DAT
prior to CLK
3.5
3.5
3.5
2.5
Output hold time of CMD/DAT
after CLK
–
Input setup time of CMD/DAT
prior to CLK
Clock period less
–
ns
output delay
Input hold time of CMD/DAT
after CLK
–
ns
eMMC: DDR timing specifications for HSIO_STD
fLP_eM-
MC_DDR
SID890
Interface clock period
–
–
–
52
55
MHz 19.2-ns period
%
DUTY_-
CLK_eM-
SID892
Duty cycle of output CLK
45
MC_DDR
CD_eM-
MC_DDR
CC_eM-
MC_DDR
tOS_eM-
MC_DDR
tOH_eM-
MC_DDR
tIS_LP_eM-
MC_DDR
tIH_eM-
MC_DDR
SID893
SID894
SID895
SID896
SID897
SID899
I/O loading at DATA/CMD pins
I/O loading at CLK pins
20
20
–
–
–
–
–
–
20
20
–
pF
pF
ns
ns
Output setup time of CMD/DAT
prior to CLK
2.6
2.6
2.4
1.5
Output hold time of CMD/DAT
after CLK
–
Input setup time of CMD/DAT
prior to CLK
Clock period less
–
ns
output delay
Input hold time of CMD/DAT
after CLK
–
ns
Datasheet
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Electrical specifications
Input Timing for SD: DS
1
VDDIO_1
or VDDIO_3
0.5 x VDDIO_1
or VDDIO_3
CLK
VSSD or VSSIO_3
3
2
0.5 x VDDIO_1
or VDDIO_3
CMD/DAT
Invalid
Valid
1: Clock period = 1/fLP
2: Input setup time = tIS_LP
3: Input hold time = tIH
Figure 27-32 SD default speed input timing
Output Timing for SD: DS
1
VDDIO_1
or
VDDIO_3
0.5 x VDDIO_1
or VDDIO_3
CLK
VSSD or VSSIO_3
2
3
0.5 x VDDIO_1
or VDDIO_3
CMD/DAT
Invalid
Valid
Invalid
1: Clock period = 1/fLP
2: Output setup time = tOS
3: Output hold time = tOH
Figure 27-33 SD default speed output timing
Datasheet
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Electrical specifications
Input Timing for SD: HS and eMMC: BWC/SDR
1
VDDIO_1
or VDDIO_3
0.5 x VDDIO_1
or VDDIO_3
CLK
VSSD or VSSIO_3
3
2
0.5 x VDDIO_1
or VDDIO_3
CMD/DAT
Invalid
Valid
1: Clock period = 1/fLP_SD_HS or 1/fLP_eMMC_BWC or 1/fLP_eMMC_SDR
2: Input setup time = tIS_LP_SD_HS or tIS_LP_eMMC_BWC or tIS_LP_eMMC_SDR
3: Input hold time = tIH_SD_HS or tIH_eMMC_BWC or tIH_eMMC_SDR
Figure 27-34 SD high-speed and eMMC BWC/SDR input timing
Output Timing for SD: HS and eMMC: BWC/SDR
1
VDDIO_1
or
VDDIO_3
0.5 x VDDIO_1
or VDDIO_3
CLK
VSSD or VSSIO_3
2
3
0.5 x VDDIO_1
or VDDIO_3
CMD/DAT
Invalid
Valid
Invalid
1: Clock period = 1/fLP_SD_HS or 1/fLP_eMMC_BWC or 1/fLP_eMMC_SDR
2: Output setup time = tOS_SD_HS or tOS_eMMC_BWC or tOS_eMMC_SDR
3: Output hold time = tOH_SD_HS or tOH_eMMC_BWC or tOH_eMMC_SDR
Figure 27-35 SD high-speed and eMMC BWC/SDR output timing
Datasheet
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Electrical specifications
Input Timing for eMMC: DDR
1
VDDIO_3
0.5 x VDDIO_3
CLK
VSSIO_3
2
3
2
3
CMD/DAT
Valid
Valid
0.5 x VDDIO_3
1: Clock period = 1/fLP_eMMC_DDR
2: Input setup time = tIS_LP_eMMC_DDR
3: Input hold time = tIH_eMMC_DDR
Figure 27-36 eMMC DDR input timing
Output Timing for eMMC: DDR
1
VDDIO_3
0.5 x VDDIO_3
CLK
VSSIO_3
2
3
2
3
0.5 x VDDIO_3
CMD/DAT
Valid
Valid
1: Clock period = 1/fLP_eMMC_DDR
2: Output setup time = tOS_LP_eMMC_DDR
3: Output hold time = tOH_eMMC_DDR
Figure 27-37 eMMC DDR output timing
Datasheet
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Electrical specifications
27.15
FlexRay specifications
All specifications are valid for –40 °C TA 125 °C and for 2.7 V to 5.5 V except where noted.
Table 27-33 FlexRay specification
Spec ID
Parameter
Description
Min
Typ
Max
Units
Details/Conditions
Guaranteed by design,
Reference clock: ECO
Guaranteed by design,
Reference clock: ECO
SID465
f
f
System clock (clk_sys) frequency
–
–
80
MHz
CLK_S
FlexRay clock (clk_peri)
frequency
SID466
SID470
–
–
–
80
MHz
V
CLK_P
FlexRay I/O supply voltage
V
3.0
5.5
drive_sel<1:0> = 0b00
FR
(V
)
DDIO_2
TxEN output characteristics
SID450
SID451
t
t
Rise time of TxEN signal at CC
Fall time of TxEN signal at CC
–
–
–
–
9
9
ns
ns
20% to 80%, 25-pF load
20% to 80%, 25-pF load
CCTxENRISE25
CCTxENFALL25
Sum of delay between TP1_FF
and TP1_CC and delays derived
from TP1_FFi, rising edge TxEN
Sum of delay between TP1_FF
and TP1_CC and delays derived
from TP1_FFi, falling edge TxEN
20% to 80%, 25-pF load,
guaranteed by design
SID452
t
t
–
–
25
ns
CCTxEN01
CCTxEN10
20% to 80%, 25-pF load,
guaranteed by design
SID453
SID468
–
–
–
–
25
25
ns
pF
C
I/O loading at TxEN pin
TXEN
TxD output characteristics
Asymmetry of sending CC
25-pF load, guaranteed
by design
SID454
t
–2.45
–
2.45
ns
CCTxASYM
(= t
50% – 100 ns)
CCDTxD
SID455
t
t
t
Sum of rise and fall time
Rise time of TxD signal
Fall time of TxD signal
–
–
–
–
–
–
9
ns
ns
ns
20% to 80%, 25-pF load
30% to 70%, 15-pF load
30% to 70%, 15-pF load
CCTxDRF25
CCTxDR15
CCTxDF15
SID455A
SID455B
2.5
2.5
Sum of delay between clock to Q
of the last FF and the final output
buffer, rising edge TxD
Sum of delay between clock to Q
of the last FF and the final output
buffer, falling edge TxD
20% to 80%, 25-pF load,
guaranteed by design
SID456
t
t
–
–
25
ns
CCTxD01
CCTxD10
20% to 80%, 25-pF load,
guaranteed by design
SID457
SID469
–
–
–
–
25
25
ns
pF
C
I/O loading at TxD pin
TXD
RxD input characteristics
SID458
C
Input capacitance on RxD pin
–
–
–
10
pF
V
CCRxD
Threshold for detecting logical
HIGH
Threshold for detecting logical
LOW
Sum of delay from actual input to
the D input of the first FF, rising
edge RxD
Sum of delay from actual input to
the D input of the first FF, falling
edge RxD
0.35 ×
DDIO_2
0.70 ×
SID459
V
V
CCLogic_1
V
V
DDIO_2
0.30 ×
DDIO_2
0.65 ×
SID460
SID461
–
–
V
CCLogic_0
CCRxD01
V
V
DDIO_2
t
t
–
10
ns
Guaranteed by design
Guaranteed by design
SID462
–
–
10
ns
CCRxD10
Receiver asymmetry
For all data rates
includingclockdeviation
of ±500 ppm
For all data rates
includingclockdeviation
of ±500 ppm
Acceptance of asymmetry at
receiving CC with 15-pF load
SID463
SID464
t
t
–31.5
–30.5
–
–
44
43
ns
ns
CCRxASYMAC15
CCRxASYMAC25
Acceptance of asymmetry at
receiving CC with 25-pF load
Datasheet
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Electrical specifications
27.16
Audio subsystem specifications
All specifications are valid for –40 °C TA 125 °C and for 2.7 V to 5.5 V except where noted.
Table 27-34 Audio subsystem specifications
Details/
Spec ID Parameter
SID770 fAUDIO
Description
Min
–
Typ
–
Max
200
3.6
Units
MHz
V
Conditions
Guaranteed by
design
Audio subsystem frequency
Audio subsystem I/O supply
voltage
SID772 VAUDIO
3.0
–
For VDDIO_2
drive_sel<1:0>=
0b0X, Pull-up,
pull-down: off
SID773 VOL_A
SID774 VOH_A
Output voltage LOW level
Output voltage HIGH level
–
–
–
0.4
–
V
V
drive_sel<1:0>=
0b0X, Pull-up,
pull-down: off
VDDIO_2 – 0.5
Input voltage HIGH
SID775 VIH_CMOS_A
SID776 VIL_CMOS_A
0.7 × VDDIO_2
–
–
–
–
V
V
threshold in CMOS mode
Input voltage LOW
threshold in CMOS mode
0.3 × VDDIO_2
I2S/TDM word clock frequency
Guaranteed by
design
SID796 fWS_I2S
SID797 fWS_TDM
WS clock rate in I2S mode
8
–
8
–
–
–
192
96
kHz
kHz
bit
Guaranteed by
design
WS clock rate in TDM mode
Length of I2S word
Guaranteed by
design
SID798 Word
32
I2S/TDM Master mode
Except TDM 96 kHz
mode, TX/RX_WS
output and
Delay Time of TX/RX_WS
Output Transition from
Falling Edge of TX/RX_SCK
Output
TX/RX_SCK output
with
SID740 tD_WS
–8
–8
–
–
9
ns
ns
drive_sel<1:0> = 0b
01, guaranteed by
design
TDM 96 kHz mode,
TX/RX_WS output
with
drive_sel<1:0> =
0b01 and
TX/RX_SCK output
with
Delay Time of TX/RX_WS
output Transition from
Falling Edge of TX/RX_SCK
output
SID740A tD_WS_TDM96A
11
drive_sel<1:0> =
0b00, guaranteed
by design
Datasheet
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Electrical specifications
Table 27-34 Audio subsystem specifications (continued)
Details/
Spec ID Parameter
Description
Min
Typ
Max
Units
Conditions
TX_SDO and
TX_SCK output
with
drive_sel<1:0> =
0b01 for except
TDM 96 kHz mode,
guaranteed by
design
Delay Time of TX_SDO
Transition from Falling Edge
of TX_SCK Output
SID741 tD_SDO
–8
–
8
ns
TX_SDO with
drive_sel<1:0> =
0b01 and TX_SCK
output with
Delay time of TX_SDO
SID741A tD_SDO_TDM96 Transition from Falling Edge
of TX_SCK Output
–8
–
8
ns drive_sel<1:0> =
0b00 for TDM
96 kHz mode,
guaranteed by
design
RX_SCK output
with
ns drive_sel<1:0> =
0b00, guaranteed
by design
RX_SDI setup time to the
following rising edge of
SID742 tS_SDI
11
tMCLK_SOC – 0.9
11
–
–
–
–
–
–
–
RX_SCK output
(RX_CTL.B_CLOCK_INV = 0)
RX_SCK output
with
ns drive_sel<1:0> =
0b00, guaranteed
by design
RX_SDI hold time to the
rising edge of RX_SCK
SID743 tH_SDI
output
(RX_CTL.B_CLOCK_INV = 0)
RX_SCK output
with
ns drive_sel<1:0> =
0b00, guaranteed
by design
RX_SDI setup time to the
following falling edge of
SID744 tS_SDI1
RX_SCK output
(RX_CTL.B_CLOCK_INV = 1)
RX_SCK output
with
ns drive_sel<1:0> =
0b00, guaranteed
by design
RX_SDI hold time to the
falling edge of RX_SCK
t
–
MCLK_SOC
SID745 tH_SDI1
–
0.9
output
(RX_CTL.B_CLOCK_INV = 1)
TX/RX_SCK output bit clock
Guaranteed by
SID746 tSCKCY
duty cycle
45
–
–
55
%
design
Internal Fractional
196.608 MHz PLL, guaranteed by
design
SID748 fMCLK_SOC
MCLK input clock frequency
1.024
SID748A fMCLK_SOC_E MCLK input clock frequency
1.024
5.086
–
–
98.304
MHz External clock
Guaranteed by
design
SID749 tMCLK_SOC
SID750 tJITTER
MCLK input clock period
976.563
ns
MCLK Input clock jitter
tolerance
Guaranteed by
design
–200
–
200
ps
Datasheet
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Electrical specifications
Table 27-34 Audio subsystem specifications (continued)
Details/
Spec ID Parameter
Description
Min
Typ
Max
Units
Conditions
MCLK output with
drive_sel<1:0> =
0b00, Guaranteed
by design
MCLK output clock
frequency
SID748B fMCLK
1.024
–
25
MHz
MCLK output with
drive_sel<1:0> =
0b01, Guaranteed
by design
MCLK output clock
frequency
SID748C fMCLK1
1.024
45
–
–
15
55
MHz
%
Guaranteed by
design
SID749B fMCLK_DT
MCLK output clock duty
I2S/TDM Slave mode
TX/RX_WS input alignment
clock setup time to the
following rising edge of
TX/RX_SCK input
TX/RX_WS input alignment
clock hold time to the rising
edge of TX/RX_SCK Input
Guaranteed by
design
SID751 tS_WS
SID752 tH_WS
SID753 tD_SDO
5
–
–
–
–
ns
ns
ns
Guaranteed by
design
tMCLK_SOC + 5.0
–
Delay time of TX_SDO
transition from falling edge
of TX_SCK input
TX_SDO with
drive_sel<1:0>=
0b00, guaranteed
by design
tMCLK_SOC + 15
–tMCLK_SOC + 5.0
(TX_CTL.B_CLOCK_INV = 0)
Delay time of TX_SDO
transition from rising edge
of TX_SCK input
TX_SDO with
drive_sel<1:0>=
0b00, guaranteed
by design
SID754 tD_SDO1
SID755 tS_SDI
tMCLK_SOC + 15
–tMCLK_SOC + 5.0
–
–
ns
ns
(TX_CTL.B_CLOCK_INV = 1)
RX_SDI setup time to the
following rising edge of
RX_SCK input
Guaranteed by
design
5
–
RX_SDI hold time to the
Guaranteed by
design
SID756 tH_SDI
SID757 tSCKCY
tMCLK_SOC + 5.0
–
–
–
ns
%
rising edge of RX_SCK input
TX/RX_SCK input bit clock
duty cycle
Guaranteed by
design
45
55
Datasheet
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Electrical specifications
I2S/TDM Master Mode: Output Delay Timing
VDDIO_2
TX/RX_SCK
or TX_SCK
output
0.5 x VDDIO_2
VSSD
1
VDDIO_2
TX/RX_WS
or TX_SDO
output
0.5 x VDDIO_2
VSSD
1: Delay time = tD_WS or tD_WS_TDM96A or tD_SDO or tD_SDO_TDM96
Figure 27-38 Master output delay
I2S/TDM Master Mode: Setup Timing
(RX_CTL.B_CLOCK_INV = 0)
VDDIO_2
RX_SCK
output
0.5 x VDDIO_2
VSSD
1
2
VDDIO_2
RX_SDI
input
0.5 x VDDIO_2
VSSD
1: Setup time = tS_SDI
2: Hold time = tH_SDI
Figure 27-39 Master setup without clock inversion
Datasheet
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Electrical specifications
I2S/TDM Master Mode: Setup Timing
(RX_CTL.B_CLOCK_INV = 1)
VDDIO_2
RX_SCK
output
0.5 x VDDIO_2
VSSD
1
2
VDDIO_2
RX_SDI
input
0.5 x VDDIO_2
VSSD
1: Setup time = tS_SDI1
2: Hold time = tH_SDI1
Figure 27-40 Master setup with clock inversion
I2S/TDM Slave Mode: Output Delay Timing
VDDIO_2
TX_SCK input
(TX_CTL.B_CLOCK_INV = 0)
0.5 x VDDIO_2
VSSD
VDDIO_2
TX_SCK input
(TX_CTL.B_CLOCK_INV = 1)
0.5 x VDDIO_2
VSSD
1
VDDIO_2
TX_SDO output
0.5 x VDDIO_2
VSSD
1: Delay time = tD_SDO or tD_SDO1
Figure 27-41 Slave output delay
Datasheet
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Electrical specifications
I2S/TDM Slave Mode: Setup Timing
VDDIO_2
TX/RX_SCK
or RX_SCK
input
0.5 x VDDIO_2
VSSD
1
2
VDDIO_2
TX/RX_WS
or RX_SDI
input
0.5 x VDDIO_2
VSSD
1: Setup time = tS_WS or tS_SDI
2: Hold time = tH_WS or tH_SDI
Figure 27-42 Slave setup
Datasheet
189
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Electrical specifications
27.17
Serial memory interface specifications
All specifications are valid for –40 °C TA 125 °C and for 2.7 V to 5.5 V except where noted.
Table 27-35 SMIF specifications [Conditions: drive_sel<1:0>= 00]
Details/
Spec ID
SMIF DC specification
SID785 VSMIF
Parameter
Description
Min
Typ Max Units
Conditions
For VDDIO_1 or
VDDIO_3
SMIF I/O supply voltage
2.7
–
3.6
V
SMIF HSSPI(SDR) specification for HSIO_STD
SID760
CL_SDR_HSIO
SR_SDR_HSIO
fCK_SDR_HSIO
tCK_SDR_HSIO
Load capacitance
–
1.5
-
–
–
30
–
pF
Guaranteed by
design
SID761
Input rise and fall slew rates
V/ns
SID762
SID763
SID764
SID765
SID766
SID767
SID768
SID769
SID780
SID781
SID782
Clock frequency
Clock period
–
–
–
–
–
–
–
–
–
–
–
100 MHz
1 / f
–
55
–
–
–
–
–
–
7.65
–
ns
%
V/ns
ns
ns
ns
ns
ns
ns
ns
CK_SDR_HSIO
DCK_SDR_HSIO Clock duty
45
CSR_SDR_HSIO
tCS_SDR_HSIO
tCSS_SDR_HSIO
tCSH_SDR_HSIO
tSU_SDR_HSIO
tHD_SDR_HSIO
tV_SDR_HSIO
Clock rise and fall slew rates
1.5
10
3
5
1.5
2
Chip select HIGH time
Chip select active setup time
Chip select active hold time
Data setup time
Data hold time
Clock LOW output valid
Input hold time
1.5
2
tHO_SDR_HSIO
Guaranteed by
design
Guaranteed by
design
SID783
SID784
tDIS_SDR_HSIO
Input disable time
0
–
–
–
7.5
0.6
ns
ns
tIO_SKEW_S-
DR_HSIO
Data skew (first data bit to
last data bit)
SMIF HSSPI(SDR) Specification for GPIO_STD
SID760A CL_SDR_GPIO
Load capacitance
–
1
–
–
–
30
–
pF
Guaranteed by
design
SID761A SR_SDR_GPIO
Input rise and fall slew rates
V/ns
SID762A fCK_SDR_GPIO
SID763A tCK_SDR_GPIO
SID764A DCK_SDR_GPIO Clock duty
Clock frequency
Clock period
–
–
–
–
–
–
–
–
–
–
–
32
–
55
–
–
–
–
–
–
9
MHz
ns
%
V/ns
ns
ns
ns
ns
ns
ns
1 / f
CK_SDR_GPIO
45
SID765A CSR_SDR_GPIO
SID766A tCS_SDR_GPIO
SID767A tCSS_SDR_GPIO
SID768A tCSH_SDR_GPIO
SID769A tSU_SDR_GPIO
SID780A tHD_SDR_GPIO
SID781A tV_SDR_GPIO
SID782A tHO_SDR_GPIO
Clock rise and fall slew rates
1
30
9
15
4.5
6
Chip select HIGH time
Chip select active setup time
Chip select active hold time
Data setup time
Data hold time
Clock LOW output valid
Input hold time
4.5
2
–
ns
Guaranteed by
design
SID783A tDIS_SDR_GPIO
Input disable time
0
–
22.5
ns
Datasheet
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Electrical specifications
Table 27-35 SMIF specifications (continued)[Conditions: drive_sel<1:0>= 00]
Details/
Spec ID
Parameter
Description
Min
Typ Max Units
Conditions
tIO_SKEW_S-
DR_GPIO
Data skew (first data bit to
last data bit)
Guaranteed by
design
SID784A
–
–
1.8
ns
SMIF HSSPI(DDR) specification for HSIO_STD
SID760B CL_DDR_HSIO
Load capacitance
–
1.5
-
–
–
15
-
pF
Guaranteed by
design
SID761B SR_DDR_HSIO
Input rise and fall slew rates
V/ns
SID762B2 fCK_DDR_HSIO
SID763B tCK_DDR_HSIO
SID764B DCK_DDR_HSIO Clock duty
SID765B CSR_DDR_HSIO Clock rise and fall slew rates
SID766B tCS_DDR_HSIO
SID767B tCSS_DDR_HSIO
Clock frequency
Clock period
–
–
–
–
–
–
–
–
–
–
–
90
–
55
–
–
–
–
–
–
6.5
–
MHz
ns
%
V/ns
ns
ns
ns
ns
ns
ns
1 / f
CK_DDR_HSIO
45
1.5
10
4
4
2
1.2
0
1
Chip select HIGH time
Chip select active setup time
SID768B tCSH_DDR_HSIO Chip select active hold time
SID769B tSU_DDR_HSIO
SID780B tHD_DDR_HSIO
SID781B tV_DDR_HSIO
SID782B tHO_DDR_HSIO
Data setup time
Data hold time
Clock LOW output valid
Input hold time
ns
Guaranteed by
design
Guaranteed by
design
SID783B tDIS_DDR_HSIO
Input disable time
–
–
–
–
7.5
0.6
ns
ns
tIO_SKEW_D-
SID784B
Data skew (first data bit to
last data bit)
DR_HSIO
SMIF HSSPI(DDR) specification for GPIO_STD
SID760C CL_DDR_GPIO
Load capacitance
–
1
–
–
–
15
–
pF
Guaranteed by
design
SID761C SR_DDR_GPIO
Input rise and fall slew rates
V/ns
SID762C fCK_DDR_GPIO
SID763C tCK_DDR_GPIO
SID764C DCK_DDR_GPIO Clock duty
SID765C CSR_DDR_GPIO Clock rise and fall slew rates
SID766C tCS_DDR_GPIO
SID767C tCSS_DDR_GPIO
Clock frequency
Clock period
–
–
–
–
–
–
–
–
–
–
–
32
-
55
–
–
–
–
–
–
9
MHz
ns
%
V/ns
ns
ns
ns
ns
ns
ns
1 / f
CK_DDR_GPIO
45
1
30
5
4
5
4.5
0
3
Chip select HIGH time
Chip select active setup time
SID768C tCSH_DDR_GPIO Chip select active hold time
SID769C tSU_DDR_GPIO
SID780C tHD_DDR_GPIO
SID781C tV_DDR_GPIO
SID782C tHO_DDR_GPIO
Data setup time
Data hold time
Clock LOW output valid
Input hold time
–
ns
Guaranteed by
design
Guaranteed by
design
SID783C tDIS_DDR_GPIO
Input disable time
–
–
–
–
22.5
1.8
ns
ns
tIO_SKEW_D-
SID784C
Data skew (first data bit to
last data bit)
DR_GPIO
SMIF HYPERBUS™ specification for HSIO_STD
SID788
CL_HB_HSIO
Load capacitance
–
–
20
pF
Datasheet
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Electrical specifications
Table 27-35 SMIF specifications (continued)[Conditions: drive_sel<1:0>= 00]
Details/
Spec ID
SID786
SID787
Parameter
Description
Min
Typ Max Units
Conditions
For all signals,
V/ns guaranteed by
design
SRI_HB_HSIO Input rise and fall slew rates
1
–
–
–
–
Output rise and fall slew
SRO_HB_HSIO
1
V/ns For all signals
rates
Clock characteristics
SID700
SID701
SID702
fCK_HB_HSIO
Clock frequency
Clock period
–
–
–
–
100 MHz
1 / fCK_H-
B_HSIO
45
tCK_HB_HSIO
–
ns
%
DCK_HB_HSIO Clock duty
55
AC parameters
Chip select HIGH between
transactions
Chip select setup to next CK
rising edge
Guaranteed by
design
SID706
SID708
tCSHI_HB_HSIO
10
3
–
–
–
–
ns
ns
tCSS_HB_HSIO
SID709
SID710
SID711
SID715
SID718
tDSV_HB_HSIO
tOSU_HB_HSIO
tOH_HB_HSIO
tCKD_HB_HSIO
Data strobe valid
DQ output setup
DQ output hold
–
1
1
1
1
–
–
–
–
–
12
–
–
5.5
5.5
ns
ns
ns
ns
ns
CK transition to DQ valid
tCKDS_HB_HSIO CK transition to RWDS valid
RWDS transition to input DQ
SID719
SID720
SID721
tDSS_HB_HSIO
–0.8
–0.8
0
–
–
–
0.8
0.8
-
ns
ns
ns
valid
Input DQ invalid to RWDS
transition
tDSH_HB_HSIO
Chip select hold after CK
tCSH_HB_HSIO
falling edge
SMIF HYPERBUS™ specification for GPIO_STD
SID785A CL_HB_GPIO Load capacitance
–
–
–
20
–
pF
For all signals,
SID786A SRI_HB_GPIO Input rise and fall slew rates
0.45
V/ns guaranteed by
design
Output rise and fall slew
rates
SID787A SRO_HB_GPIO
0.45
–
–
V/ns For all signals
Clock characteristics
SID700A fCK_HB_GPIO
Clock frequency
Clock period
-
–
–
–
32
–
MHz
ns
1 / fCK_H-
B_GPIO
SID701A tCK_HB_GPIO
SID702A DCK_HB_GPIO Clock duty
45
55
%
AC parameters
Chip select HIGH between
Guaranteed by
design
SID706A tCSHI_HB_GPIO
SID708A tCSS_HB_GPIO
30
9
–
–
–
–
ns
transactions
Chip select setup to next CK
rising edge
ns
Datasheet
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Electrical specifications
Table 27-35 SMIF specifications (continued)[Conditions: drive_sel<1:0>= 00]
Details/
Spec ID
Parameter
Description
Data strobe valid
Min
Typ Max Units
Conditions
Guaranteed by
design
SID709A tDSV_HB_GPIO
–
–
36
ns
SID710A tOSU_HB_GPIO
SID711A tOH_HB_GPIO
SID715A tCKD_HB_GPIO
DQ output setup
DQ output hold
CK transition to DQ valid
3
3
3
3
–
–
–
–
–
–
16.5
16.5
ns
ns
ns
ns
SID718A tCKDS_HB_GPIO CK transition to RWDS valid
RWDS transition to input DQ
SID719A tDSS_HB_GPIO
–2.4
–2.4
0
–
–
–
2.4
2.4
–
ns
ns
ns
valid
Input DQ invalid to RWDS
SID720A tDSH_HB_GPIO
transition
Chip select hold after CK
falling edge
SID721A tCSH_HB_GPIO
tCK
VDDIO_1
or
VDDIO_3
CK
VSSD
or
VSSIO_3
tSU
tHD
0.5 x VDDIO_1
or VDDIO_3
Data
Timing Reference Level
Figure 27-43 SDR write timing reference level
tCK
VDDIO_1
or
VDDIO_3
CK
VSSD
or
VSSIO_3
tV
tV
0.5 x VDDIO_1
or VDDIO_3
Data
Timing Reference Level
Figure 27-44 SDR read timing reference level
Datasheet
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Electrical specifications
tCK
VDDIO_1
or
VDDIO_3
CK
VSSD
or
VSSIO_3
tSU
tHD
tSU
tHD
0.5 x VDDIO_1
or VDDIO_3
Data
Timing Reference Level
Figure 27-45 DDR write timing reference level
tCK
VDDIO_1
or
VDDIO_3
CK
VSSD
or
tV
VSSIO_3
Timing
0.5 x VDDIO_1
or VDDIO_3
Data
Reference Level
Figure 27-46 DDR read timing reference level
CK
1
6
Chip
select
2
3
8
4
5
LSB OUT
LSB IN
MSB OUT
MSB IN
Data
1: Chip select active setup time = tCSS
2: Data setup time = tSU
3: Data hold time = tHD
4: Clock LOW output valid = tV
5: Input data hold time = tHO
6: Chip select active hold time = tCSH
7: Chip select HIGH time = tCS
8: Input disable time = tDIS
Figure 27-47 SDR write and read timing diagram
Datasheet
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Electrical specifications
CK
7
1
Chip
select
4
5
4
8
2
3
2
3
MSB OUT
LSB OUT
MSB IN
LSB IN
Data
1: Chip select active setup time = tCSS
2: Data setup time = tSU
3: Data hold time = tHD
4: Clock LOW output valid = tV
5: Input data hold time = tHO
6: Chip select active hold time = tCSH
7: Chip select HIGH time = tCS
8: Input disable time = tDIS
Figure 27-48 DDR write and read timing diagram
tCK
VDDIO_1
or
VDDIO_3
CK
VSSD
or
VSSIO_3
tIS
tIH
tIS
tIH
0.5 x VDDIO_1
or VDDIO_3
Data
Timing Reference Level
Figure 27-49 HYPERBUS™ timing reference level
Datasheet
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Electrical specifications
9
Chip
select
10
1
CK
2
5
RWDS
3
4
3
4
DQ[7:0]
(output)
Command Address
Host drives DQ[7:0] and RWDS
6
DQ[7:0]
(input)
7
8
Memory drives DQ[7:0] and RWDS
1: Chip select setup to next CK rising edge = tCSS
2: Data strobe valid = tDSV
3: DQ output setup = tOSU
4: DQ output hold = tOH
5: CK transition to RWDS valid = tCKDS
6: CK transition to DQ valid = tCKD
7: RWDS transition to input DQ valid = tDSS
8: Input DQ invalid to RWDS transition = tDSH
9: Chip select hold after CK falling edge = tCSH
10: Chip select HIGH between transactions = tCSHI
Figure 27-50 HYPERBUS™ timing diagram
Datasheet
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28
Ordering information
The CYT4BF microcontroller part numbers and features are listed in Table 28-1. The Arm® TAP JTAG ID is 0x6BA0 0477.
Table 28-1
CYT4BF ordering information
CYT4BF8CES
CYT4BF8CEE
CYT4BF8CDS
CYT4BF8CEDQ0AESGS 176-TEQFP
CYT4BF8CEDQ0AEEGS 176-TEQFP
CYT4BF8CDDQ0AESGS 176-TEQFP
2
2
2
2
2
2
2
2
2
2
2
2
8384[68]
8384
8384
8384
8384
8384
8384
8384
8384
8384
8384
8384
256[69]
256
256
256
256
256
256
256
256
256
256
256
1024
1024
1024
1024
1024
1024
1024
1024
1024
1024
1024
1024
81
81
81
81
96
96
96
96
96
96
96
96
10
10
10
10
11
11
11
11
11
11
11
11
17
17
17
17
20
20
20
20
20
20
20
20
1
1
1
1
2
2
2
2
2
2
2
2
0
0
1[73]
1
1
1
1
1
1
1
1
1
1
1
1
S[70]
E[71]
S
0x2E5D3069[74]
0x2E5D3069
0x2E5D7069
0x2E5D7069
0x2E5EB069
0x2E5EB069
0x2E5EF069
0x2E5EF069
0x2E5FB069
0x2E5FB069
0x2E5FF069
0x2E5FF069
CYT4BF8CDE[72] CYT4BF8CDDQ0AEEGS 176-TEQFP
1
E
CYT4BFBCJS
CYT4BFBCJE
CYT4BFBCHS
CYT4BFBCJDQ0BZSGS
CYT4BFBCJDQ0BZEGS
CYT4BFBCHDQ0BZSGS
272-BGA
272-BGA
272-BGA
272-BGA
320-BGA
320-BGA
320-BGA
320-BGA
0
S
0
E
1
S
CYT4BFBCHE[72] CYT4BFBCHDQ0BZEGS
1
E
CYT4BFCCJS
CYT4BFCCJE
CYT4BFCCHS
CYT4BFCCJDQ0BZSGS
CYT4BFCCJDQ0BZEGS
CYT4BFCCHDQ0BZSGS
0
S
0
E
1
S
CYT4BFCCHE[72] CYT4BFCCHDQ0BZEGS
1
E
Notes
67.Supported shipment types are “Tray” (default) and “Tape and Reel”. Add the character ‘T’ at the end to get the ordering code for “Tape and Reel” shipment type.
68.Code-flash size 8384 KB = 32 KB × 254 (Large Sectors) + 8 KB × 32 (Small Sectors)
69.Work-flash size 256 KB = 2 KB × 96 (Large Sectors) + 128 B × 512 (Small Sectors)
70.S-grade Temperature (–40 °C to 105 °C).
71.E-grade Temperature (–40 °C to 125 °C).
72.These parts are available as engineering samples.
73.One interface of FlexRay supports two channels (ch A and ch B).
74.JTAG ID CODE bits 12 through 27, represents the Silicon ID of the device.
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Ordering information
28.1
Part number nomenclature
Table 28-2
Device code nomenclature
Field Description
Value
Meaning
CY
T
Cypress prefix
Category
CY
T
TRAVEO™
2
B
Family name
Application
4
B
TRAVEO™ T2G (Core M7 dual)
Body
Code-flash/Work-flash/SRAM
quantity
D
F
8384 KB / 256 KB / 1024 KB
8
B
C
C
E
D
J
H
S
E
176-TEQFP
272-BGA
320-BGA
eSHE – on, HSM – on, RSA - 2K
Ethernet - 1 ch, FlexRay - 0, eMMC - 1
Ethernet - 1 ch, FlexRay - 2, eMMC - 1
Ethernet - 2 ch, FlexRay - 0, eMMC - 1
Ethernet - 2 ch, FlexRay - 2, eMMC - 1
S-grade (–40 °C to 105 °C)
E-grade (–40 °C to 125 °C)
P
Packages
H
Hardware option
I
Marketing option
C
Temperature grade
Datasheet
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Ordering information
Table 28-3
Ordering code nomenclature
Field
CY
T
Description
Cypress prefix
Category
Value
CY
T
Meaning
TRAVEO™
2
B
Family name
Application
4
B
TRAVEO™ T2G (Core M7 dual)
Body
Code-flash/Work-flash/SRAM
quantity
D
F
8384 KB / 256 KB / 1024 KB
8
B
176-TEQFP
272-BGA
P
Packages
C
320-BGA
H
Hardware option
C
E
D
J
H
A
B
C
eSHE – on, HSM – on, RSA - 2K
Ethernet - 1 ch, FlexRay - 0, eMMC - 1
Ethernet - 1 ch, FlexRay - 2, eMMC - 1
Ethernet - 2 ch, FlexRay - 0, eMMC - 1
Ethernet - 2 ch, FlexRay - 2, eMMC - 1
First revision
I
Marketing option
Revision
Second revision
Third revision
R
D
Fourth revision
F
X
Fab Location
Reserved
Q
0
UMC (Fab 12i) Singapore
Reserved
AE
BZ
S
TEQFP
BGA
K
C
Q
S
Package code
S-grade (–40 °C to 105 °C)
E-grade (–40 °C to 125 °C)
Engineering samples
Standard grade of automotive
Tray shipment
Temperature grade
Quality grade
E
ES
GS
Blank
T
Shipment type
Tape and reel shipment
Datasheet
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Packaging
29
Packaging
CYT4BF microcontroller is offered in the packages listed in the Table 29-1.
Table 29-1
Package
Package information
[75]
[80]
Dimensions
Contact/Lead pitch
Coefficient of thermal expansion
I/O Pins
[76]
[77]
a1 = 8.4 ppm/°C, a2 = 29.4
ppm/°C
a1 = 11.9 ppm/°C, a2 = 34.3
ppm/°C
a1 = 11.9 ppm/°C, a2 = 34.5
ppm/°C
176-TEQFP 24 × 24 × 1.70 mm (max)
0.5-mm
148
[76]
[77]
272-BGA
320-BGA
16 × 16 × 1.70 mm (max)
17 × 17 × 1.70 mm (max)
0.8-mm
0.8-mm
220
240
[76]
[77]
Table 29-2
Package characteristics
Description
Parameter
Conditions
Min
Typ
Max
Units
Operating ambient
temperature
TA
TA
TJ
S-grade
E-grade
–
–40
–
105
°C
Operating ambient
temperature
–40
–
–
–
125
150
°C
°C
Operating junction
temperature
176-TEQFP
272-BGA
320-BGA
176-TEQFP
272-BGA
320-BGA
176-TEQFP
272-BGA
320-BGA
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
16.4
22.4
21.8
11.96
13.5
13.6
7.5
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
Package thermal resistance,
RθJA
RθJB
RθJC
[78, 79]
junction to ambient θJA
Package θJB
Package thermal resistance,
8.9
junction to case θJC
6.5
Table 29-3
Package
Solder reflow peak temperature, package moisture sensitivity level (MSL), IPC/JEDEC
J-STD-2
Maximum peak temperature
(°C)
Maximum time at peak temperature
(seconds)
MSL
176-TEQFP
272-BGA
320-BGA
260
260
260
30
30
30
3
3
3
Notes
75.The dimensions (column 2) are valid for room temperature.
76.a1 = CTE (Coefficient of Thermal Expansion) value below Tg (ppm/°C) (Tg is glass transition temperature which is 131°C).
77.a2 = CTE value above Tg (ppm/°C).
78.Maximum value °C/Watt shown is for TA = 125 °C.
79.Board condition complies to JESD51-7(4 Layers).
80.The numbers are estimated values based simulation only and are based on a single bill of material combination per package type.
Datasheet
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Packaging
002-25324 **
Figure 29-1
Package outline – 176-TEQFP
Datasheet
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Packaging
002-24865 *A
Figure 29-2
Package outline – 272-BGA
Datasheet
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Packaging
002-23091 *A
Figure 29-3
Package outline – 320-BGA
Datasheet
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Based on Arm® Cortex®-M7 dual
Appendix
30
Appendix
30.1
Bootloading or end-of-line programming
• Triggered at device startup, if a trigger condition is applied
• Either CAN or LIN communication may be used
• Bootloader polls for the communication on CAN or LIN at the separate time frames, until the overall 300-second
timeout is reached
• If a bootloader command is received on either communication interface, the polling stops and bootloader starts
using this interface
150 ms
10 ms
10 ms
CAN,
100 Kbps
Polling
CAN,
500 Kbps
Polling
LIN,
20 Kbps
Polling
CAN,
100 Kbps
Polling
Bootloader
Stopped
….
Overall bootloading time, if no communication ( 300 s)
Figure 30-1
Bootloading sequence
CAN interface details
Table 30-1
Sl. No.
CAN interface
Configuration
1
2
3
4
5
6
7
8
9
CAN mode
CAN instance
CAN TX
CAN RX
CAN transceiver NSTB / EN (Low)
CAN transceiver EN / EN (High)
CAN RX Message ID
Classic CAN
CAN0, Channel#1
P0.2 / CAN0_1_TX
P0.3 / CAN0_1_RX
P23.3 (optional)
P2.1 (optional)
0x1A1
CAN TX Message ID
Baud
0x1B1
100 or 500 kbps alternating
VSS
CAN
Transceiver
TRAVEOTM T2G MCU
NSTB
EN
EN (Low)
EN (High)
TX
TX
RX
RX
Figure 30-2
MCU to CAN transceiver connections
Datasheet
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Appendix
Table 30-2
LIN interface details
LIN interface
Sl. No.
Configuration
LIN0, Channel#1
Slave
1
2
LIN type
LIN mode
3
4
5
6
7
8
LIN checksum type
LIN TX
LIN RX
LIN EN / EN (High)
LIN EN (Low)
LIN TX PID
Classic
P0.1 / LIN1_TX
P0.0 / LIN1_RX
P2.1 (optional)
P23.3 (optional)
0x46
9
LIN RX PID
0x45
10
11
12
Baud
Break field length
Break delimiter length
20 or 115.2 kbps
11
1 bit
VDDD / VDDIO
LIN
Transceiver
TRAVEOTM T2G MCU
EN (Low)
EN (High)
EN
TX
RX
TX
RX
Figure 30-3
MCU to LIN transceiver connections
Datasheet
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Appendix
30.2
External IP revisions
Table 30-3
IP revisions
Module
IP
Revision
Vendor
FlexRay
mxflexray
Release - Revision 1.0.3, CREL - 103 9 02 06, E-Ray Spec - Bosch
v1.2.7, Protocol Spec - v2.1
SDHC
mxsdhc
version 1.70a
Synopsys
CANFD
mxttcanfd
armcm0p
armcm7
M_TTCAN IP revision: Rev.3.2.3
Cortex®-M0+-r0p1
Cortex®-M7-r1p2
Bosch
Arm®
Arm®
Arm®
Cadence
Arm® Cortex®-M0+
Arm® Cortex®-M7
Arm® Coresight
Ethernet
armcoresighttk CoreSight-SoC-TM100-r3p2
mxeth
GEM_GXL r1p09
Datasheet
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Acronyms
31
Acronyms
Table 31-1
Acronyms used in the document
Acronym
A/D
Description
Analog to Digital
Acronym
PLL
Description
Phase Locked Loop
ABS
Absolute
POR
Power-on reset
ADC
AES
AHB
Analog to Digital converter
Advanced encryption standard
AMBA (advanced microcontroller bus
architecture) high-performance bus, Arm®
data transfer bus
PPU
PRNG
PSoC
Peripheral protection unit
Pseudo-random number generator
Programmable system on chip
Arm®
ASIL
BOD
Advanced RISC machine, a CPU architecture PWM
Pulse-width modulation
Microcontroller Unit
Multi-counter watchdog timer
Memory-Direct Memory Access
Automotive safety integrity level
Brown-out detection
MCU
MCWDT
CAN FD
Controller Area Network with Flexible Data M-DMA
rate
CMOS
CPU
CRC
Complementary metal-oxide-semiconductor MISO
Master-in slave-out
Memory mapped I/O
Master-out slave-in
Central Processing Unit
MMIO
Cyclic redundancy check, an error-checking MOSI
protocol
CSV
CTI
Clock supervisor
Cross Trigger Interface
MPU
NVIC
Memory protection unit
Nested vectored interrupt
controller
DES
ECC
Data encryption standard
Error correcting code
RAM
RISC
Random access memory
Reduced-instruction-set
computing
ECO
ETM
FLL
External crystal oscillator
Embedded Trace Macrocell
Frequency Locked Loop
Floating point unit
Green hills tool chain with IDE
General purpose input/output
Hardware security module
Input/output
ROM
RTC
SAR
SCB
SCL
SDA
SHA
SHE
Read only memory
Real-time clock
Successive approximation register
Serial communication block
I2C serial clock
FPU
GHS
GPIO
HSM
I/O
I2C serial data
Secure hash algorithm
Secure hardware extension
Shared memory protection unit
I2C
Inter-Integrated Circuit, a communications SMPU
protocol
Inter-Integrated Circuit Sound
I2S
SPI
Serial peripheral interface, a
communications protocol
ILO
IMO
IPC
Internal low-speed oscillator
Internal main oscillator
Inter-processor communication
Infrared interface
SRAM
SWD
TCM
Static random access memory
Single wire debug
Tightly Coupled Memory
Timer/Counter Pulse-width
modulator
IrDA
TCPWM
IRQ
Interrupt request
TTL
Transistor-transistor logic
JTAG
Joint test action group
TRNG
True random number generator
Datasheet
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Acronyms
Table 31-1
Acronyms used in the document
Description
Acronym
Acronym
Description
LIN
Local Interconnect Network, a communica- UART
tions protocol
Universal Asynchronous Trans-
mitter Receiver, a communications
protocol
LVD
OTA
OTP
OVD
PASS
P-DMA
Low voltage detection
WCO
WDT
XIP
Watch crystal oscillator
Watchdog timer reset
eXecute In Place
Crystal
Over-the-air programming
One-time programmable
Over voltage detection
Programmable Analog Subsystem
Peripheral-Direct Memory Access
XTAL
Datasheet
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Errata
32
Errata
This section describes the errata for the CYT4BF product family. Details include trigger conditions, scope of
impact, available workaround, and silicon revision applicability. Contact your local Cypress Sales Representative
if you have further questions.
Part numbers affected
Part numbers
All CYT4BF parts
CYT4BF qualification status
Production samples
CYT4BF errata summary
The following table defines the errata applicability to available CYT4BF family devices.
Items
Errata ID
CYT4BF
Silicon Rev.
Fix status
[1] CAN FD RX FIFO top pointer feature does not function
as expected
96
No silicon fix planned.
Use workaround.
[2] CAN FD debug message handling state machine is not
97
No silicon fix planned.
Use workaround.
reset to Idle state when CANFD_CH_CCCR.INIT is set
[3] Limitation of the memory hole in SCB register space
124
128
No silicon fix planned.
Use workaround.
[4] Limitation of the memory hole in Ethernet (ETH)
No silicon fix planned.
Use workaround.
register space
[5] CAN FD controller message order inversion when
transmitting from dedicated Tx Buffers configured with
same Message ID
No silicon fix planned.
Use workaround.
147
167
175
[6] CAN FD incomplete description of Dedicated Tx
Buffers and Tx Queue related to transmission from
multiple buffers configured with the same Message ID
No silicon fix planned.
Use workaround. TRM
was updated.
CYT4BF8CEDQ0AESGS
CYT4BF8CEDQ0AEEGS
CYT4BF8CDDQ0AESGS
CYT4BF8CDDQ0AEEGS
CYT4BFBCJDQ0BZSGS
CYT4BFBCJDQ0BZEGS
CYT4BFBCHDQ0BZSGS
CYT4BFBCHDQ0BZEGS
CYT4BFCCJDQ0BZSGS
CYT4BFCCJDQ0BZEGS
CYT4BFCCHDQ0BZSGS
CYT4BFCCHDQ0BZEGS
[7] Misleading status is returned for Flash and eFuse
system calls, if there are pending NC ECC faults in SRAM
controller #0
No silicon fix planned.
TRM will be updated.
No silicon fix planned.
TRM will be updated.
[8] WDT reset causes loss of SRAM retention
176
177
185
D
[9] RMII TX output maximum delay spec change for
No silicon fix planned.
GPIO_STD
[10] Crypto ECC errors may be set after boot with appli-
No silicon fix planned.
TRM will be updated.
cation authentication
Will be fixed to update
the Flash settings, via
Manufacturing
Test
Program Update for
Code Flash setting; this
fix is transferred to
TRAVEO™ T2G devices
during Infineon Factory
Test Flow. Fixed devices
will be identified by
Device Date Code, which
is marked on every
TRAVEO™ T2G device.
[11]Incomplete erase of Code Flash cells could happen
Erase Suspend / Erase Resume is used along with Erase
Sector operation in Non-Blocking mode
198
199
[12]Limitation for keeping the port state from peripheral
IP after wakeup from DeepSleep
No silicon fix planned.
TRM will be updated.
Datasheet
209
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Architecture block diagram
1. CAN FD RX FIFO top pointer feature does not function as expected
Problem Definition
RX FIFO top pointer function calculates the address for received messages in Message RAM by hardware. This address
should restart from the start address after reading all messages of RX FIFO n size (n: 0 or 1). However, the address does
not restart from the start address when RX FIFO n size is set to 1(CANFD_CH_RXFnC.FnS = 0x01). This results in CPU/DMA
reading messages from the wrong address in Message RAM.
Parameters Affected
Trigger Condition(s)
Scope of Impact
NA
The RX FIFO top pointer function is used when RX FIFO n size is set to 1 element (CANFD_CH_RXFnC.FnS = 0x01).
Received message cannot be correctly read by using the RX FIFO top pointer function, when RX FIFO n size is set to 1
element.
Workaround
Any of the following can be used as a workaround:
1) Set RX FIFO n size to 2 or more when using the RX FIFO top pointer function.
2) Do not use the RX FIFO top pointer function when RX FIFO n size is set to 1 element. Instead of the RX FIFO top pointer,
read received messages from the Message RAM directly.
Fix Status
No silicon fix planned. Use workaround.
2. CAN FD debug message handling state machine is not reset to Idle state when CANFD_CH_CCCR.INIT is set
Problem Definition
If either of the CANFD_CH_CCCR.INIT bits is set by the Host or when the M_TTCAN module enters BusOff state, the debug
message handling state machine stays in its current state instead of being reset to Idle state. Configuring the bit
CANFD_CH_CCCR.CCE does not change CANFD_CH_RXF1S.DMS.
Parameters Affected
Trigger Condition(s)
Scope of Impact
NA
Either of the CANFD_CH_CCCR.INIT bits is set by the Host or when the M_TTCAN module enters BusOff state.
The errata is limited to the use case when the debug on CAN functionality is active. Normal operation of the CAN module
is not affected, in which case the debug message handling state machine always remains in Idle state. In the described
use case, the debug message handling state machine is stopped and remains in the current state signaled by the
CANFD_CH_RXF1S.DMS bit. In case CANFD_CH_RXF1S.DMS is set to 0b11, the DMA request remains active.
Bosch classifies this as a non-critical error with low severity, there is no fix for the IP. Bosch recommends the workaround
listed here.
Workaround
Fix Status
In case the debug message handling state machine has stopped while CANFD_CH_RXF1S.DMS is 0b01 or 0b10, it can be
reset to Idle state by hardware reset or by reception of debug messages after CANFD_CH_CCCR.INIT is reset to zero.
No silicon fix planned. Use workaround.
3. Limitation of the memory hole in SCB register space
Problem Definition
The memory hole [offset address: 0x1000 to 0xFFFF] inside SCB register space is not aligned to the below defined spec.
The offset address bits [15:12] are ignored and treated as 4’b0000, so write/read access to offset address [0x1000 to
0xFFFF], will actually happen to [0x0000 to 0x0FFF].
- Access to address gaps in memory mapped space: writes are ignored and any read returns a zero.
Parameters Affected
Trigger Condition(s)
Scope of Impact
Workaround
NA
Access to the memory hole [offset address: 0x1000 to 0xFFFF] in SCB register space.
The memory hole [offset address: 0x1000 to 0xFFFF] in SCB register space is not aligned to other IP registers.
Do not access to the memory hole [offset address: 0x1000 to 0xFFFF] in SCB register space.
No silicon fix planned.
Fix Status
Datasheet
210
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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Architecture block diagram
4. Limitation of the memory hole in Ethernet (ETH) register space
Problem Definition
The memory hole [offset address: 0x2000 to 0xFFFF] in ETH register space has the below mentioned original spec.
However, when accessing address gaps within [0x1000 to 0x1FFF], the offset address bits [15:13] are ignored and treated
as 3’b000, so write/read access to offset address [0x3000 to 0x3FFF, 0x5000 to 0x5FFF, 0x7000 to 0x7FFF, 0x9000 to
0x9FFF, 0xB000 to 0xBFFF, 0xD000 to 0xDFFF, 0xF000 to 0xFFFF], will actually happen to [0x1000 to 0x1FFF].
- Access to address gaps within [0x0000 to 0x0FFF]: writes are ignored and any read returns a zero.
- Access to address gaps within [0x1000 to 0x1FFF]: returns AHB ERROR.
Parameters Affected
Trigger Condition(s)
NA
Access to the memory hole [offset address: 0x3000 to 0x3FFF, 0x5000 to 0x5FFF, 0x7000 to 0x7FFF, 0x9000 to 0x9FFF,
0xB000 to 0xBFFF, 0xD000 to 0xDFFF, 0xF000 to 0xFFFF] in ETH register space.
Scope of Impact
Workaround
Fix Status
Write/read access to offset address [0x3000 to 0x3FFF, 0x5000 to 0x5FFF, 0x7000 to 0x7FFF, 0x9000 to 0x9FFF, 0xB000 to
0xBFFF, 0xD000 to 0xDFFF, 0xF000 to 0xFFFF], will actually happen to [0x1000 to 0x1FFF].
Do not access the memory hole [offset address: 0x3000 to 0x3FFF, 0x5000 to 0x5FFF, 0x7000 to 0x7FFF, 0x9000 to 0x9FFF,
0xB000 to 0xBFFF, 0xD000 to 0xDFFF, 0xF000 to 0xFFFF] in ETH register space.
No silicon fix planned.
5. CAN FD controller message order inversion when transmitting from dedicated Tx Buffers configured with same Message ID
Problem Definition
Configuration:
Several Tx buffers are configured with same Message ID. Transmission of these Tx buffers is requested sequentially with
a delay between the individual Tx requests.
Expected behavior:
When multiple Tx buffers that are configured with the same Message ID have pending Tx requests, they shall be trans-
mitted in ascending order of their Tx buffer numbers. The Tx buffer with lowest buffer number and pending Tx request
is transmitted first.
Observed behavior:
It may happen, depending on the delay between the individual Tx requests, that if multiple Tx buffers are configured
with the same Message ID, the Tx buffers are not transmitted in order of the Tx buffer number (lowest number first).
Parameters Affected
Trigger Condition(s)
Scope of Impact
NA
When multiple Tx buffers configured with the same Message ID have pending Tx requests.
In the case described, it is possible that Tx buffers configured with the same Message ID and pending Tx request are not
transmitted with lowest Tx buffer number first (message order inversion).
Workaround
Any of the following:
1) First, write the group of Tx message with the same Message ID to the Message RAM and then afterwards request
transmission of all these messages concurrently by a single write access to CANFDx_CHy_TXBAR. Before requesting a
group of Tx messages with this Message ID ensure that no message with this Message ID has a pending Tx request.
2) Use the Tx FIFO instead of dedicated Tx buffers for the transmission of several messages with the same Message ID in
a specific order.
Applications not able to use workaround #1 or #2 can implement a counter within the data section of their messages
sent with same ID in order to allow the recipients to determine the correct sending sequence.
Fix Status
No silicon fix planned. Use workaround.
Datasheet
211
002-21617 Rev. *K
2022-10-10
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Architecture block diagram
6. CAN FD incomplete description of Dedicated Tx Buffers and Tx Queue related to transmission from multiple buffers configured with the same
Message ID
Problem Definition
The following are the updated description in Sections "Dedicated Tx Buffers" and "Tx Queue" of the Architecture TRM
related to the transmission from multiple buffers configured with the same Message ID.
Dedicated Tx buffers
- TRM Statement: If multiple Tx buffers are configured with the same Message ID, the Tx buffer with the lowest buffer
number is transmitted first.
- Enhancement: These Tx buffers shall be requested in ascending order with lowest buffer number first. Alternatively all
Tx buffers configured with the same Message ID can be requested simultaneously by a single write access to CANFDx-
_CHy_TXBAR.
Tx queue
- TRM statement: If multiple queue buffers are configured with the same Message ID, the queue buffer with the lowest
buffer number is transmitted first.
- Replacement: If multiple Tx queue buffers are configured with the same Message ID, the transmission order depends
on numbers of the buffers where the messages were stored for transmission. As these buffer numbers depend on the
then current states of the PUT Index, a prediction of the transmission order is not possible.
- TRM statement: An Add Request cyclically increments the Put Index to the next free Tx Buffer.
- Replacement: The PUT Index always points to that free buffer of the Tx Queue with the lowest number.
Parameters Affected
Trigger Condition(s)
Scope of Impact
NA
Using multiple dedicated Tx buffers or Tx queue buffers configured with the same Message ID.
If the dedicated Tx buffers with the same Message ID are not requested in ascending order or at the same time, or if there
are multiple Tx queue buffers with the same Message ID, it cannot be guaranteed, that these messages are transmitted
in ascending order with lowest buffer number first.
Workaround
Fix Status
In case a defined order of transmission is required the Tx FIFO shall be used for transmission of messages with the same
Message ID. Alternatively dedicated Tx buffers with the same Message ID shall be requested in ascending order with
lowest buffer number first or by a single write access to CANFDx_CHy_TXBAR. Alternatively a single Tx Buffer can be used
to transmit those messages one after the other.
No silicon fix planned. Use workaround. TRM was updated accordingly.
7. Misleading status is returned for Flash and eFuse system calls, if there are pending NC ECC faults in SRAM controller #0
Problem Definition
Flash and eFuse system calls will return misleading status of 0xF0000005 (“Page is write protected”) even for
non-protected row, or 0xF0000002 (“Invalid eFuse address”) for valid eFuse address in case of pending NC ECC faults in
SRAM controller #0.
Parameters Affected
Trigger Condition(s)
Scope of Impact
Return status of Flash and eFuse system calls.
NC ECC fault(s) pending in SRAM controller #0 and SWPUs are populated in the design.
Flash and eFuse system calls will not work until the NC ECC fault(s) pending in SRAM controller #0 is/are properly
handled.
Workaround
Fix Status
If the NC ECC fault(s) are not due to HW malfunction (i.e. if the faults are due to usage of non-initialized SRAM or improper
SRAM initialization), then clearing of these pending faults will resolve the issue.
No silicon fix planned. TRM will be updated.
8. WDT reset causes loss of SRAM retention
Problem Definition
Architecture TRM Table on “Reset Cause Distribution” shows that, the WDT reset can retain SRAM if there is an orderly
shutdown of the SRAM only during a warning interrupt. However, this is wrong. WDT reset causes loss of SRAM retention.
Parameters Affected
Trigger Condition(s)
Scope of Impact
Workaround
NA
WDT reset
WDT reset causes loss of SRAM retention.
None
Fix Status
No silicon fix planned. TRM will be updated.
Datasheet
212
002-21617 Rev. *K
2022-10-10
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Errata
9. RMII TX output maximum delay spec change for GPIO_STD
Problem Definition
RMII TX output maximum delay specification has been changed from 14 ns to 14.6 ns for GPIO_STD. The HSIO_STD spec
of 14 ns is unchanged.
Parameters Affected
Trigger Condition(s)
Scope of Impact
SID393
Using GPIO_STD as RMII
This spec change will cause the PCB delay budget between MCU and PHY to be cut down to 1.4 ns from 2 ns.
[PCB delay budget = REF_CLK period (e.g. 20 ns) – SID393 (14.6 ns) – PHY RXD setup (e.g. 4 ns)]
Workaround
Fix Status
None
No silicon fix planned.
10.Crypto ECC errors may be set after boot with application authentication
Problem Definition
Due to the improper initialization of the Crypto memory buffer, Crypto ECC errors may be set after boot with application
authentication.
Parameters Affected
Trigger Condition(s)
Scope of Impact
Workaround
N/A
Boot device with application authentication.
Crypto ECC errors may be set after boot with application authentication.
Clear or ignore Crypto ECC errors which generated during boot with application authentication.
No silicon fix planned. TRM will be updated.
Fix Status
11.Incomplete erase of Code Flash cells could happen Erase Suspend / Erase Resume is used along with Erase Sector operation in Non-Blocking
mode
Problem Definition
Code Flash memory can be erased in “Non-Blocking” mode; a Non-Blocking mode supported option allows users to
suspend an ongoing erase sector operation. When an ongoing erase operation is interrupted using “Erase Suspend” and
“Erase Resume”, Flash cells may not have been erased completely, even after the erase operation complete is indicated
by FLASHC_STATUS register. Only Code Flash is impacted by this issue, Work Flash and Supervisory Flash (SFlash) are
not impacted.
Parameters Affected
Trigger Condition(s)
N/A
Using EraseSector System Call in Non-Blocking mode for CM0+ to erase Code Flash and the ongoing erase operation is
interrupted using EraseSuspend and EraseResume System calls.
Scope of Impact
Workaround
When Code Flash sectors are erased in Non-Blocking mode and the ongoing erase operation is interrupted by Erase
Suspend / Erase Resume, it cannot be guaranteed that the Code Flash cells are fully erased. Any read on the Code Flash
area after the erase is complete or read on the programmed data after ProgramRow is complete can trigger ECC errors.
Use any of the following:
1) Use Non-Blocking mode for EraseSector, but do not interrupt the erase operation using Erase Suspend / Erase Resume.
2) If a Code Flash sector erase operation is interrupted using Erase Suspend / Erase Resume, then erase the same sector
again without Erase Suspend / Erase Resume before reading the sector or programming the sector.
Fix Status
Will be fixed to update the Flash settings, via Manufacturing Test Program Update for Code Flash setting; this fix is
transferred to TRAVEO™ T2G devices during Infineon Factory Test Flow. Fixed devices will be identified by Device Date
Code, which is marked on every TRAVEO™ T2G device.
Datasheet
213
002-21617 Rev. *K
2022-10-10
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Errata
12.Limitation for keeping the port state from peripheral IP after wakeup from DeepSleep
Problem Definition
The port state is not retained when the port selects peripheral IP (except for LIN or CAN FD) and MCU wakes up from
DeepSleep.
Parameters Affected
Trigger Condition(s)
Scope of Impact
Workaround
N/A
The port selects peripherals (except for LIN or CAN-FD) and MCU wakes up from DeepSleep.
Unexpected port output change might affect user system.
If the port selects peripherals (except for LIN or CAN FD), and the port output value need to be maintained after wakeup
from DeepSleep, set HSIOM_PRTx_PORT_SEL.IOy_SEL = 0 (GPIO) before DeepSleep and set the required output value
in GPIO configuration registers. After wakeup, change HSIOM_PRTx_PORT_SEL.IOy_SEL back to the peripheral module
as needed.
Fix Status
No silicon fix planned. TRM will be updated to add above workaround.
Datasheet
214
002-21617 Rev. *K
2022-10-10
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Errata
Revision history
Document
Date of release
version
Description of changes
**
2018-02-23
New datasheet
Updated Features and Features list.
Updated Blocks and functionality.
Updated Functional description.
Updated CYT4BF address map, Flash base address map, and Peripheral I/O map.
Added CYT4BF clock diagram.
Added Pin assignment
*A
2018-05-04
Updated Electrical specifications.
Added the following timing diagrams in Electrical specifications:
Reset, TCPWM, SCB (I2C, SPI), Crystal Connection Scheme, SAR ADC, System Resources, and JTAG.
Added Interrupts and wake-up assignments, Peripheral clock assignments, Trigger multiplexer,
Triggers group inputs, Triggers group outputs, Triggers one-to-one, and Faults.
Added Peripheral I/O map
Added Packaging.
Updated Features and Features list.
Updated Blocks and functionality.
Updated Pin assignment.
*B
2018-07-27
Updated Electrical specifications.
Added Timing Diagrams for Ethernet, SMIF
Updated SCB Diagrams
Added Ordering information.
Updated Features list and Peripheral I/O map.
Updated Functional description.
Updated Pin assignment and Package pin list and alternate functions.
Updated Trigger multiplexer, Core interrupt types, and Peripheral clock assignments.
Added General P-DMA descriptions and Clock Dividers.
Updated CYT4BF clock diagram.
*C
*D
2018-09-28
2019-01-16
Updated Electrical specifications.
Updated Design Review.
Updated Features list and Peripheral I/O map.
Updated Functional description.
Updated Pin assignment for 176-TEQFP package
Updated Electrical specifications.
Updated Design and Expert Reviews.
Updated Features list, CYT4BF address map, Peripheral I/O map.
Updated Pin assignment, Alternate function pin assignments.
Updated Trigger Group tables.
Updated Peripheral clocks and Peripheral protection unit fixed structure pairs.
Updated Bus masters and Miscellaneous configuration.
Updated Electrical specifications.
*E
2019-06-06
Updated and SPI Diagrams.
Updated Table 27-20.
Updated Ordering information and Packaging.
Updated Appendix.
Updated TCPWM Channels and Programmable Analog in Features.
Updated Ethernet MAC, TCPWM, SAR ADC, Audio I2S, and Debug Trace in Features list.
Updated TCPWM channels in Architecture block diagram.
Updated DeepSleep, PLL and FLL, TCPWM, and External Memory Interface sections in Functional
description.
Updated SRAM details in CYT4BF address map.
Added eFUSE and updated PERI Programmable PPU in Peripheral I/O map.
Added VSSD_2 in Power pin assignments.
*F
2019-11-15
Updated PASS interrupts in Interrupts and wake-up assignments.
Added Note 40 in Peripheral protection unit fixed structure pairs.
Changed MiniProg3 to MiniProg4 in Development support.
Updated , ADC Calculation of impact of neighboring pins, Clock Specifications, and SMIF Diagrams in
Electrical specifications.
Updated Ordering information and Packaging.
Updated Functional description.
Updated Power pin assignments.
Updated Pin mux descriptions.
Updated Fault assignments.
Updated ECO spec from 3.988 MHz to 8 MHz.
Updated Electrical specifications.
Updated Ordering information.
Added Errata.
*G
2020-05-04
Datasheet
215
002-21617 Rev. *K
2022-10-10
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Errata
Updated Features.
Updated Features list.
Updated Regulators.
Updated Clock system.
Updated Peripheral I/O map.
Updated Power pin assignments.
Updated Pin mux descriptions.
*H
2020-09-23
Updated DC specifications.
Updated Ethernet specifications.
Updated Packaging.
Updated Appendix.
Updated Electrical specifications.
Please refer to Revision history change logRev. *K electrical spec updates for the detailed list of
changes for this revision.
Removed Preliminary status.
Updated Features.
Updated Clock system.
Updated Power modes.
Updated Audio interface.
Updated I/Os.
Updated Pin assignment.
Updated High-speed I/O matrix connections.
Updated Alternate function pin assignments.
Updated Interrupts and wake-up assignments.
Updated Faults.
*I
2021-10-27
Updated Electrical specifications.
Updated Part number nomenclature.
Added Errata
Please refer to Rev. *K electrical spec updatesRevision history change log for the detailed list of
changes for this revision.
Updated System resources.
*J
2022-02-18
2022-10-10
Updated Serial memory interface specifications.
Updated Errata.
Updated External memory interface.
Updated Alternate function pin assignments.
Updated Electrical specifications.
Added note in Packaging.
*K
Updated Errata.
Datasheet
216
002-21617 Rev. *K
2022-10-10
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Errata
Revision history change log
Rev. *K section updates
Section
Change Description
Current Spec (002-21617 Rev. *J)
New Spec (002-21617 Rev. *K)
Reason for change
3.3.10 External
Updated description
HYPERBUS™ allows connection to Hyper- HYPERBUS™ allows connection to Correction
memory interface
Flash and HyperRAM devices, while SPI HyperFlash and HyperRAM devices,
(single, dual, quad, or octal SPI at up to 80 while SPI (single, dual, quad, or octal
MHz) can connect with serial flash
memory.
SPI) can connect with serial flash
memory.
13. Alternate
function pin
assignments
Updated Table 13-1
Updated description
Current: P1.1 / ACT #7: SCB4_MISO (2)
New: P1.1 / ACT #7: SCB4_SEL0 (2) Correction
Note 46 in “27
Electrical Specifi-
cations”
5.0 V ±10% is supported with a higher OVD 5.0 V ±10% is supported with a
Correction
setting option for VDDD and VDDA. This
setting provides robust protection for
internal and interface timing, but OVD
reset occurs at a voltage above the
specified operating conditions. A lower
higher OVD setting option for VDDD
and VDDA. This setting provides
robust protection for internal and
interface timing, but OVD reset
occurs at a voltage above the
OVD setting option is available (consistent specified operating conditions. A
with up to 5.0 V) and guarantees that all lower OVD setting option is available
operating conditions are met.
(consistent with up to 5.0 V) and
guarantees that all operating condi-
tions are met. Voltage overshoot to a
higher OVD setting range for VDDD
and VDDA is permissible, provided
the duration is less than 2 hours
cumulated. Note that during
overshoot voltage condition
electrical parameters are not
guaranteed.
27.11 Clock speci- Updated Table 27-20
fications
Old representation
New representation with source,
max permitted frequency setting
based on PLL/FLL, and ECO/IMO.
Notes 59/60/61/62 added accord-
ingly.
Improvement
Note 80 in “29
Packaging”
New addition
(none)
(none)
The numbers are estimated values Added note
based simulation only and are based
on a single bill of material combi-
nation per package type.
32. Errata
Added errata
Added errata ID 185, 198, 199
New addition
Rev. *K electrical spec updates
Reason for
Change
Spec ID
Description
Changed Item
Current Spec (002-21617 Rev. *J)
New Spec (002-21617 Rev. *K)
SID49E1 V CCD current in
external
Details/Condi-
tions
Typ: T A = 25 °C, VDDD = 5.0 V,
process typ (TT)
Max: T A = 125 °C, VDDD = 5.5 V,
process worst (FF)
Typ: TA = 25 °C, VCCD = 1.15 V,
process typ (TT)
Max: TA = 125 °C, VCCD = 1.20 V,
process worst (FF)
Correction
PMIC/transistormode,
Active mode (CM7_0
at350 MHz, CM0+ at
100 MHz, all
peripherals are
enabled)
SID50A1 V CCD current in
external
Details/Condi-
tions
Typ: T A = 25 °C, VDDD = 5.0 V,
process typ (TT)
Max: T A = 125 °C, VDDD = 5.5 V,
process worst (FF)
Typ: TA = 25 °C, VCCD = 1.15 V,
process typ (TT)
Max: TA = 125 °C, VCCD = 1.20 V,
process worst (FF)
Correction
PMIC/transistormode,
Active mode (CM7
CPUs at 350 MHz,CM0+
at 100 MHz, all periph-
erals are enabled)
Datasheet
217
002-21617 Rev. *K
2022-10-10
Trademarks
All referenced product or service names and trademarks are the property of their respective owners.
IMPORTANT NOTICE
For further information on the product, technology,
delivery terms and conditions and prices please
contact your nearest Infineon Technologies office
(www.infineon.com).
The information given in this document shall in no
event be regarded as a guarantee of conditions or
characteristics (“Beschaffenheitsgarantie”).
Edition 2022-10-10
Published by
Infineon Technologies AG
81726 Munich, Germany
With respect to any examples, hints or any typical
values stated herein and/or any information
regarding the application of the product, Infineon
Technologies hereby disclaims any and all
warranties and liabilities of any kind, including
without limitation warranties of non-infringement of
intellectual property rights of any third party.
WARNINGS
Due to technical requirements products may contain
dangerous substances. For information on the types
in question please contact your nearest Infineon
Technologies office.
© 2022 Infineon Technologies AG.
All Rights Reserved.
Except as otherwise explicitly approved by Infineon
In addition, any information given in this document
is subject to customer’s compliance with its
obligations stated in this document and any
applicable legal requirements, norms and standards
concerning customer’s products and any use of the
product of Infineon Technologies in customer’s
applications.
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authorized
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document?
Go to www.cypress.com/support
representatives
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Infineon
Technologies, Infineon Technologies’ products may
not be used in any applications where a failure of the
product or any consequences of the use thereof can
reasonably be expected to result in personal injury.
Document reference
002-21617 Rev. *K
The data contained in this document is exclusively
intended for technically trained staff. It is the
responsibility of customer’s technical departments
to evaluate the suitability of the product for the
intended application and the completeness of the
product information given in this document with
respect to such application.
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