CYUSB2024-BZXI_技术文档

CYUSB202X

SD2™ USB and Mass Storage Peripheral Controller

■ Selectable input clock frequencies

❐ 19.2, 26, 38.4, and 52 MHz

❐ 19.2-MHz crystal input support

Features

■ Latest-generation storage support

❐ SD2.0/SDXC – UHS1 SDR50 / DDR50 Master

❐ eMMC 4.4 Master

■ Independent power domains for core and I/O

■ 10 × 10 mm, 0.8-mm pitch ball grid array (BGA) package

❐ SDIO 3.0 Master

■ USB integration

❐ Certified USB 2.0 peripheral: Hi-Speed (HS), and Full-Speed

(FS) only)

❐ Thirty-two physical endpoints

❐ Integrated transceiver

Applications

■ USB thumb drives

■ Card readers

❐ Accessory charger adaptor (ACA) support

■ Laptop with SD slots

■ SD slot in TV/STB

■ WiFi Dongles

■ Ultra low-power in core power-down mode

❐ Less than 60 µA with VBATT on and 20 µA with VBATT off

■ I²C master controller at 1 MHz

Logic Block Diagram

JTAG

Embedded

SRAm

(512 kB/

256 KB)

ARM926EJ-S

D+

D-

USB

EPs

HS/FS

Peripheral

GPIOs

FSLC[0]

FSLC[1]

FSLC[2]

CLKIN

UART

SPI

SDIO/SD/MMC Controller

CLKIN_32

XTALIN

XTALOUT

I²S

I2C

S0-PORT

S1-PORT

Cypress Semiconductor Corporation

Document Number: 001-87710 Rev. *C

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised April 24, 2017

CYUSB202X

Contents

Functional Overview ........................................................3

USB Interface (U-Port) ................................................3

Mass-Storage Support (S-Port) ...................................3

I2C Interface ................................................................3

UART Interface ............................................................3

I2S Interface ................................................................3

SPI Interface ................................................................4

Boot Options ................................................................4

Reset ...........................................................................4

Clocking .......................................................................4

32-kHz Watchdog Timer Clock Input ...........................4

Power ..........................................................................5

Configuration Fuse ......................................................8

Digital I/Os ...................................................................8

EMI ..............................................................................8

System Level ESD ......................................................8

Pinout for BGA ..................................................................8

Pin Description for BGA ..................................................9

AC Timing Parameters ...................................................12

Storage Port Timing ..................................................12

I2C Interface Timing ..................................................15

Absolute Maximum Ratings ..........................................20

Operating Conditions .....................................................20

DC Specifications ...........................................................20

Reset Sequence ..............................................................22

Package Diagram ............................................................23

Ordering Information ......................................................24

Ordering Code Definitions .........................................24

Acronyms ........................................................................25

Document Conventions .................................................25

Units of Measure .......................................................25

Document History Page .................................................26

Sales, Solutions, and Legal Information ......................27

Worldwide Sales and Design Support .......................27

Products ....................................................................27

PSoC® Solutions ......................................................27

Cypress Developer Community .................................27

Technical Support .....................................................27

Document Number: 001-87710 Rev. *C

Page 2 of 27

CYUSB202X

2

I C Interface

Functional Overview

SD2 has an I²C interface compatible with the I²C Bus

Specification Revision 3. Because SD2’s I²C interface is capable

of operating only as an I²C master, it may be used to

communicate with other I²C slave devices. For example, SD2

may boot from an EEPROM connected to the I²C interface, as a

selectable boot option.

SD2™ is a USB 2.0 High Speed mass-storage controller

providing the latest SD/MMC support. SD2 complies with the SD

Specification, Version 3.0, and the MMC Specification, Version

4.41.

SD2 offers the following access paths among USB and mass

storage ports:

SD2’s I²C master controller also supports multi-master mode

functionality.

■ A USB-port (U-Port) supporting USB 2.0 peripheral

■ Two mass-storage ports (S0-Port and S1-Port) supporting

mass-storage devices. Following are the possible configura-

tions for the two mass-storage ports:

❐ SD and MMC

❐ SD and SD

❐ MMC and MMC

❐ SD and SDIO

❐ MMC and SDIO

❐ SDIO and SDIO

The power supply for the I²C interface is VIO5, which is a

separate power domain from the other serial peripherals. This is

to allow the I²C interface the flexibility to operate at a different

voltage than the other serial interfaces.

The I²C controller supports bus frequencies of 100 kHz,

400 kHz, and 1 MHz. When VIO5 is 1.2 V, the maximum

operating frequency supported is 100 kHz. When VIO5 is 1.8 V,

2.5 V, or 3.3 V, the operating frequencies supported are 400 kHz

and 1 MHz. The I²C controller supports the clock stretching

feature to enable slower devices to exercise flow control.

Combinations of these accesses can happen independently or

in an interleaved manner.

Both SCL and SDA signals of the I²C interface require external

pull-up resistors. These resistors must be connected to VIO5.

The SD2 complies with the USB 2.0 specification.

UART Interface

USB Interface (U-Port)

The UART interface of SD2 supports full-duplex communication.

It includes the signals noted in Table 1.

SD2 offers the following features:

■ Supports USB peripheral functionality compliant with the USB

2.0 Specification

Table 1. UART Interface Signals

Signal

TX

Description

Output signal

Input signal

Flow control

■ Supports up to 16 IN and 16 OUT endpoints.

■ Supports the USB 2.0 Streams feature. It also supports USB

Attached SCSI (UAS) device class to optimize mass-storage

access performance.

RX

CTS

RTS

■ As a USB peripheral, SD2 supports UAS and Mass Storage

Class (MSC) peripheral classes.

The UART is capable of generating a range of baud rates, from

300 bps to 4608 Kbps, selectable by the firmware. If flow control

is enabled, then SD2’s UART only transmits data when the CTS

input is asserted. In addition to this, SD2’s UART asserts the

RTS output signal, when it is ready to receive data.

■ When the USB port is not in use, the PHY and transceiver may

be disabled for power savings.

Figure 1. USB Interface Signals

SD3

2

I S Interface

VBATT

VBUS

SD2 has an I²S port to support external audio codec devices.

SD2 functions as I²S Master as transmitter only. The I²S

interface consists of four signals: clock line (I2S_CLK), serial

data line (I2S_SD), word select line (I2S_WS), and master

system clock (I2S_MCLK). SD2 can generate the system clock

as an output on I2S_MCLK or accept an external system clock

input on I2S_MCLK.

D-

D+

The sampling frequencies supported by the I²S interface are

32 kHz, 44.1 kHz, and 48 kHz.

Mass-Storage Support (S-Port)

The SD2 storage interface port supports the following

specifications:

■ SD Specification, Version 3.0

■ Multimedia Card-System Specification, MMCA Technical

Committee, Version 4.4

■ SDIO Host controller compliant with SDIO Specification

Version 3.00

Document Number: 001-87710 Rev. *C

Page 3 of 27

CYUSB202X

Clock inputs to SD2 must meet the phase noise and jitter require-

ments specified in Table 4.

SPI Interface

SD2 supports an SPI Master interface on the Serial Peripherals

port. The maximum operation frequency is 33 MHz.

The input clock frequency is independent of the clock/data rate

of SD2 core or any of the device interfaces. The internal PLL

applies the appropriate clock multiply option depending on the

input frequency.

The SPI controller supports four modes of SPI communication

(see SPI Timing Specification on page 18 for details on the

modes) with the Start-Stop clock. This controller is

a

single-master controller with a single automated SSN control. It

supports transaction sizes ranging from 4 bits to 32 bits.

Table 3. Crystal/Clock Frequency Selection

Crystal/Clock

FSLC[2]

FSLC[1]

FSLC[0]

Frequency

Boot Options

0

1

0

1

0

1

0

1

19.2-MHz crystal

19.2-MHz input CLK

26-MHz input CLK

38.4-MHz input CLK

52-MHz input CLK

SD2 can load boot images from various sources, selected by the

configuration of the PMODE pins. The boot options for the SD2

are as follows:

■ Boot from USB

■ Boot from I²C

■ Boot from eMMC on S0-Port

■ Boot from SPI

Table 4. Input Clock Specifications for SD2

Specification

Table 2. Booting Options for SD2

Parameter

Phase noise

Description

Units

Min

–

Max

–75

PMODE[2:0]^[1]

Boot From

S0-Port: eMMC

100-Hz offset

1-kHz offset

10-kHz offset

100-kHz offset

1-MHz offset

dB

FF0

–

–104

–120

–128

–130

150

On failure, USB boot enabled

–

dB

FF1

FFF

USB Boot

I²C

On Failure, USB Boot is enabled

–

dB

–

dB

0FF

0F1

I²C only

Maximumfrequency

deviation

–

ppm

SPI

On Failure, USB Boot is enabled

Duty cycle

30

–

70

3

%

ns

Overshoot

Reset

Undershoot

Rise time/fall time

–

–3

3

A reset is initiated by asserting the Reset# pin on SD2. The

specific reset sequence and timing requirements are detailed in

Figure 3 on page 15 and Table 13 on page 22. All I/Os are

tristated during a hard reset.

–

32-kHz Watchdog Timer Clock Input

SD2 includes a watchdog timer that can be used to interrupt the

core, automatically wake up SD2 in Standby mode, and reset the

core. The watchdog timer runs off a 32-kHz clock, which may

optionally be supplied from an external source on a dedicated

pin of SD2.

Clocking

SD2 allows either a crystal to be connected between the XTALIN

and XTALOUT pins or an external clock to be connected at the

CLKIN pin. The XTALIN, XTALOUT, CLKIN, and CLKIN_32 pins

can be left unconnected if not used.

The watchdog timer can be disabled by firmware.

Crystal frequency supported is 19.2 MHz, while the external

clock frequencies supported are 19.2, 26, 38.4, and 52 MHz.

Requirements for the optional 32-kHZ clock input are listed in

Table 4.

SD2 has an on-chip oscillator circuit that uses an external

19.2 MHz (±100 ppm) crystal (when the crystal option is used).

An appropriate load capacitance is required with a crystal. Refer

to the specification of the crystal used to determine the appro-

priate load capacitance. The FSLC[2:0] pins must be configured

appropriately to select the crystal option/clock frequency option.

The configuration options are shown in Table 3.

Table 5. 32-kHz Clock Input Requirements

Parameter

Duty cycle

Min

40

–

Max

60

Units

%

Frequency deviation

Rise Time/fall Time

±200

200

ppm

ns

–

Note

1. F indicates Floating.

Document Number: 001-87710 Rev. *C

Page 4 of 27

CYUSB202X

Power Modes

Power

SD2 supports the following power modes:

SD2 has the following main groups of power supply domains:

■ Normal mode: This is the full-functional operating mode. In this

mode the internal CPU clock and the internal PLLs are enabled.

■ IO_VDDQ: This refers to a group of independent supply

domains for digital I/Os. The voltage level on these supplies

are 1.8 V to 3.3 V. SD2 provides six independent supply

domains for digital I/Os listed as follows:

❐ VIO2: S0-Port (for SD/MMC) I/O Power Supply Domain

❐ VIO3: S1-Port (for SD/MMC) I/O Power Supply Domain

❐ VIO1: S2-Port (GPIO) Power Supply Domain

❐ VIO4: S1-Port GPIO[53:57]/O Power Supply Domain (these

pins support MMC’s high nibble data line - D[7:4] on S1-Port)

❐ VIO5: I2C Power Supply Domain (supports 1.2 V to 3.3 V)

❐ CVDDQ: Clock Power Supply Domain

Normal operating power consumption does not exceed the sum

of ICC_CORE max and ICC_USB max (see Table 8 on page 12

for current consumption specifications).

The I/O power supplies (VIO2, VIO3, VIO4, and VIO5) may be

turned off when the corresponding interface is not in use.

S2VDDQ cannot be turned off at any time if the S2-Port is used

in the application.

■ SD2 supports four low-power modes (see Table 6 on page 5):

❐ Suspend mode with USB 2.0 PHY enabled (L1 mode)

❐ Suspend mode with USB 2.0 PHY disabled (L2 mode)

❐ Standby mode (L3 mode)

■ VDD: This is the supply voltage for the logic core. The nominal

supply voltage level is 1.2 V. This supplies the core logic

circuits. The same supply must also be used for the following:

❐ AVDD: This is the 1.2-V supply for the PLL, crystal oscillator

and other core analog circuits

❐ Core power-down mode (L4 mode)

■ VBATT/VBUS: This is the 3.2-V to 6-V battery power supply

for the USB I/O and analog circuits. This supply powers the

USB transceiver through SD2’s internal voltage regulator.

VBATT is internally regulated to 3.3 V.

Table 6. Entry and Exit Methods for Low-Power Modes

Low Power Mode

Characteristics

Methods of Entry

Methods of Exit

Suspend mode with ■ The power consumption in this ■ Firmwareexecutingonthecorecan ■ D+ transitioning to low or high

USB 2.0 PHY

Enabled (L1 mode)

mode does not exceed ISB₁

put SD2 into suspend mode. For

example, on USB suspend

condition, firmware may decide to

■ D– transitioning to low or high

■ Resume condition on SSRX +/-

■ Detection of VBUS

■ USB 2.0 PHY is enabled and is in

U3 mode (one of the suspend

modes defined by the USB 3.0

specification). This one block

alone operates with its internal

clock while all other clocks are

shut down

put SD2 into suspend mode

■ Assertion of GPIO[17]

■ Assertion of RESET#

■ All I/Os maintain their previous

state

■ Power supply for the wakeup

source and core power must be

retained.Allotherpowerdomains

can be turned on/off individually

■ The states of the configuration

registers, buffer memory and all

internal RAM are maintained

■ All transactions must be

completed before SD2 enters

Suspend mode (state of

outstanding transactions are not

preserved)

■ The firmware resumes operation

from where it was suspended

(except when woken up by

RESET# assertion) because the

program counter does not reset

Document Number: 001-87710 Rev. *C

Page 5 of 27

CYUSB202X

Table 6. Entry and Exit Methods for Low-Power Modes (continued)

Low Power Mode Characteristics Methods of Entry

Suspend mode with ■ The power consumption in this ■ Firmwareexecutingonthecorecan ■ D+ transitioning to low or high

Methods of Exit

USB 2.0 PHY

disabled (L2 mode)

mode does not exceed ISB₂

put SD2 into suspend mode. For

example, on USB suspend

condition, firmware may decide to

put SD2 into suspend mode

■ D– transitioning to low or high

■ Resume condition on SSRX +/-

■ Detection of VBUS

■ USB 2.0 PHY is disabled and the

USBinterfaceisinsuspendmode

■ The clocks are shut off. The PLLs

are disabled

■ Assertion of GPIO[17]

■ All I/Os maintain their previous

state

■ Assertion of RESET#

■ USB interface maintains the

previous state

■ Power supply for the wakeup

source and core power must be

retained.Allotherpowerdomains

can be turned on/off individually

■ The states of the configuration

registers, buffer memory, and all

internal RAM are maintained

■ All transactions must be

completed before SD2 enters

Suspend mode (state of

outstanding transactions are not

preserved)

■ The firmware resumes operation

from where it was suspended

(except when woken up by

RESET# assertion) because the

program counter does not reset

Document Number: 001-87710 Rev. *C

Page 6 of 27

CYUSB202X

Table 6. Entry and Exit Methods for Low-Power Modes (continued)

Low Power Mode

Characteristics

Methods of Entry

Methods of Exit

Standby Mode (L3

mode)

■ The power consumption in this ■ Firmware executing on the core or ■ Detection of VBUS

mode does not exceed ISB3

external processor configures the

appropriate register

■ Assertion of GPIO[17]

■ Assertion of RESET#

■ All configuration register settings

and program/data RAM contents

are preserved. However, data in

the buffers or other parts of the

data path, if any, is not

guaranteed. Therefore, the

external processor should take

care that needed data is read

before putting SD2 into this

Standby Mode

■ The program counter is reset

after waking up from Standby

■ GPIO pins maintain their

configuration

■ Crystal oscillator is turned off

■ Internal PLL is turned off

■ USB transceiver is turned off

■ Core is powered down. Upon

wakeup, the core re-starts and

runs the program stored in the

program/data RAM

■ Power supply for the wakeup

source and core power must be

retained.Allotherpowerdomains

can be turned on/off individually

Core Power Down

Mode (L4 mode)

■ The power consumption in this ■ Turn off VDD

mode does not exceed ISB₄

■ Reapply VDD

■ Assertion of RESET#

■ Core power is turned off

■ All buffer memory, configuration

registers and the program RAM

do not maintain state. It is

necessary to reload the firmware

on exiting from this mode

■ In this mode, all other power

domains can be turned on/off

individually

Document Number: 001-87710 Rev. *C

Page 7 of 27

CYUSB202X

Configuration Fuse

EMI

Fuse options are available for specific usage models. Contact

Cypress Applications/Marketing for details.

SD2 meets EMI requirements outlined by FCC 15B (USA) and

EN55022 (Europe) for consumer electronics. SD2 can tolerate

reasonable EMI, conducted by aggressor, outlined by these

specifications and continue to function as expected.

Digital I/Os

SD2 provides firmware controlled pull-up or pull-down resistors

internally on all digital I/O pins. The pins can be pulled high

through an internal 50-k resistor or can be pulled low through

an internal 10-k resistor to prevent the pins from floating. The

I/O pins may have the following states:

System Level ESD

SD2 has built-in ESD protection on the D+, D–, GND pins on the

USB interface. The ESD protection levels provided on these

ports are:

■ Tristated (High-Z)

■ ±2.2-KV human body model (HBM) based on JESD22-A114

Specification

■ Weak pull-up (through internal 50 k)

■ Pull down (through internal 10 k)

■ ±6-KV contact discharge and ±8-KV air gap discharge based

on IEC61000-4-2 level 3A

■ Hold (I/O hold its value) when in low power modes

■ ±8-KV contact discharge and ±15-KV air gap discharge based

All unused I/Os should be pulled high by using the internal

pull-up resistors. All unused outputs should be left floating. All

I/Os can be driven at full-strength, three-quarter strength,

half-strength, or quarter-strength. These drive strengths are

configured based on each interface.

on IEC61000-4-2 level 4C.

This protection ensures the device continues to function after

ESD events up to the levels stated.

The S0/S1_INS have up to ±2.2 KV HBM internal ESD

protection.

Pinout for BGA

Figure 2. SD2 BGA Ball Map (Top View)

1

2

3

4

5

6

7

8

9

10

11

U3VSSQ

U3RXVDDQ

SSRXM

SSRXP

SSTXP

SSTXM

VSS

DP

DM

NC

AV DD

A

B

C

D

E

F

G

H

J

VIO4

GPIO[54]

GPIO[50]

GPIO[47]

S0VDDQ

VSS

FSLC[0]

GPIO[55]

GPIO[51]

VSS

R_USB3

VDD

FSLC[1]

GPIO[57]

GPIO[53]

GPIO[49]

GPIO[41]

GPIO[30]

GPIO[31]

GPIO[34]

VSS

U3TXVDDQ

RESET#

GPIO[56]

GPIO[48]

GPIO[46]

GPIO[25]

GPIO[29]

GPIO[28]

GPIO[27]

VDD

CVDDQ

XTALIN

CLKIN_32

FSLC[2]

NC

VSS

OTG_ID

I2C_GPIO[58]

VDD

NC

VIO5

AV SS

XTALOUT

CLKIN

V SS

R_USB2

VSS

V DD

NC

GPIO[52]

S1VDDQ

GPIO[44]

GPIO[43]

GPIO[40]

GPIO[37]

VSS

I2C_GPIO[59]

V BATT

GPIO[0]

GPIO[3]

GPIO[6]

GPIO[8]

GPIO[12]

GPIO[ 11]

O[60]

V BUS

VDD

NC

GPIO[45]

GPIO[42]

GPIO[39]

GPIO[36]

GPIO[33]

VSS

GPIO[2]

GPIO[21]

GPIO[20]

GPIO[19]

GPIO[18]

V D D

GPIO[5]

GPIO[15]

GPIO[24]

GPIO[14]

GPIO[17]

N C

GPIO[1]

GPIO[22]

GPIO[26]

GPIO[16]

GPIO[23]

VSS

GPIO[4]

GPIO[7]

VSS

VDD

S2VDDQ

VDD

GPIO[38]

GPIO[35]

VSS

GPIO[9]

GPIO[13]

S2 V D D Q

GPIO[10]

VSS

K

L

VSS

GPIO[32]

Document Number: 001-87710 Rev. *C

Page 8 of 27

CYUSB202X

Pin Description for BGA

Table 7. Pin List

Pin Power

No. Domain I/O

Name

Description

S2-PORT (GPIO)

F10

F9

VI01

I/O

GPIO[0]

GPIO[1]

GPIO[2]

GPIO[3]

GPIO[4]

GPIO[5]

GPIO[6]

GPIO[7]

GPIO[8]

GPIO[9]

GPIO[10]

GPIO[11]

GPIO[12]

GPIO[13]

GPIO[14]

GPIO[15]

GPIO[16]

GPIO[17]

GPIO[18]

GPIO[19]

GPIO[20]

GPIO[21]

GPIO[22]

GPIO[23]

GPIO[24]

GPIO[25]

GPIO[26]

GPIO[27]

GPIO[28]

GPIO[29]

GPIO[30]

GPIO[31]

GPIO[32]

NC

GPIO

F7

GPIO

G10

G9

F8

GPIO

H10

H9

J10

J9

GPIO

K11

L10

K10

K9

J8

GPIO

G8

J6

GPIO

K8

K7

J7

GPIO

H7

G7

G6

K6

H8

G5

H6

K5

J5

GPIO

H5

G4

H4

L4

GPIO

PMODE[0]

PMODE[1]

PMODE[2]

No Connect

L8

C5 CVDDQ

I

RESET#

Active Low. Hardware Reset.

8b MMC

Configuration

SD+GPIO

Configuration

GPIO

Configuration

K2

J4

K1

J2

J3

J1

VI02

I/O

GPIO[33]

GPIO[34]

GPIO[35]

GPIO[36]

GPIO[37]

GPIO[38]

S0_SD0

S0_SD1

S0_SD2

S0_SD3

S0_SD4

S0_SD5

S0_SD0

S0_SD1

S0_SD2

S0_SD3

GPIO

Document Number: 001-87710 Rev. *C

Page 9 of 27

CYUSB202X

Table 7. Pin List (continued)

Pin Power

No. Domain I/O

Name

Description

GPIO

H2

H3

F4

G2

G3

F3

F2

VI02

I/O

GPIO[39]

GPIO[40]

GPIO[41]

GPIO[42]

GPIO[43]

GPIO[44]

GPIO[45]

S0_SD6

S0_SD7

GPIO

S0_CMD

S0_CLK

S0_WP

S0S1_INS

GPIO

S0_CLK

GPIO

S0_WP

GPIO

S0S1_INS

MMC0_RST_OUT

GPIO

GPIO+

SD+SPI SD+GPIO GPIO UART+I2S

UART+SPI+

8b MMC

SD+UART

S1_SD0

SD+I2S

I2S

F5

E1

E5

E4

D1

D2

D3

D4

C1

C2

D5

C4

C9

A3

A4

A6

A5

VI03

VIO4

I/O

GPIO[46]

GPIO[47]

GPIO[48]

GPIO[49]

GPIO[50]

GPIO[51]

GPIO[52]

GPIO[53]

GPIO[54]

GPIO[55]

GPIO[56]

GPIO[57]

NC

S1_SD0

S1_SD1

S1_SD0

S1_SD1

S1_SD2

S1_SD3

S1_SD0 GPIO

S1_SD1 GPIO

S1_SD2 GPIO

S1_SD3 GPIO

GPIO

S1_SD0 UART_RTS

S1_SD1 UART_CTS

S1_SD1

S1_SD2

S1_SD3

S1_CMD

S1_CLK

S1_WP

GPIO

UART_TX

UART_RX

I2S_CLK

I2S_SD

S1_SD3

S1_CMD

S1_CLK

S1_CMD

S1_CLK

S1_CMD S1_CMD GPIO I2S_CLK

S1_CLK

S1_WP

S1_CLK GPIO

S1_WP GPIO

I2S_SD

I2S_WS

S1_WP

I2S_WS

S1_SD4

UART_RTS

UART_CTS

UART_TX

UART_RX

GPIO

SPI_SCK

SPI_SSN

SPI_MISO

SPI_MOSI

GPIO

GPIO UART_RTS

SPI_SCK

SPI_SSN

SPI_MISO

SPI_MOSI

S1_SD5

GPIO UART_CTS I2S_CLK

S1_SD6

GPIO

GPIO UART_TX

GPIO UART_RX

I2S_SD

I2S_WS

S1_SD7

GPIO

MMC1_RST_OUT

GPIO

GPIO I2S_MCLK I2S_MCLK I2S_MCLK

No Connect

NC

USB 3.0 SuperSpeed Receive Minus

USB 3.0 SuperSpeed Receive Plus

USB 3.0 SuperSpeed Transmit Minus

USB 3.0 SuperSpeed Transmit Plus

USB (HS/FS) Data Plus

NC

A9 VBATT/ I/O

VBUS

D+

A10 VBATT/ I/O

VBUS

D-

USB (HS/FS) Data Minus

No Connect

A11

NC

B2 CVDDQ

I

FSLC[0]

XTALIN

FSLC[0]

C6

C7

AVDD

I/O

XTALIN

I/O

XTALOUT

FSLC[1]

FSLC[2]

CLKIN

XTALOUT

B4 CVDDQ

E6 CVDDQ

D7 CVDDQ

D6 CVDDQ

I

FSLC[1]

FSLC[2]

CLKIN

CLKIN_32

D9

D10

E7

VIO5

I/O I²C_GPIO[58]

I/O I²C_GPIO[59]

SCL (Serial Clock) for I²C Bus Interface

SDA (Serial Data) for I²C Bus Interface

No Connect

NC

C10

B11

E8

No Connect

F6

No Connect

D11

VIO5

O

O[60]

Output only

Document Number: 001-87710 Rev. *C

Page 10 of 27

CYUSB202X

Table 7. Pin List (continued)

Pin Power

No. Domain I/O

Name

Description

E10

B10

A1

E11

D8

H11

E2

L9

PWR

VBATT

VDD

VSS

VBUS

VSS

VIO1

VSS

VIO1

VSS

VIO2

VSS

VIO3

VSS

VIO4

VSS

CVDDQ

NC

G1

F1

G11

E3

L1

B1

L6

B6

B5

A2

C11

L11

A7

B7

C3

B8

E9

B9

F11

H1

L7

NC

PWR

VIO5

VSS

AVDD

AVSS

VDD

VSS

VDD

VSS

VDD

VSS

J11

L5

K4

L3

K3

L2

A8

Precision Resistors

C8

B3

VBUS/

VBATT

I/O

R_usb2

NC

Precision resistor for USB 2.0 (Connect a 6.04 k+/-1% resistor between this pin and GND)

Precision resistor for USB 3.0 (Connect a 200 +/-1% resistor between this pin and GND)

Document Number: 001-87710 Rev. *C

Page 11 of 27

CYUSB202X

AC Timing Parameters

Storage Port Timing

The S0-Port and S1-Port support the MMC Specification Version 4.4 and SD Specification Version 2.0. Table 7 lists the timing

parameters for S0-Port and S1-Port of SD2.

Table 8. S-Port Timing Parameters^[2]

Parameter

Description

Min

Max

Units

MMC-20

MMC-26

MC-HS

tSDIS CMD

Host input setup time for CMD

Host input setup time for DAT

Host input hold time for CMD

Host input hold time for DAT

Host output setup time for CMD

Host output setup time for DAT

Host output hold time for CMD

Host output hold time for DAT

Clock rise time

4.8

4.4

5

–

ns

MHz

%

tSDIS DAT

tSDIH CMD

tSDIH DAT

tSDOS CMD

tSDOS DAT

tSDOH CMD

tSDOH DAT

tSCLKR

–

5

–

5

–

5

–

2

tSCLKF

Clock fall time

–

2

tSDCK

Clock cycle time

50

–

SDFREQ

Clock frequency

20

60

tSDCLKOD

Clock duty cycle

40

tSDIS CMD

tSDIS DAT

tSDIH CMD

tSDIH DAT

tSDOS CMD

tSDOS DAT

tSDOH CMD

tSDOH DAT

tSCLKR

Host input setup time for CMD

Host input setup time for DAT

Host input hold time for CMD

Host input hold time for DAT

Host output setup time for CMD

Host output setup time for DAT

Host output hold time for CMD

Host output hold time for DAT

Clock rise time

10

9

–

ns

MHz

%

–

9

–

3

–

3

–

3

–

3

–

2

tSCLKF

Clock fall time

–

2

tSDCK

Clock cycle time

38.5

–

SDFREQ

Clock frequency

26

60

tSDCLKOD

Clock duty cycle

40

tSDIS CMD

tSDIS DAT

tSDIH CMD

tSDIH DAT

tSDOS CMD

tSDOS DAT

tSDOH CMD

tSDOH DAT

Host input setup time for CMD

Host input setup time for DAT

Host input hold time for CMD

Host input hold time for DAT

Host output setup time for CMD

Host output setup time for DAT

Host output hold time for CMD

Host output hold time for DAT

4

3

–

ns

Document Number: 001-87710 Rev. *C

Page 12 of 27

CYUSB202X

Table 8. S-Port Timing Parameters^[2](continued)

Parameter Description

tSCLKR

Min

–

Max

2

Units

ns

Clock rise time

Clock fall time

tSCLKF

–

2

ns

tSDCK

Clock cycle time

Clock frequency

Clock duty cycle

19.2

–

ns

SDFREQ

tSDCLKOD

52

60

MHz

%

40

MMC-DDR52

tSDIS CMD

tSDIS DAT

tSDIH CMD

tSDIH DAT

tSDOS CMD

tSDOS DAT

tSDOH CMD

tSDOH DAT

tSCLKR

Host input setup time for CMD

Host input setup time for DAT

Host input hold time for CMD

Host input hold time for DAT

Host output setup time for CMD

Host output setup time for DAT

Host output hold time for CMD

Host output hold time for DAT

Clock rise time

4

0.56

3

–

ns

MHz

%

–

2.58

3

–

2.5

3

–

2.5

–

2

tSCLKF

Clock fall time

–

2

tSDCK

Clock cycle time

19.2

–

SDFREQ

Clock frequency

52

55

tSDCLKOD

Clock duty cycle

45

SD-Default Speed (SDR12)

Host input setup time for CMD

tSDIS CMD

tSDIS DAT

tSDIH CMD

tSDIH DAT

tSDOS CMD

tSDOS DAT

tSDOH CMD

tSDOH DAT

tSCLKR

24

2.5

5

–

ns

MHz

%

Host input setup time for DAT

Host input hold time for CMD

Host input hold time for DAT

Host output setup time for CMD

Host output setup time for DAT

Host output hold time for CMD

Host output hold time for DAT

Clock rise time

–

5

–

5

–

5

–

2

tSCLKF

Clock fall time

–

2

tSDCK

Clock cycle time

40

–

SDFREQ

Clock frequency

25

60

tSDCLKOD

Clock duty cycle

40

SD-High-Speed(SDR25)

tSDIS CMD

tSDIS DAT

tSDIH CMD

tSDIH DAT

tSDOS CMD

tSDOS DAT

tSDOH CMD

tSDOH DAT

Host input setup time for CMD

Host input setup time for DAT

Host input hold time for CMD

Host input hold time for DAT

Host output setup time for CMD

Host output setup time for DAT

Host output hold time for CMD

Host output hold time for DAT

4

–

ns

2.5

6

2

Document Number: 001-87710 Rev. *C

Page 13 of 27

CYUSB202X

Table 8. S-Port Timing Parameters^[2](continued)

Parameter Description

tSCLKR

Min

–

Max

2

Units

ns

Clock rise time

Clock fall time

tSCLKF

–

2

ns

tSDCK

Clock cycle time

Clock frequency

Clock duty cycle

20

–

ns

SDFREQ

tSDCLKOD

50

60

MHz

%

40

SD-SDR50

tSDIS CMD

tSDIS DAT

tSDIH CMD

tSDIH DAT

tSDOS CMD

tSDOS DAT

tSDOH CMD

tSDOH DAT

tSCLKR

Host input setup time for CMD

Host input setup time for DAT

Host input hold time for CMD

Host input hold time for DAT

Host output setup time for CMD

Host output setup time for DAT

Host output hold time for CMD

Host output hold time for DAT

Clock rise time

1.5

2.5

3

–

ns

MHz

%

–

3

–

0.8

–

2

tSCLKF

Clock fall time

–

2

tSDCK

Clock cycle time

10

–

SDFREQ

Clock frequency

100

60

tSDCLKOD

Clock duty cycle

40

SD-DDR50

tSDIS CMD

tSDIS DAT

tSDIH CMD

tSDIH DAT

tSDOS CMD

tSDOS DAT

tSDOH CMD

tSDOH DAT

tSCLKR

Host input setup time for CMD

Host input setup time for DAT

Host input hold time for CMD

Host input hold time for DAT

Host output setup time for CMD

Host output setup time for DAT

Host output hold time for CMD

Host output hold time for DAT

Clock rise time

4

0.92

2.5

6

–

ns

MHz

%

–

3

–

0.8

–

2

tSCLKF

Clock fall time

–

2

tSDCK

Clock cycle time

20

–

SDFREQ

Clock frequency

50

55

tSDCLKOD

Clock duty cycle

45

Note

2. All parameters guaranteed by design and validated through characterization.

Document Number: 001-87710 Rev. *C

Page 14 of 27

CYUSB202X

2

I C Interface Timing

I²C Timing

Figure 3. I²C Timing Definition

Table 9. I²C Timing Parameters^[3]

Parameter

Description

I²C Standard Mode Parameters

Min

Max

Units

fSCL

SCL clock frequency

0

4

100

–

kHz

µs

ns

µs

tHD:STA

tLOW

Hold time START condition

LOW period of the SCL

HIGH period of the SCL

4.7

4

–

tHIGH

tSU:STA

tHD:DAT

tSU:DAT

tr

–

Setup time for a repeated START condition

Data hold time

4.7

0

–

Data setup time

250

–

Rise time of both SDA and SCL signals

Fall time of both SDA and SCL signals

Setup time for STOP condition

Bus free time between a STOP and START condition

Data valid time

1000

300

–

tf

–

tSU:STO

tBUF

4

4.7

–

tVD:DAT

tVD:ACK

tSP

3.45

n/a

Data valid ACK

–

Pulse width of spikes that must be suppressed by input filter

n/a

Note

3. All parameters guaranteed by design and validated through characterization.

Document Number: 001-87710 Rev. *C

Page 15 of 27

CYUSB202X

Table 9. I²C Timing Parameters^[3](continued)

Parameter

Description

I²C Fast Mode Parameters

Min

Max

Units

fSCL

SCL clock frequency

0

0.6

1.3

0.6

0

400

–

kHz

µs

ns

µs

ns

tHD:STA

tLOW

Hold time START condition

LOW period of the SCL

HIGH period of the SCL

–

tHIGH

tSU:STA

tHD:DAT

tSU:DAT

tr

–

Setup time for a repeated START condition

Data hold time

–

Data setup time

100

–

Rise time of both SDA and SCL signals

Fall time of both SDA and SCL signals

Setup time for STOP condition

Bus-free time between a STOP and START condition

Data valid time

300

–

tf

–

tSU:STO

tBUF

0.6

1.3

–

tVD:DAT

tVD:ACK

tSP

0.9

50

Data valid ACK

–

Pulse width of spikes that must be suppressed by input filter

0

I²C Fast Mode Plus Parameters (Not supported at I2C_VDDQ=1.2V)

fSCL

SCL clock frequency

0

0.26

0.5

0.26

0

1000

–

kHz

µs

ns

µs

ns

tHD:STA

tLOW

Hold time START condition

LOW period of the SCL

–

tHIGH

tSU:STA

tHD:DAT

tSU:DAT

tr

HIGH period of the SCL

–

Setup time for a repeated START condition

Data hold time

–

Data setup time

50

–

Rise time of both SDA and SCL signals

Fall time of both SDA and SCL signals

Setup time for STOP condition

Bus free time between a STOP and START condition

Data valid time

120

–

tf

–

tSU:STO

tBUF

0.26

0.5

–

tVD:DAT

tVD:ACK

tSP

0.45

0.55

50

Data valid ACK

–

Pulse width of spikes that must be suppressed by input filter

0

Document Number: 001-87710 Rev. *C

Page 16 of 27

CYUSB202X

I²S Timing Diagram

Figure 4. I²S Transmit Cycle

t_T

t_TRt_TF

t_TH

t_TL

SCK

t_Thd

SA,

WS (output)

t_Td

Table 10. I²S Timing Parameters^[4]

Parameter

Description

Min

Max

Units

ns

tT

I²S transmitter clock cycle

I²S transmitter cycle LOW period

Ttr

–

tTL

tTH

tTR

tTF

tThd

tTd

0.35 Ttr

–

ns

I²S transmitter cycle HIGH period

I²S transmitter rise time

0.35 Ttr

ns

–

0

–

0.15 Ttr

–

ns

I²S transmitter fall time

ns

I²S transmitter data hold time

I²S transmitter delay time

ns

0.8tT

ns

Note tT is selectable through clock gears. Max Ttr is designed for 96-kHz codec at 32 bits to be 326 ns (3.072 MHz).

Note

4. All parameters guaranteed by design and validated through characterization.

Document Number: 001-87710 Rev. *C

Page 17 of 27

CYUSB202X

SPI Timing Specification

Figure 5. SPI Timing

SSN

(output)

t_ssnh

t_sck

t_lag

t_lead

SCK

(CPOL=0,

Output)

t_rf

t_wsck

SCK

(CPOL=1,

Output)

t_sdi

t_hoi

LSB

MISO

(input)

MSB

t_d

t_dis

t_sdd

t_di

v

MOSI

(output)

LSB

SPI Master Timing for CPHA = 0

SSN

(output)

t_ssnh

t_sck

t_lag

t_lead

t_rf

SCK

(CPOL=0,

Output)

t_wsck

SCK

(CPOL=1,

Output)

t_hoi

LSB

t_sdi

MISO

(input)

MSB

t_dis

t_di

t_dv

MOSI

(output)

LSB

SPI Master Timing for CPHA = 1

Document Number: 001-87710 Rev. *C

Page 18 of 27

CYUSB202X

Table 11. SPI Timing Parameters^[5]

Parameter

Description

Min

Max

Units

MHz

ns

fop

Operating frequency

Cycle time

0

33

tsck

twsck

tlead

tlag

trf

30

–

Clock high/low time

SSN-SCK lead time

Enable lag time

Rise/fall time

13.5

1/2 tsck^[6]- 5

–

ns

1.5 tsck^[6]+ 5

1.5 tsck^[6]+5

ns

0.5

–

ns

8

5

–

ns

tsdd

tdv

Output SSN to valid data delay time

Output data valid time

–

ns

–

ns

tdi

Output data invalid

0

ns

tssnh

tsdi

thoi

tdis

Minimum SSN high time

Data setup time input

10

8

ns

Data hold time input

0

ns

Disable data output on SSN high

0

ns

Notes

5. All parameters guaranteed by design and validated through characterization.

6. Depends on LAG and LEAD setting in the SPI_CONFIG register.

Document Number: 001-87710 Rev. *C

Page 19 of 27

CYUSB202X

■ ±6-KV contact discharge, ±8-KV air gap discharge based on

IEC61000-4-2 level 3A, ±8-KV contact discharge, and ±15-KV

air gap discharge based on IEC61000-4-2 level 4C

Absolute Maximum Ratings

Exceeding maximum ratings may shorten the useful life of the

device.

Latch-up current ........................................................ > 200 mA

Storage temperature .................................... –65 °C to +150 °C

Maximum output short circuit current

for all I/O configurations. (Vout = 0 V) ........................ –100 mA

Ambient temperature with

power supplied (Industrial) ............................ –40 °C to +85 °C

Operating Conditions

Supply voltage to ground potential

V_DD, A_VDDQ..................................................................... 1.25 V

TA (ambient temperature under bias)

S2_VDDQ,S1_VDDQ, S0_VDDQ, V_IO4, V_IO5.............................. 3.6 V

U3TX_VDDQ, U3RX_VDDQ.................................................. 1.25 V

DC input voltage to any input pin .............................. VCC + 0.3

Industrial ........................................................ –40 °C to +85 °C

V_DD, A_VDDQ, U3TX_VDDQ, U3RX_VDDQ

supply voltage .................................................. 1.15 V to 1.25 V

V_BATTsupply voltage .............................................. 3.2 V to 6 V

DC voltage applied to

outputs in High Z State ............................................. VCC + 0.3

S2_VDDQ, S1_VDDQ, S0_VDDQ, V_IO4, C_VDDQ

supply voltage ...................................................... 1.7 V to 3.6 V

(VCC is the corresponding I/O voltage)

V_IO5supply voltage ............................................ 1.15 V to 3.6 V

Static discharge voltage ESD protection levels:

■ ±2.2-KV human body model (HBM) based on JESD22-A114

■ Additional ESD Protection levels on D+, D–, VBUS, GND pins

U-port and GPIO pins LPP-Port

DC Specifications

Table 12. DC Specifications

Parameter

V_DD

Description

Core voltage supply

Min

Max

1.25

3.6

6

Units

V

Notes

1.2-V typical

1.15

1.7

3.2

4.0

1.7

1.2

A_VDD

V_IO2

Analog voltage supply

V

1.2-V typical

SD/ MMC/ CF I/O power supply domain

SD/MMC I/O power supply domain

GPIO/ CF I/O power supply domain

GPIO/ I/O power supply domain

USB voltage supply

V

1.8-, 2.5-, and 3.3-V typical

3.7-V typical

V_IO3

V

V_IO1

V

V_IO4

V

V_BATT

V_BUS

C_VDDQ

V_IO5

V

USB voltage supply

6

V

5-V typical

Clock voltage supply

I²C voltage supply

3.6

3.3

V

1.8-, 3.3-V typical

V

1.2-,1.8-, 2.5-, and 3.3-V

typical

V_IH1

Input HIGH voltage 1

Input HIGH voltage 2

0.625 × VCC

VCC - 0.4

VCC + 0.3

V

For2.0 V V_CC 3.6 V(except

USB port).VCC is the corre-

sponding I/O voltage supply.

V_IH2

For 1.7 V  V_CC2.0 V

(except USB port). VCC is the

corresponding I/O voltage

supply.

V_IL

Input LOW voltage

–0.3

0.25 × VCC

–

V

VCC is the corresponding I/O

voltage supply.

V_OH

Output HIGH voltage

0.9 × VCC

I_OH(max) = –100 µA tested at

quarter drive strength. VCC is

the corresponding I/O voltage

supply.

V_OL

Output LOW voltage

–

0.1 × VCC

V

I_OL(min) = +100 µA tested at

quarter drive strength. VCC is

the corresponding I/O voltage

supply.

Document Number: 001-87710 Rev. *C

Page 20 of 27

CYUSB202X

Table 12. DC Specifications (continued)

Parameter

Description

Min

Max

Units

Notes

I_IX

Input leakage current for all pins except

SSTXP/SSXM/SSRXP/SSRXM

–1

1

µA

All I/O signals held at V_DDQ

(For I/Os that have a

pull-up/down resistor

connected,theleakagecurrent

increases by V_DDQ/R_puor

V_DDQ/R_PD

I_OZ

OutputHigh-Zleakagecurrentforallpins

except SSTXP/SSXM/SSRXP/SSRXM

–1

–

1

µA

All I/O signals held at VDDQ

I

_CCCore

Core and Analog Voltage Operating

Current

150

mA

Total current through AVDD,

VDD

_CCUSB

I_SB1

USB voltage supply operating current

–

20

–

mA

Total suspend current during Suspend

Mode with USB 3.0 PHY enabled (L1

mode)

Core current: 1.5 mA

I/O current: 20 uA

USB current: 2 mA

For typical PVT (Typical

silicon, all power supplies at

their respective nominal levels

at 25 C.)

I_SB2

Total suspend current during Suspend

Mode with USB 3.0 PHYdisabled (L2

mode)

–

mA

µA

Core current: 250 uA

I/O current: 20 uA

USB current: 1.2 mA

For typical PVT (Typical

silicon, all power supplies at

their respective nominal levels

at 25 C.)

I_SB3

Total Standby Current during Standby

Mode (L3 mode)

Core current: 60 uA

I/O current: 20 uA

USB current: 40 uA

For typical PVT (Typical

silicon, all power supplies at

their respective nominal levels

at 25 C.)

I_SB4

TotalStandbyCurrentduringCorePower

Down Mode (L4 mode)

Core current: 0 uA

I/O current: 20 uA

USB current: 40 uA

For typical PVT (Typical

silicon, all power supplies at

their respective nominal levels

at 25 C.)

V_RAMP

V_N

Voltage Ramp Rate on Core and I/O

Supplies

0.2

–

50

100

20

V/ms

mV

Voltage ramp must be

monotonic

Noise Level Permitted on VDD and I/O

Supplies

Max p-p noise level permitted

on all supplies except A_VDD

V_{N_AVDD}

Noise Level Permitted on AVDD Supply

–

mV

Max p-p noise level permitted

on A_VDD

Document Number: 001-87710 Rev. *C

Page 21 of 27

CYUSB202X

Reset Sequence

The hard reset sequence requirements for SD2 are specified in the following table.

Table 13. Reset and Standby Timing Parameters

Parameter

Definition

Conditions

Clock Input

Crystal Input

Min (ms)

Max (ms)

tRPW

Minimum RESET# pulse width

1

5

1

5

–

tRH

tRR

Minimum high on RESET#

Reset RecoveryTime (after which Boot loader begins

firmware download)

Clock Input

Crystal Input

tSBY

tWU

Time to enter Standby/Suspend (from the time

MAIN_CLOCK_EN/ MAIN_POWER_EN bit is set)

1

Time to wakeup from standby

Clock Input

1

5

–

Crystal Input

tWH

Minimum time before Standby/Suspend source may

be reasserted

Figure 6. Reset Sequence

VDD

( core )

xVDDQ

XTALIN/

CLKIN

XTALIN/ CLKIN must be stable

before exiting Standby/Suspend

tRh

tRR

Mandatory

Reset Pulse

Hard Reset

RESET #

tWH

tWU

tRPW

tSBY

Standby/

Suspend

Source

Standby/Suspend source Is asserted

(MAIN_POWER_EN/ MAIN_CLK_EN bit

is set)

Standby/Suspend

source Is deasserted

Document Number: 001-87710 Rev. *C

Page 22 of 27

CYUSB202X

Package Diagram

Figure 7. 121-ball FBGA (10 × 10 × 1.20 mm) Package Outline, 001-54471

2X

0.10 C

E1

E

B

(datum B)

A1 CORNER

A

11 10

9

8

7

6

5

4

3

2

1

7

A1 CORNER

A

B

C

D

E

F

6

SD

D1

D

(datum A)

G

H

J

K

eD

L

2X

0.10 C

6

eE

TOP VIEW

SE

BOTTOM VIEW

0.20 C

DETAIL A

A1

0.08 C

C

121XØb

5

A

Ø0.15 M C A B

Ø0.08 M C

SIDE VIEW

DETAIL A

NOTES:

1. ALL DIMENSIONS ARE IN MILLIMETERS.

DIMENSIONS

SYMBOL

2. SOLDER BALL POSITION DESIGNATION PER JEP95, SECTION 3, SPP-020.

3. "e" REPRESENTS THE SOLDER BALL GRID PITCH.

MIN.

-

NOM.

MAX.

1.20

-

A

-

4. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D" DIRECTION.

SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION.

N IS THE NUMBER OF POPULATED SOLDER BALL POSITIONS FOR MATRIX

SIZE MD X ME.

A1

D

0.15

-

10.00 BSC

E

10.00 BSC

8.00 BSC

11

D1

E1

MD

ME

N

5.

DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A

PLANE PARALLEL TO DATUM C.

6.

"SD" AND "SE" ARE MEASURED WITH RESPECT TO DATUMS A AND B AND

DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW.

11

121

0.30

WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW,

"SD" OR "SE" = 0.

b

0.25

0.35

eD

eE

SD

SE

0.80 BSC

WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW,

"SD" = eD/2 AND "SE" = eE/2.

0.80 BSC

0.00

A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK

METALIZED MARK, INDENTATION OR OTHER MEANS.

7.

0.00

8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED SOLDER

BALLS.

001-54471 *E

Document Number: 001-87710 Rev. *C

Page 23 of 27

CYUSB202X

Ordering Information

Table 14. Ordering Information

Ordering Code

CYUSB2024-BZXI

CYUSB2025-BZXI

SD/eMMC SDIO Ports

SRAM (KB)

512

Package Type

2

121-ball BGA

512

Ordering Code Definitions

XXX

-

BZ

X

I

X

USB

CY

2

X = blank or T

blank = Tube; T = Tape and Reel

Temperature Range:

I = Industrial

Pb-free

Package Type:

BZ = 121-ball BGA

Marketing Part Number

Base Part Number for USB 2.0

Marketing Code: USB = USB Controller

Company ID: CY = Cypress

Document Number: 001-87710 Rev. *C

Page 24 of 27

CYUSB202X

Acronyms

Document Conventions

Units of Measure

Acronym

ACA

Description

accessory charger adaptor

Symbol

°C

Unit of Measure

BGA

ball grid array

degree Celsius

microamperes

microseconds

milliamperes

Megabytes per second

mega hertz

milliseconds

nanoseconds

ohms

MMC

PLL

multimedia card

µA

µs

phase locked loop

secure digital

SD

mA

Mbps

MHz

ms

ns

SDIO

SLC

secure digital input / output

single-level cell

USB

universal serial bus



pF

pico Farad

V

volts

Document Number: 001-87710 Rev. *C

Page 25 of 27

CYUSB202X

Document History Page

Document Title: CYUSB202X, SD2™ USB and Mass Storage Peripheral Controller

Document Number: 001-87710

Orig. of

Change

Submission

Date

Revision

ECN

Description of Change

**

4016299

4114923

GSZ

05/31/2013 New data sheet.

*A

09/05/2013 Changed status from “Company Confidential” to “Final”.

Updated in new template.

*B

*C

5329287

5708850

RAJV

06/29/2016 Updated the package diagram to current revision.

Updated the Cypress logo and copyright information.

AESATMP7

04/24/2017 Updated Cypress Logo and Copyright.

Document Number: 001-87710 Rev. *C

Page 26 of 27

CYUSB202X

Sales, Solutions, and Legal Information

Worldwide Sales and Design Support

Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office

closest to you, visit us at Cypress Locations.

®

Products

PSoC Solutions

®

ARM Cortex Microcontrollers

Automotive

cypress.com/arm

cypress.com/automotive

cypress.com/clocks

cypress.com/interface

cypress.com/iot

PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP | PSoC 6

Cypress Developer Community

Clocks & Buffers

Interface

Training | Components

Internet of Things

Memory

Technical Support

cypress.com/memory

cypress.com/mcu

cypress.com/support

Microcontrollers

PSoC

cypress.com/psoc

cypress.com/pmic

cypress.com/touch

cypress.com/usb

Power Management ICs

Touch Sensing

USB Controllers

Wireless Connectivity

cypress.com/wireless

including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries

worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other

intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress

hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to

modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users

(either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as

provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation

of the Software is prohibited.

TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE

OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. To the extent

permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any

product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is

the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products

are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or

systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the

device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any component of a device or system whose failure to perform can be reasonably

expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim,

damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other

liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products.

Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in

the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.

Document Number: 001-87710 Rev. *C

Revised April 24, 2017

Page 27 of 27


型号：	CYUSB2024-BZXI
厂家：	Infineon
描述：	EZ-USB™ SD3 USB 5 Gbps存储控制器时钟控制器外围集成电路存储
文件：	总27页 (文件大小：589K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

CYUSB2024-BZXI [INFINEON]

相关型号：

SI9130DB

SI9135LG-T1

SI9135LG-T1-E3

SI9135_11

SI9136_11

SI9130CG-T1-E3

SI9130LG-T1-E3

SI9130_11

SI9137

SI9137DB

SI9137LG

SI9122E