CYUSB4357-BZXC [INFINEON]
EZ-USB™ HX3PD USB 10 Gbps Hub Controller with USB Power Delivery;
| 型号： | CYUSB4357-BZXC |
| 厂家： | 
Infineon |
| 描述： | EZ-USB™ HX3PD USB 10 Gbps Hub Controller with USB Power Delivery 光电二极管 |
| 文件： | 总26页 (文件大小：1066K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Please note that Cypress is an Infineon Technologies Company.
The document following this cover page is marked as “Cypress” document as this is the
company that originally developed the product. Please note that Infineon will continue
to offer the product to new and existing customers as part of the Infineon product
portfolio.
Continuity of document content
The fact that Infineon offers the following product as part of the Infineon product
portfolio does not lead to any changes to this document. Future revisions will occur
when appropriate, and any changes will be set out on the document history page.
Continuity of ordering part numbers
Infineon continues to support existing part numbers. Please continue to use the
ordering part numbers listed in the datasheet for ordering.
www.infineon.com
CYUSB4347
CYUSB4357
HX3PD USB 3.1 Gen 2 Type-C Hub
with PD
HX3PD USB 3.1 Gen
2 Type-C Hub with PD
Functional Description
HX3PD is a family of USB 3.1 Gen 2 Type-C hub with USB Power Delivery (PD) that complies with the USB 3.1 Gen 2 (10 Gbps)
specification, and the latest Type-C and PD standards. HX3PD supports SuperSpeed USB (10 Gbps), SuperSpeed (5 Gbps),
High-Speed (HS), Full-Speed (FS), and Low-Speed (LS) on selective ports. HX3PD provides a complete Type-C and USB PD port
controller solution in Upstream (US) and one Downstream (DS) port.
HX3 USB 3.0 Hub
■ Upstream: Configurable as either Type-C or Type-B port
Features
■ Downstream: Configurable as either three Type-C and four
Type-A ports, or seven Type-A ports
■ USB-IF CertifiedUSB3.1 Gen 2 HubSilicon, TID#5030000008
■ USB 3.1 Gen 2-compliant Hub Controller with 7 downstream
ports
■ Compound USB PD hub with integrated USB device controller
support:
❐ USB Billboard
❐ In-system firmware upgrade
❐ Vendor specific messaging
❐ Five downstream ports support SS (10 Gbps), SS (5 Gbps),
and are backward-compatible with HS (480 Mbps),
FS (12 Mbps), and LS (1.5 Mbps)
❐ Two downstream ports support HS, and are
backward-compatible with FS, and LS
■ Integrated Dock Management Controller support
❐ Signed and unsigned firmware updates
❐ Firmware upgrade over USB
❐ SS (10 Gbps), SS (5 Gbps) and USB 2.0 Link Power
Management (LPM)
❐ Dedicated Hi-Speed Transaction Translators (Multi-TT)
❐ Dynamic configurations of port enable and disable from
Embedded Controllers over I2C
■ Integrated Type-C transceivers, supporting Type-C plug
orientation
■ Charging Standard support:
❐ USB PD 3.0, Battery Charging v1.2 and Apple Charging
Standards
❐ Type-C supported in four ports (1 US port and 3 DS ports)
❐ Integrated transceiver (baseband PHY)
❐ Integrated UFP (RD), and current sources for DFP (RP)
■ PD policy engine configures power profiles dynamically
■ Ghost Charge™: Charging DS port without US connection
■ 192-ball BGA (12 mm × 12 mm, 0.8-mm ball-pitch)
■ Integrated PD controllers, supporting PD 3.0 specification in
US port and 1 DS port
Block Diagram
UPSTREAM PORT
5V
1.2V
1.0V
1.0V
3.3V
1.8V
USB 2.0 Specific
1.2V to 1.0V
Regulator
3.3V to 1.8V
Regulator
CC/PD
CONTROL
USB2.0
PHY
USB 3.1 Specific
USB3.1 PHY
25
MHz
PLL
SPI
PD PORT1
R
SPI I/F
DEBUG
FLASH
SWDCLK
SWDDIO
UPSTREAM PORT CONTROL
F
L
A
S
H
UPSTREAM PORT CONTROL
A
M
CPU
HUB CONTROLLER
TRANSACTION
HUB CONTROLLER
PD PORT2
F
L
A
S
H
R
A
M
I2C/
GPIOs
CPU
TRANSLATORS
REPEATER
ROUTER/AGGREATER ENGINE
CPU
ADC/DAC
POWER
MANAG
EMENT
ROUTING LOGIC
UPSTREAM
BUFFERS
DOWNSTREAM
BUFFERS
RAM ROM
DOCK
MANAGEMENT
CONTROLLER
BATTERY CHARGING CONTROL
CRYPTO
BLOCK
ROUTING LOGIC
USB2.0
PHY
CC/PD
CONTROL
USB2.0
PHY
CC
CONTROL
USB2.0
PHY
CC
CONTROL
USB2.0 USB3.1
PHY PHY
USB2.0 USB3.1
PHY PHY
USB2.0
PHY
USB2.0
PHY
USB3.1 PHY
USB3.1 PHY
USB3.1 PHY
PORT1
PORT2
PORT3
PORT4
PORT5
PORT6
PORT7
Cypress Semiconductor Corporation
Document Number: 002-16615 Rev. *I
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised March 19, 2021
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Contents
Architecture Overview .....................................................3
SS (10 Gbps) Hub Controller ......................................3
USB 2.0 Hub Controller ...............................................3
USB-PD Controller ......................................................3
SPI, I2C, and GPIO Interfaces ....................................3
Dock Management Controller ......................................3
Crypto Block ................................................................4
Application Diagrams .......................................................4
Docking Stations .........................................................4
HX3PD Product Options ..................................................6
Pinouts ..............................................................................6
Pin Description .................................................................7
System Interfaces ...........................................................12
Upstream Port (US) ...................................................12
Downstream Ports (DS1, 2, 3, 4, 5, 6, 7) ..................12
Communication Interfaces .........................................12
Configuration Options ................................................13
Absolute Maximum Ratings ..........................................15
Electrical Specifications ................................................15
DC Electrical Characteristics .....................................15
Power Consumption.................................................. 16
Ordering Information...................................................... 17
Ordering Code Definitions .........................................17
Package Diagram ............................................................18
Silicon Revision History ................................................19
Method of Identification .............................................19
Acronyms ........................................................................20
Reference Documents ....................................................20
Document Conventions ................................................. 20
Units of Measure .......................................................20
Errata ...............................................................................21
Document History Page .................................................22
Sales, Solutions, and Legal Information ......................25
Worldwide Sales and Design Support .......................25
Products ....................................................................25
PSoC® Solutions ......................................................25
Cypress Developer Community .................................25
Technical Support ..................................................... 25
Document Number: 002-16615 Rev. *I
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The CPU in HX3PD's USB-PD controller is a Cortex-M0 32-bit
MCU controller, which is optimized for low-power operation with
extensive clock gating. It includes a nested vectored interrupt
controller (NVIC) block with 32 interrupt inputs and also includes
a Wakeup Interrupt Controller (WIC). The WIC can wake the
processor up from the Deep Sleep mode, allowing power to be
switched off to the main processor when the chip is in the Deep
Sleep mode. The Cortex-M0 CPU provides a Non-Maskable
Interrupt (NMI) input, which is made available to the user when
it is not in use for system functions requested by the user. The
CPU also includes a serial wire debug (SWD) interface, which is
a two-wire form of JTAG.
Architecture Overview
The Block Diagram on page 1 shows the HX3PD architecture.
HX3PD consists of two independent hub controllers (SS (10
Gbps) and USB 2.0), the Arm® Cortex®-M0 CPU subsystem,
2-port USB-PD controllers, Dock Management Controller
(DMC), SPI interface, Serial communication block, and GPIOs.
SS (10 Gbps) Hub Controller
This block supports the SS (10 Gbps) hub functionality based on
the USB 3.1 Gen 2 (10 Gbps) specification. The SS (10 Gbps)
hub controller supports the following:
2
■ USB precision time management (PTM)
■ Link power management (U0, U1, U2, U3 states)
■ Store and forward packet architecture
■ Full-duplex data transmission
SPI, I C, and GPIO Interfaces
HX3PD has dedicated SPI flash interfaces, used for
downloading configuration/firmware of the hub during boot-up.
HX3PD has dedicated I2C interfaces for Hub, DMC, and PD
controllers. These I2C interfaces shall be used for configurations
of individual blocks, communication between individual blocks,
and/or interface with external controllers.
USB 2.0 Hub Controller
This block supports the LS, FS, and HS hub functionalities. It
includes the repeater, frame timer, and seven transaction trans-
lators. The USB 2.0 hub controller block supports the following:
HX3PD contains many GPIOs which can be configured as input,
output to support custom features, these I/Os can be used for
serial communication with external master/slave devices. The
serial communication protocols supported are I2C, SPI, and
UART.
■ USB 2.0 link power management (L0, L1, L2, L3 states)
■ Suspend, resume, and remote wake-up signaling
■ Multi-TT (one TT for each DS port)
Dock Management Controller
The hub is also integrated with USB device, which can function
as a DMC and USB Billboard.
Dock Management Controller (DMC) integrates a Full-Speed
USB controller that is designed for managing the USB dock
system. DMC supports USB Billboard as well as firmware
download over USB to externally interfaced peripherals (over
I2C/SPI).
USB-PD Controller
HX3PD supports two USB PD ports, consisting of USB Type-C
baseband transceivers and physical-layer logic. The USB-PD
PHY consists of a transmitter and receiver that communicate
Biphase Mark Coding (BMC) and 4b/5b encoded data over the
CC channel based on the PD 3.0 standard. In addition, the
USB-PD block includes all termination resistors (RP and RD) as
required by the USB Type-C spec. RP and RD resistors are
required to implement connection detection, plug orientation
detection, and for establishing the USB source/sink roles.
Firmware Update Support
DMC has the capability to do firmware update to Hub controller,
PD controller, DMC, and other dock components. It implements
the firmware update functionality and status reporting on a
vendor interface using a full-speed USB 2.0 device controller.
Unsigned Firmware Update
The firmware update procedure expects the host to send the
metadata of the programmable component’s FW information.
The integrated RP resistor enables the PD port to be configured
as a DFP. The RP resistor is implemented as a current source
and can be programmed to support the complete range of
current capacity on the VBUS defined in the USB Type-C Spec.
This metadata includes SHA-256 of the individual firmware
image. DMC notifies the host to send the individual component’s
firmware image one by one and update to the dock components.
DMC verifies the firmware validity by comparing the received
SHA-256 with the calculated SHA-256 of the firmware received.
The RD resistor is used to identify the HX3PD port as a UFP in
a DRP application. The RD resistor on the CC pins is required
even when the part is not powered for dead battery termination
detection and charging. HX3PD’s PD ports respond to all
USB-PD communication.
Signed Firmware Update
The signed firmware update follows the same procedure as the
unsigned firmware update but is uses RSA-2018/SHA-256 for
signing.
HX3PD is designed to be fully interoperable with revision 3.0 as
well as revision 2.0 of the USB PD specification. HX3PD
supports Extended Messages containing data up to 260 bytes.
The Extended Messages will be larger than expected by the
USB-PD 2.0 hardware. To accommodate Revision 2.0 based
systems, a Chunking mechanism is implemented such that
Messages are limited to Revision 2.0 sizes unless it is
discovered that both systems support the longer Message
lengths.
Contact Cypress customer support for more information on the
signed firmware update.
Document Number: 002-16615 Rev. *I
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Crypto Block
Application Diagrams
HX3PD integrates a Crypto block for hardware assisted
authentication of firmware images. It supports field
upgradeability of firmware in a trusted ecosystem. The Crypto
block provides cryptography functionality. It includes hardware
acceleration blocks for Advanced Encryption Standard (AES)
block cipher, Secure Hash Algorithm (SHA), Cyclic Redundancy
Check (CRC), and pseudo random number generation.
Docking Stations
Figure 1 and Figure 2 show USB-C Dock design application
diagrams using HX3PD.
HX3PD integrates five chips (two 4-port USB Hubs, two USB-PD
controllers, and Dock Management controller) in typical dock
designs to a single chip; significantly reducing BOM and design
complexity. HX3PD Dock solution provides seven downstream
ports (five USB 3.1 Gen 2, and two USB 2.0) and supports PD
3.0, BC 1.2, and Apple charging standards. It also supports
signed firmware upgrades via DMC, thereby enable to keep pace
with future specification changes.
Figure 1. USB-C Dock for Notebook PCs
DP
DP Multi-
Stream
Hub
DP/SS
MUX
DP
DP-to-HDMI
Converter
DP
HDMI
DP
DS1
DS2
PC
or
USB 3.1 Gen 2
USB
Type-C + PD
Tablet
SS
SS
USB 2.0
USB 3.1 Gen 2
USB 3.1 Gen 2
USB 3.1 Gen 2
USB 2.0
USB Type-C
USB Type-C
USB Type-A
USB Type-A
US
USB 3.1
Gen 2
Type-C
+ PD
HX3PD
DS3
DS4
DS7
USB 3.1 Gen 2
DS5
DS6
USB 2.0
USB GigE
Controller
USB Audio
Controller
Audio In/Out
Gigabit Ethernet
Document Number: 002-16615 Rev. *I
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Figure 2. Thunderbolt Dock for Notebook PCs
DP
Thunder -
bolt
Controller
DP Multi-
Stream
Hub
DP
TB3
DP-to-HDMI
Converter
HDMI
DP
DS1
DS2
PC
or
Tablet
USB 3.1 Gen 2
USB
Type-C + PD
I2C
US
USB 3.1 Gen 2
USB 3.1 Gen 2
USB 3.1 Gen 2
USB 3.1 Gen 2
USB 2.0
USB Type-C
USB Type-C
CCG5
USB PD
Controller
HX3PD DS3
DS4
CC
USB Type-A
USB Type-A
USB 3.1 Gen 2
DS6
DS7
DS5
USB 2.0
USB GigE
Controller
USB Audio
Controller
Audio In/Out
Gigabit Ethernet
Document Number: 002-16615 Rev. *I
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HX3PD Product Options
Table 1. HX3PD Product Options
Marketing
Application
Part Number
No of DS US PD
DS PD LegacyCharging
USB
SignedFW
Package
Ports
Port
Port
on DS
Billboard Download
CYUSB4347
Docking Station,
Monitor
7
DRP
DFP
Yes
Yes
No
192-Ball BGA
CYUSB4357
Docking Station,
Monitor
7
DRP
DFP
Yes
Yes
Yes
192-Ball BGA
Pinouts
Figure 3. 192-Ball BGA Pin Diagram
1
2
3
4
5
6
7
8
9
10
11
12
13
14
–
DM_P7
DP_P7
VBUS_- VDDD_P
XIN
XOUT
HPD_P1 I2C_SCL2 SPI_MIS DMC_P24 DM_P6
O_DMC
DP_P6
–
A
B
C
D
E
DISCHAR
GE_P1
D
DM_P1
DP_P1
CC2_P0 SWDCLK VBUS_M VCCD_P VSEL_ VSEL_GPI I2C_SDA2 SPI_SS_ DMC_P25 DMC_P2 DM_P2
_PD ON_P1 GPIO3 O4 DMC
DP_P2
D
6
TXP1_P1 TXN1_P1 VDDIO
V5P0_P0 VBUS_C_ OCP_DE CC2_P1 VCONN_M VDDD_DM SWDIO_ XRES_D VDDIO TXP2_P2 TXN2_P2
CTRL_P1
T_P1
ON_P1/PD
_P27
C
DMC
MC
RXP1_P1 RXN1_P1 CC1_P0 VBUS_M VSEL_GP VBUS_P_ V5P0_P CC1_P1 VCCD_DM SWDCLK I2C_SDA SPI_CLK RXP2_P2 RXN2_P2
ON_P0
IO1
CTRL_P1
1
C
_DMC
1
_DMC
RXN2_P1 RXP2_P1 PD_P15 VBUS_P_ HPD_P0 VBUS_-
V5P0
AVDD33 PWREN_P PGANG I2C_SCL1 DMC_P3 RXN1_P2 RXP1_P2
CTRL_P0
DISCHAR
GE_P0
2
2
TXN2_P1 TXP2_P1 SWDIO_P DVDD10 VSEL_GP
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
OVCUR_ DVDD10 SPI_MO TXN1_P2 TXP1_P2
F
G
H
J
D
IO2
P2
SI_DMC
TXP_P5 TXN_P5
V3P3
V1P0_P7 OCP_DE
T_P0
GND
I2C_S-
DA_HUB
V1P0_P6
V3P3
RXN_P4 RXP_P4
RXP_P5 RXN_P5 V1P0_P1 VBUS_C_ SPI_MOS
CTRL_P0 I_HUB
GND
OVCUR_ V1P0_P2 V1P0_P2 TXN_P4 TXP_P4
P6
DP_P5
DM_P5 V1P0_P1 DVDD10 SPI_MIS PWREN_
O_HUB P1
GND
PWREN_ DVDD10 VDDIO
P6
DM_P4
DP_P4
DM_P0
DP_P0
V1P0_P5 XRES_P VCONN_ OVCUR_ SPI_CL AVDD10
CC1_P2
CC2_P2
PSELF V1P0_P4 DM_P3
DP_P3
K
D
MON_P0/
PD_P24
P1
K_HUB
TXP1_P0 TXN1_P0
RXP1_P0 RXN1_P0
V3P3
V3P3
V1P0_P0 OVCUR_ PWREN_ OVCUR CC1_P3
CC2_P3
CHIPEN
VDDIO
V1P0_P3
V3P3
TXP2_P3 TXN2_P3
L
M
N
P
P5
P5
_P4
V1P0_P0
I2C_S-
CL_HUB
SPI_SS_ VBUS RESET_H
RTERM OVCUR_ V1P0_P3 RXP2_P3 RXN2_P3
P7
HUB
UB
RXN2_P0 RXP2_P0 PWREN_ V1P0_ME V1P0_ME
V1P2
GPIO4_ V1P0_PHY V1P0_PHY
HUB
FB
PWREN_ OVCUR_ RXP1_P3 RXN1_P3
P3 P3
P4
M_B
M_A
–
TXN2_P0 TXP2_P0
V1P2
V1P2
V1P2
GPIO3_ V1P0_PHY V1P0_PHY V3P3_RE PWREN_ TXP1_P TXN1_P3
HUB P7
–
G
3
Document Number: 002-16615 Rev. *I
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Refer to the Application Note “AN222944 - HX3PD Hardware Design Guidelines and Checklist” for recommendation on individual pin
schematics.
Pin Description
No.
Pin Name
Type
Pin Number
Description
Upstream Port USB Signals
1
2
DP_P0
I/O
I/O
O
O
I
K2
K1
L1
Upstream port USB 2.0 data plus
DM_P0
Upstream port USB 2.0 data minus
3
TXP1_P0
TXN1_P0
RXP1_P0
RXN1_P0
TXP2_P0
TXN2_P0
RXP2_P0
RXN2_P0
Upstream port, SuperSpeed transmit plus lane 1
Upstream port, SuperSpeed transmit minus lane 1
Upstream port, SuperSpeed receive plus lane 1
Upstream port, SuperSpeed receive minus lane 1
Upstream port, SuperSpeed transmit plus lane 2
Upstream port, SuperSpeed transmit minus lane 2
Upstream port, SuperSpeed receive plus lane 2
Upstream port, SuperSpeed receive minus lane 2
4
L2
5
M1
M2
P3
P2
N2
N1
6
I
7
O
O
I
8
9
10
I
Downstream Port1 USB Signals
11
12
13
14
15
16
17
18
19
20
DP_P1
I/O
I/O
O
O
I
B2
B1
C1
C2
D1
D2
F2
F1
E2
E1
Downstream port1, USB 2.0 data plus
DM_P1
Downstream port1, USB 2.0 data minus
TXP1_P1
TXN1_P1
RXP1_P1
RXN1_P1
TXP2_P1
TXN2_P1
RXP2_P1
RXN2_P1
Downstream port1, SuperSpeed transmit plus lane 1
Downstream port1, SuperSpeed transmit minus lane 1
Downstream port1, SuperSpeed receive plus lane 1
Downstream port1, SuperSpeed receive minus lane 1
Downstream port1, SuperSpeed transmit plus lane 2
Downstream port1, SuperSpeed transmit minus lane 2
Downstream port1, SuperSpeed receive plus lane 2
Downstream port1, SuperSpeed receive minus lane 2
I
O
O
I
I
Downstream Port2 USB Signals
21
22
23
24
25
26
27
28
29
30
DP_P2
I/O
I/O
O
O
I
B14
B13
F14
F13
E14
E13
C13
C14
D13
D14
Downstream port2, USB 2.0 data plus
DM_P2
Downstream port2, USB 2.0 data minus
TXP1_P2
TXN1_P2
RXP1_P2
RXN1_P2
TXP2_P2
TXN2_P2
RXP2_P2
RXN2_P2
Downstream port2, SuperSpeed transmit plus lane 1
Downstream port2, SuperSpeed transmit minus lane 1
Downstream port2, SuperSpeed receive plus lane 1
Downstream port2, SuperSpeed receive minus lane 1
Downstream port2, SuperSpeed transmit plus lane 2
Downstream port2, SuperSpeed transmit minus lane 2
Downstream port2, SuperSpeed receive plus lane 2
Downstream port2, SuperSpeed receive minus lane 2
I
O
O
I
I
Downstream Port3 USB Signals
31
32
33
DP_P3
DM_P3
I/O
I/O
O
K14
K13
P12
Downstream port3, USB 2.0 data plus
Downstream port3, USB 2.0 data minus
Downstream port3, SuperSpeed transmit plus lane 1
TXP1_P3
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Pin Description (continued)
No.
34
35
36
37
38
39
40
Pin Name
TXN1_P3
RXP1_P3
RXN1_P3
TXP2_P3
TXN2_P3
RXP2_P3
RXN2_P3
Type
Pin Number
P13
Description
O
I
Downstream port3, SuperSpeed transmit minus lane 1
Downstream port3, SuperSpeed receive plus lane 1
Downstream port3, SuperSpeed receive minus lane 1
Downstream port3, SuperSpeed transmit plus lane 2
Downstream port3, SuperSpeed transmit minus lane 2
Downstream port3, SuperSpeed receive plus lane 2
Downstream port3, SuperSpeed receive minus lane 2
N13
I
N14
O
O
I
L13
L14
M13
I
M14
Downstream Port4 USB Signals
41
42
43
44
45
46
DP_P4
DM_P4
I/O
I/O
O
O
I
J14
J13
Downstream port4, USB 2.0 data plus
Downstream port4, USB 2.0 data minus
Downstream port4, SuperSpeed transmit plus
Downstream port4, SuperSpeed transmit minus
Downstream port4, SuperSpeed receive plus
Downstream port4, SuperSpeed receive minus
TXP_P4
TXN_P4
RXP_P4
RXN_P4
H14
H13
G14
G13
I
Downstream Port5 USB Signals
47
48
49
50
51
52
DP_P5
DM_P5
I/O
I/O
O
O
I
J1
J2
Downstream port5, USB 2.0 data plus
Downstream port5, USB 2.0 data minus
Downstream port5, SuperSpeed transmit plus
Downstream port5, SuperSpeed transmit minus
Downstream port5, SuperSpeed receive plus
Downstream port5, SuperSpeed receive minus
TXP_P5
TXN_P5
RXP_P5
RXN_P5
G1
G2
H1
H2
I
Downstream Port6 USB Signals
53
54
DP_P6
DM_P6
I/O
I/O
A13
A12
Downstream port6, USB 2.0 data plus
Downstream port6, USB 2.0 data minus
Downstream Port7 USB Signals
55
56
DP_P7
DM_P7
I/O
I/O
A3
A2
Downstream port7, USB 2.0 data plus
Downstream port7, USB 2.0 data minus
USB Port Control Signals
57
58
59
60
61
62
63
64
65
66
67
68
OVCUR_P1
I
I
K6
F10
N12
L7
Downstream port1, Active low Over current detect
Downstream port2, Active low Over current detect
Downstream port3, Active low Over current detect
Downstream port4, Active low Over current detect
Downstream port5, Active low Over current detect
Downstream port6, Active low Over current detect
Downstream port7, Active low Over current detect
Downstream port1, Active low Power enable
Downstream port2, Active low Power enable
Downstream port3, Active low Power enable
Downstream port4, Active low Power enable
Downstream port5, Active low Power enable
OVCUR_P2
OVCUR_P3
OVCUR_P4
OVCUR_P5
OVCUR_P6
OVCUR_P7
PWREN_P1
PWREN_P2
PWREN_P3
PWREN_P4
PWREN_P5
I
I
I
L5
I
H10
M11
J6
I
O
O
O
O
O
E9
N11
N3
L6
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Pin Description (continued)
No.
69
Pin Name
PWREN_P6
PWREN_P7
VBUS
Type
Pin Number
Description
O
O
I
J10
P11
M7
Downstream port6, Active low Power enable
Downstream port7, Active low Power enable
Upstream VBUS input
70
71
Upstream PD Control
72
73
VBUS_MON_P0
A
D4
E4
GPIO used as VBUS monitor for Upstream PD port
VBUS_P_CTRL_P0
I/O
GPIO used for controlling provider power switch of
Upstream PD port
74
75
VBUS_C_CTRL_P0
I/O
I/O
H4
E6
GPIO used for controlling consumer power switch of
Upstream PD port
VBUS_DISCHARGE_P0
GPIO for controlling VBUS discharge switch of
Upstream PD port
Downstream PD Control
76
77
VBUS_MON_P1
A
B5
D6
GPIO used as VBUS monitor for Downstream PD port
VBUS_P_CTRL_P1
I/O
GPIO used for controlling provider power switch of
Downstream PD port
78
79
VBUS_C_CTRL_P1
I/O
I/O
C5
A4
GPIO used for controlling consumer power switch of
Downstream PD port
VBUS_DISCHARGE_P1
GPIO for controlling VBUS discharge switch of
Downstream PD port
Type-C PD Control Signals
80
81
CC1_P0
CC1_P1
A
A
D3
D8
Upstream port connect detect/Configuration Channel 1
Downstream port1 connect detect/Configuration
Channel 1
82
83
CC1_P2
CC1_P3
A
A
K9
L8
Downstream port2 connect detect/Configuration
Channel 1
Downstream port3 connect detect/Configuration
Channel 1
84
85
CC2_P0
CC2_P1
A
A
B3
C7
Upstream port connect detect/Configuration Channel 2
Downstream port1 connect detect/Configuration
Channel 2
86
87
CC2_P2
CC2_P3
A
A
K10
L9
Downstream port2 connect detect/Configuration
Channel 2
Downstream port3 connect detect/Configuration
Channel 2
88
89
OCP_DET_P0
OCP_DET_P1
I
I
G5
C6
Over current detection input for upstream Type-C port
Over current detection input fordownstreamType-C port
1
90
91
VSEL_GPIO1
VSEL_GPIO2
I/O
I/O
D5
F5
GPIO for selecting VBUS voltage level of PD ports;
When used for I2C interface, this pin must be used as
I2C_MASTER_SDA.
GPIO for selecting VBUS voltage level of PD ports;
When used for I2C interface, this pin must be used as
I2C_MASTER_SCL.
92
93
VSEL_GPIO3
VSEL_GPIO4
I/O
I/O
B7
B8
GPIO
GPIO
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Pin Description (continued)
No.
Pin Name
Type
Pin Number
Description
SPI, I2C, and GPIOs
94
95
SPI_CLK_HUB
O
K7
M6
SPI clock. Connect to SPI EEPROM
SPI select. Connect to SPI EEPROM
SPI data in. Connect to SPI EEPROM
SPI data out. Connect to SPI EEPROM
SPI data in. This SPI interface from DMC block
SPI slave select. This SPI interface from DMC block
SPI data out. This SPI interface from DMC block
SPI clock. This SPI interface from DMC block
I2C clock - 1; Connected to DMC (I2C master)
I2C data - 1; Connected to DMC (I2C master)
I2C clock - 2; Connected to DMC (I2C slave)
I2C data - 2; Connected to DMC (I2C slave)
I2C clock, Connected to Hub controller (I2C slave) block
I2C data, Connected to Hub controller (I2C slave) block
GPIO from Hub
SPI_SS_HUB
SPI_MISO_HUB
SPI_MOSI_HUB
SPI_MISO_DMC
SPI_SS_DMC
SPI_MOSI_DMC
SPI_CLK_DMC
I2C_SCL1
O
96
I
J5
97
O
H5
98
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
A10
B10
F12
D12
E11
D11
A9
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
I2C_SDA1
I2C_SCL2
I2C_SDA2
B9
I2C_SCL_HUB
I2C_SDA_HUB
GPIO3_HUB
GPIO4_HUB
DMC_P24
M5
G10
P7
N7
GPIO from Hub
A11
B11
B12
E12
E5
GPIO
DMC_P25
GPIO
DMC_P26
GPIO
DMC_P32
GPIO
HPD_P0
GPIO used as Hot plug detect input from DisplayPort
(DP) of Upstream PD port
115
HPD_P1
I/O
A8
GPIO used as Hot plug detect output to DP of
Downstream PD port
116
117
PD_P15
I/O
I/O
E3
K5
GPIO
GPIO
VCONN_MON_P0/PD_P2
4
118
VCONN_MON_P1/PD_P2
7
I/O
C8
GPIO
Clock, Reset, Debug, and Mode Select
119
120
121
XIN
A
A
I
A6
A7
M9
Crystal In
XOUT
Crystal Out
CHIPEN
Chip enable, Recommend to connect it HIGH. Chip has
a weak internal pull-up.
122
123
124
125
126
127
RESET_HUB
XRES_DMC
XRES_PD
I
M8
C11
K4
Active Low reset input of hub controller
Active Low reset input of DMC
Active Low reset input of PD controller
SWD clock input for DMC
I
I
SWDCLK_DMC
SWDIO_DMC
SWDCLK_PD
I/O
I/O
I/O
D10
C10
B4
SWD data I/O for DMC
SWD clock input for PD controller
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Pin Description (continued)
No.
128
129
Pin Name
SWDIO_PD
PSELF
Type
I/O
I
Pin Number
Description
F3
SWD data I/O for PD controller
K11
Self/Bus power mode: This pin must be pulled HIGH for
SELF power mode and pulled LOW for BUS power
mode.
130
131
PGANG
RTERM
I
E10
M10
Gang/Individual mode: This pin must be pulled HIGH for
GANG mode and pulled LOW for INDIVIDUAL mode.
A
Connect this pin to a precision resistor (20 kΩ ±1%)
Ground, Power, and NC
132
133
AVDD10
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
GND
K8
1.0-V Input (1.0-V power for Analog)
3.3-V Input (3.3-V power for Analog)
1.0-V Input (1.0-V power for Digital)
Reserved. Connect this pin to Ground.
Regulator output of DMC
AVDD33
DVDD10
FB
E8
134–137
138
F4, F11, J4, J11
N10
D9
139
VCCD_DMC
VCCD_PD
VDDIO
140
B6
Regulator output of PD controller
141–144
145
C3, C12, L10, J12 3.3-V I/O supply
VDDD_DMC
VDDD_PD
V1P0_MEM_A
V1P0_MEM_B
V1P0_P0
V1P0_P1
V1P0_P2
V1P0_P3
V1P0_P4
V1P0_P5
V1P0_P6
V1P0_P7
V1P0_PHY
V1P2
C9
A5
3.3-V supply for DMC
146
3.3-V supply for PD controller
1.0-V supply for internal memory
1.0-V supply for internal memory
1.0-V supply for US port
1.0-V supply for port 1
147
N5
148
N4
149–150
151–152
153–154
155–156
157
L4, M4
J3, H3
H12, H11
M12, L11
K12
1.0-V supply for port 2
1.0-V supply for port 3
1.0-V supply for port 4
158
K3
1.0-V supply for port 5
159
G11
1.0-V supply for port 6
160
G4
1.0-V supply for port 7
161–164
165–168
169
P8, N8, P9, N9
P4, P5, P6, N6
P10
1.0-V supply for PHY
1.2-V input for internal LDO
3.3-V input for internal LDO. Connect to VDDIO
V3P3_REG
V3P3
170–174
175
L3, G3, G12, L12, M3 3.3-V supply for USB 2.0
V5P0_P0
V5P0_P1
V5P0
C4
D7
E7
5-V VCONN input to Upstream PD port
176
5-V VCONN input to Downstream PD port
5-V input supply to hub controller
177
178–192
GND
F6, F7, F8, F9, G6, Ground
G7, G8, G9, H6, H7,
H8, H9, J7, J8, J9
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Communication Interfaces
System Interfaces
Figure 4. Communication Interfaces
Upstream Port (US)
HX3PD
The HX3PD USB port can function in Type-C or Legacy Type-B
modes; it operates in the USB 3.1 Gen 2 (10 Gbps) specification.
This port includes an integrated 1.5-k pull-up resistor and
termination resistors. The HX3PD US port has an integrated PD
controller, which supports the PD 3.0 specification and can
charge up to 5A at 20 V.
I2C_HUB
SPI_HUB
Hub
S
Controller
M
EEPROM
S
Downstream Ports (DS1, 2, 3, 4, 5, 6, 7)
DMC
M
SPI_DMC
I2C_1
The following table summarizes the operations of HX3PD DS
ports.
S
M
Embedded
Controller
I2C_2
M
S
Table 2. Operations of HX3PD DS Ports
S
PD
Controller
DS
Port
USB
Speed
MaxCharging
Current
Connector
Charging Mode
M
DS1
DS2
DS3
DS4
DS5
Type-C
USB 3.1
Gen 2
PD 3.0
5A at 20 V
PD
S
PD
Regulator
for US Port
Type-C
Type-C
Type-A
Type-A
USB 3.1 BC 1.2, Apple
Gen 2
3A at 5 V
S
Regulator
VSEL_I2C
for DS1 Port
USB 3.1 BC 1.2, Apple
Gen 2
3A at 5 V
Note
M = Master; S = Slave
USB 3.1 BC 1.2, Apple
Gen 2
2.4A at 5 V
2.4A at 5 V
HX3PD supports SPI and I2C interfaces for communications
between individual blocks and with the Embedded Controller
(EC).
HX3PD has two SPI and four I2C interfaces.
USB 3.1 BC 1.2, Apple
Gen 2
DS6
DS7
Type-A
Type-A
USB 2.0 BC 1.2, Apple
USB 2.0 BC 1.2, Apple
2.4A at 5 V
2.4A at 5 V
SPI_HUB
This interface is connected to an SPI EEPROM. Hub controller
uses this interface to read firmware and configurations from
EEPROM.
Three HX3PD DS ports (DS1, DS2, and DS3) work in the Type-C
mode. The other ports work in the Type-A mode. USB 3.1 Gen 2
(10 Gbps) is supported in ports DS1 to DS5 and USB 2.0
(480 Mbps) is supported in ports DS6 and DS7. All DS ports
support, by default, the Battery Charging Specification 1.2. DS1
has an integrated PD controller which supports the PD 3.0 speci-
fication. Port enable/disable and charging modes shall be
configured using configuration options.
SPI_DMC
DMC also shall access SPI EEPROM using the SPI_DMC
interface.
I2C_1
The I2C interface I2C-1 is connected to the DMC and PD
controllers. DMC acts as an I2C master and PD controller acts
as the I2C slave for this interface.
I2C_2
The I2C interface I2C-2 is connected to the DMC and PD
controllers – DMC I2C is a slave; and PD I2C is unused with
default firmware. An external I2C master, such as Embedded
Controller (EC), shall use this interface to communicate to the
DMC and PD controllers.
I2C_HUB
The I2C interface I2C_HUB is connected to the Hub controller –
Hub controller acting as I2C slave. DMC shall access I2C_HUB
by connecting externally using I2C_1 to read hub status and
write hub configurations.
Document Number: 002-16615 Rev. *I
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VSEL_I2C
Clock
VSEL_GPIO1 and VSEL_GPIO2 shall be used for selecting the
VBUS voltage level of PD ports. VSEL_GPIO1 acts as
I2C_MASTER_SDA and VSEL_GPIO2 acts as I2C_MAS-
TER_SCL. These pins must be connected to the external Power
Regulator’s I2C interface to configure voltage levels for PD ports.
HX3PD requires an external crystal connected to XIN/XOUT with
25 MHz (±150 ppm), parallel resonant, fundamental mode, and
be capable of low drive level (<200 µW) with a peak-to-peak jitter
less than 50 ps.
Configuration Options
Reset
EZ-USB HX3PD Configuration Utility can be used to update
firmware and configurations of Hub controller, PD controller, and
DMC. Firmware and configuration image for the hub controller is
stored in an external SPI EEPROM. PD controller and DMC
images will be stored in device flash.
There are three reset pins for the HX3PD device. These pins
control reset operations for the Hub controller (RESET_HUB),
reset to DMC (XRES_DMC), and reset to PD controller
(XRES_PD). Additionally, the HX3PD reset shall be controlled by
DMC using a Software reset mechanism during configuration
and initialization.
Following configuration options are available in EZ-USB HX3PD
Configuration tool.
Table 3. EZ-USB HX3PD Configuration Options
No
Settings
Description
Hub Controller Configurations
1
2
3
4
5
VID
Custom Vendor ID
USB 2.0 PID
USB 3.1 PID
Power good time
PolyFuse
Custom Product ID for USB 2.0 Hub
Custom Product ID for USB 3.1 Hub
Time for Power-On sequence start in a port to Power is good to that port
Set the hub for polyfuse mode operation. Power good time is set to ‘0’ for
polyfused mode
6
7
String descriptor: Vendor
String descriptor for Vendor name
String descriptor: USB 2.0 Product String descriptor for USB 2.0 Hub Product Name
String descriptor: USB 3.1 Product String descriptor for USB 3.1 Hub Product Name
8
9
Serial
Product Serial Number
10
11
Number of USB 2.0 ports
Number of USB 3.1 ports
Number of active USB 2.0 ports
Number of active USB 3.1 ports.
Note “Number of USB 3.1 ports” should be equal or lower than “Number of USB
2.0 ports”.
12
13
Charging port
Enable or disable of BC 1.2 or Apple charging for DS ports
Compound hub
Removable or non-removable settings for DS ports.
Note DMC port is always set as “Non-removable”.
14
DFP fast charging
Enable or disable of CDP, Pure DCP, and Auto DCP modes in downstream ports.
Note Pure DCP used for compliance tests. Auto DCP allows fast charging for
Apple 2.1A/2.4A supported device or Samsung Galaxy devices.
15
16
USB type-C current
Maximum Type-C current for DS2 and DS3, 1.5A or 3.0 A
Enable Active-High power switch
High active power switch
PD Controller Configurations
1
2
3
VID
PD controller Vendor ID
PD controller Product ID
PID
PD version
PD version supported by device. PD controller support PD 2.0 and PD 3.0
versions supported.
4
5
Port power role
Rp supported
Selection of Sink, Source, or Dual Role modes
Rp values supported by the PD ports. Both PD ports support Default, 1.5A and
3A current levels
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Table 3. EZ-USB HX3PD Configuration Options (continued)
No Settings
Hub Controller Configurations
Description
6
Power data objects (PDOs)
Power source and sink capabilities of the PD ports. Default PD firmware support
5V, 9V, 15V and 20V PDOs.
7
8
9
Overvoltage protection
Overcurrent protection
VCONN OCP
Enable, threshold, and debounce of Over voltage protection
Enable, threshold, and debounce of Over current protection
Enable, threshold, and debounce of VCONN over current protection
DMC Configurations
1
2
3
VID
DMC Vendor ID
PID
DMC Product ID
Billboard enable
Billboard enable selection
You can download the EZ-USB HX3PD Configuration tool and its associated documentation at the following link:
www.cypress.com/products/ez-usb-hx3pd-usb-31-gen-2-hub-power-delivery
Document Number: 002-16615 Rev. *I
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Absolute Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the device.
Operating temperature ................................. 0 °C to +70 °C
Electrostatic discharge voltage ................................. 2200 V
Oscillator or crystal frequency ................ 25 MHz ±150 ppm
I/O voltage supply (3.3 V) .................................. 3 V to 3.6 V
I/O voltage supply (1.2 V) ............................1.14 V to 1.26 V
Maximum input sink current per I/O ............................. 4 mA
Electrical Specifications
HX3PD meets all USB-IF Electrical Compliance specifications.
DC Electrical Characteristics
Parameter
V1P2
Description
Min
1.14
3.0
3
Typ
1.2
3.3
3.3
1.0
3.3
3.3
1.8
3.3
1.8
5
Max
1.26
3.6
3.6
1.05
3.6
5.5
–
Unit
V
1.2-V voltage supply
VDDIO
3.3-V I/O voltage supply
3.3-V voltage supply
V
V3P3
V
VDD10
1.0-V core supply voltage
0.95
3
V
V3P3_U2
VDDD (PD)
VCCD_PD
VDDD (DMC)
VCCD_DMC
VBUS
3.3-V supply for the USB 2.0 PHY
3.3-V supply input to PD controller
Regulator output for PD controller
3.3-V supply input to DMC
V
3
V
–
V
2.7
–
5.5
–
V
Regulator output for DMC
V
VBUS for upstream port
0
5.25
5.5
5.5
5
V
V5P0_P0
V5P0_P1
VRAMP
ESD_HBM
ESD_CDM
LU
VCONN input to Upstream PD port
VCONN input to Downstream PD port
Voltage ramp rate on core and I/O supplies
Electrostatic discharge human body model
Electrostatic discharge charged device model
Pin current for latch-up
2.7
2.7
0.05
–
–
V
–
V
–
V/s
V
–
2200
500
100
–
–
V
–100
–
mA
Power Supply Specifications
ICC12
ICC33
ISB12
ISB33
1.2 V supplies operating current
–
–
–
–
–
–
750
70
–
mA
mA
mA
mA
3.3 V supplies operating current
1.2 V supplies combined suspend current
3.3 V supplies combined suspend current
23
3
–
I/O Specifications - Except USB Signals
VIH
VIL
Input voltage HIGH threshold
2
–
–
–
–
–
–
5.5
0.8
–
V
V
Input voltage LOW threshold
VOH
VOL
IIL
Output voltage HIGH level (when IOH = 4 mA)
Output voltage LOW level (when IOL = 8 mA)
Input leakage current
2.4
–
V
0.4
1
V
–1
μA
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Power Consumption
Table 4 provides the power consumption estimates for HX3PD under different conditions.
Table 4. Power Consumption
Measured Current (mA)
Hub Operating Condition
VP12
52.0
VP33
36.0
12.8
48.5
2.5
Upstream Not Connected to Host
Hub in Suspend Mode
25.0
Connected to Host and Hub in Idle Mode
Hub in Reset Mode
63.0
14.5
Write
1 USB 3.1 device connected
298.0
376.0
442.0
485.0
520.0
535.0
548.0
295.0
375.0
442.0
482.0
519.0
535.0
548.0
50.0
49.3
49.3
49.3
49.3
49.3
49.3
49.3
49.3
49.3
49.3
49.3
49.3
49.3
2 USB 3.1 devices connected
3 USB 3.1 devices connected
4 USB 3.1 devices connected
5 USB 3.1 devices connected
5 USB 3.1 and 1 USB 2.0 devices connected
5 USB 3.1 and 2 USB 2.0 devices connected
1 USB 3.1 device connected
Read
2 USB 3.1 devices connected
3 USB 3.1 devices connected
4 USB 3.1 devices connected
5 USB 3.1 devices connected
5 USB 3.1 and 1 USB 2.0 devices connected
5 USB 3.1 and 2 USB 2.0 devices connected
Document Number: 002-16615 Rev. *I
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Ordering Information
The following table lists HX3PD’s ordering information. The table contains only the part numbers that are currently available for order.
Additional part numbers with customized configurations can be made available on request. For more information, visit the Cypress
website or contact the local sales representative.
Table 5. Ordering Information
Signed FW
Download
Ordering Part Number
No of Ports
US PD Port
DS PD Port
CYUSB4347-BZXC
CYUSB4357-BZXC
7
7
DRP
DRP
DFP
DFP
No
Yes
Ordering Code Definitions
CY USB 43XX
XXX
C
ES
(Optional Field): Pre-production Engineering Samples only
Temperature Range: C = Commercial (0 ºC to 70 ºC)
Package Type
Product Type: 43XX = USB 3.1 Gen 2 Hub Controllers
Marketing Code: USB = USB Controllers
Company ID: CY = Cypress
Document Number: 002-16615 Rev. *I
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Package Diagram
Figure 5. 192-Ball FBGA Package Outline
002-13493 *A
Document Number: 002-16615 Rev. *I
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Silicon Revision History
This datasheet is applicable for USB-IF certified (TID# 5030000008) HX3PD Rev B and Rev A silicon.
Rev B: This silicon improves the yield of HX3PD, and fixed the Errata #2 (“Hub LVS Test “TD 10.102” Failure in DS1 to DS5 ports [1]”)
applicable to the Rev A silicon. There is no need to change the board design or layout to use the HX3PD Rev B Silicon. Products are
completely compatible with the HX3 Rev A Silicon.
However Rev B silicon requires a different firmware compared to Rev A silicon. Refer to EZ-USB HX3PD Firmware webpage for more
details
Method of Identification
Markings on row 3 of the HX3PD package differentiate Rev. B Silicon from Rev. A Silicon as indicated in the example below. Cypress
maintains traceability of product to wafer level, including wafer fabrication location, through the lot number marked on the package.
Figure 6. HX3PD REV A Silicon
Figure 7. HX3PD REV B Silicon
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Table 6. Acronyms Used in this Document
Acronym Description
SS
Acronyms
Table 6. Acronyms Used in this Document
SuperSpeed
Acronym
AES
Description
Advanced Encryption Standard
Battery Charging
TT
Transaction Translator
Upstream Facing Port
UpStream
UFP
US
BC
CC
Configuration Channel
USB
VID
Universal Serial Bus
Vendor ID
CDP
CPU
CRC
Charging Downstream Port
Central Processing Unit
Cyclic Redundancy Check, an Error-Checking
Protocol
Reference Documents
USB 2.0 Specification
DS
DownStream
USB 3.1 Specification
DCP
DFP
DMC
DNU
DP
Dedicated Charging Port
Downstream Facing Port
Dock Management Controller
Do Not Use
Battery Charging Specifications
USB Type-C Specification
USB Power Delivery Specification
DisplayPort
Document Conventions
DRP
DWG
EC
Dual-Role Power Port
Device Working Group
Embedded Controller
Units of Measure
Table 7. Units of Measure
Symbol
°C
Unit of Measure
EEPROM Electrically Erasable Programmable Read-Only
Memory
degree celsius
ohm
FS
Full-Speed
Gbps
KB
gigabit per second
kilobyte
FW
FirmWare
GND
GPIO
HS
GrouND
kHz
k
kilohertz
General-Purpose Input/Output
Hi-Speed
kilo-ohm
Mbps
MHz
µA
megabit per second
megahertz
microampere
milliampere
millisecond
milliwatt
I2C
Inter Integrated Circuit, a communications protocol
In-System Programming
Input/Output
ISP
I/O
mA
ms
LS
Low-Speed
MCU
NC
Microcontroller Unit
No Connect
mW
ns
nanosecond
parts per million
volt
OTG
PD
On-The-Go
ppm
V
Power Delivery
PID
POR
ROM
SCL
SDA
SHA
SPI
Product ID
Power-On Reset
Read-Only Memory
Serial CLock
Serial DAta
Secure Hash Algorithm
Serial Peripheral Interface, a communications
protocol
Document Number: 002-16615 Rev. *I
Page 20 of 25
CYUSB4347
CYUSB4357
Errata
No.
Errata
Applicability
1
2
Type-C Compliance Test “TD 4.1.2” Failure in DS2 and DS3 ports
Hub LVS Test “TD 10.102” Failure in DS1 to DS5 ports
HX3PD Rev A and Rev B silicon
HX3PD Rev A silicon only
1. Type-C Compliance Test “TD 4.1.2” Failure in DS2 and DS3 ports
■ Problem Definition: DS2 and DS3 ports present Rd when HX3PD is in Power-off state that leads to this compliance failure.
■ Parameters Affected: N/A
■ Trigger Condition(s): Type-C compliance test “TD 4.1.2 Unpowered CC Voltage Test” shows this failure condition. This is because
test expects no power to be present when HX3PD is in Power-off state.
■ Scope of Impact: There is no functional impact to the end user. This Errata is applicable only when DS2 and DS3 ports are used
as Type-C ports and there will be no impact when DS2 and DS3 are used as Legacy Type-A ports. Also, Type-C compliance test
“TD 4.1.2 Unpowered CC Voltage Test” failure is applicable only when DS2 and DS3 ports are expected to connect to a VBUS
Source (such as power adapter) which is not a real use case.
■ Workaround: No workaround available. This issue will not cause any functional issues or damage to silicon. Need waiver for
compliance tests.
■ Fix Status: No fix planned.
2. Hub LVS Test “TD 10.102” Failure in DS1 to DS5 ports [1]
■ Problem Definition: HX3PD’s Hub port shows wrong value for PORT_LINK_STATE parameter during link loopback mode.
■ Parameters Affected: N/A
■ Trigger Condition(s): Hub LVS test “TD 10.102” shows this failure condition. This failure will never happen in functional modes.
■ Scope of Impact: Hub LVS test “TD 10.102 Power Off Upstream Port Test” failure is applicable only in test mode; in a normal
functional mode, HX3PD will never be in test mode and hence no impact.
■ Workaround: No workaround available for Rev A silicon. Issue fixed in Rev B silicon.
■ Fix Status: Errata seen only in Rev A silicon. It is fixed in Rev B silicon.
Note
1. Applicable only for Rev A silicon.
Document Number: 002-16615 Rev. *I
Page 21 of 25
CYUSB4347
CYUSB4357
Document History Page
Document Title: CYUSB4347/CYUSB4357, HX3PD USB 3.1 Gen 2 Type-C Hub with PD
Document Number: 002-16615
Submission
Revision
ECN
Description of Change
Date
**
5894940
6000726
10/03/2017 New data sheet.
*A
12/21/2017 Updated Document Title to read as “CYUSB4347/CYUSB4357, HX3PD USB 3.1 Gen 2
Type-C Hub with PD”.
Updated Features:
Updated description.
Updated Block Diagram.
Updated Architecture Overview:
Updated USB-PD Controller:
Updated description.
Removed “SPI Interfaces”.
Removed “Serial Communication/GPIO Block”.
Removed “Dock Management Controller”.
Added SPI, I2C, and GPIO Interfaces.
Added Dock Management Controller.
Updated HX3PD Product Options:
Updated Table 1:
Updated entire table.
Updated Pinouts:
Updated Figure 5.
Updated Pin Description:
Updated entire table.
Added System Interfaces.
Added Absolute Maximum Ratings.
Added Electrical Specifications.
Added Ordering Information.
Added Errata.
Updated to new template.
*B
*C
6111605
6288356
03/27/2018 Updated Pinouts:
Updated Figure 5 (Updated details in C4 and D7).
Updated Pin Description:
Updated details in all columns corresponding to pin numbers C4, D7, E7.
Updated Electrical Specifications:
Updated Power Consumption:
Updated Table 4 (Updated entire table).
Removed Errata.
09/27/2018 Updated Features:
Updated description.
Updated Block Diagram.
Updated Architecture Overview:
Added Crypto Block.
Updated HX3PD Product Options:
Updated Table 1.
Updated System Interfaces:
Updated Downstream Ports (DS1, 2, 3, 4, 5, 6, 7):
Updated Table 2.
Updated Electrical Specifications:
Updated DC Electrical Characteristics:
Updated details in “Min” and “Max” columns corresponding to ESD_HBM parameter.
Updated Power Consumption:
Updated Table 4.
Document Number: 002-16615 Rev. *I
Page 22 of 25
CYUSB4347
CYUSB4357
Document History Page (continued)
Document Title: CYUSB4347/CYUSB4357, HX3PD USB 3.1 Gen 2 Type-C Hub with PD
Document Number: 002-16615
Submission
Revision
ECN
Description of Change
Date
*C (cont.)
6288356
09/27/2018 Updated Reference Documents:
Updated links.
Added “Silicon Revision History”.
Completing Sunset Review.
*D
6352040
10/31/2018 Updated Architecture Overview:
Updated USB-PD Controller:
Updated description.
Updated Pinouts:
Updated Figure 5 (Updated details in A5 and C9).
Updated Pin Description:
Updated details in “Description” column corresponding to pin numbers B11 and B12.
Updated details in “Pin Name” and “Description” columns corresponding to pin numbers C9
and A5.
Updated System Interfaces:
Updated Communication Interfaces:
Updated I2C_2:
Updated description.
Updated Electrical Specifications:
Updated DC Electrical Characteristics:
Updated details in “Min” and “Max” columns corresponding to ESD_CDM parameter.
Added LU parameter and its corresponding details.
Updated Power Consumption:
Updated Table 4.
*E
6439058
04/24/2019 Updated Functional Description:
Updated description.
Updated Features:
Updated description.
Updated Block Diagram.
Updated Architecture Overview:
Updated description.
Updated Dock Management Controller:
Added Firmware Update Support.
Added Application Diagrams.
Updated Pinouts:
Updated Figure 3.
Updated Pin Description:
Updated almost entire table.
Updated System Interfaces:
Updated Downstream Ports (DS1, 2, 3, 4, 5, 6, 7):
Updated Table 2.
Updated Communication Interfaces:
Updated Figure 4.
Updated SPI_HUB:
Updated description.
Updated I2C_1:
Updated description.
Updated I2C_2:
Updated description.
Updated I2C_HUB:
Updated description.
Added Configuration Options.
Document Number: 002-16615 Rev. *I
Page 23 of 25
CYUSB4347
CYUSB4357
Document History Page (continued)
Document Title: CYUSB4347/CYUSB4357, HX3PD USB 3.1 Gen 2 Type-C Hub with PD
Document Number: 002-16615
Submission
Revision
ECN
Description of Change
Date
*E (cont.)
6439058
04/24/2019 Updated Electrical Specifications:
Updated DC Electrical Characteristics:
Added V5P0_P0, V5P0_P1, VRAMP parameters and their corresponding details.
Added Power Supply Specifications, I/O Specifications - Except USB Signals sub sections
and added corresponding details.
Updated Power Consumption:
Updated Table 4.
Updated to new template.
*F
6534152
6904997
06/14/2019 Updated Ordering Information:
Updated part numbers.
Removed “Silicon Revision History”.
*G
06/25/2020 Changed status from Preliminary to Final.
Updated Block Diagram.
Updated Architecture Overview:
Updated Dock Management Controller:
Updated Firmware Update Support:
Updated description.
Updated Signed Firmware Update:
Added hyperlinks in required places.
Updated Application Diagrams:
Updated Docking Stations:
Updated description.
Updated Pinouts:
Updated Figure 3.
Updated Pin Description:
Updated details in all columns corresponding to pin numbers K5 and C8.
Updated details in “Pin Name” column corresponding to pin numbers C9 and A5.
Updated System Interfaces:
Updated Communication Interfaces:
Updated Figure 4.
Updated VSEL_I2C:
Updated description.
Updated Configuration Options:
Updated description.
Updated Table 3 (Updated details in Description column corresponding to “USB type-C
current” setting, replaced “DMC Controller Configurations” with “DMC Configurations”).
Updated Electrical Specifications:
Updated Power Consumption:
Updated Table 4 (Updated entire table).
Added Errata.
Updated to new template.
*H
*I
6993324
7105316
10/13/2020 Updated part numbers in Ordering Information.
03/19/2021 Added Silicon Revision History section.
Updated “Hub LVS Test” section in Errata and added a note “Applicable only for Rev A
silicon”.
Updated Power Consumption and Ordering Code Definitions.
Document Number: 002-16615 Rev. *I
Page 24 of 25
CYUSB4347
CYUSB4357
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
®
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PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP | PSoC 6 MCU
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cypress.com/support
Microcontrollers
PSoC
cypress.com/psoc
cypress.com/pmic
cypress.com/touch
cypress.com/usb
Power Management ICs
Touch Sensing
USB Controllers
Wireless Connectivity
cypress.com/wireless
IMPORTANT NOTE REGARDING PROTECTED FIRMWARE DOWNLOAD: Cypress has implemented protections in the product to prevent unauthorized firmware updates from being applied to the
product. However, no computing device or system can be absolutely secure. Therefore, the parties agree that Cypress shall not have any liability arising out of any failure of the product's security
features, such as the inability to load firmware or a breach allowing the loading of unauthorized firmware.
© Cypress Semiconductor Corporation, 2017–2021. This document is the property of Cypress Semiconductor Corporation, and Infineon Technologies company, and its affiliates (“Cypress”). This
document, including any software or firmware included or referenced in this document (“Software”), is owned by Cypress under the intellectual property laws and treaties of the United States and
other countries worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights,
trademarks, or other intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the
Software, then Cypress hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in
source code form, to modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form
externally to end users (either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress’s patents that are
infringed by the Software (as provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction,
modification, translation, or compilation of the Software is prohibited.
TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. No computing
device can be absolutely secure. Therefore, despite security measures implemented in Cypress hardware or software products, Cypress shall have no liability arising out of any security breach, such
as unauthorized access to or use of a Cypress product. CYPRESS DOES NOT REPRESENT, WARRANT, OR GUARANTEE THAT CYPRESS PRODUCTS, OR SYSTEMS CREATED USING
CYPRESS PRODUCTS, WILL BE FREE FROM CORRUPTION, ATTACK, VIRUSES, INTERFERENCE, HACKING, DATA LOSS OR THEFT, OR OTHER SECURITY INTRUSION (collectively,
“Security Breach”). Cypress disclaims any liability relating to any Security Breach, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from any Security
Breach. In addition, the products described in these materials may contain design defects or errors known as errata which may cause the product to deviate from published specifications. To the
extent permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of
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It is the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. “High-Risk
Device” means any device or system whose failure could cause personal injury, death, or property damage. Examples of High-Risk Devices are weapons, nuclear installations, surgical implants, and
other medical devices. “Critical Component” means any component of a High-Risk Device whose failure to perform can be reasonably expected to cause, directly or indirectly, the failure of the
High-Risk Device, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from
any use of a Cypress product as a Critical Component in a High-Risk Device. You shall indemnify and hold Cypress, including its affiliates, and its directors, officers, employees, agents, distributors,
and assigns harmless from and against all claims, costs, damages, and expenses, arising out of any claim, including claims for product liability, personal injury or death, or property damage arising
from any use of a Cypress product as a Critical Component in a High-Risk Device. Cypress products are not intended or authorized for use as a Critical Component in any High-Risk Device except to
the limited extent that (i) Cypress’s published data sheet for the product explicitly states Cypress has qualified the product for use in a specific High-Risk Device, or (ii) Cypress has given you advance
written authorization to use the product as a Critical Component in the specific High-Risk Device and you have signed a separate indemnification agreement.
Cypress, the Cypress logo, and combinations thereof, WICED, ModusToolBox, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress or a subsidiary
of Cypress in the United States or in other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Document Number: 002-16615 Rev. *I
Revised March 19, 2021
Page 25 of 25
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