CYW89820 [INFINEON]
The AIROC™ CYW89820 Automotive Bluetooth® & Bluetooth® LE SoC is a Bluetooth® 5.2 core spec compliant device for automotive and industrial applications. Manufactured using the industry's advanced 40 nm CMOS low-power process, the CYW89820 is a highly integrated device which delivers up to 11.5 dBm transmit output power in LE and BR modes and up to 2.5 dBm in EDR mode, reducing the device footprint and the costs associated with implementing Bluetooth® solutions.;
| 型号： | CYW89820 |
| 厂家： | 
Infineon |
| 描述： | The AIROC™ CYW89820 Automotive Bluetooth® & Bluetooth® LE SoC is a Bluetooth® 5.2 core spec compliant device for automotive and industrial applications. Manufactured using the industry's advanced 40 nm CMOS low-power process, the CYW89820 is a highly integrated device which delivers up to 11.5 dBm transmit output power in LE and BR modes and up to 2.5 dBm in EDR mode, reducing the device footprint and the costs associated with implementing Bluetooth® solutions. |
| 文件： | 总53页 (文件大小：735K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CYW89820
AIROC™ Bluetooth® system on chip for
automotive applications
CYW89820 is a monolithic, single-chip, Bluetooth® 5.0 compliant, standalone baseband processor system on chip
(SoC) with an integrated 2.4 GHz transceiver.
Manufactured using the industry's most advanced 40-nm CMOS low-power process, the CYW89820 employs the
highest level of integration, eliminating all critical external components, and thereby minimizing the device’s
footprint and costs associated with the implementation of Bluetooth® solutions.
Integrating a transceiver, baseband processor, Arm® Cortex®-M4, and application flash memory on a single die
provides the capability to replace function-specific devices with a single design that offers all Bluetooth® modes
of operation.
The CYW89820 brings the latest Bluetooth® technology to automotive applications and offers automotive Grade
2 (–40°C to +105°C) ambient operating temperature performance. The CYW89820 is tested to Automotive
Electronics Council AEC-Q100 environmental stress guidelines and is manufactured in ISO9001 approved and
TS16949 certified facilities.
Features
• Bluetooth® subsystem
- Complies with Bluetooth® Core Specification version 5.0
• QDID: 151200
• Declaration ID: D043201
- Includes support for BR, EDR 2 Mbps and 3 Mbps, eSCO, Bluetooth® LE, and LE 2 Mbps.
- Programmable TX Power up to 11.5 dBm
- Excellent receiver sensitivity (–94 dBm for BLE 1 Mbps)
• Microcontroller
- Powerful Arm® Cortex®-M4 core with a maximum speed of 96 MHz
- Bluetooth® stack in ROM allowing standalone operation without any external MCU
- 256-KB on-chip secure flash
- 176-KB on-chip RA
- Bluetooth® stack, peripheral drivers, security functions built into ROM (1 MB) allowing application to efficiently
use on-chip flash
- AES-128 and true random number generator (TRNG)
- Security functions in ROM including ECDSA signature verification
- Over-the-air (OTA) firmware updates
• Peripherals
- 17 GPIOs
- I2C, I2S, UART, and PCM interfaces
- Quad-SPI interfaces
- Auxiliary ADC with up to 14 analog channels
- General-purpose timers and PWM
- Real-time clock (RTC) and watchdog timers (WDT)
• Power management
- On chip power-on reset (POR)
- Integrated buck (DC-DC) and LDO regulators
- On chip software controlled power management unit
- On chip 32-kHz LPO with optional external 32-kHz crystal oscillator support
Datasheet
www.infineon.com
Please read the Important Notice and Warnings at the end of this document
page 1
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AIROC™ Bluetooth® system on chip for automotive applications
Applications
• Wi-Fi coexistence
- Global Coexistence Interface (GCI) for Infineon Wi-Fi parts
- Serial Enhanced Coexistence Interface (SECI)
• Supported in ModusToolbox™ software
• OTA firmware update support
• Grade-2 (–40°C to +105°C) operation
• Package types
- 48-pin WQFN
- RoHS compliant
Applications
• Automotive
- Car access and car sharing
- Keyless entry
- Passive entry and passive start (PEPS)
- Remote parking
- Wireless diagnostics (OBD)
- Sensors
- Cable replacement
• Industrial
- Access control
- Asset tracking
- Factory automation
- Logistics management
- Sensors
Datasheet
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AIROC™ Bluetooth® system on chip for automotive applications
Functional block diagram
Functional block diagram
Microcontroller Subsystem
Bluetooth® Core
Cache
Secure Flash
8 KB
256 KB
BT5.0
PHY
BT5.0
MAC
PA
RF
RAM
160 KB
ROM
1 MB
Arm®
Cortex® M4
96 MHz
Clocks
XTAL OSC
24 MHz
Patch Control
Patch RAM
16 KB
HP-LPO
32 kHz
Debug UART/JTAG
Watchdog
XTAL OSC
32 kHz
LP-LPO
16/32/128 kHz
Peripherals
Power Management
Core DC-DC
ADC
IR
TRNG
GPIOs (17)
I2C Master
I2C Slave
UART (x2)
I/
O
RF LDO
TRIAC
M
U
X
Digital LDO
PA LDO
PWM
PCM
Timer
Q-SPI (x2)
Coexistence Interface (GCI)
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AIROC™ Bluetooth® system on chip for automotive applications
Table of contents
Table of contents
Features ...........................................................................................................................................1
Applications......................................................................................................................................2
Functional block diagram...................................................................................................................3
Table of contents...............................................................................................................................4
1 Bluetooth® baseband core ...............................................................................................................6
1.1 BQB and regulatory testing support ......................................................................................................................6
1.2 Wi-Fi coexistence support ......................................................................................................................................7
2 Microprocessor unit ........................................................................................................................8
2.1 Main crystal oscillator.............................................................................................................................................8
2.2 32 kHz crystal oscillator..........................................................................................................................................9
2.3 Low-frequency clock sources...............................................................................................................................10
2.4 Power modes ........................................................................................................................................................11
2.5 Watchdog ..............................................................................................................................................................11
2.6 Lockout functionality............................................................................................................................................11
2.7 True random number generator ..........................................................................................................................11
3 Power-on and external reset..........................................................................................................12
4 Power management unit ...............................................................................................................13
5 Power configurations....................................................................................................................14
5.1 Configuration 1 - VBAT and VDDIO.......................................................................................................................14
5.2 Configuration 2 - External supplies......................................................................................................................15
5.3 Configuration 3 - LDOs and VDDIO.......................................................................................................................15
6 Integrated radio transceiver ..........................................................................................................16
6.1 Transmitter path...................................................................................................................................................16
6.1.1 Digital modulator...............................................................................................................................................16
6.1.2 Power amplifier..................................................................................................................................................16
6.2 Receiver path ........................................................................................................................................................16
6.2.1 Digital demodulator and bit synchronizer........................................................................................................16
6.2.2 Receiver signal strength indicator ....................................................................................................................16
6.3 Local oscillator......................................................................................................................................................16
7 Peripherals ..................................................................................................................................17
7.1 I2C compatible master .........................................................................................................................................17
7.2 Serial peripheral interface....................................................................................................................................17
7.3 HCI UART interface................................................................................................................................................17
7.4 Peripheral UART interface ....................................................................................................................................17
7.5 GPIO ports .............................................................................................................................................................17
7.6 ADC ........................................................................................................................................................................18
7.7 PWM .......................................................................................................................................................................18
7.8 PDM microphone ..................................................................................................................................................19
7.9 I2S interface ..........................................................................................................................................................19
7.10 PCM interface ......................................................................................................................................................19
7.10.1 Slot mapping....................................................................................................................................................19
7.10.2 Frame synchronization....................................................................................................................................20
7.10.3 Data formatting................................................................................................................................................20
8 Firmware .....................................................................................................................................21
9 Pin assignments and GPIOs............................................................................................................22
10 Ball maps ...................................................................................................................................31
10.1 48-pin WQFN pin map.........................................................................................................................................31
11 Specifications .............................................................................................................................32
11.1 Electrical characteristics ....................................................................................................................................32
11.2 Brown out............................................................................................................................................................33
11.2.1 Core buck regulator .........................................................................................................................................33
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Table of contents
11.2.2 Recommended component ............................................................................................................................34
11.2.3 Digital LDO........................................................................................................................................................34
11.2.4 Recommended component ............................................................................................................................35
11.2.5 RF LDO ..............................................................................................................................................................35
11.2.6 PALDO...............................................................................................................................................................36
11.2.7 Recommended component ............................................................................................................................37
11.2.8 Digital I/O characteristics ................................................................................................................................37
11.2.9 Current consumption ......................................................................................................................................37
11.3 RF specifications .................................................................................................................................................38
11.4 Timing and AC characteristics............................................................................................................................40
11.4.1 UART timing .....................................................................................................................................................40
11.4.2 SPI timing .........................................................................................................................................................41
11.4.3 BSC interface timing ........................................................................................................................................42
11.4.4 I2S .....................................................................................................................................................................43
12 Package information ...................................................................................................................45
12.1 Package thermal characteristics........................................................................................................................45
13 Packaging diagrams ....................................................................................................................46
13.1 48-Pin WQFN package.........................................................................................................................................46
13.2 Tape reel and packaging specifications ............................................................................................................47
14 Ordering information ..................................................................................................................48
15 Acronyms ...................................................................................................................................49
Revision history ..............................................................................................................................52
Datasheet
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AIROC™ Bluetooth® system on chip for automotive applications
Bluetooth® baseband core
1
Bluetooth® baseband core
The Bluetooth® baseband core (BBC) implements all of the time-critical functions required for high-performance
Bluetooth® operation. The BBC manages the buffering, segmentation, and routing of data for all ACL, SCO, eSCO,
LE, and 2 Mbps LE connections. It prioritizes and schedules all RX/TX activities including adv, paging, scanning,
and servicing of connections. In addition to these functions, it independently handles the host controller
interface (HCI) including all commands, events, and data flowing over HCI. The core also handles symbol timing,
forward error correction (FEC), header error control (HEC), cyclic redundancy check (CRC), authentication, data
encryption/decryption, and data whitening/dewhitening.
Table 1 lists key Bluetooth® features supported by the CYW89820.
Table 1
Key Bluetooth® features supported by CYW89820
Bluetooth® 1.0
Basic rate
SCO
Paging and inquiry
Page and inquiry scan
Sniff
Bluetooth® 1.2
Interlaced scans
Adaptive frequency hopping
eSCO
–
–
Bluetooth® 2.0
EDR 2 Mbps and 3 Mbps
–
–
–
–
Bluetooth® 2.1
Secure simple pairing
Enhanced inquiry response
Sniff Subrating
Bluetooth® 4.1
Low duty cycle advertising
Dual mode
Bluetooth® 3.0
Unicast connectionless data
Enhanced power control
eSCO
Bluetooth® 4.2
Data packet length extension
LE secure connection
Link layer privacy
Bluetooth® 4.0
Bluetooth® Low Energy
–
–
Bluetooth® 5.0
LE 2 Mbps
Slot availability mask
High duty cycle advertising
LE link layer topology
1.1
BQB and regulatory testing support
The CYW89820 fully supports Bluetooth® test mode as described in Part I:1 of the Specification of the Bluetooth®
System v3.0. This includes the transmitter tests, normal and delayed loop back tests, and reduced hopping
sequence.
In addition to the standard Bluetooth® test mode, the CYW89820 also supports enhanced testing features to
simplify RF debugging and qualification. These features include:
• Fixed frequency carrier wave (unmodulated) transmission
- Simplifies some type-approval measurements (Japan)
- Aids in transmitter performance analysis
• Fixed frequency constant receiver mode
- Receiver output directed to I/O pin
- Allows for direct BER measurements using standard RF test equipment
- Facilitates spurious emissions testing for receive mode
• Fixed frequency constant transmission
- 8-bit fixed pattern or PRBS-9
- Enables modulated signal measurements with standard RF test equipment
Datasheet
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Bluetooth® baseband core
1.2
Wi-Fi coexistence support
The CYW89820 includes support for:
• Global Coexistence Interface for use with Infineon Wi-Fi parts
• Serial Enhanced Coexistence Interface (SECI) for use with SECI compatible Wi-Fi parts
Datasheet
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AIROC™ Bluetooth® system on chip for automotive applications
Microprocessor unit
2
Microprocessor unit
The CYW89820 includes a Cortex® M4 processor with 1 MB of program ROM, 160 KB of data RAM, 16 KB of patch
RAM, and 256 KB of flash. The CM4 has a maximum speed of 96 MHz. The 256 KB of flash is supported by an 8 KB
cache allowing direct code execution from flash at near maximum speed and low power consumption.
The CM4 runs all the BT layers as well as application code. The ROM includes LMAC, HCI, L2CAP, GATT, as well as
other stack layers freeing up most of the flash for application usage.
A standard serial wire debug (SWD) interface provides debugging support. Refer to the “Firmware” on page 21
section for details on the architecture and layers that are included in the ROM.
2.1
Main crystal oscillator
The CYW89820 uses a 24 MHz crystal oscillator (XTAL).
The XTAL must have an accuracy of ±20 ppm as defined by the Bluetooth® specification. Two external load capac-
itors are required to work with the crystal oscillator. The selection of the load capacitors is XTAL-dependent (see
Figure 1).
CL1
XIN
Crystal
XOUT
CL2
Figure 1
Recommended oscillator configuration
Table 2
Reference crystal electrical specifications
Conditions
Parameter
Min
–
Fundamental
Typ
24.000
Max
–
Unit
MHz
–
Nominal frequency
Oscillation mode
–
–
Includes operating temperature
range and aging
Frequency accuracy
–
–
±20
ppm
Equivalent series resistance
Load capacitance
Drive level
–
–
–
–
–
–
–
–
–
8
–
–
60
–
200
2
W
pF
μW
pF
Shunt capacitance
Datasheet
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AIROC™ Bluetooth® system on chip for automotive applications
Microprocessor unit
2.2
32 kHz crystal oscillator
The CYW89820 includes a 32 kHz oscillator to provide accurate timing during low power operations. Figure 2
shows the 32 kHz XTAL oscillator with external components and Table 3 lists the oscillator’s characteristics. This
oscillator can be operated with a 32 kHz or 32.768 kHz crystal oscillator or be driven with a clock input at similar
frequency. The XTAL must have an accuracy of ±250 ppm or better per the BT spec over temperature and
including aging. The default component values are: R1 = 10 MΩ and C1 = C2 = ~6 pF. The values of C1 and C2 are
used to fine-tune the oscillator.
C 2
3 2 .7 6 8 k H z
R 1
X T A L
C 1
Figure 2
32 kHz oscillator block diagram
XTAL oscillator characteristics
Table 3
Parameter
Symbol
Foscout
–
Pdrv
Rseries
Conditions
–
Over temperature and aging
For crystal selection
For crystal selection
For crystal selection
Min
–
–
–
–
–
Typ
32.768
–
–
–
–
Max
–
250
0.5
70
Unit
kHz
ppm
μW
kΩ
pF
Output Frequency
Frequency Tolerance
XTAL Drive Level
XTAL Series Resistance
XTAL Shunt Capacitance Cshunt
2.2
Datasheet
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AIROC™ Bluetooth® system on chip for automotive applications
Microprocessor unit
2.3
Low-frequency clock sources
The 32-kHz low-frequency clock (LPO_32K on the following figure) can be obtained from multiple sources. There
are two internal low-power oscillators (LPOs), called the LP-LPO and HP-LPO, as well as external crystal connec-
tions (OSC32K). The firmware determines the clock source to use among the available LPOs depending on the
accuracy and power requirements. The preferred source is the external LPO (OSC32K) because it has good
accuracy with the lowest current consumption. Internal LP-LPO has low current consumption and low accuracy
whereas HP-LPO has higher accuracy and higher current consumption. The firmware assumes the external LPO
has less than 250 PPM error with little or no jitter.
Variable
Frequency
HCLK
CPU
48/96M
Fixed
Frequency
DIV N
Block
Timers
DIV N
1M
XTAL 24M
96M
ADPLL
SPI2
SPI1
PUART
HCI UART
I2C
48M
DIV N
PTU
24M
ADC
(12M)
24M
DIV N
1M
24M
ACLK0
24M
ACLK1
PWM(0-5)
OSC32K
LPO
LPO
LPO
LPO_32K
HP- LPO
LP-LPO
LHL
RTC
Figure 3
Simplified clock source
Datasheet
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Microprocessor unit
2.4
Power modes
The CYW89820 supports the following HW power modes:
• Active mode: Normal operating mode in which all peripherals are available and CPU is active
• Idle mode - CPU is paused: In this mode, the CPU is in “Wait for Interrupt” (WFI) and the HCLK, which is the high
frequency clock derived from the main crystal oscillator, is running at a lower clock speed. Other clocks are
active and the state of the entire chip is retained.
• Sleep mode: All systems clocks idle except for the LPO. The chip can wake up either after a programmed period
of time has expired or if an external event is received via one of the GPIOs. In this mode, CPU is in WFI and the
HCLK is not running. The PMU determines if the other clocks can be turned off and does accordingly. State of
the entire chip is retained, the internal LDOs run at a lower voltage (voltage is managed by the PMU), and SRAM
is retained.
• PDS (Power Down Sleep) mode: Radio powered down and digital core mostly powered down except for RAM,
registers, and some core logic. CYW89819 can wake up either after a programmed period of time has expired or
if an external event is received via one of the GPIOs.
• ePDS (extended PDS) mode: This is an extension of the PDS Mode. In this mode, only the main RAM and ePDS
control circuitry retains power. As in other modes, the CYW89819 can wake up either after a programmed period
or upon receiving an external event.
• HID-OFF (Deep Sleep) mode: Core, radio, and regulators powered down. Only the LHL IO domain is powered.
In this mode, the CYW89819 can be woken up either by an event on one of the GPIOs or after a certain amount
of time has expired. After wakeup, the part will go through full FW initialization although it will retain enough
information to determine that it came out of HID-OFF and the event that caused the wake up. LPO and RTC are
turned off in this mode. Either an internal LPO or an external input would provide a measure of time.
Transition between power modes is handled by the on-chip firmware with host/application involvement. In
general ePDS is the most power efficient mode for most active use cases. HID-OFF generally works for
non-connectable beacon type use cases with long advertisement intervals. Refer to the “Firmware” on page 21
section for more details.
2.5
Watchdog
CYW89820 includes an onboard watchdog with a period of approx. 4 seconds. The watchdog timer generates an
interrupt to the FW after 2 seconds of inactivity and resets the parts after 4 seconds.
2.6
Lockout functionality
The CYW89820 power up with JTAG and SWD access to flash and RAM is disabled. After reset, FW checks OCF for
the presence of a security lockout field. If present, FW leaves JTAG and SWD Flash and RAM access disabled and
also blocks any HCI commands from reading the raw contents of the RAM or Flash.
The security field can be programmed in the factory after all programming and testing has been done. Refer to
the ModusToolbox™ software documentation for details on how to enable this feature. This provides an
effective way of protecting against any tampering, dumping, probing or reverse engineering of OCF resident user
application. The only FW upgrade path in this scenario is the secure OTA update.
2.7
True random number generator
The CYW89820 includes a hardware TRNG. Applications can access the random number generator via the
firmware driver. Refer to the ModusToolbox™ software documentation for details.
Datasheet
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AIROC™ Bluetooth® system on chip for automotive applications
Power-on and external reset
3
Power-on and external reset
Figure 4 shows power-on and reset timing of the CYW89820. After VBAT is applied and reset is inactive, the
internal buck turns on, followed by the RF and Digital LDOs. Once the LDO outputs have stabilized, the PMU allows
the digital core to come out of reset. As shown in the figure, external reset can be applied at any time subsequent
to power up.
Power up with Switching Regulator
RESET_N
VBAT
VDDIO
~
1.3ms
VDDC
~
2.4ms
VDDIO POR
~
820µs
~
820µs
VDDC Reset
(internal)
3 Lpo cycles
3 Lpo cycles
XTAL_PU
31 Lpo cy cles
31 Lpo cy cles
XTAL_BUF_PU
Figure 4
Reset timing
Datasheet
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Power management unit
4
Power management unit
Figure 5 shows the CYW89820 power management unit (PMU) block diagram. The CYW89820 includes an
integrated buck regulator, a digital LDO for the digital core, and an RF LDO for the Radio. The PMU also includes
a brownout detector which places the part in shutdown when input voltage is below a certain threshold.
CYW89820 PMU
PMU_AVDD
Reset
Brownout
Detector
Buck Output
SRPVDD
SR_VLX
Buck
DIGLDO_VDDOUT
DIGLDO_VDDIN
Digital LDO
RFLDO_VDDOUT
PALDO_VDDOUT
RFLDO_VDDIN
PALDO_VDDIN
RF LDO
PA LDO
Figure 5
Power management unit
Datasheet
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Power configurations
5
Power configurations
CYW89820 supports three power configurations as described in the following table.
Table 4
Power configurations
Configuration
Description
VBAT and VDDIO are supplied externally and are used to generate all other supplies on the
VBAT and VDDIO device. Reset may be left floating as it has an internal pull-up, may be connected to an
external RC, or may be driven externally.
PMU is disabled and on-chip regulators are not used. All supplies are provided externally.
Reset is driven from the outside.
External Supplies
On-chip LDOs are used to generate internal supplies but the on-chip buck is not used.
Reset is driven externally.
LDOs and VDDIO
5.1
Configuration 1 - VBAT and VDDIO
In this configuration the device is provided with two supplies (which can also be tied together). RST_N is either
left floating and relies on the internal pull-up to VDDIO to bring the device out of reset or tied to an external RC,
or driven externally. All other required supplies are generated on-chip (see the following figure). Note that VDDIO
must be supplied at the same time or before VBAT is supplied.
The device may require an external reset when any supply voltages drop below 1 V. POR operation not
guaranteed below 1 V.
CYW89820
VBAT
PALDO_VDDIN
PMU_AVDD
SR_PVDD
PA LDO
BUCK
PALDO_VDDOUT
SR_VLX
RFLDO_VDDIN
DIGLDO_VDDIN
RF LDO
RFLDO_VDDOUT
DIGLDO_VDDOUT
DIG LDO
VDDC
RST_N
Radio
IFVDD
VDDIO
VDDIO
PLLVDD
VCOVDD
PAVDD
VDDIO
MIC_AVDD
ADC_AVDDBAT
Figure 6
VBAT and VDDIO configuration
Datasheet
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Power configurations
5.2
Configuration 2 - External supplies
In this configuration the internal regulators are not used and VBAT is not supplied. VDDIO is supplied along with
externally generated core and radio supplies. This is shown in the following figure.
CYW89820
PALDO_VDDIN
PMU_AVDD
PALDO_VDDOUT
PA LDO
_
SR PVDD
BUCK
SR_VLX
RFLDO_VDDOUT
DIGLDO_VDDOUT
RFLDO_VDDIN
DIGLDO_VDDIN
RF LDO
DIG LDO
VDDC
VDDC
External
VDDIO
RST_N
VDDRF
Radio
IFVDD
VDDIO
PLLVDD
VCOVDD
PAVDD
VDDIO
MICAVD D
AD C_AVDDBAT
VDDPA
Figure 7
External supplies configuration
Note that VDDIO must be provided simultaneously or before the rest of the supplies and the device must be held
in reset until all supplies are within normal operating ranges.
The device may require a reset if any supply goes outside the normal operating range.
5.3
Configuration 3 - LDOs and VDDIO
In this configuration the internal buck regulator is not used. Instead, power is supplied to the internal LDOs which
are responsible for supplying the rest of the device.
CYW89820
PA Supply
PALDO_VDDIN
PA LDO
PALDO_VDDOUT
PMU_AVDD
SR_PVDD
BUCK
SR_VLX
RF Supply
RFLDO_VDDIN
RF LDO
RFLDO_VDDOUT
DIGLDO_VDDOUT
DIGLDO_VDDIN
DIG LDO
DIG Supply
External
VDDC
RST_N
Radio
IFVDD
VDDIO
VDDIO
PLLVDD
VCOVDD
PAVDD
VDDIO
MIC_AVDD
ADC_AVDDBAT
Figure 8
LDOs and VDDIO configuration
Note that VDDIO must be provided simultaneously or before the rest of the supplies and the device must be held
in reset until all supplies are within normal operating ranges. The internal LDOs have a small turn-on time
(specified later in the datasheet) which should be accounted for before releasing reset.
The device may require a reset if any supply goes outside the normal operating range.
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Integrated radio transceiver
6
Integrated radio transceiver
The CYW89820 has an integrated radio transceiver that has been designed to provide low power operation in the
globally available 2.4 GHz unlicensed ISM band. It is fully compliant with Bluetooth® Radio Specification 5.0 and
meets or exceeds the requirements to provide the highest communication link quality of service.
6.1
Transmitter path
The CYW89820 features a fully integrated transmitter. The baseband transmit data is GFSK modulated in the
2.4 GHz ISM band.
6.1.1
Digital modulator
The digital modulator performs the data modulation and filtering required for the GFSK signal. The fully digital
modulator minimizes any frequency drift or anomalies in the modulation characteristics of the transmitted
signal.
6.1.2
Power amplifier
The CYW89820 has an integrated power amplifier (PA) that can transmit up to +10.5 dBm for class 1 operation.
6.2
Receiver path
The receiver path uses a low IF scheme to down-convert the received signal for demodulation in the digital
demodulator and bit synchronizer. The receiver path provides a high degree of linearity, and an extended
dynamic range to ensure reliable operation in the noisy 2.4 GHz ISM band. The front-end topology, which has
built-in out-of-band attenuation, enables the CYW89820 to be used in most applications without off-chip filtering.
6.2.1
Digital demodulator and bit synchronizer
The digital demodulator and bit synchronizer take the low-IF received signal and perform an optimal frequency
tracking and bit synchronization algorithm.
6.2.2
Receiver signal strength indicator
The radio portion of the CYW89820 provides a receiver signal strength indicator (RSSI) to the baseband. This
enables the controller to take part in a Bluetooth® power-controlled link by providing a metric of its own receiver
signal strength to determine whether the transmitter should increase or decrease its output power.
6.3
Local oscillator
The local oscillator (LO) provides fast frequency hopping (1600 hops/second) across the band. The CYW89820
uses an internal loop filter.
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AIROC™ Bluetooth® system on chip for automotive applications
Peripherals
7
Peripherals
7.1
I2C compatible master
The CYW89820 provides a 2-pin I2C compatible master interface to communicate with I2C compatible periph-
erals. The I2C compatible master supports the following clock speeds:
• 100 kHz
• 400 kHz
• 800 kHz (Not a standard I2C-compatible speed.)
• 1 MHz (Compatibility with high-speed I2C-compatible devices is not guaranteed.)
The I2C compatible master is capable for doing read, write, write followed by read, and read followed by write
operations where read/write can be up to 64 bytes.
SCL and SDA lines can be routed to any of the P1-P37 GPIOs allowing for flexible system configuration. When used
as SCL/SDA the GPIOs go into open drain mode and require an external pull-up for proper operation. BSC does
not support multimaster capability or flexible wait-state insertion by either master or slave devices.
7.2
Serial peripheral interface
The CYW89820 has two independent SPI interfaces. Both interfaces support single, dual, and Quad Mode SPI
operations. Either interface can be a master or a slave. SPI1 has 1040-byte transmit and receive buffers (shared
with UART) and SPI2 has 256-byte dedicated transmit and receive buffers. To support more flexibility for user
applications, the CYW89820 has optional I/O ports that can be configured individually and separately for each
functional pin.
SPI IO voltage depends on VDDO.
7.3
HCI UART interface
The CYW89820 includes a UART interface for factory programming as well as when operating as a BT HCI device
in a system with an external host. The UART physical interface is a standard, 4-wire interface (RX, TX, RTS, and
CTS) with adjustable baud rates from 115200 bps to 3 Mbps. Typical rates are 115200, 921600, 1500000, and
3,000,000 bps although intermediate speeds are also available. Support for changing the baud rate during normal
HCI UART operation is included through a vendor-specific command. The CYW89820 UART operates correctly
with the host UART as long as the combined baud rate error of the two devices is within ±5%. The UART interface
CYW89820 has a 1040-byte receive FIFO and a 1040-byte transmit FIFO to support enhanced data rates. The
interface supports the Bluetooth® UART HCI (H4) specification. The default baud rate for H4 is 115.2 kbaud.
In HCI Mode, the CYW89820 can wake up the host as needed or allow the host to sleep via the HOST_WAKE signal.
The HOST_WAKE signal can be enabled via a vendor specific command.
The FW UART driver allows applications to select different baud rates.
7.4
Peripheral UART interface
The CYW89820 has a second UART that may be used to interface to peripherals. Functionally, the peripheral UART
is the same as the HCI UART except for 256 byte TX/RX FIFOs. The peripheral UART is accessed through the I/O
ports, which can be configured individually and separately for each functional pin. The CYW89820 can map the
peripheral UART to any LHL GPIO.
7.5
GPIO ports
The CYW89820 has 17 general purpose IOs labeled P1-P37. All GPIOs support the following:
• Programmable pull-up/down of approx 45 k
• Input disable, allowing pins to be left floating or analog signals connected without risk of leakage
• Source/sink 8 mA at 3.3 V and 4 mA at 1.8 V
• P26/P27/P28/P29 sink/source 16 mA at 3.3 V and 8 mA at 1.8 V
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AIROC™ Bluetooth® system on chip for automotive applications
Peripherals
Most peripheral functions can be assigned to any GPIO. For details, see Table 6 and Table 7.
7.6
ADC
The CYW89820 includes a Σ-Δ ADC designed for audio and DC measurements. The ADC can measure the voltage
on 14 GPIO (P1, P9-14, P17-19, P28, P29, P32, P37). When used for analog inputs, the GPIOs must be placed in
digital input disable mode to disconnect the digital circuit from the pin and avoid leakage. The internal bandgap
reference has ±5% accuracy without calibration. Calibration and digital correction schemes can be applied to
reduce ADC absolute error and improve measurement accuracy in Direct Current (DC) Mode.
The application can access the ADC through the ADC driver included in the firmware.
7.7
PWM
The CYW89820 has four internal PWMs, labeled PWM0-3.
• Each of the six PWM channels contains the following registers:
- 16-bit initial value register (read/write)
- 16-bit toggle register (read/write)
- 16-bit PWM counter value register (read)
• PWM configuration register is shared among PWM0–3 (read/write). This 18-bit register is used:
- To enable/disable each PWM channel
- To select the clock of each PWM channel
- To invert the output of each PWM channel. The application can access the PWM module through the FW driver.
Figure 9 shows the structure of one PWM channel.
pwm_cfg_adr register
pwm#_init_val_adr register
pwm#_togg_val_adr register
16
16
pwm#_cntr_adr
16
cntr value is ARM readable
pwm_out
Example: PWM cntr w/ pwm#_init_val = 0 (dashed line)
PWM cntr w/ pwm#_init_val = x (solid line)
16'HFFFF
pwm_togg_val_adr
16'Hx
16'H000
pwm_out
Figure 9
PWM block diagram
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AIROC™ Bluetooth® system on chip for automotive applications
Peripherals
7.8
PDM microphone
The CYW89820 accepts a ΣΔ-based one-bit pulse density modulation (PDM) input stream and outputs filtered
samples at either 8 kHz or 16 kHz sampling rates. The PDM signal derives from an external kit that can process
analog microphone signals and generate digital signals. The PDM inputs share the filter path with the aux ADC.
Two types of data rates can be supported:
• 8 kHz
• 16 kHz
The external digital microphone takes in a 2.4 MHz clock generated by the CYW89820 and outputs a PDM signal
which is registered by the PDM interface with either the rising or falling edge of the 2.4 MHz clock selectable
through a programmable control bit. The design can accommodate two simultaneous PDM input channels, so
stereo voice is possible.
7.9
I2S interface
The CYW89820 supports a single I2S digital audio port with both master and slave modes. The I2S signals are:
• I2S clock: I2S SCK
• I2S word select: I2S WS
• I2S data out: I2S DO
• I2S data in: I2S DI
I2S SCK and I2S WS become outputs in master mode and inputs in slave mode, while I2S DO always stays as an
output. The channel word length is 16 bits and the data is justified so that the MSN of the left-channel data is
aligned with the MSB of the I2S bus, per I2S Specifications. The MSB of each data word is transmitted one bit clock
cycle after the I2S WS transition, synchronous with the falling edge of bit clock. Left Channel data is transmitted
when I2S WS is low, and right-channel data is transmitted when I2S WS is high. Data bits sent by the CYW89820
are synchronized with the falling edge of I2S SCK and should be sampled by the receiver on the rising edge of the
I2S SCK.
The clock rate in master mode as follows:
• 16 kHz 16 bits per frame = 256 kHz
The master clock is generated from the reference clock using an N/M clock divider. In the slave mode, any clock
rate is supported up to a maximum of 3.072 MHz.
7.10
PCM interface
The CYW89820 includes a PCM interface that can connect to linear PCM codec devices in master or slave mode.
In master mode, the CYW89820 generates the PCM_CLK and PCM_SYNC signals. In slave mode, these signals are
provided by another master on the PCM interface and are inputs to the CYW89820.The configuration of the PCM
interface may be adjusted by the host through the use of vendor-specific HCI commands.
Note PCM interface shares HW with the I2S interface and only one can be used at any time. Only audio source
(other than SCO) use cases are supported on CYW89820.
7.10.1
Slot mapping
The CYW89820 supports up to three simultaneous full-duplex channels through the PCM Interface. These three
channels are time-multiplexed onto the single PCM interface by using a time-slotting scheme where the 8 kHz or
16 kHz audio sample interval is divided into as many as 16 slots. The number of slots is dependent on the selected
interface rate (128 kHz, 512 kHz, or 1024 kHz). The corresponding number of slots for these interface rate is 1, 2,
4, 8, and 16, respectively. Transmit and receive PCM data from an SCO channel is always mapped to the same
slot. The PCM data output driver tristates its output on unused slots to allow other devices to share the same PCM
interface signals. The data output driver tristates its output after the falling edge of the PCM clock during the last
bit of the slot.
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AIROC™ Bluetooth® system on chip for automotive applications
Peripherals
7.10.2
Frame synchronization
The CYW89820 supports both short- and long-frame synchronization in both master and slave modes. In short
frame synchronization mode, the frame synchronization signal is an active-high pulse at the audio frame rate that
is a single-bit period in width and is synchronized to the rising edge of the bit clock. The PCGM slave looks for a
high on the falling edge of the bit clock and expects the first bit of the first slot to start at the next rising edge of
the clock. In long-frame synchronization mode, the frame synchronization signal is again an active-high pulse at
the audio frame rate; however, the duration is three bit periods and the pulse starts coincident with the first bit
of the first slot.
7.10.3
Data formatting
The CYW89820 may be configured to generate and accept several different data formats. For conventional narrow
band speech mode, the CYW89820 uses 13 of the 16 bits in each PCM frame. The location and order of these 13
bits can be configured to support various data formats on the PCM interface. The remaining three bits are ignored
on the input and may be filled with 0s, 1s, a sign bit, or a programmed value on the output. The default format is
13-bit 2’s complement data, left justified, and clocked MSB first.
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AIROC™ Bluetooth® system on chip for automotive applications
Firmware
8
Firmware
The CYW89820 ROM firmware runs on a real time operating system and handles the programming and configu-
ration of all on-chip hardware functions as well as the BT/LE baseband, LMAC, HCI, GATT, ATT, L2CAP, and SDP
layers. The ROM also includes drivers for on-chip peripherals as well as handling on-chip power management
functions including transitions between different power modes. The ROM also supports OTA firmware update
and acts as a root of trust.
The CYW89820 is fully supported by the Infineon ModusToolbox™. ModusToolbox™ releases provide latest ROM
patches, drivers, and sample applications allowing customized applications using the CYW89820 to be built
quickly and efficiently.
Refer to the ModusToolbox™ software documentation for details on the firmware architecture and how to write
applications/profiles using the CYW89820.
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AIROC™ Bluetooth® system on chip for automotive applications
Pin assignments and GPIOs
9
Pin assignments and GPIOs
This section addresses 48-pin WQFN pin assignment and general purpose IOs (GPIOs) for the CYW89820 device.
Table 5. 48-pin WQFN pin assignment
Pin number
WQFN-48
Power
Pin name
I/O
Description
domain
Baseband supply
VDDO
VDDO1
VDDO2
31
6
39
I
I
I
I
VDDO
VDDO
VDDO
I/O pad power supply
I/O pad power supply
I/O pad power supply
ADC_AVDDBAT 36
ADC_AVDD ADC supply
VDDC
8, 30, 41
I/O VDDC
Baseband core power supply
RF power supply
IFVDD
PLLVDD
PAVDD
VCOVDD
24
I
I
I
I
IFVDD
IFPLL power supply
RFPLL and crystal oscillator supply
PA supply
26
22
25
PLLVDD
PAVDD
VCOVDD
VCO supply
Onboard LDOs
PALDO_VDDIN
PALDO_VDDOUT 18
17
I
O
I
–
–
–
PA LDO input
PA LDO output
Internal digital LDO input
DIGLDO_VDDIN
–
DIGLDO_-
VDDOUT
21
O
–
Internal digital LDO output
RFLDO_VDDIN
RFLDO_VDDOUT 19
–
I
O
–
–
RF LDO input
RF LDO output
RFLDO_DIGLDO
_VDDIN
20
I
–
Internal digital LDO and RF LDO input
SR_PVDD
SR_VLX
PMU_AVDD
Ground pins [1]
ADC_REFGND
VSSC
ADC_AVSS
MIC_AVSS
ADC_AVSSC
PMU_AVSS
PLLVSS
15
14
16
I
O
I
–
–
–
Core buck input
Core buck output
PMU supply
–
–
–
–
–
–
–
–
–
–
I
I
I
I
I
I
I
I
I
I
AVSS
VSS
AVSS
AVSS
AVSS
VSS
Analog reference ground
Ground
Analog ground
Microphone analog ground
Analog ground
PMU ground
Ground
VSS
VSS
PAVSS
Ground
VCOVSS
SR_PVSS
Note
VSS
VSS
Ground
Ground
1. All grounds in WQFN package connected to ground paddle.
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Pin assignments and GPIOs
Table 5. 48-pin WQFN pin assignment (continued)
Pin number
WQFN-48
Power
Pin name
I/O
Description
domain
IFVSS
–
I
VSS
Ground
UART
Clear to send (CTS) for HCI UART interface.
Leave unconnected if not used.
Request to send (RTS) for HCI UART interface.
Leave unconnected if not used.
UART serial input. Serial data input for the HCI UART
interface.
UART serial output. Serial data output for the HCI UART
interface.
UART_CTS_N
UART_RTS_N
UART_RXD
35
34
32
33
I, PU VDDO
O,
VDDO
PU
I
VDDO
VDDO
O,
PU
UART_TXD
Crystal
Crystal oscillator input. See “The XTAL must have an
accuracy of ±20 ppm as defined by the Bluetooth®
specification. Two external load capacitors are
required to work with the crystal oscillator. The
selection of the load capacitors is XTAL-dependent (see
Figure 1)” for options.
XTALI
27
I
PLLVDD
XTALO
28
38
37
–
O
I
O
O
PLLVDD
VDDO
VDDO
N/A
Crystal oscillator output
XTALI_32K
XTALO_32K
CLK_REQ
Other
Low-power oscillator input
Low-power oscillator output
Used for shared-clock application
RF
23
12
–
I
–
RF antenna port
Active-low system reset with internal pull-up
resistor.
RST_N
VDDO
Arm® JTAG debug mode control. Connect to GND for all
applications.
JTAG_SEL
GPIOs
13
–
–
A signal from the CYW89820 device to the host
indicating that the Bluetooth® device requires
attention.
HOST_WAKE
29
O
VDDO
• GPIO: P1
• Keyboard scan input (row): KSI1
• A/D converter input 28
• Peripheral UART: puart_rts
• SPI_1: MISO (slave only)
• UART1_RXD
P1
5
I/O VDDO
• Supermux I/O functions as defined in Table 6 and
Table 7.
Note
1. All grounds in WQFN package connected to ground paddle.
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Pin assignments and GPIOs
Table 5. 48-pin WQFN pin assignment (continued)
Pin number
WQFN-48
Power
Pin name
P2
I/O
Description
domain
• GPIO: P2
40
I/O VDDO
I/O VDDO
• Keyboard defined in Table 6 and Table 7.
• GPIO: P4
• Keyboard scan input (row): KSI4
• Quadrature: QDY0
P4
P6
42
43
46
• SPI_1: MOSI (master only)
• Supermux I/O functions as defined in Table 6 and
Table 7.
• GPIO: P6
• Keyboard scan input (row): KSI6
• Quadrature: QDZ0
• Peripheral UART: puart_rts
• PWM2
I/O VDDO
• Triac control 1
• Supermux I/O functions as defined in Table 6 and
Table 7.
• GPIO: P9
• Keyboard scan output (column): KSO1
• A/D converter input 26
P9
I/O VDDO
• External T/R switch control: tx_pd
• Supermux I/O functions as defined in Table 6 and
Table 7.
• GPIO: P10
• Keyboard scan output (column): KSO2
• A/D converter input 25
P10
47
48
I/O VDDO
• External PA ramp control: PA_Ramp
• Supermux I/O functions as defined in Table 6 and
Table 7.
• GPIO: P11
• Keyboard scan output (column): KSO3
• A/D converter input 24
P11
I/O VDDO
• Supermux I/O functions as defined in Table 6 and
Table 7.
Note
1. All grounds in WQFN package connected to ground paddle.
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Pin assignments and GPIOs
Table 5. 48-pin WQFN pin assignment (continued)
Pin number
WQFN-48
Power
Pin name
I/O
Description
domain
• GPIO: P12
• Keyboard scan output (column): KSO4
• A/D converter input 23
P12
1
I/O VDDO
• Supermux I/O functions as defined in Table 6 and
Table 7.
• GPIO: P13
• Keyboard scan output (column): KSO5
• A/D converter input 22
• PWM3
P13
2
I/O VDDO
• Triac control 3
• Supermux I/O functions as defined in Table 6 and
Table 7.
• GPIO: P14
• Keyboard scan output (column): KSO6
• A/D converter input 21
• PWM2
P14
P17
44
45
I/O VDDO
• Triac control 4
• Supermux I/O functions as defined in Table 6 and
Table 7.
• GPIO: P17
• Keyboard scan output (column): KSO9
• A/D converter input 18
I/O VDDO
• Supermux I/O functions as defined in Table 6 and
Table 7.
• GPIO: P26
• Keyboard scan output (column): KSO18
• PWM0
• SPI_1: SPI_CS (slave only)
• Optical control output: QOC0
• Triac control 1
P26
9
I/O VDDO
• Current: 16 mA sink
• Supermux I/O functions as defined in Table 6 and
Table 7.
Note
1. All grounds in WQFN package connected to ground paddle.
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Pin assignments and GPIOs
Table 5. 48-pin WQFN pin assignment (continued)
Pin number
WQFN-48
Power
Pin name
I/O
Description
domain
• GPIO: P27
• Keyboard scan output (column): KSO19
• PWM1
• SPI_1: MOSI (master only)
• Optical control output: QOC1
• Triac control 2
P27
10
I/O VDDO
• Current: 16 mA sink
• Supermux I/O functions as defined in Table 6 and
Table 7.
• GPIO: P28
• PWM2
• SCL3 (master and slave)
• Optical control output: QOC2
• A/D converter input 11
• Current: 16 mA sink
P28
3
I/O VDDO
• Supermux I/O functions as defined in Table 6 and
Table 7.
• GPIO: P29
• PWM3
• SDA3 (master and slave)
• Optical control output: QOC3
• A/D converter input 10
• Current: 16 mA sink
P29
4
I/O VDDO
• Supermux I/O functions as defined in Table 6 and
Table 7.
Note
1. All grounds in WQFN package connected to ground paddle.
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Pin assignments and GPIOs
Table 5. 48-pin WQFN pin assignment (continued)
Pin number
WQFN-48
Power
Pin name
I/O
Description
domain
• GPIO: P32
• A/D converter input 7
• Quadrature: QDX0
P32
11
I/O VDDO
• Auxiliary clock output: ACLK0
• Peripheral UART: puart_tx
• Supermux I/O functions as defined in Table 6 and
Table 7.
• GPIO: P37
• A/D converter input 2
• Quadrature: QDZ1
• SPI_1: MISO (slave only)
• Auxiliary clock output: ACLK1
• BSC: SCL
P37
7
I/O VDDO
• Supermux I/O functions as defined in Table 6 and
Table 7.
Note
1. All grounds in WQFN package connected to ground paddle.
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Pin assignments and GPIOs
Table 6
GPIO supermux input functions
Input
SWDCK
SWDIO
spiffy1_clk[s]
spiffy1_cs[s]
spiffy1_mosi[s]
spiffy1_miso[m]
spiffy1_io2
spiffy1_io3
spiffy1_int[s]
spiffy2_clk[s]
spiffy2_cs[s]
spiffy2_mosi[s]
spiffy2_miso[m]
spiffy2_io2
spiffy2_io3
spiffy2_int[s]
puart_rx
puart_cts_n
SCL
SDA
SCL2
SDA2
PCM_IN
PCM_CLK
PCM_SYNC
I2S_DI
I2S_WS
I2S_CLK
PDM_IN_Ch_1
PDM_IN_Ch 2
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Pin assignments and GPIOs
Table 7
Output
GPIO supermux output functions
do_P# (data out of GPIO. For example: P0)
do_PCM_IN
do_PCM_OUT
do_PCM_CLK
do_PCM_SYNC
do_I2S_DO
do_I2S_DI
do_I2S_WS
do_I2S_CLK
do_CLK_REQ
IR_TX
kso0
kso1
kso2
kso3
kso4
kso5
kso6
kso7
kso8
kso9
kso10
kso11
kso12
kso13
kso14
kso15
kso16
kso17
kso18
kso19
do_P# ^ pwm0
do_P# ^ pwm1
do_P# ^ pwm2
do_P# ^ pwm3
do_P# ^ pwm4
do_P# ^ pwm5
aclk0
aclk1
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Pin assignments and GPIOs
Table 7
Output
HID_OFF
pa_ramp
tx_pd
GPIO supermux output functions (continued)
~tx_pd
SWDIO
SDA2
SCL2
puart_tx (uart2_tx)
puart_rts_n (uart2_rts_n)
spiffy1_CLK
spiffy1_CS
spiffy1_MOSI
spiffy1_MISO
spiffy1_IO2
spiffy1_IO3
spiffy2_CLK
spiffy2_CS
spiffy2_MOSI
spiffy2_MISO
spiffy2_IO2
spiffy2_IO3
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AIROC™ Bluetooth® system on chip for automotive applications
Ball maps
10
Ball maps
10.1
48-pin WQFN pin map
The CYW89820 48-pin WQFN package is shown in Figure 11.
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ꢒꢆꢇꢓҖꢍꢑꢈ
ꢍꢌҖꢁꢈꢅ
ꢍꢌҖꢀꢁꢂꢂ
ꢀꢔꢋҖꢇꢃꢂꢂ ꢀꢇꢈꢂꢄҖꢁꢂꢂꢉꢎ
ꢀꢇꢁꢂꢂ
ꢌꢕ
ꢉꢕꢁꢂꢂ
ꢋꢆ
ꢋꢆ
ꢎ
ꢄꢋꢆ
тф
тх
тц
тч
тш
тщ
тъ
ус
ут
уу
уф
ух
Figure 10
48-pin WQFN pin map
Datasheet
31
002-25826 Rev. *G
2022-09-24
AIROC™ Bluetooth® system on chip for automotive applications
Specifications
11
Specifications
11.1
Electrical characteristics
The absolute maximum ratings in Table 8 indicate levels where permanent damage to the device can occur, even
if these limits are exceeded for only a brief duration. Functional operation is not guaranteed under these condi-
tions. Operation at absolute maximum conditions for extended periods can adversely affect long-term reliability
of the device.
Table 8
Absolute maximum ratings
Specification
Min
–
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
Requirement parameter
Unit
°C
Nom
–
Max
125
Maximum junction temperature
VDDO1/VDDO2
IFVDD/PLLVDD/VCOVDD/VDDC
PMUAVDD/SR_PVDD
DIGLDO_VDDIN
RFLDO_VDDIN
PALDO_VDDIN
PAVDD
–
–
–
–
–
–
3.795
1.38
3.795
1.65
1.65
3.79
2.75
V
2.5
Table 9
ESD/latchup
Specification
Requirement parameter
Unit
Min
–2000
–500
–
Nom
–
–
200
Max
2000
500
–
ESD Tolerance HBM
ESD Tolerance CDM
Latch-up
V
mA
Table 10
Environmental ratings
Characteristic
Value
Unit
Operating Temperature
Storage Temperature
–40 to +105
–40 to +150
°C
Datasheet
32
002-25826 Rev. *G
2022-09-24
AIROC™ Bluetooth® system on chip for automotive applications
Specifications
Table 11
Recommended operating conditions
Specification
Parameter
Unit
Min
1.045[2]
1.14
1.14
1.14
2.375
1.71
1.71
1.71
1.71
1.26
1.26
2.6
Typ
1.2
Max
1.26
1.26
1.26
1.26
2.625
3.63
3.63
3.63
3.63
1.38
1.38
3.63
VDDC
IFVDD[4]
PLLVDD[4]
VCOVDD[4]
PAVDD[4]
VDDO1[3]
VDDO2[3]
PMU_AVDD
SR_PVDD
RFLDO_VDDIN
DIGLDO_VDDIN
PALDO_VDDIN[4]
1.2
1.2
1.2
2.5
3.0
3.0
3.0
3.0
1.26
1.26
3.0
V
V
V
Notes
2. 1.14 V for >48 MHz operation.
3. VDDO1 must be equal to VDDO2. Recommend that these be provided from the same source.
4. IFVDD, PLLVDD, and VCOVDD must all be equal. Recommend providing from the same supply.PAVDD_VDDIN
min. must be greater than Vout + 100 mV under max. load current.
11.2
Brown out
The CYW89820 uses an onboard low voltage detector to shut down the part when supply voltage (VDDBAT3V)
drops below the operating range.
Table 12
Parameter
VSHUT
Shutdown voltage
Specification
Min
1.5
Unit
Typ
1.56
Max
1.7
V
11.2.1
Core buck regulator
Table 13
Core buck regulator
Conditions
Parameter
Min
1.71
–
–
1.1
0.76
Typ
3.0
< 60
< 60
1.26
0.94 Avg 1.4
(0.92-0.96
)
Max Unit
Input supply, VBAT
Output current
DC range
3.63
100
70
V
mA
Active mode
PDS mode
Active Mode
Output voltage
1.4
V
PDS mode, 40 mV min regulation window.
Output voltage
accuracy
Active mode, includes line and load regulation. –4
Before trim:
–
+4
%
Note
5. Minimum values represent minimums after derating due to tolerance, temperature, and voltage effects.
Datasheet
33
002-25826 Rev. *G
2022-09-24
AIROC™ Bluetooth® system on chip for automotive applications
Specifications
Table 13
Core buck regulator (continued)
Conditions
Parameter
Ripple voltage
Min
Typ
Max Unit
Active mode
–
3
–
mV
2.2 H ± 25% inductor, DCR = 114 m ± 20%
4.7 F ± 10% capacitor, Total ESR < 20 m
PDS mode
40
40
2.2
4.7
–
–
–
Output inductor, L
Output capacitor,
COUT
Refer to the “Recommended component” on
page 34 section for more details.
1.6[5]
3.0[5]
μH
μF
Input capacitor, CIN
Input supply voltage 0 to 3.3 V
ramp time
4.0[5]
40
10
–
–
–
μs
Note
5. Minimum values represent minimums after derating due to tolerance, temperature, and voltage effects.
11.2.2
Recommended component
Table 14
Recommended component
Conditions
Parameter
Min
–
Typ
2.2
Max
–
Unit
μH
External inductor, L
2.2 μH ±25%, DCR = 114 mΩ ±20%, ACR < 1Ω
(for frequency < 1 MHz)
External output capacitor,
COUT
External input capacitor, CIN For SR_VDDBAT pin
1 μF ±10%, 6.3V, 0603 inch, X5R, MLCC
capacitor +board total-ESR < 20 mΩ
0.7
–
1
1.1
–
μF
10
Ceramic, X5R, 0402, ESR < 30 mΩ at 4 MHz,
+/-20%, 6.3V, 4.7 μF
External input capacitor
Only use an external input capacitor at
VDD_DIGLDO pin if it is not supplied from
CBUCK output.
–
1
2.2
11.2.3
Digital LDO
Table 15
Digital LDO
Parameter
Condition
Min
Typ Max Unit
Input supply, DIGLDO_-
VDDIN
Min must be met for correct operation
VOUT + 20 mV 1.26 1.4
V
Range
Step
Accuracy after trimming
At max load current
DC Load
0.9
–
–2
–
0.075
–
1.55[6]
–
1.2
25
–
–
40
–
1.275
–
Output voltage, DIGLDO_-
VDDOUT
mV
%
mV
mA
μA
μF
mV/V
mV/m
A
+2
20
60
40
–
Dropout voltage
Output current
Quiescent current
At T ≤ 85C, VIN = 1.4V
Output load capacitor, COUT Total trace + cap ESR must be < 80 mΩ
2.2
5
Line regulation
Load regulation
Note
1.235 V ≤ VIN ≤ 1.4 V
10
VOUT = 1.2 V, VIN = 1.26 V, 1 mA ≤ IOUT ≤ 25 mA –
–
0.44
6. Minimum values represent minimums after derating due to tolerance, temperature, and voltage effects.
Datasheet
34
002-25826 Rev. *G
2022-09-24
AIROC™ Bluetooth® system on chip for automotive applications
Specifications
Table 15
Digital LDO (continued)
Condition
Parameter
Min
Typ Max Unit
IOUT step 1 mA 20 mA @ 1 μs rise/fall,
COUT = 2.2 μF, VIN = 1.235 V, VOUT = 1.2V
Power down Mode, VIN = 1.4 V, Temp = 25C –
Power down Mode, VIN = 1.4 V, Temp =
125C
COUT = 2.2 μF, VIN = 1.4 V, VOUT = 1.2 V
COUT = 2.2 μF, VIN = 1.4 V, VOUT = 1.2 V, IOUT
20 mA
Load step error
–24
–
–
–
–
–
+24
50
mV
nA
μA
mA
s
Leakage current
–
2
In-rush current
–
–
100
120
=
LDO turn on time
COUT = 2.2 μF, 1.235 V ≤ VIN ≤ 1.4 V, VOUT
1.2 V,
=
PSRR
IOUT = 20 mA
f = 1 kHz
f = 100 kHz
25
13
–
–
dB
dB
Note
6. Minimum values represent minimums after derating due to tolerance, temperature, and voltage effects.
11.2.4
Recommended component
Table 16
Recommended component
Conditions
Parameter
Min
–
Typ
1
Max
2.2
Unit
μF
External input capacitor
Only use an external input capacitor at
VDD_DIGLDO pin if it is not supplied from
CBUCK output.
11.2.5
RF LDO
Table 17
RF LDO
Parameter
Conditions
Min
Typ
Max Unit
Input supply, RFLDO_-
VDDIN
Min must be met for correct operation
VOUT + 20 mV 1.26 1.4
V
Output voltage, RFLDO_- Range
1.1
–
–2
–
0.075
–
1.55[7]
1.2
25
–
–
20
–
1.275
–
VDDOUT
Step
mV
%
mV
mA
μA
μF
Accuracy after trimming
+2
20
60
40
–
Dropout voltage
Output current
Quiescent current
Output load capacitor,
COUT
At max load current
DC Load
At T ≤ 85C, VIN = 1.4V
Total trace + cap ESR must be < 80 mΩ
2.2
Line regulation
Load regulation
Load step error
1.235 V ≤ VIN ≤ 1.4 V
–
5
–
–
10
mV/V
VOUT = 1.2 V, VIN = 1.26 V, 1 mA ≤ IOUT ≤ 25 mA –
0.44 mV/mA
+24 mV
I
OUT step 1 mA 20 mA @ 1 μs rise/fall,
–24
COUT = 2.2 μF, VIN = 1.235 V, VOUT = 1.2 V
Leakage current
Power down mode, VIN = 1.4 V, Temp = 25C
Power down mode, VIN = 1.4 V, Temp = 125C –
–
–
–
50
2
nA
μA
Note
7. Minimum values represent minimums after derating due to tolerance, temperature, and voltage effects.
Datasheet
35
002-25826 Rev. *G
2022-09-24
AIROC™ Bluetooth® system on chip for automotive applications
Specifications
Table 17
RF LDO (continued)
Conditions
COUT = 2.2 μF, VIN = 1.4 V, VOUT = 1.2 V
OUT = 2.2 μF, VIN = 1.4V, VOUT = 1.2 V, IOUT
20 mA
Parameter
In-rush current
LDO turn on time
Min
–
–
Typ
–
–
Max Unit
100 mA
120 μs
C
=
PSRR
C
OUT = 2.2 μF, 1.235 V ≤ VIN ≤ 1.4 V, VOUT
=
25
13
–
–
1.2 V,
dB
dB
IOUT = 20 mA
f = 1 kHz
f = 100 kHz
Noise
C
OUT = 2.2 μF, VIN = 1.235 V, VOUT = 1.2 V, IOUT
–
–
= 20 mA
80
70
nVHz
nVHz
f = 30 kHz
f = 100 kHz
Note
7. Minimum values represent minimums after derating due to tolerance, temperature, and voltage effects.
11.2.6
PALDO
Table 18
PALDO
Parameter
Conditions
Min
2.6
Typ
3.0
Max
3.63
3.0
Unit
Input supply, PALDO_- VDDIN min must be greater than VOUT+100 mV
VDDIN
V
under max load current for proper regulation
Range
Step
1.5
2.45
100
–
3.3
–
V
mV
%
Output voltage,
PALDO_VDDOUT
Accuracy
-4
–
–
0
–
+4
–
100
60
110
–
HTOL output voltage
Dropout voltage
Output current
Quiescent current
Output load capacitor, COUT
V
At max load current
DC Load
At T ≤ 85C, VIN = 3.3 V
mV
mA
μA
30
–
1.2[8] 2.2
μF
Line regulation
Load regulation
2.7 V ≤ VIN ≤ 3.3 V, VOUT = 2.5 V
IN = 3.3 V, VOUT = 2.5 V, 0 mA ≤ IOUT ≤ 30 mA
–
–
–
–
25
1
mV/V
mV/mA
V
IOUT step 1 mA20 mA @ 1 s rise/fall, COUT
2.2 F, VIN = 3.3 V, VOUT = 2.5 V
Power-down mode, VIN = 3.6 V, Temp = 25C
Power-down mode, VIN = 3.6 V, Temp = 125C
=
Load step error
Leakage current
-25
–
25
mV
–
–
–
–
–
–
–
–
1.6
4.9
140
140
μA
μA
mA
μs
In-rush current
LDO turn on time
C
C
OUT = 2.2 F, VIN = 3.3 V, VOUT = 2.5 V
OUT=2.2 F, VIN = 3.3 V, VOUT = 2.5 V, IOUT = 20 mA
COUT=2.2 F, VIN = 3.3 V, VOUT = 2.5 V, IOUT = 20 mA
45
25
–
–
–
–
dB
dB
PSRR
f = 1kHz
f = 100kHz
Note
8. Minimum values represent minimums after derating due to tolerance, temperature, and voltage effect.
Datasheet
36
002-25826 Rev. *G
2022-09-24
AIROC™ Bluetooth® system on chip for automotive applications
Specifications
11.2.7
Recommended component
Table 19
Recommended component
Conditions
Parameter
Min
0.5
Typ
2.2
Max
4.7
Unit
μF
External output capacitor, Total ESR (trace/cap): 5 m–240 mΩ
Co
External input capacitor
Only use an external input capacitor at
VDD_DIGLDO pin if it is not supplied from
CBUCK output.
–
1
2.2
11.2.8
Digital I/O characteristics
Table 20. Digital I/O characteristics
Characteristics
Symbol
VIL
VIH
VIL
VIH
VOL
VOH
Min
–
2.4
–
1.4
–
Typ
–
Max
0.8
–
0.4
–
0.4
–
Unit
V
Input low voltage (VDDO = 3 V)
Input high voltage (VDDO = 3 V)
Input low voltage (VDDO = 1.8 V)
Input high voltage (VDDO = 1.8 V)
Output low voltage
–
–
–
–
–
Output high voltage
VDDO –
0.4V
Input low current
Input high current
IIL
IIH
–
–
–
–
–
–
–
–
–
–
–
–
–
–
1.0
1.0
4.0
2.0
8.0
4.0
0.4
μA
Output low current (VDDO = 3 V, VOL = 0.4 V)
Output low current (VDDO = 3 V, VOL = 1.8 V)
Output high current (VDDO = 3 V, VOH = 2.6 V)
Output high current (VDDO = 1.8 V, VOH = 1.4 V)
Input capacitance
IOL
IOL
IOH
IOH
CIN
mA
pF
11.2.9
Current consumption
Table 21 provides the current consumption measurements taken at input of LDOIN and VDDIO combined
(LDOIN = VDDIO = 3.0 V).
Table 21
Current consumption
Operational mode
Conditions
Typ
1.3
2.55
5.9
22.0
16.5
8.7
Unit
48 MHz with Pause
48 MHz without Pause
Continuous RX
Continuous TX - 10.5 dBm
–
HCI
mA
RX
TX
PDS
ePDS
All RAM retained
32 kHz XTAL on
μA
HID-Off (SDS)
1.75
Datasheet
37
002-25826 Rev. *G
2022-09-24
AIROC™ Bluetooth® system on chip for automotive applications
Specifications
11.3
RF specifications
Note Table 22 and Table 23 apply to single-ended industrial temperatures. Unused inputs are left open.
Table 22
BR/EDR - Receiver RF specifications
Mode and conditions
Parameter
Min
Typ
Max
Unit
Receiver section
Frequency range
–
2402
–
–
–
–20
–
2480
MHz
dBm
GFSK, BDR GFSK 0.1% BER, 1 Mbps
–91[9]
–94
–
–
–
–
RX sensitivity
EDR 2M
EDR 3M
–
dB
–87.5
–
Maximum input
dBm
Interference performance
C/I cochannel
C/I 1 MHz adjacent channel
C/I 2 MHz adjacent channel
C/I 3 MHz adjacent channel
C/I image channel
GFSK, BDR GFSK 0.1% BER[10]
GFSK, BDR GFSK 0.1% BER[10]
GFSK, BDR GFSK 0.1% BER[10]
GFSK, BDR GFSK 0.1% BER[10]
GFSK, BDR GFSK 0.1% BER[10]
–
–
–
–
–
–
–
–
–
–
11.0
–4.0
–31.5
–42.5
–24.0
dB
C/I 1 MHz adjacent to image
channel
GFSK, BDR GFSK 0.1% BER[10]
–
–
–35.0
Out-of-band blocking performance (CW)[11]
30 MHz to 2000 MHz
2000 MHz to 2399 MHz
2498 MHz to 3000 MHz
3000 MHz to 12.75 GHz
BDR GFSK 0.1% BER
–
–
–
–
–10.0
–27
–27
–
–
–
–
BDR GFSK 0.1% BER
BDR GFSK 0.1% BER
BDR GFSK 0.1% BER
dBm
–10.0
Intermodulation performance[10]
BT, interferer signal level
Spurious Emissions
30 MHz to 1 GHz
1 GHz to 12.75 GHz
Notes
BDR GFSK 0.1% BER
–
–
–39.0
dBm
dBm
–
–
–
–
–
–
–57.0
–47.0
9. The receiver sensitivity is measured at BER of 0.1% on the device interface with dirty TX Off.
10.Desired signal is 10 dB above the reference sensitivity level (defined as –70 dBm).
11.Desired signal is 3 dB above the reference sensitivity level (defined as –70 dBm).
12.Desired signal is –64 dBm Bluetooth®-modulated signal, interferer 1 is –39 dBm sine wave at frequency f1,
interferer 2 is –39 dBm Bluetooth®-modulated signal at frequency f2, f0 = 2 * f1 – f2, and |f2 – f1| = n * 1 MHz,
where n = 3, 4, or 5. For the typical case, n = 4.
Datasheet
38
002-25826 Rev. *G
2022-09-24
AIROC™ Bluetooth® system on chip for automotive applications
Specifications
Table 23
BR/EDR - Transmitter RF specifications
Parameter
Min
Typ
Max
Unit
Transmitter section
Frequency range
BR TX power
BR TX power variation
EDR 2M TX power
2402
–
11.5
±2
2.5
1.5
±2
2480
MHz
dBm
dB
dBm
dBm
dB
–
–
–
–
–
–
–
–
–
–
–
–
EDR 3M TX power
EDR 2M power variation
EDR 3M power variation
Adjacent channel power
|M – N| = 2
±3
dB
–
–
–
–
–20
–40
dBm
|M – N| 3
Out-of-band spurious emission
30 MHz to 1 GHz
1 GHz to 12.75 GHz
1.8 GHz to 1.9 GHz
5.15 GHz to 5.3 GHz
LO performance
–
–
–
–
–
–
–
–
–36.0
–30.0
–47.0
–47.0
dBm
kHz
Initial carrier frequency tolerance
Frequency drift
–75
–
+75
DH1 packet
DH3 packet
DH5 packet
Drift rate
–25
–40
–40
–20
–
–
–
–
+25
+40
+40
20
kHz
kHz/50 µs
Frequency deviation
Average deviation in payload (sequence used is 00001111)
Maximum deviation in payload (sequence used is 10101010)
Channel spacing
140
115
–
–
–
1
175
–
–
kHz
MHz
Table 24
Bluetooth® LE RF specifications
Conditions
Parameter
Min
Typ
Max
Unit
Frequency range
RX sensitivity[13]
TX power
N/A
2402
–
2480
MHz
GFSK, BDR GFSK 0.1% BER 0.1% BER,
1 Mbps
N/A
–
–94.5
–
dBm
–
11.5
255
–
–
275
–
Mod Char: Delta F1 average N/A
225
99.9
0.8
kHz
%
Mod Char: Delta F2 max[14]
Mod Char: Ratio
N/A
N/A
–
–
%
Notes
13.Dirty TX is Off.
14.At least 99.9% of all delta F2 max frequency values recorded over 10 packets must be greater than 185 kHz.
Datasheet
39
002-25826 Rev. *G
2022-09-24
AIROC™ Bluetooth® system on chip for automotive applications
Specifications
Table 25
Bluetooth® LE2 RF specifications
Conditions
Parameter
Min
–
–
Typ
–91.5
11.5
Max
–
–
Unit
dBm
RX sensitivity[15]
TX power
–
–
Note
15.255 packet.
11.4
Timing and AC characteristics
In this section, use the numbers listed in the Reference column of each table to interpret the timing diagrams
shown in Figure 11 through Figure 16.
11.4.1
UART timing
Table 26
UART timing specifications
Characteristics
Reference
Min
–
Typ
–
–
–
Max
1.50
0.67
1.33
Unit
Bit periods
1
2
3
Delay time, UART_CTS_N low to UART_TXD valid.
Setup time, UART_CTS_N high before midpoint of stop bit. –
Delay time, midpoint of stop bit to UART_RTS_N high.
–
UART_CTS_N
2
1
UART_TXD
Midpoint of STOP bit
Midpoint of STOP bit
UART_RXD
3
UART_RTS_N
Figure 11
UART timing
Datasheet
40
002-25826 Rev. *G
2022-09-24
AIROC™ Bluetooth® system on chip for automotive applications
Specifications
11.4.2
SPI timing
The SPI interface can be clocked up to 12 MHz.
Table 27 and Figure 12 show the timing requirements when operating in SPI mode 0 and 2.
Table 27
SPI mode 0 and 2
Characteristics
Reference
Min
45
6
Max
–
½ SCK
–
Unit
ns
1
2
3
Time from master assert SPI_CSN to first clock edge
Setup time for MOSI data lines
Idle time between subsequent SPI transactions
1 SCK
SPI_CSN
3
1
SPI_CLK (mode 0)
SPI_CLK (mode 2)
2
First Bit
Second Bit
Second Bit
Last Bit
Last Bit
SPI_MOSI
SPI_MISO
Not Driven
First Bit
Not Driven
Figure 12
SPI timing, mode 0 and 2
Table 28 and Figure 13 show the timing requirements when operating in SPI mode 1 and 3.
Table 28
SPI Mode 1 and 3
Reference
Characteristics
Min
45
6
Max
–
½ SCK ns
–
Unit
1
2
3
Time from master assert SPI_CSN to first clock edge
Setup time for MOSI data lines
Idle time between subsequent SPI transactions
1 SCK
SPI_CSN
3
1
SPI_CLK (mode 1)
SPI_CLK (mode 3)
SPI_MOSI
2
First Bit
First Bit
Invalid bit
Invalid bit
Second Bit
Second Bit
Last Bit
Not Driven
Last Bit
Not Driven
SPI_MISO
Figure 13
SPI timing, mode 1 and 3
Datasheet
41
002-25826 Rev. *G
2022-09-24
AIROC™ Bluetooth® system on chip for automotive applications
Specifications
11.4.3
BSC interface timing
The specifications in Table 29 references Figure 14.
Table 29
BSC interface timing specifications (up to 1 MHz)
Reference
Characteristics
Min
Max
100
400
800
1000
–
–
–
–
–
Unit
1
Clock frequency
–
kHz
2
3
4
5
6
7
8
9
START condition setup time
START condition hold time
Clock low time
650
280
650
280
0
100
280
–
Clock high time
Data input hold time[16]
Data input setup time
STOP condition setup time
Output valid from clock
Bus free time[17]
ns
–
–
400
–
10
Note
650
16.As a transmitter, 125 ns of delay is provided to bridge the undefined region of the falling edge of SCL to avoid
unintended generation of START or STOP conditions.
17.Time that the CBUS must be free before a new transaction can start.
1
5
SCL
2
8
6
4
3
7
SDA
IN
10
9
SDA
OUT
Figure 14
BSC interface timing diagram
Datasheet
42
002-25826 Rev. *G
2022-09-24
AIROC™ Bluetooth® system on chip for automotive applications
Specifications
11.4.4
I2S
Table 30. Timing for I2S transmitters and receivers
Transmitter
Receiver
Lower limit
Min
Clock period T Ttr
Upper limit
Min Max
Lower limit
Upper limit
Min Max
Notes
Max
–
Min
Tr
Max
–
[18]
–
–
–
–
Master Mode: Clock generated by transmitter or receiver
[19]
[19]
HIGH tHC
LOWtLC
0.35Ttr
0.35Ttr
–
–
–
–
–
–
0.35Ttr
0.35Ttr
–
–
–
–
–
–
Slave mode: Clock accepted by transmitter or receiver
[18]
[18]
[19]
HIGH tHC
LOW tLC
–
–
–
0.35Ttr
0.35Ttr
–
–
–
–
–
–
–
–
–
0.35Ttr
0.35Ttr
–
–
–
–
–
–
Rise time tRC
Transmitter
Delay tdtr
Hold time thtr
Receiver
0.15Ttr
[20]
[19]
–
0
–
–
–
–
0.8T
–
–
–
–
–
–
–
–
–
[21]
[21]
Setup time tsr
Hold time thr
Notes
–
–
–
–
–
–
–
–
0.2Ttr
0.2Ttr
–
–
–
–
–
–
18.The system clock period T must be greater than Ttr and Tr because both the transmitter and receiver have
to be able to handle the data transfer rate.
19.At all data rates in master mode, the transmitter or receiver generates a clock signal with a fixed mark/space
ratio. For this reason, tHC and tLC are specified with respect to T.
20.In slave mode, the transmitter and receiver need a clock signal with minimum HIGH and LOW periods so that
they can detect the signal. So long as the minimum periods are greater than 0.35Tr, any clock that meets the
requirements can be used.
21.Because the delay (tdtr) and the maximum transmitter speed (defined by Ttr) are related, a fast transmitter
driven by a slow clock edge can result in tdtr not exceeding tRC which means thtr becomes zero or negative.
Therefore, the transmitter has to guarantee that thtr is greater than or equal to zero, so long as the clock
rise-time tRC is not more than tRCmax, where tRCmax is not less than 0.15Ttr.
22.To allow data to be clocked out on a falling edge, the delay is specified with respect to the rising edge of the
clock signal and T, always giving the receiver sufficient setup time.
23.The data setup and hold time must not be less than the specified receiver setup and hold time.
Datasheet
43
002-25826 Rev. *G
2022-09-24
AIROC™ Bluetooth® system on chip for automotive applications
Specifications
T
tRC*
tLC ≥0.35T
tHC ≥ 0.35T
VH = 2.0V
VL = 0.8V
SCK
thtr ≥ 0
totr ≤ 0.8T
SD and WS
T = Clock period
Ttr = Minimum allowed clock period for transmitter
T = Ttr
* tRC is only relevant for transmitters in slave mode.
Figure 15
I2S transmitter timing
T
tLC ≥ 0.35T
tHC ≥ 0.35
VH = 2.0V
SCK
VL = 0.8V
tsr ≥ 0.2T
thr ≥ 0
SD and WS
T = Clock period
Tr = Minimum allowed clock period for transmitter
T > Tr
Figure 16
I2S receiver timing
Datasheet
44
002-25826 Rev. *G
2022-09-24
AIROC™ Bluetooth® system on chip for automotive applications
Package information
12
Package information
12.1
Package thermal characteristics
Table 31
Package thermal characteristics
Description
Ambient air temperature
Total power (W)
Board temperature (°C)
Package-top temperature (°C)
Maximum junction temperature (°C)
Value
25
Unit
°C
W
°C
°C
0.15
N/A
N/A
28.2
3.87
0.1
21.2
5.25
13.1
2.6
105
0.15
N/A
N/A
107.6
2.63
0.1
17.5
5.25
13.1
2.6
°C
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C
W
°C
°C
°C
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
JB
JT
JA
JB
JC
JCbottom
Ambient air temperature
Total power (W)
Board temperature (°C)
Package-top temperature (°C)
Maximum junction temperature (°C)
JB
JT
JA
JB
JC
JCbottom
Note: Absolute junction temperature limits are maintained through active thermal monitoring.
Datasheet
45
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2022-09-24
AIROC™ Bluetooth® system on chip for automotive applications
Packaging diagrams
13
Packaging diagrams
13.1
48-Pin WQFN package
Figure 17
CYW89820 7 mm 7 mm 48-pin WQFN package
Datasheet
46
002-25826 Rev. *G
2022-09-24
AIROC™ Bluetooth® system on chip for automotive applications
Packaging diagrams
13.2
Tape reel and packaging specifications
Table 32
CYW89820 48-pin WQFN tape reel specifications
Value
Parameter
Quantity per reel
Reel diameter
Hub diameter
Tape width
2500 parts
13 inches
4 inches
16 mm
Pocket pitch
12 mm
Sprocket hole pitch
4 mm
The top-left corner of the CYW89820 package is situated near the sprocket holes, as shown in Figure 18.
Pin 1: Top left corner of package toward sprocket holes
Figure 18
Pin 1 orientation
Datasheet
47
002-25826 Rev. *G
2022-09-24
AIROC™ Bluetooth® system on chip for automotive applications
Ordering information
14
Ordering information
Table 33
Ordering information
Package
Part number
Ambient operating temperature
40°C to 105°C
40°C to 105°C
CYW89820BWMLG
CYW89820BWMLGT
7 mm 7 mm 48-pin WQFN
7 mm x 7 mm 48-pin WQFN, tape and reel
Datasheet
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AIROC™ Bluetooth® system on chip for automotive applications
Acronyms
15
Acronyms
Table 34
Term
ACL
ADC
AFH
Acronyms used in this document
Description
asynchronous connection-less
analog-to-digital converter
adaptive frequency hopping
ARM7TDMI-S Acorn RISC Machine 7 Thumb instruction, Debugger, Multiplier, Ice, Synthesizable
BBC
BDR
BLE
BR
Bluetooth® Baseband Core
basic data rate
Bluetooth® low energy
basic data rate
CMOS
CRC
ECDSA
ED
complementary metal oxide semiconductor
cyclic redundancy check
elliptic curve digital signature algorithm
erroneous data
EDR
EIR
enhanced data rate
extended inquiry response
extended power down sleep
extended synchronous connection-oriented
encryption pause resume
forward error correction
floating point unit
ePDS
eSCO
EPR
FEC
FPU
GAP
GATT
GCI
generic access profile
generic attribute profile
global coexistence interface
Gaussian Frequency Shift Keying
general-purpose I/O
GFSK
GPIO
HCI
host control interface
HEC
HID
I2C
header error control
human-interface device
inter-integrated circuit
inter-IC sound bus
I2S
IF
intermediate frequency
Joint Test Action Group
logical link control and adaptation protocol
link control
JTAG
L2CAP
LC
LCU
LDO
LE
link control unit
low drop out
low energy
LED
light emitting diode
Datasheet
49
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AIROC™ Bluetooth® system on chip for automotive applications
Acronyms
Table 34
Term
LHL
Acronyms used in this document (continued)
Description
lean high land
LMAC
LO
Lower MAC
local oscillator
LPO
low power oscillator
link supervision time out
master out slave in
on-board diagnostics
original equipment manufacturer
on chip flash
LSTO
MOSI
OBD
OEM
OCF
OTA
over-the-air
OTP
PA
one-time programmable
power amplifier
PBF
packet boundary flag
pulse code modulation
pulse density modulation
power down sleep
PCM
PDM
PDS
PLL
phase locked loop
PMU
POR
PWM
WQFN
QoS
RAM
power management unit
power-on reset
pulse width modulation
wettable plan quad flat no-lead
quality of service
random access memory
RC oscillator A resistor-capacitor oscillator is a circuit composed of an amplifier, which provides the output
signal, and a resistor-capacitor network, which controls the frequency of the signal.
RF
radio frequency
ROM
RSSI
RTC
RX/TX
SCO
SDS
SECI
SPI
read-only memory
receiver signal strength indicator
real time clock
receive/transmit
synchronous connection-oriented
Shut Down Sleep
serial enhanced coexistence interface
serial peripheral interface
secure simple pairing
SSP
SSR
sniff subrating
SWD
TRNG
TSSI
serial wire debug
True Random Number Generator
transmit signal strength indicator
Datasheet
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AIROC™ Bluetooth® system on chip for automotive applications
Acronyms
Table 34
Term
Acronyms used in this document (continued)
Description
UART
WDT
universal asynchronous receiver/transmitter
watchdog timer
Datasheet
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AIROC™ Bluetooth® system on chip for automotive applications
Revision history
Revision history
Document
Date
Description of changes
revision
**
*A
*B
2018-12-06 New datasheet
2019-25-03 Fixed typo in Page 3
2020-07-15 Added QDID and Declaration ID and updated Programmable TX Power to 11.5
dB in Features
Added PA LDO in Functional block diagram
Added Low-frequency clock sources and updated Power modes section.
Added PA LDO in Power management unit and Power configurations section
figures
Added Power configurations section
Added VDDO and ADC_AVDDBAT and updated PALDO_VDDOUT pins in Table 5.
Added PAVDD parameter value in Table 8
Updated PAVDD and PALDO_VDDIN values in Table 11
Updated VSHUT values in Table 12
Added new section PALDO and Table 18
Updated HCI, RX and ePDS typical values in Table 21
Updated Table 22, Table 23, Table 24, and Table 25 in RF specifications
*C
*D
2021-04-23 Updated Table 23
2021-06-11 Updated Table 21 to include BR, EDR, and Bluetooth® LE
Changed from BLE to Bluetooth® LE and BT to Bluetooth® throughout the
document
*E
*F
2021-06-16 Updated to remove Preliminary
2022-01-25 Updated PALDO_VDDIN value in Table 11
Updated Input Supply, PALDO_VDDIN max value in Table 18
*G
2022-09-24 Migrated to Infineon template
Updated EDR 2M and 3M TX power parameter values in Table 23
Datasheet
52
002-25826 Rev. *G
2022-09-24
Please read the Important Notice and Warnings at the end of this document
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IMPORTANT NOTICE
For further information on the product, technology,
The information given in this document shall in no
event be regarded as a guarantee of conditions or
characteristics (“Beschaffenheitsgarantie”).
Edition 2022-09-24
Published by
delivery terms and conditions and prices please
contact your nearest Infineon Technologies office
(www.infineon.com).
Infineon Technologies AG
81726 Munich, Germany
With respect to any examples, hints or any typical
values stated herein and/or any information
regarding the application of the product, Infineon
Technologies hereby disclaims any and all
warranties and liabilities of any kind, including
without limitation warranties of non-infringement of
intellectual property rights of any third party.
WARNINGS
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dangerous substances. For information on the types
in question please contact your nearest Infineon
Technologies office.
© 2022 Infineon Technologies AG.
All Rights Reserved.
Except as otherwise explicitly approved by Infineon
In addition, any information given in this document
is subject to customer’s compliance with its
obligations stated in this document and any
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concerning customer’s products and any use of the
product of Infineon Technologies in customer’s
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Document reference
002-25826 Rev. *G
The data contained in this document is exclusively
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