ERJ-3EKF1300V_技术文档

PD-97516

IR3853MPbF

TM

HIGHLY EFFICIENT

SupIRBuck

INTEGRATED 4A, SYNCHRONOUS BUCK REGULATOR

Features

Description

•

Greater than 95% Maximum Efficiency

Wide Input Voltage Range 1.5V to 21V

Wide Output Voltage Range 0.7V to 0.9*Vin

Continuous 4A Load Capability

The IR3853 SupIRBuck^TMis an easy-to-use, fully

integrated and highly efficient DC/DC

synchronous Buck regulator. The MOSFETs co-

packaged with the on-chip PWM controller make

Integrated Bootstrap-diode

IR3853

a

space-efficient solution, providing

High Bandwidth E/A for excellent transient

performance

accurate power delivery for low output voltage

applications.

•

Programmable Switching Frequency up to 1.5MHz

Programmable Over Current Protection

Over Voltage Protection

IR3853 is a versatile regulator which offers

programmability of start up time, switching

frequency and current limit while operating in

wide input and output voltage range.

Dedicated input for output voltage monitoring

Programmable PGood output

Hiccup Current Limit

The switching frequency is programmable from

250kHz to 1.5MHz for an optimum solution.

Precision Reference Voltage (0.7V, +/-1%)

Programmable Soft-Start

Enable Input with Voltage Monitoring Capability

Enhanced Pre-Bias Start-up

It also features important protection functions,

such as Pre-Bias startup, hiccup current limit,

over-voltage, and thermal shutdown to give

required system level security in the event of fault

conditions.

Seq input for Tracking applications

External Synchronization

-40^oC to 125^oC operating junction temperature

Thermal Protection

4mm x 5mm Power QFN Package

Halogen Free, Lead Free and RoHS compliant

Applications

•

Distributed Point of Load Power Architectures

Netcom Applications

•

Server Applications

•

Storage Applications

Computing Peripheral Voltage Regulators

General DC-DC Converters

Embedded Telecom Systems

Fig. 1. Typical application diagram

1

Rev 4.0

PD-97516

IR3853MPbF

ABSOLUTE MAXIMUM RATINGS

(Voltages referenced to GND unless otherwise specified)

•

Vin ……………………………………………………. -0.3V to 25V

Vcc ……………….….…………….……..……….…… -0.3V to 8V (Note2)

Boot

SW

……………………………………..……….…. -0.3V to 33V

…………………………………………..……… -0.3V to 25V(DC), -4V to 25V(AC, 100ns)

Boot to SW ……..…………………………….…..….. -0.3V to Vcc+0.3V (Note1)

OCSet ………………………………………….……. -0.3V to 30V (Max 30mA)

Input / output Pins ……………………………….. ... -0.3V to Vcc+0.3V (Note1)

PGND to GND ……………...………………………….. -0.3V to +0.3V

Storage Temperature Range ................................... -55°C To 150°C

Junction Temperature Range ................................... -40°C To 150°C (Note2)

ESD Classification …………………………… ……… JEDEC Class 1C

Moisture sensitivity level………………...………………JEDEC Level 3@260 °C (Note5)

Note1: Must not exceed 8V

Note2: Vcc must not exceed 7.5V for Junction Temperature between -10^oC and -40^oC

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the

device. These are stress ratings only and functional operation of the device at these or any other

conditions beyond those indicated in the operational sections of the specifications are not implied.

PACKAGE INFORMATION

4mm x 5mm POWER QFN

θ_JA

= 45^oC / W ^*

)

= 45^oC / W ^*

( Sync _ FET

11

12

SW

13

V_IN

( Ctrl _ FET

)

θ_J-PCB= 2^oC / W

PGnd

^*Exposed pads on underside

are connected to copper

pads of a 4-layer (2 oz.) PCB

14

Vcc

10

Boot

17

Gnd

Sync

Enable

9

8

15

16

PGood

Seq

1

4

7

2

3

5

6

Fb Vsns COMP Gnd Rt SS OCSet

ORDERING INFORMATION

PACKAGE

DESIGNATOR

PACKAGE

PIN COUNT

PARTS PER

REEL

DESCRIPTION

M

IR3853MTRPbF

IR3853MTR1PbF

17

4000

750

2

Rev 4.0

PD-97516

IR3853MPbF

Block Diagram

Fig. 2. Simplified block diagram of the IR3853

3

Rev 4.0

PD-97516

IR3853MPbF

Pin Description

Name

Description

1

Fb

Inverting input to the error amplifier. This pin is connected directly to the

output of the regulator via resistor divider to set the output voltage and

provide feedback to the error amplifier.

2

3

Vsns

Comp

Gnd

Sense pin for PGood

Output of error amplifier. An external resistor and capacitor network is

typically connected from this pin to Fb pin to provide loop compensation.

4;17

5

Signal ground for internal reference and control circuitry.

Rt

Set the switching frequency. Connect an external resistor from this pin to

Gnd to set the switching frequency. See Table 1 for Fs vs. Rt.

6

SS/SD

Soft start / shutdown. This pin provides user programmable soft-start

function. Connect an external capacitor from this pin to Gnd to set the

start up time of the output voltage. The converter can be shutdown by

pulling this pin below 0.3V.

7

8

OCSet

PGood

Sync

Current limit set point. A resistor from this pin to SW pin will set the

current limit threshold.

Power Good status pin. Output is open drain. Connect a pull up resistor

from this pin to Vcc.

9

Sync pin, connect external system clock to synchronize multiple POLs

with the same frequency

10

V_CC

This pin powers the internal IC and the drivers. A minimum of 1uF high

frequency capacitor must be connected from this pin to the power ground

(PGnd).

11

12

13

PGnd

SW

Power Ground. This pin serves as a separated ground for the MOSFET

drivers and should be connected to the system’s power ground plane.

Switch node. This pin is connected to the output inductor.

V_IN

Input voltage connection pin.

14

15

Boot

Supply voltage for high side driver. A 0.1uF capacitor must be connected

from this pin to SW.

Enable pin to turn on and off the device. Use two external resistors to set

the turn on threshold (see Enable section). Connect this pin to Vcc if it is

not used.

Enable

16

Seq

Sequence pin. Use two external resistors to set Simultaneous Power up

sequencing. If this pin is not used connect to Vcc.

4

Rev 4.0

PD-97516

IR3853MPbF

Recommended Operating Conditions

Symbol

Definition

Min

Max

Units

V_in

V_cc

Boot to SW

V_o

I_o

Input Voltage

Supply Voltage

Output Voltage

1.5

4.5

0.7

0

21*

5.5

0.9*Vin

4

V

Output Current

A

Fs

T_j

Switching Frequency

Junction Temperature

225

-40

1650

125

kHz

^oC

*SW node should not exceed 25V

Electrical Specifications

Unless otherwise specified, these specification apply over 4.5V< V_cc<5.5V, V_in=12V, 0^oC<T_j< 125^oC.

Typical values are specified at T_a= 25^oC.

PARAMETER

SYMBOL

TEST CONDITION

MIN

TYP

MAX

UNIT

POWER STAGE

Power Losses

P_loss

Vcc=5V, V_in=12V, V_o=1.8V,

I_o=4A, Fs=600kHz, L=2.2uH,

Note4

0.642

W

V_Boot-V_sw=5V, I_D=4A, Tj=25^oC

Top Switch

R_{ds(on)_Top}

R_{ds(on)_Bot}

T_db

21

19.75

10

29

26.5

30

mΩ

V_cc=5V, I_D=4A, T=25^oC

Bottom Switch

Deadband Time

j

Note4

5

ns

Bootstrap Diode Forward

Voltage

I(Boot)= 30mA

180

260

470

mV

SW leakage Current

Isw

SW=0V, Enable=0V

uA

6

SW=0V, Enable=high, SS=3V,

Vseq=0V, Note4

SUPPLY CURRENT

V_CCSupply Current (Standby)

I_CC(Standby)

SS=0V, Vcc=5V, Enable low ,

No Switching

500

uA

V_CCSupply Current (Dyn)

I_CC(Dyn)

SS=3V, Vcc=5V, Enable high,

Fs=500kHz

6

11

mA

REFERENCE VOLTAGE

Feedback Voltage

VFB

0.7

V

Accuracy

0^oC<Tj<125^oC

-1.0

-2.0

+1.0

-2.0

-40^oC<Tj<125^oC, Note3

%

SOFT START / SD

Soft Start Current

ISS

Vss(clamp)

SD

Source

14

20

26

3.3

0.3

uA

V

Soft Start Clamp Voltage

Shutdown Output Threshold

2.7

3.0

5

Rev 4.0

PD-97516

IR3853MPbF

Electrical Specifications

Unless otherwise specified, these specification apply over 4.5V< V_cc<5.5V, V_in=12V, 0^oC<T_j< 125^oC.

Typical values are specified at T_a= 25^oC.

PARAMETER

SYMBOL

TEST CONDITION

MIN

TYP

MAX

UNIT

ERROR AMPLIFIER

Input Offset Voltage

Vos

IFb(E/A)

IVseq(E/A)

Isink(E/A)

Isource(E/A)

SR

Vfb-Vseq, Vseq=0.8V

-10

-1

+10

+1

mV

Input Bias Current

Sink Current

μA

-1

+1

0.40

8

0.85

10

1.2

13

mA

Source Current

Slew Rate

Note4

7

12

20

V/μs

MHz

dB

Gain-Bandwidth Product

DC Gain

GBWP

Note4

20

100

3.4

30

40

Gain

Note4

110

3.5

120

3.75

220

1

Maximum Voltage

Minimum Voltage

Seq Common Mode Voltage

Vmax(E/A)

Vmin(E/A)

Vcc=4.5V

V

mV

V

Note4

0

OSCILLATOR

Rt Voltage

Vrt

F_S

0.665

225

0.7

250

500

1500

1.8

0.735

275

V

Rt=59K

Frequency Range

Rt=28.7K

Rt=9.31K, Note4

Note4

450

550

kHz

1350

1650

Ramp Amplitude

Ramp Offset

Vramp

Ramp(os)

Dmin(ctrl)

Dmax

Toff

Vp-p

V

Note4

0.6

Min Pulse Width

Max Duty Cycle

Note4

50

ns

Fs=250kHz

Note4

92

%

Fixed Off Time

130

200

ns

Sync Frequency Range

Sync Pulse Duration

Sync Level Threshold

Fsync

Tsync

High

225

100

2

1650

kHz

ns

V

Low

0.6

6

Rev 4.0

PD-97516

IR3853MPbF

Electrical Specifications

Unless otherwise specified, these specification apply over 4.5V< V_cc<5.5V, V_in=12V, 0^oC<T_j< 125^oC.

Typical values are specified at T_a= 25^oC.

PARAMETER

SYMBOL

TEST CONDITION

Fs=250kHz

MIN

TYP

MAX

UNIT

FAULT PROTECTION

20.8

43

23.6

48.8

154

0

26.4

54.6

172

+10

OCSET Current

I_OCSET

uA

Fs=500kHz

Fs=1500kHz

Note4

136

-10

OC comp Offset Voltage

SS off time

V_OFFSET

mV

Cycles

%Vref

ns

SS_Hiccup

OVP(trip)

4096

115

OVP Trip Threshold

OVP Fault Prop. Delay

Thermal Shutdown

Thermal Hysteresis

V_CC-Start-Threshold

V_CC-Stop-Threshold

Vsns Rising

Note4

110

120

150

OVP(delay)

Note4

140

20

°C

V

Note4

V_CC_UVLO_Start

V_CC_UVLO_Stop

Vcc Rising Trip Level

Vcc Falling Trip Level

3.95

3.65

4.15

3.85

4.35

4.05

INPUT/OUTPUT SIGNAL

Enable-Start-Threshold

Enable-Stop-Threshold

Enable leakage current

Power Good Threshold

PGood Comparator Delay

Enable_UVLO_Start Supply ramping up

Enable_UVLO_Stop Supply ramping down

1.14

0.9

1.2

1.0

1.36

1.06

V

Ien

Enable=3.3V

Vsns Rising

uA

15

90

VPG

80

85

256/Fs

2.1

%Vref

PG(Delay)

SS(Delay)

s

PGood Delay Comparator

Threshold

Relative to charge voltage,

SS rising

2

2.3

V

PGood Delay Comparator

Hysteresis

Delay(SShys)

Note4

260

300

0

340

mV

PGood Leakage Current

PGood Voltage Low

I(PGDlk)

10

uA

V

PG(voltage)

I_Pgood=-5mA

0.5

Note3: Cold temperature performance is guaranteed via correlation using statistical quality control. Not tested in production.

Note4: Guaranteed by Design but not tested in production.

Note5: Upgrade to industrial/MSL2 level applies from date codes 1227 (marking explained on application note AN1132 page 2).

Products with prior date code of 1227 are qualified with MSL3 for Consumer market.

7

Rev 4.0

PD-97516

IR3853MPbF

Typical Efficiency and Power Loss Curves

Vin=12V, Vcc=5V, Io=0.4A-4A, F_s=600kHz, Room Temperature, No Air Flow

The table below shows the inductors used for each of the output voltages

in the efficiency measurement.

Vo (V)

1

L (uH)

1

P/N

DCR (mOhm)

SPM6550T-1R0M100A

PCMB065T-1R5

7443340220

7443340330

4.7

6.7

4.4

6.5

1.2

1.5

1.8

3.3

5

1.5

2.2

3.3

97

95

93

91

89

87

85

83

81

0.4

0.8

1.2

1.6

2.0

2.4

2.8

3.2

3.6

4.0

Load Current (A)

1.0V

1.2V

1.5V

1.8V

3.3V

5V

0.85

0.75

0.65

0.55

0.45

0.35

0.25

0.15

0.05

0.4

0.8

1.2

1.6

2.0

2.4

2.8

3.2

3.6

4.0

Load Current (A)

1.0V

1.2V

1.5V

1.8V

3.3V

5.0V

8

Rev 4.0

PD-97516

IR3853MPbF

Typical Efficiency and Power Loss Curves

Vin=5V, Vcc=5V, Io=0.4A- 4A, Fs=600kHz, Room Temperature, No Air Flow

The table below shows the inductors used for each of the output voltages

in the efficiency measurement.

Vo (V)

1

1.2

1.5

1.8

3.3

L (uH)

1

P/N

DCR (mOhm)

SPM6550T-1R0M100A

PCMB065T-1R5

4.7

6.7

1

1.5

2.2

3.3

97

96

95

94

93

92

91

90

89

88

87

86

85

84

83

0.4

0.8

1.2

1.6

2.0

2.4

2.8

3.2

3.6

4.0

Load Current (A)

1.0V

1.2V

1.5V

1.8V

3.3V

0.65

0.55

0.45

0.35

0.25

0.15

0.05

0.4

0.8

1.2

1.6

2.0

2.4

2.8

3.2

3.6

4.0

Load Current (A)

1.0Vout

1.2Vout

1.5Vout

1.8Vout

3.3Vout

9

Rev 4.0

PD-97516

IR3853MPbF

TYPICAL OPERATING CHARACTERISTICS (-40^oC - 125^oC) F_s=500 kHz

Icc(Standby)

Icc(Dyn)

11.0

10.5

10.0

9.5

290

270

250

230

210

190

170

150

9.0

8.5

8.0

7.5

7.0

6.5

6.0

-40

-20

0

20

40

60

80

100

120

-40

-20

0

20

40

60

80

100

120

Temp[ ^oC]

IOCSET(500kHz)

FREQUENCY

550

540

530

520

510

500

490

480

470

460

450

54.0

53.0

52.0

51.0

50.0

49.0

48.0

47.0

46.0

45.0

44.0

43.0

-40

-20

0

20

40

60

80

100

120

-40

-20

0

20

40

60

80

100

120

Temp[ ^oC]

Vcc(UVLO) Stop

Vcc(UVLO) Start

4.16

4.11

4.06

4.01

3.96

3.91

3.86

3.81

3.76

4.46

4.41

4.36

4.31

4.26

4.21

4.16

4.11

4.06

-40

-20

0

20

40

Temp[ ^oC]

Enable(UVLO) Stop

60

80

100

120

-40

-20

0

20

40

60

80

100

120

Temp[ ^oC]

Enable(UVLO) Start

1.06

1.04

1.02

1.00

0.98

0.96

0.94

0.92

0.90

1.36

1.34

1.32

1.30

1.28

1.26

1.24

1.22

1.20

1.18

1.16

1.14

-40

-20

0

20

40

60

80

100

120

-40

-20

0

20

40

60

80

100

120

Temp[ ^οC]

Temp[ ^oC]

ISS

Vfb

26.0

24.0

22.0

20.0

18.0

16.0

14.0

711

706

701

696

691

686

-40

-20

0

20

40

60

80

100

120

-40

-20

0

20

40

60

80

100

120

Temp[ ^oC]

10

Rev 4.0

PD-97516

IR3853MPbF

Rdson of MOSFETs Over Temperature at Vcc=5V

27

26

25

24

23

22

21

20

19

18

17

16

-40

-20

0

20

40

60

80

100

120

Temperature [ °C]

Sync-FET

Ctrl-FET

11

Rev 4.0

PD-97516

IR3853MPbF

Circuit Description

THEORY OF OPERATION

If the input to the Enable pin is derived from the

bus voltage by a suitably programmed resistive

divider, it can be ensured that the IR3853 does not

turn on until the bus voltage reaches the desired

level. Only after the bus voltage reaches or

exceeds this level will the voltage at Enable pin

exceed its threshold, thus enabling the IR3853.

Therefore, in addition to being a logic input pin to

enable the IR3853, the Enable feature, with its

precise threshold, also allows the user to

implement an Under-Voltage Lockout for the bus

voltage V_in. This is desirable particularly for high

output voltage applications, where we might want

the IR3853 to be disabled at least until V_in

exceeds the desired output voltage level.

Introduction

The IR3853 uses a PWM voltage mode control

scheme with external compensation to provide

good noise immunity and maximum flexibility in

selecting inductor values and capacitor types.

The switching frequency is programmable from

250kHz to 1.5MHz and provides the capability of

optimizing the design in terms of size and

performance.

IR3853 provides precisely regulated output

voltage programmed via two external resistors

from 0.7V to 0.9*Vin.

The IR3853 operates with an external bias

supply from 4.5V to 5.5V, allowing an extended

operating input voltage range from 1.5V to 21V.

The device utilizes the on-resistance of the low

side MOSFET as current sense element, this

method enhances the converter’s efficiency and

reduces cost by eliminating the need for external

current sense resistor.

IR3853 includes two low R_ds(on)MOSFETs using

IR’s HEXFET technology. These are specifically

designed for high efficiency applications.

Fig. 3a. Normal Start up, Device turns on

when the Bus voltage reaches 10.2V

Under-Voltage Lockout and POR

Figure 3b. shows the recommended start-up

sequence for the non-sequenced operation of

IR3853, when Enable is used as a logic input.

The under-voltage lockout circuit monitors the

input supply Vcc and the Enable input. It assures

that the MOSFET driver outputs remain in the off

state whenever either of these two signals drop

below the set thresholds. Normal operation

resumes once Vcc and Enable rise above their

thresholds.

The POR (Power On Ready) signal is generated

when all these signals reach the valid logic level

(see system block diagram). When the POR is

asserted the soft start sequence starts (see soft

start section).

Enable

The Enable features another level of flexibility for

start up. The Enable has precise threshold which

is internally monitored by Under-Voltage Lockout

(UVLO) circuit. Therefore, the IR3853 will turn on

only when the voltage at the Enable pin exceeds

this threshold, typically, 1.2V.

Fig. 3b. Recommended startup sequence,

Non-Sequenced operation

12

Rev 4.0

PD-97516

IR3853MPbF

Figure 3c. shows the recommended startup

sequence for sequenced operation of IR3853

with Enable used as logic input.

Fig. 5. Pre-Bias startup pulses

Soft-Start

The IR3853 has a programmable soft-start to

control the output voltage rise and to limit the

current surge at the start-up. To ensure correct

start-up, the soft-start sequence initiates when

the Enable and Vcc rise above their UVLO

thresholds and generate the Power On Ready

(POR) signal. The internal current source

(typically 20uA) charges the external capacitor

C_sslinearly from 0V to 3V. Figure 6 shows the

waveforms during the soft start.

Fig. 3c. Recommended startup sequence,

Sequenced operation

The start up time can be estimated by:

Pre-Bias Startup

(

1.4- 0.7

)

*C_SS

IR3853 is able to start up into pre-charged

T_start

=

- - - - - - - - - - - - - - - - - - - - (1)

output,

which

prevents

oscillation

and

20μA

disturbances of the output voltage.

During the soft start the OCP is enabled to

protect the device for any short circuit and over

current condition.

The output starts in asynchronous fashion and

keeps the synchronous MOSFET off until the first

gate signal for control MOSFET is generated.

Figure 4 shows a typical Pre-Bias condition at

start up.

The synchronous MOSFET always starts with a

narrow pulse width and gradually increases its

duty cycle with a step of 25%, 50%, 75% and

100% until it reaches the steady state value. The

number of these startup pulses for the

synchronous MOSFET is internally programmed.

Figure 5 shows a series of 32, 16, 8 startup

pulses.

Fig. 6. Theoretical operation waveforms

during soft-start

Fig. 4. Pre-Bias startup

13

Rev 4.0

PD-97516

IR3853MPbF

Operating Frequency

1400

I_OCSet(μA) =

...................................(2)

The switching frequency can be programmed

between 250kHz – 1500kHz by connecting an

external resistor from R_tpin to Gnd. Table 1

tabulates the oscillator frequency versus R_t.

R_t(kΩ)

Table 1. shows I_OCSetat different switching

frequencies. The internal current source

develops a voltage across R_OCSet. When the low

side MOSFET is turned on, the inductor current

flows through the Q2 and results in a voltage at

OCSet which is given by:

Table 1. Switching Frequency and I_OCSetvs.

External Resistor (R_t)

V_OCSet= (I_OCSet∗R_OCSet)−(R_DS(on)∗I_L)..........(3)

R_t(kΩ)

47.5

35.7

28.7

23.7

20.5

17.8

15.8

14.3

12.7

11.5

10.7

9.76

9.31

F_s(kHz)

300

I_ocset(μA)

29.4

400

39.2

500

48.7

600

59.07

68.2

700

800

78.6

900

88.6

1000

1100

1200

1300

1400

1500

97.9

110.2

121.7

130.8

143.4

150.3

Fig. 7. Connection of over current sensing resistor

An over current is detected if the OCSet pin goes

below ground. Hence, at the current limit

threshold, V_OCset=0. Then, for a current limit

setting I_Limit, R_OCSetis calculated as follows:

Shutdown

The IR3853 can be shutdown by pulling the

Enable pin below its 1 V threshold. This will tri-

state both, the high side driver as well as the low

side driver. Alternatively, the output can be

shutdown by pulling the soft-start pin below 0.3V.

Normal operation is resumed by cycling the

voltage at the Soft Start pin.

R

_DS(on)* I

R_OCSet

=

^Limit......................(4)

I_OCSet

An overcurrent detection trips the OCP

comparator, latches OCP signal and cycles the

soft start function in hiccup mode.

Over-Current Protection

The hiccup is performed by shorting the soft-start

capacitor to ground and counting the number of

switching cycles. The Soft Start pin is held low

until 4096 cycles have been completed. The

OCP signal resets and the converter recovers.

After every soft start cycle, the converter stays in

this mode until the overload or short circuit is

removed.

The over current protection is performed by

sensing current through the R_DS(on)of low side

MOSFET. This method enhances the converter’s

efficiency and reduces cost by eliminating a

current sense resistor. As shown in figure 7, an

external resistor (R_OCSet) is connected between

OCSet pin and the switch node (SW) which sets

the current limit set point.

The OCP circuit starts sampling current typically

160 ns after the low gate drive rises to about 3V.

This delay functions to filter out switching noise.

An internal current source sources current (I_OCSet

) out of the OCSet pin. This current is a function

of Rt and hence, of the free-running switching

frequency.

14

Rev 4.0

PD-97516

IR3853MPbF

1.5V <Vin<16V

4.5V <Vcc<5.5V

Thermal Shutdown

Temperature sensing is provided inside IR3853.

The trip threshold is typically set to 140^oC. When

trip threshold is exceeded, thermal shutdown

turns off both MOSFETs and discharges the soft

start capacitor.

Enable

Vin

Boot

SW

Vo(master)

Vcc

PGood

Seq

OCSet

Fb

RA

Automatic restart is initiated when the sensed

temperature drops within the operating range.

There is a 20^oC hysteresis in the thermal

shutdown threshold.

Rt

RB

Comp

PGnd

SS/ SD

Gnd

1.5V <Vin<16V

4.5V <Vcc<5.5V

Output Voltage Sequencing

The

IR3853

can

accommodate

user

Enable

Vin

Boot

SW

programmable sequencing options using Seq,

Enable and Power Good pins.

Vo(slave)

Vcc

Vo(master)

PGood

OCSet

Fb

RC

RE

RF

Seq

Rt

RD

Vo1

Vo2

Comp

PGnd

SS/ SD

Gnd

Fig. 8b. Application Circuit for Simultaneous

Sequencing

Power-Good and Over-voltage Protection

The V_snspin forms an input to a window

comparator whose upper and lower thresholds

are 0.805V and 0.595V, respectively. Hence, the

Power Good signal is flagged when the V_snspin

voltage is within the PGood window, i.e.

between 0.595V to 0.805V, as shown in figure 9.

The PGood pin is open drain and it needs to be

externally pulled high. High state indicates that

output is in regulation. Figure 9a shows the

PGood timing diagram for non-tracking

operation. In this case, during startup, PGood

goes high after the SS voltage reaches 2.1V if

the Vsns voltage is within the PGood

comparator window. Figure 9.a and Figure 9.b

also show a 256 cycle delay between the Vsns

voltage entering within the thresholds defined by

the PGood window and PGood going high.

Simultaneous Powerup

Fig. 8a. Simultaneous Power-up of the slave

with respect to the master.

Through these pins, voltage sequencing such as

simultaneous

and

sequential

can

be

implemented. Figure 8. shows simultaneous

sequencing configurations. In simultaneous

power-up, the voltage at the Seq pin of the slave

reaches 0.7V before the Fb pin of the master. For

R_E/R_F=R_C/R_D, therefore, the output voltage of

the slave follows that of the master until the

voltage at the Seq pin of the slave reaches 0.7 V.

After the voltage at the Seq pin of the slave

exceeds 0.85V, the internal 0.7V reference of

the slave dictates its output voltage.

If the output voltage exceeds the over voltage

threshold, an over voltage trip signal asserts, this

will result to turn off the high side driver and turn

on the low side driver until the Vsns voltage

drops below 1.15*Vref threshold. Both drivers are

latched off until a reset performed by cycling

either Vcc or Enable.

The OVP threshold can be externally

programmed to user defined value. Figure 10

shows the response in over-voltage condition.

15

Rev 4.0

PD-97516

IR3853MPbF

TIMING DIAGRAM OF PGOOD FUNCTION

2.1V

1.4V

0.7V

SS

0

1.15*Vref(typical),

+/-5% for Min/Max

PGood window

0.85*Vref(typical),

+/-5% for Min/Max

Vsns

0

At point “A” the power Good

signal goes low, high drive turns

off, low drive turns on till Vsns

is above Over Voltage threshold

and the device latches off. POR

(Vcc/Enable) needs to be

PGood

recycled for new start up.

0

100ns(typical) Delay

256/Fs

A

Fig.9a IR3853 Non-Tracking Operation (Seq=Vcc)

Fig.9b IR3853 Tracking Operation

16

Rev 4.0

PD-97516

IR3853MPbF

TIMING DIAGRAM OF Over Voltage Protection

Fig.10 IR3853 Over Voltage Timing Diagram

External Synchronization

the frequency of the Sync (f_Sync) and the free-

running frequency (f_{Free_Run}) results in more

change in the effective amplitude of the ramp

signal.

The IR3853 incorporates an internal circuit which

enables synchronization of the internal oscillator

(using rising edge) to an external clock. An

external resistor from Rt pin to Gnd is still

required to set the free-running frequency close

to the Sync input frequency. This function is

important to avoid sub-harmonic oscillations due

to beat frequency for embedded systems when

multiple POL (point of load) regulators are used.

The synchronization clock can be applied during

IR3853 normal operation or before IR3853 start-

up. In any case, IR3853 will perform with the

external after the end of the PreBias cycle.

Applying the external signal to the Sync input

changes the effective value of the ramp signal

(Vramp/Vosc).

Therefore, since the ramp amplitude takes part in

calculating the loop-gain and bandwidth of the

regulator, it is recommended not to use a Sync

frequency which is much higher than the free-

running frequency. In addition, the effective value

of the ramp signal, given by equation (5), should

be used when the compensator is designed for

the regulator.

The pulse width of the external clock, which is

applied to the sync, should be greater than 100ns

and its high level should be greater than 2V,

while its lower level is less than 0.6V. If this pin is

left floating, the IC will run with the free running

frequency set by the resistor Rt.

V_osc

= 1.8× f_{Free _Run}f_Sync........................(5)

(eff )

Equation (5) shows that the effective amplitude

of the ramp (V_osc(eff)) is reduced after the external

Sync signal is applied. More difference between

17

Rev 4.0

PD-97516

IR3853MPbF

Maximum Duty Ratio Considerations

Minimum on time Considerations

A fixed off-time of 200 ns maximum is specified

for the IR3853. This provides an upper limit on

the operating duty ratio at any given switching

frequency. It is clear, that higher the switching

frequency, the lower is the maximum duty ratio at

which the IR3853 can operate. To allow a margin

of 50ns, the maximum operating duty ratio in any

application using the IR3853 should still

accommodate about 250 ns off-time. Fig 10.

shows a plot of the maximum duty ratio v/s the

switching frequency, with 250 ns off-time.

The minimum ON time is the shortest amount of

time for which the Control FET may be reliably

turned on, and this depends on the internal

timing delays. For the IR3853, the typical

minimum on-time is specified as 50 ns.

Any design or application using the IR3853 must

ensure operation with a pulse width that is higher

than this minimum on-time and preferably higher

than 100 ns. This is necessary for the circuit to

operate without jitter and pulse-skipping, which

can cause high inductor current ripple and high

output voltage ripple.

Max Duty Cycle

D

t_on

=

95

90

85

80

75

70

65

60

55

F_s

V_out

V_in× F_s

=

In any application that uses the IR3853, the

following condition must be satisfied:

250

450

650

850

1050

1250

1450

1650

t_on(min)≤ t_on

Switching Frequency (kHz)

V_out

∴ t_on(min)

≤

V_in× F_s

V_out

Fig. 11. Maximum duty cycle v/s switching

frequency.

∴V_in× F_s≤

t_on(min)

The minimum output voltage is limited by the

reference voltage and hence V_out(min)= 0.7 V.

Therefore, for V_out(min)= 0.7 V,

V_out(min)

∴V × F ≤

in

s

t_on(min)

0.7 V

∴V × F ≤

= 7×10⁶V/s

in

s

100ns

Therefore, at the maximum recommended input

voltage 21V and minimum output voltage, the

converter should be designed at a switching

frequency that does not exceed 333 kHz.

Conversely, for operation at the maximum

recommended operating frequency 1.65 MHz

and minimum output voltage, any voltage above

4.2 V may not be stepped down without pulse-

skipping.

18

Rev 4.0

PD-97516

IR3853MPbF

When an external resistor divider is connected to

the output as shown in figure 12.

Equation (6) can be rewritten as:

Application Information

Design Example:

The following example is a typical application for

IR3853. The application circuit is shown on page

25.

⎛

⎞

V

ref

⎜

⎟

R₉= R₈∗

...............................(9)

V_o−V

ref

⎝

⎠

V =12 V (13.2V max)

in

For the calculated values of R8 and R9 see

feedback compensation section.

V_o=1.8 V

I_o= 4 A

ΔV_o≤± 5%of Vo

VOUT

F = 600kHz

s

IR3853

IR3624

R8

Fb

R9

Enabling the IR3853

As explained earlier, the precise threshold of the

Enable lends itself well to implementation of a

UVLO for the Bus Voltage.

Fig. 12. Typical application of the IR3853 for

programming the output voltage

Soft-Start Programming

V_in

The soft-start timing can be programmed by

selecting the soft-start capacitance value. From

(1), for a desired start-up time of the converter,

the soft start capacitor can be calculated by

using:

IR3853

R₁

Enable

R₂

C_SS(μF) = T_start( ms ) × 0.02857..........(10)

Where T_startis the desired start-up time (ms).

For a start-up time of 3.5ms, the soft-start

capacitor will be 0.099μF. Choose a 0.1μF

ceramic capacitor.

For a maximum Enable threshold of V_EN= 1.36 V

R₂

V

*

=V_EN= 1.36V...........(6)

in(min)

R₁+ R₂

V_EN

¹V_{in( min )}−V_EN

Bootstrap Capacitor Selection

R₂= R

..........(7)

To drive the Control FET, it is necessary to

supply a gate voltage at least 4V greater than

the voltage at the SW pin, which is connected

the source of the Control FET . This is achieved

For a V_{in (min)}=10.2V, R₁=49.9K and R₂=7.5K is a

good choice.

by using

a bootstrap configuration, which

comprises the internal bootstrap diode and an

external bootstrap capacitor (C6), as shown in

Fig. 13. The operation of the circuit is as follows:

When the lower MOSFET is turned on, the

capacitor node connected to SW is pulled down

to ground. The capacitor charges towards V_cc

through the internal bootstrap diode, which has a

forward voltage drop V_D. The voltage V_cacross

the bootstrap capacitor C6 is approximately

given as

Programming the frequency

For F_s= 600 kHz, select R_t= 23.7 kΩ, using

Table. 1.

Output Voltage Programming

Output voltage is programmed by reference

voltage and external voltage divider. The Fb pin

is the inverting input of the error amplifier, which

is internally referenced to 0.7V. The divider is

ratioed to provide 0.7V at the Fb pin when the

output is at its desired value. The output voltage

is defined by using the following equation:

V_c≅V_cc−V_D..........................(11)

When the upper MOSFET turns on in the next

cycle, the capacitor node connected to SW rises

to the bus voltage V_in. However, if the value of

C6 is appropriately chosen, the voltage Vc

⎛

⎞

R₈

R₉

⎜

⎟

V_o= V_ref∗ 1+

.......... .......... .(8)

⎜

⎝

⎠

19

Rev 4.0

PD-97516

IR3853MPbF

Inductor Selection

across C6 remains approximately unchanged and

the voltage at the Boot pin becomes:

The inductor is selected based on output power,

operating frequency and efficiency requirements.

A low inductor value causes large ripple current,

resulting in the smaller size, faster response to a

load transient but poor efficiency and high output

noise. Generally, the selection of the inductor

value can be reduced to the desired maximum

ripple current in the inductor (Δi ) . The optimum

point is usually found between 20% and 50%

ripple of the output current.

V_Boot≅V +V_cc−V_D........................................(12)

in

For the buck converter, the inductor value for the

desired operating ripple current can be

determined using the following relation:

Δi

Δt

1

V −V_o= L∗ ; Δt = D ∗

in

F

s

Fig. 13. Bootstrap circuit to generate

Vc voltage

....................... (15)

V_o

L =

(

V −V_o∗

)

in

V ∗Δi * F

in

s

A bootstrap capacitor of value 0.1uF is suitable

for most applications.

Where:

V_in= Maximum input voltage

V_o= Output Voltage

Δi = Inductorripple current

F_s= Switching frequency

Δt = Turn on time

Input Capacitor Selection

The ripple current generated during the on time of

the upper MOSFET should be provided by the

input capacitor. The RMS value of this ripple is

expressed by:

D = Duty cycle

I_RMS= I_o∗ D ∗(1− D ) ........................(13)

If Δi ≈ 42%(I_o), then the output inductor is

calculated to be 1.52μH. Select L=1.5 μH.

V_o

D =

................................(14)

The PCMB065T-1R5MS from Cyntec provides a

compact inductor suitable for this application.

V

in

Where:

D is the Duty Cycle

I_RMSis the RMS value of the input capacitor

current.

Io is the output current.

For I_o=4A and D = 0.15, the I_RMS= 1.43A.

Ceramic capacitors are recommended due to

their peak current capabilities. They also feature

low ESR and ESL at higher frequency which

enables better efficiency. For this application, it is

advisable to have 2x10uF 25V ceramic capacitors

C3216X5R1E106M from TDK. In addition to

these, although not mandatory, a 1X330uF, 25V

SMD capacitor EEV-FK1E331P may also be

used as a bulk capacitor and is recommended if

the input power supply is not located close to the

converter.

20

Rev 4.0

PD-97516

IR3853MPbF

Output Capacitor Selection

The output LC filter introduces a double pole,

–40dB/decade gain slope above its corner

resonant frequency, and a total phase lag of 180^o

(see figure 13). The resonant frequency of the LC

filter is expressed as follows:

The voltage ripple and transient requirements

determine the output capacitors type and values.

The criteria is normally based on the value of the

Effective Series Resistance (ESR). However the

actual capacitance value and the Equivalent

Series Inductance (ESL) are other contributing

components. These components can be

described as

1

F_LC

=

................................(17)

2∗π L_o∗C_o

ΔV_o= ΔV_o(ESR)+ ΔV_o(ESL)+ ΔV_o(C)

Figure 14 shows gain and phase of the LC filter.

Since we already have 180^ophase shift from the

output filter alone, the system runs the risk of

being unstable.

ΔV_o(ESR)= ΔI_L* ESR

V −V

⎛

⎜

⎞

⎟

in

o

ΔV_o(ESL)

=

* ESL

L

⎝

⎠

...............(16)

ΔI_L

8* C_o* F_s

ΔV_o(C)

=

ΔV_o= Output voltage ripple

ΔI_L= Inductor ripple current

Since the output capacitor has a major role in the

overall performance of the converter and

determines the result of transient response,

selection of the capacitor is critical. The IR3853

can perform well with all types of capacitors.

Fig. 14. Gain and Phase of LC filter

The IR3853 uses a voltage-type error amplifier

with high-gain (110dB) and wide-bandwidth. The

output of the amplifier is available for DC gain

control and AC phase compensation.

As a rule, the capacitor must have low enough

ESR to meet output ripple and load transient

requirements.

The error amplifier can be compensated either in

Type-II or Type-III compensation.

The goal for this design is to meet the voltage

ripple requirement in the smallest possible

capacitor size. Therefore it is advisable to select

ceramic capacitors due to their low ESR and ESL

Local feedback with Type-II compensation is

shown in figure 14.

and

small

size.

Four

of

the

TDK

This method requires that the output capacitor

should have enough ESR to satisfy stability

C2102X5R0J226M (22uF, 6.3V, 3mOhm)

capacitors is a good choice.

requirements.

In

general,

for

Type-II

compensation the output capacitor’s ESR

generates a zero typically at 5kHz to 50kHz

which is essential for an acceptable phase

margin.

Feedback Compensation

The IR3853 is a voltage mode controller. The

control loop is a single voltage feedback path

including error amplifier and error comparator. To

achieve fast transient response and accurate

output regulation, a compensation circuit is

necessary. The goal of the compensation

network is to provide a closed-loop transfer

function with the highest 0 dB crossing frequency

and adequate phase margin (greater than 45^o).

The ESR zero of the output capacitor is

expressed as follows:

1

F_ESR

=

...........................(18)

2∗π*ESR*C_o

21

Rev 4.0

PD-97516

IR3853MPbF

Where:

V_in= Maximum Input Voltage

V_osc= Oscillator Ramp Voltage

F_o= Crossover Frequency

F_ESR= Zero Frequency of the Output Capacitor

F_LC= Resonant Frequency of the Output Filter

R₈= Feedback Resistor

To cancel one of the LC filter poles, place the

zero before the LC filter resonant frequency pole:

F_z= 75% F_LC

1

F_z= 0.75*

.....................................(23)

2π L_o* C_o

Use equations (21), (22) and (23) to calculate

C4.

One more capacitor is sometimes added in

parallel with C4 and R3. This introduces one

more pole which is mainly used to suppress the

switching noise.

Fig. 15. Type II compensation network

and its asymptotic gain plot

The additional pole is given by:

1

F_P=

...............................(24)

The transfer function (V_e/V_o) is given by:

C₄* C_POLE

2π * R₃*

C₄+ C_POLE

V_e

V_o

Z_f

1+ sR₃C₄

sR₈C₄

= H(s) = −

= −

.....(19)

Z_IN

The pole sets to one half of the switching

frequency which results in the capacitor C_POLE

:

The (s) indicates that the transfer function varies

as a function of frequency. This configuration

introduces a gain and zero, expressed by:

1

C_POLE

=

≅

....................(25)

1

π*R₃*F

s

π*R₃*F −

s

R₃

C₄

H

(

s

)

=

...................................... (20)

............................ (21)

R₈

For a general solution for unconditional stability

for any type of output capacitors, and a wide

range of ESR values, we should implement local

feedback with a Type-III compensation network.

The typically used compensation network for

voltage-mode controller is shown in figure 16.

1

F_z=

2π * R₃* C₄

First select the desired zero-crossover frequency

(F_o):

Again, the transfer function is given by:

F_o> F_ESRand F_o≤

(

1/5 ~ 1/10 * F_s

)

V_e

V_o

Z_f

= H(s) = −

Use the following equation to calculate R3:

Z_IN

By replacing Z_inand Z_faccording to figure 16,

the transfer function can be expressed as:

V_osc* F_o* F_ESR* R₈

R₃=

...........................(22)

V * F_L²_C

in

−

(

1+ sR₃C₄

)

[

1+ sC₇

(

R₈+ R₁₀

)]

H(s) =

⎡

⎤

⎥

⎛

⎞

C₄* C₃

⎜

⎟

sR₈

(

C₄+ C₃

)

1+ sR

(

1+ sR C

)

⎢

3

10

7

C₄+ C₃

⎢

⎥

⎦

⎝

⎠

⎣

.......(26)

22

Rev 4.0

PD-97516

IR3853MPbF

V^OUT

Compensator

Type

Output

Capacitor

Z^IN

F

_ESRvs F_o

C³

C⁷

R³

C⁴

Electrolytic

Tantalum

Type II

Type III

F_LC<F_ESR<F_o<F_s/2

F_LC<F_o<F_ESR

R

10

R⁸

Zf

Tantalum

Ceramic

Fb

Ve

E/A

R⁹

Comp

V^REF

The higher the crossover frequency, the

potentially faster the load transient response.

However, the crossover frequency should be low

enough to allow attenuation of switching noise.

Typically, the control loop bandwidth or crossover

frequency is selected such that

Gain(dB)

H(s) dB

Frequency

FZ¹

FZ²

FP²

FP³

F_o≤

(

1/5 ~ 1/10 * F_s

)

The DC gain should be large enough to provide

high DC-regulation accuracy. The phase margin

should be greater than 45^ofor overall stability.

Fig.16. Type III Compensation network and

its asymptotic gain plot

The compensation network has three poles and

two zeros and they are expressed as follows:

For this design we have:

V_in=12V

V_o=1.8V

V_osc=1.8V

V_ref=0.7V

L_o=1.5uH

C_o=4x22uF, ESR=3mOhm each

F_P1= 0..............................................................(27)

1

F_P2

=

...........................................(28 )

1

2π * R₁₀* C₇

1

F_P3

=

≅

............(29)

2π * R₃* C₃

⎛

⎞

C₄* C₃

It must be noted here that the value of the

capacitance used in the compensator design

must be the small signal value. For instance, the

small signal capacitance of the 22uF capacitor

used in this design (i.e. C3216X5R1E106M from

TDK) is 9.5uF at 1.8 V DC bias and 600 kHz

frequency. It is this value that must be used for all

computations related to the compensation. The

small signal value may be obtained from the

manufacturer’s datasheets, design tools or

SPICE models. Alternatively, they may also be

inferred from measuring the power stage transfer

function of the converter and measuring the

double pole frequency F_LCand using equation

(16) to compute the small signal C_o.

⎜

⎟

2π * R₃

C₄+ C₃

⎝

⎠

1

F_Z1

F_Z2

=

.............................................(30)

1

2π * R₃* C₄

1

=

≅

..........(31)

2π * C₇* (R₈+ R₁₀

)

2π * C₇* R₈

Cross over frequency is expressed as:

V

1

in

F = R₃* C₇*

*

.......................(32)

o

V_osc2π * L_o* C_o

Based on the frequency of the zero generated by

the output capacitor and its ESR, relative to

crossover frequency, the compensation type can

be different. The table below shows the

compensation types for relative locations of the

crossover frequency.

These result to:

F_LC=21 kHz

F_ESR=5.5 MHz

F_s/2=300 kHz

Select crossover frequency F_o=100 kHz

Since F_LC<F_o<F_s/2<F_ESR, Type-III is selected to

place the pole and zeros.

23

Rev 4.0

PD-97516

IR3853MPbF

Detailed calculation of compensation Type-III

R_DS(on)= 19.75 mΩ*1.25 = 24.687 mΩ

Desired Phase Margin Θ=70^o

I_SET≅ I_{o(LIM )}= 4 A*1.5 = 6 A

(50% over nominal output current )

1−sin Θ

1+sin Θ

F

_Z2= F

=17.63 kHz

= 567.1kHz

o

I_OCSet= 59.07 μA (at F = 600kHz)

s

1+sin Θ

1−sin Θ

R_OCSet= 2.51 kΩ Select R₇= 2.55 kΩ

F_P2= F

o

Select: F = 0.5* F_Z2= 8.82 kHz and

Z1

Setting the Power Good Threshold

F

_P3= 0.5*F = 300 kHz

s

Select:C₇= 2.2nF

Power Good threshold can be programmed by

using two external resistors (R5, R7 on Page 24).

Calculate R₃, C₃and C₄:

The following formula can be used to set the

threshold:

2π * F * L_o*C_o*V

o

R₃=

^osc;R₃= 2.44 kΩ

C₇*V

in

Select: R₃= 2.43 kΩ

V_o

(PGood _TH )

R₆= (

−1)* R₇

- - (33)

0.85*V_ref

1

C₄=

C₃=

;C₄= 7.43 nF, Select: C₄= 8.2 nF

2π *F *R

Z1

3

Where: 0.85*Vref is reference of the internal

comparator, for IR3853.

V_{o(PGood_TH)}is the selectable output voltage

threshold for power good, for this design it is

1.53V (i.e. 0.85*1.8V).

1

;C₃= 222 pF, Select:C₃= 220 pF

2π * F *R₃

P3

Calculate R₁₀, R₈and R₉:

1

Select R₇=2.55KOhm

Using (24): R₅=3.97KOhm

Select R₆=4.02KOhm

R₁₀

=

; R₁₀=128 Ω, Select:R₁₀=130 Ω

-R₁₀; R₈= 3.97 kΩ,

2π *C₇* F

P2

1

R₈=

2π *C₇* F

Z2

Select:R₈= 4.02kΩ

The PGood is an open drain output. Hence, it is

necessary to use a pull up resistor R_PGfrom

PGood pin to Vcc. The value of the pull-up

resistor must be chosen such as to limit the

current flowing into the PGood pin, when the

output voltage is not in regulation, to less than 5

mA. A typical value used is 10kΩ.

V

ref

R₉=

*R₈;R₉= 2.56 kΩ Select:R₉= 2.55 kΩ

V -V

o

ref

Programming the Current-Limit

The Current-Limit threshold can be set by

connecting a resistor (R_OCSET) from the SW pin

to the OCSet pin. The resistor can be calculated

by using equation (4). This resistor R_OCSETmust

be placed close to the IC.

The R_DS(on)has

a

positive temperature

coefficient and it should be considered for the

worst case operation.

R_OCSet∗I_OCSet

I_SET= I_{L (critical )}

=

...........(32)

R_{DS (on )}

24

Rev 4.0

PD-97516

IR3853MPbF

Application Diagram:

Vin=12V

C_in= 2 X 10 uF +

330 uF+1x0.1uF

R₁

49.9 K

4.5V <Vcc<5.5V

R₂

7.5K

Enable

Vin

Boot

SW

Seq

Vcc

C6

0.1 uF

Lo

1.5uH

Vo

R_PG

10 K

C_Vcc

1uF

R_OCSet

2.55 K

PGood

R7

4.02 K

OCSet

Vsns

C7

2.2nF

R8

4.02 K

Co=4X22uF

R5

2.55 K

Sync

Rt

R10

130

R_t

23.7 K

Fb

C4

8.2 nF

R3

2.43 K

R9

2.55 K

Comp

PGnd

SS/ SD

Gnd

C_SS

0.1 uF

C3

220 pF

Fig. 17. Application circuit diagram for a 12V to 1.8 V, 4A Point Of Load Converter

Suggested Bill of Materials for the application circuit:

Part Reference Quantity Value

Description

SMD Elecrolytic, Fsize, 25V, 20%

1206, 25V, X5R, 20%

0603, 25V, X7R, 10%

7x7x5mm, 20%, 6.7mOhm

0805, 6.3V, X5R, 20%

Thick Film, 0603,1/10 W,1%

Thick Film, 0603,1/10W,1%

Manufacturer

Panasonic

TDK

Panasonic

Cyntec

TDK

Rohm

Part Number

EEV-FK1E331P

1

2

1

4

1

330uF

10uF

0.1uF

1.5uH

22uF

49.9k

7.5k

Cin

C3216X5R1E106M

ECJ-1VB1E104K

PCMB065T-1R5MS

C2102X5R0J226M

MCR03EZPFX4992

MCR03EZPFX7501

MCR03EZPFX2372

Lo

Co

R1

R2

R_t

23.7k

R_PG

1

10k

Thick Film, 0603,1/10W,1%

Rohm

MCR03EZPFX1002

C_ssC6

2

1

2

3

1

0.1uF

2.43k

220pF

8.2nF

4.02k

2.55k

130

2200pF

1.0uF

IR3853

0603, 25V, X7R, 10%

Thick Film, 0603,1/10W,1%

50V, 0603, NPO, 5%

Panasonic

Rohm

Panasonic

Rohm

ECJ-1VB1E104K

MCR03EZPFX2431

ECJ-1VC1H221J

ECJ-1VB1H822K

MCR03EZPFX4021

MCR03EZPFX2551

ERJ-3EKF1300V

ECJ-1VB1H222K

ECJ-BVB1C105M

R3

C3

C4

R8 R6

R9 R5 Rocset

R10

C7

C_Vcc

U1

0603, 50V, X7R, 10%

Thick Film, 0603,1/10W,1%

0603, 50V, X7R, 10%

0603, 16V, X5R, 20%

SupIRBuck, 4A, PQFN 4x5mm

Rohm

Panasonic

International Rectifier IR3853MPbF

25

Rev 4.0

PD-97516

IR3853MPbF

TYPICAL OPERATING WAVEFORMS

Vin=12.0V, Vcc=5V, Vo=1.8V, Io=0-4A, Room Temperature, No Air Flow

Fig. 18: Start up at 4A Load

Ch₁:V_in, Ch₂:V_out, Ch₃:V_ss, Ch₄:Enable

Fig. 19: Start up at 4A Load,

Ch₁:V_in, Ch₂:V_out, Ch₃:V_ss, Ch₄:V_PGood

Fig. 21: Output Voltage Ripple, 4A

load Ch₂: V_out

Fig. 20: Start up with 1.62V Pre-

Bias, 0A Load, Ch₂:V_out, Ch₃:V_SS

Fig. 23: Short (Hiccup) Recovery

Ch₂:V_out, Ch₃:V_ss

Fig. 22: Inductor node at 4A load

Ch₂: Switch Node

26

Rev 4.0

PD-97516

IR3853MPbF

TYPICAL OPERATING WAVEFORMS

Vin=12V, Vcc=5V, Vo=1.8V, Io=2A- 4A, Room Temperature, No Air Flow

Fig. 24: Transient Response, 2A to 4A step 2.5A/μs

Ch₂:V_out, Ch₄:I_out

27

Rev 4.0

PD-97516

IR3853MPbF

TYPICAL OPERATING WAVEFORMS

Vin=12V, Vcc=5V, Vo=1.8V, Io=4A, Room Temperature, No Air Flow

Fig. 25: Bode Plot at 4A load shows a bandwidth of 93kHz and phase margin of 51

degrees

Fig. 26: Synchronization to 700kHz external clock signal at 4A load

Ch₁: SW (Switch Node) Ch₂:Sync

28

Rev 4.0

PD-97516

IR3853MPbF

TYPICAL OPERATING WAVEFORMS

Simultaneous Tracking at Power Up and Power Down

Vin=12V, Vo=1.8V, Io=4A, Room Temperature, No Air Flow

3.3V

VOUT

IR3853

IR3624

4.02K

R

8

R_s1

R_s2

4.02K

2.55K

Seq

Fb

2.55K

R9

Fig. 27: Simultaneous Tracking a 3.3V input at power-up and shut-down

Ch₁: SEQ(3.3V) Ch₂:SS(1.8V) Ch₄: Vout(1.8V)

29

Rev 4.0

PD-97516

IR3853MPbF

Layout Considerations

The connection between the OCSet resistor and

the SW pin should not share any trace with the

connection between the bootstrap capacitor and

the SW pin. Instead, it is recommended to use a

Kelvin connection of the trace from the OCSet

The layout is very important when designing high

frequency switching converters. Layout will affect

noise pickup and can cause a good design to

perform with less than expected results.

Make all the connections for the power

components in the top layer with wide, copper

filled areas or polygons. In general, it is desirable

to make proper use of power planes and

polygons for power distribution and heat

dissipation.

The inductor, output capacitors and the IR3853

should be as close to each other as possible.

This helps to reduce the EMI radiated by the

power traces due to the high switching currents

through them. Place the input capacitor directly at

the Vin pin of IR3853.

The feedback part of the system should be kept

away from the inductor and other noise sources.

The critical bypass components such as

capacitors for Vcc should be close to their

respective pins. It is important to place the

feedback components including feedback

resistors and compensation components close to

Fb and Comp pins.

Vin

PGnd

resistor _Vinand the trace from the bootstrap

PGnd

capacitor at the SW pin.

In a multilayer PCB use one layer as a power

^{ground plane and have a control circuit}V^groo^uu^ndt

AGnd

(analog ground), to which all signals are

referenced. The goal is to localize the high

current path to a separate loop that does not

interfere with the more sensit^Viv^oe^utanalog control

AGnd

function. These two grounds must be connected

together on the PC board layout at a single point.

The Power QFN is a thermally enhanced

package. Based on thermal performance it is

recommended to use at least a 4-layers PCB. To

effectively remove heat from the device the

exposed pad should be connected to the ground

plane using vias. Figure 28 illustrates the

implementation of the layout guidelines outlined

above, on the IRDC3853 4 layer demoboard.

Enough copper &

minimum length

ground path between

Input and Output

Compensation parts

should be placed as close

as possible to

the Comp pin.

Vin

PGnd

All bypass caps should

be placed as close as

possible to their

connecting pins.

Vout

Resistors Rt, SS cap,

and Rocset should be

placed as close as

possible to their pins.

AGnd

Fig. 28a. IRDC3853 demoboard layout

considerations – Top Layer

30

Rev 4.0

PD-97516

IR3853MPbF

PGnd

Vin

Single point

connection between

AGND & PGND; It

should be close to the

SupIRBuck, kept

away from noise

sources.

SW

PGnd

Vout

Fig. 28b. IRDC3853 demoboard layout

considerations – Bottom Layer

PGnd

AGnd

Fig. 28c. IRDC3853 demoboard layout

considerations – Mid Layer 1

Use separate trace for

connecting Boost cap and

Rocset to the switch node

and with the minimum

length traces. Avoid big

loops.

Feedback trace should be

kept away form noise

sources

Fig. 28d. IRDC3853 demoboard layout

considerations – Mid Layer 2

31

Rev 4.0

PD-97516

IR3853MPbF

PCB Metal and Components Placement

Evaluations have shown that the best overall performance is achieved using the substrate/PCB layout

as shown in following figures. PQFN devices should be placed to an accuracy of 0.050mm on both X

and Y axes. Self-centering behavior is highly dependent on solders and processes, and experiments

should be run to confirm the limits of self-centering on specific processes. For further information,

please refer to “SupIRBuck™ Multi-Chip Module (MCM) Power Quad Flat No-Lead (PQFN) Board

Mounting Application Note.” (AN-1132)

PCB metal pad sizing (all dimensions in mm)

PCB metal pad spacing (all dimensions in mm)

32

Rev 4.0

PD-97516

IR3853MPbF

Solder Resist

IR recommends that the larger Power or Land Area pads are Solder Mask Defined (SMD.) This allows

the underlying Copper traces to be as large as possible, which helps in terms of current carrying

capability and device cooling capability.

When using SMD pads, the underlying copper traces should be at least 0.05mm larger (on each edge)

than the Solder Mask window, in order to accommodate any layer to layer misalignment. (i.e. 0.1mm in X

& Y.)

However, for the smaller Signal type leads around the edge of the device, IR recommends that these are

Non Solder Mask Defined or Copper Defined.

When using NSMD pads, the Solder Resist Window should be larger than the Copper Pad by at least

0.025mm on each edge, (i.e. 0.05mm in X&Y,) in order to accommodate any layer to layer misalignment.

Ensure that the solder resist in-between the smaller signal lead areas are at least 0.15mm wide, due to

the high x/y aspect ratio of the solder mask strip.

33

Rev 4.0

PD-97516

IR3853MPbF

Stencil Design

Stencils for PQFN can be used with thicknesses of 0.100-0.250mm (0.004-0.010"). Stencils thinner

than 0.100mm are unsuitable because they deposit insufficient solder paste to make good solder

joints with the ground pad; high reductions sometimes create similar problems. Stencils in the range

of 0.125mm-0.200mm (0.005-0.008"), with suitable reductions, give the best results.

Evaluations have shown that the best overall performance is achieved using the stencil design shown

in following figure. This design is for a stencil thickness of 0.127mm (0.005"). The reduction should be

adjusted for stencils of other thicknesses.

Stencil pad sizing (all dimensions in mm)

Stencil pad spacing (all dimensions in mm)

34

Rev 4.0

PD-97516

IR3853MPbF

IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105

TAC Fax: (310) 252-7903

This product has been designed and qualified for the Industrial market (Note5)

Visit us at www.irf.com for sales contact information

Data and specifications subject to change without notice. 08/12

35

Rev 4.0


型号：	ERJ-3EKF1300V
厂家：	Infineon
描述：	HIGHLY EFFICIENT INTEGRATED 4A, SYNCHRONOUS BUCK REGULATOR 高效的综合4A ，同步降压稳压器稳压器开关
文件：	总35页 (文件大小：973K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ERJ-3EKF1300V [INFINEON]

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