HYB3118165BST-50 [INFINEON]
1M x 16-Bit Dynamic RAM 1k Refresh; 1M ×16位动态RAM 1K刷新
| 型号： | HYB3118165BST-50 |
| 厂家： | 
Infineon |
| 描述： | 1M x 16-Bit Dynamic RAM 1k Refresh |
| 文件： | 总24页 (文件大小：194K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
1M × 16-Bit Dynamic RAM
1k Refresh
HYB 5118165BSJ/BST-50/-60
HYB 3118165BSJ/BST-50/-60
(Hyper Page Mode-EDO)
Advanced Information
• 1 048 576 words by 16-bit organization
• 0 to 70 °C operating temperature
• Hyper Page Mode-EDO-operation
• Performance:
-50 -60
50 60
13 15
25 30
tRAC RAS access time
ns
ns
ns
tCAC CAS access time
tAA Access time from address
tRC Read/Write cycle time
tHPC Hyper page mode (EDO) cycle time
84 104 ns
20 25 ns
• Power Dissipation, Refresh & Addressing:
HYB5118165
HYB3118165
-50 -60
-50
-60
Power Supply
Addressing
Refresh
5 V ± 10 %
3.3 V ± 0.3 V
10/10
10/10
1024 cycles / 16 ms
632 468
Active
715
414 mW
mW
TTL Standby
CMOS Standby
11
7.2
3.6
5.5
mW
• Read, write, read-modify-write, CAS-before-RAS refresh, RAS-only refresh and hidden refresh
• All inputs, outputs and clocks fully TTL (5 V versions) and LV-TTL (3.3 V version)-compatible
• Plastic Package: P-SOJ-42-1
400 mil
P-TSOPII-50/44-1 400 mil
Semiconductor Group
1
1998-10-01
HYB 5118165BSJ/BST-50/-60
HYB 3118165BSJ/BST-50/-60
1M × 16 EDO-DRAM
The HYB 5(3)118165 are 16 MBit dynamic RAMs based on die revisions “G” & “F” and organized
as 1 048 576 words by 16-bits. The HYB 5(3)118165 utilizes a submicron CMOS silicon gate
process technology, as well as advanced circuit techniques to provide wide operating margins, both
internally and for the system user. Multiplexed address inputs permit the HYB 5(3)18165 to be
packaged in a standard SOJ-42 and TSOPII-50/44 plastic package with 400 mil width. These
packages provide high system bit densities and are compatible with commonly used automatic
testing and insertion equipment.
Ordering Information
Type
Ordering Code Package
Descriptions
HYB 5118165BSJ-50 Q67100-Q1107 P-SOJ-42-1 400 mil
HYB 5118165BSJ-60 Q67100-Q1108 P-SOJ-42-1 400 mil
5 V 50 ns EDO-DRAM
5 V 60 ns EDO-DRAM
3.3 V 50 ns EDO-DRAM
3.3 V 60 ns EDO-DRAM
HYB 3118165BSJ-50 on request
HYB 3118165BSJ-60 on request
HYB 5118165BST-50 on request
HYB 5118165BST-60 on request
HYB 3118165BST-50 on request
HYB 3118165BST-60 on request
P-SOJ-42-1 400 mil
P-SOJ-42-1 400 mil
P-TSOPII-50/44-1 400 mil 5 V 50 ns EDO-DRAM
P-TSOPII-50/44-1 400 mil 5 V 60 ns EDO-DRAM
P-TSOPII-50/44-1 400 mil 3.3 V 50 ns EDO-DRAM
P-TSOPII-50/44-1 400 mil 3.3 V 60 ns EDO-DRAM
Semiconductor Group
2
1998-10-01
HYB 5118165BSJ/BST-50/-60
HYB 3118165BSJ/BST-50/-60
1M × 16 EDO-DRAM
Pin Names and Configuration
HYB 5(3)118165
A0 - A9
A0 - A9
RAS
Row Address Inputs
Column Address Inputs
Row Address Strobe
Upper Column Address Strobe
Lower Column Address Strobe
Output Enable
UCAS
LCAS
OE
Data Input/Output
I/O1 - I/O16
WE
Read/Write Input
Power Supply
VCC
Ground (0 V)
VSS
Not Connected
N.C.
P-TSOPII-50/44-1 (400 mil)
P-SOJ-42-1 (400 mil)
VCC
VSS
1
50
49
48
47
46
45
44
43
42
41
40
V
V
SS
1
2
3
4
5
6
7
8
42
41 I/O16
CC
I/O1
I/O2
I/O3
2
I/O16
I/O15
I/O14
I/O1
I/O2
I/O3
I/O4
3
40
39
38
37
36
35
34
33
32
I/O15
I/O14
I/O13
4
I/O4
VCC
5
I/O13
VSS
6
I/O5
I/O6
I/O7
I/O8
N.C.
7
I/O12
I/O11
I/O10
I/O9
V
V
CC
SS
8
I/O5
I/O6
I/O7
I/O8
N.C.
N.C.
WE
RAS
N.C.
N.C.
A0
I/O12
9
I/O11
I/O10
I/O9
10
11
9
N.C.
10
11
12
13
14
15
16
17
N.C.
31 LCAS
N.C.
N.C.
15
16
17
18
19
20
21
22
23
24
25
36
35
34
33
32
31
30
29
28
27
26
N.C.
LCAS
UCAS
OE
30
29
28
27
26
25
24
23
22
UCAS
OE
A9
A8
A7
A6
A5
A4
WE
RAS
A11 / N.C.
A10 / N.C.
A0
A9
A8
A7
A1 18
A1
A6
A2
A3
V
19
20
21
A2
A5
A3
VCC
A4
VSS
V
CC
SS
SPP03457
SPP02812
Semiconductor Group
3
1998-10-01
HYB 5118165BSJ/BST-50/-60
HYB 3118165BSJ/BST-50/-60
1M × 16 EDO-DRAM
. . .
I/O1 I/O2
I/O16
.
.
.
Data In
Buffer
Data Out
Buffer
OE
16
WE
UCAS
LCAS
&
16
No.2 Clock
Generator
Column
Address
Buffers (10)
10
10
Column
Decoder
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
Refresh
Controller
16
Sense Amplifier
I/O Gating
Refresh
Counter (10)
1024
x 16
10
.
.
.
Row
Address
Buffers (10)
10
10
Row
Decoder
Memory Array
1024 x 1024 x
16
1024
.
.
.
No.1 Clock
Generator
RAS
V
V
Voltage Down
Generator
CC
CC
(internal)
SPB02826
Block Diagram for HYB 5118165BSJ
Semiconductor Group
4
1998-10-01
HYB 5118165BSJ/BST-50/-60
HYB 3118165BSJ/BST-50/-60
1M × 16 EDO-DRAM
Absolute Maximum Ratings
Operating temperature range ........................................................................................... 0 to 70 °C
Storage temperature range........................................................................................ – 55 to 150 °C
Input/output voltage (5 V versions).................................................... – 0.5 to min (VCC + 0.5, 7.0) V
Input/output voltage (3.3 V versions)................................................. – 0.5 to min (VCC + 0.5, 4.6) V
Power supply voltage (5 V versions) ....................................................................... – 1.0 V to 7.0 V
Power supply voltage (3.3 V versions) .................................................................... – 1.0 V to 4.6 V
Power dissipation (5 V versions) ............................................................................................. 1.0 W
Power dissipation (3.3 V versions) .......................................................................................... 0.5 W
Data out current (short circuit) ................................................................................................ 50 mA
Note: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent
damage of the device. Exposure to absolute maximum rating conditions for extended periods
may affect device reliability.
DC Characteristics
TA = 0 to 70 °C, VSS = 0 V, tT = 2 ns
Parameter
Symbol
Limit Values
Unit Test
Condition
min.
max.
5 V Versions
Power supply voltage
VCC
VIH
4.5
2.4
– 0.5
2.4
–
5.5
V
1
1
1
1
Input high voltage
VCC + 0.5 V
Input low voltage
VIL
0.8
–
V
V
V
Output high voltage (IOUT = – 5 mA)
Output low voltage (IOUT = 4.2 mA)
3.3 V Versions
VOH
VOL
0.4
Power supply voltage
VCC
VIH
3.0
2.0
– 0.5
2.4
–
3.6
V
1
1
1
1
Input high voltage
VCC + 0.5 V
Input low voltage
VIL
0.8
–
V
V
V
V
V
TTL Output high voltage (IOUT = – 2 mA)
TTL Output low voltage (IOUT = 2 mA)
VOH
VOL
0.4
CMOS Output high voltage (IOUT = – 100 µA) VOH
VCC – 0.2 –
CMOS Output low voltage (IOUT = 100 µA)
VOL
–
0.2
Semiconductor Group
5
1998-10-01
HYB 5118165BSJ/BST-50/-60
HYB 3118165BSJ/BST-50/-60
1M × 16 EDO-DRAM
DC Characteristics (cont’d)
TA = 0 to 70 °C, VSS = 0 V, tT = 2 ns
Parameter
Symbol Limit Values Unit Notes
min. max.
Common Parameters
1
Input leakage current
(0 V ≤ VIH ≤ VCC + 0.3 V, all other pins = 0 V)
II(L)
– 10
– 10
10 µA
10 µA
1
Output leakage current
(DO is disabled, 0 V ≤ VOUT ≤ VCC + 0.3 V)
IO(L)
ICC1
Average VCC supply current
2, 3, 4
2, 3, 4
-50 ns version
-60 ns version
–
–
130
115
mA
mA
(RAS, CAS, address cycling: tRC = tRC MIN.
)
Standby VCC supply current (RAS = CAS = VIH)
ICC2
–
2
mA
–
Average VCC supply current, during RAS-only refresh ICC3
2, 4
2, 4
cycles
-50 ns version
–
–
130
115
mA
mA
-60 ns version
)
(RAS cycling, CAS = VIH, tRC = tRC MIN.
Average VCC supply current, during hyper page mode ICC4
2, 3, 4
2, 3, 4
(EDO)
-50 ns version
–
–
50
40
mA
mA
-60 ns version
(RAS = VIL, CAS, address cycling: tPC = tPC MIN.
)
1
Standby VCC supply current
(RAS = CAS = VCC – 0.2 V)
ICC5
–
1
mA
Average VCC supply current, during CAS-before-RAS ICC6
2, 4
2, 4
refresh mode
-50 ns version
–
–
130
115
mA
mA
-60 ns version
(RAS, CAS cycling: tRC = tRC MIN.
)
Semiconductor Group
6
1998-10-01
HYB 5118165BSJ/BST-50/-60
HYB 3118165BSJ/BST-50/-60
1M × 16 EDO-DRAM
Capacitance
TA = 0 to 70 °C, f = 1 MHz
Parameter
Symbol
Limit Values
Unit
min.
max.
Input capacitance (A0 to A11)
CI1
–
–
–
5
7
7
pF
pF
pF
Input capacitance (RAS, UCAS, LCAS, WE, OE) CI2
I/O capacitance (I/O1 - I/O16)
CIO
5, 6
AC Characteristics
TA = 0 to 70 °C, VCC = 5 V ± 10 % / VCC = 3.3 V ± 0.3 V, tT = 2 ns
Parameter
Symbol
Limit Values
-50 -60
min. max. min. max.
Unit Note
Common Parameters
Random read or write cycle time
RAS precharge time
tRC
84
30
50
8
–
–
104
40
–
–
ns
ns
tRP
RAS pulse width
tRAS
tCAS
tASR
tRAH
tASC
tCAH
tRCD
tRAD
tRSH
tCSH
tCRP
tT
10k 60
10k 10
10k ns
10k ns
CAS pulse width
Row address setup time
Row address hold time
Column address setup time
Column address hold time
RAS to CAS delay time
RAS to column address delay
RAS hold time
0
–
0
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
8
–
10
0
–
0
–
–
8
–
10
14
12
15
50
5
–
12
10
13
40
5
37
25
–
45
30
–
CAS hold time
–
–
CAS to RAS precharge time
Transition time (rise and fall)
Refresh period for 1k-refresh version
–
–
7
1
50
16
1
50
16
tREF
–
–
Read Cycle
8, 9
Access time from RAS
Access time from CAS
Access time from column address
OE access time
tRAC
tCAC
tAA
–
–
–
–
50
13
25
13
–
–
–
–
60
15
30
15
ns
ns
ns
ns
8, 9
8, 10
tOEA
Semiconductor Group
7
1998-10-01
HYB 5118165BSJ/BST-50/-60
HYB 3118165BSJ/BST-50/-60
1M × 16 EDO-DRAM
5, 6
AC Characteristics (cont’d)
TA = 0 to 70 °C, VCC = 5 V ± 10 % / VCC = 3.3 V ± 0.3 V, tT = 2 ns
Parameter
Symbol
Limit Values
-50 -60
min. max. min. max.
Unit Note
Column address to RAS lead time
Read command setup time
Read command hold time
tRAL
tRCS
tRCH
25
0
–
30
0
–
ns
ns
–
–
11
0
–
0
–
ns
11
Read command hold time referenced to RAS tRRH
0
–
0
–
ns
8
CAS to output in low-Z
Output buffer turn-off delay
Output turn-off delay from OE
Data to CAS low delay
Data to OE low delay
tCLZ
tOFF
tOEZ
tDZC
tDZO
tCDD
tODD
0
–
0
–
ns
12
0
13
13
–
0
15
15
–
ns
12
0
0
ns
13
0
0
ns
13
0
–
0
–
ns
14
CAS high to data delay
OE high to data delay
10
10
–
13
13
–
ns
14
–
–
ns
Write Cycle
Write command hold time
Write command pulse width
Write command setup time
Write command to RAS lead time
Write command to CAS lead time
Data setup time
tWCH
tWP
8
8
0
8
8
0
8
–
–
–
–
–
–
–
10
10
0
–
–
–
–
–
–
–
ns
ns
15
tWCS
tRWL
tCWL
tDS
ns
10
10
0
ns
ns
16
ns
16
Data hold time
tDH
10
ns
Read-Modify-Write Cycle
Read-write cycle time
tRWC
tRWD
tCWD
tAWD
tOEH
113
64
27
39
10
–
–
–
–
–
138
77
32
47
13
–
–
–
–
–
ns
15
RAS to WE delay time
ns
15
CAS to WE delay time
ns
15
Column address to WE delay time
OE command hold time
ns
ns
Hyper Page Mode (EDO) Cycle
Hyper page mode (EDO) cycle time
CAS precharge time
tHPC
tCP
20
8
–
–
25
10
–
–
ns
ns
Semiconductor Group
8
1998-10-01
HYB 5118165BSJ/BST-50/-60
HYB 3118165BSJ/BST-50/-60
1M × 16 EDO-DRAM
5, 6
AC Characteristics (cont’d)
TA = 0 to 70 °C, VCC = 5 V ± 10 % / VCC = 3.3 V ± 0.3 V, tT = 2 ns
Parameter
Symbol
Limit Values
-50 -60
min. max. min. max.
Unit Note
7
Access time from CAS precharge
Output data hold time
tCPA
tCOH
tRAS
tRHCP
tOES
–
27
–
–
5
32
–
ns
5
ns
RAS pulse width in EDO mode
CAS precharge to RAS delay
OE setup time prior to CAS
50
27
5
200k 60
200k ns
–
–
32
5
–
–
ns
5
–
Hyper Page Mode (EDO) Read-Modify-Write Cycle
Hyper page mode (EDO) read-write cycle time tPRWC
58
41
–
–
68
49
–
–
ns
ns
CAS precharge to WE
tCPWD
CAS-before-RAS Refresh Cycle
CAS setup time
tCSR
tCHR
tRPC
tWRP
tWRH
10
10
5
–
–
–
–
–
10
10
5
–
–
–
–
–
ns
ns
ns
ns
ns
CAS hold time
RAS to CAS precharge time
Write to RAS precharge time
Write hold time referenced to RAS
10
10
10
10
CAS-before-RAS Counter Test Cycle
CAS precharge time (CAS-before-RAS
counter test cycle)
tCPT
35
–
40
–
ns
Semiconductor Group
9
1998-10-01
HYB 5118165BSJ/BST-50/-60
HYB 3118165BSJ/BST-50/-60
1M × 16 EDO-DRAM
Notes
1. All voltages are referenced to VSS.
2. ICC1, ICC3, ICC4 and ICC6 depend on cycle rate.
3. ICC1 and ICC4 depend on output loading. Specified values are obtained with the output open.
4. Address can be changed once or less while RAS = VIL. In case of ICC4 it can be changed once
or less during a hyper page mode (EDO) cycle
5. An initial pause of 200 µs is required after power-up followed by 8 RAS cycles of which at least
one cycle has to be a refresh cycle, before proper device operation is achieved. In case of using
the internal refresh counter, a minimum of 8 CAS-before-RAS initialization cycles instead of 8
RAS cycles are required.
6. AC measurements assume tT = 2 ns.
7. VIH (MIN.) and VIL (MAX.) are reference levels for measuring timing of input signals. Transition times
are also measured between VIH and VIL.
8. Measured with the specified current load and 100 pF at VOL = 0.8 V and VOH = 2.0 V. Access
time is determined by the latter of tRAC, tCAC, tAA, tCPA, tOEA. tCAC is measured from tristate.
9. Operation within the tRCD (MAX.) limit ensures that tRAC (MAX.) can be met. tRCD (MAX.) is specified as
a reference point only. If tRCD is greater than the specified tRCD (MAX.) limit, then access time is
controlled by tCAC
.
10.Operation within the tRAD (MAX.) limit ensures that tRAC (MAX.) can be met. tRAD (MAX.) is specified as
a reference point only. If tRAD is greater than the specified tRAD (MAX.) limit, then access time is
controlled by tAA.
11.Either tRCH or tRRH must be satisfied for a read cycle.
12.tOFF (MAX.), tOEZ (MAX.) define the time at which the output achieves the open-circuit conditions and
are not referenced to output voltage levels. tOFF is referenced from the rising edge of RAS or
CAS, whichever occurs last.
13.Either tDZC or tDZO must be satisfied.
14.Either tCDD or tODD must be satisfied.
15.tWCS, tRWD, tCWD and tAWD are not restrictive operating parameters. They are included in the data
sheet as electrical characteristics only. If tWCS > tWCS (MIN.), the cycle is an early write cycle and
data out pin will remain open-circuit (high impedance) through the entire cycle; if
t
RWD > tRWD (MIN.), tCWD > tCWD (MIN.) and tAWD > tAWD (MIN.), the cycle is a read-write cycle and I/O will
contain data read from the selected cells. If neither of the above sets of conditions is satisfied, the
condition of I/O (at access time) is indeterminate.
16.These parameters are referenced to the CAS leading edge in early write cycles and to the WE
leading edge in read-write cycles.
Semiconductor Group
10
1998-10-01
HYB 5118165BSJ/BST-50/-60
HYB 3118165BSJ/BST-50/-60
1M × 16 EDO-DRAM
t RC
t RAS
t RP
VIH
VIL
RAS
t CSH
t RCD
t RSH
t CRP
VIH
VIL
t CAS
UCAS
LCAS
t RAD
t ASC
t RAL
t CAH
t ASR
Row
t ASR
VIH
VIL
Address
Column
Row
t RAH
t RCH
t RCS
t RRH
VIH
VIL
WE
OE
t AA
t OEA
VIH
VIL
t DZC
t CDD
t DZO
t ODD
VIH
VIL
I/O
(Inputs)
t OFF
t CAC
t CLZ
t OEZ
VOH
VOL
Hi Z
Hi Z
I/O
(Outputs)
Valid Data OUT
t RAC
"H" or "L"
SPT03043
Read Cycle
Semiconductor Group
11
1998-10-01
HYB 5118165BSJ/BST-50/-60
HYB 3118165BSJ/BST-50/-60
1M × 16 EDO-DRAM
t RC
t RAS
t RP
VIH
VIL
RAS
t CSH
t RCD
t RSH
t CRP
VIH
VIL
t CAS
UCAS
LCAS
t RAD
t ASC
t RAL
t CAH
t ASR
Row
t RAH
t ASR
VIH
VIL
Address
Column
Row
t CWL
t WCS
VIH
VIL
t WP
WE
OE
t WCH
t RWL
VIH
VIL
t DH
t DS
VIH
VIL
I/O
(Inputs)
Valid Data IN
VOH
VOL
Hi Z
I/O
(Outputs)
"H" or "L"
SPT03044
Write Cycle (Early Write)
Semiconductor Group
12
1998-10-01
HYB 5118165BSJ/BST-50/-60
HYB 3118165BSJ/BST-50/-60
1M × 16 EDO-DRAM
t RC
t RAS
t RP
VIH
VIL
RAS
t CSH
t RCD
t RSH
t CRP
VIH
VIL
t CAS
UCAS
LCAS
t RAD
t ASC
t RAL
t CAH
t ASR
Row
t RAH
t ASR
VIH
VIL
Address
Column
Row
t CWL
t RWL
t WP
VIH
VIL
WE
OE
t OEH
VIH
VIL
t ODD
t DZO
t DZC
t DH
tDS
VIH
VIL
I/O
(Inputs)
Valid Data
tOEZ
t CLZ
t OEA
VOH
VOL
Hi Z
Hi Z
I/O
(Outputs)
"H" or "L"
SPT03045
Write Cycle (OE Controlled Write)
Semiconductor Group
13
1998-10-01
HYB 5118165BSJ/BST-50/-60
HYB 3118165BSJ/BST-50/-60
1M × 16 EDO-DRAM
t RWC
t RAS
VIH
VIL
RAS
t CSH
t RP
t RSH
t RCD
t CAS
t CRP
VIH
VIL
UCAS
LCAS
t RAH
t CAH
t ASR
Row
t ASC
tASR
VIH
VIL
Address
Column
Row
t RAD
t CWL
t AWD
t CWD
t RWL
t WP
t RWD
VIH
VIL
WE
OE
t AA
t RCS
t OEA
t OEH
VIH
VIL
t DZC
t DS
t DH
tDZO
VIH
VIL
I/O
(Inputs)
Valid
Data IN
t ODD
t OEZ
t CAC
t CLZ
VOH
VOL
I/O
(Outputs)
Data
OUT
t RAC
"H" or "L"
SPT03046
Read-Write (Read-Modify-Write) Cycle
Semiconductor Group
14
1998-10-01
HYB 5118165BSJ/BST-50/-60
HYB 3118165BSJ/BST-50/-60
1M × 16 EDO-DRAM
tRAS
tRCD
tRHCP
VIH
VIL
RAS
tHPC
tRP
tCP
tRSH
tCRP
tCAS
tCAS
tCAS
tCRP
VIH
VIL
UCAS
LCAS
tCSH
tRAL
tCAH
tCAH
tRAH
tCAH
tASR
tASC
tASC
tASC
VIH
VIL
Address
WE
Row
tRAD
Column 1
Column 2
Column N
tRRH
tRCH
tRCS
VIH
VIL
tCAC
tAA
tCPA
tCAC
tAA
tCPA
tOES
tOEA
tOFF
VIH
VIL
OE
tRAC
tAA
tCAC
tCLZ
tCOH
tCOH
Data OUT 2
tOEZ
Data OUT N
VOH
VOL
I/O
(Output)
Data OUT 1
"H" or "L"
SPT03056
Hyper Page Mode (EDO) Read Cycle
Semiconductor Group
15
1998-10-01
HYB 5118165BSJ/BST-50/-60
HYB 3118165BSJ/BST-50/-60
1M × 16 EDO-DRAM
tRAS
tRCD
tRHCP
VIH
VIL
RAS
tHPC
tRP
tCP
t RSH
tCRP
tCAS
tCAS
tCAS
tCRP
VIH
VIL
UCAS
LCAS
tCSH
tRAL
tCAH
tRAH
tCAH
tCAH
tASR
tASC
tASC
tASC
VIH
VIL
Row
Address
Column 1
tCWL
Column 2
tCWL
Column N
Address
tRAD
tWCS
tRWL
tCWL
t WCS
t WCS
t WCH
t WP
t WCH
t WP
t WCH
t WP
VIH
VIL
WE
OE
VIH
VIL
tDH
tDH
tDH
tDS
tDS
tDS
VIH
VIL
I/O
(Input)
Data IN 1
Data IN 2
Data IN N
"H" or "L"
SPT03057
Hyper Page Mode (EDO) Early Write Cycle
Semiconductor Group
16
1998-10-01
HYB 5118165BSJ/BST-50/-60
HYB 3118165BSJ/BST-50/-60
1M × 16 EDO-DRAM
tRAS
VIH
VIL
RAS
tCSH
tRP
t CP
tPRWC
tRSH
tRCD
tCAS
tCAS
tCAS
tCRP
VIH
VIL
UCAS
LCAS
tRAD
tRAH
tRAL
tCAH
tCAH
tCAH
tASR
tASC
tASC
tASC
Column
tASR
Row
VIH
VIL
Address
Row
Column
tRWD
Column
tCPWD
tCWD
tCPWD
tCWD
tRWL
tCWL
tCWD
tCWL
tCWL
tOEH
tODD
tRCS
VIH
VIL
WE
tAWD
tAWD
tOEA
t AWD
tOEA
tAA
tWP
tWP
t WP
tOEA
tOEH
tOEH
VIH
VIL
OE
tCLZ
tCLZ
tCLZ
tDZC
tODD
tCPA
tCPA
tDZC
tODD
tDZC
tDZO
VIH
VIL
I/O
(Inputs)
Data IN
Data IN
Data IN
tDH
tDH
tDH
tCAC
tCAC
tAA
tDS
tOEZ
tDS
tRAC
tAA
tDS
tOEZ
tOEZ
VOH
VOL
I/O
(Outputs)
Data
OUT
Data
OUT
Data
OUT
"H" or "L"
SPT03049
Hyper Page Mode (EDO) Late Write and Read-Modify-Write Cycle
Semiconductor Group
17
1998-10-01
HYB 5118165BSJ/BST-50/-60
HYB 3118165BSJ/BST-50/-60
1M × 16 EDO-DRAM
tRC
tRAS
tRP
VIH
VIL
RAS
tCRP
tRPC
VIH
VIL
UCAS
LCAS
tRAH
tASR
tASR
VIH
VIL
Address
Row
Row
VOH
VOL
Hi Z
I/O
(Outputs)
"H" or "L"
SPT03050
RAS-only Refresh Cycle
Semiconductor Group
18
1998-10-01
HYB 5118165BSJ/BST-50/-60
HYB 3118165BSJ/BST-50/-60
1M × 16 EDO-DRAM
tRC
tRP
tRAS
tRP
VIH
VIL
RAS
tRPC
tCP
tCHR
tRPC
tCRP
tCSR
VIH
VIL
UCAS
LCAS
tWRH
tWRP
VIH
VIL
WE
OE
VIH
VIL
tODD
VIH
VIL
I/O
(Inputs)
tCDD
tOEZ
VOH
VOL
Hi Z
I/O
(Outputs)
tOFF
"H" or "L"
SPT03051
CAS-before-RAS Refresh Cycle
Semiconductor Group
19
1998-10-01
HYB 5118165BSJ/BST-50/-60
HYB 3118165BSJ/BST-50/-60
1M × 16 EDO-DRAM
tRC
tRC
tRP
tRP
tRAS
tRAS
VIH
VIL
RAS
tRCD
tRSH
tCHR
tCRP
VIH
VIL
UCAS
LCAS
tRAD
tASC
tRAH
tWRP
tASR
t WRH
tASR
tCAH
Column
VIH
VIL
Address
WE
Row
Row
tRCS
tRRH
VIH
VIL
tAA
tOEA
VIH
VIL
OE
tDZC
tCDD
tODD
tDZO
VIH
VIL
I/O
(Inputs)
tCAC
tCLZ
tRAC
tOFF
tOEZ
VOH
VOL
Hi Z
I/O
(Outputs)
Valid Data OUT
"H" or "L"
SPT03053
Hidden Refresh Cycle (Read)
Semiconductor Group
20
1998-10-01
HYB 5118165BSJ/BST-50/-60
HYB 3118165BSJ/BST-50/-60
1M × 16 EDO-DRAM
tRC
tRC
tRAS
tRP
tRAS
tRP
VIH
VIL
RAS
tRCD
tRSH
tCHR
tCRP
VIH
VIL
UCAS
LCAS
tRAD
tASC
tRAH
t ASR
t ASR
tCAH
Column
VIH
VIL
Address
Row
Row
tWCS
t WCH
t WP
t WRH
t WRP
VIH
VIL
WE
tDS
tDH
Valid Data
VIN
VIL
I/O
(Input)
VOH
VOL
Hi Z
I/O
(Output)
"H" or "L"
SPT03054
Hidden Refresh Cycle (Early Write)
Semiconductor Group
21
1998-10-01
HYB 5118165BSJ/BST-50/-60
HYB 3118165BSJ/BST-50/-60
1M × 16 EDO-DRAM
Read Cycle
tRAS
tRP
VIH
RAS
VIL
tCHR
tRSH
tCSR
tCP
VIH
tCAS
UCAS
LCAS
VIL
tRAL
tCAH
tASR
tASC
VIH
VIL
Address
WE
Column
tAA
Row
tWRP
tRRH
VIH
VIL
tCAC
tWRH
tRCS
tRCH
tOEA
VIH
VIL
OE
tCDD
tDZC
VIH
VIL
tODD
tOFF
tOEZ
I/O
(Inputs)
t DZO
tCLZ
VOH
VOL
I/O
(Outputs)
Data OUT
tWCS
tRWL
tCWL
tWCH
tWRP
Write Cycle
VIH
WE
VIL
tWRH
tDH
VIH
OE
VIL
tDS
VIH
I/O
Data IN
Hi Z
(Inputs)
VIL
VOH
I/O
(Outputs)
VOL
"H" or "L"
SPT03055
CAS-before-RAS Refresh Counter Test Cycle
Semiconductor Group
22
1998-10-01
HYB 5118165BSJ/BST-50/-60
HYB 3118165BSJ/BST-50/-60
1M × 16 EDO-DRAM
Package Outlines
Plastic Package P-SOJ-42-1 (SMD) (400mil)
(Plastic small outline J-leaded)
Sorts of Packing
Package outlines for tubes, trays etc. are contained in our
Data Book “Package Information”.
Dimensions in mm
1998-10-01
SMD = Surface Mounted Device
Semiconductor Group
23
HYB 5118165BSJ/BST-50/-60
HYB 3118165BSJ/BST-50/-60
1M × 16 EDO-DRAM
Plastic Package P-TSOPII-50/44-1 (400 mil) (SMD)
(Plastic Thin Small Outline Package (Type II))
15˚±5˚
2)
10.16±0.13
0.8
0.5±0.1
11.76±0.2
15˚±5˚
0.1 50x
24x 0.8 = 19.2
M
0.2
50x
3)
+0.05
-0.1
0.4
50
40 36
26
25
1
11 15
2.5 max
1)
20.95±0.13
GPX05958
Index Marking
1) Does not include plastic or metal protrusion of 0.15 max per side
2) Does not include plastic protrusion of 0.25 max per side
3) Does not include dambar protrusion of 0.13 max per side
Sorts of Packing
Package outlines for tubes, trays etc. are contained in our
Data Book “Package Information”.
Dimensions in mm
1998-10-01
SMD = Surface Mounted Device
Semiconductor Group
24
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