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HYB39S256800DFL-6 [INFINEON]

Synchronous DRAM, 32MX8, 5ns, CMOS, PBGA54, 12 X 8 MM, PLASTIC, TFBGA-54;
HYB39S256800DFL-6
型号： HYB39S256800DFL-6
厂家： Infineon    Infineon
描述：

Synchronous DRAM, 32MX8, 5ns, CMOS, PBGA54, 12 X 8 MM, PLASTIC, TFBGA-54

动态存储器
文件： 总61页 (文件大小：2394K)
中文：  中文翻译
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Data Sheet, Rev. 1.30, Feb. 2006  
HYB39S256400D[C/T](L)  
HYB39S256800D[C/T](L)  
HYB39S256160D[C/T](L)  
256-MBit Synchronous DRAM  
SDRAM  
Memory Products  
Edition 2006-02  
Published by Infineon Technologies AG,  
St.-Martin-Strasse 53,  
81669 München, Germany  
© Infineon Technologies AG 2006.  
All Rights Reserved.  
Attention please!  
The information herein is given to describe certain components and shall not be considered as a guarantee of  
characteristics.  
Terms of delivery and rights to technical change reserved.  
We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding  
circuits, descriptions and charts stated herein.  
Information  
For further information on technology, delivery terms and conditions and prices please contact your nearest  
Infineon Technologies Office (www.infineon.com).  
Warnings  
Due to technical requirements components may contain dangerous substances. For information on the types in  
question please contact your nearest Infineon Technologies Office.  
Infineon Technologies Components may only be used in life-support devices or systems with the express written  
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure  
of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support  
devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain  
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may  
be endangered.  
HYB39S256400D[C/T](L) HYB39S256800D[C/T](L) HYB39S256160D[C/T](L)  
Revision History: 2006-02, Rev. 1.30  
Previous Version: 2005-07, Rev. 1.22  
Page  
7
Subjects (major changes since last revision)  
Changed format in table 1  
28  
Changed format in table 12  
29  
Corrected −7.5 = PC133−333  
We Listen to Your Comments  
Any information within this document that you feel is wrong, unclear or missing at all?  
Your feedback will help us to continuously improve the quality of this document.  
Please send us your proposal (including a reference to this document) to:  
techdoc.mp@infineon.com  
Template: mp_a4_s_rev321 / 3 / 2005-10-05  
HYB39S256[40/80/16]0D[C/T](L)  
256-MBit Synchronous DRAM  
Table of Contents  
Table of Contents  
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4  
List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5  
List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6  
1
1.1  
1.2  
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7  
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7  
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7  
2
Pin Configuration and Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9  
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9  
Package P–TSOPII–54 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13  
Package P–TFBGA–54 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14  
Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16  
2.1  
2.2  
2.3  
2.4  
3
3.1  
3.2  
3.3  
3.3.1  
3.4  
3.5  
3.5.1  
3.5.2  
3.5.3  
3.5.4  
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19  
Operation Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19  
Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20  
Mode Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21  
Burst Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22  
Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23  
Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24  
Read and Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24  
DQM Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25  
Suspend Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25  
Power Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25  
4
4.1  
4.2  
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26  
Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26  
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29  
5
6
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31  
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59  
Data Sheet  
4
Rev. 1.30, 2006-02  
10072003-13LE-FGQQ  
HYB39S256[40/80/16]0D[C/T](L)  
256-MBit Synchronous DRAM  
List of Tables  
List of Tables  
Table 1  
Table 2  
Table 3  
Table 4  
Table 5  
Table 6  
Table 7  
Table 8  
Table 9  
Table 10  
Table 11  
Table 12  
Table 13  
Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7  
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8  
Pin Configuration of the SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9  
Truth Table: Operation Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19  
Mode Register Definition (BA[1:0] = 00B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21  
Burst Length and Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22  
Bank Selection by Address Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23  
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26  
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26  
Input and Output Capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27  
I
I
DD Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27  
DD Specifications and Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28  
AC Timing - Absolute Specifications –8/-7.5/–7/-6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29  
Data Sheet  
5
Rev. 1.30, 2006-02  
10072003-13LE-FGQQ  
HYB39S256[40/80/16]0D[C/T](L)  
256-MBit Synchronous DRAM  
List of Figures  
List of Figures  
Figure 1  
Figure 2  
Figure 3  
Figure 4  
Figure 5  
Figure 6  
Figure 7  
Figure 8  
Figure 9  
Pin Configuration P-TSOPII-54 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13  
Ball out for ×16 components, PG-TFBGA-54 (top view). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14  
Ball out for ×8 components, PG-TFBGA-54 (top view). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15  
Ball out for ×4 components, PG-TFBGA-54 (top view). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15  
Block Diagram for 64M x 4 SDRAM (13/11/2 Addressing). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16  
Block Diagram for 32M x 8 SDRAM (13/10/2 Addressing). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17  
Block Diagram for 16M x 16 SDRAM (13/9/2 Addressing). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18  
Measurement conditions for tAC and tOH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30  
Bank Activate Command Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31  
Figure 10 Burst Read Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31  
Figure 11 Read Interrupted by a Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32  
Figure 12 Read to Write Interval. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32  
Figure 13 Minimum Read to Write Interval . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33  
Figure 14 Non-Minimum Read to Write Interval . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33  
Figure 15 Burst Write Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34  
Figure 16 Write Interrupted by a Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34  
Figure 17 Write Interrupted by a Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35  
Figure 18 Burst Write with Auto-Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35  
Figure 19 Burst Read with Auto-Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36  
Figure 20  
AC Parameters for a Write Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37  
Figure 21 AC Parameters for a Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38  
Figure 22 Mode Register Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39  
Figure 23 Power on Sequence and Auto Refresh (CBR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40  
Figure 24 Clock Suspension During Burst Read CAS Latency = 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41  
Figure 25 Clock Suspension During Burst Read CAS Latency = 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42  
Figure 26 Clock Suspension During Burst Write CAS Latency = 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43  
Figure 27 Clock Suspension During Burst Write CAS Latency = 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44  
Figure 28 Power Down Mode and Clock Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45  
Figure 29 Self Refresh (Entry and Exit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46  
Figure 30 Auto Refresh (CBR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47  
Figure 31 CAS Latency = 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48  
Figure 32 CAS Latency = 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49  
Figure 33 CAS Latency = 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50  
Figure 34 CAS Latency = 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51  
Figure 35 CAS Latency = 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52  
Figure 36 CAS Latency = 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53  
Figure 37 CAS Latency = 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54  
Figure 38 CAS Latency = 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55  
Figure 39 CAS Latency = 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56  
Figure 40 Full Page Burst Read, CAS Latency = 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57  
Figure 41 Full Page Burst Write, CAS Latency = 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58  
Figure 42 Package Outline P-TSOPII-54-1 (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59  
Figure 43 Package Outline P-TFBGA-54-8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60  
Data Sheet  
6
Rev. 1.30, 2006-02  
10072003-13LE-FGQQ  
256-MBit Synchronous DRAM  
SDRAM  
HYB39S256400D[C/T](L)  
HYB39S256800D[C/T](L)  
HYB39S256160D[C/T](L)  
1
Overview  
This chapter lists all main features of the product family HYB39S256[40/80/16]0D[C/T](L) and the ordering  
information.  
1.1  
Features  
•
•
•
•
•
Fully Synchronous to Positive Clock Edge  
0 to 70 °C Operating Temperature  
Four Banks controlled by BA0 & BA1  
Programmable CAS Latency: 2 & 3  
Programmable Wrap Sequence: Sequential or  
Interleave  
Programmable Burst Length: 1, 2, 4, 8 and full page  
Multiple Burst Read with Single Write Operation  
Automatic and Controlled Precharge Command  
Data Mask for Read / Write control (x4, x8)  
•
•
•
•
•
•
•
•
Data Mask for Byte Control (x16)  
Auto Refresh (CBR) and Self Refresh  
Power Down and Clock Suspend Mode  
8192 refresh cycles / 64 ms (7.8 µs)  
Random Column Address every CLK (1-N Rule)  
Single 3.3 V ± 0.3 V Power Supply  
LVTTL Interface  
Plastic Packages:  
– P–TSOPII–54 400mil width  
– P–TFBGA–54 (12 mm x 8 mm)  
•
•
•
•
Table 1  
Performance  
Poduct Type Speed Code  
Speed Grade  
–6  
–7  
–7.5  
–8  
Unit  
—
Note  
PC166–333 PC133–222 PC133–333 PC100–222  
Max. Clock Frequency  
fCK3 166  
fCK2 133  
143  
133  
7
133  
100  
7.5  
10  
125  
100  
8
MHz  
MHz  
ns  
CL3  
CL2  
CL3  
CL2  
CL3  
CL2  
Min. Clock Cycle Time  
tCK3  
tCK2 7.5  
Max. Access Time from Clock tAC3  
tAC2 5.4  
6
7.5  
5.4  
5.4  
10  
6
ns  
5
5.4  
6
ns  
6
ns  
1.2  
Description  
The HYB39S256[40/80/16]0D[C/T](L) are four bank Synchronous DRAM’s organized as 4 banks x 16 MBit x4,  
4 banks x 8 MBit x8 and 4 banks x 4 Mbit x16 respectively. These synchronous devices achieve high speed data  
transfer rates for CAS latencies by employing a chip architecture that prefetches multiple bits and then  
synchronizes the output data to a system clock. The chip is fabricated with INFINEON’s advanced 0.14 µm  
256-MBit DRAM process technology.  
The device is designed to comply with all industry standards set for synchronous DRAM products, both electrically  
and mechanically. All of the control, address, data input and output circuits are synchronized with the positive edge  
of an externally supplied clock.  
Operating the four memory banks in an interleave fashion allows random access operation to occur at a higher  
rate than is possible with standard DRAMs. A sequential and gapless data rate is possible depending on burst  
length, CAS latency and speed grade of the device.  
Auto Refresh (CBR) and Self Refresh operation are supported. These devices operate with a single 3.3 V ± 0.3 V  
power supply. All 256-Mbit components are available in P–TSOPII–54 and P–TFBGA–54 packages.  
Data Sheet  
7
Rev. 1.30, 2006-02  
10072003-13LE-FGQQ  
HYB39S256[40/80/16]0D[C/T](L)  
256-MBit Synchronous DRAM  
Overview  
Table 2  
Ordering Information  
Product Type  
Speed Grade  
Package  
Description  
HYB 39S256400DT–6  
HYB 39S256400DT–7  
HYB 39S256400DT–7.5  
HYB 39S256400DT–8  
HYB 39S256800DT–6  
HYB 39S256800DT–7  
HYB 39S256800DT–7.5  
HYB 39S256800DT–8  
HYB 39S256160DT–6  
HYB 39S256160DT–7  
HYB 39S256160DT–7.5  
HYB 39S256160DT–8  
HYB39S256400DTL–x  
PC166–333–520  
PC133–222–520  
PC133–333–520  
PC100–222–620  
PC166–333–520  
PC133–222–520  
PC133–333–520  
PC100–222–620  
PC166–333–520  
PC133–222–520  
PC133–333–520  
PC100–222–620  
—
P–TSOP–54–1 (400mil) 166MHz 4B x 16M x 4 SDRAM  
P–TSOP–54–1 (400mil) 143MHz 4B x 16M x 4 SDRAM  
P–TSOP–54–1 (400mil) 133MHz 4B x 16M x 4 SDRAM  
P–TSOP–54–1 (400mil) 125MHz 4B x 16M x 4 SDRAM  
P–TSOP–54–1 (400mil) 166MHz 4B x 8M x 8 SDRAM  
P–TSOP–54–1 (400mil) 143MHz 4B x 8M x 8 SDRAM  
P–TSOP–54–1 (400mil) 133MHz 4B x 8M x 8 SDRAM  
P–TSOP–54–1 (400mil) 125MHz 4B x 8M x 8 SDRAM  
P–TSOP–54–1 (400mil) 166MHz 4B x 4M x 16 SDRAM  
P–TSOP–54–1 (400mil) 143MHz 4B x 4M x 16 SDRAM  
P–TSOP–54–1 (400mil) 133MHz 4B x 4M x 16 SDRAM  
P–TSOP–54–1 (400mil) 125MHz 4B x 4M x 16 SDRAM  
P–TSOP–54–1 (400mil) 4B x 16M x 4 SDRAM Low Power  
Versions (on request)  
HYB39S256800DTL–x  
HYB39S256160DTL–x  
HYB39S256xx0DC(L)–x  
—
—
—
P–TSOP–54–1 (400mil) 4B x 8M x 8 SDRAM Low Power  
Versions (on request)  
P–TSOP–54–1 (400mil) 4B x 4M x 16 SDRAM Low Power  
Versions (on request)  
P–TFBGA–54-8  
(on request)  
Data Sheet  
8
Rev. 1.30, 2006-02  
10072003-13LE-FGQQ  
HYB39S256[40/80/16]0D[C/T](L)  
256-MBit Synchronous DRAM  
Pin Configuration and Block Diagrams  
2
Pin Configuration and Block Diagrams  
This chapter contains the pin configuration table, the TSOP and FBGA package drawing, and the block diagrams  
for the ×4, ×8, ×16 organization of the SDRAM.  
2.1  
Pin Description  
Listed below are the pin configurations sections for the various signals of the SDRAM  
•
•
•
•
•
•
•
•
•
•
•
•
Clock Signals ×4/×8/×16 Organization  
Control Signals ×4/×8/×16 Organization  
Address Signals ×4/×8/×16 Organization  
Data Signals ×4 Organization  
Data Signals ×8 Organization  
Data Signals ×16 Organization  
Data Mask ×4/×8 Organization  
Data Mask ×16 Organization  
Power Supplies ×4/×8/×16 Organization  
Not connected ×4 Organization  
Not connected ×8 Organization  
Not connected ×16 Organization  
Table 3  
Pin Configuration of the SDRAM  
Name Pin Buffer Function  
Type Type  
Pin or  
Ball No.  
Clock Signals ×4/×8/×16 Organization  
38,2F  
37,3F  
CLK  
I
LVTTL  
Clock Signal CK  
Note: The system clock input. All of the SDRAM inputs are sampled on the  
rising edge of the clock.  
CKE  
I
LVTTL  
Clock Enable  
Note: Activates the CLK signal when high and deactivates the CLK signal  
when low, thereby initiating either the Power Down mode, Suspend  
mode, or the Self Refresh mode.  
Control Signals ×4/×8/×16 Organization  
18, 8F  
17, 7F  
16, 9F  
RAS  
CAS  
WE  
I
I
I
LVTTL  
LVTTL  
LVTTL  
Row Address Strobe (RAS), Column Address Strobe (CAS), Write  
Enable (WE)  
Note: When sampled at the positive rising edge of the clock, CAS, RAS, and  
WE define the command to be executed by the SDRAM.  
19, 9G  
CS  
I
LVTTL  
Chip Select  
Note: Enables the command decoder when low and disables the command  
decoder when high. When the command decoder is disabled, new  
commands are ignored but previous operations continue.  
Address Signals ×4/×8/×16 Organization  
20, 7G  
21, 8G  
BA0  
BA1  
I
I
LVTTL  
LVTTL  
Bank Address Signals 1:0  
Note: Bank Select Inputs. Bank address inputs selects which of the four  
banks a command applies to.  
Data Sheet  
9
Rev. 1.30, 2006-02  
10072003-13LE-FGQQ  
HYB39S256[40/80/16]0D[C/T](L)  
256-MBit Synchronous DRAM  
Pin Configuration and Block Diagrams  
Table 3  
Pin Configuration of the SDRAM (cont’d)  
Name Pin Buffer Function  
Type Type  
Pin or  
Ball No.  
23, 7H  
24,8H  
25, 8J  
26, 7J  
29, 3J  
30, 2J  
31, H  
A0  
I
I
I
I
I
I
I
I
I
I
I
I
I
LVTTL  
LVTTL  
LVTTL  
LVTTL  
LVTTL  
LVTTL  
LVTTL  
LVTTL  
LVTTL  
LVTTL  
LVTTL  
LVTTL  
LVTTL  
Address Signal 9:0, Address Signal 10/Auto precharge  
A1  
Note: During a Bank Activate command cycle, A0-A12 define the row  
address (RA0-RA12) when sampled at the rising clock edge. During a  
Read or Write command cycle, A0-An define the column address  
(CA0-CAn) when sampled at the rising clock edge. CAn depends  
upon the SDRAM organization:  
A2  
A3  
A4  
A5  
64M x4SDRAM CAn = CA9, CA11 (Page Length = 2048 bits)  
32M x8SDRAM CAn = CA9 (Page Length = 1024 bits)  
16M x16SDRAM CAn = CA8 (Page Length = 512 bits)  
A6  
32, 2H  
33, 1H  
34, 3G  
22, 9H  
35,2G  
36, 1G  
A7  
In addition to the column address, A10 (= AP) is used to invoke the  
auto pre charge operation at the end of the burst read or write cycle.  
If A10 is high, auto pre charge is selected and BA0, BA1 defines the  
bank to be precharged. If A10 is low, auto pre charge is  
disabled.During a Precharge command cycle, A10 (= AP) is used in  
conjunction with BA0 and BA1 to control which bank(s) to precharge.  
If A10 is high, all four banks will be precharged regardless of the state  
of BA0 and BA1. If A10 is low, then BA0 and BA1 are used to define  
which bank to precharge.  
A8  
A9  
A10  
A11  
A12  
Data Signals ×4 Organization  
5, 8B  
DQ0  
DQ1  
DQ2  
DQ3  
I/O  
I/O  
I/O  
I/O  
LVTTL  
LVTTL  
LVTTL  
LVTTL  
Data Signal Bus [15:0]  
11, 8D  
44, 2D  
50, 2B  
Note: Data Input/Output pins operate in the same manner as on EDO or  
FPM DRAMs.  
Data Signals ×8 Organization  
2, 8A  
DQ0  
DQ1  
DQ2  
DQ3  
DQ4  
DQ5  
DQ6  
DQ7  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
LVTTL  
LVTTL  
LVTTL  
LVTTL  
LVTTL  
LVTTL  
LVTTL  
LVTTL  
Data Signal Bus [15:0]  
5, 8B  
Note: Data Input/Output pins operate in the same manner as on EDO or  
FPM DRAMs.  
8, 8C  
11, 8D  
44, 2D  
47, 2C  
50, 2B  
53, 2A  
Data Sheet  
10  
Rev. 1.30, 2006-02  
10072003-13LE-FGQQ  
HYB39S256[40/80/16]0D[C/T](L)  
256-MBit Synchronous DRAM  
Pin Configuration and Block Diagrams  
Table 3  
Pin Configuration of the SDRAM (cont’d)  
Pin or  
Name Pin  
Buffer  
Function  
Ball No.  
Type Type  
Data Signals ×16 Organization  
2, 9A  
DQ0  
DQ1  
DQ2  
DQ3  
DQ4  
DQ5  
DQ6  
DQ7  
DQ8  
DQ9  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
LVTTL  
LVTTL  
LVTTL  
LVTTL  
LVTTL  
LVTTL  
LVTTL  
LVTTL  
LVTTL  
LVTTL  
LVTTL  
LVTTL  
LVTTL  
LVTTL  
LVTTL  
LVTTL  
Data Signal Bus [15:0]  
4, 9B  
Note: Data Input/Output pins operate in the same manner as on EDO or  
FPM DRAMs.  
5, 8B  
7, 9C  
8, 8C  
10, 9D  
11, 8D  
13, 9E  
42, 1E  
44, 2D  
45, 1D  
47, 2C  
48, 1C  
50, 2B  
51, 1B  
53, 2A  
DQ10 I/O  
DQ11 I/O  
DQ12 I/O  
DQ13 I/O  
DQ14 I/O  
DQ15 I/O  
Data Mask ×4/×8 Organization  
39, 1F DQM I/O LVTTL  
Data Mask  
Note: The Data Input/Output mask places the DQ buffers in a high  
impedance state when sampled high. In Read mode, DQM has a  
latency of two clock cycles and controls the output buffers like an  
output enable. In Write mode, DQM has a latency of zero and  
operates as a word mask by allowing input data to be written if it is low  
but blocks the write operation if DQM is high.One DQM input is  
present in x4 and x8 SDRAMs.  
Data Mask ×16 Organization  
39, 1F  
UDQM I/O  
LVTTL  
Data Mask Upper Byte  
Note: LDQM and UDQM controls the lower and upper bytes in x16  
SDRAMs.  
15, 8E  
LDQM I/O  
LVTTL  
Data Mask Lower Byte  
Power Supplies ×4/×8/×16 Organization  
3B, 3D, VDDQ PWR –  
Power Supply  
7A, 7C  
7E, 9A, VDD  
9J  
PWR –  
PWR –  
Power Supply  
Note: Power for the input buffers and the core logic (3.3 V)  
Power Supply Ground for DQs  
3A, 3C, VSSQ  
7B, 7D  
Note: Isolated power supply and ground for the output buffers to provide  
improved noise immunity.  
1J, 1A, VSS  
PWR –  
Power Supply Ground  
3E  
Data Sheet  
11  
Rev. 1.30, 2006-02  
10072003-13LE-FGQQ  
HYB39S256[40/80/16]0D[C/T](L)  
256-MBit Synchronous DRAM  
Pin Configuration and Block Diagrams  
Table 3  
Pin Configuration of the SDRAM (cont’d)  
Pin or  
Name Pin  
Buffer  
Function  
Ball No.  
Type Type  
Not connected ×4 Organization  
2, 4, 7, 8, NC  
10, 13,  
15, 40,  
NC  
–
Not connected  
Note: No internal electrical connection is present.  
42, 45,  
47, 48,  
51, 53,  
1B, 1C,  
1D, 1E,  
2A, 2C,  
2E, 8A,  
8C, 8E,  
9B, 9C,  
9D, 9E  
Not connected ×8 Organization  
7, 10,  
NC  
NC  
–
Not connected  
13, 15,  
40, 42,  
45, 48,  
51, 1B,  
1C, 1D,  
1E, 2E,  
8E, 9B,  
9C, 9D,  
9E  
Note: No internal electrical connection is present.  
Not connected ×16 Organization  
40, 2E NC NC  
–
Not connected  
Note: No internal electrical connection is present.  
Data Sheet  
12  
Rev. 1.30, 2006-02  
10072003-13LE-FGQQ  
HYB39S256[40/80/16]0D[C/T](L)  
256-MBit Synchronous DRAM  
Pin Configuration and Block Diagrams  
2.2  
Package P–TSOPII–54  
Listed below are the pin outs of the TSOP package.  
X ꢂꢆ  
X ꢈ  
X ꢁ  
6$$  
$1ꢀ  
6$$1  
$1ꢂ  
$1ꢃ  
6331  
$1ꢄ  
$1ꢁ  
6$$1  
$1ꢅ  
$1ꢆ  
6331  
$1ꢇ  
6$$  
6$$  
$1ꢀ  
6$$1  
.ꢌ#ꢌ  
$1ꢂ  
6331  
.ꢌ#ꢌ  
$1ꢃ  
6$$1  
.ꢌ#ꢌ  
$1ꢄ  
6331  
.ꢌ#ꢌ  
6$$  
6$$  
.ꢌ#ꢌ  
6$$1  
.ꢌ#ꢌ  
$1ꢀ  
6331  
.ꢌ#ꢌ  
.ꢌ#ꢌ  
6$$1  
.ꢌ#ꢌ  
$1ꢂ  
6331  
.ꢌ#ꢌ  
6$$  
ꢂ
ꢅꢁ  
ꢅꢄ  
ꢅꢃ  
ꢅꢂ  
ꢅꢀ  
ꢁꢉ  
ꢁꢈ  
ꢁꢇ  
ꢁꢆ  
ꢁꢅ  
ꢁꢁ  
ꢁꢄ  
ꢁꢃ  
ꢁꢂ  
ꢁꢀ  
ꢄꢉ  
ꢄꢈ  
ꢄꢇ  
ꢄꢆ  
ꢄꢅ  
ꢄꢁ  
ꢄꢄ  
ꢄꢃ  
ꢄꢂ  
ꢄꢀ  
ꢃꢉ  
ꢃꢈ  
633  
633  
633  
ꢃ
.ꢌ#ꢌ  
6331  
.ꢌ#ꢌ  
$1ꢄ  
6$$1  
.ꢌ#ꢌ  
.ꢌ#ꢌ  
6331  
.ꢌ#ꢌ  
$1ꢃ  
6$$1  
.ꢌ#ꢌ  
633  
$1ꢇ  
6331  
.ꢌ#ꢌ  
$1ꢆ  
6$$1  
.ꢌ#ꢌ  
$1ꢅ  
6331  
.ꢌ#ꢌ  
$1ꢁ  
6$$1  
.ꢌ#ꢌ  
633  
$1ꢂꢅ  
6331  
ꢄ
ꢁ
$1ꢂꢁ  
$1ꢂꢄ  
6$$1  
$1ꢂꢃ  
$1ꢂꢂ  
6331  
ꢅ
ꢆ
ꢇ
ꢈ
ꢉ
ꢂꢀ  
ꢂꢂ  
ꢂꢃ  
ꢂꢄ  
ꢂꢁ  
ꢂꢅ  
ꢂꢆ  
ꢂꢇ  
ꢂꢈ  
ꢂꢉ  
ꢃꢀ  
ꢃꢂ  
ꢃꢃ  
ꢃꢄ  
ꢃꢁ  
ꢃꢅ  
ꢃꢆ  
ꢃꢇ  
$1ꢂꢀ  
$1ꢉ  
6$$1  
$1ꢈ  
633  
,$1-  
7%  
.ꢌ#ꢌ  
7%  
.ꢌ#ꢌ  
7%  
.ꢌ#ꢌꢊ!ꢂꢄ .ꢌ#ꢌꢊ!ꢂꢄ .ꢌ#ꢌꢊ!ꢂꢄ  
$1-  
#+  
$1-  
#+  
5$1-  
#+  
#!3  
2!3  
#3ꢀ  
"!ꢀ  
#!3  
2!3  
#3ꢀ  
"!ꢀ  
#!3  
2!3  
#3ꢀ  
"!ꢀ  
#+%  
#+%  
#+%  
.ꢌ#ꢌꢊ!ꢂꢃ .ꢌ#ꢌꢊ!ꢂꢃ .ꢌ#ꢌꢊ!ꢂꢃ  
!ꢂꢂ  
!ꢉ  
!ꢈ  
!ꢇ  
!ꢆ  
!ꢂꢂ  
!ꢉ  
!ꢈ  
!ꢇ  
!ꢆ  
!ꢂꢂ  
!ꢉ  
!ꢈ  
!ꢇ  
!ꢆ  
!ꢂꢃꢊ"!ꢂ !ꢂꢃꢊ"!ꢂ !ꢂꢃꢊ"!ꢂ  
!ꢂꢀꢋ!0 !ꢂꢀꢋ!0 !ꢂꢀꢋ!0  
!ꢀ  
!ꢂ  
!ꢀ  
!ꢂ  
!ꢀ  
!ꢂ  
!ꢃ  
!ꢃ  
!ꢃ  
!ꢅ  
!ꢁ  
633  
!ꢅ  
!ꢁ  
633  
!ꢅ  
!ꢁ  
633  
!ꢄ  
!ꢄ  
!ꢄ  
6$$  
6$$  
6$$  
-003ꢀꢀꢁꢀ  
Figure 1  
Pin Configuration P-TSOPII-54  
Data Sheet  
13  
Rev. 1.30, 2006-02  
10072003-13LE-FGQQ  
HYB39S256[40/80/16]0D[C/T](L)  
256-MBit Synchronous DRAM  
Pin Configuration and Block Diagrams  
2.3  
Package P–TFBGA–54  
Listed below are the ball outs of the TFBGA package.  
•
•
•
Ball out for ×16 components, PG-TFBGA-54 (top view)  
Ball out for ×8 components, PG-TFBGA-54 (top view)  
Ball out for ×4 components, PG-TFBGA-54 (top view)  
ꢂ
ꢃ
ꢄ
ꢁ
ꢅ
!
"
#
$
%
&
'
(
*
ꢆ
ꢇ
ꢈ
ꢉ
633  
6331  
6$$1  
6331  
6$$1  
633  
6$$1  
6331  
6$$1  
6331  
6$$  
6$$  
$1ꢂꢅ  
$1ꢀ  
$1ꢃ  
$1ꢁ  
$1ꢆ  
$1ꢂꢁ $1ꢂꢄ  
$1ꢂꢃ $1ꢂꢂ  
$1ꢂꢀ $1ꢉ  
$1ꢂ  
$1ꢄ  
$1ꢅ  
$1ꢈ  
.#  
,$1- $1ꢇ  
5$1- #,+  
#+%  
!ꢉ  
#!3  
"!ꢀ  
!ꢀ  
2!3  
"!ꢂ  
!ꢂ  
7%  
#3  
!ꢂꢃ  
!ꢈ  
!ꢂꢂ  
!ꢇ  
!ꢆ  
!ꢂꢀ  
633  
6$$  
!ꢅ  
!ꢁ  
!ꢄ  
!ꢃ  
-00$ꢀꢄꢉꢂ  
Figure 2  
Ball out for ×16 components, PG-TFBGA-54 (top view)  
Data Sheet  
14  
Rev. 1.30, 2006-02  
10072003-13LE-FGQQ  
HYB39S256[40/80/16]0D[C/T](L)  
256-MBit Synchronous DRAM  
Pin Configuration and Block Diagrams  
ꢂ
ꢃ
ꢄ
ꢁ
ꢅ
!
"
#
$
%
&
'
(
*
ꢆ
ꢇ
ꢈ
ꢉ
633  
6331  
6$$1  
6331  
6$$1  
633  
6$$1  
6331  
6$$1  
6331  
6$$  
6$$  
$1ꢇ  
$1ꢆ  
$1ꢅ  
$1ꢁ  
.#  
$1ꢀ  
$1ꢂ  
$1ꢃ  
$1ꢄ  
.#  
.#  
.#  
.#  
.#  
.#  
.#  
7%  
#3  
.#  
.#  
$1-  
!ꢂꢃ  
!ꢈ  
#,+  
!ꢂꢂ  
!ꢇ  
#+%  
!ꢉ  
#!3  
"!ꢀ  
!ꢀ  
2!3  
"!ꢂ  
!ꢂ  
!ꢆ  
!ꢂꢀ  
633  
6$$  
!ꢅ  
!ꢁ  
!ꢄ  
!ꢃ  
-00$ꢀꢁꢀꢀ  
Figure 3  
Ball out for ×8 components, PG-TFBGA-54 (top view)  
ꢂ
ꢃ
ꢄ
ꢁ
ꢅ
!
"
#
$
%
&
'
(
*
ꢆ
ꢇ
ꢈ
ꢉ
633  
6331  
6$$1  
6331  
6$$1  
633  
6$$1  
6331  
6$$1  
6331  
6$$  
6$$  
.#  
$1ꢄ  
.#  
$1ꢃ  
.#  
.#  
.#  
.#  
$1ꢀ  
.#  
.#  
.#  
.#  
.#  
7%  
#3  
.#  
$1ꢂ  
.#  
.#  
$1-  
!ꢂꢃ  
!ꢈ  
#,+  
!ꢂꢂ  
!ꢇ  
#+%  
!ꢉ  
#!3  
"!ꢀ  
!ꢀ  
2!3  
"!ꢂ  
!ꢂ  
!ꢆ  
!ꢂꢀ  
633  
6$$  
!ꢅ  
!ꢁ  
!ꢄ  
!ꢃ  
-00$ꢀꢁꢂꢀ  
Figure 4  
Ball out for ×4 components, PG-TFBGA-54 (top view)  
Data Sheet  
15  
Rev. 1.30, 2006-02  
10072003-13LE-FGQQ  
HYB39S256[40/80/16]0D[C/T](L)  
256-MBit Synchronous DRAM  
Pin Configuration and Block Diagrams  
2.4  
Block Diagrams  
The Block diagrams for 64M ×4, 32M ×8 and 16M ×16 are shown below.  
•
•
•
Block Diagram for 64M x 4 SDRAM (13/11/2 Addressing)  
Block Diagram for 32M x 8 SDRAM (13/10/2 Addressing)  
Block Diagram for 16M x 16 SDRAM (13/9/2 Addressing)  
C olum n A d d resses  
R ow A d d resses  
A 0 - A 9 , A 11 , A P,  
B A 0 , B A 1  
A 0 - A 1 2 ,  
B A 0 , B A 1  
C olum n A d d ress  
C o un ter  
C olum n A d d ress  
B uffe r  
R ow A d d ress  
B u ffe r  
R e fresh C o u nte r  
R ow  
R ow  
R ow  
R ow  
D e co de r  
D e co de r  
D e co de r  
D eco de r  
M em ory  
A rray  
M e m ory  
A rray  
M e m o ry  
A rray  
M e m o ry  
A rray  
B an k 0  
B a nk 1  
B a nk 2  
B a nk 3  
81 96  
x 20 48  
x 4 B it  
81 92  
x 20 48  
x 4 B it  
81 9 2  
x 20 4 8  
x 4 B it  
8 19 2  
x 2 04 8  
x 4 B it  
In p ut B u ffer  
O u tpu t B uffe r  
C o ntro l L og ic &  
T im ing G en erato r  
D Q 0 - D Q 3  
S P B 041 27_2  
Figure 5  
Block Diagram for 64M x 4 SDRAM (13/11/2 Addressing)  
Data Sheet  
16  
Rev. 1.30, 2006-02  
10072003-13LE-FGQQ  
HYB39S256[40/80/16]0D[C/T](L)  
256-MBit Synchronous DRAM  
Pin Configuration and Block Diagrams  
#OLUMN !DDRESSES  
2OW !DDRESSES  
!ꢀ ꢐ !ꢉꢊ !0ꢊ  
"!ꢀꢊ "!ꢂ  
!ꢀ ꢐ !ꢂꢃꢊ  
"!ꢀꢊ "!ꢂ  
#OLUMN !DDRESS  
#OUNTER  
#OLUMN !DDRESS  
"UFFER  
2OW !DDRESS  
"UFFER  
2EFRESH #OUNTER  
2OW  
$ECODER  
2OW  
$ECODER  
2OW  
$ECODER  
2OW  
$ECODER  
-EMOR  
!RRA  
-EMOR  
!RRA  
-EMOR  
!RRA  
-EMOR  
!RRA  
"ANK ꢀ  
"ANK ꢂ  
"ANK ꢃ  
"ANK ꢄ  
ꢈꢂꢉꢃ  
X ꢂꢀꢃꢁ  
X ꢈ "IT  
ꢈꢂꢉꢃ  
X ꢂꢀꢃꢁ  
X ꢈ "IT  
ꢈꢂꢉꢃ  
X ꢂꢀꢃꢁ  
X ꢈ "IT  
ꢈꢂꢉꢃ  
X ꢂꢀꢃꢁ  
X ꢈ "IT  
)NPUT "UFFER /UTPUT "UFFER  
$1ꢀ ꢐ $1ꢇ  
#ONTROL ,OGIC ꢍ  
4IMING 'ENERATOR  
30"ꢀꢁꢂꢃꢈ  
Figure 6  
Block Diagram for 32M x 8 SDRAM (13/10/2 Addressing)  
Data Sheet  
17  
Rev. 1.30, 2006-02  
10072003-13LE-FGQQ  
HYB39S256[40/80/16]0D[C/T](L)  
256-MBit Synchronous DRAM  
Pin Configuration and Block Diagrams  
#OLUMN !DDRESSES  
2OW !DDRESSES  
!ꢀ ꢐ !ꢈꢊ !0ꢊ  
"!ꢀꢊ "!ꢂ  
!ꢀ ꢐ !ꢂꢃꢊ  
"!ꢀꢊ "!ꢂ  
#OLUMN !DDRESS  
#OUNTER  
#OLUMN !DDRESS  
"UFFER  
2OW !DDRESS  
"UFFER  
2EFRESH #OUNTER  
2OW  
$ECODER  
2OW  
$ECODER  
2OW  
$ECODER  
2OW  
$ECODER  
-EMOR  
!RRA  
-EMOR  
!RRA  
-EMOR  
!RRA  
-EMOR  
!RRA  
"ANK ꢀ  
"ANK ꢂ  
"ANK ꢃ  
"ANK ꢄ  
ꢈꢂꢉꢃ X ꢅꢂꢃ  
X ꢂꢆ "IT  
ꢈꢂꢉꢃ X ꢅꢂꢃ  
X ꢂꢆ "IT  
ꢈꢂꢉꢃ X ꢅꢂꢃ  
X ꢂꢆ "IT  
ꢈꢂꢉꢃ X ꢅꢂꢃ  
X ꢂꢆ "IT  
)NPUT "UFFER /UTPUT "UFFER  
$1ꢀ ꢐ $1ꢂꢅ  
#ONTROL ,OGIC ꢍ  
4IMING 'ENERATOR  
30"ꢀꢁꢂꢃꢉ  
Figure 7  
Block Diagram for 16M x 16 SDRAM (13/9/2 Addressing)  
Data Sheet  
18  
Rev. 1.30, 2006-02  
10072003-13LE-FGQQ  
HYB39S256[40/80/16]0D[C/T](L)  
256-MBit Synchronous DRAM  
Functional Description  
3
Functional Description  
This chapter list all defined commands and their usage for this Synchronous DRAM family.  
3.1  
Operation Definition  
All of SDRAM operations are defined by states of control signals CS, RAS, CAS, WE, and DQM at the positive  
edge of the clock. The following list shows the truth table for the operation commands.  
Table 4  
Truth Table: Operation Command  
Operation  
Device State  
CKE  
n-11)2)  
CKE DQM BA0  
AP=  
Addr. CS RAS CAS WE  
1)2)  
1)2)  
1)2)  
1)2)  
1)2)  
1)2)  
n1)2)  
BA11)2) A101)2)  
Bank Active  
Bank Precharge  
Precharge All  
Write  
Idle3)  
Any  
H
H
H
H
H
X
X
X
X
X
X
V
V
X
V
V
V
L
V
X
X
V
V
L
L
L
L
L
L
L
H
H
H
L
H
L
L
L
L
X
Any  
Active3)  
X
H
L
L
X
H
H
Write with Auto pre Active3)  
X
H
L
charge  
Read  
Active3)  
H
H
X
X
X
X
V
V
L
V
V
L
L
H
H
L
L
H
H
Read with Auto pre Active3)  
H
charge  
Mode Register Set  
No Operation  
Idle  
H
H
H
H
H
H
X
X
X
X
H
L
X
X
X
X
X
X
X
V
X
X
X
X
X
X
V
X
X
X
X
X
X
V
X
X
X
X
X
X
L
L
L
L
Any  
Active  
Any  
Idle  
L
H
H
X
L
H
H
X
L
H
L
Burst Stop  
L
Device Deselect  
Auto Refresh  
H
L
X
H
H
X
X
X
X
Self Refresh Entry  
Self Refresh Exit  
Idle  
L
L
L
Idle (Self Refr.) L  
H
H
L
X
H
X
X
X
H
X
X
Clock Suspend Entry Active  
H
H
L
L
X
X
X
X
X
X
X
X
X
H
Power Down Entry  
(Precharge or active  
standby)  
Idle  
Active  
L
H
X
X
H
X
H
X
X
H
X
H
X
X
L
Clock Suspend Exit Active4)  
L
L
H
H
X
X
X
X
X
X
X
X
X
H
L
Power Down Exit  
Any (Power  
Down)  
Data Write/Output  
Enable  
Active  
H
H
X
X
L
X
X
X
X
X
X
X
X
Data Write/Output  
Disable  
Active  
H
X
X
X
X
1) V = Valid, x = Don’t Care, L = Low Level, H = High Level  
2) CKEn signal is input level when commands are provided, CKEn-1 signal is input level one clock before the commands are  
provided.  
3) This is the state of the banks designated by BA0, BA1 signals.  
4) Power Down Mode can not be entered in a burst cycle. When this command asserted in the burst mode cycle device is in  
clock suspend mode.  
Data Sheet  
19  
Rev. 1.30, 2006-02  
10072003-13LE-FGQQ  
HYB39S256[40/80/16]0D[C/T](L)  
256-MBit Synchronous DRAM  
Functional Description  
3.2  
Initialization  
The default power on state of the mode register is supplier specific and may be undefined. The following power  
on and initialization sequence guarantees the device is preconditioned to each users specific needs. Like a  
conventional DRAM, the Synchronous DRAM must be powered up and initialized in a predefined manner. During  
power on, all VDD and VDDQ pins must be built up simultaneously to the specified voltage when the input signals  
are held in the “NOP” state. The power on voltage must not exceed VDD + 0.3 V on any of the input pins or VDD  
supplies. The CLK signal must be started at the same time. After power on, an initial pause of 200 µs is required  
followed by a precharge of all banks using the precharge command. To prevent data contention on the DQ bus  
during power on, it is required that the DQM and CKE pins be held high during the initial pause period. Once all  
banks have been precharged, the Mode Register Set Command must be issued to initialize the Mode Register. A  
minimum of eight Auto Refresh cycles (CBR) are also required.These may be done before or after programming  
the Mode Register. Failure to follow these steps may lead to unpredictable start-up modes.  
Data Sheet  
20  
Rev. 1.30, 2006-02  
10072003-13LE-FGQQ  
HYB39S256[40/80/16]0D[C/T](L)  
256-MBit Synchronous DRAM  
Functional Description  
3.3  
Mode Register Definition  
The Mode register designates the operation mode at the read or write cycle. This register is divided into four fields.  
First, a Burst Length field which sets the length of the burst. Second, an Addressing Selection bit which programs  
the column access sequence in a burst cycle (interleaved or sequential). Third, a CAS Latency field to set the  
access time at clock cycle. Fourth, an Operation Mode field to differentiate between normal operation (Burst read  
and burst Write) and special Burst Read and Single Write mode. After the initial power up, the mode set operation  
must be done before any activate command. Any content of the mode register can be altered by re-executing the  
mode set command. All banks must be in precharged state and CKE must be high at least one clock before the  
mode set operation. After the mode register is set, a Standby or NOP command is required. Low signals of RAS,  
CAS, and WE at the positive edge of the clock activate the mode set operation. Address input data at this timing  
defines parameters to be set as shown in the previous table.  
"!ꢂ "!ꢀ !ꢂꢃ !ꢂꢂ !ꢂꢀ !ꢂꢀ !ꢉ  
!ꢈ  
!ꢇ  
!ꢆ  
!ꢅ  
#,  
!ꢁ  
!ꢄ  
"4  
!ꢃ  
!ꢂ  
",  
!ꢀ  
ꢀ
-/$%  
W
ꢀ
REGꢌ ADDR  
W
W
W
-0"3ꢀꢀꢀꢀ  
Table 5  
Mode Register Definition (BA[1:0] = 00B)  
Field  
BL  
Bits  
Type  
Description  
[2:0]  
w
Burst Length  
Number of sequential bits per DQ related to one read/write command, see  
Chapter 3.3.1  
All other bit combinations are RESERVED  
000B1,  
001B2,  
010B4,  
011B8,  
111BFull Page (Sequential burst type only),  
BT  
CL  
3
w
w
Burst Type  
See Table 7 for internal address sequence of low order address bits.  
0BSequential,  
1BInterleaved,  
[6:4]  
CAS Latency  
Number of full clocks from read command to first data valid window.  
All other bit combinations are RESERVED.  
010B2,  
011B3,  
Mode  
[12:7]  
w
Operation Mode  
All other bit combinations are RESERVED.  
0BBurst read/burst write,  
1BBurst read/single write,  
Data Sheet  
21  
Rev. 1.30, 2006-02  
10072003-13LE-FGQQ  
HYB39S256[40/80/16]0D[C/T](L)  
256-MBit Synchronous DRAM  
Functional Description  
3.3.1  
Burst Length  
Table 6  
Burst Length and Sequence  
Burst Length  
Starting Column Address  
Order of Accesses Within a Burst  
A2  
A1  
A0  
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Type=Sequential  
0–1  
Type=Interleaved  
0–1  
2
4
1–0  
1–0  
0
0
1
1
0
0
1
1
0
0
1
1
0–1–2–3  
0–1–2–3  
1–2–3–0  
1–0–3–2  
2–3–0–1  
2–3–0–1  
3–0–1–2  
3–2–1–0  
8
0
0
0
0
1
1
1
1
n
0–1–2–3–4–5–6–7  
1–2–3–4–5–6–7–0  
2–3–4–5–6–7–0–1  
3–4–5–6–7–0–1–2  
4–5–6–7–0–1–2–3  
5–6–7–0–1–2–3–4  
6–7–0–1–2–3–4–5  
7–0–1–2–3–4–5–6  
Cn, Cn+1, Cn+2 ....  
0–1–2–3–4–5–6–7  
1–0–3–2–5–4–7–6  
2–3–0–1–6–7–4–5  
3–2–1–0–7–6–5–4  
4–5–6–7–0–1–2–3  
5–4–7–6–1–0–3–2  
6–7–4–5–2–3–0–1  
7–6–5–4–3–2–1–0  
not supported  
FullPage  
Notes  
1. For a burst length of two, A1-Ai selects the two-data-element block; A0 selects the first access within the block.  
2. For a burst length of four, A2-Ai selects the four-data-element block; A0-A1 selects the first access within the  
block.  
3. For a burst length of eight, A3-Ai selects the eight-data- element block; A0-A2 selects the first access with in  
the block.  
4. Whenever a boundary of the block is reached within a given sequence above, the following access wraps  
within the block.  
Data Sheet  
22  
Rev. 1.30, 2006-02  
10072003-13LE-FGQQ  
HYB39S256[40/80/16]0D[C/T](L)  
256-MBit Synchronous DRAM  
Functional Description  
3.4  
Commands  
Refresh Mode  
SDRAM has two refresh modes, Auto Refresh and Self Refresh. Auto Refresh is similar to the CAS -before-RAS  
refresh of conventional DRAMs. All banks must be precharged before applying any refresh mode. An on-chip  
address counter increments the word and the bank addresses and no bank information is required for both refresh  
modes.  
The chip enters the Auto Refresh mode, when RAS and CAS are held low and CKE and WE are held high at a  
clock timing. The mode restores word line after the refresh and no external precharge command is necessary. A  
minimum tRC time is required between two automatic refreshes in a burst refresh mode. The same rule applies to  
any access command after the automatic refresh operation.  
The chip has an on-chip timer and the Self Refresh mode is available. The mode restores the word lines after RAS,  
CAS, and CKE are low and WE is high at a clock timing. All of external control signals including the clock are  
disabled. Returning CKE to high enables the clock and initiates the refresh exit operation. After the exit command,  
at least one tRC delay is required prior to any access command.  
Auto Precharge  
Two methods are available to precharge SDRAMs. In an automatic precharge mode, the CAS timing accepts one  
extra address, CA10, to determine whether the chip restores or not after the operation. If CA10 is high when a  
Read Command is issued, the Read with Auto-Precharge function is initiated. If CA10 is high when a Write  
Command is issued, the Write with Auto-Precharge function is initiated. The SDRAM automatically enters the  
precharge operation a time delay equal to tWR (“write recovery time”) after the last data in. A burst operation with  
Auto-Precharge may only be interrupted by a burst start to another bank. It must not be interrupted by a precharge  
or a burst stop command.  
Precharge Command  
There is also a separate precharge command available. When RAS and WE are low and CAS is high at a clock  
timing, it triggers the precharge operation. Three address bits, BA0, BA1 and A10 are used to define banks as  
shown in the following list. The precharge command can be imposed one clock before the last data out for CAS  
latency = 2 and two clocks before the last data out for CAS latency = 3. Writes require a time delay tWR (“write  
recovery time”) of 2 clocks minimum from the last data out to apply the precharge command.  
Table 7  
Bank Selection by Address Bits  
A10  
0
BA0  
BA1  
0
0
1
1
1
0
1
0
1
X
Bank 0  
Bank 1  
Bank 2  
Bank 3  
All Banks  
0
0
0
1
Data Sheet  
23  
Rev. 1.30, 2006-02  
10072003-13LE-FGQQ  
HYB39S256[40/80/16]0D[C/T](L)  
256-MBit Synchronous DRAM  
Functional Description  
Burst Termination  
Once a burst read or write operation has been initiated, there are several methods in which to terminate the burst  
operation prematurely. These methods include using another Read or Write Command to interrupt an existing  
burst operation, use a Precharge Command to interrupt a burst cycle and close the active bank, or using the Burst  
Stop Command to terminate the existing burst operation but leave the bank open for future Read or Write  
Commands to the same page of the active bank. When interrupting a burst with another Read or Write Command  
care must be taken to avoid DQ contention. The Burst Stop Command, however, has the fewest restrictions  
making it the easiest method to use when terminating a burst operation before it has been completed. If a Burst  
Stop command is issued during a burst write operation, then any residual data from the burst write cycle will be  
ignored. Data that is presented on the DQ pins before the Burst Stop Command is registered will be written to the  
memory.  
3.5  
Operations  
3.5.1  
Read and Write  
When RAS is low and both CAS and WE are high at the positive edge of the clock, a RAS cycle starts. According  
to address data, a word line of the selected bank is activated and all of sense amplifiers associated to the wordline  
are set. A CAS cycle is triggered by setting RAS high and CAS low at a clock timing after a necessary delay, tRCD  
from the RAS timing. WE is used to define either a read (WE = H) or a write (WE = L) at this stage.  
SDRAM provides a wide variety of fast access modes. In a single CAS cycle, serial data read or write operations  
are allowed at up to a 166 MHz data rate. The numbers of serial data bits are the burst length programmed at the  
mode set operation, i.e., one of 1, 2, 4 and 8 and full page. Column addresses are segmented by the burst length  
and serial data accesses are done within this boundary. The first column address to be accessed is supplied at  
the CAS timing and the subsequent addresses are generated automatically by the programmed burst length and  
its sequence. For example, in a burst length of 8 with interleave sequence, if the first address is ‘2’, then the rest  
of the burst sequence is 3, 0, 1, 6, 7, 4, and 5.  
Full page burst operation is only possible using the sequential burst type and page length is a function of the I/O  
organization and column addressing. Full page burst operation does not self terminate once the burst length has  
been reached. In other words, unlike burst lengths of 2, 4 and 8, full page burst continues until it is terminated  
using another command.  
Similar to the page mode of conventional DRAMs, burst read or write accesses on any column address are  
possible once the RAS cycle latches the sense amplifiers. The maximum tRAS or the refresh interval time limits the  
number of random column accesses. A new burst access can be done even before the previous burst ends. The  
interrupt operation at every clock cycle is supported. When the previous burst is interrupted, the remaining  
addresses are overridden by the new address with the full burst length. An interrupt which accompanies an  
operation change from a read to a write is possible by exploiting DQM to avoid bus contention.  
When two or more banks are activated sequentially, interleaved bank read or write operations are possible. With  
the programmed burst length, alternate access and precharge operations on two or more banks can realize fast  
serial data access modes among many different pages. Once two or more banks are activated, column to column  
interleave operation can be performed between different pages.  
Data Sheet  
24  
Rev. 1.30, 2006-02  
10072003-13LE-FGQQ  
HYB39S256[40/80/16]0D[C/T](L)  
256-MBit Synchronous DRAM  
Functional Description  
3.5.2  
DQM Function  
DQM has two functions for data I/O read and write operations. During reads, when it turns to “high“ at a clock  
timing, data outputs are disabled and become high impedance after two clock delay (DQM Data Disable Latency  
t
DQZ). It also provides a data mask function for writes. When DQM is activated, the write operation at the next clock  
is prohibited (DQM Write Mask Latency tDQW = zero clocks).  
3.5.3  
Suspend Mode  
During normal access mode, CKE is held high enabling the clock. When CKE is low, it freezes the internal clock  
and extends data read and write operations. One clock delay is required for mode entry and exit (Clock Suspend  
Latency tCSL).  
3.5.4  
Power Down  
In order to reduce standby power consumption, a power down mode is available. All banks must be precharged  
and the necessary Precharge delay (tRP) must occur before the SDRAM can enter the Power Down mode. Once  
the Power Down mode is initiated by holding CKE low, all of the receiver circuits except CLK and CKE are gated  
off. The Power Down mode does not perform any refresh operations, therefore the device can’t remain in Power  
Down mode longer than the Refresh period (tREF) of the device. Exit from this mode is performed by taking CKE  
“high“. One clock delay is required for Power Down mode entry and exit.  
Data Sheet  
25  
Rev. 1.30, 2006-02  
10072003-13LE-FGQQ  
HYB39S256[40/80/16]0D[C/T](L)  
256-MBit Synchronous DRAM  
Electrical Characteristics  
4
Electrical Characteristics  
4.1  
Operating Conditions  
Table 8  
Absolute Maximum Ratings  
Parameter  
Symbol  
Limit Values  
Unit  
Note/  
Test Condition  
Min.  
– 1.0  
– 1.0  
– 1.0  
0
Max.  
Input / Output voltage relative to VSS  
Voltage on VDD supply relative to VSS  
Voltage on VDDQ supply relative to VSS  
Operating Temperature  
VIN, VOUT  
VDD  
+4.6  
+4.6  
+4.6  
+70  
+150  
1
V
–
–
–
–
–
–
–
V
VDDQ  
TA  
V
°C  
°C  
W
mA  
Storage temperature range  
TSTG  
PD  
-55  
–
Power dissipation per SDRAM component  
Data out current (short circuit)  
IOUT  
–
50  
Attention: Stresses above the max. values listed here may cause permanent damage to the device.  
Exposure to absolute maximum rating conditions for extended periods may affect device  
reliability. Maximum ratings are absolute ratings; exceeding only one of these values maycause  
irreversible damage to the integrated circuit.  
Table 9  
DC Characteristics1)  
Parameter  
Symbol  
Values  
Max.  
Unit  
Note/  
Test Condition  
Min.  
3.0  
3.0  
2.0  
– 0.3  
2.4  
–
2)  
Supply Voltage  
VDD  
VDDQ  
VIH  
3.6  
3.6  
V
2)  
I/O Supply Voltage  
V
2)3)  
2)3)  
2)  
Input high voltage  
V
DDQ+0.3  
V
Input low voltage  
VIL  
+0.8  
–
V
Output high voltage (IOUT = – 4.0 mA)  
Output low voltage (IOUT = 4.0 mA)  
VOH  
VOL  
IIL  
V
2)  
0.4  
+5  
V
Input leakage current, any input  
(0 V < VIN < VDD, all other inputs = 0 V)  
– 5  
µA  
–
–
Output leakage current  
IOL  
– 5  
+5  
µA  
(DQs are disabled, 0 V < VOUT < VDDQ  
1) TA = 0 to 70 οC  
)
2) All voltages are referenced to VSS  
3) VIH may overshoot to VDDQ + 2.0 V for pulse width of < 4ns with 3.3 V. VIL may undershoot to -2.0 V for pulse width < 4.0 ns  
with 3.3 V. Pulse width measured at 50% points with amplitude measured peak to DC reference.  
Data Sheet  
26  
Rev. 1.30, 2006-02  
10072003-13LE-FGQQ  
HYB39S256[40/80/16]0D[C/T](L)  
256-MBit Synchronous DRAM  
Electrical Characteristics  
Table 10  
Input and Output Capacitances1)  
Parameter  
Symbol  
Values2)  
Min.  
2.5  
Unit  
Max.  
3.5  
Input Capacitances: CK, CK  
CI1  
CI2  
pF  
pF  
Input Capacitance  
2.5  
3.8  
(A0-A12, BA0, BA1, RAS, CAS, WE, CS, CKE, DQM)  
Input/Output Capacitance (DQ)  
CI0  
4.0  
6.0  
pF  
1) TA = 0 to 70 °C; VDD,VDDQ = 3.3 V ± 0.3 V, f = 1 MHz  
2) Capacitance values are shown for TSOP-54 packages. Capacitance values for TFBGA packages are lower by 0.5 pF  
Table 11  
IDD Conditions  
Parameter  
Symbol  
Operating Current  
IDD1  
One bank active, Burst length = 1  
Precharge Standby Current in Power Down Mode  
Recharge Standby Current in Non-Power Down Mode  
IDD2P  
IDD2N  
IDD3N  
IDD3P  
IDD4  
No Operating Current  
Active state (max. 4 banks)  
Burst Operating Current  
Read command cycling  
Auto Refresh Current  
Auto Refresh command cycling  
IDD5  
IDD6  
Self Refresh Current (standard )  
Self Refresh Mode, CKE=0.2V, tCK=infinity  
Data Sheet  
27  
Rev. 1.30, 2006-02  
10072003-13LE-FGQQ  
HYB39S256[40/80/16]0D[C/T](L)  
256-MBit Synchronous DRAM  
Electrical Characteristics  
Table 12  
Symbol  
I
DD Specifications and Conditions1)  
-6  
-7  
-7.5  
Max.  
80  
2
-8  
Unit  
Note/ Test Condition  
Max.  
100  
2
Max.  
80  
2
Max.  
80  
2
IDD1  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
t
RC = tRC(min), IO = 0 mA 2)3)  
2)  
IDD2P  
IDD2N  
IDD3N  
IDD3P  
IDD4  
CS =VIH (min.), CKE ≤VIL(max)  
2)  
35  
40  
5
30  
35  
5
30  
35  
5
25  
30  
5
CS =VIH (min), CKE≥ VIH(min)  
CS = VIH(min), CKE ≥VIH(min)  
2)  
2)  
CS = VIH(min), CKE ≤ VIL(max)  
2)3)  
110  
220  
3
90  
190  
3
90  
190  
3
70  
160  
3
4)  
IDD5  
t
t
RFC = tRFC(min)  
RFC = 7.8 µs  
IDD6  
3
3
3
3
Standard components  
Low power components  
1.5  
1.5  
1.5  
1.5  
1) TA = 0 to 70 °C; VSS = 0 V; VDD, VDDQ = 3.3 V ± 0.3 V  
2) These parameters depend on the cycle rate. All values are measured at 166 MHz for -6, at 133 MHz for  
-7 and -7.5 and at 100 MHz for -8 components with the outputs open. Input signals are changed once during tCK.  
3) These parameters are measured with continuous data stream during read access and all DQ toggling. CL=3 and BL=4 is  
assumed and the VDDQ current is excluded.  
4) tRFC= tRFC(min) “burst refresh”, tRFC= 7.8 µs “distributed refresh”.  
Data Sheet  
28  
Rev. 1.30, 2006-02  
10072003-13LE-FGQQ  
HYB39S256[40/80/16]0D[C/T](L)  
256-MBit Synchronous DRAM  
Electrical Characteristics  
4.2  
AC Characteristics  
Table 13  
AC Timing - Absolute Specifications –8/-7.5/–7/-6 1)2)3)  
Parameter  
Symbol –8  
–7.5  
–7  
–6  
Unit Note  
PC100–222 PC133–333 PC133–222 PC166–333  
Min. Max. Min. Max. Min. Max. Min. Max.  
Clock and Clock Enable  
Clock Cycle Time  
tCK3  
tCK2  
fCK3  
fCK2  
tAC3  
tAC2  
tCH  
8
—
—
125  
100  
6
7.5  
10  
—
—
7
—
6
—
ns  
ns  
CL3  
CL2  
10  
—
—
—
—
3
—
7.5  
—
—
7.5  
—
—
—
—
2
—
Clock Frequency  
133  
100  
5.4  
6
143  
133  
5.4  
5.4  
—
166  
133  
5
MHz CL3  
MHz CL2  
—
—
Access Time from Clock  
—
—
ns  
ns  
ns  
ns  
ns  
CL3  
CL23)4)5)  
6
—
—
5.4  
—
Clock High Pulse Width  
Clock Low Pulse Width  
Transition time  
—
—
2.5  
2.5  
—
2.5  
2.5  
0.3  
tCL  
3
—
—
2
—
tT  
0.5 10  
0.3 1.2  
1.2  
0.3  
1.2  
Setup and Hold Times  
Input Setup Time  
Input Hold Time  
6)  
6)  
6)  
6)  
tIS  
2
1
2
1
2
—
—
—
—
—
1.5  
0.8  
1.5  
0.8  
2
—
—
—
—
—
1.5  
0.8  
1.5  
0.8  
2
—
—
—
—
—
1.5  
0.8  
1.5  
0.8  
2
—
—
—
—
—
ns  
tIH  
ns  
CKE Setup Time  
tCKS  
tCKH  
tRSC  
ns  
CKE Hold Time  
ns  
Mode Register Set-up to  
Active delay  
CLK  
Power Down Mode Entry Time tSB  
0
8
0
7.5  
0
7
0
6
ns  
Common Parameters  
7)  
7)  
7)  
7)  
Row to Column Delay Time  
Row Precharge Time  
Row Active Time  
tRCD  
20  
20  
48  
70  
70  
—
—
20  
20  
—
—
15  
15  
—
—
15  
15  
—
—
ns  
ns  
tRP  
tRAS  
tRC  
100k 45  
100k 37  
100k 36  
100k ns  
Row Cycle Time  
—
—
67  
67  
—
—
60  
63  
—
—
60  
60  
—
—
ns  
ns  
Row Cycle Time during Auto tRFC  
Refresh  
7)  
Activate(a) to Activate(b)  
Command period  
tRRD  
16  
1
—
—
15  
1
—
—
14  
1
—
—
12  
1
—
—
ns  
CAS(a) to CAS(b) Command tCCD  
CLK  
period  
Refresh Cycle  
Refresh Period (8192 cycles) tREF  
–
1
3
64  
—
—
–
1
3
64  
—
—
–
1
3
64  
—
—
–
64  
—
—
ms  
CLK  
ns  
Self Refresh Exit Time  
Data Out Hold Time  
Read Cycle  
tSREX  
tOH  
1
3)5)  
2.5  
Data Out to Low Impedance  
Time  
tLZ  
0
—
0
—
0
—
0
—
ns  
Data Sheet  
29  
Rev. 1.30, 2006-02  
10072003-13LE-FGQQ  
HYB39S256[40/80/16]0D[C/T](L)  
256-MBit Synchronous DRAM  
Electrical Characteristics  
Table 13  
AC Timing - Absolute Specifications –8/-7.5/–7/-6 (cont’d)1)2)3)  
Symbol –8 –7.5 –7  
Parameter  
–6  
Unit Note  
PC100–222 PC133–333 PC133–222 PC166–333  
Min. Max. Min. Max. Min. Max. Min. Max.  
Data Out to High Impedance tHZ  
3
8
3
7
3
7
3
6
ns  
Time  
DQM Data Out Disable  
Latency  
tDQZ  
—
2
—
2
—
2
—
2
CLK  
Write Cycle  
8)  
Last Data Input to Precharge tWR  
(Write without AutoPrecharge)  
15  
—
15  
—
—
14  
0
—
—
12  
0
—
—
ns  
9)  
Last Data Input to Activate  
(Write with AutoPrecharge)  
tDAL(min.) (tWR/tCK) + (tRP/tCK)  
tDQW  
CLK  
DQM Write Mask Latency  
0
—
0
CLK  
1) TA = 0 to 70 °C; VSS = 0 V; VDD, VDDQ = 3.3 V ± 0.3 V, tT = 1 ns  
2) For proper power-up see the operation section of this data sheet.  
3) AC timing tests for LV-TTL versions have VIL = 0.4 V and VIH = 2.4 V with the timing referenced to the 1.4 V crossover point.  
The transition time is measured between VIH and VIL. All AC measurements assume tT = 1 ns with the AC output load circuit  
shown in figure below. Specified tAC and tOH parameters are measured with a 50 pF only, without any resistive termination  
and with an input signal of 1V / ns edge rate between 0.8 V and 2.0 V.  
4) If clock rising time is longer than 1 ns, a time (tT/2 - 0.5) ns has to be added to this parameter.  
5) Access time from clock tac is 4.6 ns for PC133 components with no termination and 0 pF load,  
Data out hold time toh is 1.8 ns for PC133 components with no termination and 0 pF load.  
6) If tT is longer than 1 ns, a time (tT - 1) ns has to be added to this parameter.  
7) These parameter account for the number of clock cycles and depend on the operating frequency of the clock, as follows:  
the number of clock cycles = specified value of timing period (counted in fractions as a whole number)  
8) It is recommended to use two clock cycles between the last data-in and the precharge command in case of a write command  
without Auto-Precharge. One clock cycle between the last data-in and the precharge command is also supported, but  
restricted to cycle times tck greater or equal the specified twr value, where tck is equal to the actual system clock time.  
9) When a Write command with AutoPrecharge has been issued, a time of tDAL(min) has be fullfilled before the next Activate  
Command can be applied. For each of the terms, if not already an integer, round up to the next highest integer. tCK is equal  
to the actual system clock time.  
t C H  
2.4 V  
0.4 V  
1.4  
V
C LO C K  
tT  
tC L  
tIH  
tIS  
IN PU T  
1.4 V  
tAC  
tAC  
tLZ  
tO H  
O U TP U T  
1.4 V  
I/O  
t H Z  
50 pF  
Measurement conditions for  
AC and tOH  
IO.vsd  
t
Figure 8  
Measurement conditions for tAC and tOH  
30  
Data Sheet  
Rev. 1.30, 2006-02  
10072003-13LE-FGQQ  
HYB39S256[40/80/16]0D[C/T](L)  
256-MBit Synchronous DRAM  
Timing Diagrams  
5
Timing Diagrams  
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Figure 9  
Bank Activate Command Cycle  
7ꢂꢀ  
7ꢄꢀ  
7ꢉꢀ  
7ꢅꢀ  
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'287ꢀ$ꢂꢀ '287ꢀ$ꢄꢀ '287ꢀ$ꢉꢀ '287ꢀ$ꢅꢀ  
637ꢂꢅꢆꢄꢉꢀ  
Figure 10 Burst Read Operation  
Data Sheet  
31  
Rev. 1.30, 2006-02  
10072003-13LE-FGQQ  
HYB39S256[40/80/16]0D[C/T](L)  
256-MBit Synchronous DRAM  
Timing Diagrams  
ꢀ%XUVWꢁ/HQJWKꢁ ꢁꢄꢅꢁ&$6ꢁODWHQF\ꢁ ꢁꢆꢅꢁꢂꢃꢁ  
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7ꢉꢀ  
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5HDGꢀ%ꢀ  
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Figure 11 Read Interrupted by a Read  
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7ꢉꢀ  
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Figure 12 Read to Write Interval  
Data Sheet  
32  
Rev. 1.30, 2006-02  
10072003-13LE-FGQQ  
HYB39S256[40/80/16]0D[C/T](L)  
256-MBit Synchronous DRAM  
Timing Diagrams  
ꢀ%XUVWꢁ/HQJWKꢁ ꢁꢄꢅꢁ&$6ꢁODWHQF\ꢁ ꢁꢆꢃꢁ  
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Figure 13 Minimum Read to Write Interval  
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637ꢂꢅꢐꢈꢂꢀ  
Figure 14 Non-Minimum Read to Write Interval  
Data Sheet  
33  
Rev. 1.30, 2006-02  
10072003-13LE-FGQQ  
HYB39S256[40/80/16]0D[C/T](L)  
256-MBit Synchronous DRAM  
Timing Diagrams  
ꢀ%XUVWꢁ/HQJWKꢁ ꢁꢄꢅꢁ&$6ꢁODWHQF\ꢁ ꢁꢆꢅꢁꢂꢃꢁ  
7ꢂꢀ  
7ꢄꢀ  
7ꢉꢀ  
7ꢅꢀ  
7ꢈꢀ  
7ꢊꢀ  
7ꢋꢀ  
7ꢆꢀ  
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&RPPDQGꢀ  
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123ꢀ  
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Figure 15 Burst Write Operation  
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7ꢂꢀ  
7ꢄꢀ  
7ꢉꢀ  
7ꢅꢀ  
7ꢈꢀ  
1 Clk Interval  
7ꢊꢀ  
7ꢋꢀ  
7ꢆꢀ  
7ꢇꢀ  
&/.ꢀ  
&RPPDQGꢀ  
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123ꢀ  
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Figure 16 Write Interrupted by a Write  
Data Sheet  
34  
Rev. 1.30, 2006-02  
10072003-13LE-FGQQ  
HYB39S256[40/80/16]0D[C/T](L)  
256-MBit Synchronous DRAM  
Timing Diagrams  
ꢀ%XUVWꢁ/HQJWKꢁ ꢁꢄꢅꢁ&$6ꢁODWHQF\ꢁ ꢁꢆꢅꢁꢂꢃꢁ  
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7ꢉꢀ  
7ꢅꢀ  
7ꢈꢀ  
7ꢊꢀ  
7ꢋꢀ  
7ꢆꢀ  
7ꢇꢀ  
&/.ꢀ  
&RPPDQGꢀ  
123ꢀ  
:ULWHꢀ$ꢀ  
',1ꢀ$ꢂꢀ  
',1ꢀ$ꢂꢀ  
5HDGꢀ%ꢀ  
GRQꢍWꢀFDUHꢀ  
GRQꢍWꢀFDUHꢀ  
123ꢀ  
123ꢀ  
123ꢀ  
123ꢀ  
123ꢀ  
123ꢀ  
&$6ꢀ  
ODWHQF\ꢀ ꢀꢉꢀ  
Wꢀ&.ꢉꢀꢌꢀ'4ꢍVꢀ  
'287ꢀ%ꢂꢀ '287ꢀ%ꢄꢀ '287ꢀ%ꢉꢀ '287ꢀ%ꢅꢀ  
&$6ꢀ  
GRQꢍWꢀFDUHꢀ  
ODWHQF\ꢀ ꢀꢅꢀ  
Wꢀ&.ꢅꢀꢌꢀ'4ꢍVꢀ  
'287ꢀ%ꢂꢀ '287ꢀ%ꢄꢀ '287ꢀ%ꢉꢀ '287ꢀ%ꢅꢀ  
,QSXWꢀGDWDꢀPXVWꢀEHꢀUHPRYHGꢀIURPꢀWKHꢀ'4ꢍVꢀ  
DWꢀOHDVWꢀRQHꢀFORFNꢀF\FOHꢀEHIRUHꢀWKHꢀ5HDGꢀGDWDꢀ  
DSSHDUVꢀRQꢀWKHꢀRXWSXWVꢀWRꢀDYRLGꢀGDWDꢀFRQWHQWLRQꢃꢀ  
,QSXWꢀGDWDꢀIRUꢀWKHꢀ:ULWHꢀLVꢀLJQRUHGꢃꢀ  
637ꢂꢅꢆꢄꢐꢀ  
Figure 17 Write Interrupted by a Read  
ꢀ%XUVWꢁ/HQJWKꢁ ꢁꢆꢅꢁ&$6ꢁODWHQF\ꢁ ꢁꢆꢅꢁꢂꢃꢁ  
7ꢂꢀ  
7ꢄꢀ  
7ꢉꢀ  
7ꢅꢀ  
7ꢈꢀ  
7ꢊꢀ  
7ꢋꢀ  
7ꢆꢀ  
7ꢇꢀ  
&/.ꢀ  
:ULWHꢀ$ꢀ  
%DQNꢀ$ꢀ  
$FWLYHꢀ  
&RPPDQGꢀ  
123ꢀ  
123ꢀ  
123ꢀ  
123ꢀ  
123ꢀ  
123ꢀ  
123ꢀ  
$XWRꢀ3UHFKDUJHꢀ  
Wꢀ:5ꢀ  
Wꢀ53ꢀ  
&$6ꢀ  
ODWHQF\ꢀ ꢀꢉꢀ  
'4ꢍVꢀ  
',1ꢀ$ꢂꢀ  
',1ꢀ$ꢄꢀ  
Wꢀ:5ꢀ  
Wꢀ53ꢀ  
&$6ꢀ  
ODWHQF\ꢀ ꢀꢅꢀ  
'4ꢍVꢀ  
',1ꢀ$ꢂꢀ  
',1ꢀ$ꢄꢀ  
%HJLQꢀ$XWRꢀ3UHFKDUJHꢀ  
%DQNꢀFDQꢀEHꢀUHDFWLYDWHGꢀDIWHUꢀWꢀ53ꢀ  
637ꢂꢅꢆꢉꢂꢀ  
Figure 18 Burst Write with Auto-Precharge  
Data Sheet  
35  
Rev. 1.30, 2006-02  
10072003-13LE-FGQQ  
HYB39S256[40/80/16]0D[C/T](L)  
256-MBit Synchronous DRAM  
Timing Diagrams  
ꢀ%XUVWꢁ/HQJWKꢁ ꢁꢄꢅꢁ&$6ꢁODWHQF\ꢁ ꢁꢆꢅꢁꢂꢃꢁ  
7ꢂꢀ  
7ꢄꢀ  
7ꢉꢀ  
7ꢅꢀ  
7ꢈꢀ  
7ꢊꢀ  
7ꢋꢀ  
7ꢆꢀ  
7ꢇꢀ  
&/.ꢀ  
5HDGꢀ$ꢀ  
ZLWKꢀ$3ꢀ  
&RPPDQGꢀ  
123ꢀ  
123ꢀ  
123ꢀ  
123ꢀ  
123ꢀ  
123ꢀ  
123ꢀ  
123ꢀ  
Wꢀ53ꢀ  
&$6ꢀ  
ODWHQF\ꢀ ꢀꢉꢀ  
Wꢀ&.ꢉꢀꢌꢀ'4ꢍVꢀ  
'287ꢀ$ꢂꢀ '287ꢀ$ꢄꢀ '287ꢀ$ꢉꢀ '287ꢀ$ꢅꢀ  
Wꢀ53ꢀ  
&$6ꢀ  
ODWHQF\ꢀ ꢀꢅꢀ  
Wꢀ&.ꢅꢀꢌꢀ'4ꢍVꢀ  
'287ꢀ$ꢂꢀ '287ꢀ$ꢄꢀ '287ꢀ$ꢉꢀ '287ꢀ$ꢅꢀ  
%HJLQꢀ$XWRꢀ3UHFKDUJHꢀ  
%DQNꢀFDQꢀEHꢀUHDFWLYDWHGꢀDIWHUꢀWꢀ  
637ꢂꢅꢆꢉꢄꢀ  
53ꢀ  
Figure 19 Burst Read with Auto-Precharge  
Data Sheet  
36  
Rev. 1.30, 2006-02  
10072003-13LE-FGQQ  
HYB39S256[40/80/16]0D[C/T](L)  
256-MBit Synchronous DRAM  
Timing Diagrams  
%XUVWꢀ/HQJWKꢀ ꢀꢈꢌꢀ&$6ꢀ/DWHQF\ꢀ ꢀꢉꢀ  
7ꢂꢀ 7ꢄꢀ 7ꢉꢀ 7ꢅꢀ 7ꢈꢀ 7ꢊꢀ 7ꢋꢀ 7ꢆꢀ 7ꢇꢀ 7ꢐꢀ 7ꢄꢂꢀ 7ꢄꢄꢀ 7ꢄꢉꢀ 7ꢄꢅꢀ 7ꢄꢈꢀ 7ꢄꢊꢀ 7ꢄꢋꢀ 7ꢄꢆꢀ 7ꢄꢇꢀ 7ꢄꢐꢀ 7ꢉꢂꢀ 7ꢉꢄꢀ 7ꢉꢉꢀ  
&/.ꢁ  
&.(ꢁ  
Wꢀ&+ꢀ  
Wꢀ&.ꢉꢀ  
Wꢀ&/ꢀ  
Wꢀ&.+ꢀ  
Wꢀ&.6ꢀ  
%HJLQꢀ$XWRꢀ  
3UHFKDUJHꢀ  
%DQNꢀ$ꢀ  
%HJLQꢀ$XWRꢀ  
3UHFKDUJHꢀ  
%DQNꢀ%ꢀ  
Wꢀ&6ꢀ  
Wꢀ&+ꢀ  
&6ꢁ  
5$6ꢁ  
&$6ꢁ  
:(ꢁ  
%6ꢁ  
Wꢀ  
$+ꢀ  
$3ꢁ  
5$[ꢀ  
5$[ꢀ  
5%[ꢀ  
5%[ꢀ  
5$\ꢀ  
5$]ꢀ  
5%\ꢀ  
5%\ꢀ  
Wꢀ  
$6ꢀ  
$GGUꢇꢁ  
'40ꢁ  
&$[ꢀ  
&%[ꢀ  
5$\ꢀ  
5$\ꢀ  
5$]ꢀ  
Wꢀ'6ꢀ  
Wꢀ5&'ꢀ  
Wꢀ:5ꢀ  
Wꢀ'+ꢀ  
Wꢀ5&ꢀ  
Wꢀ53ꢀ  
Wꢀ55'ꢀ  
+Lꢏ=ꢀ  
'4ꢁ  
$[ꢂꢀ $[ꢄꢀ $[ꢉꢀ $[ꢅꢀ %[ꢂꢀ %[ꢄꢀ %[ꢉꢀ %[ꢅꢀ $\ꢂꢀ $\ꢄꢀ $\ꢉꢀ $\ꢅꢀ  
$FWLYDWHꢀ  
$FWLYDWHꢀ  
&RPPDQGꢀ  
%DQNꢀ%ꢀ  
$FWLYDWHꢀ  
:ULWHꢀ  
3UHFKDUJHꢀ  
&RPPDQGꢀ  
%DQNꢀ$ꢀ  
$FWLYDWHꢀ  
$FWLYDWHꢀ  
&RPPDQGꢀ  
%DQNꢀ%ꢀ  
&RPPDQGꢀ  
%DQNꢀ$ꢀ  
&RPPDQGꢀ &RPPDQGꢀ  
&RPPDQGꢀ  
%DQNꢀ$ꢀ  
%DQNꢀ$ꢀ  
%DQNꢀ$ꢀ  
:ULWHꢀZLWKꢀ  
:ULWHꢀZLWKꢀ  
$XWRꢀ3UHFKDUJHꢀ  
&RPPDQGꢀ  
%DQNꢀ$ꢀ  
$XWRꢀ3UHFKDUJHꢀ  
&RPPDQGꢀ  
%DQNꢀ%ꢀ  
637ꢂꢅꢐꢄꢂꢀ  
Figure 20  
AC Parameters for a Write Timing  
Data Sheet  
37  
Rev. 1.30, 2006-02  
10072003-13LE-FGQQ  
HYB39S256[40/80/16]0D[C/T](L)  
256-MBit Synchronous DRAM  
Timing Diagrams  
%XUVWꢀ/HQJWKꢀ ꢀꢉꢌꢀ&$6ꢀ/DWHQF\ꢀ ꢀꢉꢀ  
7ꢂꢀ  
7ꢄꢀ  
7ꢉꢀ  
7ꢅꢀ  
7ꢈꢀ  
7ꢊꢀ  
7ꢋꢀ  
7ꢆꢀ  
7ꢇꢀ  
7ꢐꢀ  
7ꢄꢂꢀ  
7ꢄꢄꢀ  
7ꢄꢉꢀ  
7ꢄꢅꢀ  
&/.ꢁ  
&.(ꢁ  
Wꢀ&+ꢀ  
Wꢀ&.ꢉꢀ  
Wꢀ&/ꢀ  
Wꢀ&.+ꢀ  
Wꢀ&6ꢀ  
%HJLQꢀ$XWRꢀ  
3UHFKDUJHꢀ  
%DQNꢀ$ꢀ  
%HJLQꢀ$XWRꢀ  
3UHFKDUJHꢀ  
%DQNꢀ%ꢀ  
Wꢀ&.6ꢀ  
Wꢀ&+ꢀ  
&6ꢁ  
5$6ꢁ  
&$6ꢁ  
:(ꢁ  
%6ꢁ  
Wꢀ$+ꢀ  
$3ꢁ  
5$[ꢀ  
5$[ꢀ  
5%[ꢀ  
5$\ꢀ  
5$\ꢀ  
Wꢀ$6ꢀ  
$GGUꢇꢁ  
&$[ꢀ  
5%[ꢀ  
5%[ꢀ  
Wꢀ55'ꢀ  
Wꢀ5$6ꢀ  
Wꢀ5&ꢀ  
'40ꢁ  
'4ꢁ  
Wꢀ  
Wꢀ$&ꢉꢀ  
Wꢀ+=ꢀ  
Wꢀ53ꢀ  
/=ꢀ  
Wꢀ$&ꢉꢀ  
Wꢀ2+ꢀ  
Wꢀ5&'ꢀ  
Wꢀ+=ꢀ  
%[ꢄꢀ  
+Lꢏ=ꢀ  
$[ꢂꢀ  
$[ꢄꢀ  
%[ꢂꢀ  
$FWLYDWHꢀ  
&RPPDQGꢀ  
%DQNꢀ$ꢀ  
5HDGꢀZLWKꢀ  
$FWLYDWHꢀ  
5HDGꢀZLWKꢀ  
3UHFKDUJHꢀ  
&RPPDQGꢀ  
%DQNꢀ$ꢀ  
$FWLYDWHꢀ  
$XWRꢀ3UHFKDUJHꢀ  
&RPPDQGꢀ  
%DQNꢀ$ꢀ  
&RPPDQGꢀ  
%DQNꢀ%ꢀ  
$XWRꢀ3UHFKDUJHꢀ  
&RPPDQGꢀ  
%DQNꢀ%ꢀ  
&RPPDQGꢀ  
%DQNꢀ$ꢀ  
637ꢂꢅꢐꢄꢄꢀ  
Figure 21 AC Parameters for a Read Timing  
Data Sheet  
38  
Rev. 1.30, 2006-02  
10072003-13LE-FGQQ  
HYB39S256[40/80/16]0D[C/T](L)  
256-MBit Synchronous DRAM  
Timing Diagrams  
&$6ꢀ/DWHQF\ꢀ ꢀꢉꢀ  
7ꢂꢀ 7ꢄꢀ 7ꢉꢀ 7ꢅꢀ 7ꢈꢀ 7ꢊꢀ 7ꢋꢀ 7ꢆꢀ 7ꢇꢀ 7ꢐꢀ 7ꢄꢂꢀ 7ꢄꢄꢀ 7ꢄꢉꢀ 7ꢄꢅꢀ 7ꢄꢈꢀ 7ꢄꢊꢀ 7ꢄꢋꢀ 7ꢄꢆꢀ 7ꢄꢇꢀ 7ꢄꢐꢀ 7ꢉꢂꢀ 7ꢉꢄꢀ 7ꢉꢉꢀ  
&/.ꢁ  
&.(ꢁ  
Wꢀ56&ꢀ  
&6ꢁ  
5$6ꢁ  
&$6ꢁ  
:(ꢁ  
%6ꢈꢅꢁ%6ꢉꢁ  
$ꢉꢈꢅꢁ$ꢉꢉꢁ  
$GGUHVVꢀ.H\ꢀ  
$ꢈꢊ$ꢋꢁ  
3UHFKDUJHꢀ  
&RPPDQGꢀ  
$OOꢀ%DQNVꢀ  
$Q\ꢀ  
&RPPDQGꢀ  
0RGHꢀ5HJLVWHUꢀ  
6HWꢀ&RPPDQGꢀ
 
637ꢂꢅꢐꢄꢉꢀ  
Figure 22 Mode Register Set  
Data Sheet  
39  
Rev. 1.30, 2006-02  
10072003-13LE-FGQQ  
HYB39S256[40/80/16]0D[C/T](L)  
256-MBit Synchronous DRAM  
Timing Diagrams  
7ꢂꢀ 7ꢄꢀ 7ꢉꢀ 7ꢅꢀ 7ꢈꢀ 7ꢊꢀ 7ꢋꢀ 7ꢆꢀ 7ꢇꢀ 7ꢐꢀ 7ꢄꢂꢀ 7ꢄꢄꢀ 7ꢄꢉꢀ 7ꢄꢅꢀ 7ꢄꢈꢀ 7ꢄꢊꢀ 7ꢄꢋꢀ 7ꢄꢆꢀ 7ꢄꢇꢀ 7ꢄꢐꢀ 7ꢉꢂꢀ 7ꢉꢄꢀ 7ꢉꢉꢀ  
&/.ꢁ  
&.(ꢁ  
+LJKꢀ /HYHOꢀ  
ꢉꢀ&ORFNꢀPLQꢃꢀ  
0LQLPXPꢀRIꢀꢇꢀ5HIUHVKꢀ&\FOHVꢀDUHꢀUHTXLUHGꢀ  
LVꢀ UHTXLUHGꢀ  
&6ꢁ  
5$6ꢁ  
&$6ꢁ  
:(ꢁ  
%6ꢁ  
$3ꢁ  
$GGUHVVꢀ.H\ꢀ  
$GGUꢇꢁ  
'40ꢁ  
Wꢀ53ꢀ  
Wꢀ5&ꢀ  
+Lꢏ=ꢀ  
'4ꢁ  
3UHFKDUJHꢀ  
&RPPDQGꢀ  
$OOꢀ%DQNVꢀ  
ꢇWKꢀ$XWRꢀ5HIUHVKꢀ  
&RPPDQGꢀ  
0RGHꢀ5HJLVWHUꢀ  
6HWꢀ&RPPDQGꢀ  
$Q\ꢀ  
&RPPDQGꢀ  
,QSXWVꢀPXVWꢀEHꢀ  
VWDEOHꢀIRUꢀ ꢉꢂꢂꢀ Vꢀ  
ꢄVWꢀ$XWRꢀ5HIUHVKꢀ  
&RPPDQGꢀ  
637ꢂꢅꢐꢄꢅꢀ  
Figure 23 Power on Sequence and Auto Refresh (CBR)  
Data Sheet  
40  
Rev. 1.30, 2006-02  
10072003-13LE-FGQQ  
HYB39S256[40/80/16]0D[C/T](L)  
256-MBit Synchronous DRAM  
Timing Diagrams  
%XUVWꢀ/HQJWKꢀ ꢀꢈꢌꢀ&$6ꢀ/DWHQF\ꢀ ꢀꢉꢀ  
7ꢂꢀ 7ꢄꢀ 7ꢉꢀ 7ꢅꢀ 7ꢈꢀ 7ꢊꢀ 7ꢋꢀ 7ꢆꢀ 7ꢇꢀ 7ꢐꢀ 7ꢄꢂꢀ 7ꢄꢄꢀ 7ꢄꢉꢀ 7ꢄꢅꢀ 7ꢄꢈꢀ 7ꢄꢊꢀ 7ꢄꢋꢀ 7ꢄꢆꢀ 7ꢄꢇꢀ 7ꢄꢐꢀ 7ꢉꢂꢀ 7ꢉꢄꢀ 7ꢉꢉꢀ  
&/.ꢁ  
Wꢀ&.ꢉꢀ  
&.(ꢁ  
&6ꢁ  
5$6ꢁ  
&$6ꢁ  
:(ꢁ  
%6ꢁ  
$3ꢁ  
5$[ꢀ  
$GGUꢇꢁ  
'40ꢁ  
5$[ꢀ  
&$[ꢀ  
Wꢀ&6/ꢀ  
Wꢀ+=ꢀ  
Wꢀ&6/ꢀ  
$[ꢂꢀ  
Wꢀ&6/ꢀ  
+Lꢏ=ꢀ  
'4ꢁ  
$[ꢄꢀ  
$[ꢉꢀ  
$[ꢅꢀ  
$FWLYDWHꢀ  
5HDGꢀ  
&ORFNꢀ  
&ORFNꢀ  
&ORFNꢀ  
&RPPDQGꢀ &RPPDQGꢀ  
6XVSHQGꢀ  
ꢄꢀ&\FOHꢀ  
6XVSHQGꢀ  
ꢉꢀ&\FOHVꢀ  
6XVSHQGꢀ  
ꢅꢀ&\FOHVꢀ  
%DQNꢀ$ꢀ  
%DQNꢀ$ꢀ  
637ꢂꢅꢐꢄꢈꢀ  
Figure 24 Clock Suspension During Burst Read CAS Latency = 2  
Data Sheet  
41  
Rev. 1.30, 2006-02  
10072003-13LE-FGQQ  
HYB39S256[40/80/16]0D[C/T](L)  
256-MBit Synchronous DRAM  
Timing Diagrams  
%XUVWꢀ/HQJWKꢀ ꢀꢈꢌꢀ&$6ꢀ/DWHQF\ꢀ ꢀꢅꢀ  
7ꢂꢀ 7ꢄꢀ 7ꢉꢀ 7ꢅꢀ 7ꢈꢀ 7ꢊꢀ 7ꢋꢀ 7ꢆꢀ 7ꢇꢀ 7ꢐꢀ 7ꢄꢂꢀ 7ꢄꢄꢀ 7ꢄꢉꢀ 7ꢄꢅꢀ 7ꢄꢈꢀ 7ꢄꢊꢀ 7ꢄꢋꢀ 7ꢄꢆꢀ 7ꢄꢇꢀ 7ꢄꢐꢀ 7ꢉꢂꢀ 7ꢉꢄꢀ 7ꢉꢉꢀ  
&/.ꢁ  
Wꢀ&.ꢅꢀ  
&.(ꢁ  
&6ꢁ  
5$6ꢁ  
&$6ꢁ  
:(ꢁ  
%6ꢁ  
$3ꢁ  
5$[ꢀ  
$GGUꢇꢁ  
'40ꢁ  
5$[ꢀ  
&$[ꢀ  
Wꢀ&6/ꢀ  
Wꢀ&6/ꢀ  
Wꢀ&6/ꢀ  
Wꢀ+=ꢀ  
+Lꢏ=ꢀ  
'4ꢁ  
$[ꢂꢀ  
$[ꢄꢀ  
$[ꢉꢀ  
$[ꢅꢀ  
$FWLYDWHꢀ  
&RPPDQGꢀ  
%DQNꢀ$ꢀ  
5HDGꢀ  
&RPPDQGꢀ  
%DQNꢀ$ꢀ  
&ORFNꢀ  
&ORFNꢀ  
&ORFNꢀ  
6XVSHQGꢀ  
ꢄꢀ&\FOHꢀ  
6XVSHQGꢀ  
ꢉꢀ&\FOHVꢀ  
6XVSHQGꢀ  
ꢅꢀ&\FOHVꢀ  
637ꢂꢅꢐꢄꢊꢀ  
Figure 25 Clock Suspension During Burst Read CAS Latency = 3  
Data Sheet  
42  
Rev. 1.30, 2006-02  
10072003-13LE-FGQQ  
HYB39S256[40/80/16]0D[C/T](L)  
256-MBit Synchronous DRAM  
Timing Diagrams  
%XUVWꢀ/HQJWKꢀ ꢀꢈꢌꢀ&$6ꢀ/DWHQF\ꢀ ꢀꢉꢀ  
7ꢂꢀ 7ꢄꢀ 7ꢉꢀ 7ꢅꢀ 7ꢈꢀ 7ꢊꢀ 7ꢋꢀ 7ꢆꢀ 7ꢇꢀ 7ꢐꢀ 7ꢄꢂꢀ 7ꢄꢄꢀ 7ꢄꢉꢀ 7ꢄꢅꢀ 7ꢄꢈꢀ 7ꢄꢊꢀ 7ꢄꢋꢀ 7ꢄꢆꢀ 7ꢄꢇꢀ 7ꢄꢐꢀ 7ꢉꢂꢀ 7ꢉꢄꢀ 7ꢉꢉꢀ  
&/.ꢁ  
Wꢀ&.ꢉꢀ  
&.(ꢁ  
&6ꢁ  
5$6ꢁ  
&$6ꢁ  
:(ꢁ  
%6ꢁ  
$3ꢁ  
5$[ꢀ  
$GGUꢇꢁ  
'40ꢁ  
'4ꢁ  
5$[ꢀ  
&$[ꢀ  
+Lꢏ=ꢀ  
'$[ꢂꢀ  
'$[ꢄꢀ  
'$[ꢉꢀ  
'$[ꢅꢀ  
$FWLYDWHꢀ  
&ORFNꢀ  
&ORFNꢀ  
&ORFNꢀ  
&RPPDQGꢀ  
%DQNꢀ$ꢀ  
6XVSHQGꢀ  
ꢄꢀ&\FOHꢀ  
6XVSHQGꢀ  
ꢉꢀ&\FOHVꢀ  
6XVSHQGꢀ  
ꢅꢀ&\FOHVꢀ  
:ULWHꢀ  
&RPPDQGꢀ  
%DQNꢀ$ꢀ  
637ꢂꢅꢐꢄꢋꢀ  
Figure 26 Clock Suspension During Burst Write CAS Latency = 2  
Data Sheet  
43  
Rev. 1.30, 2006-02  
10072003-13LE-FGQQ  
HYB39S256[40/80/16]0D[C/T](L)  
256-MBit Synchronous DRAM  
Timing Diagrams  
%XUVWꢀ/HQJWKꢀ ꢀꢈꢌꢀ&$6ꢀ/DWHQF\ꢀ ꢀꢅꢀ  
7ꢂꢀ 7ꢄꢀ 7ꢉꢀ 7ꢅꢀ 7ꢈꢀ 7ꢊꢀ 7ꢋꢀ 7ꢆꢀ 7ꢇꢀ 7ꢐꢀ 7ꢄꢂꢀ 7ꢄꢄꢀ 7ꢄꢉꢀ 7ꢄꢅꢀ 7ꢄꢈꢀ 7ꢄꢊꢀ 7ꢄꢋꢀ 7ꢄꢆꢀ 7ꢄꢇꢀ 7ꢄꢐꢀ 7ꢉꢂꢀ 7ꢉꢄꢀ 7ꢉꢉꢀ  
&/.ꢁ  
Wꢀ&.ꢅꢀ  
&.(ꢁ  
&6ꢁ  
5$6ꢁ  
&$6ꢁ  
:(ꢁ  
%$ꢁ  
$ꢌꢍ$3ꢁ  
$GGUꢇꢁ  
'40[ꢁ  
'4ꢁ  
5$[ꢀ  
5$[ꢀ  
&$[ꢀ  
+Lꢏ=ꢀ  
'$[ꢂꢀ  
'$[ꢄꢀ  
'$[ꢉꢀ  
'$[ꢅꢀ  
$FWLYDWHꢀ  
&RPPDQGꢀ  
%DQNꢀ$ꢀ  
&ORFNꢀ  
&ORFNꢀ  
&ORFNꢀ  
6XVSHQGꢀ  
ꢄꢀ&\FOHꢀ  
6XVSHQGꢀ  
ꢉꢀ&\FOHVꢀ  
6XVSHQGꢀ  
ꢅꢀ&\FOHVꢀ  
:ULWHꢀ  
&RPPDQGꢀ  
%DQNꢀ$ꢀ  
637ꢂꢅꢐꢄꢆꢀ  
Figure 27 Clock Suspension During Burst Write CAS Latency = 3  
Data Sheet  
44  
Rev. 1.30, 2006-02  
10072003-13LE-FGQQ  
HYB39S256[40/80/16]0D[C/T](L)  
256-MBit Synchronous DRAM  
Timing Diagrams  
%XUVWꢀ/HQJWKꢀ ꢀꢈꢌꢀ&$6ꢀ/DWHQF\ꢀ ꢀꢉꢀ  
7ꢂꢀ 7ꢄꢀ 7ꢉꢀ 7ꢅꢀ 7ꢈꢀ 7ꢊꢀ 7ꢋꢀ 7ꢆꢀ 7ꢇꢀ 7ꢐꢀ 7ꢄꢂꢀ 7ꢄꢄꢀ 7ꢄꢉꢀ 7ꢄꢅꢀ 7ꢄꢈꢀ 7ꢄꢊꢀ 7ꢄꢋꢀ 7ꢄꢆꢀ 7ꢄꢇꢀ 7ꢄꢐꢀ 7ꢉꢂꢀ 7ꢉꢄꢀ 7ꢉꢉꢀ  
&/.ꢁ  
Wꢀ&.6ꢀ  
Wꢀ&.6ꢀ  
Wꢀ&.ꢉꢀ  
&.(ꢁ  
&6ꢁ  
5$6ꢁ  
&$6ꢁ  
:(ꢁ  
%6ꢁ  
$3ꢁ  
5$[ꢀ  
$GGUꢇꢁ  
'40ꢁ  
5$[ꢀ  
&$[ꢀ  
Wꢀ+=ꢀ  
+Lꢏ=ꢀ  
'4ꢁ  
$[ꢂꢀ $[ꢄꢀ  
$[ꢉꢀ  
$[ꢅꢀ  
$FWLYDWHꢀ  
&RPPDQGꢀ  
%DQNꢀ$ꢀ  
$FWLYHꢀ  
5HDGꢀ  
&RPPDQGꢀ  
%DQNꢀ$ꢀ  
&ORFNꢀ0DVNꢀ  
6WDUWꢀ  
&ORFNꢀ0DVNꢀ  
(QGꢀ  
3UHFKDUJHꢀ  
&RPPDQGꢀ  
%DQNꢀ$ꢀ  
3UHFKDUJHꢀ  
6WDQGE\ꢀ  
$Q\ꢀ  
6WDQGE\ꢀ  
&RPPDQGꢀ  
&ORFNꢀ6XVSHQGꢀ  
0RGHꢀ(QWU\ꢀ  
&ORFNꢀ6XVSHQGꢀ  
0RGHꢀ([LWꢀ  
3RZHUꢀ'RZQꢀ  
0RGHꢀ(QWU\ꢀ  
3RZHUꢀ'RZQꢀ  
0RGHꢀ([LWꢀ  
637ꢂꢅꢐꢄꢇꢀ  
Figure 28 Power Down Mode and Clock Suspend  
Data Sheet  
45  
Rev. 1.30, 2006-02  
10072003-13LE-FGQQ  
HYB39S256[40/80/16]0D[C/T](L)  
256-MBit Synchronous DRAM  
Timing Diagrams  
7ꢂꢀ 7ꢄꢀ 7ꢉꢀ 7ꢅꢀ 7ꢈꢀ 7ꢊꢀ 7ꢋꢀ 7ꢆꢀ 7ꢇꢀ 7ꢐꢀ 7ꢄꢂꢀ 7ꢄꢄꢀ 7ꢄꢉꢀ 7ꢄꢅꢀ 7ꢄꢈꢀ 7ꢄꢊꢀ 7ꢄꢋꢀ 7ꢄꢆꢀ 7ꢄꢇꢀ 7ꢄꢐꢀ 7ꢉꢂꢀ 7ꢉꢄꢀ 7ꢉꢉꢀ  
&/.ꢁ  
&.(ꢁ  
Wꢀ&.6ꢀ  
Wꢀ&.6ꢀ  
&6ꢁ  
5$6ꢁ  
&$6ꢁ  
:(ꢁ  
%6ꢁ  
$3ꢁ  
$GGUꢇꢁ  
Wꢀ65(;ꢀ  
Wꢀ5&ꢀ  
'40ꢁ  
'4ꢁ  
+Lꢏ=ꢀ  
$OOꢀ%DQNVꢀ  
PXVWꢀEHꢀLGOHꢀ  
6HOIꢀ5HIUHVKꢀ  
(QWU\ꢀ  
%HJLQꢀ6HOIꢀ5HIUHVKꢀ  
([LWꢀ&RPPDQGꢀ  
$Q\ꢀ  
&RPPDQGꢀ  
6HOIꢀ5HIUHVKꢀ([LWꢀ  
&RPPDQGꢀLVVXHGꢀ  
6HOIꢀ5HIUHVKꢀ  
([LWꢀ  
637ꢂꢅꢐꢄꢐꢀ  
Figure 29 Self Refresh (Entry and Exit)  
Data Sheet  
46  
Rev. 1.30, 2006-02  
10072003-13LE-FGQQ  
HYB39S256[40/80/16]0D[C/T](L)  
256-MBit Synchronous DRAM  
Timing Diagrams  
%XUVWꢀ/HQJWKꢀ ꢀꢈꢌꢀ&$6ꢀ/DWHQF\ꢀ ꢀꢉꢀ  
7ꢂꢀ 7ꢄꢀ 7ꢉꢀ 7ꢅꢀ 7ꢈꢀ 7ꢊꢀ 7ꢋꢀ 7ꢆꢀ 7ꢇꢀ 7ꢐꢀ 7ꢄꢂꢀ 7ꢄꢄꢀ 7ꢄꢉꢀ 7ꢄꢅꢀ 7ꢄꢈꢀ 7ꢄꢊꢀ 7ꢄꢋꢀ 7ꢄꢆꢀ 7ꢄꢇꢀ 7ꢄꢐꢀ 7ꢉꢂꢀ 7ꢉꢄꢀ 7ꢉꢉꢀ  
&/.ꢁ  
Wꢀ&.ꢉꢀ  
&.(ꢁ  
&6ꢁ  
5$6ꢁ  
&$6ꢁ  
:(ꢁ  
%6ꢁ  
$3ꢁ  
5$[ꢀ  
$GGUꢇꢁ  
5$[ꢀ  
&$[ꢀ  
Wꢀ5&ꢀ  
Wꢀ5&ꢀ  
Wꢀ53ꢀ  
ꢑ0LQLPXPꢀ,QWHUYDOꢒꢀ  
'40ꢁ  
'4ꢁ  
+Lꢏ=ꢀ  
$[ꢂꢀ $[ꢄꢀ $[ꢉꢀ $[ꢅꢀ  
3UHFKDUJHꢀ $XWRꢀ5HIUHVKꢀ  
$XWRꢀ5HIUHVKꢀ  
&RPPDQGꢀ  
$FWLYDWHꢀ  
&RPPDQGꢀ  
%DQNꢀ$ꢀ  
5HDGꢀ  
&RPPDQGꢀ  
%DQNꢀ$ꢀ  
&RPPDQGꢀ  
$OOꢀ%DQNVꢀ  
&RPPDQGꢀ  
637ꢂꢅꢐꢉꢂꢀ  
Figure 30 Auto Refresh (CBR)  
Data Sheet  
47  
Rev. 1.30, 2006-02  
10072003-13LE-FGQQ  
HYB39S256[40/80/16]0D[C/T](L)  
256-MBit Synchronous DRAM  
Timing Diagrams  
%XUVWꢀ/HQJWKꢀ ꢀꢈꢌꢀ&$6ꢀ/DWHQF\ꢀ ꢀꢉꢀ  
7ꢂꢀ 7ꢄꢀ 7ꢉꢀ 7ꢅꢀ 7ꢈꢀ 7ꢊꢀ 7ꢋꢀ 7ꢆꢀ 7ꢇꢀ 7ꢐꢀ 7ꢄꢂꢀ 7ꢄꢄꢀ 7ꢄꢉꢀ 7ꢄꢅꢀ 7ꢄꢈꢀ 7ꢄꢊꢀ 7ꢄꢋꢀ 7ꢄꢆꢀ 7ꢄꢇꢀ 7ꢄꢐꢀ 7ꢉꢂꢀ 7ꢉꢄꢀ 7ꢉꢉꢀ  
&/.ꢁ  
Wꢀ&.ꢉꢀ  
&.(ꢁ  
&6ꢁ  
5$6ꢁ  
&$6ꢁ  
:(ꢁ  
%6ꢁ  
$3ꢁ  
5$Zꢀ  
5$Zꢀ  
5$]ꢀ  
5$]ꢀ  
$GGUꢇꢁ  
'40ꢁ  
'4ꢁ  
&$Zꢀ  
&$[ꢀ  
&$\ꢀ  
&$]ꢀ  
+Lꢀ=ꢀ  
$Zꢂꢀ $Zꢄꢀ $Zꢉꢀ $Zꢅꢀ $[ꢂꢀ $[ꢄꢀ $\ꢂꢀ $\ꢄꢀ $\ꢉꢀ $\ꢅꢀ  
$]ꢂꢀ $]ꢄꢀ $]ꢉꢀ $]ꢅꢀ  
$FWLYDWHꢀ  
5HDGꢀ  
5HDGꢀ  
&RPPDQGꢀ  
%DQNꢀ$ꢀ  
5HDGꢀ  
&RPPDQGꢀ  
%DQNꢀ$ꢀ  
3UHFKDUJHꢀ  
$FWLYDWHꢀ  
5HDGꢀ  
&RPPDQGꢀ &RPPDQGꢀ  
&RPPDQGꢀ &RPPDQGꢀ &RPPDQGꢀ  
%DQNꢀ$ꢀ  
%DQNꢀ$ꢀ  
%DQNꢀ$ꢀ  
%DQNꢀ$ꢀ  
%DQNꢀ$ꢀ  
637ꢂꢅꢐꢉꢄꢀ  
Figure 31 CAS Latency = 2  
Data Sheet  
48  
Rev. 1.30, 2006-02  
10072003-13LE-FGQQ  
HYB39S256[40/80/16]0D[C/T](L)  
256-MBit Synchronous DRAM  
Timing Diagrams  
%XUVWꢀ/HQJWKꢀ ꢀꢈꢌꢀ&$6ꢀ/DWHQF\ꢀ ꢀꢅꢀ  
7ꢂꢀ 7ꢄꢀ 7ꢉꢀ 7ꢅꢀ 7ꢈꢀ 7ꢊꢀ 7ꢋꢀ 7ꢆꢀ 7ꢇꢀ 7ꢐꢀ 7ꢄꢂꢀ 7ꢄꢄꢀ 7ꢄꢉꢀ 7ꢄꢅꢀ 7ꢄꢈꢀ 7ꢄꢊꢀ 7ꢄꢋꢀ 7ꢄꢆꢀ 7ꢄꢇꢀ 7ꢄꢐꢀ 7ꢉꢂꢀ 7ꢉꢄꢀ 7ꢉꢉꢀ  
&/.ꢁ  
Wꢀ&.ꢅꢀ  
&.(ꢁ  
&6ꢁ  
5$6ꢁ  
&$6ꢁ  
:(ꢁ  
%6ꢁ  
$3ꢁ  
5$Zꢀ  
5$Zꢀ  
5$]ꢀ  
5$]ꢀ  
$GGUꢇꢁ  
'40ꢁ  
&$Zꢀ  
&$[ꢀ  
&$\ꢀ  
&$]ꢀ  
+Lꢀ=ꢀ  
'4ꢁ  
$Zꢂꢀ $Zꢄꢀ $Zꢉꢀ $Zꢅꢀ $[ꢂꢀ $[ꢄꢀ $\ꢂꢀ $\ꢄꢀ $\ꢉꢀ $\ꢅꢀ  
$FWLYDWHꢀ  
&RPPDQGꢀ  
%DQNꢀ$ꢀ  
5HDGꢀ  
&RPPDQGꢀ  
%DQNꢀ$ꢀ  
5HDGꢀ  
5HDGꢀ  
3UHFKDUJHꢀ  
&RPPDQGꢀ  
%DQNꢀ$ꢀ  
$FWLYDWHꢀ  
&RPPDQGꢀ  
%DQNꢀ$ꢀ  
5HDGꢀ  
&RPPDQGꢀ &RPPDQGꢀ  
&RPPDQGꢀ  
%DQNꢀ$ꢀ  
637ꢂꢅꢐꢉꢉꢀ  
%DQNꢀ$ꢀ  
%DQNꢀ$ꢀ  
Figure 32 CAS Latency = 3  
Data Sheet  
49  
Rev. 1.30, 2006-02  
10072003-13LE-FGQQ  
HYB39S256[40/80/16]0D[C/T](L)  
256-MBit Synchronous DRAM  
Timing Diagrams  
%XUVWꢀ/HQJWKꢀ ꢀꢈꢌꢀ&$6ꢀ/DWHQF\ꢀ ꢀꢉꢀ  
7ꢂꢀ 7ꢄꢀ 7ꢉꢀ 7ꢅꢀ 7ꢈꢀ 7ꢊꢀ 7ꢋꢀ 7ꢆꢀ 7ꢇꢀ 7ꢐꢀ 7ꢄꢂꢀ 7ꢄꢄꢀ 7ꢄꢉꢀ 7ꢄꢅꢀ 7ꢄꢈꢀ 7ꢄꢊꢀ 7ꢄꢋꢀ 7ꢄꢆꢀ 7ꢄꢇꢀ 7ꢄꢐꢀ 7ꢉꢂꢀ 7ꢉꢄꢀ 7ꢉꢉꢀ  
&/.ꢁ  
Wꢀ&.ꢉꢀ  
&.(ꢁ  
&6ꢁ  
5$6ꢁ  
&$6ꢁ  
:(ꢁ  
%6ꢁ  
$3ꢁ  
5$Zꢀ  
5$Zꢀ  
5$]ꢀ  
5$]ꢀ  
$GGUꢇꢁ  
'40ꢁ  
'4ꢁ  
&$Zꢀ  
&$[ꢀ  
&$\ꢀ  
&$]ꢀ  
+Lꢀ=ꢀ  
'%Zꢂꢀ '%Zꢄꢀ '%Zꢉꢀ '%Zꢅꢀ '%[ꢂꢀ '%[ꢄꢀ '%\ꢂꢀ '%\ꢄꢀ '%\ꢉꢀ '%\ꢅꢀ  
'%]ꢂꢀ '%]ꢄꢀ '%]ꢉꢀ '%]ꢅꢀ  
5HDGꢀ  
$FWLYDWHꢀ  
:ULWHꢀ  
:ULWHꢀ  
&RPPDQGꢀ  
%DQNꢀ%ꢀ  
:ULWHꢀ  
&RPPDQGꢀ  
%DQNꢀ%ꢀ  
3UHFKDUJHꢀ  
$FWLYDWHꢀ  
&RPPDQGꢀ &RPPDQGꢀ  
&RPPDQGꢀ &RPPDQGꢀ &RPPDQGꢀ  
%DQNꢀ$ꢀ  
%DQNꢀ%ꢀ  
%DQNꢀ%ꢀ  
%DQNꢀ%ꢀ  
%DQNꢀ%ꢀ  
637ꢂꢅꢐꢉꢅꢀ  
Figure 33 CAS Latency = 2  
Data Sheet  
50  
Rev. 1.30, 2006-02  
10072003-13LE-FGQQ  
HYB39S256[40/80/16]0D[C/T](L)  
256-MBit Synchronous DRAM  
Timing Diagrams  
%XUVWꢀ/HQJWKꢀ ꢀꢈꢌꢀ&$6ꢀ/DWHQF\ꢀ ꢀꢅꢀ  
7ꢂꢀ 7ꢄꢀ 7ꢉꢀ 7ꢅꢀ 7ꢈꢀ 7ꢊꢀ 7ꢋꢀ 7ꢆꢀ 7ꢇꢀ 7ꢐꢀ 7ꢄꢂꢀ 7ꢄꢄꢀ 7ꢄꢉꢀ 7ꢄꢅꢀ 7ꢄꢈꢀ 7ꢄꢊꢀ 7ꢄꢋꢀ 7ꢄꢆꢀ 7ꢄꢇꢀ 7ꢄꢐꢀ 7ꢉꢂꢀ 7ꢉꢄꢀ 7ꢉꢉꢀ  
&/.ꢁ  
Wꢀ&.ꢅꢀ  
&.(ꢁ  
&6ꢁ  
5$6ꢁ  
&$6ꢁ  
:(ꢁ  
%6ꢁ  
$3ꢁ  
5%]ꢀ  
5%]ꢀ  
5%]ꢀ  
5%]ꢀ  
$GGUꢇꢁ  
'40ꢁ  
'4ꢁ  
&%]ꢀ  
&%[ꢀ  
&%\ꢀ  
&%]ꢀ  
+Lꢀ=ꢀ  
'%Zꢂꢀ '%Zꢄꢀ '%Zꢉꢀ '%Zꢅꢀ '%[ꢂꢀ '%[ꢄꢀ '%\ꢂꢀ '%\ꢄꢀ '%\ꢉꢀ '%\ꢅꢀ  
'%]ꢂꢀ '%]ꢄꢀ  
$FWLYDWHꢀ  
&RPPDQGꢀ  
%DQNꢀ%ꢀ  
:ULWHꢀ  
&RPPDQGꢀ  
%DQNꢀ%ꢀ  
:ULWHꢀ  
&RPPDQGꢀ  
%DQNꢀ%ꢀ  
:ULWHꢀ  
&RPPDQGꢀ  
%DQNꢀ%ꢀ  
3UHFKDUJHꢀ  
&RPPDQGꢀ  
%DQNꢀ%ꢀ  
$FWLYDWHꢀ  
&RPPDQGꢀ  
%DQNꢀ%ꢀ  
:ULWHꢀ  
&RPPDQGꢀ  
%DQNꢀ%ꢀ637ꢂꢅꢐꢉꢈꢀ  
Figure 34 CAS Latency = 3  
Data Sheet  
51  
Rev. 1.30, 2006-02  
10072003-13LE-FGQQ  
HYB39S256[40/80/16]0D[C/T](L)  
256-MBit Synchronous DRAM  
Timing Diagrams  
%XUVWꢀ/HQJWKꢀ ꢀꢇꢌꢀ&$6ꢀ/DWHQF\ꢀ ꢀꢉꢀ  
7ꢂꢀ 7ꢄꢀ 7ꢉꢀ 7ꢅꢀ 7ꢈꢀ 7ꢊꢀ 7ꢋꢀ 7ꢆꢀ 7ꢇꢀ 7ꢐꢀ 7ꢄꢂꢀ 7ꢄꢄꢀ 7ꢄꢉꢀ 7ꢄꢅꢀ 7ꢄꢈꢀ 7ꢄꢊꢀ 7ꢄꢋꢀ 7ꢄꢆꢀ 7ꢄꢇꢀ 7ꢄꢐꢀ 7ꢉꢂꢀ 7ꢉꢄꢀ 7ꢉꢉꢀ  
&/.ꢁ  
Wꢀ&.ꢉꢀ  
&.(ꢁ +LJKꢀ  
&6ꢁ  
5$6ꢁ  
&$6ꢁ  
:(ꢁ  
%6ꢁ  
$3ꢁ  
5%[ꢀ  
5$[ꢀ  
5$[ꢀ  
5%\ꢀ  
5%\ꢀ  
$GGUꢇꢁ  
5%[ꢀ  
&%[ꢀ  
&$[ꢀ  
&%\ꢀ  
Wꢀ5&'ꢀ  
Wꢀ53ꢀ  
'40ꢁ  
'4ꢁ  
Wꢀ$&ꢉꢀ  
+Lꢏ=ꢀ  
%[ꢂꢀ %[ꢄꢀ %[ꢉꢀ %[ꢅꢀ %[ꢈꢀ %[ꢊꢀ %[ꢋꢀ %[ꢆꢀ $[ꢂꢀ $[ꢄꢀ $[ꢉꢀ $[ꢅꢀ $[ꢈꢀ $[ꢊꢀ $[ꢋꢀ $[ꢆꢀ  
%\ꢂꢀ %\ꢄꢀ  
$FWLYDWHꢀ  
5HDGꢀ  
$FWLYDWHꢀ  
&RPPDQGꢀ  
%DQNꢀ$ꢀ  
3UHFKDUJHꢀ $FWLYDWHꢀ  
&RPPDQGꢀ &RPPDQGꢀ  
5HDGꢀ  
&RPPDQGꢀ  
%DQNꢀ%ꢀ  
&RPPDQGꢀ &RPPDQGꢀ  
%DQNꢀ%ꢀ  
%DQNꢀ%ꢀ  
%DQNꢀ%ꢀ  
%DQNꢀ%ꢀ  
5HDGꢀ  
&RPPDQGꢀ  
%DQNꢀ$ꢀ  
637ꢂꢅꢐꢉꢊꢀ  
Figure 35 CAS Latency = 2  
Data Sheet  
52  
Rev. 1.30, 2006-02  
10072003-13LE-FGQQ  
HYB39S256[40/80/16]0D[C/T](L)  
256-MBit Synchronous DRAM  
Timing Diagrams  
%XUVWꢀ/HQJWKꢀ ꢀꢇꢌꢀ&$6ꢀ/DWHQF\ꢀ ꢀꢅꢀ  
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3UHFKDUJHꢀ  
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%DQNꢀ$ꢀ  
637ꢂꢅꢐꢉꢋꢀ  
Figure 36 CAS Latency = 3  
Data Sheet  
53  
Rev. 1.30, 2006-02  
10072003-13LE-FGQQ  
HYB39S256[40/80/16]0D[C/T](L)  
256-MBit Synchronous DRAM  
Timing Diagrams  
%XUVWꢀ/HQJWKꢀ ꢀꢇꢌꢀ&$6ꢀ/DWHQF\ꢀ ꢀꢉꢀ  
7ꢂꢀ 7ꢄꢀ 7ꢉꢀ 7ꢅꢀ 7ꢈꢀ 7ꢊꢀ 7ꢋꢀ 7ꢆꢀ 7ꢇꢀ 7ꢐꢀ 7ꢄꢂꢀ 7ꢄꢄꢀ 7ꢄꢉꢀ 7ꢄꢅꢀ 7ꢄꢈꢀ 7ꢄꢊꢀ 7ꢄꢋꢀ 7ꢄꢆꢀ 7ꢄꢇꢀ 7ꢄꢐꢀ 7ꢉꢂꢀ 7ꢉꢄꢀ 7ꢉꢉꢀ  
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637ꢂꢅꢐꢉꢆꢀ  
Figure 37 CAS Latency = 2  
Data Sheet  
54  
Rev. 1.30, 2006-02  
10072003-13LE-FGQQ  
HYB39S256[40/80/16]0D[C/T](L)  
256-MBit Synchronous DRAM  
Timing Diagrams  
%XUVWꢀ/HQJWKꢀ ꢀꢇꢌꢀ&$6ꢀ/DWHQF\ꢀ ꢀꢅꢀ  
7ꢂꢀ 7ꢄꢀ 7ꢉꢀ 7ꢅꢀ 7ꢈꢀ 7ꢊꢀ 7ꢋꢀ 7ꢆꢀ 7ꢇꢀ 7ꢐꢀ 7ꢄꢂꢀ 7ꢄꢄꢀ 7ꢄꢉꢀ 7ꢄꢅꢀ 7ꢄꢈꢀ 7ꢄꢊꢀ 7ꢄꢋꢀ 7ꢄꢆꢀ 7ꢄꢇꢀ 7ꢄꢐꢀ 7ꢉꢂꢀ 7ꢉꢄꢀ 7ꢉꢉꢀ  
&/.ꢁ  
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637ꢂꢅꢐꢉꢇꢀ  
Figure 38 CAS Latency = 3  
Data Sheet  
55  
Rev. 1.30, 2006-02  
10072003-13LE-FGQQ  
HYB39S256[40/80/16]0D[C/T](L)  
256-MBit Synchronous DRAM  
Timing Diagrams  
%XUVWꢀ/HQJWKꢀ ꢀꢇꢀRUꢀ)XOOꢀ3DJHꢌꢀ&$6ꢀ/DWHQF\ꢀ ꢀꢉꢀ  
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:ULWHꢀ'DWDꢀLVꢀPDVNHGꢃꢀ  
637ꢂꢅꢐꢅꢅꢀ  
Figure 39 CAS Latency = 2  
Data Sheet  
56  
Rev. 1.30, 2006-02  
10072003-13LE-FGQQ  
HYB39S256[40/80/16]0D[C/T](L)  
256-MBit Synchronous DRAM  
Timing Diagrams  
"URST ,ENGTH ꢓ &ULL 0AGEꢊ #!3 ,ATENC ꢓ ꢃ  
4ꢀ  
4ꢂ  
4ꢃ  
4ꢄ  
4ꢁ  
4ꢅ  
4ꢆ  
4ꢇ  
4ꢈ  
4ꢉ 4ꢂꢀ 4ꢂꢂ 4ꢂꢃ 4ꢂꢄ 4ꢂꢁ 4ꢂꢅ 4ꢂꢆ 4ꢂꢇ 4ꢂꢈ 4ꢂꢉ 4ꢃꢀ 4ꢃꢂ 4ꢃꢃ  
#,+  
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#+%  
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!CTIVATE  
#OMMAND #OMMAND #OMMAND  
"ANK ! "ANK ! "ANK "  
2EAD  
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2EAD  
#OMMAND  
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"URST 3TOP 0RECHARGE  
#OMMAND #OMMAND  
"ANK "  
4HE BURST COUNTER WRAPS  
FROM THE HIGHEST ORDER  
PAGE ADDRESS BACK TO ZERO  
DURING THIS TIME INTERVALꢌ  
&ULL 0AGE BURST OPERATION DOES NOT  
!CTIVATE  
#OMMAND  
"ANK "  
TERMINATE WHEN THE BURST LENGTH IS SATISFIEDꢒ  
THE BURST COUNTER INCREMENTS AND CONTINUES  
BURSTING BEGINNING WITH THE STARTING ADDRESSꢌ  
304ꢀꢄꢉꢃꢉ  
Figure 40 Full Page Burst Read, CAS Latency = 2  
Data Sheet  
57  
Rev. 1.30, 2006-02  
10072003-13LE-FGQQ  
$[ꢀ $[ꢀꢎꢀ ꢀ $[ꢀꢎꢀꢉꢀ $[ꢀꢏ  
                                                                                                
ꢉꢀ  
$[ꢀꢏꢀ ꢀ $[ꢀ $[ꢀꢎꢀ ꢀ %[ꢀ %[ꢀꢎꢀ ꢀ %[ꢀꢎꢀꢉꢀ %[ꢀꢎꢀꢅꢀ %[  
                                                                                                                                                     
ꢎꢀ ꢀ %[ꢀꢎꢀꢊꢀ  
HYB39S256[40/80/16]0D[C/T](L)  
256-MBit Synchronous DRAM  
Timing Diagrams  
%XUVWꢀ/HQJWKꢀ ꢀ)XOOꢀ3DJHꢌꢀ&$6ꢀ/DWHQF\ꢀ ꢀꢅꢀ  
7ꢂꢀ 7ꢄꢀ 7ꢉꢀ 7ꢅꢀ 7ꢈꢀ 7ꢊꢀ 7ꢋꢀ 7ꢆꢀ 7ꢇꢀ 7ꢐꢀ 7ꢄꢂꢀ 7ꢄꢄꢀ 7ꢄꢉꢀ 7ꢄꢅꢀ 7ꢄꢈꢀ 7ꢄꢊꢀ 7ꢄꢋꢀ 7ꢄꢆꢀ 7ꢄꢇꢀ 7ꢄꢐꢀ 7ꢉꢂꢀ 7ꢉꢄꢀ 7ꢉꢉꢀ  
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SDJHꢀDGGUHVVꢀEDFNꢀWRꢀ]HURꢀ  
GXULQJꢀWKLVꢀWLPHꢀLQWHUYDOꢃꢀ  
WHUPLQDWHꢀZKHQꢀWKHꢀEXUVWꢀOHQJWKꢀLVꢀVDWLVILHGꢓꢀ  
WKHꢀEXUVWꢀFRXQWHUꢀLQFUHPHQWVꢀDQGꢀFRQWLQXHVꢀ  
EXUVWLQJꢀEHJLQQLQJꢀZLWKꢀWKHꢀVWDUWLQJꢀDGGUHVVꢃꢀ  
637ꢂꢅꢐꢅꢂꢀ  
Figure 41 Full Page Burst Write, CAS Latency = 3  
Data Sheet  
58  
Rev. 1.30, 2006-02  
10072003-13LE-FGQQ  
HYB39S256[40/80/16]0D[C/T](L)  
256-MBit Synchronous DRAM  
Package Outlines  
6
Package Outlines  
ꢅ
ꢂꢅ  
ꢂꢅ  
ꢃꢏ  
ꢀꢌꢂꢄ  
ꢂꢀꢌꢂꢆ  
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ꢃꢆ X ꢀꢌꢈ  
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ꢃꢃꢌꢃꢃ  
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)NDEX -ARKING  
ꢂꢏ $OES NOT INCLUDE PLASTIC OR METAL PROTRUSION OF ꢀꢌꢂꢅ MAX PER SIDE  
ꢃꢏ $OES NOT INCLUDE PLASTIC PROTRUSION OF ꢀꢌꢃꢅ MAX PER SIDE  
ꢄꢏ $OES NOT INCLUDE DAMBAR PROTRUSION OF ꢀꢌꢂꢄ MAX PER SIDE  
Figure 42 Package Outline P-TSOPII-54-1 (top view)  
Data Sheet  
59  
Rev. 1.30, 2006-02  
10072003-13LE-FGQQ  
HYB39S256[40/80/16]0D[C/T](L)  
256-MBit Synchronous DRAM  
Package Outlines  
ꢂꢃ  
"
ꢂꢃ X ꢀꢌꢈ ꢓ ꢉꢌꢆ  
ꢀꢌꢈ  
ꢀꢌꢂꢈ -!8ꢌ  
!
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ꢄꢏ  
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#
ꢀꢌꢂ  
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-
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#
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-
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›ꢀꢌꢀꢅ  
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ꢁꢌꢃꢅ  
!ꢂ )NDEX -ARKꢃꢏ  
ꢂꢏ !ꢂ MARKING BALLSIDE  
ꢃꢏ !ꢂ MARKING CHIPSIDEꢌ 0OLISH GRINDINGꢌ  
ꢄꢏ .O BALL AT THIS POSITION  
'0!ꢀꢂꢂꢂꢅ  
Figure 43 Package Outline P-TFBGA-54-8  
Data Sheet  
60  
Rev. 1.30, 2006-02  
10072003-13LE-FGQQ  
w w w . i n f i n e o n . c o m  
Published by Infineon Technologies AG  

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SI9130_11

 Pin-Programmable Dual Controller - Portable PCs

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SI9137

 Multi-Output, Sequence Selectable Power-Supply Controller for Mobile Applications

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SI9137DB

 Multi-Output, Sequence Selectable Power-Supply Controller for Mobile Applications

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SI9137LG

 Multi-Output, Sequence Selectable Power-Supply Controller for Mobile Applications

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SI9122E

 500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification Drivers

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