HYB39S256800DT-7 [INFINEON]
256 MBit Synchronous DRAM; 256兆比特的同步DRAM
| 型号： | HYB39S256800DT-7 |
| 厂家： | 
Infineon |
| 描述： | 256 MBit Synchronous DRAM |
| 文件： | 总22页 (文件大小：545K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HYB39S256400/800/160DT(L)/DC(L)
256MBit Synchronous DRAM
256 MBit Synchronous DRAM
•
High Performance:
•
•
•
•
•
•
Data Mask for Read / Write control (x4, x8)
Data Mask for byte control (x16)
-6
-7
-7.5
-8
Units
Auto Refresh (CBR) and Self Refresh
Power Down and Clock Suspend Mode
8192 refresh cycles / 64 ms (7,8 µs)
Random Column Address every CLK
( 1-N Rule)
fCK
166
6
143
7
133
7.5
5.4
10
6
125
8
MHz
ns
tCK3
tAC3
tCK2
tAC2
5
5.4
7.5
5.4
6
ns
7.5
5.4
10
6
ns
•
•
•
Single 3.3V +/- 0.3V Power Supply
LVTTL Interface versions
ns
Plastic Packages:
P-TSOPII-54 400mil width (x4, x8, x16)
•
•
•
•
•
Fully Synchronous to Positive Clock Edge
0 to 70 °C operating temperature
Four Banks controlled by BA0 & BA1
Programmable CAS Latency: 2 & 3
•
•
Chipsize Packages:
54 ball TFBGA (12 mm x 8 mm)
-6 parts for PC166 3-3-3 operation
-7 parts for PC133 2-2-2 operation
-7.5 parts for PC133 3-3-3 operation
-8 parts for PC100 2-2-2 operation
Programmable Wrap Sequence: Sequential
or Interleave
•
•
•
Programmable Burst Length:
1, 2, 4, 8 and full page
Multiple Burst Read with Single Write
Operation
Automatic and Controlled Precharge
Command
The HYB39S256400/800/160DT(L) are four bank Synchronous DRAM’s organized as 4 banks x
16MBit x4, 4 banks x 8MBit x8 and 4 banks x 4Mbit x16 respectively. These synchronous devices
achieve high speed data transfer rates for CAS-latencies by employing a chip architecture that
prefetches multiple bits and then synchronizes the output data to a system clock. The chip is
fabricated with INFINEON’s advanced 0.14 µm 256MBit DRAM process technology.
The device is designed to comply with all industry standards set for synchronous DRAM products,
both electrically and mechanically. All of the control, address, data input and output circuits are
synchronized with the positive edge of an externally supplied clock.
Operating the four memory banks in an interleave fashion allows random access operation to occur
at a higher rate than is possible with standard DRAMs. A sequential and gapless data rate is
possible depending on burst length, CAS latency and speed grade of the device.
Auto Refresh (CBR) and Self Refresh operation are supported. These devices operate with a single
3.3V +/- 0.3V power supply. All 256Mbit components are available in TSOPII-54 and TFBGA-54
packages.
INFINEON Technologies
1
2002-04-23
HYB39S256400/800/160DT(L)/DC(L)
256MBit Synchronous DRAM
Ordering Information
Type
Speed Grade
Package
Description
HYB 39S256400DT-6
HYB 39S256400DT-7
HYB 39S256400DT-7.5
HYB 39S256400DT-8
HYB 39S256800DT-6
HYB 39S256800DT-7
HYB 39S256800DT-7.5
HYB 39S256800DT-8
HYB 39S256160DT-6
HYB 39S256160DT-7
HYB 39S256160DT-7.5
HYB 39S256160DT-8
HYB39S256800DTL-x
PC166-333-520
PC133-222-520
PC133-333-520
PC100-222-620
PC166-333-520
PC133-222-520
PC133-333-520
PC100-222-620
PC166-333-520
PC133-222-520
PC133-333-520
PC100-222-620
P-TSOP-54-2 (400mil)
P-TSOP-54-2 (400mil)
P-TSOP-54-2 (400mil)
P-TSOP-54-2 (400mil)
P-TSOP-54-2 (400mil)
P-TSOP-54-2 (400mil)
P-TSOP-54-2 (400mil)
P-TSOP-54-2 (400mil)
P-TSOP-54-2 (400mil)
P-TSOP-54-2 (400mil)
P-TSOP-54-2 (400mil)
P-TSOP-54-2 (400mil)
P-TSOP-54-2 (400mil)
166MHz 4B x 16M x 4 SDRAM
143MHz 4B x 16M x 4 SDRAM
133MHz 4B x 16M x 4 SDRAM
125MHz 4B x 16M x 4 SDRAM
166MHz 4B x 8M x 8 SDRAM
143MHz 4B x 8M x 8 SDRAM
133MHz 4B x 8M x 8 SDRAM
125MHz 4B x 8M x 8 SDRAM
166MHz 4B x 4M x 16 SDRAM
143MHz 4B x 4M x 16 SDRAM
133MHz 4B x 4M x 16 SDRAM
125MHz 4B x 4M x 16 SDRAM
4B x 8M x 8 SDRAM Low Power
Versions (on request)
HYB39S256160DTL-x
HYB39S256xx0DC(L)-x
P-TSOP-54-2 (400mil)
P-TFBGA-54
4B x 4M x 16 SDRAM Low Power
Versions (on request)
(on request)
Pin Description:
CLK
CKE
Clock Input
DQx
Data Input /Output
Data Mask
Clock Enable
DQM, LDQM, UDQM
CS
RAS
Chip Select
Row Address Strobe
Column Address Strobe
Write Enable
VDD
VSS
Power (+3.3V)
Ground
CAS
VDDQ
VSSQ
NC
Power for DQ’s (+ 3.3V)
Ground for DQ’s
not connected
WE
A0-A12
BA0, BA1
Address Inputs
Bank Select
INFINEON Technologies
2
2002-04-23
HYB39S256400/800/160DT(L)/DC(L)
256MBit Synchronous DRAM
Pinouts (TSOP-54)
16 M x 16
32 M x 8
64 M x 4
VDD
VDD
VDD
VSS
VSS
VSS
1
2
3
4
5
6
7
8
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
DQ0
VDDQ
DQ0
VDDQ
N.C.
VDDQ
N.C.
VSSQ
DQ7
VSSQ
DQ15
VSSQ
DQ1
DQ2
VSSQ
N.C.
DQ1
VSSQ
N.C.
DQ0
VSSQ
N.C.
DQ3
VDDQ
N.C.
DQ6
VDDQ
DQ14
DQ13
VDDQ
DQ3
DQ4
VDDQ
N.C.
DQ2
VDDQ
N.C.
N.C.
VDDQ
N.C.
N.C.
VSSQ
N.C.
DQ5
VSSQ
DQ12
DQ11
VSSQ
9
DQ5
DQ6
VSSQ
N.C.
DQ3
VSSQ
N.C.
DQ1
VSSQ
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
N.C.
DQ2
VDDQ
N.C.
DQ4
VDDQ
DQ10
DQ9
VDDQ
DQ8
VSS
DQ7
VDD
N.C.
VDD
N.C.
VDD
N.C.
VSS
N.C.
VSS
LDQM N.C.
WE
N.C.
WE
CAS
RAS
CS
N.C.
DQM
CLK
CKE
A12
A11
A9
A8
A7
A6
A5
N.C.
DQM
CLK
CKE
A12
A11
A9
A8
A7
A6
A5
N.C.
UDQM
CLK
CKE
A12
A11
A9
A8
A7
A6
A5
WE
CAS
RAS
CS
BA0
BA1
CAS
RAS
CS
BA0
BA1
BA0
BA1
A10/AP A10/AP A10/AP
A0
A1
A2
A3
VDD
A0
A1
A2
A3
VDD
A0
A1
A2
A3
VDD
A4
VSS
A4
VSS
A4
VSS
TSOPII-54 (400 mil x 875 mil, 0.8 mm pitch)
SPP04126
INFINEON Technologies
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2002-04-23
HYB39S256400/800/160DT(L)/DC(L)
256MBit Synchronous DRAM
Pinouts (TFBGA-54)
Pin Configuration for x16 devices:
1
2
3
7
8
9
VSS DQ15 VSSQ
DQ14 DQ13 VDDQ
DQ12 DQ11 VSSQ
DQ10 DQ9 VDDQ
A
B
C
D
E
F
VDDQ DQ0
VSSQ DQ2
VDDQ DQ4
VSSQ DQ6
VDD
DQ1
DQ3
DQ5
DQ8
NC
VSS
CKE
A9
VDD LDQM DQ7
UDQM CLK
CAS
BA0
A0
RAS
BA1
A1
WE
CS
A12
A8
A11
A7
G
H
J
A6
A10
VDD
VSS
A5
A4
A3
A2
Pin Configuration for x8 devices:
1
2
3
7
8
9
VSS
NC
NC
NC
NC
DQ7 VSSQ
DQ6 VDDQ
DQ5 VSSQ
DQ4 VDDQ
A
B
C
D
E
F
VDDQ DQ0
VSSQ DQ1
VDDQ DQ2
VSSQ DQ3
VDD
NC
NC
NC
NC
VSS
CKE
A9
VDD
CAS
BA0
A0
NC
RAS
BA1
A1
NC
DQM CLK
WE
CS
A12
A8
A11
A7
G
H
J
A6
A10
VDD
VSS
A5
A4
A3
A2
Pin Configuration for x4 devices:
1
2
3
7
8
9
VSS
NC
NC
NC
NC
NC
VSSQ
A
B
C
D
E
F
VDDQ
NC
VDD
NC
DQ3 VDDQ
NC VSSQ
DQ2 VDDQ
VSSQ DQ0
VDDQ NC
VSSQ DQ1
NC
NC
NC
VSS
CKE
A9
VDD
CAS
BA0
A0
NC
RAS
BA1
A1
NC
DQM CLK
WE
CS
G
H
J
A12
A8
A11
A7
A6
A10
VDD
VSS
A5
A4
A3
A2
INFINEON Technologies
4
2002-04-23
HYB39S256400/800/160DT(L)/DC(L)
256MBit Synchronous DRAM
Pinout for x4, x8 & x16 organised 256M-DRAMs
C o lum n A d d res ses
R ow A d d re sse s
A 0 - A 9 , A 11 , A P,
B A 0 , B A 1
A 0 - A 1 2 ,
B A 0 , B A 1
C olu m n A d d re ss
C o un ter
C olu m n A d d re ss
B u ffe r
R ow A d d re ss
R e fre sh C o u nte r
B u ffe r
R o w
D e co de r
R ow
D e co d e r
R o w
D e co de r
R ow
D eco d e r
M em ory
A rray
M e m o ry
A rray
M e m o ry
A rray
M e m o ry
A rray
B a n k 0
8 1 96
B a nk
81 9 2
x 2 0 48
x 4 B it
1
B a n k 2
8 1 9 2
B a nk
3
8 19 2
x 2 0 4 8
x 4 B it
x
20 4 8
x
20 4 8
B it
x
4
B it
x
4
In p ut B u ffe r
O u tp u t B uffe r
C o ntro l L og ic &
T im in g G en e rato r
D Q 0 - D Q 3
S P B 0 4 1 2 7 _2
Block Diagram for 64M x 4 SDRAM ( 13 / 11 / 2 addressing)
INFINEON Technologies
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2002-04-23
HYB39S256400/800/160DT(L)/DC(L)
256MBit Synchronous DRAM
Column Addresses
Row Addresses
A0 - A9, AP,
BA0, BA1
A0 - A12,
BA0, BA1
Column Address
Counter
Column Address
Buffer
Row Address
Refresh Counter
Buffer
Row
Decoder
Row
Decoder
Row
Decoder
Row
Decoder
Memory
Array
Memory
Array
Memory
Array
Memory
Array
Bank 0
Bank 1
Bank 2
Bank 3
8192
x 1024
x 8 Bit
8192
x 1024
x 8 Bit
8192
x 1024
x 8 Bit
8192
x 1024
x 8 Bit
Input Buffer Output Buffer
DQ0 - DQ7
Control Logic &
Timing Generator
SPB04128
Block Diagram for 32M x 8 SDRAM ( 13 / 10 / 2 addressing)
INFINEON Technologies
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2002-04-23
HYB39S256400/800/160DT(L)/DC(L)
256MBit Synchronous DRAM
Column Addresses
Row Addresses
A0 - A8, AP,
BA0, BA1
A0 - A12,
BA0, BA1
Column Address
Counter
Column Address
Buffer
Row Address
Refresh Counter
Buffer
Row
Decoder
Row
Decoder
Row
Decoder
Row
Decoder
Memory
Array
Memory
Array
Memory
Array
Memory
Array
Bank 0
Bank 1
Bank 2
Bank 3
8192 x 512
x 16 Bit
8192 x 512
x 16 Bit
8192 x 512
x 16 Bit
8192 x 512
x 16 Bit
Input Buffer Output Buffer
DQ0 - DQ15
Control Logic &
Timing Generator
SPB04129
Block Diagram for 16M x16 SDRAM ( 13 / 9 / 2 addressing)
INFINEON Technologies
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2002-04-23
HYB39S256400/800/160DT(L)/DC(L)
256MBit Synchronous DRAM
Signal Pin Description
Pin
Type Signal Polarity Function
CLK
Input Pulse Positive The system clock input. All of the SDRAM inputs are
Edge
sampled on the rising edge of the clock.
CKE
CS
Input Level Active
High
Activates the CLK signal when high and deactivates the
CLK signal when low, thereby initiating either the Power
Down mode, Suspend mode, or the Self Refresh mode.
Input Pulse Active
Low
CS enables the command decoder when low and disables
the command decoder when high. When the command
decoder is disabled, new commands are ignored but
previous operations continue.
RAS
CAS
WE
Input Pulse Active
Low
When sampled at the positive rising edge of the clock,
CAS, RAS, and WE define the command to be executed by
the SDRAM.
A0 - A12 Input Level
–
During a Bank Activate command cycle, A0-A12 define the
row address (RA0-RA12) when sampled at the rising clock
edge.
During a Read or Write command cycle, A0-An define the
column address (CA0-CAn) when sampled at the rising
clock edge.CAn depends upon the SDRAM organization:
64M x4 SDRAM CAn = CA9, CA11 (Page Length = 2048 bits)
32M x8 SDRAM
CAn = CA9
(Page Length = 1024 bits)
16M x16 SDRAM
CAn = CA8
(Page Length = 512 bits)
In addition to the column address, A10(= AP) is used to
invoke the autoprecharge operation at the end of the burst
read or write cycle. If A10 is high, autoprecharge is
selected and BA0, BA1 defines the bank to be precharged.
If A10 is low, autoprecharge is disabled.
During a Precharge command cycle, A10 (= AP) is used in
conjunction with BA0 and BA1 to control which bank(s) to
precharge. If A10 is high, all four banks will be precharged
regardless of the state of BA0 and BA1. If A10 is low, then
BA0 and BA1 are used to define which bank to precharge.
BA0, BA1 Input Level
–
–
Bank Select Inputs. Bank address inputs selects which of
the four banks a command applies to.
DQx
Input Level
Output
Data Input/Output pins operate in the same manner as on
conventional DRAMs.
INFINEON Technologies
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2002-04-23
HYB39S256400/800/160DT(L)/DC(L)
256MBit Synchronous DRAM
Pin
Type Signal Polarity Function
DQM
LDQM
UDQM
Input Pulse Active
High
The Data Input/Output mask places the DQ buffers in a
high impedance state when sampled high. In Read mode,
DQM has a latency of two clock cycles and controls the
output buffers like an output enable. In Write mode, DQM
has a latency of zero and operates as a word mask by
allowing input data to be written if it is low but blocks the
write operation if DQM is high.
One DQM input is present in x4 and x8 SDRAMs, LDQM
and UDQM controls the lower and upper bytes in x16
SDRAMs.
VDD
VSS
Supply –
Supply –
–
–
Power and ground for the input buffers and the core logic.
VDDQ
VSSQ
Isolated power supply and ground for the output buffers to
provide improved noise immunity.
INFINEON Technologies
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2002-04-23
HYB39S256400/800/160DT(L)/DC(L)
256MBit Synchronous DRAM
Operation Definition
All of SDRAM operations are defined by states of control signals CS, RAS, CAS, WE, and DQM at
the positive edge of the clock. The following list shows the truth table for the operation commands.
Operation
Device
State
Idle3
CKE CKE DQM BA0 AP= Addr CS
RAS CAS WE
n-1
H
H
H
H
H
H
H
H
H
H
H
H
H
n
X
X
X
X
X
X
X
X
X
X
X
H
L
BA1 A10
.
Bank Active
Bank Precharge
Precharge All
Write
X
X
X
X
X
X
X
X
X
X
X
X
X
V
V
X
V
V
V
V
V
X
X
X
X
X
V
L
V
X
X
V
V
V
V
V
X
X
X
X
X
L
L
L
L
L
L
L
L
L
L
H
L
L
H
L
L
L
H
H
H
L
H
L
Any
Any
H
L
L
L
Active3
H
H
H
H
L
L
Write with Autoprecharge Active3
Read
Active3
Read with Autoprecharge Active3
H
L
L
L
L
H
H
L
H
V
X
X
X
X
X
L
Mode Register Set
No Operation
Idle
L
Any
Active
Any
Idle
H
H
X
L
H
H
X
L
H
L
Burst Stop
Device Deselect
Auto Refresh
X
H
H
X
X
Self Refresh Entry
Self Refresh Exit
Idle
L
L
Idle
(Self
Refr.)
X
H
X
H
L
H
H
H
L
L
X
X
X
X
X
X
X
X
X
X
X
X
Clock Suspend Entry
Active
Idle
X
H
X
X
X
X
X
X
Power Down Entry
(Precharge or active
standby)
Active4
Active
L
X
H
L
H
X
X
H
H
X
X
H
H
X
X
L
Clock Suspend Exit
Power Down Exit
L
L
H
H
X
X
X
X
X
X
X
X
Any
(Power
Down)
Data Write/Output Enable Active
Data Write/Output Disable Active
Notes
H
H
X
X
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
H
1. V = Valid, x = Don’t Care, L = Low Level, H = High Level
2. CKEn signal is input level when commands are provided, CKEn-1 signal is input level one clock before the
commands are provided.
3. This is the state of the banks designated by BA0, BA1 signals.
4. Power Down Mode can not be entered in a burst cycle. When this command asserted in the burst mode cycle
device is in clock suspend mode.
INFINEON Technologies
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HYB39S256400/800/160DT(L)/DC(L)
256MBit Synchronous DRAM
Mode Register Set Table
BA0 A12A11 A10 A9
Operation Mode
BA1
A8 A7 A6 A5 A4 A3 A2 A1 A0
Address Bus (Ax)
CAS Latency BT Burst Length
Mode Register (Mx)
Operation Mode
Burst Type
M9
0
Mode
M3
0
Type
burst read / burst write
burst read / single write
Sequential
Interleave
1
1
Burst Length
CAS Latency
Length
M2
M1
M0
M6
0
M5
0
M4
0
Latency
Sequential Interleave
Reserved
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
2
4
8
1
2
4
8
0
0
1
Reserved
0
1
0
2
3
0
1
1
1
0
0
1
0
1
Reserved
Full Page
Reserved
Reserved
1
1
0
1
1
1
INFINEON Technologies
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HYB39S256400/800/160DT(L)/DC(L)
256MBit Synchronous DRAM
Power On and Initialization
The default power on state of the mode register is supplier specific and may be undefined.
The following power on and initialization sequence guarantees the device is preconditioned to each
users specific needs. Like a conventional DRAM, the Synchronous DRAM must be powered up and
initialized in a predefined manner. During power on, all VDD and VDDQ pins must be built up
simultaneously to the specified voltage when the input signals are held in the “NOP” state. The
power on voltage must not exceed VDD+0.3V on any of the input pins or VDD supplies. The CLK
signal must be started at the same time. After power on, an initial pause of 200 µs is required
followed by a precharge of all banks using the precharge command. To prevent data contention on
the DQ bus during power on, it is required that the DQM and CKE pins be held high during the initial
pause period. Once all banks have been precharged, the Mode Register Set Command must be
issued to initialize the Mode Register. A minimum of eight Auto Refresh cycles (CBR) are also
required.These may be done before or after programming the Mode Register. Failure to follow these
steps may lead to unpredictable start-up modes.
Programming the Mode Register
The Mode register designates the operation mode at the read or write cycle. This register is
divided into four fields. First, a Burst Length Field which sets the length of the burst, Second, an
Addressing Selection bit which programs the column access sequence in a burst cycle (interleaved
or sequential). Third, a CAS Latency Field to set the access time at clock cycle. Fourth, an
Operation mode field to differentiate between normal operation (Burst read and burst Write) and a
special Burst Read and Single Write mode. After the initial power up, the mode set operation must
be done before any activate command. Any content of the mode register can be altered by re-
executing the mode set command. All banks must be in precharged state and CKE must be high at
least one clock before the mode set operation. After the mode register is set, a Standby or NOP
command is required. Low signals of RAS, CAS, and WE at the positive edge of the clock activate
the mode set operation. Address input data at this timing defines parameters to be set as shown in
the previous table.
Read and Write Operation
When RAS is low and both CAS and WE are high at the positive edge of the clock, a RAS cycle
starts. According to address data, a word line of the selected bank is activated and all of sense
amplifiers associated to the wordline are set. A CAS cycle is triggered by setting RAS high and CAS
low at a clock timing after a necessary delay, tRCD, from the RAS timing. WE is used to define either
a read (WE = H) or a write (WE = L) at this stage.
SDRAM provides a wide variety of fast access modes. In a single CAS cycle, serial data read
or write operations are allowed at up to a 166 MHz data rate. The numbers of serial data bits are the
burst length programmed at the mode set operation, i.e., one of 1, 2, 4 and 8 and full page. Column
addresses are segmented by the burst length and serial data accesses are done within this
boundary. The first column address to be accessed is supplied at the CAS timing and the
subsequent addresses are generated automatically by the programmed burst length and its
sequence. For example, in a burst length of 8 with interleave sequence, if the first address is ‘2’,
then the rest of the burst sequence is 3, 0, 1, 6, 7, 4, and 5.
Full page burst operation is only possible using the sequential burst type and page length is
a function of the I/O organization and column addressing. Full page burst operation does not self
INFINEON Technologies
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HYB39S256400/800/160DT(L)/DC(L)
256MBit Synchronous DRAM
terminate once the burst length has been reached. In other words, unlike burst lengths of 2, 4 and
8, full page burst continues until it is terminated using another command.
Similar to the page mode of conventional DRAMs, burst read or write accesses on any column
address are possible once the RAS cycle latches the sense amplifiers. The maximum tRAS or the
refresh interval time limits the number of random column accesses. A new burst access can be
done even before the previous burst ends. The interrupt operation at every clock cycle is supported.
When the previous burst is interrupted, the remaining addresses are overridden by the new address
with the full burst length. An interrupt which accompanies an operation change from a read to a write
is possible by exploiting DQM to avoid bus contention.
When two or more banks are activated sequentially, interleaved bank read or write operations
are possible. With the programmed burst length, alternate access and precharge operations on two
or more banks can realize fast serial data access modes among many different pages. Once two or
more banks are activated, column to column interleave operation can be performed between
different pages.
Burst Length and Sequence:
Burst Starting Address Sequential Burst Addressing
Interleave Burst Addressing
(decimal)
Length
(A2 A1 A0)
(decimal)
2
xx0
xx1
0, 1
1, 0
0, 1
1, 0
4
8
x00
x01
x10
x11
0, 1, 2, 3
1, 2, 3, 0
2, 3, 0, 1
3, 0, 1, 2
0, 1, 2, 3
1, 0, 3, 2
2, 3, 0, 1
3, 2, 1, 0
000
001
010
011
100
101
110
111
0
1
2
3
4
5
6
7
1
2
3
4
5
6
7
0
2
3
4
5
6
7
0
1
3
4
5
6
7
0
1
2
4
5
6
7
0
1
2
3
5
6
7
0
1
2
3
4
6
7
0
1
2
3
4
5
7
0
1
2
3
4
5
6
0
1
2
3
4
5
6
7
1
0
3
2
5
4
7
6
2
3
0
1
6
7
4
5
3
2
1
0
7
6
5
4
4
5
6
7
0
1
2
3
5
4
7
6
1
0
3
2
6
7
4
5
2
3
0
1
7
6
5
4
3
2
1
0
Full
nnn
Cn, Cn+1, Cn+2 ....
not supported
Page
Refresh Mode
SDRAM has two refresh modes, Auto Refresh and Self Refresh. Auto Refresh is similar to the
CAS -before-RAS refresh of conventional DRAMs. All banks must be precharged before applying
any refresh mode. An on-chip address counter increments the word and the bank addresses and no
bank information is required for both refresh modes.
The chip enters the Auto Refresh mode, when RAS and CAS are held low and CKE and WE
are held high at a clock timing. The mode restores word line after the refresh and no external
precharge command is necessary. A minimum tRC time is required between two automatic
refreshes in a burst refresh mode. The same rule applies to any access command after the
automatic refresh operation.
INFINEON Technologies
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2002-04-23
HYB39S256400/800/160DT(L)/DC(L)
256MBit Synchronous DRAM
The chip has an on-chip timer and the Self Refresh mode is available. The mode restores the
word lines after RAS, CAS, and CKE are low and WE is high at a clock timing. All of external control
signals including the clock are disabled. Returning CKE to high enables the clock and initiates the
refresh exit operation. After the exit command, at least one tRC delay is required prior to any access
command.
DQM Function
DQM has two functions for data I/O read and write operations. During reads, when it turns to
“high“ at a clock timing, data outputs are disabled and become high impedance after two clock delay
(DQM Data Disable Latency tDQZ). It also provides a data mask function for writes. When DQM is
activated, the write operation at the next clock is prohibited (DQM Write Mask Latency tDQW = zero
clocks).
Suspend Mode
During normal access mode, CKE is held high enabling the clock. When CKE is low, it freezes the
internal clock and extends data read and write operations. One clock delay is required for mode
entry and exit (Clock Suspend Latency tCSL).
Power Down
In order to reduce standby power consumption, a power down mode is available. All banks
must be precharged and the necessary Precharge delay (trp) must occur before the SDRAM can
enter the Power Down mode. Once the Power Down mode is initiated by holding CKE low, all of the
receiver circuits except CLK and CKE are gated off. The Power Down mode does not perform any
refresh operations, therefore the device can’t remain in Power Down mode longer than the Refresh
period (tref) of the device. Exit from this mode is performed by taking CKE “high“. One clock delay
is required for Power Down mode entry and exit.
Auto Precharge
Two methods are available to precharge SDRAMs. In an automatic precharge mode, the CAS
timing accepts one extra address, CA10, to determine whether the chip restores or not after the
operation. If CA10 is high when a Read Command is issued, the Read with Auto-Precharge
function is initiated. If CA10 is high when a Write Command is issued, the Write with Auto-
Precharge function is initiated. The SDRAM automatically enters the precharge operation a time
delay equal to tWR (“write recovery time”) after the last data in.
A burst operation with Auto-Precharge may only be interrupted by a burst start to another bank. It
must not be interrupted by a precharge or a burst stop command.
Precharge Command
There is also a separate precharge command available. When RAS and WE are low and CAS is
high at a clock timing, it triggers the precharge operation. Three address bits, BA0, BA1 and A10 are
used to define banks as shown in the following list. The precharge command can be imposed one
clock before the last data out for CAS latency = 2 and two clocks before the last data out for CAS
latency = 3. Writes require a time delay twr (“write recovery time”) of 2 clocks minimum from the last
data out to apply the precharge command.
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2002-04-23
HYB39S256400/800/160DT(L)/DC(L)
256MBit Synchronous DRAM
Bank Selection by Address Bits
A10 BA0 BA1
0
0
0
0
1
0
0
1
1
x
0
1
0
1
x
Bank 0
Bank 1
Bank 2
Bank 3
all Banks
Burst Termination
Once a burst read or write operation has been initiated, there are several methods in which to
terminate the burst operation prematurely. These methods include using another Read or Write
Command to interrupt an existing burst operation, use a Precharge Command to interrupt a burst
cycle and close the active bank, or using the Burst Stop Command to terminate the existing burst
operation but leave the bank open for future Read or Write Commands to the same page of the
active bank. When interrupting a burst with another Read or Write Command care must be taken to
avoid DQ contention. The Burst Stop Command, however, has the fewest restrictions making it the
easiest method to use when terminating a burst operation before it has been completed. If a Burst
Stop command is issued during a burst write operation, then any residual data from the burst write
cycle will be ignored. Data that is presented on the DQ pins before the Burst Stop Command is
registered will be written to the memory.
Capacitance
TA = 0 to 70 °C; VDD,
V
DDQ = 3.3 V 0.3 V, f = 1 MHz
Symbol
Parameter
Values
Unit
min.
max.
3.5
Input capacitance (CLK)
CI1
2.5
2.5
pF
Input capacitance
CI2
3.8
pF
(A0-A12, BA0,BA1,RAS, CAS, WE, CS, CKE, DQM)
Input / Output capacitance (DQ)
CIO
4.0
6.0
pF
Note: Capacitance values are shown for TSOP-54 packages. Capacitance values for TFBGA packages
are lower by 0.5 pF.
INFINEON Technologies
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2002-04-23
HYB39S256400/800/160DT(L)/DC(L)
256MBit Synchronous DRAM
Absolute Maximum Ratings
Parameter
Symbol
Limit Values
max.
Unit
min.
Input / Output voltage relative to VSS
Power supply voltage
VIN, VOUT
VDD,VDDQ
TA
– 1.0
4.6
4.6
+70
+150
1
V
– 1.0
0
V
Operating Temperature
oC
oC
W
mA
Storage temperature range
TSTG
PD
-55
–
Power dissipation per SDRAM component
Data out current (short circuit)
IOS
–
50
Permanent device damage may occur if “Absolute Maximum Ratings” are exceeded.
Functional operation should be restricted to recommended operation conditions.
Exposure to higher than recommended voltage for extended periods of time affect device reliability
Recommended Operation Conditions and DC Eletrical Characteristics
T
A = 0 to 70 oC;
Parameter
Symbol
Limit Values
Unit Notes
min.
3.0
2.0
– 0.3
2.4
–
typ.
max.
Supply Voltage
Input high voltage
Input low voltage
VDD,VDDQ
VIH
3.3
3.6
V
V
1
3.0
0
VDDQ+0.3
1, 2
1, 2
1
VIL
0.8
–
V
Output high voltage (IOUT = – 4.0 mA) VOH
–
V
Output low voltage (IOUT = 4.0 mA)
VOL
IIL
–
0.4
5
V
1
Input leakage current, any input
– 5
–
mA
(0 V < VIN < VDD, all other inputs = 0 V)
Output leakage current
IOL
– 5
–
5
mA
(DQs are disabled, 0 V < VOUT < VDDQ
)
Notes:
1. All voltages are referenced to VSS
.
2. Vih may overshoot to VDDQ + 2.0 V for pulse width of < 4ns with 3.3V. Vil may undershoot to -2.0 V for pulse
width < 4.0 ns with 3.3V. Pulse width measured at 50% points with amplitude measured peak to DC
reference.
INFINEON Technologies
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2002-04-23
HYB39S256400/800/160DT(L)/DC(L)
256MBit Synchronous DRAM
Operating Currents
TA = 0 to 70 oC; VSS = 0 V; VDD, VDDQ = 3.3 V 0.3 V
Symb.
Note
Parameter & Test Condition
-6
-7
-7.5
max.
-8
Operating Current
One bank active, Burst length = 1
tRC = tRC(min)
Io = 0 mA
,
IDD1
IDD2P
IDD2N
IDD3N
IDD3P
IDD4
100
2
80
80
80
2
mA 3, 4
Precharge Standby Current
in Power Down Mode
CS =VIH (min.),
CKE<=Vil(max)
2
2
mA
mA
mA
mA
3
3
3
3
Precharge Standby Current
in Non-Power Down Mode
CS = VIH (min.),
CKE>=Vih(min)
35
40
5
30
35
5
30
35
5
25
30
5
No Operating Current
CS = VIH(min),
CKE>=VIH(min.)
CS = VIH(min),
CKE<=VIL(max.)
active state ( max. 4 banks)
Burst Operating Current
110
90
90
70
mA 3, 4
Read command cycling
Auto Refresh Current
t
RFC= tRFC(min)
220
3
190
3
190
3
160
3
mA
IDD5
IDD6
5
tRFC= 7.8 µs
mA
Auto Refresh command cycling
Self Refresh Current
(standard components)
Self Refresh Mode, CKE=0.2V,
tck=infinity
x4, x8
x16
3
1.5
3
1.5
3
1.5
3
1.5
mA
mA
Self Refresh Current
(low power components)
Self Refresh Mode, CKE=0.2V,
tck=infinity
x8, x16
IDD6
0.85
0.85
0.85
0.85 mA
Notes:
3. These parameters depend on the cycle rate. All values are measured at 166 MHz for “-6”, at 133 MHz for
“-7” and “-7.5” and at 100 MHz for “-8” components with the outputs open. Input signals are changed once
during tck.
4. These parameters are measured with continuous data stream during read access and all DQ toggling. CL=3
and BL=4 is assumed and the VDDQ current is excluded.
5. tRFC= tRFC(min) “burst refresh”, tRFC= 7.8 µs “distributed refresh”.
INFINEON Technologies
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2002-04-23
HYB39S256400/800/160DT(L)/DC(L)
256MBit Synchronous DRAM
AC Characteristics 1)2)
TA = 0 to 70 oC; VSS = 0 V; VDD, VDDQ = 3.3 V 0.3 V, tT = 1 ns
Symbol
Unit
Parameter
Limit Values
-6
PC166-
333
-7
PC133-
222
-7.5
PC133-
333
-8
PC100-
222
min. max. min. max. min. max. min. max.
Clock and Clock Enable
Clock Cycle Time
CAS Latency = 3
CAS Latency = 2
Clock Frequency
6
7.5
–
–
7
7.5
–
–
7.5
10
–
–
8
10
–
–
ns
ns
tCK
tCK
tAC
CAS Latency = 3
CAS Latency = 2
–
–
166
133
–
–
143
133
–
–
133
100
–
–
125 MHz
100 MHz
Access Time from Clock
2,
3,
6
CAS Latency = 3
CAS Latency = 2
–
–
5
5.4
–
–
5.4
5.4
–
–
5.4
6
–
–
6
6
ns
ns
Clock High Pulse Width
tCH
tCL
tT
2
2
–
–
2.5
2.5
–
–
2.5
2.5
–
–
3
3
–
–
ns
ns
Clock Low Pulse Width
Transition time
0.3
1.2 0.3
1.2 0.3
1.2 0.5
10 ns
Setup and Hold Times
Input Setup Time
Input Hold Time
4
4
4
4
tIS
tIH
1.5
0.8
1.5
0.8
2
–
–
–
–
–
1.5
0.8
1.5
0.8
2
–
–
–
–
–
1.5
0.8
1.5
0.8
2
–
–
–
–
–
2
1
2
1
2
–
–
–
–
–
ns
ns
CKE Setup Time
CKE Hold Time
tCKS
tCKH
tRSC
ns
ns
Mode Register Set-up to Active
delay
CLK
Power Down Mode Entry Time
tSB
0
6
0
7
0
7.5
0
8
ns
Common Parameters
Row to Column Delay Time
Row Precharge Time
Row Active Time
5
5
5
5
tRCD
tRP
tRAS
tRC
15
15
–
–
15
15
–
–
20
20
–
–
20
20
48
70
–
–
ns
ns
ns
ns
100k
100k
–
36 100k 37 100k 45
Row Cycle Time
60
–
60
–
67
–
INFINEON Technologies
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2002-04-23
HYB39S256400/800/160DT(L)/DC(L)
256MBit Synchronous DRAM
Symbol
Unit
Parameter
Limit Values
-6
PC166-
333
-7
PC133-
222
-7.5
PC133-
333
-8
PC100-
222
min. max. min. max. min. max. min. max.
Row Cycle Time during Auto
Refresh
tRFC
tRRD
tCCD
60
12
1
63
14
1
67
15
1
70
16
1
ns
5
Activate(a) to Activate(b)
Command period
–
–
–
–
–
–
–
–
ns
CAS(a) to CAS(b) Command
period
CLK
Refresh Cycle
Refresh Period (8192 cycles)
Self Refresh Exit Time
tREF
–
1
64
–
–
1
64
–
–
1
64
–
–
1
64 ms
CLK
tSREX
Read Cycle
Data Out Hold Time
tOH
2.5
–
3
–
3
–
3
–
ns
2,
6
Data Out to Low Impedance Time
Data Out to High Impedance Time
DQM Data Out Disable Latency
tLZ
tHZ
0
3
–
–
6
2
0
3
–
–
7
2
0
3
–
–
7
2
0
3
–
–
8
2
ns
ns
tDQZ
CLK
Write Cycle
7
8
Last Data Input to Precharge
(Write without AutoPrecharge)
tWR
tDAL,min
tDQW
12
0
–
–
14
–
15
–
15
0
–
–
ns
Last Data Input to Activate
(Write with AutoPrecharge)
(twr/tck) + (trp/tck)
CLK
CLK
DQM Write Mask Latency
0
–
0
–
INFINEON Technologies
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2002-04-23
HYB39S256400/800/160DT(L)/DC(L)
256MBit Synchronous DRAM
Notes
1. For proper power-up see the operation section of this data sheet.
2. AC timing tests for LV-TTL versions have VIL = 0.4 V and VIH = 2.4 V with the timing referenced to
the 1.4 V crossover point. The transition time is measured between VIH and VIL. All AC
measurements assume tT = 1 ns with the AC output load circuit shown in figure below. Specified
tAC and tOH parameters are measured with a 50 pF only, without any resistive termination and
with an input signal of 1V / ns edge rate between 0.8 V and 2.0 V.
t CH
2.4
0.4
V
V
1 .4 V
C L O C K
tT
tC L
tIH
tIS
IN PU T
1 .4 V
tAC
tA C
tL Z
t OH
O U TPU T
1.4 V
I/O
50 pF
tH Z
Measurement conditions for
IO.vsd
tAC and tOH
3. If clock rising time is longer than 1 ns, a time (tT/2 − 0.5) ns has to be added to this parameter.
4. If tT is longer than 1 ns, a time (tT − 1) ns has to be added to this parameter.
5. These parameter account for the number of clock cycles and depend on the operating frequency
of the clock, as follows:
the number of clock cycles = specified value of timing period (counted in fractions as a whole
number)
6. Access time from clock tAC is 4.6 ns for PC133 components with no termination and 0 pF load,
Data out hold time tOH is 1.8 ns for PC133 components with no termination and 0 pF load.
7. It is recommended to use two clock cycles between the last data-in and the precharge command
in case of a write command without Auto-Precharge. One clock cycle between the last data-in
and the precharge command is also supported, but restricted to cycle times tck greater or equal
the specified twr value, where tck is equal to the actual system clock time
8. When a Write command with AutoPrecharge has been issued, a time of tdal(min) has be fullfilled
before the next Activate Command can be applied. For each of the terms, if not already an
integer, round up to the next highest integer. tck is equal to the actual system clock time.
INFINEON Technologies
20
2002-04-23
HYB39S256400/800/160DT(L)/DC(L)
256MBit Synchronous DRAM
Package Outlines - TSOP
Plastic Package P-TSOPII-54
(400 mil, 0.8 mm lead pitch)
Thin Small Outline Package, SMD
ꢀ5˚ 5˚
2)
ꢀ0.ꢀ6 0.ꢀ3
0.8
0.5 0.ꢀ
ꢀꢀ.76 0.2
ꢀ5˚ 5˚
0.ꢀ 54x
26x 0.8 = 20.8
3)
+0.ꢀ
-0.05
M
0.2
54x
0.35
54
ꢀ
28
27
2.5 max
ꢀ)
22.22 0.ꢀ3
GPX09039
Index Marking
ꢀ) Does not include plastic or metal protrusion of 0.ꢀ5 max per side
2) Does not include plastic protrusion of 0.25 max per side
3) Does not include dambar protrusion of 0.ꢀ3 max per side
INFINEON Technologies
21
2002-04-23
HYB39S256400/800/160DT(L)/DC(L)
256MBit Synchronous DRAM
Package Outlines- TFBGA
TFBGA-54 package
(12 mm x 8 mm, 54 balls)
INFINEON Technologies
22
2002-04-23
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