HYM324000GDL-60 [INFINEON]
Fast Page DRAM Module, 4MX32, 50ns, CMOS, SODIMM-72;
| 型号： | HYM324000GDL-60 |
| 厂家： | 
Infineon |
| 描述： | Fast Page DRAM Module, 4MX32, 50ns, CMOS, SODIMM-72 动态存储器 内存集成电路 |
| 文件： | 总10页 (文件大小：52K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
4M × 32 -Bit Dynamic RAM Module
HYM 324020GD(L)-50/-60
SMALL OUTLINE MEMORY MODULE
Preliminary Information
• 72-Pin Small Outline Dual-in-Line Memory Module
• 4 0194 034 words by 32-bit organization
• Performance:
-50
90
-60
110
tRC
Read / Write Cycle Time
ns
ns
ns
ns
ns
tRAC RAS Access Time
tCAC CAS Access Time
50
13
25
35
60
15
30
40
tAA
tPC
Access Time From Address
Fast Page Mode Cycle Time
• Single + 3.3 V (± 0.3 V) supply
• Low power dissipation
max. 2880 mW active (-50 version)
max. 2592 mW active (-60 version)
LVTLL - 57.6 mw standby
LVCMOS– 28.8 mW standby
LVCMOS– 5.76 mW standby (L-version)
• Fast Page Mode
• Low Power Versions with Self Refresh
• CAS-before-RAS refresh, RAS-only-refresh
• 8 decoupling capacitors mounted on substrate
• All inputs, outputs and clock fully TTL compatible
• Utilizes eight 4M × 4 -DRAMs in TSOPII-packages
• Card size 56.69mm x 25.40mm x 3.80 mm
• 12 / 10 Adressing (Row/Column)
• 4096 refresh cycles / 64 ms
• Gold contact pad
Semiconductor Group
1
2.96
HYM324020GD(L)-50/-60
4M x 32 SO-DIMM
The HYM 324020GD(L) -50/-60 are 16 MByte DRAM 72pin small outline dual-in-line memory
modules organized as 4M x 32, comprising eight HYB3116400BT(L) 4M × 4 DRAMs in 300 mil wide
TSOPII-26/24 - packages mounted together with eight 0.2 µF ceramic decoupling capacitors on a
PC board. These modules are optimized for use in byte-write non-parity applications. Each HYB
3116400BT(L) is described in the data sheet and is fully electrically tested and processed according
to Siemens standard quality procedure prior to module assembly. After assembly onto the board, a
further set of electrical tests is performed.
The density and speed of the module can be detected by the use of presence detect pins.
These modules are ideal for portable systems applications where high memory capacity is needed.
Ordering Information
Type
Ordering Code
Package
Descriptions
HYM 324020GD -50
HYM 324000GD -60
HYM 324020GDL -50
HYM 324000GDL -60
L-DIM-72-3
L-DIM-72-3
L-DIM-72-3
L-DIM-72-3
50 ns DRAM module
60 ns DRAM module
50 ns Low Power DRAM module
60 ns Low Power DRAM module
Pin Names
A0-A11
Row Address Input
Column Address Inputs
Data Input/Output
Row Address Strobe
Column Address Strobe
Read / Write Input
Power (+3.3 Volt)
Ground
A0-A9
DQ0 - DQ31
RAS0, RAS2
CAS0 - CAS3
WE
Vcc
Vss
PD1 - PD7
N.C.
Presence Detect Pins
No Connection
Presence-Detect Truth Table *):
Module
PD1 PD2 PD3 PD4 PD5 PD6 PD7
HYM 324000GD -50
HYM 324000GD -60
HYM 324000GDL -50
HYM 324000GDL -60
NC
NC
NC
NC
NC
NC
NC
NC
VSS NC
VSS NC
VSS NC
VSS NC
VSS VSS NC
NC NC NC
VSS VSS VSS
NC NC VSS
*) note:
PD1...PD4
PD5..PD6
PD7
: configuration
: speed
: refresh mode
Semiconductor Group
2
HYM324020GD(L)-50/-60
4M x 32 SO-DIMM
Pin Configuration
PIN
Name
PIN
NAME
PIN
NAME
PIN
NAME
1
VSS
DQ1
DQ3
DQ5
DQ7
PD1
A1
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
DQ16
VSS
2
DQ0
DQ2
DQ4
DQ6
VCC
A0
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
DQ17
CAS0
CAS3
RAS0
NC
Pin1
3
4
Pin2
5
CAS2
CAS1
NC
6
7
8
9
10
12
14
16
18
20
22
24
26
28
30
32
34
36
11
13
15
17
19
21
23
25
27
29
31
33
35
WRITE
DQ18
DQ20
DQ22
NC
NC
A2
DQ19
DQ21
DQ23
DQ24
DQ26
DQ27
DQ29
DQ31
PD2
A3
A4
A5
A6
A10
DQ8
DQ10
DQ12
DQ14
A11
NC
DQ25
DQ28
VCC
DQ30
NC
DQ9
DQ11
DQ13
A7
VCC
A9
Pin71
Pin72
A8
PD3
PD4
NC
PD5
RAS2
NC
PD6
DQ15
PD7
VSS
Front Side
Back Side
Semiconductor Group
3
HYM324020GD(L)-50/-60
4M x 32 SO-DIMM
RAS0
CAS0
CAS RAS
I/O1-I/O4
OE
DQ0-DQ3
D0
CAS RAS
I/O1-I/O4
OE
DQ4-DQ7
CAS1
D1
CAS RAS
DQ8-DQ11
I/O1-I/O4
OE
D2
CAS RAS
I/O1-I/O4
OE
DQ12-DQ15
D3
RAS2
CAS2
CAS RAS
I/O1-I/O4
OE
DQ16-DQ19
DQ20-DQ23
D4
CAS RAS
I/O1-I/O4
OE
D5
CAS3
CAS RAS
I/O1-I/O4
OE
DQ24-DQ27
DQ28-DQ31
D6
CAS RAS
I/O1-I/O4
OE
D7
D0-D7
VCC
VSS
A0R-A11R
A0C-A9C
C0 - C7
D0-D7
D0-D7
WE
Block Diagram
Semiconductor Group
4
HYM324020GD(L)-50/-60
4M x 32 SO-DIMM
Absolute Maximum Ratings
Operating temperature range..............................................................................................0 to 70 °C
Storage temperature range.........................................................................................– 55 to 150 °C
Input/output voltage..................................................................................-0.5 to min (Vcc+0.5,4.6) V
Power supply voltage....................................................................................................-0.5V to 4.6 V
Power dissipation......................................................................................................................1.0 W
Data out current (short circuit)..................................................................................................50 mA
DC Characteristics
TA = 0 to 70 °C, VSS = 0 V, VCC = 3.3 V ± 0.3 V
Parameter
Symbol
Limit Values
Unit Note
min.
max.
Vcc+0.3
0.8
Input high voltage
Input low voltage
VIH
VIL
2.0
V
V
V
1)
1)
1)
– 0.3
2.4
Output high voltage (LVTTL)
VOH
–
Output „H“ level voltage (Iout = -2mA)
Output low voltage (LVTTL)
Output „L“level voltage (Iout = +2mA)
VOL
VOH
VOL
II(L)
–
0.4
-
V
1)
1)
!)
Output high voltage (LVCMOS)
Output „H“ level voltage (Iout = -100uA)
Vcc-0.2
-
V
Ouput low voltage (LVCMOS)
Output „L“ level voltage (Iout = +100uA)
0.2
10
10
V
Input leakage current,any input
(0 V < Vin < Vcc , all other pins = 0 V
– 10
– 10
µA
µA
Output leakage current
(DO is disabled, 0 V < Vout < Vcc )
IO(L)
ICC1
Average Vcc supply current:
-50 ns version
-60 ns version
–
–
800
720
mA 2) 3)
mA 4)
(RAS, CAS, address cycling: tRC = tRC min.)
Standby Vcc supply current
(RAS=CAS= Vih)
ICC2
ICC3
–
16
mA
–
Average Vcc supply current, during RAS-only
refresh cycles:
-50 ns version
–
–
800
720
mA 2) 3)
mA
-60 ns version
(RAS cycling: CAS = VIH: tRC = tRC min.)
Semiconductor Group
5
HYM324020GD(L)-50/-60
4M x 32 SO-DIMM
DC Characteristics (cont’d)
TA = 0 to 70 °C, VSS = 0 V, VCC = 3.3 V ± 0.3 V
Parameter
Symbol
Limit Values
Unit Note
min.
max.
Average Vcc supply current,
ICC4
during fast page mode:
-50 ns version
-60 ns version
–
–
320
280
mA 2) 3)
mA 4)
(RAS = VIL, CAS, address cycling: tPC=tPC min.)
ICC5
ICC5
ICC6
–
–
8
mA
mA
–
–
Standby Vcc supply current
(RAS=CAS= Vcc-0.2V)
1.6
Standby Vcc supply current (L-version)
(RAS=CAS= Vcc-0.2V)
Average Vcc supply current, during CAS-before-
RAS refresh mode:
-50 ns version
–
–
800
720
mA 2) 4)
mA
-60 ns version
(RAS, CAS cycling: tRC = tRC min.)
Self Refresh Current (L-version only)
ICC7
–
2
mA
CBR cycle with RAS>tRASS(min.); CAS held low;
WE=Vcc-0.2V; Addresses and Di=Vcc-0.2V or 0.2V
Capacitance
TA = 0 to 70 °C, VCC = 3.3 V ± 0.3 V, f = 1 MHz
Parameter
Symbol
Limit Values
Unit
min.
max.
55
Input capacitance (A0 to A11,WE)
Input capacitance (RAS0, RAS2)
Input capacitance (CAS0 - CAS3)
I/O capacitance (DQ0-DQ31)
CI1
CI2
CI3
CIO
–
–
–
–
pF
pF
pF
pF
40
25
15
Semiconductor Group
6
HYM324020GD(L)-50/-60
4M x 32 SO-DIMM
5)6)
AC Characteristics
TA = 0 to 70 °C,VCC = 5 V ± 10 %, tT = 5 ns
Symbol
Note
Parameter
Limit Values
-50 -60
min. max. min. max.
Unit
common parameters
Random read or write cycle time
RAS precharge time
tRC
90
30
50
13
10
0
–
110
40
60
15
10
0
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
tRP
–
–
RAS pulse width
tRAS
tCAS
tCP
10k
10k
–
10k
10k
–
CAS pulse width
CAS precharge time
Row address setup time
Row address hold time
Column address setup time
Column address hold time
RAS to CAS delay time
RAS to column address delay time
RAS hold time
tASR
tRAH
tASC
tCAH
tRCD
tRAD
tRSH
tCSH
tCRP
tT
–
–
8
–
10
0
–
0
–
–
10
18
13
13
50
5
–
15
20
15
15
60
5
–
37
25
45
30
–
ns
ns
ns
ns
ns
ms
ms
CAS hold time
–
CAS to RAS precharge time
Transition time (rise and fall)
Refresh period
–
–
3
50
64
256
3
50
64
256
7
tREF
tREF
–
–
Refresh period (L-version)
–
–
Read Cycle
Access time from RAS
tRAC
tCAC
tAA
–
50
13
25
–
–
60
15
30
–
ns
ns
ns
ns
ns
ns
ns
8, 9
8, 9
8,10
Access time from CAS
–
–
Access time from column address
Column address to RAS lead time
Read command setup time
Read command hold time
–
–
tRAL
tRCS
tRCH
tRRH
25
0
30
0
–
–
0
–
0
–
11
11
Read command hold time referenced to
RAS
0
–
0
–
CAS to output in low-Z
tCLZ
tOFF
0
0
–
0
0
–
ns
ns
8
Output buffer turn-off delay
13
15
12
Semiconductor Group
7
HYM324020GD(L)-50/-60
4M x 32 SO-DIMM
5)6)
AC Characteristics (cont’d)
TA = 0 to 70 °C,VCC = 5 V ± 10 %, tT = 5 ns
Symbol
Note
Parameter
Limit Values
-50 -60
min. max. min. max.
Unit
Early Write Cycle
Write command hold time
Write command pulse width
Write command setup time
Write command to RAS lead time
Write command to CAS lead time
Data setup time
tWCH
tWP
8
–
–
–
–
–
–
–
10
10
0
–
–
–
–
–
–
–
ns
ns
ns
ns
ns
ns
ns
8
tWCS
tRWL
tCWL
tDS
0
13
13
13
0
15
15
0
14
14
Data hold time
tDH
10
10
Fast Page Mode Cycle
Fast page mode cycle time
Access time from CAS precharge
RAS pulse width
tPC
35
–
–
40
–
–
ns
ns
tCPA
tRAS
tRHCP
30
35
7
50
30
200k 60
200k ns
CAS precharge to RAS Delay
–
35
–
ns
CAS-before-RAS refresh cycle
CAS setup time
tCSR
tCHR
tRPC
tWRP
tWRH
10
10
5
–
–
–
–
–
10
10
5
–
–
–
–
–
ns
ns
ns
ns
ns
CAS hold time
RAS to CAS precharge time
Write to RAS precharge time
Write hold time referenced to RAS
10
10
10
10
Self Refresh Cycle (L-version only)
RAS pulse width
tRASS
tRPS
tCHS
100k
95
_
_
_
100k
110
-50
_
_
_
ns
ns
ns
RAS precharge time
CAS hold time
-50
Semiconductor Group
8
HYM324020GD(L)-50/-60
4M x 32 SO-DIMM
Notes:
1) All voltages are referenced to VSS.
2) ICC1, ICC3, ICC4 and ICC6 depend on cycle rate.
3) ICC1 and ICC4 depend on output loading. Specified values are measured with the output open.
4) Address can be changed once or less while RAS = VIL. In the case of ICC4 it can be changed once or less
during a fast page mode cycle (tPC).
5) An initial pause of 200 µs is required after power-up followed by 8 RAS cycles of which at least one cycle has
to be a refresh cycle, before proper device operation is achieved. In case of using internal refresh counter, a
minimum of 8 CAS-before-RAS initialization cycles instead of 8 RAS cycles are required.
6) AC measurements assume tT = 5 ns.
7) VIH (min.) and VIL (max.) are reference levels for measuring timing of input signals. Transition times are also
measured between VIH and VIL.
8) Measured with a load equivalent to 2 TTL loads and 100 pF.
9) Operation within the tRCD (max.) limit ensures that tRAC (max.) can be met. tRCD (max.) is specified as a
reference point only: If tRCD is greater than the specified tRCD (max.) limit, then access time is controlled by
tCAC.
10)Operation within the tRAD (max.) limit ensures that tRAC (max.) can be met. tRAD (max.) is specified as a
reference point only: If tRAD is greater than the specified tRAD (max.) limit, then access time is controlled by
tAA.
11)Either tRCH or tRRH must be satisfied for a read cycle.
12)tOFF (max.) define the time at which the outputs achieve the open-circuit condition and are not referenced to
output voltage levels
.
13)tWCS is not a restrictive operating parameter. This is included in the data sheet as electrical characteristics
only. If tWCS > tWCS (min.), the cycle is an early write cycle and the I/O pin will remain open-circuit (high
impedance) through the entire cycle.
14)These parameters are referenced to the CAS leading edge.
Semiconductor Group
9
HYM324020GD(L)-50/-60
4M x 32 SO-DIMM
SO-DIMM PACKAGE OUTLINES
56.69
3.8 max
FRONT SIDE
1
71
5.0 min.
E
44.45
7.62
1.0 +/- 0.1
8.255
R 2.0
51.66
2
72
R 2.0
BACK SIDE
1.0
note:
mechanical key for supply voltage
5 V E = 6.35
3.3V E = 3.175
1.27
Preliminary Drawing
L-DIM-72-3
Semiconductor Group
10
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