HYM324020GS-70 [INFINEON]
4M x 32-Bit Dynamic RAM Module; 4M ×32位的动态内存模块
| 型号： | HYM324020GS-70 |
| 厂家： | 
Infineon |
| 描述： | 4M x 32-Bit Dynamic RAM Module |
| 文件： | 总9页 (文件大小：127K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
4M x 32-Bit Dynamic RAM Module
HYM 324020S/GS-60/-70
Preliminary Information
• 4 194 304 words by 32-bit organization
• CAS-before-RAS refresh
(alternative 8 388 608 words by 16-bit)
RAS-only-refresh
Hidden-refresh
• Fast access and cycle time
60 ns access time
• 8 decoupling capacitors mounted on
110 ns cycle time (-60 version)
70 ns access time
130 ns cycle time (-70 version)
substrate
• All inputs, outputs and clocks fully TTL
compatible
• Fast page mode capability
40 ns cycle time (-60 version)
45 ns cycle time (-70 version)
• 72 pin Single in-Line Memory Module with
22.86 mm (900 mil) height
• Utilizes eight 4Mx4-DRAMs in 300mil wide
• Single + 5 V (± 10 %) supply
SOJ-packages
• Low power dissipation
max. 4840 mW active
(HYM 324020S/GS-60)
max. 4400 mW active
(HYM 324020S/GS-70)
CMOS – 44 mW standby
TTL – 88 mW standby
• 2048 refresh cycles / 32 ms
• Tin-Lead contact pads (S - version)
• Gold contact pads (GS - version)
Ordering Information
Type
Ordering Code
Package
Description
HYM 324020S-60
Q67100-Q979
L-SIM-72-12
L-SIM-72-12
L-SIM-72-12
L-SIM-72-12
DRAM Module
(access time 60 ns)
HYM 324020S-70
HYM 324020GS-60
HYM 324020GS-70
Q67100-Q980
Q67100-Q2005
on request
DRAM Module
(access time 70 ns)
DRAM Module
(access time 60 ns)
DRAM Module
(access time 70 ns)
Semiconductor Group
571
09.94
HYM 324020S/GS-60/-70
4M x 32-Bit
The HYM 324020S/GS-60/-70 is a 16 M Byte DRAM module organized as 4 194 304 words by
32-bit in a 72-pin single-in-line package comprising eight HYB 5117400BJ 4M x 4 DRAMs in 300
mil wide SOJ-packages mounted together with eight 0.2 µF ceramic decoupling capacitors on a PC
board.
The HYM 324020S/GS-60/-70 can also be used as a 8 388 608 words by 16-bits dynamic RAM
module by means of connecting DQ0 and DQ16, DQ1 and DQ17, DQ2 and DQ18, …, DQ15 and
DQ31, respectively.
Each HYB 5117400BJ is described in the data sheet and is fully electrical tested and processed
according to SIEMENS standard quality procedure prior to module assembly. After assembly onto
the board, a further set of electrical tests is performed.
The speed of the module can be detected by the use of four presence detect pins.
The common I/O feature on the HYM 324020S/GS-60/-70 dictates the use of early write cycles.
Pin Definitions and Functions
Pin No.
Functions
A0-A10
Address Inputs for
HYM 324020S/GS
DQ0-DQ31
CAS0 - CAS3
RAS0, RAS2
WE
Data Input/Output
Column Address Strobe
Row Address Strobe
Read/Write Input
Power (+ 5 V)
VCC
VSS
Ground
PD
Presence Detect Pin
No Connection
N.C.
Presence Detect Pins
-60
-70
PD0
PD1
PD2
PD3
VSS
VSS
N.C.
N.C.
N.C.
N.C.
VSS
N.C.
Semiconductor Group
572
HYM 324020S/GS-60/-70
4M x 32-Bit
Pin Configuration
(top view)
Semiconductor Group
573
HYM 324020S/GS-60/-70
4M x 32-Bit
Block Diagram
Semiconductor Group
574
HYM 324020S/GS-60/-70
4M x 32-Bit
Absolute Maximum Ratings
Operation temperature range ......................................................................................... 0 to + 70 ˚C
Storage temperature range......................................................................................... – 55 to 125 ˚C
Soldering temperature ............................................................................................................ 260 ˚C
Soldering time.............................................................................................................................10 s
Input/output voltage ........................................................................ – 0.5 V to min (VCC + 0.5, 7.0) V
Power supply voltage...................................................................................................... – 1 to + 7 V
Power dissipation................................................................................................................... 6.16 W
Data out current (short circuit) ................................................................................................ 50 mA
Note:Stresses above those listed under "Absolute Maximum Ratings" may cause permanent
damage of the device. Exposure to absolute maximum rating conditions for extended periods may
affect device reliability.
DC Characteristics1)
TA = 0 to 70 ˚C, VCC = 5 V ± 10 %
Parameter
Symbol
Limit Values
min. max.
Unit Test
Condition
Input high voltage
VIH
VIL
2.4
– 0.5
2.4
–
V
CC + 0.5 V
Input low voltage
0.8
–
V
Output high voltage (IOUT = – 5 mA)
Output low voltage (IOUT = 4.2 mA)
VOH
VOL
II(L)
V
0.4
20
V
Input leakage current
– 20
µA
(0 V < VIN < 6.5 V, all other pins = 0 V)
Output leakage current
(DO is disabled, 0 V < VOUT < 5.5 V)
IO(L)
ICC1
– 10
10
µA
Average VCC supply current
(RAS, CAS, address cycling, tRC = tRC min)
60 ns - Version
2)
3)
–
–
880
800
mA
mA
70 ns - Version
Standby VCC supply current
(RAS = CAS = VIH)
ICC2
ICC3
–
16
mA
Average VCC supply current
during RAS only refresh cycles
(RAS cycling, CAS = VIH, tRC = tRC min)
60 ns - Version
2)
–
–
880
800
mA
mA
70 ns - Version
Semiconductor Group
575
HYM 324020S/GS-60/-70
4M x 32-Bit
DC Characteristics1) (cont’d)
Parameter
Symbol
Limit Values
Unit Test
Condition
min.
max.
Average VCC supply current
during fast page mode
ICC4
(RAS = VIL, CAS, address cycling,
tPC = tPC min)
2)
3)
60 ns - Version
70 ns - Version
–
–
640
560
mA
mA
Standby VCC supply current
(RAS = CAS = VCC – 0.2 V)
ICC5
ICC6
–
8
mA
Average VCC supply current
during CAS-before-RAS refresh mode
(RAS, CAS cycling, tRC = tRC min)
2)
60 ns - Version
70 ns - Version
–
–
880
800
mA
mA
Capacitance
TA = 0 to 70 ˚C, VCC = 5 V ± 10 %, f = 1 MHz
Parameter
Symbol
Limit Values
Unit
min.
max.
90
Input capacitance (A0 to A10,WE)
Input capacitance (RAS0, RAS2)
Input capacitance (CAS0 - CAS3)
CI1
CI2
CI3
CIO
–
–
–
–
pF
pF
pF
pF
45
40
I/O capacitance
(DQ0-DQ31)
25
Semiconductor Group
576
HYM 324020S/GS-60/-70
4M x 32-Bit
AC Characteristics4) 5)
TA = 0 to 70 ˚C, VCC = 5 V ± 10 %, tT = 5 ns
Parameter
Symbol
Limit Values
Unit
HYM
HYM
324020S/GS-60
324020S/GS-70
min.
max.
–
min.
max.
–
Random read or write cycle time tRC
110
40
–
130
45
–
ns
ns
ns
ns
ns
Fast page mode cycle time
Access time from RAS
Access time from CAS
tPC
–
–
6) 11) 12)
6) 11)
tRAC
tCAC
tAA
60
15
30
70
20
35
–
–
Access time from column
address
–
–
6) 12)
Access time from CAS
precharge
tCPA
–
35
–
40
ns
6)
6)
7)
5)
CAS to output in low-Z
tCLZ
tOFF
tT
0
–
0
–
ns
ns
ns
ns
ns
ns
Output buffer turn-off delay
0
20
0
20
Transition time (rise and fall)
RAS precharge time
RAS pulse width
3
50
3
50
tRP
40
60
60
–
50
70
70
–
tRAS
tRASP
10000
200000
10000
200000
RAS pulse width
(fast page mode)
CAS precharge to RAS delay
RAS hold time
tRHCP
tRSH
tCSH
tCAS
tRCD
tRAD
35
15
60
15
20
15
–
40
20
70
20
20
15
–
ns
ns
ns
ns
ns
ns
–
–
CAS hold time
–
–
CAS pulse width
10000
45
10000
50
11)
12)
RAS to CAS delay time
RAS to column address
delay time
30
35
CAS to RAS precharge time
tCRP
tCP
5
–
–
5
–
–
ns
ns
CAS precharge time
(fast page mode)
10
10
Row address setup time
Row address hold time
Column address setup time
Column address hold time
tASR
tRAH
tASC
tCAH
0
–
–
–
–
0
–
–
–
–
ns
ns
ns
ns
10
0
10
0
15
15
Semiconductor Group
577
HYM 324020S/GS-60/-70
4M x 32-Bit
AC Characteristics4) 5) (cont’d)
TA = 0 to 70 ˚C, VCC = 5 V ± 10 %, tT = 5 ns
Parameter
Symbol
Limit Values
Unit
HYM
HYM
324020S/GS-60
324020S/GS-70
min.
max.
min.
max.
Column address to RAS lead time tRAL
30
0
–
–
–
–
35
0
–
–
–
–
ns
ns
ns
ns
Read command setup time
Read command hold time
tRCS
tRCH
tRRH
8)
8)
0
0
Read command hold time
ref. to RAS
0
0
Write command hold time
Write command pulse width
tWCH
tWP
10
10
15
15
0
–
–
–
–
–
–
32
–
–
–
–
–
–
–
15
15
20
20
0
–
–
–
–
–
–
32
–
–
–
–
–
–
–
ns
ns
ns
ns
ns
ns
ms
ns
ns
ns
ns
ns
ns
ns
Write command to RAS lead time tRWL
Write command to CAS lead time tCWL
9)
Data setup time
tDS
9)
Data hold time
tDH
15
–
15
–
Refresh period
tREF
tWCS
tCSR
tCHR
tRPC
tCP
10)
13)
13)
Write command setup time
CAS setup time
0
0
10
10
5
10
10
5
CAS hold time
RAS to CAS precharge time
CAS precharge time
Write to RAS precharge time
Write hold time ref. to RAS
10
10
10
10
10
10
13)
13)
tWRP
tWRH
Semiconductor Group
578
HYM 324020S/GS-60/-70
4M x 32-Bit
Notes
1) All voltages are referenced to VSS.
2) ICC1, ICC3, ICC4 and ICC6 depend on cycle rate.
3) ICC1 and ICC4 depend on output loading.
Specified values are measured with the output open.
4) An initial pause of 200 µs is required after power-up followed by 8 RAS cycles out of which at least one cycle
has to be a refresh cycle before proper device operation is achieved. In case of using internal refresh counter,
a minimum of 8 CAS-before-RAS initialization cycles instead of 8 RAS cycles are required.
5) VIH (max) and VIL (max) are reference levels for measuring timing of input signals.
Transition times are also measured between VIH and VIL.
6) Measured with a load equivalent of 2 TTL loads and 100 pF.
7) tOFF (max) defines the time at which the output achieves the open-circuit condition and is not referenced to
output voltage levels.
8) Either tRCH or tRRH must be satisfied for a read cycle.
9) These parameters are referenced to the CAS leading edge.
10) tWCS is not a restrictive operating parameter. This is included in the data sheet as electrical characteristic only.
If tWCS > tWCS (min), the cycle is an early write cycle and data out pin will remain open (high impedance).
11) Operation within the tRCD (max) limit insures that tRAC (max) can be met. tRCD (max) is specified as a reference point
only. If tRCD is greater than the specified tRCD (max) limit, then access time is controlled by tCAS
.
12) Operation within the tRAD (max) limit insures that tRAC (max) can be met. tRAD (max) is specified as a reference point
only. If tRAD is greater than the specified tRAD (max) limit, then access time is controlled by tAA.
13) For CAS-before-RAS cycles only.
Semiconductor Group
579
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