HYS64D32000GU-7-B [INFINEON]
184-Pin Unbuffered Dual-In-Line Memory Modules; 184针无缓冲双列直插式内存模块
| 型号： | HYS64D32000GU-7-B |
| 厂家： | 
Infineon |
| 描述： | 184-Pin Unbuffered Dual-In-Line Memory Modules |
| 文件： | 总51页 (文件大小：1296K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Data Sheet, V1.1, July 2003
HYS[64/72]D64x20GU-x-B
HYS[64/72]D32x00[G/E]U-x-B
HYS64D16301GU-x-B
184-Pin Unbuffered Dual-In-Line Memory Modules
UDIMM
DDR SDRAM
Memory Products
N e v e r s t o p t h i n k i n g .
Edition 2003-07
Published by Infineon Technologies AG,
St.-Martin-Strasse 53,
81669 München, Germany
© Infineon Technologies AG 2003.
All Rights Reserved.
Attention please!
The information herein is given to describe certain components and shall not be considered as a guarantee of
characteristics.
Terms of delivery and rights to technical change reserved.
We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding
circuits, descriptions and charts stated herein.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest
Infineon Technologies Office (www.infineon.com).
Warnings
Due to technical requirements components may contain dangerous substances. For information on the types in
question please contact your nearest Infineon Technologies Office.
Infineon Technologies Components may only be used in life-support devices or systems with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
Data Sheet, V1.1, July 2003
HYS[64/72]D64x20GU-x-B
HYS[64/72]D32x00[G/E]U-x-B
HYS64D16301GU-x-B
184-Pin Unbuffered Dual-In-Line Memory Modules
UDIMM
DDR SDRAM
Memory Products
N e v e r s t o p t h i n k i n g .
HYS[64/72]D64x20GU-x-B, HYS[64/72]D32x00[G/E]U-x-B, HYS64D16301GU-x-B
Revision History:
V1.1
2003-07
Previous Version:
V1.01
2003-01
Page
all
Subjects (major changes since last revision)
new data sheet template
all
replace bank by rank if DIMM related (4 bank SDRAM on 1 or 2 rank DIMM)
Table 6: Address Table updated
10
19ff
20ff
24f
26f
29ff
41ff
Table 10ff: IDD conditions now in seperate table
Table 11ff: added part numbers to IDD tables
Table 15: split in two tables (now 15 & 16)
Table 16: add –5 (DDR400)
Chapter 4: added part numbers to SPD tables
Table 21: set Bytes 47-55 to not used (00hex); set byte 62 to SPD rev. 0.0 (00hex); update
Checksum (TPCR)
8
Table 4: Changed RAS/CAS/WE description to command inputs and amended CLK to CK
Table 5: Changed CLK to CK
9
44ff
Figure 7 - Figure 13 Amended and updated package outline drawings
We Listen to Your Comments
Any information within this document that you feel is wrong, unclear or missing at all?
Your feedback will help us to continuously improve the quality of this document.
Please send your proposal (including a reference to this document) to:
techdoc.mp@infineon.com
Template: mp_a4_v2.0_2003-06-06.fm
HYS[64/72]D[16x01/32x00/64x20][G/E]U-[5/6/7/8]-B
Unbuffered DDR SDRAM Modules
Table of Contents
1
1.1
1.2
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Current Conditions and Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.1
3.2
3.3
4
5
SPD Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Data Sheet
5
V1.1, 2003-07
184-Pin Unbuffered Dual-In-Line Memory Modules
UDIMM
HYS[64/72]D64x20GU-x-B
HYS[64/72]D32x00[G/E]U-x-B
HYS64D16301GU-x-B
1
Overview
1.1
Features
•
184-Pin Unbuffered Dual-In-Line Memory Modules (ECC and non-parity) for PC and Server main memory
applications
•
•
•
•
•
•
•
•
•
•
•
•
One rank 16M x 64, 32M × 64, 32M × 72 and two ranks 64M × 64, 64M × 72 organization
JEDEC standard Double Data Rate Synchronous DRAMs (DDR SDRAM) Single +2.5V (±0.2V) power supply
Built with 256 Mbit DDR SDRAM in P-TSOPII-66-1 package
Programmable CAS Latency, Burst Length, and Wrap Sequence (Sequential & Interleave)
Auto Refresh (CBR) and Self Refresh
All inputs and outputs SSTL_2 compatible
Serial Presence Detect with E2PROM
JEDEC standard MO-206 form factor: 133.35 mm × 31.75 mm × 4.00 mm max.
Jedec standard reference layout
Gold plated contacts
DDR400 Speed Grade supported
Lead- & halogene-free DIMM available
Table 1
Performance
Part Number Speed Code
Module Speed Grade
Component Module
–5
–6
–7F
–7
–8
Unit
–
DDR400B DDR333B DDR266
DDR266A DDR200
PC3200
-3033
PC2700
-2533
PC2100
-2022
PC2100
-2033
PC1600
-2022
–
max. Clock
Frequency
@ CL = 3 fCK3
200
166
133
166
166
133
–
–
–
MHz
MHz
MHz
@ CL = 2.5 fCK2.5
@ CL = 2 fCK2
143
133
143
133
125
100
1.2
Description
The HYS[64/72]D64x20GU-x-B, HYS[64/72]D32x00[G/E]U-x-B, and HYS64D16301GU-x-B are industry standard
184-Pin Unbuffered Dual-In-Line Memory Modules (UDIMM) organized as 32M × 64 and 64M × 64 for non-parity
and 32M × 72 and 64M × 72 for ECC main memory applications. The memory array is designed with 256Mbit
Double Data Rate Synchronous DRAMs. A variety of decoupling capacitors are mounted on the printed
circuit board. The DIMMs feature serial presence detect (SPD) based on a serial E2PROM device using the 2-pin
I2C protocol. The first 128 bytes are programmed with configuration data and the second 128 bytes are available
to the customer
Data Sheet
6
V1.1, 2003-07
HYS[64/72]D[16x01/32x00/64x20][G/E]U-[5/6/7/8]-B
Unbuffered DDR SDRAM Modules
Overview
Table 2
Type
Ordering Information
Compliance Code
Description
SDRAM Technology
PC3200 (CL=3)
HYS64D16301GU-5-B
HYS64D32300GU-5-B
HYS72D32300GU-5-B
HYS64D64320GU-5-B
HYS72D64320GU-5-B
PC3200U-30330-C0
PC3200U-30330-A0
PC3200U-30330-A0
PC3200U-30330-B0
PC3200U-30330-B0
one rank 128MB DIMM
one rank 256MB DIMM
256 Mbit (× 16)
256 Mbit (× 8)
one rank 256MB ECC-DIMM 256 Mbit (× 8)
two ranks 512MB DIMM 256 Mbit (× 8)
two ranks 512MB ECC-DIMM 256 Mbit (× 8)
PC2700 (CL=2.5)
HYS64D16301GU-6-B
HYS64D32300GU-6-B
HYS72D32300GU-6-B
HYS64D64320GU-6-B
HYS72D64320GU-6-B
PC2700U-25330-C0
PC2700U-25330-A0
PC2700U-25330-A0
PC2700U-25330-B0
PC2700U-25330-B0
one rank 128MB DIMM
one rank 256MB DIMM
256 Mbit (× 16)
256 Mbit (× 8)
one rank 256MB ECC-DIMM 256 Mbit (× 8)
two ranks 512MB DIMM 256 Mbit (× 8)
two ranks 512MB ECC-DIMM 256 Mbit (× 8)
PC2100 (CL=2)
HYS64D16301GU-7-B
HYS64D32000GU-7-B
HYS72D32000GU-7F-B
HYS72D32000GU-7-B
HYS64D64020GU-7-B
HYS72D64020GU-7F-B
HYS72D64020GU-7-B
PC2100U-20330-C2
PC2100U-20330-A1
PC2100U-20220-A1
PC2100U-20330-A1
PC2100U-20330-B1
PC2100U-20220-B1
PC2100U-20330-B1
one rank 128MB DIMM
one rank 256MB DIMM
256 Mbit (× 16)
256 Mbit (× 8)
one rank 256MB ECC-DIMM 256 Mbit (× 8)
one rank 256MB ECC-DIMM 256 Mbit (× 8)
two ranks 512MB DIMM
256 Mbit (× 8)
two ranks 512MB ECC-DIMM 256 Mbit (× 8)
two ranks 512MB ECC-DIMM 256 Mbit (× 8)
PC1600 (CL=2)
HYS64D16301GU-8-B
HYS64D32000GU-8-B
HYS72D32000GU-8-B
HYS64D64020GU-8-B
HYS72D64020GU-8-B
PC1600U-20330-C2
PC1600U-20220-A1
PC1600U-20220-A1
PC1600U-20220-B1
PC1600U-20220-B1
one rank 128MB DIMM
one rank 256MB DIMM
256 Mbit (× 16)
256 Mbit (× 8)
one rank 256MB ECC-DIMM 256 Mbit (× 8)
two ranks 512MB DIMM 256 Mbit (× 8)
two ranks 512MB ECC-DIMM 256 Mbit (× 8)
Table 3
Lead- and Halogene-Free DIMM
Type
Compliance Code
Description
SDRAM Technology
256 Mbit (× 8)
PC2100 (CL=2)
HYS64D32300EU-7-B
PC2100U-20330-A1
one rank 256MB DIMM
Note:All part numbers end with a place code designating the silicon-die revision. Reference information available
on request. Example: HYS72D32000GU-6-B, indicating rev. B dies are used for SDRAM components. The
Compliance Code is printed on the module labels describing the speed sort (for example “PC2700”), the
latencies and SPD code definition (for example “20330” means CAS latency of 2.0 clocks, RCD1) latency of
3 clocks, Row Precharge latency of 3 clocks, and JEDEC SPD code definiton version 0), and the Raw Card
used for this module.
1) RCD: Row-Column-Delay
Data Sheet
7
V1.1, 2003-07
HYS[64/72]D[16x01/32x00/64x20][G/E]U-[5/6/7/8]-B
Unbuffered DDR SDRAM Modules
Pin Configuration
2
Pin Configuration
Table 4
Pin Definitions and Functions
Symbol
Type1)
Function
A0 - A12
BA0, BA1
DQ0 - DQ63
CB0 - CB7
I
Address Inputs
I
Bank Selects
I/O
I/O
Data Input/Output
Check Bits (× 72 organization only)
Command Inputs
RAS, CAS, WE
CKE0 - CKE1
DQS0 - DQS8
CK0 - CK2,
I
I
Clock Enable
I/O
SDRAM low data strobes
SDRAM clock (positive lines)
SDRAM clock (negative lines)
I
I
CK0 - CK2
DM0 - DM8
DQS9 - DQS17
I
SDRAM low data mask/
high data strobes
I/O
S0, S1
VDD
I
Chip Selects for Rank0 and Rank1
Power (+2.5 V)
PWR
GND
PWR
PWR
AI
VSS
Ground
VDDQ
VDDID
VREF
I/O Driver power supply
VDD Indentification flag
I/O reference supply
Serial EEPROM power supply
Serial bus clock
VDDSPD
SCL
PWR
I
SDA
I/O
Serial bus data line
slave address select
Not Connected
SA0 - SA2
NC
I
NC
1) I: Input; O: Output; I/O: bidirectional In-/Output; AI: Analog Input; PWR: Power Supply; GND: Signal Ground; NC: Not
Connected
Note:S1 and CKE1 are used on two rank modules only
Data Sheet
8
V1.1, 2003-07
HYS[64/72]D[16x01/32x00/64x20][G/E]U-[5/6/7/8]-B
Unbuffered DDR SDRAM Modules
Pin Configuration
Table 5
Pin Configuration
PIN#
Frontside
Backside
PIN#
Symbol
Symbol
PIN#
Symbol
PIN#
Symbol
1
VREF
48
A0
93
VSS
140
NC /
DM8/DQS17
2
DQ0
VSS
49
50
51
52
NC / CB2
VSS
94
DQ4
141
142
143
144
A10
3
95
DQ5
NC / CB6
VDDQD
4
DQ1
DQS0
DQ2
VDD
NC / CB3
BA1
96
VDDQD
DM0/DQS9
DQ6
5
97
NC / CB7
Key
6
Key
98
7
99
DQ7
8
DQ3
NC
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
DQ32
VDDQ
DQ33
DQS4
DQ34
VSS
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
VSS
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
VSS
9
NC
DQ36
DQ37
VDD
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
NC
NC
VSS
NC
DQ8
DQ9
DQS1
VDDQ
CK1
CK1
VSS
VDDQ
DM4/DQS13
DQ38
DQ39
VSS
DQ12
DQ13
DM1/DQS10
VDD
BA0
DQ35
DQ40
VDDQ
WE
DQ44
RAS
DQ14
DQ15
CKE1
VDDQ
DQ45
VDDQ
DQ10
DQ11
CKE0
VDDQ
DQ16
DQ17
DQS2
VSS
DQ41
CAS
VSS
S0
NC (BA2)
DQ20
NC / A12
VSS
S1
DQS5
DQ42
DQ43
VDD
DM5/DQS14
VSS
DQ46
DQ47
NC
DQ21
A11
NC
A9
DQ48
DQ49
VSS
DM2/DQS11
VDD
VDDQ
DQ18
A7
DQ52
DQ53
NC (A13)
VDD
DQ22
A8
VDDQ
DQ19
A5
CK2
CK2
DQ23
VSS
VDDQ
DQS6
DQ50
DQ51
VSS
DM6/DQS15
DQ54
DQ55
VDDQ
DQ24
VSS
A6
DQ28
DQ29
VDDQ
DQ25
DQS3
A4
NC
VDDID
DQ56
DQ57
DM3/DQS12
A3
DQ60
DQ61
VSS
VDD
DQ26
DQ30
Data Sheet
9
V1.1, 2003-07
HYS[64/72]D[16x01/32x00/64x20][G/E]U-[5/6/7/8]-B
Unbuffered DDR SDRAM Modules
Pin Configuration
Table 5
Pin Configuration (cont’d)
Frontside
Backside
PIN#
40
Symbol
PIN#
85
Symbol
PIN#
132
133
134
135
136
137
138
139
Symbol
VSS
PIN#
177
178
179
180
181
182
183
184
Symbol
DM7/DQS16
DQ62
DQ63
VDDQ
DQ27
A2
VDD
41
86
DQS7
DQ58
DQ59
VSS
DQ31
NC / CB4
NC / CB5
VDDQ
42
VSS
87
43
A1
88
44
NC / CB0
NC / CB1
VDD
89
SA0
45
90
NC
CK0
SA1
46
91
SDA
SCL
CK0
SA2
47
NC / DQS8
92
VSS
VDDSPD
Note:Pins 44, 45, 47, 49, 51, 134, 135, 140 and 144 are NC (“not connected”) on × 64 organised non-ECC
modules.
Table 6
Address Format
Density Organization Memory SDRAMs # of
# of row/bank/ Refresh Period Interval
SDRAMs columns bits
Ranks
128MB
256MB
256MB
512MB
512MB
16M × 64
32M × 64
32M × 72
64M × 64
64M × 72
1
1
1
2
2
16M × 16
32M × 8
32M × 8
32M × 8
32M × 8
4
13/2/10
13/2/11
13/2/11
13/2/11
13/2/11
8K
8K
8K
8K
8K
64 ms 7.8 µs
64 ms 7.8 µs
64 ms 7.8 µs
64 ms 7.8 µs
64 ms 7.8 µs
8
9
16
18
Data Sheet
10
V1.1, 2003-07
HYS[64/72]D[16x01/32x00/64x20][G/E]U-[5/6/7/8]-B
Unbuffered DDR SDRAM Modules
Pin Configuration
S0
S
LDQS
LDM
DQS1
DM1/DQS10
DQS5
DM5/DQS14
LDQS
LDM
S
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
UDQS
UDM
I/O 8
DQ8
DQ9
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
D2
D0
DQ10
DQ11
DQ12
DQ13
DQ14
I/O 6
DQ15
I/O 7
DQS0
DM0/DQS9
DQS4
UDQS
UDM
I/O 8
DM4/DQS13
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
I/O 9
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
DQ39
DQ7
S
DQS3
DQS7
DM7/DQS16
LDQS
LDM
S
LDQS
LDM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
UDQS
UDM
I/O 8
DM3/DQS12
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
UDQS
UDM
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
D1
D3
DQS2
DM2/DQS11
DQS6
DM6/DQS15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
* Clock Wiring
Serial PD
Clock
Input
SDRAMs
SCL
SDA
NC
2 SDRAMs
2 SDRAMs
*CK0/CK0
*CK1/CK1
*CK2/CK2
VDD SPD
WP
A0
SPD
A1
A2
V
DD/VDDQ
D0 - D3
SA0 SA1
SA2
* Wire per Clock Loading
Table/Wiring Diagrams
VREF
VSS
D0 - D3
D0 - D3
Notes:
VDDID
Strap: see Note 4
1. DQ-to-I/O wiring is shown as recommended but may
be changed.
2. DQ/DQS/DM/CKE/S relationships must be main-
tained as shown.
3. DQ, DQS, DM/DQS resistors: 22 ohms ± 5%.
4. VDDID strap connections
BA0-BA1: SDRAMs D0 - D3
A0-A13: SDRAMs D0 - D3
RAS: SDRAMs D0 - D3
BA0 - BA1
A0 - A13
RAS
(for memory device VDD, VDDQ):
STRAP OUT (OPEN): VDD = VDDQ
STRAP IN (VSS): VDD ≠ VDDQ
CAS
CKE0
WE
CAS: SDRAMs D0 - D3
CKE: SDRAMs D0 - D3
WE: SDRAMs D0 - D3
5. BAx, Ax, RAS, CAS, WE resistors: 7.5 ohms ± 5%
Figure 1
Block Diagram - One Rank 16M × 64 DDR SDRAM DIMM HYS64D16301GU using × 16
organized SDRAMs
Data Sheet
11
V1.1, 2003-07
HYS[64/72]D[16x01/32x00/64x20][G/E]U-[5/6/7/8]-B
Unbuffered DDR SDRAM Modules
Pin Configuration
S0
DQS0
DM0/DQS9
DQS4
DM4/DQS13
DM
I/O 0
S
DQS
DQS
S
DM
I/O 0
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D4
D0
DQS5
DM5/DQS14
DQS1
DM1/DQS10
DQS
DM
S
DQS
S
DM
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ8
DQ9
DQ10
DQ11
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D5
D1
DQ12
DQ13
DQ14
DQ15
DQS6
DM6/DQS15
DQS2
DM2/DQS11
S
DM
DQS
S
DM
DQS
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ16
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D6
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
D2
DQS7
DM7/DQS16
DQS3
DM3/DQS12
S
DM
DQS
S
DQS
DM
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ24
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
D7
D3
Serial PD
* Clock Wiring
Clock
Input
SCL
SDRAMs
SDA
WP
A0
2 SDRAMs
3 SDRAMs
3 SDRAMs
A1
A2
*CK0/CK0
*CK1/CK1
*CK2/CK2
SA0 SA1 SA2
* Wire per Clock Loading
Table/Wiring Diagrams
Notes:
1. DQ-to-I/O wiring is shown as recommended
but may be changed.
2. DQ/DQS/DM/CKE/S relationships must be
maintained as shown.
3. DQ, DQS, DM/DQS resistors: 22 ohms ± 5%
4. VDDID strap connections
BA0-BA1: SDRAMs D0 - D7
A0-A13: SDRAMs D0 - D7
BA0 - BA1
A0 - A13
RAS
RAS: SDRAMs D0 - D7
CAS: SDRAMs D0 - D7
VDD SPD
SPD
CAS
V
DD/VDDQ
VREF
CKE0
WE
CKE: SDRAMs D0 - D7
WE: SDRAMs D0 - D7
(for memory device VDD, VDDQ):
STRAP OUT (OPEN): VDD = VDDQ
STRAP IN (VSS): VDD ≠ VDDQ
D0 - D7
D0 - D7
D0 - D7
.
VSS
5. BAx, Ax, RAS, CAS, WE resistors: 5.1 ohms
+5%
VDDID
Strap: see Note 4
Figure 2
Block Diagram - One Rank 32M × 64 DDR-I SDRAM DIMM HYS64D32x00GU / HYS64D32300EU
using × 8 organized SDRAMs
Data Sheet
12
V1.1, 2003-07
HYS[64/72]D[16x01/32x00/64x20][G/E]U-[5/6/7/8]-B
Unbuffered DDR SDRAM Modules
Pin Configuration
S1
S0
DQS4
DM4/DQS13
DQS0
DM0/DQS9
DQS
DM
I/O 0
DQS
DM
I/O 0
S
S
DQS
S
DQS
DM
I/O 0
DM
S
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D12
D4
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D8
D0
DQS5
DM5/DQS14
DQS1
DM1/DQS10
DM
DM
S
S
DQS
DQS
DQS
DQS
S
DM
DM
S
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ8
DQ9
DQ10
DQ11
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D13
D5
D9
D1
DQ12
DQ13
DQ14
DQ15
DQS6
DM6/DQS15
DQS2
DM2/DQS11
DM
S
DM
S
DQS
DQS
DQS
DM
S
DQS
DM
S
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ48
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ16
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ49
DQ50
DQ51
D6
D14
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
D2
D10
DQ52
DQ53
DQ54
DQ55
DQS7
DM7/DQS16
DQS3
DM3/DQS12
DM
S
DQS
DM
S
DQS
S
DM
S
DM
DQS
DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ56
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ24
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
D15
D7
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
D11
D3
VDD SPD
SPD
V
DD/VDDQ
D0 - D15
Serial PD
VREF
VSS
D0 - D15
D0 - D15
SCL
SDA
Notes:
WP
A0
A1
A2
VDDID
Strap: see Note 4
SA0 SA1 SA2
1. DQ-to-I/O wiring is shown as recommended
but may be changed.
2. DQ/DQS/DM/CKE/S relationships must be
maintained as shown.
3. DQ, DQS, DM/DQS resistors: 22 ohms ± 5%.
4. VDDID strap connections
* Clock Wiring
BA0-BA1: SDRAMs D0 - D15
A0-A13: SDRAMs D0 - D15
BA0 - BA1
A0 - A13
Clock
Input
SDRAMs
CKE1
RAS
CKE: SDRAMs D8 - D15
RAS: SDRAMs D0 - D15
4 SDRAMs
6 SDRAMs
6 SDRAMs
*CK0/CK0
*CK1/CK1
*CK2/CK2
(for memory device VDD, VDDQ):
STRAP OUT (OPEN): VDD = VDDQ
STRAP IN (VSS): VDD ≠ VDDQ
CAS
CKE0
WE
CAS: SDRAMs D0 - D15
CKE: SDRAMs D0 - D7
WE: SDRAMs D0 - D15
* Wire per Clock Loading
Table/Wiring Diagrams
5. BAx, Ax, RAS, CAS, WE resistors: 3 ohms
+5%
Figure 3
Block Diagram - Two Rank 64M × 64 DDR-I SDRAM DIMM HYS64D64x20GU using × 8
organized SDRAMs
Data Sheet
13
V1.1, 2003-07
HYS[64/72]D[16x01/32x00/64x20][G/E]U-[5/6/7/8]-B
Unbuffered DDR SDRAM Modules
Pin Configuration
S0
DQS0
DM0/DQS9
DQS4
DM4/DQS13
DM
I/O 0
DQS
S
DQS
DQS
DQS
S
DM
I/O 0
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D4
D0
DQS5
DM5/DQS14
DQS1
DM1/DQS10
DQS
DM
S
S
DM
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ8
DQ9
DQ10
DQ11
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D5
D1
DQ12
DQ13
DQ14
DQ15
DQS6
DM6/DQS15
DQS2
DM2/DQS11
DM
S
DQS
DM
S
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ16
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D6
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
D2
DQS7
DM7/DQS16
DQS3
DM3/DQS12
S
DM
DQS
S
DM
DQS
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ24
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
D7
D3
DQS8
* Clock Wiring
DM8/DQS17
Clock
Input
SDRAMs
Serial PD
DM
S
DQS
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
3 SDRAMs
3 SDRAMs
3 SDRAMs
SCL
*CK0/CK0
*CK1/CK1
*CK2/CK2
D8
SDA
WP
A0
A1
A2
* Wire per Clock Loading
Table/Wiring Diagrams
SA0 SA1
SA2
Notes:
1. DQ-to-I/O wiring is shown as recommended
BA0 - BA1
BA0-BA1: SDRAMs D0 - D8
A0-A13: SDRAMs D0 - D8
but may be changed.
2. DQ/DQS/DM/CKE/S relationships must be
maintained as shown.
A0 - A13
RAS
VDDSPD
DD/VDDQ
SPD
RAS: SDRAMs D0 - D8
V
D0 - D8
3. DQ, DQS, DM/DQS resistors: 22 ohms ± 5%.
CAS
CKE0
WE
CAS: SDRAMs D0 - D8
CKE: SDRAMs D0 - D8
WE: SDRAMs D0 - D8
4. VDDID strap connections
VREF
VSS
D0 - D8
D0 - D8
(for memory device VDD, VDDQ):
STRAP OUT (OPEN): VDD = VDDQ
STRAP IN (VSS): VDD ≠ VDDQ
.
VDDID
Strap: see Note 4
5. BAx, Ax, RAS, CAS, WE resistors: 5.1 ohm
+5%
Figure 4
Block Diagram - One Rank 32M × 72 DDR-I SDRAM DIMM HYS72D32x00GU using × 8
organized SDRAMs
Data Sheet
14
V1.1, 2003-07
HYS[64/72]D[16x01/32x00/64x20][G/E]U-[5/6/7/8]-B
Unbuffered DDR SDRAM Modules
Pin Configuration
S1
S0
DQS4
DM4/DQS13
DQS0
DM0/DQS9
DQS
DM
I/O 0
DM
I/O 0
DQS
S
S
DM
I/O 0
DQS
DM
S
S
DQS
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D4
D13
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D9
D0
DQS5
DM5/DQS14
DQS1
DM1/DQS10
DQS
DM
DM
S
S
DQS
DM
DQS
DQS
S
DM
S
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ8
DQ9
DQ10
DQ11
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D5
D14
D10
D1
DQ12
DQ13
DQ14
DQ15
DQS6
DM6/DQS15
DQS2
DM2/DQS11
DM
DM
S
DQS
S
DQS
DQS
DM
S
S
DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ16
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D15
D6
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
D11
D2
DQS7
DM7/DQS16
DQS3
DM3/DQS12
S
DM
S
DM
DQS
DQS
DM
S
DQS
DM
S
DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ56
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ24
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
D16
D7
DQ25
DQ26
DQ27
D3
D12
DQ28
DQ29
DQ30
DQ31
V
DD SPD
SPD
* Clock Wiring
DQS8
DM8/DQS17
VDD/VDDQ
Clock
Input
D0 - D17
SDRAMs
DM
DM
DQS
S
DQS
S
VREF
VSS
D0 - D17
D0 - D17
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
6 SDRAMs
6 SDRAMs
6 SDRAMs
*CK0/CK0
*CK1/CK1
*CK2/CK2
D17
D8
VDDID
* Wire per Clock Loading
Table/Wiring Diagrams
Strap: see Note 4
Notes:
1. DQ-to-I/O wiring is shown as recommended
but may be changed.
2. DQ/DQS/DM/CKE/S relationships must be
maintained as shown.
3. DQ, DQS, DM/DQS resistors: 22 ohms ± 5%.
4. VDDID strap connections
BA0 - BA1
A0 - A13
CKE1
BA0-BA1: SDRAMs D0 - D17
A0-A13: SDRAMs D0 - D17
CKE: SDRAMs D9 - D17
RAS: SDRAMs D0 - D17
Serial PD
RAS
SCL
SDA
CAS
CKE0
WE
CAS: SDRAMs D0 - D17
CKE: SDRAMs D0 - D8
WE: SDRAMs D0 - D17
(for memory device VDD, VDDQ):
STRAP OUT (OPEN): VDD = VDDQ
STRAP IN (VSS): VDD ≠ VDDQ
WP
A0
A1
A2
SA0 SA1 SA2
5. BAx, Ax, RAS, CAS, WE resistors: 3 ohms
+5%
Figure 5
Block Diagram - Two Rank 64M × 72 DDR-I SDRAM DIMM HYS72D64x20GU using × 8
organized SDRAMs
Data Sheet
15
V1.1, 2003-07
HYS[64/72]D[16x01/32x00/64x20][G/E]U-[5/6/7/8]-B
Unbuffered DDR SDRAM Modules
Pin Configuration
6 DRAM Loads
DRAM1
DRAM2
DRAM3
R = 120 Ω ± 5%
CK
DIMM
Connector
4 DRAM Loads
DRAM4
DRAM5
DRAM1
CK
DRAM2
Cap.
R = 120 Ω ± 5%
DRAM6
DRAM1
DIMM
Connector
Cap.
3 DRAM Loads
DRAM5
Cap.
DRAM6
R = 120 Ω ± 5%
DRAM3
DIMM
Connector
Cap.
2 DRAM Loads
DRAM1
DRAM5
Cap.
Cap.
Cap.
Cap.
R = 120 Ω ± 5%
DIMM
Connector
1 DRAM Loads
Cap.
DRAM5
Cap.
R = 120 Ω ± 5%
DRAM3
Cap.
DIMM
Connector
Cap.
Cap.
Cap.
Cap. = 1/2 DDR SDRAM input capacitance; 1.0 pF ± 20%
Figure 6
Clock Net Wiring
Data Sheet
16
V1.1, 2003-07
HYS[64/72]D[16x01/32x00/64x20][G/E]U-[5/6/7/8]-B
Unbuffered DDR SDRAM Modules
Electrical Characteristics
3
Electrical Characteristics
3.1
Operating Conditions
Table 7
Absolute Maximum Ratings
Parameter
Symbol
Values
typ.
–
Unit Note/ Test
Condition
min.
VIN, VOUT -0.5
max.
Voltage on I/O pins relative to VSS
VDDQ
+
V
–
0.5
Voltage on Inputs relative to VSS
Voltage on VDD supply relative to VSS
Voltage on VDDQ supply relative to VSS
Operating Temperature (Ambient)
Storage Temperature
VIN
-0.5
-0.5
-0.5
0
–
+3.6
+3.6
+3.6
+70
+150
–
V
–
–
–
–
–
–
–
VDD
VDDQ
TA
–
V
–
V
–
° C
° C
W
mA
TSTG
PD
-55
–
–
Power dissipation (per SDRAM component)
Short Circuit Output Current
1
IOUT
–
50
–
Attention: Permanent device damage may occur if “Absolute Maximum Ratings” are exceeded. Functional
operation should be restricted to recommended operation conditions. Exceeding only one of
these values for extended periods of time affect device reliability and may cause irreversible
damage to the integrated circuit.
Table 8
Supply Voltage Levels
Symbol Limit Values
Parameter
Unit Note/ Test Condition
min.
2.3
2.5
2.3
2.5
nom.
2.5
max.
2.7
Device Supply Voltage
Device Supply Voltage
Output Supply Voltage
Output Supply Voltage
VDD
V
V
V
V
V
V
fCK ≤166 MHz
CK > 166 MHz 1)
fCK ≤166 MHz 2)
CK > 166 MHz 1)2)
fCK ≤166 MHz 3)
CK > 166 MHz 1)3)
VDD
2.6
2.7
f
VDDQ
VDDQ
2.5
2.7
2.6
2.7
f
Input Reference Voltage VREF
0.49 × VDDQ 0.5 × VDDQ 0.51 × VDDQ
DDQ / 2 –50 VDDQ / 2 DDQ/ 2 + 50
mV mV
REF – 0.04
EEPROM supply voltage VDDSPD 2.3
Input Reference Voltage VREF
V
V
f
4)
Termination Voltage
VTT
V
VREF
V
REF + 0.04
V
V
2.5
3.6
—
1) DDR400 conditions apply for all clock frequencies above 166 MHz
2) Under all conditions, VDDQ must be less than or equal to VDD
.
3) Peak to peak AC noise on VREF may not exceed ± 2% VREF (DC). VREF is also expected to track noise variations in VDDQ
4) VTT of the transmitting device must track VREF of the receiving device.
.
Data Sheet
17
V1.1, 2003-07
HYS[64/72]D[16x01/32x00/64x20][G/E]U-[5/6/7/8]-B
Unbuffered DDR SDRAM Modules
Electrical Characteristics
Table 9
DC Operating Conditions (SSTL_2 Inputs)
Parameter
Symbol
Values
max.
Unit Note/ Test Condition 1)
min.
2)
DC Input Logic High
DC Input Logic Low
Input Leakage Current
Output Leakage Current
VIH (DC)
VIL (DC)
IIL
VREF + 0.15
– 0.30
– 5
VDDQ + 0.3
V
VREF – 0.15
V
–
3)
5
5
µA
µA
3)
IOL
– 5
1) VDDQ = 2.5 V, TA = 70 °C, Voltage Referenced to VSS
2) The relationship between the VDDQ of the driving device and the VREF of the receiving device is what determines noise
margins. However, in the case of VIH (max.) (input overdrive), it is the VDDQ of the receiving device that is referenced. In the
case where a device is implemented such that it supports SSTL_2 inputs but has no SSTL_2 outputs (such as a translator),
and therefore no VDDQ supply voltage connection, inputs must tolerate input overdrive to 3.0 V (High corner
VDDQ + 300 mV).
3) For any pin under test input of 0 V ≤VIN ≤VDDQ + 0.3 V. Values are shown per DDR SDRAM component
Data Sheet
18
V1.1, 2003-07
HYS[64/72]D[16x01/32x00/64x20][G/E]U-[5/6/7/8]-B
Unbuffered DDR SDRAM Modules
Electrical Characteristics
3.2
Current Conditions and Specification
Table 10
IDD Conditions
Parameter
Symbol
Operating Current 0
IDD0
one bank; active/ precharge; tRC = tRC,MIN
;
DQ, DM, and DQS inputs changing once per clock cycle;
address and control inputs changing once every two clock cycles.
Operating Current 1
IDD1
one bank; active/read/precharge; Burst Length = 4; see component data sheet.
Precharge Power-Down Standby Current
all banks idle; power-down mode; CKE ≤VIL,MAX
IDD2P
IDD2F
Precharge Floating Standby Current
CS ≥ VIH,,MIN, all banks idle; CKE ≥ VIH,MIN
;
address and other control inputs changing once per clock cycle; VIN = VREF for DQ, DQS and DM.
Precharge Quiet Standby Current
IDD2Q
CS ≥ VIHMIN, all banks idle; CKE ≥ VIH,MIN
;
address and other control inputs stable at ≥ VIH,MIN or ≤VIL,MAX; VIN = VREF for DQ, DQS and DM.
Active Power-Down Standby Current
one bank active; power-down mode; CKE ≤VILMAX; VIN = VREF for DQ, DQS and DM.
IDD3P
IDD3N
Active Standby Current
one bank active; CS ≥ VIH,MIN; CKE ≥ VIH,MIN; tRC = tRAS,MAX
DQ, DM and DQS inputs changing twice per clock cycle;
address and control inputs changing once per clock cycle.
;
Operating Current Read
IDD4R
one bank active; Burst Length = 2; reads; continuous burst;
address and control inputs changing once per clock cycle;
50% of data outputs changing on every clock edge;
CL = 2 for DDR266(A), CL = 3 for DDR333 and DDR400B; IOUT = 0 mA
Operating Current Write
IDD4W
one bank active; Burst Length = 2; writes; continuous burst;
address and control inputs changing once per clock cycle;
50% of data outputs changing on every clock edge;
CL = 2 for DDR266(A), CL = 3 for DDR333 and DDR400B
Auto-Refresh Current
IDD5
IDD6
IDD7
tRC = tRFCMIN, distributed refresh
Self-Refresh Current
CKE ≤0.2 V; external clock on
Operating Current 7
four bank interleaving with Burst Length = 4; see component data sheet.
Data Sheet
19
V1.1, 2003-07
HYS[64/72]D[16x01/32x00/64x20][G/E]U-[5/6/7/8]-B
Unbuffered DDR SDRAM Modules
Electrical Characteristics
Table 11
Operating, Standby and Refresh Currents (PC2100, –8)
Unit Note1)2)
128MB × 64
256MB × 64
256MB × 72
512MB × 64
512MB × 72
1 rank
1 rank
1 rank
2 ranks
2 ranks
Symbol
IDD0
typ.
288
332
20
max. typ.
max. typ.
720 630
800 720
max. typ.
max. typ.
1080 990
1160 1080 1305 mA
max.
3)
380
420
28
560
640
40
810
900
63
880
960
80
1215 mA
3)4)
5)
IDD1
IDD2P
IDD2F
IDD2Q
IDD3P
IDD3N
IDD4R
IDD4W
IDD5
56
45
112
560
352
256
720
90
126
630
396
288
810
mA
mA
mA
mA
mA
5)
120
72
140
88
240
144
104
320
632
680
280
176
128
360
760
840
270
162
117
360
711
765
315
198
144
405
855
945
480
288
208
640
952
540
324
234
720
5)
5)
52
64
5)
168
356
384
200
440
480
3)4)
3)
1120 1071 1260 mA
1000 1200 1125 1350 mA
3)
504.8 680
1010 1360 1136 1530 1330 1720 1496 1935 mA
12 20 13.5 22.5 24 40 27 45 mA
1200 1680 1350 1890 1520 2040 1710 2295 mA
5)
IDD6
6
10
3)4)
IDD7
632
880
1) DRAM component currents only
2) Test condition for maximum values: VDD = 2.7 V, TA = 10 °C
3) The module IDDx values are calculated from the component IDDx data sheet values as:
m × IDDx[component] + n × IDD3N[component] with m and n number of components of rank 1 and 2; n=0 for 1 rank modules
4) DQ I/O (IDDQ) currents are not included into calculations: module IDD values will be measured differently depending on load
conditions
5) The module IDDx values are calculated from the corrponent IDDx data sheet values as: (m + n) × IDDx[component]
Data Sheet
20
V1.1, 2003-07
HYS[64/72]D[16x01/32x00/64x20][G/E]U-[5/6/7/8]-B
Unbuffered DDR SDRAM Modules
Electrical Characteristics
Table 12
Operating, Standby and Refresh Currents (PC2100, –7 & –7F)
Unit Note
1)2)
128MB
256MB
256MB
512MB
512MB
512MB
512MB
× 64
× 64
× 72
× 64
× 72
× 72
× 72
1 rank
1 rank
1 rank
1 rank
1 rank
2 ranks
2 ranks
Sym- typ. max. typ. max. typ. max. typ. max. typ. max. typ. max. typ. max.
bol
3)
IDD0
IDD1
308 420
376 460
600 800 675 900 747 990 1000 1240 1125 1395 1197 1485 mA
720 880 810 990 882 1080 1120 1320 1260 1485 1332 1575 mA
44 64 49.5 72 49.5 72 88 128 99 144 99 144 mA
3)4)
5)
IDD2P 22 32
IDD2F 140 160
IDD2Q 80 100
IDD3P 60 72
IDD3N 208 240
IDD4R 428 520
IDD4W 476 560
5)
280 320 315 360 315 360 560 640 630 720 630 720 mA
160 200 180 225 180 225 320 400 360 450 360 450 mA
120 144 135 162 135 162 240 288 270 324 270 324 mA
400 440 450 495 450 495 800 880 900 990 900 990 mA
760 920 855 1035 855 1035 1160 1360 1305 1530 1305 1530 mA
840 1000 945 1125 945 1125 1240 1440 1395 1620 1395 1620 mA
1080 1440 1215 1620 1217 1620 1480 1880 1665 2115 1667 2115 mA
5)
5)
5)
3)4)
3)
3)
IDD5
IDD6
IDD7
540 720
10
720 940
5)
6
12
20
13.5 22.5 13.5 22.5 24
40
27
45
27
45
mA
3)4)
1369 1800 1540 2025 1540 2025 1769 2240 1990 2520 1990 2520 mA
1) DRAM component currents only
2) Test condition for maximum values: VDD = 2.7 V, TA = 10 °C
3) The module IDDx values are calculated from the component IDDx data sheet values as:
m × IDDx[component] + n × IDD3N[component] with m and n number of components of rank 1 and 2; n=0 for 1 rank modules
4) DQ I/O (IDDQ) currents are not included into calculations: module IDD values will be measured differently depending on load
conditions
5) The module IDDx values are calculated from the corrponent IDDx data sheet values as: (m + n) × IDDx[component]
Data Sheet
21
V1.1, 2003-07
HYS[64/72]D[16x01/32x00/64x20][G/E]U-[5/6/7/8]-B
Unbuffered DDR SDRAM Modules
Electrical Characteristics
Table 13
Operating, Standby and Refresh Currents (PC2700, –6)
Unit Note
1)2)
128MB × 64
256MB × 64
256MB × 72
512MB × 64
512MB × 72
1 rank
1 rank
1 rank
2 ranks
2 ranks
Symbol
IDD0
typ.
352
416
24
max.
typ.
680
800
48
max.
typ.
765
900
54
max.
typ.
1160
1280
96
max.
typ.
1305
1440
108
max.
3)
460
500
36
880
960
72
990
1080
81
1400
1480
144
1575
1665
162
mA
3)4)
IDD1
mA
5)
IDD2P
IDD2F
IDD2Q
IDD3P
IDD3N
IDD4R
IDD4W
IDD5
mA
5)
180
98.8
72
220
112
84
360
440
405
495
720
880
810
990
mA
5)
197.6 224
222.3 252
395.2 448
444.6 504
mA
5)
144
480
880
1000
1148
12
168
162
189
288
336
324
378
mA
5)
252
496
564
574
6
280
640
660
760
10
520
540
585
960
1040
1640
1680
2040
40
1080
1530
1665
1832
27
1170
1845
1890
2295
45
mA
3)4)
1120
1160
1520
20
990
1260
1305
1710
22.5
2430
1360
1480
1628
24
mA
3)
1125
1292
13.5
1870
mA
3)
mA
5)
IDD6
mA
3)4)
IDD7
872
1140
1662
2160
2142
2680
2410
3015
mA
1) DRAM component currents only
2) Test condition for maximum values: VDD = 2.7 V, TA = 10 °C
3) The module IDDx values are calculated from the component IDDx data sheet values as:
m × IDDx[component] + n × IDD3N[component] with m and n number of components of rank 1 and 2; n=0 for 1 rank modules
4) DQ I/O (IDDQ) currents are not included into calculations: module IDD values will be measured differently depending on load
conditions
5) The module IDDx values are calculated from the corrponent IDDx data sheet values as: (m + n) × IDDx[component]
Data Sheet
22
V1.1, 2003-07
HYS[64/72]D[16x01/32x00/64x20][G/E]U-[5/6/7/8]-B
Unbuffered DDR SDRAM Modules
Electrical Characteristics
Table 14
Operating, Standby and Refresh Currents (PC3200, –5)
Unit Note1)2)
128MB × 64
256MB × 64
256MB × 72
512MB × 64
512MB × 72
1 rank
1 rank
1 rank
2 ranks
2 ranks
Symbol
IDD0
typ.
400
460
24
max.
typ.
720
840
48
max.
typ.
810
945
54
max.
typ.
1176
1296
96
max.
typ.
132
max.
3)
480
540
36
920
1035
1125
81
1472
1552
144
1656
1746
162
mA
3)4)
IDD1
1000
72
1458
108
mA
5)
IDD2P
IDD2F
IDD2Q
IDD3P
IDD3N
IDD4R
IDD4W
IDD5
mA
5)
184
96
224
136
96
368
192
136
456
920
1000
1240
12.8
1920
448
414
216
153
513
1035
1125
1395
14.4
2160
504
736
896
828
1008
612
mA
5)
272
306
384
544
432
mA
5)
68
192
216
272
384
306
432
mA
5)
240
560
600
620
6.4
296
700
720
780
10.4
1240
552
621
912
1104
1712
1752
2112
41.6
2792
1026
1548
1638
1908
28.8
2673
1242
1926
1971
2376
46.8
3141
mA
3)4)
1160
1200
1560
20.8
2240
1305
1350
1755
23.4
2520
1376
1456
1696
25.6
2376
mA
3)
mA
3)
mA
5)
IDD6
mA
3)4)
IDD7
1040
mA
1) DRAM component currents only
2) Test condition for maximum values: VDD = 2.7 V, TA = 10 °C
3) The module IDDx values are calculated from the component IDDx data sheet values as:
m × IDDx[component] + n × IDD3N[component] with m and n number of components of rank 1 and 2; n=0 for 1 rank modules
4) DQ I/O (IDDQ) currents are not included into calculations: module IDD values will be measured differently depending on load
conditions
5) The module IDDx values are calculated from the corrponent IDDx data sheet values as: (m + n) × IDDx[component]
Data Sheet
23
V1.1, 2003-07
HYS[64/72]D[16x01/32x00/64x20][G/E]U-[5/6/7/8]-B
Unbuffered DDR SDRAM Modules
Electrical Characteristics
3.3
AC Characteristics
Table 15
AC Timing - Absolute Specifications –8/–7/–7F
Parameter
Symbol
–8
–7
–7F
Unit Note/
Test Condition 1)
DDR200
DDR266A
DDR266
Min.
Max. Min.
Max. Min.
Max.
2)3)4)5)
2)3)4)5)
DQ output access time from tAC
CK/CK
–0.8
+0.8
–0.75 +0.75 –0.75 +0.75 ns
DQS output access time
from CK/CK
tDQSCK
–0.8
+0.8
–0.75 +0.75 –0.75 +0.75 ns
2)3)4)5)
2)3)4)5)
2)3)4)5)
CK high-level width
CK low-level width
Clock Half Period
Clock cycle time
tCH
0.45
0.45
0.55
0.55
0.45
0.45
0.55
0.55
0.45
0.45
0.55
0.55
tCK
tCK
tCL
tHP
min. (tCL, tCH) min. (tCL, tCH) min. (tCL, tCH) ns
tCK3
tCK2.5
tCK2
tCK1.5
8
12
12
12
12
—
—
7
12
12
12
—
—
—
7
12
12
12
—
—
—
ns
ns
ns
ns
ns
ns
CL = 3.0 2)3)4)5)
CL = 2.5 2)3)4)5)
CL = 2.0 2)3)4)5)
CL = 1.5 2)3)4)5)
2)3)4)5)
8
7
7
10
10
0.6
0.6
7.5
—
0.5
0.5
7.5
—
0.5
0.5
DQ and DM input hold time tDH
2)3)4)5)
DQ and DM input setup
time
tDS
2)3)4)5)6)
2)3)4)5)6)
2)3)4)5)7)
2)3)4)5)7)
2)3)4)5)
Control and Addr. input
pulse width (each input)
tIPW
tDIPW
tHZ
2.5
2.0
–0.8
–0.8
0.75
—
—
2.2
—
—
2.2
—
—
ns
ns
DQ and DM input pulse
width (each input)
—
1.75
1.75
Data-out high-impedance
time from CK/CK
+0.8
+0.8
1.25
+0.6
–0.75 +0.75 –0.75 +0.75 ns
–0.75 +0.75 –0.75 +0.75 ns
Data-out low-impedance
time from CK/CK
Write command to 1st DQS tDQSS
tLZ
0.75
—
1.25
+0.5
0.75
—
1.25
+0.5
tCK
latching transition
2)3)4)5)
DQS-DQ skew (DQS and tDQSQ
ns
associated DQ signals)
2)3)4)5)
2)3)4)5)
Data hold skew factor
tQHS
—
1.0
—
—
0.75
—
—
0.75
—
ns
ns
DQ/DQS output hold time tQH
tHP
–
tHP
–
tHP –
tQHS
tQHS
tQHS
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)
DQS input low (high) pulse tDQSL,H 0.35
—
—
—
—
0.35
0.2
0.2
2
—
—
—
—
0.35
—
—
—
—
tCK
tCK
tCK
tCK
width (write cycle)
DQS falling edge to CK
setup time (write cycle)
tDSS
0.2
0.2
2
0.2
0.2
2
DQS falling edge hold time tDSH
from CK (write cycle)
Mode register set command tMRD
cycle time
2)3)4)5)8)
2)3)4)5)9)
2)3)4)5)
Write preamble setup time tWPRES
0
—
0
—
0
—
ns
Write postamble
Write preamble
tWPST
tWPRE
0.40
0.25
0.60
—
0.40
0.25
0.60
—
0.40
0.25
0.60
—
tCK
tCK
Data Sheet
24
V1.1, 2003-07
HYS[64/72]D[16x01/32x00/64x20][G/E]U-[5/6/7/8]-B
Unbuffered DDR SDRAM Modules
Electrical Characteristics
Table 15
AC Timing - Absolute Specifications –8/–7/–7F (cont’d)
Parameter
Symbol
–8
–7
–7F
Unit Note/
Test Condition 1)
DDR200
DDR266A
DDR266
Min.
Max. Min.
Max. Min.
Max.
Address and control input tIS
setup time
1.1
1.1
1.1
1.1
—
—
—
—
0.9
1.0
0.9
1.0
—
—
—
—
1.1
0.9
1.0
0.9
1.0
—
—
—
—
1.1
ns
ns
ns
ns
fast slew rate
3)4)5)6)10)
slow slew rate
3)4)5)6)10)
Address and control input tIH
hold time
fast slew rate
3)4)5)6)10)
slow slew rate
3)4)5)6)10)
Read preamble
tRPRE
0.9
1.1
1.1
—
0.9
NA
NA
0.40
45
0.9
NA
NA
0.40
45
tCK
tCK
ns
CL > 1.5 2)3)4)5)
CL = 1.5 2)3)4)5)11)
tRPRE1.5 0.9
2)3)4)5)12)
Read preamble setup time tRPRES
1.5
0.40
50
2)3)4)5)
2)3)4)5)
Read postamble
tRPST
tRAS
0.60
0.60
0.60
tCK
ns
Active to Precharge
command
120
E+3
120
E+3
120
E+3
2)3)4)5)
2)3)4)5)
2)3)4)5)
Active to Active/Auto-
refresh command period
tRC
70
80
20
—
—
—
65
75
20
—
—
—
60
75
15
—
—
—
ns
ns
ns
Auto-refresh to Active/Auto- tRFC
refresh command period
Active to Read or Write
delay
tRCD
2)3)4)5)
2)3)4)5)
Precharge command period tRP
20
20
—
—
20
20
—
—
15
15
—
—
ns
ns
Active to Autoprecharge
delay
tRAP
2)3)4)5)
Active bank A to Active
bank B command
tRRD
15
15
—
—
15
—
15
15
—
—
ns
2)3)4)5)
Write recovery time
tWR
15
—
ns
2)3)4)5)13)
Auto precharge write
tDAL
(twr/tCK) + (trp/tCK)
tCK
recovery + precharge time
Internal write to read
command delay
tWTR
1
—
—
—
1
—
—
—
1
—
—
—
tCK
tCK
ns
CL > 1.5 2)3)4)5)
CL = 1.5 2)3)4)5)
tWTR1.5
2
—
75
—
75
2)3)4)5)
Exit self-refresh to non-read tXSNR
80
command
2)3)4)5)
Exit self-refresh to read
command
tXSRD
200
—
—
200
—
—
200
—
—
tCK
2)3)4)5)14)
Average Periodic Refresh tREFI
7.8
7.8
7.8
µs
Interval
1) 0 °C ≤TA ≤70 °C; VDDQ = 2.5 V ±0.2 V, VDD = +2.5 V ±0.2 V
2) Input slew rate ≥ 1 V/ns for DDR400, DDR333, DDR266, and = 1 V/ns for DDR200
3) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference
level for signals other than CK/CK, is VREF. CK/CK slew rate are ≥ 1.0 V/ns.
4) Inputs are not recognized as valid until VREF stabilizes.
5) The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (note 3) is VTT.
6) These parameters guarantee device timing, but they are not necessarily tested on each device.
Data Sheet
25
V1.1, 2003-07
HYS[64/72]D[16x01/32x00/64x20][G/E]U-[5/6/7/8]-B
Unbuffered DDR SDRAM Modules
Electrical Characteristics
7) tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred
to a specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ).
8) The specific requirement is that DQS be valid (HIGH, LOW, or some point on a valid transition) on or before this CK edge.
A valid transition is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were
previously in progress on the bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress,
DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on tDQSS
.
9) The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but
system performance (bus turnaround) degrades accordingly.
10) Fast slew rate ≥ 1.0 V/ns , slow slew rate ≥ 0.5 V/ns and < 1 V/ns for command/address and CK & CK slew rate > 1.0 V/ns,
measured between VOH(ac) and VOL(ac)
.
11) CAS Latency 1.5 operation is supported on DDR200 devices only
12) tRPRES is defined for CL = 1.5 operation only
13) For each of the terms, if not already an integer, round to the next highest integer. tCK is equal to the actual system clock
cycle time.
14) A maximum of eight Autorefresh commands can be posted to any given DDR SDRAM device.
Table 16
AC Timing - Absolute Specifications –6/–5
Symbol
Parameter
–6
DDR333
Min.
–5
Unit Note/
Test Condition 1)
DDR400B
Max. Min.
Max.
+0.6
+0.5
0.55
0.55
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)
DQ output access time from CK/CK
DQS output access time from CK/CK
CK high-level width
tAC
–0.7
–0.6
0.45
0.45
+0.7
+0.6
0.55
0.55
–0.6
–0.5
0.45
0.45
ns
ns
tCK
tCK
tDQSCK
tCH
CK low-level width
tCL
Clock Half Period
tHP
min. (tCL, tCH) min. (tCL, tCH) ns
Clock cycle time
tCK
6
12
12
12
—
—
—
5
12
12
12
—
—
—
ns
ns
ns
ns
ns
ns
CL = 3.0 2)3)4)5)
CL = 2.5 2)3)4)5)
CL = 2.0 2)3)4)5)
6
6
7.5
0.45
0.45
2.2
7.5
0.4
0.4
tbd
2)3)4)5)
DQ and DM input hold time
DQ and DM input setup time
tDH
tDS
2)3)4)5)
2)3)4)5)6)
Control and Addr. input pulse width (each tIPW
input)
2)3)4)5)6)
2)3)4)5)7)
2)3)4)5)7)
2)3)4)5)
DQ and DM input pulse width (each input) tDIPW
Data-out high-impedance time from CK/CK tHZ
Data-out low-impedance time from CK/CK tLZ
1.75
–0.7
–0.7
0.75
—
tbd
—
ns
ns
ns
tCK
+0.7
+0.7
1.25
–0.6
–0.6
0.75
+0.6
+0.6
1.25
Write command to 1st DQS latching
transition
tDQSS
tDQSQ
tQHS
tQH
DQS-DQ skew (DQS and associated DQ
signals)
—
—
—
—
+0.40
+0.45
+0.50
+0.55
—
—
—
—
—
+0.40 ns
+0.40 ns
+0.50 ns
+0.50 ns
TFBGA 2)3)4)5)
TSOPII 2)3)4)5)
TFBGA 2)3)4)5)
TSOPII 2)3)4)5)
2)3)4)5)
Data hold skew factor
DQ/DQS output hold time
tHP
–
tHP
–
—
ns
tQHS
tQHS
2)3)4)5)
DQS input low (high) pulse width (write
cycle)
tDQSL,H 0.35
—
0.35
—
tCK
Data Sheet
26
V1.1, 2003-07
HYS[64/72]D[16x01/32x00/64x20][G/E]U-[5/6/7/8]-B
Unbuffered DDR SDRAM Modules
Electrical Characteristics
Table 16
AC Timing - Absolute Specifications –6/–5 (cont’d)
Parameter
Symbol
–6
–5
Unit Note/
Test Condition 1)
DDR333
DDR400B
Min.
Max. Min.
Max.
2)3)4)5)
2)3)4)5)
DQS falling edge to CK setup time (write
cycle)
tDSS
0.2
—
0.2
—
tCK
tCK
DQS falling edge hold time from CK (write tDSH
0.2
—
0.2
—
cycle)
2)3)4)5)
Mode register set command cycle time
Write preamble setup time
Write postamble
tMRD
2
—
2
—
tCK
ns
2)3)4)5)8)
2)3)4)5)9)
2)3)4)5)
tWPRES
tWPST
tWPRE
tIS
0
—
0
—
0.40
0.25
0.75
0.60
—
0.40
0.25
0.6
0.60
—
tCK
tCK
ns
Write preamble
Address and control input setup time
—
—
fast slew rate
3)4)5)6)10)
0.8
—
—
—
NA
0.6
NA
ns
ns
ns
slow slew rate
3)4)5)6)10)
Address and control input hold time
tIH
0.75
0.8
—
fast slew rate
3)4)5)6)10)
slow slew rate
3)4)5)6)10)
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)
Read preamble
tRPRE
tRPST
tRAS
tRC
0.9
0.40
42
1.1
0.9
1.1
tCK
tCK
Read postamble
0.60
0.40
0.60
Active to Precharge command
70E+3 40
70E+3 ns
Active to Active/Auto-refresh command
period
60
—
55
—
ns
2)3)4)5)
Auto-refresh to Active/Auto-refresh
command period
tRFC
72
—
65
—
ns
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)11)
Active to Read or Write delay
Precharge command period
Active to Autoprecharge delay
tRCD
tRP
18
18
18
12
15
—
—
—
—
—
15
15
15
10
15
—
—
—
—
—
ns
ns
ns
ns
ns
tCK
tRAP
Active bank A to Active bank B command tRRD
Write recovery time tWR
Auto precharge write recovery + precharge tDAL
time
2)3)4)5)
Internal write to read command delay
Exit self-refresh to non-read command
Exit self-refresh to read command
Average Periodic Refresh Interval
tWTR
tXSNR
tXSRD
tREFI
1
—
—
1
—
—
—
7.8
tCK
ns
tCK
µs
2)3)4)5)
75
200
—
75
200
—
2)3)4)5)
—
2)3)4)5)12)
7.8
1) 0 °C ≤TA ≤70 °C; VDDQ = 2.5 V ±0.2 V, VDD = +2.5 V ±0.2 V (DDR333); VDDQ = 2.6 V ±0.1 V, VDD = +2.6 V ±0.1 V (DDR400)
2) Input slew rate ≥ 1 V/ns for DDR400, DDR333
3) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference
level for signals other than CK/CK, is VREF. CK/CK slew rate are ≥ 1.0 V/ns.
4) Inputs are not recognized as valid until VREF stabilizes.
5) The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (note 3) is VTT.
6) These parameters guarantee device timing, but they are not necessarily tested on each device.
Data Sheet
27
V1.1, 2003-07
HYS[64/72]D[16x01/32x00/64x20][G/E]U-[5/6/7/8]-B
Unbuffered DDR SDRAM Modules
Electrical Characteristics
7) tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred
to a specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ).
8) The specific requirement is that DQS be valid (HIGH, LOW, or some point on a valid transition) on or before this CK edge.
A valid transition is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were
previously in progress on the bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress,
DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on tDQSS
.
9) The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but
system performance (bus turnaround) degrades accordingly.
10) Fast slew rate ≥ 1.0 V/ns , slow slew rate ≥ 0.5 V/ns and < 1 V/ns for command/address and CK & CK slew rate > 1.0 V/ns,
measured between VOH(ac) and VOL(ac)
.
11) For each of the terms, if not already an integer, round to the next highest integer. tCK is equal to the actual system clock
cycle time.
12) A maximum of eight Autorefresh commands can be posted to any given DDR SDRAM device.
Data Sheet
28
V1.1, 2003-07
HYS[64/72]D[16x01/32x00/64x20][G/E]U-[5/6/7/8]-B
Unbuffered DDR SDRAM Modules
SPD Contents
4
SPD Contents
Table 17
Operating, Standby and Refresh Currents (PC1600, –8)
128MB
× 64
256MB
256MB
× 72
512MB
512MB
× 64
1 rank
HEX
80
× 64
× 72
1 rank
HEX
80
1 rank
HEX
80
2 ranks 2 ranks
Byte
Description
HEX
80
HEX
80
0
1
Number of SPD Bytes 128
Total Bytes in Serial
PD
256
08
08
08
08
08
2
3
Memory Type
DDR-SDRAM
13
07
07
07
07
07
Number of Row
Addresses
0D
0D
0D
0D
0D
4
5
Number of Column
Addresses
9/10
1/2
09
01
0A
01
0A
01
0A
02
0A
01
Number of DIMM
Banks
6
7
Module Data Width
× 64/× 72
40
00
40
00
48
00
40
00
48
00
Module Data Width
(cont’d)
0
8
Module Interface
Levels
SSTL_2.5
04
80
80
04
80
80
04
80
80
04
80
80
04
80
80
9
SDRAM Cycle Time at 8 ns
CL = 2.5
10
Access Time from
Clock at
0.8 ns
CL = 2.5
11
12
13
DIMM config
non-ECC/ECC
Self-Refresh 7.8 µs
× 16/ ×8
00
82
10
00
82
08
02
82
08
00
82
08
02
82
08
Refresh Rate/Type
SDRAM Width,
Primary
14
15
Error Checking
SDRAM Data Witdh
na/ × 8
00
01
00
01
08
01
00
01
08
01
Minimum Clock Delay tCCD = 1 CLK
for Back-to-Back
Random Column
Address
16
Burst Length
Supported
2, 4 & 8
0E
0E
0E
0E
0E
Data Sheet
29
V1.1, 2003-07
HYS[64/72]D[16x01/32x00/64x20][G/E]U-[5/6/7/8]-B
Unbuffered DDR SDRAM Modules
SPD Contents
Table 17
Operating, Standby and Refresh Currents (PC1600, –8) (cont’d)
128MB
× 64
256MB
× 64
256MB
× 72
512MB
512MB
× 64
× 72
1 rank
HEX
04
1 rank
HEX
04
1 rank
HEX
04
2 ranks 2 ranks
Byte
Description
HEX
HEX
17
Number of SDRAM
Banks
4
04
04
18
Supported CAS
Latencies
CAS latency = 2 & 2.5 0C
0C
0C
0C
0C
19
20
21
CS Latencies
WE Latencies
CS latency = 0
Write latency = 1
unbuffered
01
02
20
01
02
20
01
02
20
01
02
20
01
02
20
SDRAM DIMM
Module Attributes
22
23
24
SDRAM Device
Attributes: General
−
C0
A0
80
C0
A0
80
C0
A0
80
C0
A0
80
C0
A0
80
Min. Clock Cycle Time 10 ns
at CAS Latency = 2
Access Time from
Clock for
0.8 ns
CL = 2
25
26
Minimum Clock Cycle not supported
Time for CL = 1.5
00
00
00
00
00
00
00
00
00
00
Access Time from
Clock at
not supported
CL = 1.5
27
28
29
30
31
32
33
Minimum Row
Precharge Time
20 ns
50
3C
50
32
20
B0
B0
50
3C
50
32
40
B0
B0
50
3C
50
32
40
B0
B0
50
3C
50
32
40
B0
B0
50
3C
50
32
40
B0
B0
Minimum Row Act. to 15 ns
Row Act. Delay tRRD
Minimum RAS to CAS 20 ns
Delay tRCD
Minimum RAS Pulse 50 ns
Width tRAS
Module Bank Density 256 MByte
(per Bank)
Addr. and Command 1.1 ns
Setup Time
Addr. and Command 1.1 ns
Hold Time
Data Sheet
30
V1.1, 2003-07
HYS[64/72]D[16x01/32x00/64x20][G/E]U-[5/6/7/8]-B
Unbuffered DDR SDRAM Modules
SPD Contents
Table 17
Operating, Standby and Refresh Currents (PC1600, –8) (cont’d)
128MB
× 64
256MB
× 64
256MB
× 72
1 rank
HEX
60
512MB
512MB
× 64
× 72
1 rank
HEX
60
1 rank
HEX
60
2 ranks 2 ranks
Byte
34
Description
HEX
60
HEX
60
Data Input Setup Time 0.6 ns
Data Input Hold Time 0.6 ns
35
60
60
60
60
60
36 to 40
41
Superset Information
–
00
00
00
00
00
Minimum Core Cycle 70 ns
46
46
46
46
46
Time tRC
42
43
44
Min. Auto Refresh 80 ns
Cmd Cycle Time tFRC
50
30
3C
50
30
3C
50
30
3C
48
30
3C
50
30
3C
Maximum Clock Cycle 12 ns
Time tCK
Max. DQS-DQ Skew 0.6 ns
tDQSQ
45
X-Factor tQHS
1.0 ns
A0
00
00
E8
A0
00
00
A7
A0
00
00
B9
A0
00
00
A8
A0
00
00
B9
46 to 61
62
Superset Information
SPD Revision
–
Revision 0.0
63
Checksum for Bytes 0 –
- 62
64
Manufacturers
–
C1
C1
C1
C1
C1
JEDEC ID Codes
65 to 71
72
Manufacturer
–
Infineon Infineon Infineon Infineon Infineon
Module
Assembly –
–
–
–
–
–
Location
73 to 90
91 to 92
Module Part Number
–
–
–
–
–
–
–
–
–
–
–
Module
Code
Revision –
93 to 94
Module
–
–
–
–
–
–
Manufacturing Date
95 to 98
Module Serial Number –
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
99 to 127
–
–
128 to 255 open for Customer –
use
Data Sheet
31
V1.1, 2003-07
HYS[64/72]D[16x01/32x00/64x20][G/E]U-[5/6/7/8]-B
Unbuffered DDR SDRAM Modules
SPD Contents
Table 18
SPD Codes for PC2100 Modules “–7”
128MB 256MB 256MB 512MB 512MB
× 64
1 rank
HEX
80
× 64
1 rank
HEX
80
× 72
1 rank
HEX
80
× 64
× 72
2 ranks 2 ranks
Byte
Description
HEX
80
HEX
80
0
1
Number of SPD Bytes 128
Total Bytes in Serial
PD
256
08
08
08
08
08
2
3
Memory Type
DDR-SDRAM
13
07
07
07
07
07
Number of Row
Addresses
0D
0D
0D
0D
0D
4
5
Number of Column
Addresses
9/10
1/2
09
01
0A
01
0A
01
0A
02
0A
01
Number of DIMM
Banks
6
7
Module Data Width
× 64/× 72
40
00
40
00
48
00
40
00
48
00
Module Data Width
(cont’d)
0
8
Module Interface
Levels
SSTL_2.5
04
70
75
04
70
75
04
70
75
04
70
75
04
70
75
9
SDRAM Cycle Time at 7 ns
CL = 2.5
10
Access Time from
Clock at
0.75 ns
CL = 2.5
11
12
13
DIMM config
non-ECC/ECC
Self-Refresh 7.8 µs
× 16/ × 8
00
82
10
00
82
08
02
82
08
00
82
08
02
82
08
Refresh Rate/Type
SDRAM Width,
Primary
14
15
Error Checking
SDRAM Data Witdh
na/ ×8
00
01
00
01
08
01
00
01
08
01
Minimum Clock Delay tCCD = 1 CLK
for Back-to-Back
Random Column
Address
16
17
Burst Length
Supported
2, 4 & 8
4
0E
04
0E
04
0E
04
0E
04
0E
04
Number of SDRAM
Banks
Data Sheet
32
V1.1, 2003-07
HYS[64/72]D[16x01/32x00/64x20][G/E]U-[5/6/7/8]-B
Unbuffered DDR SDRAM Modules
SPD Contents
Table 18
SPD Codes for PC2100 Modules “–7” (cont’d)
128MB 256MB 256MB 512MB 512MB
× 64
× 64
× 72
× 64
× 72
1 rank
HEX
1 rank
HEX
0C
1 rank
HEX
0C
2 ranks 2 ranks
Byte
Description
HEX
HEX
18
Supported CAS
Latencies
CAS latency = 2 & 2.5 0C
0C
0C
19
20
21
CS Latencies
WE Latencies
CS latency = 0
Write latency = 1
unbuffered
01
02
20
01
02
20
01
02
20
01
02
20
01
02
20
SDRAM DIMM
Module Attributes
22
23
24
SDRAM Device
Attributes: General
−
C0
75
75
C0
75
75
C0
75
75
C0
75
75
C0
75
75
Min. Clock Cycle Time 7.5 ns
at CAS Latency = 2
Access Time from
Clock for
0.75 ns
CL = 2
25
26
Minimum Clock Cycle not supported
Time for CL = 1.5
00
00
00
00
00
00
00
00
00
00
Access Time from
Clock at
not supported
CL = 1.5
27
28
29
30
31
32
33
Minimum Row
Precharge Time
20 ns
50
3C
50
2D
50
3C
50
2D
40
90
90
50
3C
50
2D
40
90
90
50
3C
50
2D
40
90
90
50
3C
50
2D
40
90
90
Minimum Row Act. to 15 ns
Row Act. Delay tRRD
Minimum RAS to CAS 20 ns
Delay tRCD
Minimum RAS Pulse 45 ns
Width tRAS
Module Bank Density 128 MByte/256 MByte 20
(per Bank)
Addr. and Command 0.9 ns
Setup Time
90
Addr. and Command 0.9 ns
Hold Time
90
34
35
Data Input Setup Time 0.5 ns
Data Input Hold Time 0.5 ns
50
50
50
50
50
50
50
50
50
50
Data Sheet
33
V1.1, 2003-07
HYS[64/72]D[16x01/32x00/64x20][G/E]U-[5/6/7/8]-B
Unbuffered DDR SDRAM Modules
SPD Contents
Table 18
SPD Codes for PC2100 Modules “–7” (cont’d)
128MB 256MB 256MB 512MB 512MB
× 64
1 rank
HEX
00
× 64
1 rank
HEX
00
× 72
1 rank
HEX
00
× 64
× 72
2 ranks 2 ranks
Byte
36 to 40
41
Description
HEX
00
HEX
00
Superset Information
–
Minimum Core Cycle 65 ns
41
41
41
41
41
Time tRC
42
43
44
Min. Auto Refresh 75 ns
Cmd Cycle Time tFRC
4B
30
32
4B
30
32
4B
30
32
4B
30
32
4B
30
32
Maximum Clock Cycle 12 ns
Time tCK
Max. DQS-DQ Skew 0.5 ns
tDQSQ
45
X-Factor tQHS
0.75 ns
75
00
00
99
75
00
00
B2
75
00
00
C4
75
00
00
B3
75
00
00
C4
46 to 61
62
Superset Information
SPD Revision
–
Revision 0.0
63
Checksum for Bytes 0 –
- 62
64
Manufacturers
–
C1
C1
C1
C1
C1
JEDEC ID Codes
65 to 71
72
Manufacturer
–
Infineon Infineon Infineon Infineon Infineon
Module
Assembly –
–
–
–
–
–
Location
73 to 90
91 to 92
Module Part Number
–
–
–
–
–
–
–
–
–
–
–
Module
Code
Revision –
93 to 94
Module Manufacturing –
Date
–
–
–
–
–
95 to 98
Module Serial Number –
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
99 to 127
–
–
128 to 255 open for Customer –
use
Data Sheet
34
V1.1, 2003-07
HYS[64/72]D[16x01/32x00/64x20][G/E]U-[5/6/7/8]-B
Unbuffered DDR SDRAM Modules
SPD Contents
Table 19
SPD Codes for PC2100 Modules “–7F”
256MB
× 72
1 rank
HEX
80
512MB
× 72
1 rank
HEX
80
Byte
Description
0
1
2
3
4
Number of SPD Bytes
Total Bytes in Serial PD
Memory Type
128
256
08
08
DDR-SDRAM
07
07
Number of Row Addresses
13
0D
0D
Number of Column
Addresses
9/10
0A
0A
5
6
7
8
9
Number of DIMM Banks
Module Data Width
1/2
01
48
00
04
70
02
48
00
04
70
× 64/× 72
0
Module Data Width (cont’d)
Module Interface Levels
SSTL_2.5
7 ns
SDRAM Cycle Time at
CL = 2.5
10
Access Time from Clock at
CL = 2.5
0.75 ns
75
75
11
12
13
14
DIMM config
non-ECC/ECC
Self-Refresh 7.8 µs
× 16/ × 8
02
82
08
08
02
82
08
08
Refresh Rate/Type
SDRAM Width, Primary
Error Checking SDRAM Data na/ ×8
Witdh
15
Minimum Clock Delay for
Back-to-Back Random
Column Address
t
CCD = 1 CLK
01
01
16
17
18
19
20
21
Burst Length Supported
Number of SDRAM Banks
Supported CAS Latencies
CS Latencies
2, 4 & 8
0E
04
0C
01
02
20
0E
04
0C
01
02
20
4
CAS latency = 2 & 2.5
CS latency = 0
Write latency = 1
unbuffered
WE Latencies
SDRAM DIMM Module
Attributes
22
SDRAM Device Attributes:
General
−
C0
C0
Data Sheet
35
V1.1, 2003-07
HYS[64/72]D[16x01/32x00/64x20][G/E]U-[5/6/7/8]-B
Unbuffered DDR SDRAM Modules
SPD Contents
Table 19
SPD Codes for PC2100 Modules “–7F” (cont’d)
256MB
× 72
512MB
× 72
1 rank
HEX
75
1 rank
HEX
75
Byte
Description
23
Min. Clock Cycle Time at
CAS Latency = 2
7.5 ns
24
25
26
27
28
29
30
31
32
33
Access Time from Clock for 0.75 ns
CL = 2
75
00
00
3C
3C
3C
2D
40
90
90
75
00
00
3C
3C
3C
2D
40
90
90
Minimum Clock Cycle Time
for CL = 1.5
not supported
Access Time from Clock at
CL = 1.5
not supported
15 ns
Minimum Row Precharge
Time
Minimum Row Act. to Row
15 ns
Act. Delay tRRD
Minimum RAS to CAS Delay 15 ns
tRCD
Minimum RAS Pulse Width
45 ns
tRAS
Module Bank Density (per
Bank)
128 MByte/256 MByte
0.9 ns
Addr. and Command Setup
Time
Addr. and Command Hold 0.9 ns
Time
34
Data Input Setup Time
Data Input Hold Time
Superset Information
0.5 ns
0.5 ns
–
50
50
00
3C
50
50
00
3C
35
36 to 40
41
Minimum Core Cycle Time 60 ns
tRC
42
43
Min. Auto Refresh Cmd Cycle 75 ns
Time tFRC
4B
30
4B
30
Maximum Clock Cycle Time 12 ns
tCK
44
45
Max. DQS-DQ Skew tDQSQ
0.5 ns
32
75
32
75
X-Factor tQHS
0.75 ns
Data Sheet
36
V1.1, 2003-07
HYS[64/72]D[16x01/32x00/64x20][G/E]U-[5/6/7/8]-B
Unbuffered DDR SDRAM Modules
SPD Contents
Table 19
SPD Codes for PC2100 Modules “–7F” (cont’d)
256MB
× 72
1 rank
HEX
00
512MB
× 72
1 rank
HEX
00
Byte
46 to 61
62
Description
Superset Information
SPD Revision
–
Revision 0.0
–
00
00
63
Checksum for Bytes 0 - 62
97
98
64
Manufactures JEDEC ID –
Codes
C1
C1
65 to 71
72
Manufacturer
–
–
–
–
–
–
–
–
Infineon
Infineon
Module Assembly Location
Module Part Number
Module Revision Code
Module Manufacturing Date
Module Serial Number
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
73 to 90
91 to 92
93 to 94
95 to 98
99 to 127
128 to 255 open for Customer use
Data Sheet
37
V1.1, 2003-07
HYS[64/72]D[16x01/32x00/64x20][G/E]U-[5/6/7/8]-B
Unbuffered DDR SDRAM Modules
SPD Contents
Table 20
SPD Codes for PC2700 Modules “–6”
128MB 256MB 256MB 512MB 512MB
× 64
1 rank
HEX
80
× 64
1 rank
HEX
80
× 72
1 rank
HEX
80
× 64
× 72
2 ranks 2 ranks
Byte
Description
HEX
80
HEX
80
0
1
Number of SPD Bytes 128
Total Bytes in Serial
PD
256
08
08
08
08
08
2
3
Memory Type
DDR-SDRAM
13
07
07
07
07
07
Number of Row
Addresses
0D
0D
0D
0D
0D
4
5
Number of Column
Addresses
9/10
1/2
09
01
0A
01
0A
01
0A
02
0A
01
Number of DIMM
Banks
6
7
Module Data Width
× 64/× 72
40
00
40
00
48
00
40
00
48
00
Module Data Width
(cont’d)
0
8
Module Interface
Levels
SSTL_2.5
04
60
70
04
60
70
04
60
70
04
60
70
04
60
70
9
SDRAM Cycle Time at 6 ns
CL = 2.5
10
Access Time from
Clock at
0.75 ns
CL = 2.5
11
12
13
DIMM config
non-ECC/ECC
Self-Refresh 7.8 µs
× 16/ × 8
00
82
10
00
82
08
02
82
08
00
82
08
02
82
08
Refresh Rate/Type
SDRAM Width,
Primary
14
15
Error Checking
SDRAM Data Witdh
na/ ×8
00
01
00
01
08
01
00
01
08
01
Minimum Clock Delay tCCD = 1 CLK
for Back-to-Back
Random Column
Address
16
17
Burst Length
Supported
2, 4 & 8
4
0E
04
0E
04
0E
04
0E
04
0E
04
Number of SDRAM
Banks
Data Sheet
38
V1.1, 2003-07
HYS[64/72]D[16x01/32x00/64x20][G/E]U-[5/6/7/8]-B
Unbuffered DDR SDRAM Modules
SPD Contents
Table 20
SPD Codes for PC2700 Modules “–6” (cont’d)
128MB 256MB 256MB 512MB 512MB
× 64
× 64
× 72
× 64
× 72
1 rank
HEX
1 rank
HEX
0C
1 rank
HEX
0C
2 ranks 2 ranks
Byte
Description
HEX
HEX
18
Supported CAS
Latencies
CAS latency = 2 & 2.5 0C
0C
0C
19
20
21
CS Latencies
WE Latencies
CS latency = 0
01
02
20
01
02
20
01
02
20
01
02
20
01
02
20
Write latency = 1
SDRAMDIMMModule unbuffered
Attributes
22
23
24
SDRAM Device
Attributes: General
−
C0
75
70
C0
75
70
C0
75
70
C0
75
70
C0
75
70
Min. Clock Cycle Time 7.5 ns
at CAS Latency = 2
Access Time from
Clock for
0.70 ns
CL = 2
25
26
Minimum Clock Cycle not supported
Time for CL = 1.5
00
00
00
00
00
00
00
00
00
00
Access Time from
Clock at
not supported
CL = 1.5
27
28
29
30
31
32
33
Minimum Row
Precharge Time
18 ns
48
30
48
2A
48
30
48
2A
40
75
75
48
30
48
2A
40
75
75
48
30
48
2A
40
75
75
48
30
48
2A
40
75
75
Minimum Row Act. to 12 ns
Row Act. Delay tRRD
Minimum RAS to CAS 18 ns
Delay tRCD
Minimum RAS Pulse 42 ns
Width tRAS
Module Bank Density 128 MByte/256 MByte 20
(per Bank)
Addr. and Command 0.75 ns
Setup Time
75
Addr. and Command 0.75 ns
Hold Time
75
34
35
Data Input Setup Time 0.45 ns
Data Input Hold Time 0.45 ns
45
45
45
45
45
45
45
45
45
45
Data Sheet
39
V1.1, 2003-07
HYS[64/72]D[16x01/32x00/64x20][G/E]U-[5/6/7/8]-B
Unbuffered DDR SDRAM Modules
SPD Contents
Table 20
SPD Codes for PC2700 Modules “–6” (cont’d)
128MB 256MB 256MB 512MB 512MB
× 64
1 rank
HEX
00
× 64
1 rank
HEX
00
× 72
1 rank
HEX
00
× 64
× 72
2 ranks 2 ranks
Byte
36 to 40
41
Description
HEX
00
HEX
00
Superset Information
–
Minimum Core Cycle 60 ns
3C
3C
3C
3C
3C
Time tRC
42
43
44
Min. Auto Refresh 72 ns
Cmd Cycle Time tFRC
48
30
2D
48
30
2D
48
30
2D
48
30
2D
48
30
2D
Maximum Clock Cycle 12 ns
Time tCK
Max. DQS-DQ Skew 0.45 ns
tDQSQ
45
X-Factor tQHS
0.55 ns
55
00
00
E7
55
00
00
00
55
00
00
12
55
00
00
01
55
00
00
12
46 to 61
62
Superset Information
SPD Revision
–
Revision 0.0
63
Checksum for Bytes 0 –
- 62
64
Manufacturers JEDEC –
ID Codes
C1
C1
C1
C1
C1
65 to 71
72
Manufacturer
–
Infineon Infineon Infineon Infineon Infineon
Module
Assembly –
–
–
–
–
–
Location
73 to 90
91 to 92
93 to 94
Module Part Number
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Module Revision Code –
Module Manufacturing –
Date
95 to 98
Module Serial Number –
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
99 to 127
–
–
128 to 255 open for Customer use –
Data Sheet
40
V1.1, 2003-07
HYS[64/72]D[16x01/32x00/64x20][G/E]U-[5/6/7/8]-B
Unbuffered DDR SDRAM Modules
SPD Contents
Table 21
SPD Codes for PC3200 Modules “–5”
128MB 256MB 256MB 512MB 512MB
× 64 × 64 × 72 × 64 × 72
1 rank 1 rank 1 rank 2 ranks 2 ranks
Byte Description
HEX
80
08
07
0D
09
01
40
00
04
50
50
00
82
HEX
80
08
07
0D
0A
01
40
00
04
50
50
00
82
HEX
80
08
07
0D
0A
01
48
00
04
50
50
02
82
HEX
80
08
07
0D
0A
02
40
00
04
50
50
00
82
HEX
80
08
07
0D
0A
02
48
00
04
50
50
02
82
0
Programmed SPD Bytes in E2PROM
128
1
Total number of Bytes in E2PROM
Memory Type DDR-I = 07h
# of Row Addresses
256
2
DDR-SDRAM
13
3
4
# Number of Column Addresses
# of DIMM Banks
9/10
5
1/2
6
Data Width (LSB)
× 64/× 72
0
7
Data Width (MSB)
8
Interface Voltage Levels
tCK @ CLmax (Byte 18) [ns]
tAC SDRAM @ CLmax (Byte 18) [ns]
SSTL_2.5
5 ns
9
10
11
12
0.50 ns
DIMM Configuration Type (non- / ECC) non-ECC/ECC
Refresh Rate
Self-Refresh
7.8 µs
13
14
15
16
17
18
Primary SDRAM width
Error Checking SDRAM width
tCCD [cycles]
× 16/ ×8
na/ ×8
10
00
01
0E
04
08
00
01
0E
04
1C
08
08
01
0E
04
1C
08
00
01
0E
04
1C
08
08
01
0E
04
1C
t
CCD = 1 CLK
Burst Length Supported
Number of Banks on SDRAM
CAS Latency
2, 4 & 8
4
CAS latency = 2, 1C
2.5, 3
19
20
21
22
23
24
25
26
27
28
CS Latency
CS latency = 0
01
01
02
20
C1
60
50
75
50
3C
28
01
02
20
C1
60
50
75
50
3C
28
01
02
20
C1
60
50
75
50
3C
28
01
02
20
C1
60
50
75
50
3C
28
WE (Write) Latency
Write latency = 1 02
DIMM Attributes
unbuffered
−
20
C1
60
50
75
50
3C
28
Component Attributes
tCK @ CLmax -0.5 (Byte 18) [ns]
tAC SDRAM @ CLmax -0.5 [ns]
tCK @ CLmax -1 (Byte 18) [ns]
tAC SDRAM @ CLmax -1 [ns]
tRPmin (ns)
6.0 ns
0.50 ns
7.5 ns
not supported
15 ns
tRRDmin [ns]
10 ns
Data Sheet
41
V1.1, 2003-07
HYS[64/72]D[16x01/32x00/64x20][G/E]U-[5/6/7/8]-B
Unbuffered DDR SDRAM Modules
SPD Contents
Table 21
SPD Codes for PC3200 Modules “–5” (cont’d)
128MB 256MB 256MB 512MB 512MB
× 64 × 64 × 72 × 64 × 72
1 rank 1 rank 1 rank 2 ranks 2 ranks
Byte Description
HEX
3C
28
HEX
3C
28
HEX
3C
28
HEX
3C
28
HEX
3C
28
29
30
31
tRCDmin [ns]
15 ns
40 ns
tRASmin [ns]
Module Density per Bank
128 MByte/
256 MByte
20
40
40
40
40
32
33
34
35
tAS, tCS [ns]
tAH, TCH [ns]
tDS [ns]
0.60 ns
0.60 ns
0.40 ns
0.40 ns
–
60
60
40
40
00
60
60
40
40
00
60
60
40
40
00
60
60
40
40
00
60
60
40
40
00
tDH [ns]
36 -
40
not used
41
42
43
44
45
tRCmin [ns]
tRFCmin [ns]
tCKmax [ns]
tDQSQmax [ns]
tQHSmax [ns]
not used
55 ns
65 ns
10 ns
0.40 ns
0.50 ns
–
37
41
28
28
50
00
37
41
28
28
50
00
37
41
28
28
50
00
37
41
28
28
50
00
37
41
28
28
50
00
46 -
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
SPD Revision
Revision 0.0
00
E4
C1
49
4E
46
49
4E
45
4F
xx
00
FD
C1
49
4E
46
49
4E
45
4F
xx
00
0F
C1
49
4E
46
49
4E
45
4F
xx
00
FE
C1
49
4E
46
49
4E
45
4F
xx
00
10
C1
49
4E
46
49
4E
45
4F
xx
Checksum of Byte 0-62 (LSB only)
JEDEC ID Code for Infineon
JEDEC ID Code for Infineon
JEDEC ID Code for Infineon
JEDEC ID Code for Infineon
JEDEC ID Code for Infineon
JEDEC ID Code for Infineon
JEDEC ID Code for Infineon
JEDEC ID Code for Infineon
Module Manufacturer Location
Module Part Number, Char 1
Module Part Number, Char 2
Module Part Number, Char 3
–
–
“I”
“N”
“F”
“I”
“N”
“E”
“O”
–
–
36
34
44
36
34
44
37
32
44
36
34
44
37
32
44
–
–
Data Sheet
42
V1.1, 2003-07
HYS[64/72]D[16x01/32x00/64x20][G/E]U-[5/6/7/8]-B
Unbuffered DDR SDRAM Modules
SPD Contents
Table 21
SPD Codes for PC3200 Modules “–5” (cont’d)
128MB 256MB 256MB 512MB 512MB
× 64 × 64 × 72 × 64 × 72
1 rank 1 rank 1 rank 2 ranks 2 ranks
Byte Description
HEX
31
36
33
30
31
47
55
35
42
20
20
20
20
20
20
xx
HEX
33
32
33
30
30
47
55
35
42
20
20
20
20
20
20
xx
HEX
33
32
33
30
30
47
55
35
42
20
20
20
20
20
20
xx
HEX
36
34
33
32
30
47
55
35
42
20
20
20
20
20
20
xx
HEX
36
34
33
32
30
47
55
35
42
20
20
20
20
20
20
xx
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
Module Part Number, Char 4
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Module Part Number, Char 5
Module Part Number, Char 6
Module Part Number, Char 7
Module Part Number, Char 8
Module Part Number, Char 9
Module Part Number, Char 10
Module Part Number, Char 11
Module Part Number, Char 12
Module Part Number, Char 13
Module Part Number, Char 14
Module Part Number, Char 15
Module Part Number, Char 16
Module Part Number, Char 17
Module Part Number, Char 18
Module Revision Code
Test Program Revision Code
Module Manufacturing Date Year
Module Manufacturing Date Week
Module Serial Number
xx
xx
xx
xx
xx
xx
xx
xx
xx
xx
xx
xx
xx
xx
xx
xx
xx
xx
xx
xx
Module Serial Number
xx
xx
xx
xx
xx
Module Serial Number
xx
xx
xx
xx
xx
Module Serial Number
xx
xx
xx
xx
xx
99 -
127
not used
00
00
00
00
00
Data Sheet
43
V1.1, 2003-07
HYS[64/72]D[16x01/32x00/64x20][G/E]U-[5/6/7/8]-B
Unbuffered DDR SDRAM Modules
Package Outlines
5
Package Outlines
133.35
0.15
A B C
128.95
2.7 MAX.
1)
A
1
2.36
92
6.62
2.175
B
C
±0.1
ø0.1
A B C
64.77
0.4
6.35
±0.1
1.27
49.53
95 x 1.27 = 120.65
±0.1
1.8
0.1
A B C
93
184
3 MIN.
Detail of contacts
1.27
±0.05
1
0.1
A B C
1) On ECC modules only
Burr max. 0.4 allowed
L-DIM-184-18
Figure 7
Package Outline - Raw Card C (128 MByte, 1 Rank Module)
Data Sheet
44
V1.1, 2003-07
HYS[64/72]D[16x01/32x00/64x20][G/E]U-[5/6/7/8]-B
Unbuffered DDR SDRAM Modules
Package Outlines
133.35
128.95
0.15
A B C
2.7 MAX.
1)
A
1
2.36
92
6.62
2.175
B
C
±0.1
ø0.1
A B C
64.77
0.4
6.35
±0.1
1.27
49.53
95 x 1.27 = 120.65
±0.1
1.8
0.1
A B C
93
184
3 MIN.
Detail of contacts
1.27
±0.05
1
0.1
A B C
1) On ECC modules only
Burr max. 0.4 allowed
L-DIM-184-29
Figure 8
Package Outline - Raw Card A (256 MByte, 1 Rank Module, –7 and –8)
Data Sheet
45
V1.1, 2003-07
HYS[64/72]D[16x01/32x00/64x20][G/E]U-[5/6/7/8]-B
Unbuffered DDR SDRAM Modules
Package Outlines
133.35
0.15
A B C
128.95
4 MAX.
A
1)
1
2.36
92
6.62
2.175
B
C
±0.1
ø0.1
A B C
64.77
0.4
6.35
±0.1
1.27
49.53
95 x 1.27 = 120.65
±0.1
1.8
0.1
A B C
93
184
1)
3 MIN.
Detail of contacts
1.27
±0.05
1
0.1
A B C
1) On ECC modules only
Burr max. 0.4 allowed
L-DIM-184-9
Figure 9
Package Outline - Raw Card B (512 MByte, 2 Rank Module, –7 and –8)
Data Sheet
46
V1.1, 2003-07
HYS[64/72]D[16x01/32x00/64x20][G/E]U-[5/6/7/8]-B
Unbuffered DDR SDRAM Modules
Package Outlines
133.35
0.15
A B C
128.95
2.7 MAX.
1)
A
1
2.36
92
6.62
2.175
B
C
±0.1
ø0.1
A B C
64.77
0.4
6.35
±0.1
1.27
49.53
95 x 1.27 = 120.65
±0.1
1.8
0.1
A B C
93
184
3 MIN.
Detail of contacts
1.27
±0.05
1
0.1
A B C
1) On ECC modules only
Burr max. 0.4 allowed
L-DIM-184-30
Figure 10 Package Outline - Raw Card A (256 MByte, 1 Rank Module, –5 and –6, ECC)
Data Sheet
47
V1.1, 2003-07
HYS[64/72]D[16x01/32x00/64x20][G/E]U-[5/6/7/8]-B
Unbuffered DDR SDRAM Modules
Package Outlines
133.35
0.15
A B C
128.95
4 MAX.
1)
A
1
2.36
92
6.62
2.175
B
C
±0.1
ø0.1
A B C
64.77
0.4
6.35
±0.1
1.27
49.53
95 x 1.27 = 120.65
±0.1
1.8
0.1
A B C
93
184
3 MIN.
Detail of contacts
1.27
±0.05
1
0.1
A B C
1) On ECC modules only
Burr max. 0.4 allowed
L-DIM-184-31
Figure 11 Package Outline - Raw Card B (512 MByte, 2 Rank Module, –5 and –6, ECC)
Data Sheet
48
V1.1, 2003-07
HYS[64/72]D[16x01/32x00/64x20][G/E]U-[5/6/7/8]-B
Unbuffered DDR SDRAM Modules
Package Outlines
133.35
0.15
A B C
128.95
2.7 MAX.
A
1
2.36
92
6.62
2.175
B
C
±0.1
ø0.1
A B C
64.77
0.4
6.35
±0.1
1.27
49.53
95 x 1.27 = 120.65
±0.1
1.8
0.1
A B C
93
184
3 MIN.
Detail of contacts
1.27
±0.05
1
0.1
A B C
Burr max. 0.4 allowed
Figure 12 Package Outline - Raw Card A (256 MByte, 1 Rank Module, –5 and –6, Non ECC)
L-DIM-184-32
Data Sheet
49
V1.1, 2003-07
HYS[64/72]D[16x01/32x00/64x20][G/E]U-[5/6/7/8]-B
Unbuffered DDR SDRAM Modules
Package Outlines
133.35
0.15
A B C
128.95
4 MAX.
A
1
2.36
92
6.62
2.175
B
C
±0.1
ø0.1
A B C
64.77
0.4
6.35
±0.1
1.27
49.53
95 x 1.27 = 120.65
±0.1
1.8
0.1
A B C
93
184
3 MIN.
Detail of contacts
1.27
±0.05
1
0.1
A B C
Burr max. 0.4 allowed
Figure 13 Package Outline - Raw Card B (512 MByte, 2 Rank Module, –5 and –6, Non ECC)
L-DIM-184-33
Data Sheet
50
V1.1, 2003-07
w w w . i n f i n e o n . c o m
Published by Infineon Technologies AG
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