HYS64V16220GU-7.5-B [INFINEON]
Synchronous DRAM Module, 32MX64, 5.4ns, CMOS, DIMM-168;
| 型号： | HYS64V16220GU-7.5-B |
| 厂家： | 
Infineon |
| 描述： | Synchronous DRAM Module, 32MX64, 5.4ns, CMOS, DIMM-168 动态存储器 内存集成电路 |
| 文件： | 总18页 (文件大小：120K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HYS 64/72V8300/16220GU
SDRAM-Modules
3.3 V 8M × 64/72-Bit 1 Bank SDRAM Module
3.3 V 16M × 64/72-Bit 2 Bank SDRAM Module
168-Pin Unbuffered DIMM Modules
• 168-Pin unbuffered 8-Byte Dual-In-Line
SDRAM Modules for PC main memory
applications
• Programmed Latencies:
Product Speed
CL tRCD
tRP
3
-7.5
-8
PC133
PC100
3
2
3
2
• PC100 and PC133 versions
2
• 1 bank 8M × 64, 8M × 72 and 2 bank
16M × 64, 16M × 72 organzation
• Single +3.3 V(±0.3 V) Power Supply
• Optimized for byte-write non-parity (x64) or
ECC (x72) applications
• Programmable CAS Latency, Burst Length,
and Wrap Sequence
(Sequential and Interleave)
• JEDEC standard Synchronous DRAMs
(SDRAM)
• Auto-Refresh (CBR) and Self-Refresh
• Decoupling capacitors mounted on substrate
• All inputs and outputs are LVTTL compatible
• Serial Presence Detect with E2PROM
• Fully PC board layout compatible to INTEL’s
Rev. 1.0 Module Specification
• SDRAM Performance:
-7.5
-8
Unit
• Utilizes 8M × 8 SDRAMs in TSOPII-54
packages with 4096 refresh cycles every
64 ms
PC133 PC100
fCK Clock
Frequency
(max.)
133
100
6
MHz
• 133.35 mm × 31.75 mm × 4,00 mm card size
with gold-contact pads
tAC Clock Access 5.4
ns
Time
The HYS 64(72)8300 and HYS 64(72)16220 are industry-standard 168-pin 8-byte Dual In-line
Memory Modules (DIMMs) which are organized as 8M × 64, 8M × 72 in 1 bank and 16M × 64 and
16M × 72 in two banks of high-speed memory arrays designed with 64M Synchronous DRAMs
(SDRAMs) for non-parity and ECC applications. The DIMMs use -7.5 speed sorted 8M × 8 SDRAM
devices in TSOP54 packages to meet the PC133-333 requirements and use -8 components for the
standard PC100-222 applications. Decoupling capacitors are mounted on the PC board. The PC
board design is in accordance with INTEL’s PC SDRAM Rev. 1.0 Module Specification. The DIMMs
have Serial Presence Detect, implemented with a serial E2PROM using the two-pin I2C protocol.
The first 128 bytes are utilized by the DIMM manufacturer and the second 128 bytes are available
to the end user. All INFINEON 168-pin DIMMs provide a high performance, flexible 8-byte interface
in a 133.35 mm long footprint, with 1.25“ (31.75 mm) height.
Data Book
1
12.99
HYS 64/72V8300/16220GU
SDRAM-Modules
Ordering Information
Type
Code
Package
Descriptions
Module
Height
64 MByte DIMMs
HYS 64V8300GU-7.5-… PC133-333-520 L-DIM-168-33 133 Mhz 8M × 64 1 bank 1.25“
SDRAM module
HYS 72V8300GU-7.5-… PC133-333-520 L-DIM-168-33 133 Mhz 8M × 72 1 bank 1.25“
SDRAM module
HYS 64V8300GU-8-…
HYS 72V8300GU-8-…
128 MByte DIMMs
PC100-222-620 L-DIM-168-33 100 MHz 8M × 64 1 bank 1.25“
SDRAM module
PC100-222-620 L-DIM-168-33 100 MHz 8M × 72 1 bank 1.25“
SDRAM module
HYS 64V16220GU-7.5-… PC133-333-520 L-DIM-168-30 133 MHz 16M × 64
1.25“
1.25“
1.25“
1.25“
2 bank SDRAM module
HYS 72V16220GU-7.5-… PC133-333-520 L-DIM-168-30 133 Mhz 16M × 72
2 bank SDRAM module
HYS 64V16220GU-8-…
HYS 72V16220GU-8-…
PC100-222-620 L-DIM-168-30 100 MHz 16M × 64
2 bank SDRAM module
PC100-222-620 L-DIM-168-30 100 Mhz 16M × 72
2 bank SDRAM module
Note: All part numbers end with a place code (not shown), designating the die revision. Consult
factory for current revision. Example: HYS 64V8300GU-8-B, indicates that Rev.B dies are
used for SDRAM components.
Data Book
2
12.99
HYS 64/72V8300/16220GU
SDRAM-Modules
Pin Definitions and Functions
A0-A11
Address Inputs
Bank Selects
WE
Read/Write Input VSS Ground
BA0, BA1
CKE0, CKE1
CLK0 - CLK3
Clock Enable
Clock Input
SCL Clock for SPD
SDA Serial Data Out
N.C. No Connection
DQ0 - DQ63 Data Input/Output
CB0-CB7
Check Bits
(x72 only)
DQMB0 - DQMB7 Data Mask
RAS
Row Address Strobe CS0 - CS3
Chip Select
–
–
–
–
CAS
Column Address
Strobe
VDD
Power (+3.3 V)
Address Format
Part Number
Rows
12
Columns Bank Select Refresh Period Interval
8M × 64
8M × 72
HYS 64V8300GU
HYS 72V8300GU
9
9
9
9
2
2
2
2
4k
4k
4k
4k
64 ms 15,6 µs
64 ms 15,6 µs
64 ms 15,6 µs
64 ms 15,6 µs
12
16M × 64 HYS 64V16220GU 12
16M × 72 HYS 72V16220GU 12
Pin Configuration
PIN# Symbol
PIN# Symbol
PIN# Symbol
PIN# Symbol
1
VSS
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
VSS
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
VSS
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
VSS
2
DQ0
DQ1
DQ2
DQ3
VDD
DU
DQ32
DQ33
DQ34
DQ35
VDD
CKE0
CS3
3
CS2
4
DQMB2
DQMB3
DU
DQMB6
DQMB7
N.C.
5
6
7
DQ4
DQ5
DQ6
DQ7
DQ8
VSS
VDD
DQ36
DQ37
DQ38
DQ39
DQ40
VSS
VDD
8
N.C.
N.C.
9
N.C.
N.C.
10
11
12
13
14
15
16
N.C. (CB2)
N.C. (CB3)
VSS
CB6
CB7
VSS
DQ9
DQ10
DQ11
DQ12
DQ16
DQ17
DQ18
DQ19
DQ41
DQ42
DQ43
DQ44
DQ48
DQ49
DQ50
DQ51
Data Book
3
12.99
HYS 64/72V8300/16220GU
SDRAM-Modules
Pin Configuration (cont’d)
PIN# Symbol PIN# Symbol
PIN# Symbol
PIN# Symbol
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
DQ13
VDD
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
VDD
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
DQ45
VDD
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
VDD
DQ20
N.C.
DQ52
N.C.
DU
DQ14
DQ15
N.C. (CB0)
N.C. (CB1)
VSS
DQ46
DQ47
N.C. (CB4)
N.C. (CB5)
VSS
DU
CKE1
VSS
N.C.
VSS
DQ21
DQ22
DQ23
VSS
DQ53
DQ54
DQ55
VSS
N.C.
N.C.
VDD
N.C.
N.C.
VDD
WE
DQ24
DQ25
DQ26
DQ27
VDD
CAS
DQMB4
DQMB5
CS1
DQ56
DQ57
DQ58
DQ59
VDD
DQMB0
DQMB1
CS0
DU
RAS
VSS
VSS
DQ28
DQ29
DQ30
DQ31
VSS
DQ60
DQ61
DQ62
DQ63
VSS
A0
A1
A2
A3
A4
A5
A6
A7
A8
CLK2
N.C.
A9
CLK3
N.C.
SA0
A10
BA0
BA1
WP
A11
VDD
SDA
SCL
VDD
SA1
VDD
CLK1
N.C.
SA2
CLK0
VDD
VDD
Note: Pin names in parentheses are for the x72 ECC versions; example: Pin 106 = (CB5).
Data Book
4
12.99
HYS 64/72V8300/16220GU
SDRAM-Modules
WE
CS0
CS
DQM
WE
CS
DQM
WE
DQMB0
DQ(7:0)
DQMB4
DQ0-DQ7
DQ(39:32)
DQ0-DQ7
D0
D4
CS
DQM
WE
CS
DQM
WE
DQMB1
DQMB5
DQ(15:8)
DQ0-DQ7
DQ(47:40)
DQ0-DQ7
D1
D5
CS
WE
DQM
CB(7:0)
CS2
DQ0-DQ7
D8
CS
DQM
WE
CS
DQM
WE
DQMB2
DQMB6
DQ(23:16)
DQ0-DQ7
DQ(55:48)
DQ0-DQ7
D2
D6
CS
DQM
WE
CS
DQM
WE
DQMB3
DQMB7
DQ(31:24)
DQ0-DQ7
DQ(63:56)
DQ0-DQ7
D3
D7
A0-A11, BA0, BA1
VCC
D0-D7, (D8)
D0-D7, (D8)
D0-D7, (D8)
D0-D7, (D8)
D0-D7, (D8)
D0-D7, (D8)
E2PROM (256 word x 8 Bit)
SA0
SA0
SA1
SA2
SCL
SA1
SA2
SCL
SDA
WP
C0-C15, (C16, C17)
VSS
47 k
Ω
RAS
CAS
CKE0
Clock Wiring
8 M x 64
8 M x 72
5 SDRAM
CLK0
4 SDRAM + 3.3 pF
Termination
CLK1
CLK2
CLK3
Termination
4 SDRAM + 3.3 pF
Termination
4 SDRAM + 3.3 pF
Termination
Note: D8 is only used in the x72 ECC version.
SPB03958
Block Diagram for 8M × 64/72 SDRAM DIMM Modules (HYS 64/72V82(3)00GU)
Data Book
5
12.99
HYS 64/72V8300/16220GU
SDRAM-Modules
CS1
CS0
CS
CS
CS
CS
DQMB0
DQ(7:0)
DQM
DQM
DQMB4
DQM
DQM
DQ0-DQ7
DQ0-DQ7
DQ(39:32)
DQ0-DQ7
DQ0-DQ7
D0
D1
D8
D9
D4
D5
D12
D13
CS
CS
CS
CS
DQMB1
DQM
DQM
DQMB5
DQM
DQM
DQ(15:8)
DQ0-DQ7
DQ0-DQ7
DQ(47:40)
DQ0-DQ7
DQ0-DQ7
CS
CS
DQM
DQM
DQ0-DQ7
CB(7:0)
DQ0-DQ7
D16
D17
CS3
CS2
CS
CS
CS
CS
DQMB2
DQM
DQM
DQMB6
DQM
DQM
DQ(23:16)
DQ0-DQ7
DQ0-DQ7
DQ(55:48)
DQ0-DQ7
DQ0-DQ7
D2
D3
D10
D11
D6
D7
D14
D15
CS
CS
CS
CS
DQMB3
DQM
DQM
DQMB7
DQM
DQM
DQ(31:24)
DQ0-DQ7
DQ0-DQ7
DQ(63:56)
DQ0-DQ7
DQ0-DQ7
A0-A11, BA0, BA1
VDD
D0-D15, (D16, D17)
D0-D15, (D16, D17)
D0-D7, (D8)
E2PROM (256 Word x 8 Bit)
SA0
SA0
SA1
SA2
SCL
SA1
SA2
SCL
SDA
WP
C0-C31, (C32...C35)
VSS
47 k
Ω
RAS, CAS, WE
CKE0
D0-D15, (D16, D17)
D0-D7, (D16)
Clock Wiring
16 M x 64
VDD
10 k
16 M x 72
5 SDRAM
5 SDRAM
4 SDRAM + 3.3 pF
4 SDRAM + 3.3 pF
Ω
CLK0
4 SDRAM + 3.3 pF
4 SDRAM + 3.3 pF
4 SDRAM + 3.3 pF
4 SDRAM + 3.3 pF
CLK1
CLK2
CLK3
CKE1
D9-D15, (D17)
SPB03769
Note: D16 & D17 is only used in the x72 ECC version and all resistor values are 10 Ω except otherwise noted.
Block Diagram for 16M × 64/72 SDRAM DIMM Modules (HYS 64/72V1620GU)
Data Book
6
12.99
HYS 64/72V8300/16220GU
SDRAM-Modules
DC Characteristics
TA = 0 to 70 °C; VSS = 0 V; VDD,VDDQ = 3.3 V ±0.3 V
Parameter
Symbol
Limit Values
max.
Unit
min.
2.0
–0.5
2.4
–
Input High Voltage
VIH
V
DD + 0.3
V
Input Low Voltage
VIL
0.8
–
V
Output High Voltage (IOUT = – 4.0 mA)
Output Low Voltage (IOUT = 4.0 mA)
VOH
VOL
II(L)
V
0.4
40
V
Input Leakage Current, any input
–40
µA
(0 V < VIN < 3.6 V, all other inputs = 0 V)
Output Leakage Current
IO(L)
–40
40
µA
(DQ is disabled, 0 V < VOUT < VDD)
Capacitance
TA = 0 to 70 °C; VDD = 3.3 V ±0.3 V, f = 1 MHz
Parameter
Symbol
Limit Values
max. max.
8M × 64 8M × 72 16M × 64 16M × 72
Unit
max.
max.
Input Capacitance
CI1
65
72
105
144
pF
(A0 to A11, BA0, BA1, RAS, CAS, WE)
Input Capacitance (CS0 - CS3)
Input Capacitance (CLK0 - CLK3)
Input Capacitance (CKE0, CKE1)
CCS
32
38
65
13
10
40
40
72
13
10
32
40
65
20
17
40
43
72
20
17
pF
pF
pF
pF
pF
CCLK
CCKE
Input Capacitance (DQMB0 - DQMB7) CI4
Input/Output Capacitance
(DQ0 - DQ63, CB0 - CB7)
CIO
Input Capacitance (SCL, SA0-2)
Input/Output Capacitance
CSC
CSD
8
8
8
8
8
8
8
8
pF
pF
Data Book
7
12.99
HYS 64/72V8300/16220GU
SDRAM-Modules
Operating Currents per SDRAM Component 1)
TA = 0 to 70 oC, VDD = 3.3 V ±0.3 V
(Recommended Operating Conditions unless otherwise noted)
Parameter
Test
Symbol -7.5
-8
Unit Note
Condition
max.
1)
Operating Current
–
ICC1
120
110
mA
tRC = tRCMIN., tCK = tCKMIN.
Outputs open, Burst Length = 4, CL = 3
All banks operated in random access,
all banks operated in ping-pong manner
to maximize gapless data access
1)
Precharge Standby Current
in Power Down Mode
t
CK = min.
ICC2P
2
1
2
1
mA
1)
tCK = Infinity
ICC2PS
mA
CS = VIH (min.), CKE ≤ VIL(MAX)
1)
Precharge Stand-by Current
in Non-Power Down Mode
t
CK = min.
ICC2N
40
5
35
5
mA
1)
tCK = Infinity
ICC2NS
mA
CS = VIH (MIN.), CKE ≥ VIH(MIN)
1)
No Operating Current
CKE ≥ VIH(MIN.) ICC3N
CKE ≤ VIL(MAX.) ICC3P
50
8
45
8
mA
1)
mA
tCK = min., CS = VIH(MIN),
active state (max. 4 banks)
1), 2)
Burst Operating Current
–
–
–
ICC4
ICC5
ICC6
80
140
1
70
130
1
mA
tCK = min.,
Read command cycling
1)
Auto-Refresh Current
mA
tCK = min.,
Auto-Refresh command cycling
1)
Self-Refresh Current
mA
Self-Refresh Mode, CKE = 0.2 V
Data Book
8
12.99
HYS 64/72V8300/16220GU
SDRAM-Modules
3), 4)
AC Characteristics
TA = 0 to 70 °C; VSS = 0 V; VDD = 3.3 V ±0.3 V, tT = 1 ns
Parameter
Symbol
Limit Values
Unit Note
-7.5
-8
PC133-333
PC100-222
min.
max.
min.
max.
Clock and Access Time
Clock Cycle Time
CAS Latency = 3
CAS Latency = 2
tCK
fCK
tAC
–
7.5
10
–
–
10
10
–
–
ns
ns
System Frequency
CAS Latency = 3
CAS Latency = 2
–
MHz
–
–
133
100
–
–
100
100
MHz
4), 5)
Clock Access Time
CAS Latency = 3
CAS Latency = 2
–
–
5.4
6
–
–
6
6
ns
ns
6)
Clock High Pulse Width
Clock Low Pulse Width
tCH
tCL
2.5
2.5
–
–
3
3
–
–
ns
6)
ns
Setup & Hold Parameters
Input Setup Time
7)
tIS
1.5
0.8
–
–
–
1
–
–
–
2
1
–
1
2
1
–
–
1
–
–
–
ns
7)
Input Hold Time
tIH
tSB
ns
8)
Power Down Mode Entry Time
CLK
9)
Power Down Mode Exit Setup Time tPDE
1
CLK
Mode Register Setup Time
Transition Time (rise and fall)
tRSC
tT
2
CLK
1
ns
–
Common Parameters
RAS to CAS Delay
Precharge Time
tRCD
tRP
tRAS
tRC
20
20
45
67.5
15
1
–
20
20
50
70
16
1
–
ns
–
–
–
–
–
–
–
–
ns
Active Command Period
Cycle Time
100k
100k
ns
–
–
–
–
–
–
ns
Bank-to-Bank Delay Time
tRRD
ns
CAS to CAS Delay Time (same bank) tCCD
CLK
Data Book
9
12.99
HYS 64/72V8300/16220GU
SDRAM-Modules
AC Characteristics (cont’d) 3), 4)
TA = 0 to 70 °C; VSS = 0 V; VDD = 3.3 V ±0.3 V, tT = 1 ns
Parameter
Symbol
Limit Values
Unit Note
-7.5
-8
PC133-333
PC100-222
min.
max.
min.
max.
Refresh Cycle
Refresh Period (4096 cycles)
Self-Refresh Exit Time
tREF
–
1
64
–
–
1
64
–
ms
10)
tSREX
CLK
Read Cycle
4)
Data Out Hold Time
tOH
tLZ
3
0
3
–
–
–
7
2
3
0
3
–
–
–
8
2
ns
Data Out to Low Impedance
Data Out to High Impedance
DQM Data Out Disable Latency
ns
–
11
tHZ
ns
tDQZ
CLK
–
Write Cycle
Data Input to Precharge
(write recovery)
tWR
2
0
–
–
2
0
–
–
CLK
CLK
–
–
DQM Write Mask Latency
tDQW
Data Book
10
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HYS 64/72V8300/16220GU
SDRAM-Modules
Notes
1. These parameters depend on the cycle rate. These values are measured at 133 MHz for -7.5
modules and at 100 Mhz for -8 modules. Input signals are changed once during tCK, except for
I
CC6 and for standby currents when tCK = infinity. All values are shown per memory component.
2. These parameters are measured with continuous data stream during read access and all DQ
toggling. CL = 3 and BL = 4 assumed and the VDDQ current is excluded.
3. All AC characteristics are shown on SDRAM component level.
An initial pause of 100 µs is required after power-up, then a Precharge All Banks command must
be given followed by eight Auto-Refresh (CBR) cycles before the Mode Register Set Operation
can begin.
4. AC timing tests have VIL = 0.4 V and VIH = 2.4 V with the timing referenced to the 1.4 V crossover
point. The transition time is measured between VIH and VIL. All AC measurements assume
tT = 1 ns with the AC output load circuit show. Specified tAC and tOH parameters are measured
with a 50 pF only, without any resistive termination and with a input signal of 1 V/ns edge rate
between 0.8 V and 2.0 V.
5. If clock rising time is longer than 1 ns, a time (tT/2 – 0.5) ns must be added to this parameter.
6. Rated at 1.4 V
7. If tT is longer than 1 ns, a time (tT – 1) ns has to be added to this parameter.
8. Anytime the Refresh Period has been exceeded, a minimum of two Auto-Refresh (CBR)
commands must be given to “wake-up” the device.
9. Timing is asynchronous. If setup time is not met by rising edge of the clock then the CKE signal
is assumed latched on the next cycle.
10.Self-Refresh Exit is a synchronous operation and begins on the second positive clock edge after
CKE returns high. Self-Refresh Exit is not complete until a time period equal to tRC is satisfied
after the Self Refresh Exit command is registered.
11.This is referenced to the time at which the output achieves the open circuit condition, not to
output voltage levels.
tCH
2.4 V
0.4 V
CLOCK
tT
tCL
tHOLD
tSETUP
INPUT
1.4 V
tAC
tAC
tLZ
tOH
I/O
OUTPUT
1.4 V
50 pF
tHZ
Measurement conditions for
AC and tOH
SPT03404
t
A Serial Presence Detect storage device—E2PROM—is assembled onto the module. Information
about the module configuration, speed, etc. is written into the E2PROM device during module
production using a Serial Presence Detect protocol (I2C synchronous 2-wire bus).
Data Book
11
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HYS 64/72V8300/16220GU
SDRAM-Modules
SPD-Table for PC133 Modules
Byte# Description
SPD Entry Value
Hex
8M × 64 8M × 72 16M × 64 16M × 72
-7.5
80
-7.5
80
-7.5
80
-7.5
80
0
1
2
3
Number of SPD Bytes
Total Bytes in Serial PD
Memory Type
128
256
08
08
08
08
SDRAM
04
04
04
04
Number of Row Addresses 12
(without BS bits)
0C
0C
0C
0C
4
Number of Column
Addresses (for
9
09
09
09
09
8M × 8 SDRAMs)
Number of DIMM Banks
Module Data Width
5
6
7
8
9
1/2
01
40
00
01
75
01
48
00
01
75
02
40
00
01
75
02
48
00
01
75
64/72
Module Data Width (cont’d) 0
Module Interface Levels
SDRAM Cycle Time at
CL = 3
LVTTL
7.5 ns
10
SDRAM Access time from
Clock at CL = 3
5.4 ns
54
54
54
54
11
12
Dimm Config
none/ECC
Self-Refresh,
15.6 µs
x8
00
80
02
80
00
80
02
80
Refresh Rate/Type
13
14
SDRAM Width, primary
Error Checking SDRAM
data width
08
00
08
08
08
00
08
08
n/a/x8
15
16
Minimum Clock Delay for
Back-to-Back Random
Column Address
t
CCD = 1 CLK
01
01
8F
01
8F
01
8F
Burst Length supported
1, 2, 4, 8 & full
page
8F
04
17
18
Number of SDRAM Banks
Supported CAS Latencies
4
04
06
04
06
04
06
CAS latency = 2 06
& 3
19
20
21
CS Latencies
CS latency = 0
01
01
01
00
01
01
00
01
01
00
WE Latencies
Write latency = 0 01
non buffered/non 00
reg.
SDRAM DIMM Module
Attributes
22
23
24
SDRAM Device Attributes
General
V
DD tol ±10%
0E
A0
60
0E
A0
60
0E
A0
60
0E
A0
60
Min. Clock Cycle Time at
CAS Latency = 2
Max. Data Access Time
from Clock for CL = 2
10.0 ns
6.0 ns
Data Book
12
12.99
HYS 64/72V8300/16220GU
SDRAM-Modules
SPD-Table for PC133 Modules (cont’d)
Byte# Description SPD Entry Value
Hex
8M × 64 8M × 72 16M × 64 16M × 72
-7.5
-7.5
-7.5
-7.5
25
26
27
28
29
30
31
Minimum Clock Cycle Time not supported
at CL = 1
FF
FF
FF
FF
Maximum Data Access
Time from Clock at CL = 1
Minimum Row Precharge
Time
not supported
20 ns
FF
14
0F
14
2D
10
FF
14
0F
14
2D
10
FF
14
0F
14
2D
10
FF
14
0F
14
2D
10
Minimum Row Active to
Row Active delay tRRD
Minimum RAS to CAS
Delay tRCD
15
20 ns
Minimum RAS Pulse Width 45 ns
tRAS
Module Bank Density (per
bank)
64 MByte
32
33
34
SDRAM Input Setup Time 1.5 ns
15
08
15
15
08
15
15
08
15
15
08
15
SDRAM Input Hold Time
SDRAM Data Input Hold
Time
0.8 ns
1.5 ns
35
SDRAM Data Input Setup
Time
0.8 ns
08
08
08
08
62-61 Superset Information (may
be used in future)
–
FF
FF
FF
FF
62
63
SPD Revision
Revision 1.2
12
82
XX
12
94
XX
12
83
XX
12
95
XX
Checksum for Bytes 0 - 62
–
–
64-125 Manufacturers Information
(optional), (FFH if not used)
126
Frequency Specification
133 MHz Support Details
Unused Storage Locations
64
64
64
64
127
–
–
AD
FF
AD
FF
FD
FF
FD
FF
128+
Data Book
13
12.99
HYS 64/72V8300/16220GU
SDRAM-Modules
SPD-Table for PC100 Modules
Byte# Description
SPD Entry Value
Hex
8M × 64 8M × 72 16M × 64 16M × 72
-8
-8
-8
-8
0
1
2
3
Number of SPD Bytes
Total Bytes in Serial PD
Memory Type
128
80
08
04
0C
80
08
04
0C
80
08
04
0C
80
08
04
0C
256
SDRAM
Number of Row Addresses 12
(without BS bits)
4
Number of Column
Addresses (for
9
09
09
09
09
8M × 8 SDRAMs)
Number of DIMM Banks
Module Data Width
5
6
7
8
9
1/2
01
40
00
01
A0
01
48
00
01
A0
02
40
00
01
A0
02
48
00
01
A0
64/72
Module Data Width (cont’d) 0
Module Interface Levels
SDRAM Cycle Time at
CL = 3
LVTTL
10.0 ns
10
SDRAM Access time from
Clock at CL = 3
6.0 ns
60
60
60
60
11
12
Dimm Config
none/ECC
Self-Refresh,
15.6 µs
x8
00
80
02
80
00
80
02
80
Refresh Rate/Type
13
14
SDRAM Width, primary
Error Checking SDRAM
Data Width
08
00
08
08
08
00
08
08
n/a/x8
15
16
Minimum Clock Delay for
Back-to-Back Random
Column Address
t
CCD = 1 CLK
01
01
8F
01
8F
01
8F
Burst Length Supported
1, 2, 4, 8 & full
page
8F
04
17
18
Number of SDRAM Banks
4
04
06
04
06
04
06
Supported CAS Latencies CASlatency = 2& 06
3
19
20
21
CS Latencies
CS latency = 0
01
01
01
00
01
01
00
01
01
00
WE Latencies
Write latency = 0 01
non buffered/non 00
reg.
SDRAM DIMM Module
Attributes
22
23
24
SDRAM Device Attributes
General
V
DD tol ±10%
0E
A0
60
0E
A0
60
0E
A0
60
0E
A0
60
Min. Clock Cycle Time at
CAS Latency = 2
Max. Data Access Time
from Clock for CL = 2
10.0/12.0 ns
6.0/7.0 ns
Data Book
14
12.99
HYS 64/72V8300/16220GU
SDRAM-Modules
SPD-Table for PC100 Modules
Byte# Description
SPD Entry Value
Hex
8M × 64 8M × 72 16M × 64 16M × 72
-8
-8
-8
-8
25
26
27
28
29
30
31
Minimum Clock Cycle Time not supported
at CL = 1
FF
FF
FF
FF
Maximum Data Access
Time from Clock at CL = 1
Minimum Row Precharge
Time
not supported
20/30 ns
16/20 ns
20 ns
FF
14
10
14
2D
10
FF
14
10
14
2D
10
FF
14
10
14
2D
10
FF
14
10
14
2D
10
Minimum Row Active to
Row Active delay tRRD
Minimum RAS to CAS
delay tRCD
Minimum RAS Pulse Width 45 ns
tRAS
Module Bank Density
(per bank)
64 MByte
32
33
34
SDRAM Input Setup Time 2 ns
20
10
20
20
10
20
20
10
20
20
10
20
SDRAM Input Hold Time
SDRAM Data Input Hold
Time
1 ns
2 ns
35
SDRAM Data Input Setup 1 ns
Time
10
10
10
10
62-61 Superset Information (may
be used in future)
–
FF
FF
FF
FF
62
63
SPD Revision
Revision 1.2
12
12
F2
XX
12
12
F3
XX
Checksum for Bytes 0 - 62
–
–
E0
XX
E1
XX
64-125 Manufacturers Information
(optional), (FFH if not used)
126
Frequency Specification
100 MHz Support Details
Unused Storage Locations
100 MHz
64
AF
FF
64
AF
FF
64
FF
FF
64
FF
FF
127
–
–
128+
Data Book
15
12.99
HYS 64/72V8300/16220GU
SDRAM-Modules
Package Outlines
L-DIM-168-30
SDRAM DIMM Module Package
HYS 64/72V16220GU
133.35
127.35
4
*)
1
10
11
6.35
40
41
6.35
84
1.27±
0.1
3
1.27
42.18
91 x 1.27 = 115.57
124 125
2
85 94
95
168
*)
R1.27+0.1
3 min.
2.26
Detail of Contacts
*) on ECC modules only
1±
0.05
1.27
GLD09159
Sorts of Packing
Package outlines for tubes, trays etc. are contained in our
Data Book “Package Information”.
Dimensions in mm
Data Book
16
12.99
HYS 64/72V8300/16220GU
SDRAM-Modules
L-DIM-168-33
SDRAM DIMM Module Package
HYS 64/72V8300GU
133,35
127,35
4,0 max.
x)
84
1
10 11
40 41
+ 0.1
42,18
1,27
-
66,68
A
C
B
85
94 95
124 125
168
6,35
6,35
1,27
1,0 + 0.5
-
+
0,2 0,15
-
2,0
2,0
Detail C
Detail A
Detail B
DM168-33.WMF
x) on ECC modules only
Sorts of Packing
Package outlines for tubes, trays etc. are contained in our
Data Book “Package Information”.
Dimensions in mm
Data Book
17
12.99
HYS 64/72V8300/16220GU
SDRAM-Modules
Update Releases:
April 18, 1999
Input capacitances adjusted according to latested measurements
Infineon logo inserted
-8B speed sort removed
April 19, 1999
June 1, 1999
8300 version on L-DIMM-33 added
Explanation for factory specific code in part numbers added
Byte 22 for PC100 modules changed from 06 to 0E
PC133 spec incorpoated, 8200 versions removed
June 17, 1999
August 3, 1999
August,6,1999
August 23, 1999
August 25,1999
Input capacitances adjusted according to latest measurements (S20 DD2C)
Byte 126 changed to 64h for PC133 modules
Final release after Lauridsen and Lewbel changes
Template from R&L
Sept.30,1999
Dec.2, 1999
Some errors on pages 16 & 17 corrected
Some timing parameters adjusted according to INTELs PC 133 specification
Data Book
18
12.99
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