HYS72D64300EU-5-D [QIMONDA]
DDR DRAM Module, 64MX72, 0.7ns, CMOS, GREEN, UDIMM-184;
| 型号： | HYS72D64300EU-5-D |
| 厂家： | 
QIMONDA AG |
| 描述： | DDR DRAM Module, 64MX72, 0.7ns, CMOS, GREEN, UDIMM-184 动态存储器 双倍数据速率 |
| 文件： | 总39页 (文件大小：1042K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
May 2008
HYS64D32301EU–[5/6]–D
HYS[64/72]D64300EU–[5/6]–D
HYS[64/72]D128320EU–[5/6]–D
184-Pin Unbuffered Double-Data-Rate Memory Modules
UDIMM SDRAM
DDR SDRAM
Advance
Internet Data Sheet
Rev. 0.60
Advance Internet Data Sheet
HYS[64/72]D[64/128]3x0EU–[5/6]–D
Unbuffered DDR SDRAM Modules
HYS64D32301EU–[5/6]–D, HYS[64/72]D64300EU–[5/6]–D
Revision History: 2008-05, Rev. 0.60
Page
Subjects (major changes since last revision)
Added Product type HYS64D[64/128]3x0-6-D and HYS64D32301EU-[5/6]-D and adapted to internet edition.
All
Previous Revision: 2008-04, Rev. 0.53
16, 17 Added IDD values.
Previous Revision: 2008-02, Rev. 0.52
21 - 24 SPD codes updated.
Previous Revision: 2007-10, Rev. 0.51
All
Added products HYS72D[64/128]3x0EU-[5/6]-D
Previous Revision: 2007-09, Rev. 0.50
All
New Document.
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qag_techdoc_A4, 4.20, 2008-01-25
02142008-4Z51-SEDD
2
Advance Internet Data Sheet
HYS[64/72]D[64/128]3x0EU–[5/6]–D
Unbuffered DDR SDRAM Modules
1
Overview
This chapter contains features and the description.
1.1
Features
•
184-Pin Unbuffered Double-Data-Rate Memory Modules (ECC and non-parity) for PC and Workstation main memory
applications
•
•
•
•
•
•
•
•
•
•
•
•
•
One rank 64M x 64, 64M x 72, 32Mx64 and two ranks 128M × 64, 128M × 72 module organization
Standard Double Data Rate Synchronous DRAMs (DDR SDRAM)
Single +2.5V (±0.2V) power supply
Built with 512-Mbit in P-TSOPII-66 package
Programmable CAS Latency, Burst Length, and Wrap Sequence (Sequential & Interleave)
Auto Refresh (CBR) and Self Refresh
All inputs and outputs SSTL_2 compatible
Serial Presence Detect with E2PROM
JEDEC standard MO-206 form factor: 133.35 mm × 31.75 mm × 4.00 mm max.
Standard reference layout
Gold plated contacts
DDR400 speed grade supported
Lead-free
TABLE 1
Performance for –5 and –6
Part Number Speed Code
–5
–6
Unit
Speed Grade
Component
Module
@CL3
DDR400B
PC3200-3033
200
DDR333B
PC2700-2533
166
—
Max. Clock Frequency
fCK3
MHz
MHz
MHz
@CL2.5
@CL2
fCK2.5
fCK2
166
166
133
133
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02142008-4Z51-SEDD
Advance Internet Data Sheet
HYS[64/72]D[64/128]3x0EU–[5/6]–D
Unbuffered DDR SDRAM Modules
1.2
Description
The Qimonda HYS64D[64/128]3x0EU-5-D are industry
standard 184-Pin Unbuffered Double-Data-Rate Memory
Modules (UDIMM) organized as 32Mx64 (256MB),
64M ×64 (512 MB), 64M ×72 (512 MB), 128M ×72 (1 GB)
and 128M ×64 (1 GB) for non-parity and main memory
applications. The memory array is designed with 512Mbit
Double Data Rate Synchronous DRAMs. A variety of
decoupling capacitors are mounted on the printed
circuit board. The DIMMs feature serial presence detect
(SPD) based on a serial E2PROM device using the 2-pin I2C
protocol. The first 128 bytes are programmed with
configuration data and the second 128 bytes are available to
the customer.
TABLE 2
Ordering Information
Product Type
Compliance Code
Description
SDRAM Technology
PC3200 (CL=3.0)
HYS64D32301EU–5–D
HYS64D64300EU–5–D
HYS72D64300EU–5–D
HYS64D128320EU–5–D
HYS72D128320EU–5–D
PC2700 (CL=2.5)
PC3200U–30331–C2
PC3200U–30331–A0
PC3200U–30331–A0
PC3200U–30331–B0
PC3200U–30331–B0
one rank 256MB DIMM
one rank 512 MB DIMM
one rank 512 MB DIMM ECC
two rank 1GB DIMM
512 Mbit (×16)
512 Mbit (×8)
512 Mbit (×8)
512 Mbit (×8)
512 Mbit (×8)
two rank 1GB DIMM ECC
HYS64D32301EU–6–D
HYS64D64300EU–6–D
HYS72D64300EU–6–D
HYS64D128320EU–6–D
HYS72D128320EU–6–D
PC3200U–30331–C2
PC2700U–25331–A0
PC2700U–25331–A0
PC2700U–25331–B0
PC2700U–25331–B0
one rank 256MB DIMM
one rank 512 MB DIMM
one rank 512 MB DIMM ECC
two rank 1GB DIMM
512 Mbit (×16)
512 Mbit (×8)
512 Mbit (×8)
512 Mbit (×8)
512 Mbit (×8)
two rank 1GB DIMM ECC
Note: All product type numbers end with a place code designating the silicon-die revision. Reference information available on
request. Example: HYS72D64300EU-5-D, indicating rev. D dies are used for SDRAM components. The Compliance
Code is printed on the module labels describing the speed sort (for example “PC3200”), the latencies and SPD code
definition (for example “30331” means CAS latency of 3.0 clocks, RCD (Row-Column-Delay) latency of 3 clocks, Row
Precharge latency of 3 clocks, and JEDEC SPD code definiton version 1), and the Raw Card used for this module.
TABLE 3
Address Format
Density
Organization Memory
Ranks
SDRAM
Organization SDRAMs
# of
# of row/bank/
columns bits
Refresh
Period Interval
256 MB
512 MB
512 MB
1 GB
32M ×64
64M ×64
64M ×72
128M ×64
128M ×72
1
1
1
2
2
512M ×16
512M ×8
512M ×8
512M ×8
512M ×8
4
13/2/10
13/2/11
13/2/11
13/2/11
13/2/11
8K
8K
8K
8K
8K
64 ms
64 ms
64 ms
64 ms
64 ms
7.8 ms
7.8 ms
7.8 ms
7.8 ms
7.8 ms
8
8
16
16
1 GB
Rev. 0.60, 2008-05
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02142008-4Z51-SEDD
Advance Internet Data Sheet
HYS[64/72]D[64/128]3x0EU–[5/6]–D
Unbuffered DDR SDRAM Modules
2
Configuration
2.1
Pin Configuration
The pin configuration of the Unbuffered DDR SDRAM DIMM
is listed by function in Table 4 (184 pins). The abbreviations
used in columns Pin and Buffer Type are explained in Table 5
and Table 6 respectively. The pin numbering is depicted in
Figure 1.
TABLE 4
Pin Configuration of UDIMM
Pin#
Name
Pin
Type
Buffer
Type
Function
Clock Signals
137
CK0
I
SSTL
–
Clock Signals 2:0
Note: For clock net loading see block diagram, CK0 is
NC
NC
NC on 1R ×16
16
CK1
CK2
CK0
NC
I
SSTL
SSTL
SSTL
–
76
I
138
I
Complement Clock Signals 2:0
Note: For clock net loading see block diagram, CK0 is
NC
NC on 1R ×16
17
CK1
CK2
CKE0
CKE1
I
I
I
I
SSTL
SSTL
SSTL
SSTL
75
21
Clock Enable Rank 0
Clock Enable Rank 1
Note: 2-rank module
Note: 1-rank module
111
NC
NC
–
Control Signals
157
158
S0
S1
I
I
SSTL
SSTL
Chip Select Rank 0
Chip Select Rank 1
Note: 2-rank module
Note: 1-rank module
Row Address Strobe
Column Address Strobe
Write Enable
NC
NC
–
154
65
RAS
CAS
WE
I
I
I
SSTL
SSTL
SSTL
63
Address Signals
59
52
BA0
BA1
I
I
SSTL
SSTL
Bank Address Bus 2:0
Rev. 0.60, 2008-05
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02142008-4Z51-SEDD
Advance Internet Data Sheet
HYS[64/72]D[64/128]3x0EU–[5/6]–D
Unbuffered DDR SDRAM Modules
Pin#
Name
Pin
Type
Buffer
Type
Function
48
A0
I
I
I
I
I
I
I
I
I
I
I
I
I
I
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
Address Bus 11:0
43
A1
41
A2
130
37
A3
A4
32
A5
125
29
A6
A7
122
27
A8
Address Bus 11:0
A9
141
A10
AP
A11
A12
118
115
Address Signal 12
Note: Module based on 256 Mbit or larger dies
Note: 128 Mbit based module
Address Signal 13
NC
NC
I
–
167
A13
SSTL
Note: 1 Gbit based module
NC
NC
–
Note: Module based on 512 Mbit or smaller dies
Data Signals
2
DQ0
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
Data Bus 63:0
4
DQ1
6
DQ2
8
DQ3
94
95
98
99
12
13
19
20
105
106
109
110
23
24
28
31
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
Rev. 0.60, 2008-05
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02142008-4Z51-SEDD
Advance Internet Data Sheet
HYS[64/72]D[64/128]3x0EU–[5/6]–D
Unbuffered DDR SDRAM Modules
Pin#
Name
Pin
Type
Buffer
Type
Function
114
117
121
123
33
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
Data Bus 63:0
35
39
40
126
127
131
133
53
55
57
60
146
147
150
151
61
64
68
69
153
155
161
162
72
73
79
80
165
166
170
171
83
84
87
88
Rev. 0.60, 2008-05
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02142008-4Z51-SEDD
Advance Internet Data Sheet
HYS[64/72]D[64/128]3x0EU–[5/6]–D
Unbuffered DDR SDRAM Modules
Pin#
Name
Pin
Type
Buffer
Type
Function
174
DQ60
DQ61
DQ62
DQ63
I/O
I/O
I/O
I/O
SSTL
SSTL
SSTL
SSTL
Data Bus 63:0
175
178
179
Check Bit
44
CB0
I/O
SSTL
Check Bit 0
Note: ECC type module
Note: Non-ECC module
Check Bit 1
NC
NC
I/O
–
45
CB1
SSTL
Note: ECC type module
Note: Non-ECC module
Check Bit 2
NC
NC
I/O
–
49
CB2
SSTL
Note: ECC type module
Note: Non-ECC module
Check Bit 3
NC
NC
I/O
–
51
CB3
SSTL
Note: ECC type module
Note: Non-ECC module
Check Bit 4
NC
NC
I/O
–
134
135
142
144
CB4
SSTL
Note: ECC type module
Note: Non-ECC module
Check Bit 5
NC
NC
I/O
–
CB5
SSTL
Note: ECC type module
Note: Non-ECC module
Check Bit 6
NC
NC
I/O
–
CB6
SSTL
Note: ECC type module
Note: Non-ECC module
Check Bit 7
NC
NC
I/O
–
CB7
SSTL
Note: ECC type module
Note: Non-ECC module
Data Strobe Bus 7:0
NC
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
–
5
DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
DQS8
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
14
25
36
56
67
78
86
47
Data Strobe 8
Note: ECC type module
Note: Non-ECC module
NC
NC
–
Rev. 0.60, 2008-05
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02142008-4Z51-SEDD
Advance Internet Data Sheet
HYS[64/72]D[64/128]3x0EU–[5/6]–D
Unbuffered DDR SDRAM Modules
Pin#
Name
Pin
Type
Buffer
Type
Function
97
DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7
DM8
I
I
I
I
I
I
I
I
I
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
Data Mask Bus 7:0
107
119
129
149
159
169
177
140
Data Mask 8
Note: ECC type module
Note: Non-ECC module
NC
NC
–
EEPROM
92
SCL
SDA
SA0
SA1
SA2
I
CMOS
OD
Serial Bus Clock
91
I/O
Serial Bus Data
181
I
I
I
CMOS
CMOS
CMOS
Slave Address Select Bus 2:0
182
183
Power Supplies
1
VREF
AI
–
–
–
I/O Reference Voltage
EEPROM Power Supply
I/O Driver Power Supply
184
VDDSPD
VDDQ
PWR
PWR
15,
22,
30,
54,
62,
77,
96,
104,
112,
128,
136,
143,
156,
164,
172,
180
7,
VDD
PWRzp
–
Power Supply
38,
46,
70,
85,
108,
120,
148,
168
Rev. 0.60, 2008-05
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02142008-4Z51-SEDD
Advance Internet Data Sheet
HYS[64/72]D[64/128]3x0EU–[5/6]–D
Unbuffered DDR SDRAM Modules
Pin#
Name
Pin
Type
Buffer
Type
Function
3,
VSS
GND
–
Ground Plane
11,
18,
26,
34,
42,
50,
58,
66,
74,
81,
89,
93,
100,
116,
124,
132,
139,
145,
152,
160,
176
Other Pins
82
VDDID
O
OD
–
VDD Identification
Note: Pin in tristate, indicating VDD and VDDQ nets
connected on PCB
9,
NC
NC
Not connected
10,
Pins not connected on Qimonda UDIMMs
71,
90,
101,
102,
103,
113,
163,
173
Rev. 0.60, 2008-05
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02142008-4Z51-SEDD
Advance Internet Data Sheet
HYS[64/72]D[64/128]3x0EU–[5/6]–D
Unbuffered DDR SDRAM Modules
TABLE 5
Abbreviations for Pin Type
Abbreviation
Description
I
Standard input-only pin. Digital levels.
Output. Digital levels.
I/O is a bidirectional input/output signal.
Input. Analog levels.
Power
O
I/O
AI
PWR
GND
NC
Ground
Not Connected
TABLE 6
Abbreviations for Buffer Type
Abbreviation
Description
SSTL
Serial Stub Terminated Logic (SSTL2)
Low Voltage CMOS
LV-CMOS
CMOS
OD
CMOS Levels
Open Drain. The corresponding pin has 2 operational states, active low and tristate, and
allows multiple devices to share as a wire-OR.
Rev. 0.60, 2008-05
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02142008-4Z51-SEDD
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Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
ꢁ
ꢁ
ꢁ
ꢁ
ꢁ
ꢁ
ꢁ
ꢁ
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ꢄ
ꢄ
ꢄ
ꢉ
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ꢅ
ꢅ
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ꢅ
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ꢁ
Advance Internet Data Sheet
HYS[64/72]D[64/128]3x0EU–[5/6]–D
Unbuffered DDR SDRAM Modules
FIGURE 1
Pin Configuration 184-Pin, UDIMM
9ꢀ )ꢀꢇꢀ 3
9ꢀ66ꢀꢇꢀ 3
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
ꢁ
ꢁ
ꢁ
ꢁ
ꢁ
ꢁ
ꢁ
ꢁ
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ꢁ
ꢁ
ꢁ
ꢁ
ꢁ
ꢁ
ꢁ
ꢁ
ꢁ
ꢁ
ꢁ
ꢁ
ꢁ
ꢁ
ꢁ
ꢁ
ꢁ
ꢁꢆꢀ
ꢁꢂꢀ
ꢁꢄꢀ
ꢁꢅꢀ
ꢁꢃꢀ
ꢆꢆꢀ
ꢆꢂꢀ
ꢆꢄꢀ
ꢆꢅꢀ
ꢆꢃꢀ
ꢋꢆꢀ
ꢋꢂꢀ
ꢋꢄꢀ
ꢋꢅꢀ
ꢋꢃꢀ
ꢂꢆꢀ
ꢂꢂꢀ
ꢂꢄꢀ
ꢂꢅꢀ
ꢂꢃꢀ
ꢈꢆꢀ
ꢈꢂꢀ
ꢈꢄꢀ
ꢈꢅꢀ
ꢈꢃꢀ
ꢄꢆꢀ
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
ꢁ
ꢁ
ꢁ
ꢁ
ꢆ
ꢆ
ꢆ
ꢆ
ꢆ
ꢆ
ꢆ
ꢆ
ꢆ
ꢆ
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ꢆ
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ꢆ
ꢆ
ꢆ
ꢆ
ꢆ
ꢆ
ꢃꢂ
ꢃꢄ
ꢃꢅ
ꢃꢃ
ꢁꢆ
ꢁꢂ
ꢁꢄ
ꢁꢅ
ꢁꢃ
ꢆꢆ
ꢆꢂ
ꢆꢄ
ꢆꢅ
ꢆꢃ
ꢋꢆ
ꢋꢂ
ꢋꢄ
ꢋꢅ
ꢋꢃ
ꢂꢆ
ꢂꢂ
ꢂꢄ
ꢂꢅ
ꢂꢃ
ꢈꢆ
ꢈꢂ
ꢀꢇꢀ 9ꢀ
5(
66ꢀ
'
'
'
'
4
4
4
4
ꢁ
ꢁ
ꢁ
ꢁ
ꢁꢀꢇꢀ 3
ꢆꢀꢇꢀ 3
ꢋꢀꢇꢀ 3
ꢂꢀꢇꢀ 3
ꢀꢇꢀ 3
ꢊꢀꢇꢀ 3
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
ꢁ
ꢁ
ꢁ
ꢁ
ꢁ
ꢁ
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ꢁ
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ꢁ
ꢁ
ꢁ
ꢁ
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ꢁ
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ꢁ
ꢁ
ꢁ
ꢁ
ꢆ
ꢆ
ꢆ
ꢆ
ꢆ
ꢋ
ꢋ
ꢋ
ꢋ
ꢋ
ꢂ
ꢂ
ꢂ
ꢂ
ꢂ
ꢈ
ꢈ
ꢈ
ꢈ
ꢈ
ꢄ
ꢄ
ꢋꢀ
ꢈꢀ
ꢉꢀ
ꢊꢀ
ꢁꢀ
ꢋꢀ
ꢈꢀ
ꢉꢀ
ꢊꢀ
ꢁꢀ
ꢋꢀ
ꢈꢀ
ꢉꢀ
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ꢁꢀ
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ꢉꢀ
ꢊꢀ
ꢁꢀ
ꢋꢀ
ꢈꢀ
ꢉꢀ
ꢊꢀ
ꢁꢀ
ꢋꢀ
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
LQ
LQ
LQ
LQ
LQ
LQ
LQ
LQ
LQ
LQ
LQ
LQ
LQ
LQ
LQ
LQ
LQ
LQ
LQ
LQ
LQ
LQ
LQ
LQ
LQ
LQ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
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ꢀ
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ꢀ
ꢀ
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ꢁꢃ
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ꢁꢃ
ꢆꢁ
ꢆꢁ
ꢆꢁ
ꢆꢁ
ꢆꢁ
ꢆꢆ
ꢆꢆ
ꢆꢆ
ꢆꢆ
ꢆꢆ
ꢆꢋ
ꢆꢋ
ꢆꢋ
ꢆꢋ
ꢆꢋ
ꢆꢂ
ꢆꢂ
ꢆꢂ
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ꢆꢂ
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4
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ꢀꢇꢀ '
ꢀꢇꢀ '
ꢀꢇꢀ 1
ꢀꢇꢀ 1
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ꢀꢇꢀ 1
ꢀꢇꢀ $
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4ꢁ
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9ꢀ
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4ꢀ
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46
ꢁꢀꢇꢀ 3
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4
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9ꢀ
ꢁꢀ ꢇꢀ
66ꢀ
1
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9ꢀ66ꢀꢇꢀ 3
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4
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6
.
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4ꢀ
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0ꢆ
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.
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4ꢂ
ꢋꢀ
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'
4
&
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9ꢀ 4ꢀꢇꢀ 3
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.
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4
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9ꢀ
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4ꢆ
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4ꢀ ꢇꢀ3
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3
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4
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6
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4
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6
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3
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1
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%
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%
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1
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3
ꢀꢇꢀ
ꢀꢇꢀ 9ꢀ
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ꢆꢀ ꢇꢀ3
1
9ꢀ '
9ꢀ
9ꢀ
9ꢀ '
9ꢀ
9ꢀ
9ꢀ
9ꢀ
9ꢀ
9ꢀ
9ꢀ
9ꢀ
9ꢀ '
Rev. 0.60, 2008-05
12
02142008-4Z51-SEDD
Advance Internet Data Sheet
HYS[64/72]D[64/128]3x0EU–[5/6]–D
Unbuffered DDR SDRAM Modules
3
Electrical Characteristics
This chapter lists the electrical characteristics.
3.1
Operating Conditions
This chapter describes the operating conditions.
TABLE 7
Absolute Maximum Ratings
Parameter
Symbol
Values
Unit Note/ Test
Condition
min.
typ. max.
Voltage on I/O pins relative to VSS
Voltage on inputs relative to VSS
Voltage on VDD supply relative to VSS
Voltage on VDDQ supply relative to VSS
Operating temperature (ambient)
Storage temperature (plastic)
VIN, VOUT
VIN
–0.5
–1
–1
–1
0
–
V
DDQ + 0.5
V
–
–
–
–
–
–
–
–
–
+3.6
+3.6
+3.6
+70
+150
–
V
VDD
–
V
VDDQ
TA
–
V
–
°C
°C
W
mA
TSTG
PD
-55
–
–
Power dissipation (per SDRAM component)
Short circuit output current
1
IOUT
–
50
–
Attention: Permanent damage to the device may occur if “Absolute Maximum Ratings” are exceeded. This is a stress
rating only, and functional operation should be restricted to recommended operation conditions. Exposure
to absolute maximum rating conditions for extended periods of time may affect device reliability and
exceeding only one of the values may cause irreversible damage to the integrated circuit.
TABLE 8
Electrical Characteristics and DC Operating Conditions
Parameter
Symbol
Values
Unit Note/Test Condition 1)
Min.
Typ.
Max.
Device Supply Voltage
Device Supply Voltage
Output Supply Voltage
Output Supply Voltage
EEPROM supply voltage
VDD
2.3
2.5
2.3
2.5
2.3
0
2.5
2.6
2.5
2.6
2.5
2.7
2.7
2.7
2.7
3.6
0
V
V
V
V
V
V
fCK ≤ 166 MHz
CK > 166 MHz 2)
fCK ≤ 166 MHz 3)
CK > 166 MHz 2)3)
VDD
f
VDDQ
VDDQ
VDDSPD
f
—
—
Supply Voltage, I/O Supply
Voltage
VSS,
VSSQ
4)
5)
Input Reference Voltage
VREF
VTT
0.49 × VDDQ 0.5 × VDDQ 0.51 × VDDQ
REF – 0.04 REF + 0.04
V
V
I/O Termination Voltage
(System)
V
V
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Unbuffered DDR SDRAM Modules
Parameter
Symbol
Values
Typ.
Unit Note/Test Condition 1)
Min.
Max.
8)
Input High (Logic1) Voltage VIH(DC)
Input Low (Logic0) Voltage VIL(DC)
V
REF + 0.15
V
V
V
DDQ + 0.3
V
8)
–0.3
–0.3
REF – 0.15
DDQ + 0.3
V
8)
Input Voltage Level, CK and VIN(DC)
V
CK Inputs
8)6)
Input Differential Voltage, CK VID(DC)
and CK Inputs
0.36
0.71
–2
V
DDQ + 0.6
V
7)
VI-Matching Pull-up Current VIRatio
to Pull-down Current
1.4
2
—
Input Leakage Current
II
μA
μA
Any input 0 V ≤ VIN ≤ VDD; All
other pins not under test = 0 V
8)9)
Output Leakage Current
IOZ
–5
5
DQs are disabled; 0 V ≤ VOUT
VDDQ
≤
8)
8)
Output High Current, Normal IOH
Strength Driver
–16.2
16.2
—
—
mA VOUT
=
1.95 V
Output Low Current, Normal IOL
mA
V
OUT = 0.35 V8)
Strength Driver
1) 0 °C ≤ TA ≤ 70 °C
2) DDR400 conditions apply for all clock frequencies above 166 MHz
3) Under all conditions, VDDQ must be less than or equal to VDD
4) Peak to peak AC noise on VREF may not exceed ± 2% VREF (DC). VREF is also expected to track noise variations in VDDQ
.
.
5)
V
TT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF, and
must track variations in the DC level of VREF
ID is the magnitude of the difference between the input level on CK and the input level on CK.
.
6)
V
7) The ration of the pull-up current to the pull-down current is specified for the same temperature and voltage, over the entire temperature
and voltage range, for device drain to source voltage from 0.25 to 1.0 V. For a given output, it represents the maximum difference between
pull-up and pull-down drivers due to process variation.
8) Inputs are not recognized as valid until VREF stabilizes.
9) Values are shown per component
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HYS[64/72]D[64/128]3x0EU–[5/6]–D
Unbuffered DDR SDRAM Modules
3.2
Current Conditions and Specification
This chapter describes the Conditions and Specification.
TABLE 9
DD Conditions
I
Parameter
Symbol
Operating Current 0
IDD0
one bank; active/ precharge; DQ, DM, and DQS inputs changing once per clock cycle;
address and control inputs changing once every two clock cycles.
Operating Current 1
IDD1
one bank; active/read/precharge; Burst Length = 4; see component data sheet.
Precharge Power-Down Standby Current
all banks idle; power-down mode; CKE ≤ VIL,MAX
IDD2P
IDD2F
Precharge Floating Standby Current
CS ≥ VIH,,MIN, all banks idle; CKE ≥ VIH,MIN
;
address and other control inputs changing once per clock cycle; VIN = VREF for DQ, DQS and DM.
Precharge Quiet Standby Current
IDD2Q
CS ≥ VIHMIN, all banks idle; CKE ≥ VIH,MIN; VIN = VREF for DQ, DQS and DM;
address and other control inputs stable at ≥ VIH,MIN or ≤ VIL,MAX
.
Active Power-Down Standby Current
one bank active; power-down mode; CKE ≤ VILMAX; VIN = VREF for DQ, DQS and DM.
IDD3P
IDD3N
Active Standby Current
one bank active; CS ≥ VIH,MIN; CKE ≥ VIH,MIN; tRC = tRAS,MAX
DQ, DM and DQS inputs changing twice per clock cycle;
address and control inputs changing once per clock cycle.
;
Operating Current Read
IDD4R
one bank active; Burst Length = 2; reads; continuous burst;
address and control inputs changing once per clock cycle;
50% of data outputs changing on every clock edge;
CL = 2 for DDR266(A), CL = 3 for DDR333 and DDR400B; IOUT = 0 mA
Operating Current Write
IDD4W
one bank active; Burst Length = 2; writes; continuous burst;
address and control inputs changing once per clock cycle;
50% of data outputs changing on every clock edge;
CL = 2 for DDR266(A), CL = 3 for DDR333 and DDR400B
Auto-Refresh Current
IDD5
IDD6
IDD7
t
RC = tRFCMIN, burst refresh
Self-Refresh Current
CKE ≤ 0.2 V; external clock on
Operating Current 7
four bank interleaving with Burst Length = 4; see component data sheet.
Rev. 0.60, 2008-05
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HYS[64/72]D[64/128]3x0EU–[5/6]–D
Unbuffered DDR SDRAM Modules
TABLE 10
DD Specification for HYS64D32301EU–[5/6]–D
I
Product Type
Unit
Note 1)2)
Organization
256 MB
×64
256 MB
×64
1 Rank
–5
1 Rank
–6
Symbol
Typ.
Max.
Typ.
Max.
3)
IDD0
224
256
4
276
312
18
192
220
4
240
272
18
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
3)4)
5)
IDD1
IDD2P
IDD2F
IDD2Q
IDD3P
IDD3N
IDD4R
IDD4W
IDD5
5)
88
120
88
80
108
80
5)
60
56
5)
32
56
32
56
5)
116
292
280
492
6
148
352
340
584
20
104
252
244
440
6
136
308
296
504
20
3)4)
3)
5)
5)
IDD6
3)4)
IDD7
708
852
596
668
1) DRAM component currents only
2) Test condition for maximum values: VDD = 2.7 V, TA = 10 °C
3) The module IDDx values are calculated from the component IDDx data sheet values as: m × IDDx[component] + n × IDD2P[component] with
m and n number of components of rank 1 and 2; n=0 for 1 rank modules
4) DQ I/O (IDDQ) currents are not included into calculations: module IDD values will be measured differently depending on load conditions
5) The module IDDx values are calculated from the component IDDx data sheet values as: (m + n) × IDDx[component]
Rev. 0.60, 2008-05
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HYS[64/72]D[64/128]3x0EU–[5/6]–D
Unbuffered DDR SDRAM Modules
TABLE 11
DD Specification for HYS64D[64/128]3x0EU–[5/6]–D
I
Product Type
Unit
Note 1)2)
Organization
512 MB
×64
512 MB
×64
1 GB
×64
1 GB
×64
1 Rank
–5
1 Rank
–6
2 Ranks
–5
2 Ranks
–6
Symbol
Typ.
Max.
Typ.
Max.
Typ.
Max.
Typ.
Max.
3)
IDD0
432
472
8
520
576
37
368
408
8
456
496
37
440
480
16
557
613
74
376
416
16
493
533
74
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
3)4)
5)
IDD1
IDD2P
IDD2F
IDD2Q
IDD3P
IDD3N
IDD4R
IDD4W
IDD5
5)
176
120
64
240
176
112
296
552
552
1168
40
160
112
64
216
160
112
272
512
512
1008
40
352
240
128
416
464
464
992
24
480
352
224
592
589
589
1205
80
320
224
128
368
400
400
888
24
432
320
224
544
549
549
1045
80
5)
5)
5)
208
456
456
984
12
184
392
392
880
12
3)4)
3)
5)
5)
IDD6
3)4)
IDD7
1328
1584
1112
1424
1336
1621
1120
1461
1) DRAM component currents only
2) Test condition for maximum values: VDD = 2.7 V, TA = 10 °C
3) The module IDDx values are calculated from the component IDDx data sheet values as: m × IDDx[component] + n × IDD2P[component] with
m and n number of components of rank 1 and 2; n=0 for 1 rank modules
4) DQ I/O (IDDQ) currents are not included into calculations: module IDD values will be measured differently depending on load conditions
5) The module IDDx values are calculated from the component IDDx data sheet values as: (m + n) × IDDx[component]
Rev. 0.60, 2008-05
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HYS[64/72]D[64/128]3x0EU–[5/6]–D
Unbuffered DDR SDRAM Modules
TABLE 12
DD Specification for HYS72D[64/128]3x0EU–[5/6]–D
I
Product Type
Unit
Note 1)2)
Organization
512 MB
×72
512 MB
×72
1 GB
×72
1 GB
×72
1 Rank
–5
1 Rank
–6
2 Ranks
–5
2 Ranks
–6
Symbol
Typ.
Max.
Typ.
Max.
Typ.
Max.
Typ.
Max.
3)
IDD0
486
531
9
585
648
41
414
459
9
513
558
41
495
540
18
626
689
83
423
468
18
554
599
83
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
3)4)
5)
IDD1
IDD2P
IDD2F
IDD2Q
IDD3P
IDD3N
IDD4R
IDD4W
IDD5
5)
198
135
72
270
198
126
333
621
621
1314
45
180
126
72
243
180
126
306
576
576
1134
45
396
270
144
468
522
522
1116
27
540
396
252
666
662
662
1355
90
360
252
144
414
450
450
999
27
486
360
252
612
617
617
1175
90
5)
5)
5)
234
513
513
1107
14
207
441
441
990
14
3)4)
3)
5)
5)
IDD6
3)4)
IDD7
1494
1782
1251
1602
1503
1823
1260
1643
1) DRAM component currents only
2) Test condition for maximum values: VDD = 2.7 V, TA = 10 °C
3) The module IDDx values are calculated from the component IDDx data sheet values as: m × IDDx[component] + n × IDD2P[component] with
m and n number of components of rank 1 and 2; n=0 for 1 rank modules
4) DQ I/O (IDDQ) currents are not included into calculations: module IDD values will be measured differently depending on load conditions
5) The module IDDx values are calculated from the component IDDx data sheet values as: (m + n) × IDDx[component]
Rev. 0.60, 2008-05
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Unbuffered DDR SDRAM Modules
3.3
AC Characteristics
This chapter describes the AC characteristics.
TABLE 13
AC Timing - Absolute Specifications for PC3200 and PC2700
Parameter
Symbol –5
–6
Unit Note/ Test
Condition1)
DDR400B
DDR333
Min.
Max.
Min.
Max.
2)3)4)5)
DQ output access time from
CK/CK
tAC
–0.7
+0.7
–0.7
+0.7
ns
2)3)4)5)
CK high-level width
Clock cycle time
tCH
tCK
0.45
0.55
12
0.45
6
0.55
12
tCK
5
ns
ns
ns
tCK
tCK
CL = 3.0 2)3)4)5)
CL = 2.5 2)3)4)5)
CL = 2.0 2)3)4)5)
6
12
6
12
7
12
7.5
0.45
12
2)3)4)5)
CK low-level width
tCL
0.45
0.55
0.55
2)3)4)5)6)
Auto precharge write recovery + tDAL
(tWR/tCK) + (tRP/tCK)
precharge time
2)3)4)5)
DQ and DM input hold time
tDH
0.4
—
—
0.45
1.75
—
—
ns
ns
2)3)4)5)6)
DQ and DM input pulse width
(each input)
tDIPW
1.75
2)3)4)5)
2)3)4)5)
DQS output access time from
CK/CK
tDQSCK
–0.6
0.35
—
+0.6
—
–0.6
0.35
—
+0.6
—
ns
tCK
ns
tCK
DQS input low (high) pulse width tDQSL,H
(write cycle)
DQS-DQ skew (DQS and
associated DQ signals)
Write command to 1st DQS
latching transition
tDQSQ
tDQSS
tDS
+0.40
1.25
+0.45
1.25
TSOPII 2)3)4)5)
2)3)4)5)
0.72
0.75
2)3)4)5)
2)3)4)5)
DQ and DM input setup time
0.4
0.2
—
—
0.45
0.2
—
—
ns
DQS falling edge hold time from tDSH
tCK
CK (write cycle)
2)3)4)5)
DQS falling edge to CK setup
time (write cycle)
tDSS
0.2
—
0.2
—
tCK
2)3)4)5)
Clock Half Period
tHP
tHZ
Min. (tCL, tCH
)
—
Min. (tCL, tCH
)
—
ns
ns
2)3)4)5)7)
Data-out high-impedance time
from CK/CK
+0.7
–0.7
+0.7
Address and control input hold
time
tIH
0.6
0.7
2.2
—
—
—
0.75
0.8
—
—
—
ns
ns
ns
Fast slew rate
3)4)5)6)10)
Slow slew rate
3)4)5)6)10)
2)3)4)5)8)
Control and Addr. input pulse
width (each input)
tIPW
2.2
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Unbuffered DDR SDRAM Modules
Parameter
Symbol –5
DDR400B
–6
Unit Note/ Test
Condition1)
DDR333
Min.
Max.
Min.
Max.
Address and control input setup tIS
time
0.6
—
0.75
—
ns
ns
ns
tCK
Fast slew rate
3)4)5)6)9)
0.7
–0.7
2
—
0.8
–0.7
2
—
Slow slew rate
3)4)5)6)10)
2)3)4)5)7)
2)3)4)5)
2)3)4)5)
Data-out low-impedance time
from CK/CK
tLZ
+0.7
—
+0.7
—
Mode register set command
cycle time
tMRD
DQ/DQS output hold time
Data hold skew factor
tQH
t
HP – tQHS
—
t
HP – tQHS
—
ns
ns
ns
tQHS
tRAP
tRAS
tRC
—
+0.50
—
—
+0.55
—
TSOPII 2)3)4)5)
2)3)4)5)
Active to Autoprecharge delay
Active to Precharge command
tRCD
40
tRCD
2)3)4)5)
2)3)4)5)
70E+3 42
70E+3 ns
Active to Active/Auto-refresh
command period
55
—
60
—
ns
2)3)4)5)
Active to Read or Write delay
tRCD
tREFI
15
—
—
18
—
—
ns
2)3)4)5)10)
Average Periodic Refresh
Interval
7.8
7.8
μs
2)3)4)5)
Auto-refresh to Active/Auto-
refresh command period
tRFC
70
—
72
—
ns
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)
Precharge command period
Read preamble
tRP
15
—
18
—
ns
tCK
tCK
ns
tRPRE
tRPST
tRRD
0.9
0.40
10
1.1
0.60
—
0.9
0.40
12
1.1
0.60
—
Read postamble
Active bank A to Active bank B
command
2)3)4)5)
Write preamble
tWPRE
tWPRES
tWPST
tWR
0.25
0
—
0.25
0
—
tCK
ns
2)3)4)5)11)
2)3)4)5)12)
2)3)4)5)
Write preamble setup time
Write postamble
—
—
0.40
15
0.60
—
0.40
15
0.60
—
tCK
ns
Write recovery time
2)3)4)5)
Internal write to read command tWTR
2
—
1
—
tCK
delay
2)3)4)5)
2)3)4)5)
Exit self-refresh to non-read
command
tXSNR
tXSRD
75
—
—
75
—
—
ns
Exit self-refresh to read
command
200
200
tCK
1) 0 °C ≤ TA ≤ 70 °C; VDDQ = 2.5 V ± 0.2 V, VDD = +2.5 V ± 0.2 V (DDR333); VDDQ = 2.6 V ± 0.1 V, VDD = +2.6 V ± 0.1 V (DDR400)
2) Input slew rate ≥ 1 V/ns for DDR400, DDR333
3) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference level for signals
other than CK/CK, is VREF. CK/CK slew rate are ≥ 1.0 V/ns.
4) Inputs are not recognized as valid until VREF stabilizes.
5) The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (note 3) is VTT
6) For each of the terms, if not already an integer, round to the next highest integer. tCK is equal to the actual system clock cycle time.
7) HZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred to a specific
voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ).
.
t
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Unbuffered DDR SDRAM Modules
8) These parameters guarantee device timing, but they are not necessarily tested on each device.
9) Fast slew rate ≥ 1.0 V/ns, slow slew rate ≥ 0.5 V/ns and < 1 V/ns for command/address and CK & CK slew rate > 1.0 V/ns, measured
between VOH(ac) and VOL(ac)
.
10) A maximum of eight Autorefresh commands can be posted to any given DDR SDRAM device.
11) The specific requirement is that DQS be valid (HIGH, LOW, or some point on a valid transition) on or before this CK edge. A valid transition
is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were previously in progress on the
bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress, DQS could be HIGH, LOW, or transitioning from
HIGH to LOW at this time, depending on tDQSS
.
12) The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but system
performance (bus turnaround) degrades accordingly.
Rev. 0.60, 2008-05
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HYS[64/72]D[64/128]3x0EU–[5/6]–D
Unbuffered DDR SDRAM Modules
4
SPD Codes
This chapter lists all hexadecimal byte values stored in the EEPROM of the products described in this data sheet. SPD stands
for serial presence detect. All values with XX in the table are module specific bytes which are defined during production.
List of SPD Code Tables
•
•
•
Table 14 “HYS[64/72]D[64/128]3x0-5-D” on Page 22
Table 15 “HYS[64/72]D[64/128]3x0-6-D” on Page 26
Table 16 “HYS64D32301EU-[5/6]-D” on Page 30
TABLE 14
HYS[64/72]D[64/128]3x0-5-D
Product Type
Organization
512MB
512MB
1 GByte
1 GByte
×64
×72
×64
×72
1 Rank (×8) 1 Rank (×8) 2 Ranks (×8) 2 Ranks (×8)
Label Code
PC3200U–
30331
PC3200U–
30331
PC3200U–
30331
PC3200U–
30331
JEDEC SPD Revision
Rev. 1.0
HEX
Rev. 1.0
HEX
Rev. 1.0
HEX
Rev. 1.0
HEX
Byte#
Description
0
Programmed SPD Bytes in E2PROM
Total number of Bytes in E2PROM
Memory Type (DDR = 07h)
Number of Row Addresses
Number of Column Addresses
Number of DIMM Ranks
80
08
07
0D
0B
01
40
00
04
50
70
00
82
80
08
07
0D
0B
01
48
00
04
50
70
02
82
80
08
07
0D
0B
02
40
00
04
50
70
00
82
80
08
07
0D
0B
02
48
00
04
50
70
02
82
1
2
3
4
5
6
Data Width (LSB)
7
Data Width (MSB)
8
Interface Voltage Levels
9
tCK @ CLmax (Byte 18) [ns]
10
11
12
tAC SDRAM @ CLmax (Byte 18) [ns]
Error Correction Support
Refresh Rate
Rev. 0.60, 2008-05
22
02142008-4Z51-SEDD
Advance Internet Data Sheet
HYS[64/72]D[64/128]3x0EU–[5/6]–D
Unbuffered DDR SDRAM Modules
Product Type
Organization
512MB
512MB
1 GByte
1 GByte
×64
×72
×64
×72
1 Rank (×8) 1 Rank (×8) 2 Ranks (×8) 2 Ranks (×8)
Label Code
PC3200U–
30331
PC3200U–
30331
PC3200U–
30331
PC3200U–
30331
JEDEC SPD Revision
Rev. 1.0
HEX
Rev. 1.0
HEX
Rev. 1.0
HEX
Rev. 1.0
HEX
Byte#
Description
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
Primary SDRAM Width
Error Checking SDRAM Width
tCCD [cycles]
08
00
01
0E
04
1C
01
02
20
C1
60
70
75
70
3C
28
3C
28
80
60
60
40
40
00
37
41
08
08
01
0E
04
1C
01
02
20
C1
60
70
75
70
3C
28
3C
28
80
60
60
40
40
00
37
41
08
00
01
0E
04
1C
01
02
20
C1
60
70
75
70
3C
28
3C
28
80
60
60
40
40
00
37
41
08
08
01
0E
04
1C
01
02
20
C1
60
70
75
70
3C
28
3C
28
80
60
60
40
40
00
37
41
Burst Length Supported
Number of Banks on SDRAM Device
CAS Latency
CS Latency
Write Latency
DIMM Attributes
Component Attributes
t
t
t
CK @ CLmax -0.5 (Byte 18) [ns]
AC SDRAM @ CLmax -0.5 [ns]
CK @ CLmax -1 (Byte 18) [ns]
tAC SDRAM @ CLmax -1 [ns]
t
t
RPmin [ns]
RRDmin [ns]
tRCDmin [ns]
RASmin [ns]
t
Module Density per Rank
tAS, tCS [ns]
t
t
AH, tCH [ns]
DS [ns]
tDH [ns]
36 - 40 Not used
41
42
t
RCmin [ns]
tRFCmin [ns]
Rev. 0.60, 2008-05
23
02142008-4Z51-SEDD
Advance Internet Data Sheet
HYS[64/72]D[64/128]3x0EU–[5/6]–D
Unbuffered DDR SDRAM Modules
Product Type
Organization
512MB
512MB
1 GByte
1 GByte
×64
×72
×64
×72
1 Rank (×8) 1 Rank (×8) 2 Ranks (×8) 2 Ranks (×8)
Label Code
PC3200U–
30331
PC3200U–
30331
PC3200U–
30331
PC3200U–
30331
JEDEC SPD Revision
Rev. 1.0
HEX
Rev. 1.0
HEX
Rev. 1.0
HEX
Rev. 1.0
HEX
Byte#
Description
43
44
45
46
47
tCKmax [ns]
28
28
50
00
01
00
10
AF
7F
7F
7F
7F
7F
51
00
00
xx
28
28
50
00
01
00
10
C1
7F
7F
7F
7F
7F
51
00
00
xx
28
28
50
00
01
00
10
B0
7F
7F
7F
7F
7F
51
00
00
xx
28
28
50
00
01
00
10
C2
7F
7F
7F
7F
7F
51
00
00
xx
tDQSQmax [ns]
t
QHSmax [ns]
not used
DIMM PCB Height
48 - 61 Not used
SPD Revision
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
Checksum of Byte 0-62
Manufacturer’s JEDEC ID Code (1)
Manufacturer’s JEDEC ID Code (2)
Manufacturer’s JEDEC ID Code (3)
Manufacturer’s JEDEC ID Code (4)
Manufacturer’s JEDEC ID Code (5)
Manufacturer’s JEDEC ID Code (6)
Manufacturer’s JEDEC ID Code (7)
Manufacturer’s JEDEC ID Code (8)
Module Manufacturer Location
Part Number, Char 1
36
34
44
36
34
33
30
30
45
37
32
44
36
34
33
30
30
45
36
34
44
31
32
38
33
32
30
37
32
44
31
32
38
33
32
30
Part Number, Char 2
Part Number, Char 3
Part Number, Char 4
Part Number, Char 5
Part Number, Char 6
Part Number, Char 7
Part Number, Char 8
Part Number, Char 9
Rev. 0.60, 2008-05
24
02142008-4Z51-SEDD
Advance Internet Data Sheet
HYS[64/72]D[64/128]3x0EU–[5/6]–D
Unbuffered DDR SDRAM Modules
Product Type
Organization
512MB
512MB
1 GByte
1 GByte
×64
×72
×64
×72
1 Rank (×8) 1 Rank (×8) 2 Ranks (×8) 2 Ranks (×8)
Label Code
PC3200U–
30331
PC3200U–
30331
PC3200U–
30331
PC3200U–
30331
JEDEC SPD Revision
Rev. 1.0
HEX
Rev. 1.0
HEX
Rev. 1.0
HEX
Rev. 1.0
HEX
Byte#
Description
82
83
84
85
86
87
88
89
90
91
92
93
94
Part Number, Char 10
55
35
44
20
20
20
20
20
20
0x
xx
xx
xx
xx
00
55
35
44
20
20
20
20
20
20
0x
xx
xx
xx
xx
00
45
55
35
44
20
20
20
20
20
0x
xx
xx
xx
xx
00
45
55
35
44
20
20
20
20
20
0x
xx
xx
xx
xx
00
Part Number, Char 11
Part Number, Char 12
Part Number, Char 13
Part Number, Char 14
Part Number, Char 15
Part Number, Char 16
Part Number, Char 17
Part Number, Char 18
Module Revision Code
Test Program Revision Code
Module Manufacturing Date Year
Module Manufacturing Date Week
95 - 98 Module Serial Number
99 - 127 Not used
Rev. 0.60, 2008-05
25
02142008-4Z51-SEDD
Advance Internet Data Sheet
HYS[64/72]D[64/128]3x0EU–[5/6]–D
Unbuffered DDR SDRAM Modules
TABLE 15
HYS[64/72]D[64/128]3x0-6-D
Product Type
Organization
512MB
512MB
1 GByte
1 GByte
×64
×72
×64
×72
1 Rank (×8) 1 Rank (×8) 2 Ranks (×8) 2 Ranks (×8)
Label Code
PC2700U–
25331
PC2700U–
25331
PC2700U–
25331
PC2700U–
25331
JEDEC SPD Revision
Rev. 1.0
HEX
Rev. 1.0
HEX
Rev. 1.0
HEX
Rev. 1.0
HEX
Byte#
Description
0
Programmed SPD Bytes in E2PROM
Total number of Bytes in E2PROM
Memory Type (DDR = 07h)
Number of Row Addresses
Number of Column Addresses
Number of DIMM Ranks
80
08
07
0D
0B
01
40
00
04
60
70
00
82
08
00
01
0E
04
0C
01
02
20
C1
80
08
07
0D
0B
01
48
00
04
60
70
02
82
08
08
01
0E
04
0C
01
02
20
C1
80
08
07
0D
0B
02
40
00
04
60
70
00
82
08
00
01
0E
04
0C
01
02
20
C1
80
08
07
0D
0B
02
48
00
04
60
70
02
82
08
08
01
0E
04
0C
01
02
20
C1
1
2
3
4
5
6
Data Width (LSB)
7
Data Width (MSB)
8
Interface Voltage Levels
9
tCK @ CLmax (Byte 18) [ns]
10
11
12
13
14
15
16
17
18
19
20
21
22
tAC SDRAM @ CLmax (Byte 18) [ns]
Error Correction Support
Refresh Rate
Primary SDRAM Width
Error Checking SDRAM Width
t
CCD [cycles]
Burst Length Supported
Number of Banks on SDRAM Device
CAS Latency
CS Latency
Write Latency
DIMM Attributes
Component Attributes
Rev. 0.60, 2008-05
26
02142008-4Z51-SEDD
Advance Internet Data Sheet
HYS[64/72]D[64/128]3x0EU–[5/6]–D
Unbuffered DDR SDRAM Modules
Product Type
Organization
512MB
512MB
1 GByte
1 GByte
×64
×72
×64
×72
1 Rank (×8) 1 Rank (×8) 2 Ranks (×8) 2 Ranks (×8)
Label Code
PC2700U–
25331
PC2700U–
25331
PC2700U–
25331
PC2700U–
25331
JEDEC SPD Revision
Rev. 1.0
HEX
Rev. 1.0
HEX
Rev. 1.0
HEX
Rev. 1.0
HEX
Byte#
Description
23
24
25
26
27
28
29
30
31
32
33
34
35
tCK @ CLmax -0.5 (Byte 18) [ns]
tAC SDRAM @ CLmax -0.5 [ns]
75
70
00
00
48
30
48
2A
80
75
75
45
45
00
3C
48
30
2D
55
00
01
00
10
53
7F
7F
75
70
00
00
48
30
48
2A
80
75
75
45
45
00
3C
48
30
2D
55
00
01
00
10
65
7F
7F
75
70
00
00
48
30
48
2A
80
75
75
45
45
00
3C
48
30
2D
55
00
01
00
10
54
7F
7F
75
70
00
00
48
30
48
2A
80
75
75
45
45
00
3C
48
30
2D
55
00
01
00
10
66
7F
7F
t
t
CK @ CLmax -1 (Byte 18) [ns]
AC SDRAM @ CLmax -1 [ns]
tRPmin [ns]
t
t
RRDmin [ns]
RCDmin [ns]
tRASmin [ns]
Module Density per Rank
t
AS, tCS [ns]
tAH, tCH [ns]
t
t
DS [ns]
DH [ns]
36 - 40 Not used
41
42
43
44
45
46
47
t
t
RCmin [ns]
RFCmin [ns]
tCKmax [ns]
t
t
DQSQmax [ns]
QHSmax [ns]
not used
DIMM PCB Height
48 - 61 Not used
62
63
64
65
SPD Revision
Checksum of Byte 0-62
Manufacturer’s JEDEC ID Code (1)
Manufacturer’s JEDEC ID Code (2)
Rev. 0.60, 2008-05
27
02142008-4Z51-SEDD
Advance Internet Data Sheet
HYS[64/72]D[64/128]3x0EU–[5/6]–D
Unbuffered DDR SDRAM Modules
Product Type
Organization
512MB
512MB
1 GByte
1 GByte
×64
×72
×64
×72
1 Rank (×8) 1 Rank (×8) 2 Ranks (×8) 2 Ranks (×8)
Label Code
PC2700U–
25331
PC2700U–
25331
PC2700U–
25331
PC2700U–
25331
JEDEC SPD Revision
Rev. 1.0
HEX
Rev. 1.0
HEX
Rev. 1.0
HEX
Rev. 1.0
HEX
Byte#
Description
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
Manufacturer’s JEDEC ID Code (3)
Manufacturer’s JEDEC ID Code (4)
Manufacturer’s JEDEC ID Code (5)
Manufacturer’s JEDEC ID Code (6)
Manufacturer’s JEDEC ID Code (7)
Manufacturer’s JEDEC ID Code (8)
Module Manufacturer Location
Part Number, Char 1
7F
7F
7F
51
00
00
xx
7F
7F
7F
51
00
00
xx
7F
7F
7F
51
00
00
xx
7F
7F
7F
51
00
00
xx
36
34
44
36
34
33
30
30
45
55
36
44
20
20
20
20
20
20
0x
37
32
44
36
34
33
30
30
45
55
36
44
20
20
20
20
20
20
0x
36
34
44
31
32
38
33
32
30
45
55
36
44
20
20
20
20
20
0x
37
32
44
31
32
38
33
32
30
45
55
36
44
20
20
20
20
20
0x
Part Number, Char 2
Part Number, Char 3
Part Number, Char 4
Part Number, Char 5
Part Number, Char 6
Part Number, Char 7
Part Number, Char 8
Part Number, Char 9
Part Number, Char 10
Part Number, Char 11
Part Number, Char 12
Part Number, Char 13
Part Number, Char 14
Part Number, Char 15
Part Number, Char 16
Part Number, Char 17
Part Number, Char 18
Module Revision Code
Rev. 0.60, 2008-05
28
02142008-4Z51-SEDD
Advance Internet Data Sheet
HYS[64/72]D[64/128]3x0EU–[5/6]–D
Unbuffered DDR SDRAM Modules
Product Type
Organization
512MB
512MB
1 GByte
1 GByte
×64
×72
×64
×72
1 Rank (×8) 1 Rank (×8) 2 Ranks (×8) 2 Ranks (×8)
Label Code
PC2700U–
25331
PC2700U–
25331
PC2700U–
25331
PC2700U–
25331
JEDEC SPD Revision
Rev. 1.0
HEX
Rev. 1.0
HEX
Rev. 1.0
HEX
Rev. 1.0
HEX
Byte#
Description
92
93
94
Test Program Revision Code
xx
xx
xx
xx
00
xx
xx
xx
xx
00
xx
xx
xx
xx
00
xx
xx
xx
xx
00
Module Manufacturing Date Year
Module Manufacturing Date Week
95 - 98 Module Serial Number
99 - 127 Not used
Rev. 0.60, 2008-05
29
02142008-4Z51-SEDD
Advance Internet Data Sheet
HYS[64/72]D[64/128]3x0EU–[5/6]–D
Unbuffered DDR SDRAM Modules
TABLE 16
HYS64D32301EU-[5/6]-D
Product Type
Organization
HYS64D32301EU–5–D
HYS64D32301EU–6–D
256MB
256MB
×64
×64
1 Rank (×16)
PC3200U–30331
Rev. 1.0
HEX
1 Rank (×16)
PC2700U–25331
Rev. 1.0
Label Code
JEDEC SPD Revision
Byte#
Description
HEX
0
Programmed SPD Bytes in E2PROM
Total number of Bytes in E2PROM
Memory Type (DDR = 07h)
Number of Row Addresses
Number of Column Addresses
Number of DIMM Ranks
80
08
07
0D
0A
01
40
00
04
50
70
00
82
10
00
01
0E
04
1C
01
02
20
C1
60
70
75
70
3C
28
3C
80
08
07
0D
0A
01
40
00
04
60
70
00
82
10
00
01
0E
04
0C
01
02
20
C1
75
70
00
00
48
30
48
1
2
3
4
5
6
Data Width (LSB)
7
Data Width (MSB)
8
Interface Voltage Levels
9
tCK @ CLmax (Byte 18) [ns]
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
tAC SDRAM @ CLmax (Byte 18) [ns]
Error Correction Support
Refresh Rate
Primary SDRAM Width
Error Checking SDRAM Width
t
CCD [cycles]
Burst Length Supported
Number of Banks on SDRAM Device
CAS Latency
CS Latency
Write Latency
DIMM Attributes
Component Attributes
t
t
CK @ CLmax -0.5 (Byte 18) [ns]
AC SDRAM @ CLmax -0.5 [ns]
tCK @ CLmax -1 (Byte 18) [ns]
t
t
AC SDRAM @ CLmax -1 [ns]
RPmin [ns]
tRRDmin [ns]
RCDmin [ns]
t
Rev. 0.60, 2008-05
30
02142008-4Z51-SEDD
Advance Internet Data Sheet
HYS[64/72]D[64/128]3x0EU–[5/6]–D
Unbuffered DDR SDRAM Modules
Product Type
Organization
HYS64D32301EU–5–D
HYS64D32301EU–6–D
256MB
256MB
×64
×64
1 Rank (×16)
PC3200U–30331
Rev. 1.0
HEX
1 Rank (×16)
PC2700U–25331
Rev. 1.0
Label Code
JEDEC SPD Revision
Byte#
Description
HEX
30
31
32
33
34
35
tRASmin [ns]
28
40
60
60
40
40
00
37
41
28
28
50
00
01
00
10
76
7F
7F
7F
7F
7F
51
00
00
xx
2A
40
75
75
45
45
00
3C
48
30
2D
55
00
01
00
10
1A
7F
7F
7F
7F
7F
51
00
00
xx
Module Density per Rank
tAS, tCS [ns]
t
AH, tCH [ns]
tDS [ns]
DH [ns]
t
36 - 40 Not used
41
42
43
44
45
46
47
tRCmin [ns]
t
t
RFCmin [ns]
CKmax [ns]
tDQSQmax [ns]
QHSmax [ns]
t
not used
DIMM PCB Height
48 - 61 Not used
SPD Revision
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
Checksum of Byte 0-62
Manufacturer’s JEDEC ID Code (1)
Manufacturer’s JEDEC ID Code (2)
Manufacturer’s JEDEC ID Code (3)
Manufacturer’s JEDEC ID Code (4)
Manufacturer’s JEDEC ID Code (5)
Manufacturer’s JEDEC ID Code (6)
Manufacturer’s JEDEC ID Code (7)
Manufacturer’s JEDEC ID Code (8)
Module Manufacturer Location
Part Number, Char 1
36
34
44
33
32
33
30
36
34
44
33
32
33
30
Part Number, Char 2
Part Number, Char 3
Part Number, Char 4
Part Number, Char 5
Part Number, Char 6
Part Number, Char 7
Rev. 0.60, 2008-05
31
02142008-4Z51-SEDD
Advance Internet Data Sheet
HYS[64/72]D[64/128]3x0EU–[5/6]–D
Unbuffered DDR SDRAM Modules
Product Type
Organization
HYS64D32301EU–5–D
HYS64D32301EU–6–D
256MB
256MB
×64
×64
1 Rank (×16)
PC3200U–30331
Rev. 1.0
HEX
1 Rank (×16)
PC2700U–25331
Rev. 1.0
Label Code
JEDEC SPD Revision
Byte#
Description
HEX
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
Part Number, Char 8
31
45
55
35
44
20
20
20
20
20
20
0x
xx
xx
xx
xx
00
31
45
55
36
44
20
20
20
20
20
20
0x
xx
xx
xx
xx
00
Part Number, Char 9
Part Number, Char 10
Part Number, Char 11
Part Number, Char 12
Part Number, Char 13
Part Number, Char 14
Part Number, Char 15
Part Number, Char 16
Part Number, Char 17
Part Number, Char 18
Module Revision Code
Test Program Revision Code
Module Manufacturing Date Year
Module Manufacturing Date Week
95 - 98 Module Serial Number
99 - 127 Not used
Rev. 0.60, 2008-05
32
02142008-4Z51-SEDD
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Advance Internet Data Sheet
HYS[64/72]D[64/128]3x0EU–[5/6]–D
Unbuffered DDR SDRAM Modules
5
Package Outlines
This chapter contains the package outlines of the products.
FIGURE 2
Package Outline UDIMM Raw Card A (L-DIM-184-30)
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1. Drawing according to ISO 8015
2. Dimensions in mm
3. General tolerances +/- 0.15
Rev. 0.60, 2008-05
33
02142008-4Z51-SEDD
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Advance Internet Data Sheet
HYS[64/72]D[64/128]3x0EU–[5/6]–D
Unbuffered DDR SDRAM Modules
FIGURE 3
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Advance Internet Data Sheet
HYS[64/72]D[64/128]3x0EU–[5/6]–D
Unbuffered DDR SDRAM Modules
FIGURE 4
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35
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Advance Internet Data Sheet
HYS[64/72]D[64/128]3x0EU–[5/6]–D
Unbuffered DDR SDRAM Modules
FIGURE 5
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Rev. 0.60, 2008-05
36
02142008-4Z51-SEDD
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Advance Internet Data Sheet
HYS[64/72]D[64/128]3x0EU–[5/6]–D
Unbuffered DDR SDRAM Modules
FIGURE 6
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Rev. 0.60, 2008-05
37
02142008-4Z51-SEDD
Advance Internet Data Sheet
HYS[64/72]D[64/128]3x0EU–[5/6]–D
Unbuffered DDR SDRAM Modules
Table of Contents
1
1.1
1.2
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2
Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.1
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Current Conditions and Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.1
3.2
3.3
4
5
SPD Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Rev. 0.60, 2008-05
38
02142008-4Z51-SEDD
Advance Internet Data Sheet
Edition 2008-05
Published by Qimonda AG
Gustav-Heinemann-Ring 212
D-81739 München, Germany
© Qimonda AG 2008.
All Rights Reserved.
Legal Disclaimer
THE INFORMATION GIVEN IN THIS INTERNET DATA SHEET SHALL IN NO EVENT BE REGARDED AS A GUARANTEE
OF CONDITIONS OR CHARACTERISTICS. WITH RESPECT TO ANY EXAMPLES OR HINTS GIVEN HEREIN, ANY
TYPICAL VALUES STATED HEREIN AND/OR ANY INFORMATION REGARDING THE APPLICATION OF THE DEVICE,
QIMONDA HEREBY DISCLAIMS ANY AND ALL WARRANTIES AND LIABILITIES OF ANY KIND, INCLUDING WITHOUT
LIMITATION WARRANTIES OF NON-INFRINGEMENT OF INTELLECTUAL PROPERTY RIGHTS OF ANY THIRD PARTY.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest Qimonda Office.
Warnings
Due to technical requirements components may contain dangerous substances. For information on the types in question please
contact your nearest Qimonda Office.
Qimonda Components may only be used in life-support devices or systems with the express written approval of Qimonda, if a
failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect
the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human
body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health
of the user or other persons may be endangered.
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