HYS72D64300GU-6-B [INFINEON]
184-Pin Unbuffered Dual-In-Line Memory Modules; 184针无缓冲双列直插式内存模块
| 型号： | HYS72D64300GU-6-B |
| 厂家： | 
Infineon |
| 描述： | 184-Pin Unbuffered Dual-In-Line Memory Modules |
| 文件： | 总40页 (文件大小：1326K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Data Sheet, Rev. 1.0, May. 2004
HYS64D64300[G/H]U–[5/6]–B
HYS72D64300[G/H]U–[5/6]–B
HYS64D128320[G/H]U–[5/6]–B
HYS72D128320[G/H]U–[5/6]–B
184-Pin Unbuffered Dual-In-Line Memory Modules
UDIMM
DDR SDRAM
Memory Products
N e v e r s t o p t h i n k i n g .
Edition 2004-05
Published by Infineon Technologies AG,
St.-Martin-Strasse 53,
81669 München, Germany
© Infineon Technologies AG 2004.
All Rights Reserved.
Attention please!
The information herein is given to describe certain components and shall not be considered as a guarantee of
characteristics.
Terms of delivery and rights to technical change reserved.
We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding
circuits, descriptions and charts stated herein.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest
Infineon Technologies Office (www.infineon.com).
Warnings
Due to technical requirements components may contain dangerous substances. For information on the types in
question please contact your nearest Infineon Technologies Office.
Infineon Technologies Components may only be used in life-support devices or systems with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
Data Sheet, Rev. 1.0, May. 2004
HYS64D64300[G/H]U–[5/6]–B
HYS72D64300[G/H]U–[5/6]–B
HYS64D128320[G/H]U–[5/6]–B
HYS72D128320[G/H]U–[5/6]–B
184-Pin Unbuffered Dual-In-Line Memory Modules
UDIMM
DDR SDRAM
Memory Products
N e v e r s t o p t h i n k i n g .
HYS64D64300[G/H]U–[5/6]–B, HYS72D64300[G/H]U–[5/6]–B, HYS64D128320[G/H]U–[5/6]–B
Revision History:
Rev. 1.0
2004-05
Previous Version:
Rev. 0.5
Page
Subjects (major changes since last revision)
7
Added Non-Green Modules DDR400 & DDR333 and removed DDR266
editorial changes
8,12ff
22,23
24,27,30,33
Updated IDD currents to final
Update SPD Codes
We Listen to Your Comments
Any information within this document that you feel is wrong, unclear or missing at all?
Your feedback will help us to continuously improve the quality of this document.
Please send your proposal (including a reference to this document) to:
techdoc.mp@infineon.com
Template: mp_a4_v2.0_2003-06-06.fm
HYS[64/72]D[64300/128320][G/H]U–[5/6]–B
Unbuffered DDR SDRAM Modules
Table of Contents
1
1.1
1.2
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3
3.1
3.2
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Current Conditions and Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4
5
SPD Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Data Sheet
5
Rev. 1.0, 2004-05
184-Pin Unbuffered Dual-In-Line Memory Modules
UDIMM
HYS64D64300[G/H]U–[5/6]–B
HYS72D64300[G/H]U–[5/6]–B
HYS64D128320[G/H]U–[5/6]–B
HYS72D128320[G/H]U–[5/6]–B
1
Overview
1.1
Features
•
184-Pin Unbuffered Dual-In-Line Memory Modules (ECC and non-parity) for PC and Workstation main
memory applications
•
•
•
•
•
•
•
•
•
•
•
•
One rank 64M x 64, 64M ×72 and two ranks 128M × 64, 128M ×72 organization
JEDEC standard Double Data Rate Synchronous DRAMs (DDR SDRAM) Single +2.5V (±0.2V) power supply
Built with 512 Mbit DDR SDRAM in P-TSOPII-66-1 package
Programmable CAS Latency, Burst Length, and Wrap Sequence (Sequential & Interleave)
Auto Refresh (CBR) and Self Refresh
All inputs and outputs SSTL_2 compatible
Serial Presence Detect with E2PROM
JEDEC standard MO-206 form factor: 133.35 mm × 31.75 mm × 4.00 mm max.
Jedec standard reference layout
Gold plated contacts
DDR400 speed grade supported
Lead-free
Table 1
Performance
Part Number Speed Code
–5
–6
Unit
—
Speed Grade
Component
Module
@CL3
DDR400B
PC3200–3033
200
DDR333B
PC2700–2533
166
—
max. Clock Frequency
fCK3
MHz
MHz
MHz
@CL2.5
@CL2
fCK2.5
fCK2
166
166
133
133
1.2
Description
The HYS64D64300[G/H]U–[5/6]–B, HYS72D64300[G/H]U–[5/6]–B, HYS64D128320[G/H]U–[5/6]–B, and
HYS72D128320[G/H]U–[5/6]–B are industry standard 184-Pin Unbuffered Dual-In-Line Memory Modules
(UDIMM) organized as 64M ×64, 128M ×64 for non-parity and 64M ×72,128M ×72 for ECC main memory
applications. The memory array is designed with 512Mbit Double Data Rate Synchronous DRAMs. A variety of
decoupling capacitors are mounted on the printed circuit board. The DIMMs feature serial presence detect (SPD)
based on a serial E2PROM device using the 2-pin I2C protocol. The first 128 bytes are programmed with
configuration data and the second 128 bytes are available to the customer
Data Sheet
6
Rev. 1.0, 2004-05
HYS[64/72]D[64300/128320][G/H]U–[5/6]–B
Unbuffered DDR SDRAM Modules
Overview
Table 2
Type
Ordering Information
Compliance Code
Description
SDRAM Technology
PC3200 (CL=3.0)
HYS64D64300GU–5–B
HYS72D64300GU–5–B
PC3200U–30330–A0 one rank 512 MB DIMM
512 Mbit (×8)
PC3200U–30330–A0 one rank 512 MB ECC-DIMM 512 Mbit (×8)
HYS64D128320GU–5–B PC3200U–30330–B0 two ranks 1 GB DIMM
HYS72D128320GU–5–B PC3200U–30330–B0 two ranks 1 GB ECC-DIMM
512 Mbit (×8)
512 Mbit (×8)
PC2700 (CL=2.5)
HYS64D64300GU–6–B
HYS72D64300GU–6–B
PC2700U–25330–A0 one rank 512 MB DIMM
512 Mbit (×8)
PC2700U–25330–A0 one rank 512 MB ECC-DIMM 512 Mbit (×8)
HYS64D128320GU–6–B PC2700U–25330–B0 two ranks 1 GB DIMM
HYS72D128320GU–6–B PC2700U–25330–B0 two ranks 1 GB ECC-DIMM
512 Mbit (×8)
512 Mbit (×8)
PC3200 (CL=3.0)
HYS64D64300HU–5–B
HYS72D64300HU–5–B
PC3200U–30330–A0 one rank 512 MB DIMM
512 Mbit (×8)
PC3200U–30330–A0 one rank 512 MB ECC-DIMM 512 Mbit (×8)
HYS64D128320HU–5–B PC3200U–30330–B0 two ranks 1 GB DIMM
HYS72D128320HU–5–B PC3200U–30330–B0 two ranks 1 GB ECC-DIMM
512 Mbit (×8)
512 Mbit (×8)
PC2700 (CL=2.5)
HYS64D64300HU–6–B
HYS72D64300HU–6–B
PC2700U–25330–A0 one rank 512 MB DIMM
512 Mbit (×8)
PC2700U–25330–A0 one rank 512 MB ECC-DIMM 512 Mbit (×8)
HYS64D128320HU–6–B PC2700U–25330–B0 two ranks 1 GB DIMM
HYS72D128320HU–6–B PC2700U–25330–B0 two ranks 1 GB ECC-DIMM
512 Mbit (×8)
512 Mbit (×8)
Note:All part numbers end with a place code designating the silicon-die revision. Reference information available
on request. Example: HYS72D64300HU-6-B, indicating rev. B dies are used for SDRAM components. The
Compliance Code is printed on the module labels describing the speed sort (for example “PC2700”), the
latencies and SPD code definition (for example “20330” means CAS latency of 2.0 clocks, RCD1) latency of
3 clocks, Row Precharge latency of 3 clocks, and JEDEC SPD code definiton version 0), and the Raw Card
used for this module.
1) RCD: Row-Column-Delay
Data Sheet
7
Rev. 1.0, 2004-05
HYS[64/72]D[64300/128320][G/H]U–[5/6]–B
Unbuffered DDR SDRAM Modules
Pin Configuration
2
Pin Configuration
The pin configuration of the Unbuffered DDR SDRAM Table 3
DIMM is listed by function in Table 3 (184 pins). The
Pin Configuration of UDIMM (cont’d)
Pin# Name Pin Buffer Function
abbreviations used in columns Pin and Buffer Type are
explained in Table 4 and Table 5 respectively. The pin
numbering is depicted in Figure 1.
Type Type
122 A8
27 A9
I
I
I
I
I
I
SSTL Address Bus 11:0
SSTL
141 A10
AP
SSTL
Table 3
Pin Configuration of UDIMM
SSTL
Pin# Name Pin Buffer Function
Type Type
118 A11
115 A12
SSTL
Clock Signals
SSTL Address Signal 12
137 CK0
NC
I
SSTL Clock Signals 2:0
Note:Module based on
256 Mbit or larger
dies
Note: For clock net
loading see block
diagram, CK0 is
NC on 1R ×16
NC
–
16
76
CK1
CK2
I
I
SSTL
SSTL
NC
NC
I
–
Note:128 Mbit based
module
138 CK0
NC
I
SSTL Complement Clock
167 A13
SSTL Address Signal 13
Signals 2:0
NC
–
Note:1 Gbit
module
based
Note: For clock net
17
75
CK1
CK2
I
I
SSTL
loading see block
diagram, CK0 is
NC
NC
–
Note:Module based on
SSTL
512 Mbit
or
NC on 1R ×16
SSTL Clock Enable Rank 0
SSTL Clock Enable Rank 1
Note: 2-rank module
smaller dies
21
CKE0
I
I
Data Signals
111 CKE1
2
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
SSTL Data Bus 63:0
SSTL
4
NC
NC
–
Note: 1-rank module
6
SSTL
Control Signals
8
SSTL
157 S0
158 S1
I
I
SSTL Chip Select Rank 0
SSTL Chip Select Rank 1
Note: 2-rank module
94
95
98
99
12
13
19
20
SSTL
SSTL
SSTL
NC
NC
–
Note: 1-rank module
SSTL
154 RAS
I
I
SSTL Row Address Strobe
SSTL
65
CAS
SSTL Column Address
SSTL
Strobe
DQ10 I/O
DQ11 I/O
SSTL
63
WE
I
SSTL Write Enable
SSTL
Address Signals
105 DQ12 I/O
106 DQ13 I/O
109 DQ14 I/O
110 DQ15 I/O
SSTL
59
52
48
43
41
BA0
BA1
A0
I
I
I
I
I
I
I
I
I
I
SSTL Bank Address Bus
SSTL
2:0
SSTL
SSTL
SSTL Address Bus 11:0
SSTL
A1
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
23
24
28
31
DQ16 I/O
DQ17 I/O
DQ18 I/O
DQ19 I/O
SSTL
A2
SSTL
130 A3
SSTL
37
32
A4
A5
SSTL
114 DQ20 I/O
117 DQ21 I/O
SSTL
125 A6
29 A7
SSTL
Data Sheet
8
Rev. 1.0, 2004-05
HYS[64/72]D[64300/128320][G/H]U–[5/6]–B
Unbuffered DDR SDRAM Modules
Pin Configuration
Table 3
Pin Configuration of UDIMM (cont’d)
Table 3
Pin Configuration of UDIMM (cont’d)
Pin# Name Pin Buffer Function
Type Type
Pin# Name Pin Buffer Function
Type Type
121 DQ22 I/O
123 DQ23 I/O
SSTL Data Bus 63:0
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
178 DQ62 I/O
179 DQ63 I/O
SSTL Data Bus 63:0
SSTL
33
35
39
40
DQ24 I/O
DQ25 I/O
DQ26 I/O
DQ27 I/O
44
45
49
51
CB0
I/O
SSTL Check Bit 0
Note:ECC type module
Note:Non-ECC module
SSTL Check Bit 1
Note:ECC type module
Note:Non-ECC module
SSTL Check Bit 2
Note:ECC type module
Note:Non-ECC module
SSTL Check Bit 3
Note:ECC type module
Note:Non-ECC module
SSTL Check Bit 4
Note:ECC type module
Note:Non-ECC module
SSTL Check Bit 5
Note:ECC type module
Note:Non-ECC module
SSTL Check Bit 6
Note:ECC type module
Note:Non-ECC module
SSTL Check Bit 7
Note:ECC type module
Note:Non-ECC module
SSTL Data Strobe Bus 7:0
NC
NC
I/O
–
CB1
126 DQ28 I/O
127 DQ29 I/O
131 DQ30 I/O
133 DQ31 I/O
NC
NC
I/O
–
CB2
NC
NC
I/O
–
53
55
57
60
DQ32 I/O
DQ33 I/O
DQ34 I/O
DQ35 I/O
CB3
NC
NC
I/O
–
134 CB4
146 DQ36 I/O
147 DQ37 I/O
150 DQ38 I/O
151 DQ39 I/O
NC
NC
I/O
–
135 CB5
61
64
68
69
DQ40 I/O
DQ41 I/O
DQ42 I/O
DQ43 I/O
NC
NC
I/O
–
142 CB6
NC
NC
I/O
–
153 DQ44 I/O
155 DQ45 I/O
161 DQ46 I/O
162 DQ47 I/O
144 CB7
NC
NC
–
5
DQS0 I/O
DQS1 I/O
DQS2 I/O
DQS3 I/O
DQS4 I/O
DQS5 I/O
DQS6 I/O
DQS7 I/O
DQS8 I/O
72
73
79
80
DQ48 I/O
DQ49 I/O
DQ50 I/O
DQ51 I/O
Note:See
diagram
block
for
14
25
36
56
67
78
86
47
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
corresponding
DQ signals
165 DQ52 I/O
166 DQ53 I/O
170 DQ54 I/O
171 DQ55 I/O
SSTL Data Strobe 8
Note:ECC type module
83
84
87
88
DQ56 I/O
DQ57 I/O
DQ58 I/O
DQ59 I/O
NC
NC
–
Note:Non-ECC module
174 DQ60 I/O
175 DQ61 I/O
Data Sheet
9
Rev. 1.0, 2004-05
HYS[64/72]D[64300/128320][G/H]U–[5/6]–B
Unbuffered DDR SDRAM Modules
Pin Configuration
Table 3
Pin Configuration of UDIMM (cont’d)
Table 3
Pin Configuration of UDIMM (cont’d)
Pin# Name Pin Buffer Function
Type Type
Pin# Name Pin Buffer Function
Type Type
97
DM0
I
I
I
I
I
I
I
I
I
SSTL Data Mask Bus 7:0
3,
11,
18,
26,
34,
42,
50,
58,
66,
74,
81,
89,
VSS
GND –
Ground Plane
107 DM1
119 DM2
129 DM3
149 DM4
159 DM5
169 DM6
177 DM7
140 DM8
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL Data Mask 8
Note: ECC type module
93,
NC
NC
–
Note: Non-ECC module
100,
116,
124,
132,
139,
145,
152,
160,
176
EEPROM
92
91
SCL
SDA
I
CMOS Serial Bus Clock
OD Serial Bus Data
I/O
181 SA0
182 SA1
183 SA2
I
I
I
CMOS Slave Address Select
Bus 2:0
CMOS
CMOS
Power Supplies
AI
184 VDDSPD PWR –
Other Pins
1
VREF
–
I/O Reference Voltage
82
VDDID
O
OD
V
DD Identification
Note:Pin in tristate,
indicating VDD
and VDDQ nets
EEPROM Power
Supply
15, VDDQ
22,
PWR –
I/O Driver Power
Supply
connected
PCB
on
30,
54,
62,
77,
96,
9,
10,
71,
90,
NC
NC
–
Not connected
Pins not connected on
Infineon UDIMMs
104,
112,
128,
136,
143,
156,
164,
172,
180
101,
102,
103,
113,
163,
173
7,
VDD
PWR –
Power Supply
38,
46,
70,
85,
108,
120,
148,
168
Data Sheet
10
Rev. 1.0, 2004-05
HYS[64/72]D[64300/128320][G/H]U–[5/6]–B
Unbuffered DDR SDRAM Modules
Pin Configuration
Table 4
Abbreviations for Pin Type
Table 5
Abbreviations for Buffer Type
Abbreviation Description
Abbreviation Description
I
Standard input-only pin. Digital levels.
SSTL
Serial Stub Terminated Logic (SSTL2)
O
Output. Digital levels.
I/O is a bidirectional input/output signal.
Input. Analog levels.
Power
LV-CMOS
CMOS
OD
Low Voltage CMOS
CMOS Levels
I/O
AI
Open Drain. The corresponding pin has 2
operational states, active low and tristate,
and allows multiple devices to share as a
wire-OR.
PWR
GND
NC
Ground
Not Connected
VREF - Pin 001
DQS0 - Pin 005
NC - Pin 009
DQ09 - Pin 013
CK1 - Pin 017
CKE0 - Pin 021
DQS2 - Pin 025
A7 - Pin 029
DQ24 - Pin 033
A04 - Pin 037
Pin 002 - DQ00
Pin 004 - DQ01
Pin 006 - DQ02
Pin 008 - DQ03
Pin 010 - NC
V
V
SS - Pin 003
DD - Pin 007
V
SS - Pin 011
Pin 012 - DQ08
Pin 014 - DQS1
Pin 016 - CK1
V
DDQ - Pin 015
DQ10 - Pin 019
DQ16 - Pin 023
A9 - Pin 027
Pin 018 - VSS
Pin 020 - DQ11
Pin 022 - VDDQ
Pin 024 - DQ17
Pin 026 - VSS
Pin 028 - DQ18
Pin 030 - VDDQ
DQ19 - Pin 031
DQ25 - Pin 035
DQ26 - Pin 039
Pin 032 - A5
VSS
VDD
Pin 034 -
Pin 038 -
Pin 036 - DQS3
Pin 040 - DQ27
A2 - Pin 041
CB01/NC - Pin 045
CB02/NC - Pin 049
DQ32 - Pin 053
DQ34 - Pin 057
DQ40 - Pin 061
CAS - Pin 065
Pin 042 - VSS
VDD
A1 - Pin 043
DQS8/NC - Pin 047
CB03/NC - Pin 051
DQ33 - Pin 055
BA0 - Pin 059
Pin 044 - CB00/NC
Pin 048 - A0
Pin 046 -
Pin 050 - VSS
Pin 054 - VDDQ
Pin 058 - VSS
Pin 062 - VDDQ
Pin 066 - VSS
VDD
Pin 070 -
Pin 074 - VSS
Pin 078 - DQS6
VDDID
Pin 082 -
Pin 086 - DQS7
Pin 090 - NC
Pin 094 - DQ04
Pin 098 - DQ06
Pin 102 - NC
Pin 106 - DQ13
Pin 110 - DQ15
Pin 114 - DQ20
Pin 118 - A11
Pin 122 - A8
Pin 126 - DQ28
Pin 130 - A3
Pin 134 - CB4/NC
Pin 138 - CK0/NC
Pin 142 - CB06/NC
Pin 146 - DQ36
Pin 150 - DQ38
Pin 154 - RAS
Pin 158 - S1 /NC
Pin 162 - DQ47
Pin 166 - DQ53
Pin 170 - DQ54
Pin 174 - DQ60
Pin 178 - DQ62
Pin 182 - SA1
Pin 052 - BA1
Pin 056 - DQS4
Pin 060 - DQ35
Pin 064 - DQ41
Pin 068 - DQ42
Pin 072 - DQ48
Pin 076 - CK2
Pin 080 - DQ51
Pin 084 - DQ57
Pin 088 - DQ59
Pin 092 - SCL
WE - Pin 063
DQS5 - Pin 067
NC - Pin 071
DQ43 - Pin 069
DQ49 - Pin 073
VDDQ - Pin 077
CK2 - Pin 075
DQ50 - Pin 079
DQ56 - Pin 083
DQ58 - Pin 087
SDA - Pin 091
DQ05 - Pin 095
DQ07 - Pin 099
NC - Pin 103
V
SS - Pin 081
V
DD - Pin 085
V
V
SS - Pin 089
SS - Pin 093
VDDQ
VSS
VDDQ
VDD
VDDQ
VSS
VDD
VSS
VDDQ
VSS
Pin 096 -
Pin 100 -
Pin 104 -
Pin 108 -
Pin 112 -
Pin 116 -
Pin 120 -
Pin 124 -
Pin 128 -
Pin 132 -
Pin 136 -
DM0 - Pin 097
NC - Pin 101
DQ12 - Pin 105
DQ14 - Pin 109
NC - Pin 113
DQ21 - Pin 117
DQ22 - Pin 121
A6 - Pin 125
DM1 - Pin 107
CKE1/NC - Pin 111
A12/NC - Pin 115
DM2 - Pin 119
DQ23 - Pin 123
DQ29 - Pin 127
DQ30 - Pin 131
CB5/NC - Pin 135
DM3 - Pin 129
DQ31 - Pin 133
CK0/NC - Pin 137
A10/AP - Pin 141
VDDQ
V
SS - Pin 139
Pin 140 - DM8/NC
Pin 144 - CB7/NC
V
DDQ - Pin 143
DQ37 - Pin 147
DQ39 - Pin 151
DQ45 - Pin 155
DM5 - Pin 159
NC - Pin 163
V
SS - Pin 145
VDD
VSS
VDDQ
VSS
VDDQ
VDD
VDDQ
VSS
VDDQ
Pin 148 -
Pin 152 -
Pin 156 -
Pin 160 -
Pin 164 -
Pin 168 -
Pin 172 -
Pin 176 -
Pin 180 -
DM4 - Pin 149
DQ44 - Pin 153
S0 - Pin 157
DQ46 - Pin 161
DQ52 - Pin 165
DM6 - Pin 169
NC - Pin 173
A13/NC - Pin 167
DQ55 - Pin 171
DQ61 - Pin 175
DQ63 - Pin 179
SA2 - Pin 183
DM7 - Pin 177
SA0 - Pin 181
Pin 184 - VDDSPD
MPPD0030
Figure 1
Pin Configuration 184-Pin, UDIMM
Data Sheet
11
Rev. 1.0, 2004-05
HYS[64/72]D[64300/128320][G/H]U–[5/6]–B
Unbuffered DDR SDRAM Modules
Pin Configuration
Table 6
Address Format
Density Organization Memory SDRAMs # of
# of row/bank/ Refresh Period Interval
Ranks
SDRAMs columns bits
512 MB
512 MB
1 GB
64M ×64
64M ×72
128M ×64
128M ×72
1
1
2
2
64M ×8
64M ×8
64M ×8
64M ×8
8
13/2/11
13/2/11
13/2/12
13/2/12
8K
8K
8K
8K
64 ms 7.8 µs
64 ms 7.8 µs
64 ms 7.8 µs
64 ms 7.8 µs
8
16
18
1 GB
VDDSPD
V
V
V
V
DD: SPD EEPROM E0
BA0 - BA1: SDRAMs D0 - D7
A0 - An: SDRAMs D0 - D7
RAS: SDRAMs D0 - D7
CAS: SDRAMs D0 - D7
WE: SDRAMs D0 - D7
BA0 - BA1
V
DD/VDDQ
DD/VDDQ: SDRAMs D0 - D7
REF: SDRAMs D0 - D7
SS: SDRAMs D0 - D7
A0 - An
RAS
VREF
VSS
CAS
WE
VDDID
CKE: SDRAMs D0 - D7
CKE0
Strap: see Note 1
S0
D3
D6
D0
DM0
DQS0
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DM CS
DQS
I/O 0
DM3
DQS3
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DM CS
DQS
I/O 0
DM6
DQS6
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DM CS
DQS
I/O 0
I/O 1
I/O 1
I/O 1
I/O 2
I/O 2
I/O 2
I/O 3
I/O 3
I/O 3
I/O 4
I/O 4
I/O 4
I/O 5
I/O 5
I/O 5
I/O 6
I/O 6
I/O 6
I/O 7
I/O 7
I/O 7
D1
D2
D4
D5
D7
DM1
DQS1
DQ8
DM CS
DQS
I/O 0
DM4
DQS4
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DM CS
DQS
I/O 0
DM7
DQS7
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DM CS
DQS
I/O 0
DQ9
I/O 1
I/O 1
I/O 1
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
I/O 2
I/O 2
I/O 2
I/O 3
I/O 3
I/O 3
I/O 4
I/O 4
I/O 4
I/O 5
I/O 5
I/O 5
I/O 6
I/O 6
I/O 6
I/O 7
I/O 7
I/O 7
DM2
DQS2
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DM CS
DQS
I/O 0
DM5
DQS5
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DM CS
DQS
I/O 0
I/O 1
I/O 1
E0
I/O 2
I/O 2
SCL
SAD
SA0
SA1
SA2
VSS
SCL
SAD
A0
I/O 3
I/O 3
I/O 4
I/O 4
I/O 5
I/O 5
A1
I/O 6
I/O 6
A2
I/O 7
I/O 7
WP
MPBD1011
Figure 2
Note:
Block Diagram UDIMM Raw Card A ×64, 1 Rank, ×8
1. VDD = VDDQ, therefore VDDID strap open
2. DQ, DQS, DM resistors are 22 Ω ±5 %
3. BAn, An, RAS, CAS, WE resistors are 5.1 Ω ±5 %
Table 7
Clock Signal Loads
Number of SDRAMs
2 SDRAMs
Clock Input
CK0, CK0
CK1, CK1
CK2, CK2
Note
—
3 SDRAMs
—
3 SDRAMs
—
Data Sheet
12
Rev. 1.0, 2004-05
HYS[64/72]D[64300/128320][G/H]U–[5/6]–B
Unbuffered DDR SDRAM Modules
Pin Configuration
VDDSPD
V
V
V
V
DD: SPD EEPROM E0
DD/VDDQ: SDRAMs D0 - D15
REF: SDRAMs D0 - D15
SS: SDRAMs D0 - D15
BA0 - BA1: SDRAMs D0 - D15
A0 - An: SDRAMs D0 - D15
RAS: SDRAMs D0 - D15
CAS: SDRAMs D0 - D15
WE: SDRAMs D0 - D15
CKE: SDRAMs D0 - D7
CKE:SDRAMs D8 - D15
BA0 - BA1
A0 - An
RAS
V
DD/VDDQ
VREF
CAS
VSS
WE
VDDID
CKE0
CKE1
Strap: see Note 1
S0
S1
D12
D13
D14
D15
D4
D5
D6
D7
D0
D1
D2
D3
D8
DM0
DQS0
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DM CS
DQS
I/O 0
DM CS
DQS
I/O 0
DM4
DM CS
DM CS
DQS
I/O 0
DQS4
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 1
I/O 1
I/O 1
I/O 2
I/O 2
I/O 2
I/O 3
I/O 3
I/O 3
I/O 4
I/O 4
I/O 4
I/O 5
I/O 5
I/O 5
I/O 6
I/O 6
I/O 6
I/O 7
I/O 7
I/O 7
D9
DM1
DQS1
DQ8
DM CS
DQS
I/O 0
DM CS
DQS
I/O 0
DM5
DQS5
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DM CS
DQS
I/O 0
DM CS
DQS
I/O 0
DQ9
I/O 1
I/O 1
I/O 1
I/O 1
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
I/O 2
I/O 2
I/O 2
I/O 2
I/O 3
I/O 3
I/O 3
I/O 3
I/O 4
I/O 4
I/O 4
I/O 4
I/O 5
I/O 5
I/O 5
I/O 5
I/O 6
I/O 6
I/O 6
I/O 6
I/O 7
I/O 7
I/O 7
I/O 7
D10
D11
DM2
DQS2
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DM CS
DQS
I/O 0
DM CS
DQS
I/O 0
DM6
DQS6
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DM CS
DQS
I/O 0
DM CS
DQS
I/O 0
I/O 1
I/O 1
I/O 1
I/O 1
I/O 2
I/O 2
I/O 2
I/O 2
I/O 3
I/O 3
I/O 3
I/O 3
I/O 4
I/O 4
I/O 4
I/O 4
I/O 5
I/O 5
I/O 5
I/O 5
I/O 6
I/O 6
I/O 6
I/O 6
I/O 7
I/O 7
I/O 7
I/O 7
DM3
DQS3
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DM CS
DQS
I/O 0
DM CS
DQS
I/O 0
DM7
DQS7
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DM CS
DQS
I/O 0
DM CS
DQS
I/O 0
I/O 1
I/O 1
I/O 1
I/O 1
I/O 2
I/O 2
I/O 2
I/O 2
I/O 3
I/O 3
I/O 3
I/O 3
I/O 4
I/O 4
I/O 4
I/O 4
I/O 5
I/O 5
I/O 5
I/O 5
I/O 6
I/O 6
I/O 6
I/O 6
I/O 7
I/O 7
I/O 7
I/O 7
E0
SCL
SAD
SA0
SA1
SA2
VSS
SCL
SAD
A0
A1
A2
WP
MPBD1031
Figure 3
Block Diagram UDIMM Raw Card B (x64, 2 Ranks, x8)
Note:
Table 8
Clock Signal Loads
Number of SDRAMs
4 SDRAMs
1. VDD = VDDQ, therefore VDDID strap open
2. DQ, DQS, DM resistors are 22 Ω ±5 %
3. BAn, An, RAS, CAS, WE resistors are 3 Ω ±5 %
Clock Input
CK0, CK0
CK1, CK1
CK2, CK2
Note
—
6 SDRAMs
—
6 SDRAMs
—
Data Sheet
13
Rev. 1.0, 2004-05
HYS[64/72]D[64300/128320][G/H]U–[5/6]–B
Unbuffered DDR SDRAM Modules
Pin Configuration
VDDSPD
BA0 - BA1: SDRAMs D0 - D8
A0 - An: SDRAMs D0 - D8
RAS: SDRAMs D0 - D8
CAS: SDRAMs D0 - D8
WE: SDRAMs D0 - D8
BA0 - BA1
A0 - An
RAS
V
V
V
V
DD: SPD EEPROM E0
DD/VDDQ: SDRAMs D0 - D8
REF: SDRAMs D0 - D8
SS: SDRAMs D0 - D8
V
DD/VDDQ
VREF
CAS
VSS
WE
VDDID
CKE: SDRAMs D0 - D8
CKE0
Strap: see Note 1
S0
D3
D6
D7
D8
D0
DM0
DQS0
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DM3
DQS3
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DM CS
DQS
I/O 0
DM6
DQS6
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DM CS
DQS
I/O 0
DM CS
DQS
I/O 0
I/O 1
I/O 1
I/O 1
I/O 2
I/O 2
I/O 2
I/O 3
I/O 3
I/O 3
I/O 4
I/O 4
I/O 4
I/O 5
I/O 5
I/O 5
I/O 6
I/O 6
I/O 6
I/O 7
I/O 7
I/O 7
D1
D2
D4
D5
DM1
DQS1
DQ8
DM CS
DQS
I/O 0
DM4
DQS4
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DM CS
DQS
I/O 0
DM7
DQS7
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DM CS
DQS
I/O 0
DQ9
I/O 1
I/O 1
I/O 1
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
I/O 2
I/O 2
I/O 2
I/O 3
I/O 3
I/O 3
I/O 4
I/O 4
I/O 4
I/O 5
I/O 5
I/O 5
I/O 6
I/O 6
I/O 6
I/O 7
I/O 7
I/O 7
DM2
DQS2
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DM CS
DQS
I/O 0
DM5
DQS5
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DM CS
DQS
I/O 0
DM8
DQS8
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
DM CS
DQS
I/O 0
I/O 1
I/O 1
I/O 1
I/O 2
I/O 2
I/O 2
I/O 3
I/O 3
I/O 3
I/O 4
I/O 4
I/O 4
I/O 5
I/O 5
I/O 5
I/O 6
I/O 6
I/O 6
I/O 7
I/O 7
I/O 7
E0
SCL
SAD
SA0
SA1
SA2
VSS
SCL
SAD
A0
A1
A2
WP
MPBD1001
Figure 4
Block Diagram UDIMM Raw Card A ×72, 1Rank, ×8, ECC
Note:
1. VDD = VDDQ, therefore VDDID strap open
2. DQ, DQS, DM resistors are 22 Ω ±5 %
3. BAn, An, RAS, CAS, WE resistors are 5.1 Ω ±5 %
Table 9
Clock Signal Loads
Number of SDRAMs
3 SDRAMs
Clock Input
CK0, CK0
CK1, CK1
CK2, CK2
Note
—
3 SDRAMs
—
3 SDRAMs
—
Data Sheet
14
Rev. 1.0, 2004-05
HYS[64/72]D[64300/128320][G/H]U–[5/6]–B
Unbuffered DDR SDRAM Modules
Pin Configuration
BA0 - BA1
A0 - An
RAS
BA0 - BA1: SDRAMs D0 - D17
A0 - An: SDRAMs D0 - D17
RAS: SDRAMs D0 - D17
CAS: SDRAMs D0 - D17
WE: SDRAMs D0 - D17
CKE: SDRAMs D0 - D8
CKE:SDRAMs D9 - D17
E0
SCL
SAD
SA0
SA1
SA2
VSS
SCL
SAD
A0
CAS
WE
A1
CKE0
CKE1
A2
WP
S0
S1
D0
D9
D4
D5
D6
D7
D8
D13
D14
D15
D16
D17
CS
CS
CS
CS
CS
CS
CS
CS
CS
CS
CS
CS
CS
CS
CS
CS
CS
CS
DM0/DQS9
DQS0
DQ0
DM4/DQS13
DQS4
DQ32
DM
DM
DM
DM
DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ1
DQ33
DQ2
DQ34
DQ3
DQ35
DQ4
DQ36
DQ5
DQ37
DQ6
DQ38
DQ7
DQ39
D1
D2
D3
D10
D11
D12
DM5/DQS14
DQS5
DQ40
DM
DM
DM
DM
DM1/DQS10
DQS1
DQ8
DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ41
DQ9
DQ42
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ43
DQ44
DQ45
DQ46
DQ47
DM2/DQS11
DQS2
DQ16
DM6/DQS15
DQS6
DQ48
DM
DM
DM
DM
DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ17
DQ49
DQ18
DQ50
DQ19
DQ51
DQ20
DQ52
DQ21
DQ53
DQ22
DQ54
DQ23
DQ55
DM7/DQS16
DQS7
DQ56
DM
DM
DM
DM
DM3/DQS12
DQS3
DQ24
DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ57
DQ25
DQ58
DQ26
DQ59
DQ27
DQ60
DQ28
DQ61
DQ29
DQ62
DQ30
DQ63
DQ31
DM8/DQS17
DQS8
CB0
DM
DM
VDDSPD
V
V
V
V
DD: SPD EEPROM E0
DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
V
DD/VDDQ
DD/VDDQ: SDRAMs D0 - D17
REF: SDRAMs D0 - D17
SS: SDRAMs D0 - D17
VREF
CB1
CB2
VSS
CB3
VDDID
DM: SDRAMs D0 - D17
CB4
CB5
Strap: see Note 1
CB6
CB7
MPBD1021
Figure 5
Block Diagram UDIMM Raw Card B ×72, 2Ranks, ×8, ECC
Note:
1. VDD = VDDQ, therefore VDDID strap open
2. DQ, DQS, DM resistors are 22 Ω ±5 %
3. BAn, An, RAS, CAS, WE resistors are 3 Ω ±5 %
Table 10
Clock Signal Loads
Clock Input
CK0, CK0
CK1, CK1
CK2, CK2
Number of SDRAMs
6 SDRAMs
Note
—
6 SDRAMs
—
6 SDRAMs
—
Data Sheet
15
Rev. 1.0, 2004-05
HYS[64/72]D[64300/128320][G/H]U–[5/6]–B
Unbuffered DDR SDRAM Modules
Pin Configuration
6 DRAM Loads
DRAM1
DRAM2
DRAM3
R = 120 Ω ± 5%
CK
DIMM
Connector
4 DRAM Loads
DRAM4
DRAM5
DRAM1
CK
DRAM2
R = 120 Ω ± 5%
DRAM6
DRAM1
Cap.
DIMM
Connector
Cap.
3 DRAM Loads
DRAM5
Cap.
DRAM6
R = 120 Ω ± 5%
DRAM3
DIMM
Connector
Cap.
2 DRAM Loads
DRAM1
DRAM5
Cap.
Cap.
Cap.
R = 120 Ω ± 5%
Cap.
DIMM
Connector
1 DRAM Loads
Cap.
DRAM5
Cap.
R = 120 Ω ± 5%
DRAM3
Cap.
DIMM
Connector
Cap.
Cap.
Cap.
Figure 6
Clock Net Wiring
Data Sheet
16
Rev. 1.0, 2004-05
HYS[64/72]D[64300/128320][G/H]U–[5/6]–B
Unbuffered DDR SDRAM Modules
Electrical Characteristics
3
Electrical Characteristics
3.1
Operating Conditions
Table 11
Parameter
Absolute Maximum Ratings
Symbol
Values
typ.
–
Unit Note/ Test
Condition
min.
VIN, VOUT –0.5
max.
Voltage on I/O pins relative to VSS
VDDQ
+
V
–
0.5
Voltage on inputs relative to VSS
Voltage on VDD supply relative to VSS
Voltage on VDDQ supply relative to VSS
Operating temperature (ambient)
Storage temperature (plastic)
VIN
–1
–1
–1
0
–
+3.6
+3.6
+3.6
+70
+150
–
V
–
–
–
–
–
–
–
VDD
VDDQ
TA
–
V
–
V
–
°C
°C
W
mA
TSTG
PD
-55
–
–
Power dissipation (per SDRAM component)
Short circuit output current
1
IOUT
–
50
–
Attention: Permanent damage to the device may occur if “Absolute Maximum Ratings” are exceeded. This
is a stress rating only, and functional operation should be restricted to recommended operation
conditions. Exposure to absolute maximum rating conditions for extended periods of time may
affect device reliability and exceeding only one of the values may cause irreversible damage to
the integrated circuit.
Table 12
Electrical Characteristics and DC Operating Conditions
1)
Parameter
Symbol
Values
Typ.
Unit Note/Test Condition
Min.
2.3
2.5
2.3
2.5
Max.
2.7
2.7
2.7
2.7
3.6
0
Device Supply Voltage
Device Supply Voltage
Output Supply Voltage
Output Supply Voltage
EEPROM supply voltage
VDD
2.5
2.6
2.5
2.6
2.5
V
V
V
V
V
V
fCK ≤ 166 MHz
fCK > 166 MHz
fCK ≤ 166 MHz
fCK > 166 MHz
—
2)
VDD
3)
VDDQ
VDDQ
2)3)
VDDSPD 2.3
Supply Voltage, I/O Supply VSS
,
0
—
Voltage
VSSQ
4)
5)
Input Reference Voltage
VREF
0.49 ×
VDDQ
0.5 ×
VDDQ
0.51 ×
VDDQ
V
I/O Termination Voltage
(System)
VTT
VREF – 0.04
VREF + 0.04 V
8)
8)
8)
Input High (Logic1) Voltage VIH(DC) VREF + 0.15
Input Low (Logic0) Voltage VIL(DC) –0.3
VDDQ + 0.3 V
VREF – 0.15 V
VDDQ + 0.3 V
Input Voltage Level,
CK and CK Inputs
VIN(DC) –0.3
8)6)
7)
Input Differential Voltage, VID(DC) 0.36
CK and CK Inputs
VDDQ + 0.6 V
VI-Matching Pull-up
Current to Pull-down
Current
VI
0.71
1.4
—
Ratio
Data Sheet
17
Rev. 1.0, 2004-05
10042003-RYU3-RQON
HYS[64/72]D[64300/128320][G/H]U–[5/6]–B
Unbuffered DDR SDRAM Modules
Electrical Characteristics
Table 12
Electrical Characteristics and DC Operating Conditions (cont’d)
1)
Parameter
Symbol
Values
Typ.
Unit Note/Test Condition
Min.
Max.
Input Leakage Current
Output Leakage Current
II
–2
2
µA Any input 0 V ≤ VIN ≤ VDD;
All other pins not under test
8)9)
= 0 V
IOZ
IOH
IOL
–5
5
µA DQs are disabled;
8)
0 V ≤ VOUT ≤ VDDQ
8)
Output High Current,
Normal Strength Driver
—
–16.2
—
mA VOUT = 1.95 V
8)
Output Low
16.2
mA VOUT = 0.35 V
Current, Normal Strength
Driver
1) 0 °C ≤ TA ≤ 70 °C
2) DDR400 conditions apply for all clock frequencies above 166 MHz
3) Under all conditions, VDDQ must be less than or equal to VDD
4) Peak to peak AC noise on VREF may not exceed ± 2% VREF (DC). VREF is also expected to track noise variations in VDDQ
5) VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal
to VREF, and must track variations in the DC level of VREF
.
.
.
6) VID is the magnitude of the difference between the input level on CK and the input level on CK.
7) The ration of the pull-up current to the pull-down current is specified for the same temperature and voltage, over the entire
temperature and voltage range, for device drain to source voltage from 0.25 to 1.0 V. For a given output, it represents the
maximum difference between pull-up and pull-down drivers due to process variation.
8) Inputs are not recognized as valid until VREF stabilizes.
9) Values are shown per DDR SDRAM component
Table 13
AC Timing - Absolute Specifications for PC3200 and PC2700
Parameter
Symbol
–5
–6
Unit
Note/ Test
Condition
1)
DDR400B
DDR333
Min.
–0.7
–0.6
0.45
0.45
Min.
–0.5
–0.6
0.45
0.45
Max.
Max.
+0.7
+0.6
0.55
0.55
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)
DQ output access time from CK/CK
tAC
+0.5
+0.6
0.55
0.55
ns
DQS output access time from CK/CK tDQSCK
ns
CK high-level width
CK low-level width
Clock Half Period
Clock cycle time
tCH
tCL
tHP
tCK
tCK
tCK
ns
min. (tCL, tCH
)
min. (tCL, tCH)
5
6
8
—
—
12
12
ns
CL = 3.0
2)3)4)5)
12
7.5
7.5
ns
ns
CL = 2.5
2)3)4)5)
7.5
12
CL = 2.0
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)6)
DQ and DM input hold time
DQ and DM input setup time
tDH
tDS
0.4
0.4
2.2
—
—
—
0.45
0.45
2.2
—
—
—
ns
ns
ns
Control and Addr. input pulse width
(each input)
tIPW
Data Sheet
18
Rev. 1.0, 2004-05
10042003-RYU3-RQON
HYS[64/72]D[64300/128320][G/H]U–[5/6]–B
Unbuffered DDR SDRAM Modules
Electrical Characteristics
Table 13
AC Timing - Absolute Specifications for PC3200 and PC2700
Parameter
Symbol
–5
–6
Unit
Note/ Test
Condition
1)
DDR400B
DDR333
Min.
Min.
Max.
Max.
2)3)4)5)6)
2)3)4)5)7)
2)3)4)5)7)
2)3)4)5)
DQ and DM input pulse width (each
input)
tDIPW
tHZ
1.75
—
1.75
—
ns
ns
ns
tCK
ns
ns
Data-out high-impedance time from
CK/CK
–0.7
–0.7
0.75
—
+0.7
+0.7
1.25
+0.40
+0.50
–0.7
–0.7
0.75
—
+0.7
Data-out low-impedance time from CK/ tLZ
CK
+0.7
st
Write command to 1 DQS latching
transition
tDQSS
1.25
DQS-DQ skew (DQS and associated tDQSQ
DQ signals)
+0.45
+0.55
TSOPII
2)3)4)5)
Data hold skew factor
tQHS
tQH
—
—
TSOPII
2)3)4)5)
2)3)4)5)
2)3)4)5)
DQ/DQS output hold time
tHP –tQHS
tHP –tQHS
ns
DQS input low (high) pulse width (write tDQSL,H
0.35
—
0.35
—
tCK
cycle)
2)3)4)5)
2)3)4)5)
DQS falling edge to CK setup time
(write cycle)
tDSS
tDSH
0.2
—
—
0.2
—
—
tCK
tCK
DQS falling edge hold time from CK
(write cycle)
0.2
0.2
2)3)4)5)
Mode register set command cycle time tMRD
2
—
2
—
tCK
ns
2)3)4)5)8)
2)3)4)5)9)
2)3)4)5)
Write preamble setup time
Write postamble
tWPRES
0
—
0
—
tWPST
tWPRE
tIS
0.40
0.25
0.6
0.60
—
0.40
0.25
0.75
0.60
—
tCK
tCK
ns
Write preamble
Address and control input setup time
—
—
fast slew rate
3)4)5)6)10)
0.7
—
0.8
—
ns
slow slew
rate
3)4)5)6)10)
Address and control input hold time
tIH
0.6
0.7
—
—
0.75
0.8
—
—
ns
ns
fast slew rate
3)4)5)6)10)
slow slew
rate
3)4)5)6)10)
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)
Read preamble
tRPRE
tRPST
tRAS
0.9
0.40
40
1.1
0.9
1.1
tCK
tCK
Read postamble
0.60
0.40
0.60
Active to Precharge command
70E+3 42
70E+3 ns
Active to Active/Auto-refresh command tRC
55
—
60
—
ns
period
2)3)4)5)
Auto-refresh to Active/Auto-refresh
command period
tRFC
70
—
72
—
ns
2)3)4)5)
2)3)4)5)
2)3)4)5)
Active to Read or Write delay
Precharge command period
Active to Autoprecharge delay
tRCD
tRP
15
15
—
—
18
18
—
—
ns
ns
ns
tRAP
t
– t
RCD RASmin
Data Sheet
19
Rev. 1.0, 2004-05
10042003-RYU3-RQON
HYS[64/72]D[64300/128320][G/H]U–[5/6]–B
Unbuffered DDR SDRAM Modules
Electrical Characteristics
Table 13
AC Timing - Absolute Specifications for PC3200 and PC2700
Parameter
Symbol
–5
–6
Unit
Note/ Test
Condition
1)
DDR400B
DDR333
Min.
12
Min.
Max.
Max.
2)3)4)5)
Active bank A to Active bank B
command
tRRD
10
—
—
ns
2)3)4)5)
Write recovery time
tWR
15
—
15
—
ns
2)3)4)5)11)
Auto precharge write recovery +
precharge time
tDAL
tCK
2)3)4)5)
Internal write to read command delay tWTR
Exit self-refresh to non-read command tXSNR
2
—
—
—
7.8
1
—
—
—
7.8
tCK
ns
2)3)4)5)
75
200
—
75
200
—
2)3)4)5)
Exit self-refresh to read command
Average Periodic Refresh Interval
tXSRD
tREFI
tCK
µs
2)3)4)5)12)
1) 0 °C ≤ TA ≤ 70 °C; VDDQ = 2.5 V ± 0.2 V, VDD = +2.5 V ± 0.2 V (DDR333); VDDQ = 2.6 V ± 0.1 V, VDD = +2.6 V ± 0.1 V
(DDR400)
2) Input slew rate ≥ 1 V/ns for DDR400, DDR333
3) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference
level for signals other than CK/CK, is VREF. CK/CK slew rate are ≥ 1.0 V/ns.
4) Inputs are not recognized as valid until VREF stabilizes.
5) The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (note 3) is VTT
.
6) These parameters guarantee device timing, but they are not necessarily tested on each device.
7) tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred
to a specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ).
8) The specific requirement is that DQS be valid (HIGH, LOW, or some point on a valid transition) on or before this CK edge.
A valid transition is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were
previously in progress on the bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress,
DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on tDQSS
.
9) The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but
system performance (bus turnaround) degrades accordingly.
10) Fast slew rate ≥ 1.0 V/ns , slow slew rate ≥ 0.5 V/ns and < 1 V/ns for command/address and CK & CK slew rate > 1.0 V/
ns, measured between VIH(ac) and VIL(ac)
.
11) For each of the terms, if not already an integer, round to the next highest integer. tCK is equal to the actual system clock
cycle time.
12) A maximum of eight Autorefresh commands can be posted to any given DDR SDRAM device.
Data Sheet
20
Rev. 1.0, 2004-05
10042003-RYU3-RQON
HYS[64/72]D[64300/128320][G/H]U–[5/6]–B
Unbuffered DDR SDRAM Modules
Electrical Characteristics
3.2
Current Conditions and Specification
IDD Conditions
Parameter
Symbol
Operating Current 0
IDD0
one bank; active/ precharge; DQ, DM, and DQS inputs changing once per clock cycle;
address and control inputs changing once every two clock cycles.
Operating Current 1
IDD1
one bank; active/read/precharge; Burst Length = 4; see component data sheet.
Precharge Power-Down Standby Current
all banks idle; power-down mode; CKE ≤ VIL,MAX
IDD2P
IDD2F
Precharge Floating Standby Current
CS ≥ VIH,,MIN, all banks idle; CKE ≥ VIH,MIN
;
address and other control inputs changing once per clock cycle; VIN = VREF for DQ, DQS and DM.
Precharge Quiet Standby Current
IDD2Q
CS ≥ VIHMIN, all banks idle; CKE ≥ VIH,MIN; VIN = VREF for DQ, DQS and DM;
address and other control inputs stable at ≥ VIH,MIN or ≤ VIL,MAX
.
Active Power-Down Standby Current
one bank active; power-down mode; CKE ≤ VILMAX; VIN = VREF for DQ, DQS and DM.
IDD3P
IDD3N
Active Standby Current
one bank active; CS ≥ VIH,MIN; CKE ≥ VIH,MIN; tRC = tRAS,MAX
DQ, DM and DQS inputs changing twice per clock cycle;
address and control inputs changing once per clock cycle.
;
Operating Current Read
IDD4R
one bank active; Burst Length = 2; reads; continuous burst;
address and control inputs changing once per clock cycle;
50% of data outputs changing on every clock edge;
CL = 2 for DDR266(A), CL = 3 for DDR333 and DDR400B; IOUT = 0 mA
Operating Current Write
IDD4W
one bank active; Burst Length = 2; writes; continuous burst;
address and control inputs changing once per clock cycle;
50% of data outputs changing on every clock edge;
CL = 2 for DDR266(A), CL = 3 for DDR333 and DDR400B
Auto-Refresh Current
tRC = tRFCMIN, burst refresh
IDD5
IDD6
IDD7
Self-Refresh Current
CKE ≤ 0.2 V; external clock on
Operating Current 7
four bank interleaving with Burst Length = 4; see component data sheet.
Data Sheet
21
Rev. 1.0, 2004-05
10042003-RYU3-RQON
HYS[64/72]D[64300/128320][G/H]U–[5/6]–B
Unbuffered DDR SDRAM Modules
Electrical Characteristics
Table 14
IDD Specification for HYS[64/72]D[64/128][300/320]HU–5–B
1)2)
Product Type
Unit Note
Organization
512MB
×64
512MB
×64
1GB
×64
1GB
×72
1 Rank
–5
1 Rank
–5
2 Ranks
–5
2 Ranks
–5
Symbol
IDD0
Typ.
800
Max.
920
1040
40
Typ.
900
Max.
1040
1170
40
Typ.
1110
1190
50
Max.
1300
1420
70
Typ.
1250
1340
50
Max.
1460
1590
80
3)
mA
3)4)
IDD1
880
990
mA
5)
IDD2P
IDD2F
IDD2Q
IDD3P
IDD3N
IDD4R
IDD4W
IDD5
20
30
mA
3)
240
290
210
130
380
960
1000
2320
46
270
320
480
580
540
650
mA
5)
150
170
230
300
420
340
470
mA
5)
100
110
140
190
260
220
290
mA
5)
310
350
420
620
750
700
850
mA
3)4)
800
900
1080
1130
2610
51
1110
1150
2230
46
1340
1380
2700
91
1250
1300
2510
52
1500
1550
3030
103
mA
3)
840
950
mA
3)
1920
23
2160
26
mA
5)
IDD6
mA
3)4)
IDD7
2480
2920
2790
3290
2790
3300
3140
3710
mA
1) DRAM component currents only
2) Test condition for maximum values: VDD = 2.7 V, TA = 10 °C
3) The module IDDx values are calculated from the component IDDx data sheet values as:
m × IDDx[component] + n × IDD3N[component] with m and n number of components of rank 1 and 2; n=0 for 1 rank
modules
4) DQ I/O (IDDQ) currents are not included into calculations: module IDD values will be measured differently depending on
load conditions
5) The module IDDx values are calculated from the corrponent IDDx data sheet values as: (m + n) × IDDx[component]
Data Sheet
22
Rev. 1.0, 2004-05
10042003-RYU3-RQON
HYS[64/72]D[64300/128320][G/H]U–[5/6]–B
Unbuffered DDR SDRAM Modules
Electrical Characteristics
Table 15
IDD Specification for HYS[64/72]D[64/128][300/320]HU–6–B
1)2)
Product Type
Unit Note
Organization
512MB
×64
512MB
×72
1 GB
×64
1 GB
×72
1 Rank
–6
1 Rank
–6
2 Ranks
–6
2 Ranks
–6
Symbol
IDD0
Typ.
720
760
20
Max.
840
920
30
Typ.
810
860
30
Max.
950
1040
40
Typ.
1000
1040
50
Max.
1170
1250
60
Typ.
1130
1170
50
Max.
1310
1400
70
3)
mA
3)4)
IDD1
mA
5)
IDD2P
IDD2F
IDD2Q
IDD3P
IDD3N
IDD4R
IDD4W
IDD5
mA
5)
200
140
90
240
190
120
330
840
880
2040
46
230
150
100
320
770
810
1940
26
270
220
140
370
950
990
2300
51
400
270
180
560
960
1000
2000
46
480
450
540
mA
5)
380
310
430
mA
5)
240
200
270
mA
5)
280
680
720
1720
23
660
630
740
mA
3)4)
1170
1210
2370
91
1080
1130
2250
52
1310
1360
2660
103
mA
3)
mA
3)
mA
5)
IDD6
mA
3)4)
IDD7
2200
2600
2480
2930
2480
2930
2790
3290
mA
1) DRAM component currents only
2) Test condition for maximum values: VDD = 2.7 V, TA = 10 °C
3) The module IDDx values are calculated from the component IDDx data sheet values as:
m × IDDx[component] + n × IDD3N[component] with m and n number of components of rank 1 and 2; n=0 for 1 rank
modules
4) DQ I/O (IDDQ) currents are not included into calculations: module IDD values will be measured differently depending on
load conditions
5) The module IDDx values are calculated from the corrponent IDDx data sheet values as: (m + n) × IDDx[component]
[
Data Sheet
23
Rev. 1.0, 2004-05
10042003-RYU3-RQON
HYS[64/72]D[64300/128320][G/H]U–[5/6]–B
Unbuffered DDR SDRAM Modules
SPD Contents
4
SPD Contents
Table 16
SPD Codes for HYS[64/72]D[64/128][300/320]GU–5–B
Product Type
Organization
Label Code
512 MB
512 MB
1 GByte
1 GByte
×64
×72
×64
×72
1 Rank (×8) 1 Rank (×8) 2 Ranks (×8) 2 Ranks (×8)
PC3200U–30330
JEDEC SPD Revision
Rev 0.0
HEX
80
Rev 0.0
HEX
80
Rev 0.0
HEX
80
Rev 0.0
HEX
80
Byte#
0
Description
Programmed SPD Bytes in E2PROM
Total number of Bytes in E2PROM
Memory Type (DDR = 07h)
Number of Row Addresses
Number of Column Addresses
Number of DIMM Ranks
Data Width (LSB)
1
08
08
08
08
2
07
07
07
07
3
0D
0B
01
0D
0B
01
0D
0B
02
0D
0B
02
4
5
6
40
48
40
48
7
Data Width (MSB)
00
00
00
00
8
Interface Voltage Levels
04
04
04
04
9
tCK @ CLmax (Byte 18) [ns]
50
50
50
50
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
t
AC SDRAM @ CLmax (Byte 18) [ns]
50
50
50
50
Error Correction Support
Refresh Rate
00
02
00
02
82
82
82
82
Primary SDRAM Width
Error Checking SDRAM Width
08
08
08
08
00
08
00
08
tCCD [cycles]
01
01
01
01
Burst Length Supported
Number of Banks on SDRAM Device
CAS Latency
0E
04
0E
04
0E
04
0E
04
1C
01
1C
01
1C
01
1C
01
CS Latency
Write Latency
02
02
02
02
DIMM Attributes
20
20
20
20
Component Attributes
C1
60
C1
60
C1
60
C1
60
tCK @ CLmax -0.5 (Byte 18) [ns]
tAC SDRAM @ CLmax -0.5 [ns]
tCK @ CLmax -1 (Byte 18) [ns]
50
50
50
50
75
75
75
75
Data Sheet
24
Rev. 1.0, 2004-05
HYS[64/72]D[64300/128320][G/H]U–[5/6]–B
Unbuffered DDR SDRAM Modules
SPD Contents
Table 16
SPD Codes for HYS[64/72]D[64/128][300/320]GU–5–B (cont’d)
Product Type
Organization
Label Code
512 MB
512 MB
1 GByte
1 GByte
×64
×72
×64
×72
1 Rank (×8) 1 Rank (×8) 2 Ranks (×8) 2 Ranks (×8)
PC3200U–30330
JEDEC SPD Revision
Description
Rev 0.0
HEX
50
Rev 0.0
HEX
50
Rev 0.0
HEX
50
Rev 0.0
HEX
50
Byte#
26
t
t
t
t
t
AC SDRAM @ CLmax -1 [ns]
27
RPmin [ns]
3C
28
3C
28
3C
28
3C
28
28
RRDmin [ns]
29
RCDmin [ns]
3C
28
3C
28
3C
28
3C
28
30
RASmin [ns]
31
Module Density per Rank
80
80
80
80
32
t
t
t
t
AS, tCS [ns]
AH, tCH [ns]
DS [ns]
60
60
60
60
33
60
60
60
60
34
40
40
40
40
35
DH [ns]
40
40
40
40
36 - 40
41
not used
00
00
00
00
t
t
t
t
t
RCmin [ns]
37
37
37
37
42
RFCmin [ns]
CKmax [ns]
DQSQmax [ns]
QHSmax [ns]
41
41
41
41
43
28
28
28
28
44
28
28
28
28
45
50
50
50
50
46
not used
00
00
00
00
47
DIMM PCB Height
00
00
00
00
48 - 61
62
not used
00
00
00
00
SPD Revision
00
00
00
00
63
Checksum of Byte 0-62
JEDEC ID Code of Infineon (1)
JEDEC ID Code of Infineon (2 -8)
Module Manufacturer Location
Part Number, Char 1
Part Number, Char 2
Part Number, Char 3
Part Number, Char 4
3E
C1
00
50
3F
C1
00
51
64
C1
00
C1
00
65 - 71
72
xx
xx
xx
xx
73
36
37
36
37
74
34
32
34
32
75
44
44
44
44
76
36
36
31
31
Data Sheet
25
Rev. 1.0, 2004-05
HYS[64/72]D[64300/128320][G/H]U–[5/6]–B
Unbuffered DDR SDRAM Modules
SPD Contents
Table 16
SPD Codes for HYS[64/72]D[64/128][300/320]GU–5–B (cont’d)
Product Type
Organization
Label Code
512 MB
512 MB
1 GByte
1 GByte
×64
×72
×64
×72
1 Rank (×8) 1 Rank (×8) 2 Ranks (×8) 2 Ranks (×8)
PC3200U–30330
JEDEC SPD Revision
Rev 0.0
HEX
34
Rev 0.0
HEX
34
Rev 0.0
HEX
32
Rev 0.0
HEX
32
Byte#
77
Description
Part Number, Char 5
78
Part Number, Char 6
33
33
38
38
79
Part Number, Char 7
30
30
33
33
80
Part Number, Char 8
30
30
32
32
81
Part Number, Char 9
47
47
30
30
82
Part Number, Char 10
Part Number, Char 11
Part Number, Char 12
Part Number, Char 13
Part Number, Char 14
Part Number, Char 15
Part Number, Char 16
Part Number, Char 17
Part Number, Char 18
Module Revision Code
Test Program Revision Code
Module Manufacturing Date Year
Module Manufacturing Date Week
Module Serial Number (1 - 4)
55
55
47
47
83
35
35
55
55
84
42
42
35
35
85
20
20
42
42
86
20
20
20
20
87
20
20
20
20
88
20
20
20
20
89
20
20
20
20
90
20
20
20
20
91
0x
0x
0x
0x
92
xx
xx
xx
xx
93
xx
xx
xx
xx
94
xx
xx
xx
xx
95 - 98
xx
xx
xx
xx
99 - 127 not used
00
00
00
00
Data Sheet
26
Rev. 1.0, 2004-05
HYS[64/72]D[64300/128320][G/H]U–[5/6]–B
Unbuffered DDR SDRAM Modules
SPD Contents
Table 17
SPD Codes for HYS[64/72]D[64/128][300/320]HU–5–B
Product Type
Organization
Label Code
512 MB
512 MB
1 GByte
1 GByte
×64
×72
×64
×72
1 Rank (×8) 1 Rank (×8) 2 Ranks (×8) 2 Ranks (×8)
PC3200U–30330
JEDEC SPD Revision
Rev 0.0
HEX
80
Rev 0.0
HEX
80
Rev 0.0
HEX
80
Rev 0.0
HEX
80
Byte#
0
Description
Programmed SPD Bytes in E2PROM
Total number of Bytes in E2PROM
Memory Type (DDR = 07h)
Number of Row Addresses
Number of Column Addresses
Number of DIMM Ranks
Data Width (LSB)
1
08
08
08
08
2
07
07
07
07
3
0D
0B
01
0D
0B
01
0D
0B
02
0D
0B
02
4
5
6
40
48
40
48
7
Data Width (MSB)
00
00
00
00
8
Interface Voltage Levels
04
04
04
04
9
tCK @ CLmax (Byte 18) [ns]
50
50
50
50
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
t
AC SDRAM @ CLmax (Byte 18) [ns]
50
50
50
50
Error Correction Support
Refresh Rate
00
02
00
02
82
82
82
82
Primary SDRAM Width
Error Checking SDRAM Width
08
08
08
08
00
08
00
08
tCCD [cycles]
01
01
01
01
Burst Length Supported
Number of Banks on SDRAM Device
CAS Latency
0E
04
0E
04
0E
04
0E
04
1C
01
1C
01
1C
01
1C
01
CS Latency
Write Latency
02
02
02
02
DIMM Attributes
20
20
20
20
Component Attributes
C1
60
C1
60
C1
60
C1
60
tCK @ CLmax -0.5 (Byte 18) [ns]
tAC SDRAM @ CLmax -0.5 [ns]
tCK @ CLmax -1 (Byte 18) [ns]
tAC SDRAM @ CLmax -1 [ns]
50
50
50
50
75
75
75
75
50
50
50
50
Data Sheet
27
Rev. 1.0, 2004-05
HYS[64/72]D[64300/128320][G/H]U–[5/6]–B
Unbuffered DDR SDRAM Modules
SPD Contents
Table 17
SPD Codes for HYS[64/72]D[64/128][300/320]HU–5–B (cont’d)
Product Type
Organization
Label Code
512 MB
512 MB
1 GByte
1 GByte
×64
×72
×64
×72
1 Rank (×8) 1 Rank (×8) 2 Ranks (×8) 2 Ranks (×8)
PC3200U–30330
JEDEC SPD Revision
Description
Rev 0.0
HEX
3C
28
Rev 0.0
HEX
3C
28
Rev 0.0
HEX
3C
28
Rev 0.0
HEX
3C
28
Byte#
27
tRPmin [ns]
tRRDmin [ns]
tRCDmin [ns]
tRASmin [ns]
28
29
3C
28
3C
28
3C
28
3C
28
30
31
Module Density per Rank
80
80
80
80
32
t
t
t
t
AS, tCS [ns]
AH, tCH [ns]
DS [ns]
60
60
60
60
33
60
60
60
60
34
40
40
40
40
35
DH [ns]
40
40
40
40
36 - 40
41
not used
00
00
00
00
t
t
t
t
t
RCmin [ns]
37
37
37
37
42
RFCmin [ns]
CKmax [ns]
DQSQmax [ns]
QHSmax [ns]
41
41
41
41
43
28
28
28
28
44
28
28
28
28
45
50
50
50
50
46
not used
00
00
00
00
47
DIMM PCB Height
00
00
00
00
48 - 61
62
not used
00
00
00
00
SPD Revision
00
00
00
00
63
Checksum of Byte 0-62
JEDEC ID Code of Infineon (1)
JEDEC ID Code of Infineon (2 - 8)
Module Manufacturer Location
Part Number, Char 1
Part Number, Char 2
Part Number, Char 3
Part Number, Char 4
Part Number, Char 5
3E
C1
00
50
3F
C1
00
51
64
C1
00
C1
00
65 - 71
72
xx
xx
xx
xx
73
36
37
36
37
74
34
32
34
32
75
44
44
44
44
76
36
36
31
31
77
34
34
32
32
Data Sheet
28
Rev. 1.0, 2004-05
HYS[64/72]D[64300/128320][G/H]U–[5/6]–B
Unbuffered DDR SDRAM Modules
SPD Contents
Table 17
SPD Codes for HYS[64/72]D[64/128][300/320]HU–5–B (cont’d)
Product Type
Organization
Label Code
512 MB
512 MB
1 GByte
1 GByte
×64
×72
×64
×72
1 Rank (×8) 1 Rank (×8) 2 Ranks (×8) 2 Ranks (×8)
PC3200U–30330
JEDEC SPD Revision
Rev 0.0
HEX
33
Rev 0.0
HEX
33
Rev 0.0
HEX
38
Rev 0.0
HEX
38
Byte#
78
Description
Part Number, Char 6
79
Part Number, Char 7
30
30
33
33
80
Part Number, Char 8
30
30
32
32
81
Part Number, Char 9
48
48
30
30
82
Part Number, Char 10
Part Number, Char 11
Part Number, Char 12
Part Number, Char 13
Part Number, Char 14
Part Number, Char 15
Part Number, Char 16
Part Number, Char 17
Part Number, Char 18
Module Revision Code
Test Program Revision Code
Module Manufacturing Date Year
Module Manufacturing Date Week
Module Serial Number (1 - 4)
55
55
48
48
83
35
35
55
55
84
42
42
35
35
85
20
20
42
42
86
20
20
20
20
87
20
20
20
20
88
20
20
20
20
89
20
20
20
20
90
20
20
20
20
91
0x
0x
0x
0x
92
xx
xx
xx
xx
93
xx
xx
xx
xx
94
xx
xx
xx
xx
95 - 98
xx
xx
xx
xx
99 - 127 not used
00
00
00
00
Data Sheet
29
Rev. 1.0, 2004-05
HYS[64/72]D[64300/128320][G/H]U–[5/6]–B
Unbuffered DDR SDRAM Modules
SPD Contents
Table 18
SPD Codes for HYS[64/72]D[64/128][300/320]GU–6–B
Product Type
Organization
Label Code
512 MB
512 MB
1 GByte
1 GByte
×64
×72
×64
×72
1 Rank (×8) 1 Rank (×8) 2 Ranks (×8) 2 Ranks (×8)
PC2700U–25330
JEDEC SPD Revision
Rev 0.0
HEX
80
Rev 0.0
HEX
80
Rev 0.0
HEX
80
Rev 0.0
HEX
80
Byte#
0
Description
Programmed SPD Bytes in E2PROM
Total number of Bytes in E2PROM
Memory Type (DDR = 07h)
Number of Row Addresses
Number of Column Addresses
Number of DIMM Ranks
Data Width (LSB)
1
08
08
08
08
2
07
07
07
07
3
0D
0B
01
0D
0B
01
0D
0B
02
0D
0B
02
4
5
6
40
48
40
48
7
Data Width (MSB)
00
00
00
00
8
Interface Voltage Levels
04
04
04
04
9
tCK @ CLmax (Byte 18) [ns]
60
60
60
60
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
t
AC SDRAM @ CLmax (Byte 18) [ns]
70
70
70
70
Error Correction Support
Refresh Rate
00
02
00
02
82
82
82
82
Primary SDRAM Width
Error Checking SDRAM Width
08
08
08
08
00
08
00
08
tCCD [cycles]
01
01
01
01
Burst Length Supported
Number of Banks on SDRAM Device
CAS Latency
0E
04
0E
04
0E
04
0E
04
0C
01
0C
01
0C
01
0C
01
CS Latency
Write Latency
02
02
02
02
DIMM Attributes
20
20
20
20
Component Attributes
C1
75
C1
75
C1
75
C1
75
tCK @ CLmax -0.5 (Byte 18) [ns]
tAC SDRAM @ CLmax -0.5 [ns]
tCK @ CLmax -1 (Byte 18) [ns]
tAC SDRAM @ CLmax -1 [ns]
70
70
70
70
00
00
00
00
00
00
00
00
Data Sheet
30
Rev. 1.0, 2004-05
HYS[64/72]D[64300/128320][G/H]U–[5/6]–B
Unbuffered DDR SDRAM Modules
SPD Contents
Table 18
SPD Codes for HYS[64/72]D[64/128][300/320]GU–6–B (cont’d)
Product Type
Organization
Label Code
512 MB
512 MB
1 GByte
1 GByte
×64
×72
×64
×72
1 Rank (×8) 1 Rank (×8) 2 Ranks (×8) 2 Ranks (×8)
PC2700U–25330
JEDEC SPD Revision
Description
Rev 0.0
HEX
48
Rev 0.0
HEX
48
Rev 0.0
HEX
48
Rev 0.0
HEX
48
Byte#
27
tRPmin [ns]
tRRDmin [ns]
tRCDmin [ns]
tRASmin [ns]
28
30
30
30
30
29
48
48
48
48
30
2A
80
2A
80
2A
80
2A
80
31
Module Density per Rank
CS [ns]
CH [ns]
DS [ns]
DH [ns]
32
tAS,
tAH,
t
75
75
75
75
33
t
75
75
75
75
34
t
t
45
45
45
45
35
45
45
45
45
36 - 40
41
not used
00
00
00
00
t
t
t
t
t
RCmin [ns]
3C
48
3C
48
3C
48
3C
48
42
RFCmin [ns]
CKmax [ns]
DQSQmax [ns]
QHSmax [ns]
43
30
30
30
30
44
2D
55
2D
55
2D
55
2D
55
45
46
not used
00
00
00
00
47
DIMM PCB Height
00
00
00
00
48 - 61
62
not used
00
00
00
00
SPD Revision
00
00
00
00
63
Checksum of Byte 0-62
JEDEC ID Code of Infineon (1)
JEDEC ID Code of Infineon (2 - 8)
Module Manufacturer Location
Part Number, Char 1
Part Number, Char 2
Part Number, Char 3
Part Number, Char 4
Part Number, Char 5
42
54
43
55
64
C1
00
C1
00
C1
00
C1
00
65 - 71
72
xx
xx
xx
xx
73
36
37
36
37
74
34
32
34
32
75
44
44
44
44
76
36
36
31
31
77
34
34
32
32
Data Sheet
31
Rev. 1.0, 2004-05
HYS[64/72]D[64300/128320][G/H]U–[5/6]–B
Unbuffered DDR SDRAM Modules
SPD Contents
Table 18
SPD Codes for HYS[64/72]D[64/128][300/320]GU–6–B (cont’d)
Product Type
Organization
Label Code
512 MB
512 MB
1 GByte
1 GByte
×64
×72
×64
×72
1 Rank (×8) 1 Rank (×8) 2 Ranks (×8) 2 Ranks (×8)
PC2700U–25330
JEDEC SPD Revision
Rev 0.0
HEX
33
Rev 0.0
HEX
33
Rev 0.0
HEX
38
Rev 0.0
HEX
38
Byte#
78
Description
Part Number, Char 6
79
Part Number, Char 7
30
30
33
33
80
Part Number, Char 8
30
30
32
32
81
Part Number, Char 9
47
47
30
30
82
Part Number, Char 10
Part Number, Char 11
Part Number, Char 12
Part Number, Char 13
Part Number, Char 14
Part Number, Char 15
Part Number, Char 16
Part Number, Char 17
Part Number, Char 18
Module Revision Code
Test Program Revision Code
Module Manufacturing Date Year
Module Manufacturing Date Week
Module Serial Number (1 - 4)
55
55
47
47
83
36
36
55
55
84
42
42
36
36
85
20
20
42
42
86
20
20
20
20
87
20
20
20
20
88
20
20
20
20
89
20
20
20
20
90
20
20
20
20
91
0x
0x
0x
0x
92
xx
xx
xx
xx
93
xx
xx
xx
xx
94
xx
xx
xx
xx
95 - 98
xx
xx
xx
xx
99 - 127 not used
00
00
00
00
Data Sheet
32
Rev. 1.0, 2004-05
HYS[64/72]D[64300/128320][G/H]U–[5/6]–B
Unbuffered DDR SDRAM Modules
SPD Contents
Table 19
SPD Codes for HYS[64/72]D[64/128][300/320]HU–6–B
Product Type
Organization
Label Code
512 MB
512 MB
1 GByte
1 GByte
×64
×72
×64
×72
1 Rank (×8) 1 Rank (×8) 2 Ranks (×8) 2 Ranks (×8)
PC2700U–25330
JEDEC SPD Revision
Rev 0.0
HEX
80
Rev 0.0
HEX
80
Rev 0.0
HEX
80
Rev 0.0
HEX
80
Byte#
0
Description
Programmed SPD Bytes in E2PROM
Total number of Bytes in E2PROM
Memory Type (DDR = 07h)
Number of Row Addresses
Number of Column Addresses
Number of DIMM Ranks
Data Width (LSB)
1
08
08
08
08
2
07
07
07
07
3
0D
0B
01
0D
0B
01
0D
0B
02
0D
0B
02
4
5
6
40
48
40
48
7
Data Width (MSB)
00
00
00
00
8
Interface Voltage Levels
04
04
04
04
9
tCK @ CLmax (Byte 18) [ns]
60
60
60
60
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
t
AC SDRAM @ CLmax (Byte 18) [ns]
70
70
70
70
Error Correction Support
Refresh Rate
00
02
00
02
82
82
82
82
Primary SDRAM Width
Error Checking SDRAM Width
08
08
08
08
00
08
00
08
tCCD [cycles]
01
01
01
01
Burst Length Supported
Number of Banks on SDRAM Device
CAS Latency
0E
04
0E
04
0E
04
0E
04
0C
01
0C
01
0C
01
0C
01
CS Latency
Write Latency
02
02
02
02
DIMM Attributes
20
20
20
20
Component Attributes
C1
75
C1
75
C1
75
C1
75
tCK @ CLmax -0.5 (Byte 18) [ns]
tAC SDRAM @ CLmax -0.5 [ns]
tCK @ CLmax -1 (Byte 18) [ns]
tAC SDRAM @ CLmax -1 [ns]
70
70
70
70
00
00
00
00
00
00
00
00
Data Sheet
33
Rev. 1.0, 2004-05
HYS[64/72]D[64300/128320][G/H]U–[5/6]–B
Unbuffered DDR SDRAM Modules
SPD Contents
Table 19
SPD Codes for HYS[64/72]D[64/128][300/320]HU–6–B
Product Type
Organization
Label Code
512 MB
512 MB
1 GByte
1 GByte
×64
×72
×64
×72
1 Rank (×8) 1 Rank (×8) 2 Ranks (×8) 2 Ranks (×8)
PC2700U–25330
JEDEC SPD Revision
Description
Rev 0.0
HEX
48
Rev 0.0
HEX
48
Rev 0.0
HEX
48
Rev 0.0
HEX
48
Byte#
27
tRPmin [ns]
tRRDmin [ns]
tRCDmin [ns]
tRASmin [ns]
28
30
30
30
30
29
48
48
48
48
30
2A
80
2A
80
2A
80
2A
80
31
Module Density per Rank
CS [ns]
CH [ns]
DS [ns]
DH [ns]
32
tAS,
tAH,
t
75
75
75
75
33
t
75
75
75
75
34
t
t
45
45
45
45
35
45
45
45
45
36 - 40
41
not used
00
00
00
00
t
t
t
t
t
RCmin [ns]
3C
48
3C
48
3C
48
3C
48
42
RFCmin [ns]
CKmax [ns]
DQSQmax [ns]
QHSmax [ns]
43
30
30
30
30
44
2D
55
2D
55
2D
55
2D
55
45
46
not used
00
00
00
00
47
DIMM PCB Height
00
00
00
00
48 - 61
62
not used
00
00
00
00
SPD Revision
00
00
00
00
63
Checksum of Byte 0-62
JEDEC ID Code of Infineon (1)
JEDEC ID Code of Infineon (2 - 8)
Module Manufacturer Location
Part Number, Char 1
Part Number, Char 2
Part Number, Char 3
Part Number, Char 4
Part Number, Char 5
42
54
43
55
64
C1
00
C1
00
C1
00
C1
00
65 - 71
72
xx
xx
xx
xx
73
36
37
36
37
74
34
32
34
32
75
44
44
44
44
76
36
36
31
31
77
34
34
32
32
Data Sheet
34
Rev. 1.0, 2004-05
HYS[64/72]D[64300/128320][G/H]U–[5/6]–B
Unbuffered DDR SDRAM Modules
SPD Contents
Table 19
SPD Codes for HYS[64/72]D[64/128][300/320]HU–6–B
Product Type
Organization
Label Code
512 MB
512 MB
1 GByte
1 GByte
×64
×72
×64
×72
1 Rank (×8) 1 Rank (×8) 2 Ranks (×8) 2 Ranks (×8)
PC2700U–25330
JEDEC SPD Revision
Rev 0.0
HEX
33
Rev 0.0
HEX
33
Rev 0.0
HEX
38
Rev 0.0
HEX
38
Byte#
78
Description
Part Number, Char 6
79
Part Number, Char 7
30
30
33
33
80
Part Number, Char 8
30
30
32
32
81
Part Number, Char 9
48
48
30
30
82
Part Number, Char 10
Part Number, Char 11
Part Number, Char 12
Part Number, Char 13
Part Number, Char 14
Part Number, Char 15
Part Number, Char 16
Part Number, Char 17
Part Number, Char 18
Module Revision Code
Test Program Revision Code
Module Manufacturing Date Year
Module Manufacturing Date Week
Module Serial Number (1 - 4)
55
55
48
48
83
36
36
55
55
84
42
42
36
36
85
20
20
42
42
86
20
20
20
20
87
20
20
20
20
88
20
20
20
20
89
20
20
20
20
90
20
20
20
20
91
0x
0x
0x
0x
92
xx
xx
xx
xx
93
xx
xx
xx
xx
94
xx
xx
xx
xx
95 - 98
xx
xx
xx
xx
99 - 127 not used
00
00
00
00
Data Sheet
35
Rev. 1.0, 2004-05
HYS[64/72]D[64300/128320][G/H]U–[5/6]–B
Unbuffered DDR SDRAM Modules
Package Outlines
5
Package Outlines
133.35
128.95
0.15
A B C
2.7 MAX.
A
1
2.36
92
6.62
2.175
B
C
±0.1
ø0.1
A B C
64.77
0.4
6.35
±0.1
1.27
49.53
95 x 1.27 = 120.65
±0.1
1.8
0.1
A B C
93
184
3 MIN.
Detail of contacts
1.27
±0.05
1
0.1
A B C
Burr max. 0.4 allowed
L-DIM-184-32
Figure 7
Raw Card A DDR UDIMM HYS64D64300HU-[5/6/7]-B (1 Rank Module)
Data Sheet
36
Rev. 1.0, 2004-05
HYS[64/72]D[64300/128320][G/H]U–[5/6]–B
Unbuffered DDR SDRAM Modules
Package Outlines
133.35
128.95
0.15
A B C
2.7 MAX.
1)
A
1
2.36
92
6.62
2.175
B
C
±0.1
ø0.1
A B C
64.77
0.4
6.35
±0.1
1.27
49.53
95 x 1.27 = 120.65
±0.1
1.8
0.1
A B C
93
184
3 MIN.
Detail of contacts
1.27
±0.05
1
0.1
A B C
1) On ECC modules only
Burr max. 0.4 allowed
L-DIM-184-30
Figure 8
Raw Card A DDR UDIMM HYS72D64300HU-[5/6/7F]-B (1 Rank Module)
Data Sheet
37
Rev. 1.0, 2004-05
HYS[64/72]D[64300/128320][G/H]U–[5/6]–B
Unbuffered DDR SDRAM Modules
Package Outlines
133.35
128.95
0.15
A B C
4 MAX.
A
1
2.36
92
6.62
2.175
B
C
±0.1
ø0.1
A B C
64.77
0.4
6.35
±0.1
1.27
49.53
95 x 1.27 = 120.65
±0.1
1.8
0.1
A B C
93
184
3 MIN.
Detail of contacts
1.27
±0.05
1
0.1
A B C
Burr max. 0.4 allowed
L-DIM-184-33
Figure 9
Raw Card B DDR UDIMM HYS64D128320HU-[5/6/7]-B (2 Ranks Module)
Data Sheet
38
Rev. 1.0, 2004-05
HYS[64/72]D[64300/128320][G/H]U–[5/6]–B
Unbuffered DDR SDRAM Modules
Package Outlines
133.35
128.95
0.15
A B C
4 MAX.
1)
A
1
2.36
92
6.62
2.175
B
C
±0.1
ø0.1
A B C
64.77
0.4
6.35
±0.1
1.27
49.53
95 x 1.27 = 120.65
±0.1
1.8
0.1
A B C
93
184
3 MIN.
Detail of contacts
1.27
±0.05
1
0.1
A B C
1) On ECC modules only
Burr max. 0.4 allowed
L-DIM-184-31
Figure 10 Raw Card B DDR UDIMM HYS72D128320HU-[5/6/7/-B (2 Rank Module)
Data Sheet
39
Rev. 1.0, 2004-05
w w w . i n f i n e o n . c o m
Published by Infineon Technologies AG
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