HYS72T256040HP-3S-A_技术文档

Data Sheet, Rev. 1.00, Feb. 2006

Cover Page

HYS72T64000HP–[3S/3.7]–A

HYS72T1280x0HP–[3S/3.7]–A

HYS72T256x20HP–[3S/3.7]–A

HYS72T256040HP–[3S/3.7]–A

240-Pin Registered DDR2 SDRAM Modules with parity

DDR2 SDRAM

RDIMM SDRAM

RoHs Compliant

Memory Products

Imprint

Edition 2006-02

Published by Infineon Technologies AG,

St.-Martin-Strasse 53,

81669 München, Germany

Attention please!

The information herein is given to describe certain components and shall not be considered as a guarantee of

characteristics.

Terms of delivery and rights to technical change reserved.

We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding

circuits, descriptions and charts stated herein.

Information

For further information on technology, delivery terms and conditions and prices please contact your nearest

Infineon Technologies Office (www.infineon.com).

Warnings

Due to technical requirements components may contain dangerous substances. For information on the types in

question please contact your nearest Infineon Technologies Office.

Infineon Technologies Components may only be used in life-support devices or systems with the express written

approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure

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devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain

and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may

be endangered.

Revision History

HYS72T64000HP–[3S/3.7]–A, HYS72T1280x0HP–[3S/3.7]–A, HYS72T256x20HP–[3S/3.7]–A,

HYS72T256040HP–[3S/3.7]–A

Revision History: 2006-02, Rev. 1.00

Previous Version:

Page

Subjects (major changes since last revision)

Initial Document

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Template: mp_a4_s_rev321 / 3 / 2005-10-05

HYS72T[64/128/256]xx0]HP–[3S/3.7]–A

Registered DDR2 SDRAM Modules with parity

Table of Contents

1

1.1

1.2

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2

2.1

2.2

Pin Configuration and Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3

Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

DC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Speed Grades Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

AC Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

ODT AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Currents Specifications and Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

3.1

3.2

3.3

3.3.1

3.3.2

3.3.3

3.4

3.4.1

3.4.2

I_DDTest Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

On Die Termination (ODT) Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

SPD Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Product Type Nomenclature (DDR2 DRAMs and DIMMs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

4

5

6

Data Sheet

4

Rev. 1.00, 2006-02

04212005-MF7V-DNO1

240-Pin Registered DDR2 SDRAM Modules with parity

DDR2 SDRAM

HYS72T64000HP–[3S/3.7]–A

HYS72T1280x0HP–[3S/3.7]–A

HYS72T256x20HP–[3S/3.7]–A

HYS72T256040HP–[3S/3.7]–A

1

Overview

This chapter gives an overview of the 240-pin Registered DDR2 SDRAM Modules with parity product family and

describes its main characteristics.

1.1

Features

•

240-pin PC2-5300 and PC2-4200 DDR2 SDRAM

memory modules

One rank 64M x 72, 128M x 72, two ranks

128M × 72, 256M × 72, and four ranks 256M × 72

module organization and 64M × 8, 128M × 4 chip

organization

512 MByte, 1GByte and 2GByte module built with

512-Mbit DDR2 SDRAMs in P-TFBGA-60 chipsize

packages.

Standard Double-Data-Rate-Two Synchronous

DRAMs (DDR2 SDRAM) with a single + 1.8 V

(± 0.1 V) power supply

All speed grades faster than DDR2-400 comply with

DDR2-400 timing specifications as well.

•

Registered DIMM Parity bit for address and control

bus

Programmable CAS Latencies (3, 4 & 5), Burst

Length (4 & 8) and Burst Type

•

Auto Refresh (CBR) and Self Refresh

All inputs and outputs SSTL_18 compatible

Off-Chip Driver Impedance Adjustment (OCD) and

On-Die Termination (ODT)

•

Serial Presence Detect with E²PROM

Based on standard reference layouts Raw Card “A-

F”, “C-H”, “B-G”, “J“, “L“ and “N”

•

RDIMM with parity Dimensions (nominal):

30.00 mm high, 133.35 mm wide

RoHS compliant products¹⁾

Table 1

Performance for PC2–5300–555

Product Type Speed Code

Speed Grade

–3S

Unit

—

PC2–5300 5–5–5

max. Clock Frequency

@CL5

@CL4

@CL3

f_CK5

f_CK4

f_CK3

t_RCD

t_RP

t_RAS

t_RC

333

266

200

15

45

MHz

ns

min. RAS-CAS-Delay

min. Row Precharge Time

min. Row Active Time

min. Row Cycle Time

60

ns

1) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic

equipment as defined in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January

2003. These substances include mercury, lead, cadmium, hexavalent chromium, polybrominated biphenyls and

polybrominated biphenyl ethers.

Data Sheet

5

Rev. 1.00, 2006-02

04212005-MF7V-DNO1

HYS72T[64/128/256]xx0]HP–[3S/3.7]–A

Registered DDR2 SDRAM Modules with parity

Overview

Table 2

Performance for PC2–4200–444

Product Type Speed Code

Speed Grade

–3.7

PC2–4200 4–4–4

Unit

—

max. Clock Frequency

@CL5

@CL4

@CL3

f_CK5

f_CK4

f_CK3

t_RCD

t_RP

t_RAS

t_RC

266

200

15

45

MHz

ns

min. RAS-CAS-Delay

min. Row Precharge Time

min. Row Active Time

min. Row Cycle Time

60

ns

Table 3

Performance for PC2–3200–333

Product Type Speed Code

Speed Grade

–5

Units

—

PC2–3200 3–3–3

max. Clock Frequency

@CL5

@CL4

@CL3

f_CK5

f_CK4

f_CK3

t_RCD

t_RP

t_RAS

t_RC

200

15

40

MHz

ns

min. RAS-CAS-Delay

min. Row Precharge Time

min. Row Active Time

min. Row Cycle Time

55

ns

Data Sheet

6

Rev. 1.00, 2006-02

04212005-MF7V-DNO1

HYS72T[64/128/256]xx0]HP–[3S/3.7]–A

Registered DDR2 SDRAM Modules with parity

Overview

1.2

Description

The INFINEON HYS72T[64/128/256]xx0]HP–[3S/3.7]–A module family are Registered DIMM (RDIMM with parity)

with 30.00 mm height based on DDR2 technology. DIMMs are available as ECC modules in 64M x 72

(512 MByte), 128M x 72 (1 GByte) and 256M x 72 (2 GByte) organization and density, intended for mounting into

240-Pin connector sockets.

The memory array is designed with 512-Mbit Double-Data-Rate-Two (DDR2) Synchronous DRAMs. All control

and address signals are re-driven on the DIMM using register devices and a PLL for the clock distribution. This

reduces capacitive loading to the system bus, but adds one cycle to the SDRAM timing. Decoupling capacitors

are mounted on the PCB board. The DIMMs feature serial presence detect based on a serial E²PROM device

using the 2-pin I²C protocol. The first 128 bytes are programmed with configuration data and the second 128 bytes

are available to the customer.

Table 4

Ordering Information for RoHS Compliant Products

Product Type¹⁾

Compliance Code²⁾

Description SDRAM Technology

PC2-5300

HYS72T64000HP–3S–A

HYS72T128000HP–3S–A

HYS72T128020HP–3S–A

HYS72T256020HP–3S–A

HYS72T256220HP–3S–A

HYS72T256040HP–3S–A

PC2-4200

512 MB 1R×8 PC2–5300P–555–12–F0

1 GB 1R×4 PC2–5300P–555–12–H0

1 GB 2R×8 PC2–5300P–555–12–G0

2 GB 2R×4 PC2–5300P–555-12–L0

2 GB 2R×4 PC2–5300P–555-12–J1

2 GB 4R×8 PC2–5300P–555-12–N0

1 Rank, ECC 512 Mbit (×8)

1 Rank, ECC 512 Mbit (×4)

2 Ranks, ECC 512 Mbit (×8)

2 Ranks, ECC 512 Mbit (×4)

4 Ranks, ECC 512 Mbit (×8)

HYS72T64000HP–3.7–A

HYS72T128000HP–3.7–A

HYS72T128020HP–3.7–A

HYS72T256220HP–3.7–A

HYS72T256040HP–3.7–A

512 MB 1R×8 PC2–4200P–444–12–F0

1 GB 1R×4 PC2–4200P–444–12–H0

1 GB 2R×8 PC2–4200P–444–12–G0

2 GB 2R×4 PC2–4200P–444–12–J1

2 GB 4R×8 PC2–4200P–444–12–N0

1 Rank, ECC 512 Mbit (×8)

1 Rank, ECC 512 Mbit (×4)

2 Ranks, ECC 512 Mbit (×8)

2 Ranks, ECC 512 Mbit (×4)

4 Ranks, ECC 512 Mbit (×8)

1) All part numbers end with a place code, designating the silicon die revision. Example: HYS72T128000HP–3.7–A, indicating

Rev. “A” dies are used for DDR2 SDRAM components. For all INFINEON DDR2 module and component nomenclature see

Chapter 6 of this data sheet.

2) The Compliance Code is printed on the module label and describes the speed grade, for example “PC2–4200P–444–

12–H0”, where 4200P means Registered DIMM parity modules with 4.26 GB/sec Module Bandwidth and “444-12” means

Column Address Strobe (CAS) latency = 4, Row Column Delay (RCD) latency = 4 and Row Precharge (RP) latency = 4

using the latest JEDEC SPD Revision 1.2 and produced on the Raw Card “H”

Data Sheet

7

Rev. 1.00, 2006-02

04212005-MF7V-DNO1

HYS72T[64/128/256]xx0]HP–[3S/3.7]–A

Registered DDR2 SDRAM Modules with parity

Overview

Table 5

Address Format

DIMM

Density

Module

Organization

Memory ECC/

# of

SDRAMs

# of row/bank/columns bits Raw Card

Ranks

Non-ECC

512 MB

1 GB

2 GB

64M × 72

1

2

4

ECC

9

14/2/10

A-F

C-H

B-G

J, L

N

128M × 72

256M × 72

18

36

2 GB

Table 6

Components on Modules ¹⁾

Product Type²⁾

DRAM Components²⁾

HYB18T512800AF

HYB18T512400AF

HYB18T512800AF

HYB18T512400AF

HYB18T512800AF

DRAM Density

512 Mbit

DRAM Organization

64M × 8

HYS72T64000HP

HYS72T128000HP

HYS72T128020HP

HYS72T256020HP

HYS72T256220HP

HYS72T256040HP

512 Mbit

128M × 4

512 Mbit

64M × 8

512 Mbit

128M × 4

512 Mbit

128M × 4

512 Mbit

64M × 8

1) For a detailed description of all available functions of the DRAM components on these modules see the component data

sheet.

2) Green Product

Data Sheet

8

Rev. 1.00, 2006-02

04212005-MF7V-DNO1

HYS72T[64/128/256]xx0]HP–[3S/3.7]–A

Registered DDR2 SDRAM Modules with parity

Pin Configuration and Block Diagrams

2

Pin Configuration and Block Diagrams

2.1

Pin Configuration

The pin configuration of the Registered DDR2 SDRAM explained in Table 8 and Table 9 respectively. The pin

DIMM is listed by function in Table 7 (240 pins). The numbering is depicted in Figure 1.

abbreviations used in columns Pin and Buffer Type are

Table 7

Pin Configuration of RDIMM

Pin or Ball No.

Name

Buffer Function

Type Type

Clock Signals

185

186

CK0

I

SSTL

Clock Signal CK0, Complementary Clock Signal CK0

The system clock inputs. All address and command lines are

sampled on the cross point of the rising edge of CK and the

falling edge of CK. A Delay Locked Loop (DLL) circuit is driven

from the clock inputs and output timing for read operations is

synchronized to the input clock.

52

171

CKE0

CKE1

I

SSTL

Clock Enables 1:0

Activates the DDR2 SDRAM CK signal when HIGH and

deactivates the CK signal when LOW. By deactivating the

clocks, CKE0 initiates the Power Down Mode or the Self

Refresh Mode.

Note: 2-Ranks module

Not Connected

NC

—

Note: 1-Rank module

Control Signals

193

76

S0

S1

I

SSTL

Chip Select Rank 1:0

Enables the associated DDR2 SDRAM command decoder

when LOW and disables the command decoder when HIGH.

When the command decoder is disabled, new commands are

ignored but previous operations continue. Rank 0 is selected by

S0; Rank 1 is selected by S1. The input signals also disable all

outputs (except CKE and ODT) of the register(s) on the DIMM

when both inputs are high. When S is HIGH, all register outputs

(except CK, ODT and Chip select) remain in the previous state.

Note: 2-Ranks module

Not Connected

NC

—

Note: 1-Rank module

192

74

73

RAS

CAS

WE

I

SSTL

Row Address Strobe (RAS), Column Address Strobe

(CAS), Write Enable (WE)

When sampled at the cross point of the rising edge of CK, and

falling edge of CK, RAS, CAS and WE define the operation to

be executed by the SDRAM.

Data Sheet

9

Rev. 1.00, 2006-02

04212005-MF7V-DNO1

HYS72T[64/128/256]xx0]HP–[3S/3.7]–A

Registered DDR2 SDRAM Modules with parity

Pin Configuration and Block Diagrams

Table 7

Pin Configuration of RDIMM (cont’d)

Pin or Ball No.

Name

Buffer Function

Type Type

18

RESET

I

CMOS Register Reset

The RESET pin is connected to the RST pin on the register and

to the OE pin on the PLL. When LOW, all register outputs will

be driven LOW and the PLL clocks to the DRAMs and the

register(s) will be set to low-level. The PLL will remain

synchronized with the input clock.

Address Signals

71

190

54

BA0

BA1

BA2

I

SSTL

Bank Address Bus 1:0

Selects internal SDRAM memory bank

Bank Address Bus 2

Greater than 512Mb DDR2 SDRAMS

NC

I

SSTL

Not Connected

Less than 1Gb DDR2 SDRAMS

188

183

63

182

61

60

180

58

A0

A1

A2

A3

A4

A5

A6

A7

I

SSTL

—

Address Bus 12:0, Address Signal 10/AutoPrecharge

During a Bank Activate command cycle, defines the row

address when sampled at the crosspoint of the rising edge of

CK and falling edge of CK. During a Read or Write command

cycle, defines the column address when sampled at the cross

point of the rising edge of CK and falling edge of CK. In addition

to the column address, AP is used to invoke autoprecharge

operation at the end of the burst read or write cycle. If AP is

HIGH, autoprecharge is selected and BA[1:0] defines the bank

to be precharged. If AP is LOW, autoprecharge is disabled.

During a Precharge command cycle, AP is used in conjunction

with BA[1:0] to control which bank(s) to precharge. If AP is

HIGH, all banks will be precharged regardless of the state of

BA[1:0] inputs. If AP is LOW, then BA[1:0] are used to define

which bank to precharge.

179

177

70

A8

A9

A10

AP

A11

A12

A13

NC

57

176

196

Address Signal 13

Not Connected

NC

Note: Non CA parity modules based on 256 Mbit component

Address Signal 14

Note: CA Parity module

Not Connected

Note: Non CA parity module

Address Signal 14

Note: CA Parity module

Not Connected

174

173

A14

NC

I

SSTL

—

NC

I

A15

NC

SSTL

—

NC

Note: Non CA parity module

Data Sheet

10

Rev. 1.00, 2006-02

04212005-MF7V-DNO1

HYS72T[64/128/256]xx0]HP–[3S/3.7]–A

Registered DDR2 SDRAM Modules with parity

Pin Configuration and Block Diagrams

Table 7

Pin Configuration of RDIMM (cont’d)

Pin or Ball No.

Name

Buffer Function

Type Type

Data Signals

3

4

9

10

122

123

128

129

12

13

21

22

131

132

140

141

24

25

30

31

143

144

149

150

33

34

39

40

152

153

158

159

80

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

I/O

SSTL

Data Bus 63:0

Data Input/Output pins

DQ8

DQ9

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

DQ24

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

DQ32

DQ33

DQ34

DQ35

DQ36

DQ37

DQ38

81

86

87

199

200

205

Data Sheet

11

Rev. 1.00, 2006-02

04212005-MF7V-DNO1

HYS72T[64/128/256]xx0]HP–[3S/3.7]–A

Registered DDR2 SDRAM Modules with parity

Pin Configuration and Block Diagrams

Table 7

Pin Configuration of RDIMM (cont’d)

Pin or Ball No.

Name

Buffer Function

Type Type

206

89

90

95

96

208

209

214

215

98

DQ39

DQ40

DQ41

DQ42

DQ43

DQ44

DQ45

DQ46

DQ47

DQ48

DQ49

DQ50

DQ51

DQ52

DQ53

DQ54

DQ55

DQ56

DQ57

DQ58

DQ59

DQ60

DQ61

DQ62

DQ63

I/O

SSTL

Data Bus 63:0

99

107

108

217

218

226

227

110

111

116

117

229

230

235

236

Check Bits

42

43

48

49

161

162

167

168

CB0

CB1

CB2

CB3

CB4

CB5

CB6

CB7

I/O

SSTL

Check Bits 7:0

Check Bit Input / Output pins

Note: NC on Non-ECC module

Data Sheet

12

Rev. 1.00, 2006-02

04212005-MF7V-DNO1

HYS72T[64/128/256]xx0]HP–[3S/3.7]–A

Registered DDR2 SDRAM Modules with parity

Pin Configuration and Block Diagrams

Table 7

Pin Configuration of RDIMM (cont’d)

Pin or Ball No.

Name

Buffer Function

Type Type

Data Strobe Bus

7

6

16

15

28

27

37

36

84

83

93

92

105

104

114

113

46

DQS0

DQS1

DQS2

DQS3

DQS4

DQS5

DQS6

DQS7

DQS8

DQS9

DQS10

DQS11

DQS12

DQS13

DQS14

DQS15

DQS16

DQS17

I/O

SSTL

Data Strobes 17:0

The data strobes, associated with one data byte, sourced with

data transfers. In Write mode, the data strobe is sourced by the

controller and is centered in the data window. In Read mode the

data strobe is sourced by the DDR2 SDRAM and is sent at the

leading edge of the data window. DQS signals are

complements, and timing is relative to the crosspoint of

respective DQS and DQS. If the module is to be operated in

single ended strobe mode, all DQS signals must be tied on the

system board to V_SSthrough a 20 ohm to 10 Kohm resistor and

DDR2 SDRAM mode registers programmed appropriately.

Note: See block diagram for corresponding DQ signals

45

125

126

134

135

146

147

155

156

202

203

211

212

223

224

232

233

164

165

Data Sheet

13

Rev. 1.00, 2006-02

04212005-MF7V-DNO1

HYS72T[64/128/256]xx0]HP–[3S/3.7]–A

Registered DDR2 SDRAM Modules with parity

Pin Configuration and Block Diagrams

Table 7

Pin Configuration of RDIMM (cont’d)

Pin or Ball No.

Name

Buffer Function

Type Type

Data Mask

125

134

146

155

202

211

223

232

DM0

DM1

DM2

DM3

DM4

DM5

DM6

DM7

DM8

I

SSTL

Data Masks 8:0

The data write masks, associated with one data byte. In Write

mode, DM operates as a byte mask by allowing input data to be

written if it is LOW but blocks the write operation if it is HIGH. In

Read mode, DM lines have no effect.

Note: ×8 based module

164

EEPROM

120

SCL

SDA

I

CMOS Serial Bus Clock

This signal is used to clock data into and out of the SPD

EEPROM.

119

I/O

OD

Serial Bus Data

This is a bidirectional pin used to transfer data into or out of the

SPD EEPROM. A resistor must be connected from SDA to

V

_DDSPDon the motherboard to act as a pull-up.

239

240

101

Parity

55

SA0

SA1

SA2

I

CMOS Serial Address Select Bus 2:0

These signals are tied at the system planar to either V_SSor

_DDSPDto configure the serial SPD EEPROM address range

CMOS

V

ERR_OUT

PAR_IN

O

I

CMOS Parity bits

CMOS

Note: Only for modules with parity bit for address and control

bus. Not connected on non-parity registered modules.

Power Supplies

1

V_REF

AI

—

I/O Reference Voltage

Reference voltage for the SSTL-18 inputs.

238

V_DDSPD

PWR —

EEPROM Power Supply

Serial EEPROM positive power supply, wired to a separated

power pin at the connector which supports from 1.7 Volt to 3.6

Volt.

51, 56, 62, 72, 75, V_DDQ

78, 170, 175,,

PWR —

I/O Driver Power Supply

Power and ground for the DDR SDRAM

181, 191, 194

53, 59, 64, 67, 69, V_DD

Power Supply

Power and ground for the DDR SDRAM

172, 178, 184,,

187, 189, 197

Data Sheet

14

Rev. 1.00, 2006-02

04212005-MF7V-DNO1

HYS72T[64/128/256]xx0]HP–[3S/3.7]–A

Registered DDR2 SDRAM Modules with parity

Pin Configuration and Block Diagrams

Table 7

Pin Configuration of RDIMM (cont’d)

Pin or Ball No.

Name

Buffer Function

Type Type

2, 5, 8, 11, 14, 17, V_SS

20, 23, 26, 29, 32,

35, 38, 41, 44, 47,

50, 65, 66, 79, 82,

85, 88, 91, 94, 97,

100, 103, 106,

109, 112, 115,

118, 121, 124,

127, 130, 133,

136, 139, 142,

145, 148, 151,

154, 157, 160,

163, 166, 169,

198, 201, 204,

207, 210, 213,

216, 219, 222,

225, 228, 231,

234, 237

GND —

Ground Plane

Power and ground for the DDR SDRAM

Other Pins

19, 55, 68, 102,

137, 138, 173,

220, 221

NC

—

Not connected

Pins not connected on Infineon RDIMM’s

195

77

ODT0

ODT1

I

SSTL

On-Die Termination Control 1:0

Asserts on-die termination for DQ, DM, DQS, and DQS signals

if enabled via the DDR2 SDRAM mode register.

Note: 2-Ranks module

NC

—

Note: 1-Rank modules

Table 8

Abbreviation

SSTL

Abbreviations for Buffer Type

Description

Serial Stub Terminated Logic (SSTL_18)

CMOS

OD

CMOS Levels

Open Drain. The corresponding pin has 2 operational states, active low and

tristate, and allows multiple devices to share as a wire-OR.

Data Sheet

15

Rev. 1.00, 2006-02

04212005-MF7V-DNO1

HYS72T[64/128/256]xx0]HP–[3S/3.7]–A

Registered DDR2 SDRAM Modules with parity

Pin Configuration and Block Diagrams

Table 9

Abbreviations for Pin Type

Abbreviation

Description

I

O

Standard input-only pin. Digital levels.

Output. Digital levels.

I/O is a bidirectional input/output signal.

Input. Analog levels.

Power

Ground

Not Usable

Not Connected

I/O

AI

PWR

GND

NU

NC

Data Sheet

16

Rev. 1.00, 2006-02

04212005-MF7V-DNO1

ꢃ

HYS72T[64/128/256]xx0]HP–[3S/3.7]–A

Registered DDR2 SDRAM Modules with parity

Pin Configuration and Block Diagrams

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Figure 1

Pin Configuration for RDIMM (240 pins)

Data Sheet

17

Rev. 1.00, 2006-02

04212005-MF7V-DNO1

HYS72T[64/128/256]xx0]HP–[3S/3.7]–A

Registered DDR2 SDRAM Modules with parity

Pin Configuration and Block Diagrams

2.2

Block Diagram

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$13ꢌ

$1ꢀ

$13

$13ꢄ

$13

$13ꢅ

$13

$-ꢉ2$13

.5ꢉ2$13

)ꢉ/ ꢀ

$-ꢄꢉ$13ꢁꢃ

$13ꢁꢃ

$1ꢃꢇ

$-ꢉ2$13

.5ꢉ2$13

)ꢉ/ ꢀ

$-ꢅꢉ$13ꢁꢈ

$13ꢁꢈ

$1ꢇꢂ

$-ꢉ2$13

.5ꢉ2$13

)ꢉ/ ꢀ

$1ꢁ

)ꢉ/ ꢁ

$1ꢃꢈ

)ꢉ/ ꢁ

$1ꢇꢌ

)ꢉ/ ꢁ

$1ꢃ

)ꢉ/ ꢃ

$1ꢃꢅ

)ꢉ/ ꢃ

$1ꢈꢀ

)ꢉ/ ꢃ

$1ꢄ

)ꢉ/ ꢄ

$1ꢃꢆ

)ꢉ/ ꢄ

$1ꢈꢁ

)ꢉ/ ꢄ

$1ꢇ

)ꢉ/ ꢇ

$1ꢃꢂ

)ꢉ/ ꢇ

$1ꢈꢃ

)ꢉ/ ꢇ

$1ꢈ

)ꢉ/ ꢈ

$1ꢃꢌ

)ꢉ/ ꢈ

$1ꢈꢄ

)ꢉ/ ꢈ

$1ꢅ

)ꢉ/ ꢅ

$1ꢄꢀ

)ꢉ/ ꢅ

$1ꢈꢇ

)ꢉ/ ꢅ

$1ꢆ

)ꢉ/ ꢆ

$1ꢄꢁ

)ꢉ/ ꢆ

$1ꢈꢈ

)ꢉ/ ꢆ

$ꢁ

#3

$13

#3

$13

$13ꢁ

$13

$13ꢇ

$13ꢆ

$13

$-ꢁꢉ$13ꢁꢀ

$13ꢁꢀ

$1ꢂ

$-ꢉ2$13

.5ꢉ2$13

)ꢉ/ ꢀ

$-ꢇꢉ$13ꢁꢄ

$13ꢁꢄ

$1ꢄꢃ

$-ꢉ2$13

.5ꢉ2$13

)ꢉ/ ꢀ

$-ꢆꢉ$13ꢁꢅ

$13ꢁꢅ

$1ꢈꢅ

$-ꢉ2$13

.5ꢉ2$13

)ꢉ/ ꢀ

$1ꢌ

)ꢉ/ ꢁ

$1ꢄꢄ

)ꢉ/ ꢁ

$1ꢈꢆ

)ꢉ/ ꢁ

$1ꢁꢀ

)ꢉ/ ꢃ

$1ꢄꢇ

)ꢉ/ ꢃ

$1ꢈꢂ

)ꢉ/ ꢃ

$1ꢁꢁ

)ꢉ/ ꢄ

$1ꢄꢈ

)ꢉ/ ꢄ

$1ꢈꢌ

)ꢉ/ ꢄ

$1ꢁꢃ

)ꢉ/ ꢇ

$1ꢄꢅ

)ꢉ/ ꢇ

$1ꢅꢀ

)ꢉ/ ꢇ

$1ꢁꢄ

)ꢉ/ ꢈ

$1ꢄꢆ

)ꢉ/ ꢈ

$1ꢅꢁ

)ꢉ/ ꢈ

$1ꢁꢇ

)ꢉ/ ꢅ

$1ꢄꢂ

)ꢉ/ ꢅ

$1ꢅꢃ

)ꢉ/ ꢅ

$1ꢁꢈ

)ꢉ/ ꢆ

$1ꢄꢌ

)ꢉ/ ꢆ

$1ꢅꢄ

)ꢉ/ ꢆ

$ꢃ

#3

$13

#3

$13

#3

$13

$13ꢈ

$13ꢂ

$-ꢂꢉ$13ꢁꢆ

$13ꢁꢆ

#"ꢀ

$13ꢃ

$13

$-ꢉ2$13

.5ꢉ2$13

)ꢉ/ ꢀ

$-ꢈꢉ$13ꢁꢇ

$13ꢁꢇ

$1ꢇꢀ

$-ꢉ2$13

.5ꢉ2$13

)ꢉ/ ꢀ

$-ꢉ2$13

.5ꢉ2$13

)ꢉ/ ꢀ

$-ꢃꢉ$13ꢁꢁ

$13ꢁꢁ

$1ꢁꢅ

)ꢉ/ ꢁ

$1ꢇꢁ

)ꢉ/ ꢁ

#"ꢁ

)ꢉ/ ꢁ

$1ꢁꢆ

)ꢉ/ ꢃ

$1ꢇꢃ

)ꢉ/ ꢃ

#"ꢃ

)ꢉ/ ꢃ

$1ꢁꢂ

)ꢉ/ ꢄ

$1ꢇꢄ

)ꢉ/ ꢄ

#"ꢄ

)ꢉ/ ꢄ

$1ꢁꢌ

)ꢉ/ ꢇ

$1ꢇꢇ

)ꢉ/ ꢇ

#"ꢇ

)ꢉ/ ꢇ

$1ꢃꢀ

)ꢉ/ ꢈ

$1ꢇꢈ

)ꢉ/ ꢈ

#"ꢈ

)ꢉ/ ꢈ

$1ꢃꢁ

)ꢉ/ ꢅ

$1ꢇꢅ

)ꢉ/ ꢅ

#"ꢅ

)ꢉ/ ꢅ

$1ꢃꢃ

)ꢉ/ ꢆ

$1ꢇꢆ

)ꢉ/ ꢆ

#"ꢆ

)ꢉ/ ꢆ

$1ꢃꢄ

-0"4ꢀꢁꢂꢀ

Figure 2

Notes

Block Diagram Raw Card A-F RDIMM (x72, 1Rank, x8)

3. CSR of register1 and DCS of register2 connects to

V_DD

1. Unless otherwise noted, resistors are 22 Ω ± 5 %

2. S0 connects to DCS of register1 and CSR of

register2.

4. RESET, PCK7 and PCK7 connect to both registers.

Data Sheet

18

Rev. 1.00, 2006-02

04212005-MF7V-DNO1

HYS72T[64/128/256]xx0]HP–[3S/3.7]–A

Registered DDR2 SDRAM Modules with parity

Pin Configuration and Block Diagrams

#+ꢀ

0,,

/%

0#+ꢀꢉ0#+ꢄꢊ 0#+ꢈꢊ 0#+ꢋ

0#+ꢅ

#+ꢌ 3$2!-S $ꢀꢉ$ꢂꢅ

#+ꢌ 2EGISTER

-0"4ꢀꢁꢀꢂ

6_$$ꢌ 30$ %%02/- %ꢀ

6_$$ꢊ30$

6_$$ꢍ6_$$1

6_2%&

2%3%4

0#+ꢅ

#+ꢌ 2EGISTER

6_$$ꢍ6_$$1ꢌ 3$2!-S $ꢀꢉ$ꢂꢅ

6_2%&ꢌ 3$2!-S $ꢀꢉ$ꢂꢅ

6₃₃ꢌ 3$2!-S $ꢀꢉ$ꢂꢅ

%ꢀ

3ꢀ

"!ꢀ ꢉ "!N

!ꢀ ꢉ !N

2!3

23ꢀ

#3ꢌ 3$2!-S $ꢀꢉ$ꢂꢅ

"!ꢀꢉ"!Nꢌ 3$2!-S $ꢀꢉ$ꢂꢅ

ꢂꢌꢁ

2"!ꢀꢉ2"!N

2!ꢀꢉ2!N

22!3

6₃₃

2

%

'

)

3

4

%

2

!ꢀꢉ!Nꢌ 3$2!-S $ꢀꢉ$ꢂꢅ

2!3ꢌ 3$2!-S $ꢀꢉ$ꢂꢅ

#!3ꢌ 3$2!-S $ꢀꢉ$ꢂꢅ

7%ꢌ 3$2!-S $ꢀꢉ$ꢂꢅ

#+%ꢌ 3$2!-S $ꢀꢉ$ꢂꢅ

/$4ꢌ 3$2!-S $ꢀꢉ$ꢂꢅ

#!3

2#!3

3#,

3$!

!ꢀ

3#,

3$!

3!ꢀ

3!ꢂ

3!ꢁ

6₃₃

7%

27%

#+%ꢀ

2#+%ꢀ

2/$4ꢀ

/$4ꢀ

0#+ꢅ

!ꢂ

!ꢁ

70

0#+ꢅ

2%3%4

23ꢀ

$ꢀ

$ꢄ

$ꢂꢁ

$ꢂꢃ

$ꢂꢆ

$ꢂꢇ

$ꢂꢄ

$ꢂꢅ

#3

$13ꢀ

$1ꢀ

$1ꢂ

$1ꢁ

$1ꢃ

6₃₃

$13

)ꢍ/ ꢀ

)ꢍ/ ꢂ

)ꢍ/ ꢁ

)ꢍ/ ꢃ

$-

$13ꢄ

$13

)ꢍ/ ꢀ

)ꢍ/ ꢂ

)ꢍ/ ꢁ

)ꢍ/ ꢃ

$-

$13ꢂꢁ

$1ꢁꢈ

$1ꢁꢋ

$1ꢃꢀ

$1ꢃꢂ

6₃₃

$13

)ꢍ/ ꢀ

)ꢍ/ ꢂ

)ꢍ/ ꢁ

)ꢍ/ ꢃ

$-

2EGISTER !

0!2?).

6₃₃

6_$$

$13ꢄ

$1ꢆꢈ

$1ꢆꢋ

$1ꢇꢀ

$1ꢇꢂ

6₃₃

#ꢀ

#ꢂ

0!2?).

00/

1%22

$ꢂ

$ꢁ

$ꢃ

$ꢆ

$ꢇ

$ꢅ

#3

$13ꢂ

$1ꢈ

$13

)ꢍ/ ꢀ

)ꢍ/ ꢂ

)ꢍ/ ꢁ

)ꢍ/ ꢃ

$-

$13ꢅ

$1ꢇꢄ

$1ꢇꢅ

$1ꢇꢈ

$1ꢇꢋ

6₃₃

$13

)ꢍ/ ꢀ

)ꢍ/ ꢂ

)ꢍ/ ꢁ

)ꢍ/ ꢃ

$-

$13ꢂꢃ

$1ꢃꢄ

$1ꢃꢅ

$1ꢃꢈ

$1ꢃꢋ

6₃₃

$13

)ꢍ/ ꢀ

)ꢍ/ ꢂ

)ꢍ/ ꢁ

)ꢍ/ ꢃ

$-

2EGISTER "

6_$$

#ꢀ

#ꢂ

0!2?).

$1ꢋ

$1ꢂꢀ

$1ꢂꢂ

6₃₃

00/

1%22

$ꢈ

%RR?/UT

$13

)ꢍ/ ꢀ

)ꢍ/ ꢂ

)ꢍ/ ꢁ

)ꢍ/ ꢃ

$-

$13ꢈ

#"ꢀ

#"ꢂ

#"ꢁ

#"ꢃ

6₃₃

$13

)ꢍ/ ꢀ

)ꢍ/ ꢂ

)ꢍ/ ꢁ

)ꢍ/ ꢃ

$-

$13ꢂꢆ

$1ꢆꢆ

$1ꢆꢇ

$1ꢆꢄ

$1ꢆꢅ

6₃₃

$13

)ꢍ/ ꢀ

)ꢍ/ ꢂ

)ꢍ/ ꢁ

)ꢍ/ ꢃ

$-

$13ꢁ

$1ꢂꢄ

$1ꢂꢅ

$1ꢂꢈ

$1ꢂꢋ

6₃₃

$ꢋ

$13ꢃ

$1ꢁꢆ

$1ꢁꢇ

$1ꢁꢄ

$1ꢁꢅ

6₃₃

$13

)ꢍ/ ꢀ

)ꢍ/ ꢂ

)ꢍ/ ꢁ

)ꢍ/ ꢃ

$-

$13ꢋ

$1ꢆ

$1ꢇ

$1ꢄ

$1ꢅ

6₃₃

$13

)ꢍ/ ꢀ

)ꢍ/ ꢂ

)ꢍ/ ꢁ

)ꢍ/ ꢃ

$-

$13ꢂꢇ

$1ꢇꢁ

$1ꢇꢃ

$1ꢇꢆ

$1ꢇꢇ

6₃₃

$13

)ꢍ/ ꢀ

)ꢍ/ ꢂ

)ꢍ/ ꢁ

)ꢍ/ ꢃ

$-

$ꢂꢀ

$ꢂꢂ

$13ꢆ

$1ꢃꢁ

$1ꢃꢃ

$1ꢃꢆ

$1ꢃꢇ

6₃₃

$13

)ꢍ/ ꢀ

)ꢍ/ ꢂ

)ꢍ/ ꢁ

)ꢍ/ ꢃ

$-

$13ꢂꢀ

$1ꢂꢁ

$1ꢂꢃ

$1ꢂꢆ

$1ꢂꢇ

6₃₃

$13

)ꢍ/ ꢀ

)ꢍ/ ꢂ

)ꢍ/ ꢁ

)ꢍ/ ꢃ

$-

$13ꢂꢄ

$1ꢄꢀ

$1ꢄꢂ

$1ꢄꢁ

$1ꢄꢃ

6₃₃

$13

)ꢍ/ ꢀ

)ꢍ/ ꢂ

)ꢍ/ ꢁ

)ꢍ/ ꢃ

$-

$13ꢇ

$1ꢆꢀ

$1ꢆꢂ

$1ꢆꢁ

$1ꢆꢃ

6₃₃

$13

)ꢍ/ ꢀ

)ꢍ/ ꢂ

)ꢍ/ ꢁ

)ꢍ/ ꢃ

$-

$13ꢂꢂ

$1ꢁꢀ

$1ꢁꢂ

$1ꢁꢁ

$1ꢁꢃ

6₃₃

$13

)ꢍ/ ꢀ

)ꢍ/ ꢂ

)ꢍ/ ꢁ

)ꢍ/ ꢃ

$-

$13ꢂꢅ

#"ꢆ

$13

)ꢍ/ ꢀ

)ꢍ/ ꢂ

)ꢍ/ ꢁ

)ꢍ/ ꢃ

$-

#"ꢇ

#"ꢄ

#"ꢅ

6₃₃

Figure 3

Notes

Block Diagram Raw Card C-H RDIMM (x72, 1Rank, x4)

3. CSR of register1 and DCS of register2 connects to

V_DD.

1. Unless otherwise noted, resistors are 22 Ω ± 5 %

2. S0 connects to DCS of register1 and CSR of

register2.

4. RESET, PCK7 and PCK7 connect to both registers.

Data Sheet

19

Rev. 1.00, 2006-02

04212005-MF7V-DNO1

HYS72T[64/128/256]xx0]HP–[3S/3.7]–A

Registered DDR2 SDRAM Modules with parity

Pin Configuration and Block Diagrams

6_{$ $}

6_{$ $}30$ %%02 / -

%

30$

# +

0, ,

0# + 0# + 0# + 0# +

# + 3$ 2 ! - S $

# + 2 EGISTER

$

0# + 0# + 0# + 0# +

6_{$ $}6_{$ $ 1}

6_{2 %&}

6_{$ $}6_{$ $ 1}3$ 2 ! - S $

$

0# +

6_{2 %&}3$ 2 ! - S $

6₃₃3$ 2 ! - S $

$

2 %3%4

/ %

6₃₃

$

3

" ! N

! N

2 ! 3

# ! 3

7 %

2 3

# 3 3$ 2 ! - S $

$

2 3

# 3 3$ 2 ! - S $

$

2

%

'

" !

2 " ! 2 " ! N

2 ! 2 ! N

2 2 ! 3

2 # ! 3

2 7 %

" ! " ! N 3$ 2 ! - S $

$

!

! N 3$ 2 ! - S $

$

# 3

2 ! 3 3$ 2 ! - S $

# ! 3 3$ 2 ! - S $

7 % 3$ 2 ! - S $

$

)

$ 1 3

3

4

%

2

$ 1 3

$

$ - $ 1 3

$ - 2 $ 1 3

. 5 2 $ 1 3

$ - 2 $ 1 3

# +%

/ $ 4

0# +

2 # +%

2 / $ 4

# +% 3$ 2 ! - S $

/ $ 4 3$ 2 ! - S $

$

$ 1 3

$ 1

. 5 2 $ 1 3

$

) /

2 %3%4

2 3

$

# 3

$ 1 3

$ - 2 $ 1 3

. 5 2 $ 1 3

) /

$ 1 3

$ - 2 $ 1 3

. 5 2 $ 1 3

) /

$ 1 3

$ - $ 1 3

$ 1 3

$ - $ 1 3

$ 1 3

$ 1

$ - 2 $ 1 3

. 5 2 $ 1 3

$ - 2 $ 1 3

. 5 2 $ 1 3

$ 1 3

$ 1

) /

$ 1

%

$ 1

3# ,

3$ !

3!

$ 1

3$ !

$ 1

!

$ 1

!

3!

$ 1

!

3!

6₃₃

$ 1

7 0

$

# 3

$ 1 3

$ - $ 1 3

$ 1 3

$ 1

$ 1 3

$ - 2 $ 1 3

. 5 2 $ 1 3

) /

$ 1 3

$ - 2 $ 1 3

. 5 2 $ 1 3

) /

$ 1 3

$ - 2 $ 1 3

. 5 2 $ 1 3

$ - $ 1 3

$ 1 3

$ 1

$ - 2 $ 1 3

. 5 2 $ 1 3

2 EGISTER !

0! 2 ?).

) /

6₃₃

6_{$ $}

#

$ 1

0! 2 ?).

$ 1

00/

1 %2 2

$ 1

2 EGISTER "

# 3

6_{$ $}

#

$ 1 3

$ - 2 $ 1 3

. 5 2 $ 1 3

) /

$ 1 3

$ - $ 1 3

$ 1 3

$ - 2 $ 1 3

. 5 2 $ 1 3

) /

$ 1 3

$ - $ 1 3

$ 1 3

$ 1

0! 2 ?).

$ - 2 $ 1 3

. 5 2 $ 1 3

$ - 2 $ 1 3

. 5 2 $ 1 3

$ 1 3

$ 1

00/

1 %2 2

) /

$ 1

%RR?/ UT

$ 1

# 3

$ 1 3

$ - $ 1 3

$ 1 3

$ 1

$ 1 3

$ - 2 $ 1 3

. 5 2 $ 1 3

) /

$ 1 3

$ - $ 1 3

$ 1 3

# "

$ 1 3

$ - 2 $ 1 3

. 5 2 $ 1 3

$ - 2 $ 1 3

. 5 2 $ 1 3

$ - 2 $ 1 3

. 5 2 $ 1 3

) /

$ 1

# "

$ 1

- 0" 4

Figure 4

Block Diagram Raw Card B-G RDIMM (x72, 2Ranks, x8)

Notes

2. RS0 and RS1 alternate between the back and front

sides of the DIMM.

1. Unless otherwise noted, resistors are 22 Ω ± 5 %

Data Sheet

20

Rev. 1.00, 2006-02

04212005-MF7V-DNO1

HYS72T[64/128/256]xx0]HP–[3S/3.7]–A

Registered DDR2 SDRAM Modules with parity

Pin Configuration and Block Diagrams

3ꢀ

3ꢂ

23ꢀ

#3ꢍ 3$2!-S $ꢀꢋ$ꢂꢈ

-0"4ꢀꢁꢂꢀ

ꢂꢍꢁ

23ꢂ

#3ꢍ 3$2!-S $ꢂꢃꢋ$ꢅꢊ

"!ꢀꢋ"!Nꢍ 3$2!-S $ꢀꢋ$ꢅꢊ

!ꢀꢋ!Nꢍ 3$2!-S $ꢀꢋ$ꢅꢊ

2!3ꢍ 3$2!-S $ꢀꢋ$ꢅꢊ

#!3ꢍ 3$2!-S $ꢀꢋ$ꢅꢊ

"!ꢀ ꢋ "!N

!ꢀ ꢋ !N

2!3

2"!ꢀꢋ2"!N

2!ꢀꢋ2!N

22!3

2#!3

27%

2#+%ꢀ

2#+%ꢂ

2/$4ꢀ

2/$4ꢂ

#+ꢀ

0,,

0#+ꢀꢋ0#+ꢇꢌ 0#+ꢃꢌ 0#+ꢆ

0#+ꢈ

#+ꢍ 3$2!-S $ꢀꢋ$ꢅꢊ

#+ꢍ 2EGISTER

2

%

'

)

3

4

%

2

#!3

7%

2%3%4

/%

0#+ꢈ

#+ꢍ 2EGISTER

7%ꢍ 3$2!-S $ꢀꢋ$ꢅꢊ

#+%ꢀꢍ 3$2!-S $ꢀꢋ$ꢂꢈ

#+%ꢂꢍ 3$2!-S $ꢂꢃꢋ$ꢅꢊ

/$4ꢀꢍ 3$2!-S $ꢀꢋ$ꢂꢈ

/$4ꢂꢍ 3$2!-S $ꢂꢃꢋ$ꢅꢊ

%ꢀ

#+%ꢀ

#+%ꢂ

/$4ꢀ

/$4ꢂ

0#+ꢈ

2%3%4

3#,

3$!

!ꢀ

3#,

3$!

3!ꢀ

3!ꢂ

3!ꢁ

6₃₃

6_$$ꢌ30$

6_$$ꢄ6_$$1

6_2%&

6_$$ꢍ 30$ %%02/- %ꢀ

6_$$ꢄ6_$$1ꢍ 3$2!-S $ꢀꢋ$ꢂꢈ

6_2%&ꢍ 3$2!-S $ꢀꢋ$ꢂꢈ

6₃₃ꢍ 3$2!-S $ꢀꢋ$ꢂꢈ

!ꢂ

!ꢁ

70

6₃₃

23ꢀ

23ꢂ

$13ꢆ

$1ꢉ

$13ꢀ

$1ꢀ

$ꢀ

$ꢂ

$ꢁ

$ꢅ

$ꢉ

$ꢊ

$ꢇ

$ꢈ

$ꢃ

$ꢂꢃ

$ꢆ

$ꢁꢈ

$ꢁꢃ

$ꢁꢆ

$ꢅꢀ

$ꢅꢂ

$ꢅꢁ

$ꢅꢅ

$ꢅꢉ

$ꢅꢊ

$13 $13 $- #3

)ꢄ/ ꢀ

)ꢄ/ ꢂ

)ꢄ/ ꢁ

)ꢄ/ ꢅ

)ꢄ/ ꢀ

)ꢄ/ ꢂ

)ꢄ/ ꢁ

)ꢄ/ ꢅ

)ꢄ/ ꢀ

)ꢄ/ ꢂ

)ꢄ/ ꢁ

)ꢄ/ ꢅ

)ꢄ/ ꢀ

)ꢄ/ ꢂ

)ꢄ/ ꢁ

)ꢄ/ ꢅ

$1ꢊ

$1ꢂ

$1ꢇ

$1ꢈ

$1ꢁ

$1ꢅ

$13ꢂ

$1ꢃ

$1ꢆ

$1ꢂꢀ

$1ꢂꢂ

$13ꢂꢀ

$1ꢂꢁ

$1ꢂꢅ

$1ꢂꢉ

$1ꢂꢊ

$ꢂꢀ

$ꢂꢆ

$13 $13 $- #3

)ꢄ/ ꢀ

)ꢄ/ ꢂ

)ꢄ/ ꢁ

)ꢄ/ ꢅ

)ꢄ/ ꢀ

)ꢄ/ ꢂ

)ꢄ/ ꢁ

)ꢄ/ ꢅ

)ꢄ/ ꢀ

)ꢄ/ ꢂ

)ꢄ/ ꢁ

)ꢄ/ ꢅ

)ꢄ/ ꢀ

)ꢄ/ ꢂ

)ꢄ/ ꢁ

)ꢄ/ ꢅ

$13ꢁ

$1ꢂꢇ

$1ꢂꢈ

$1ꢂꢃ

$1ꢂꢆ

$13ꢂꢂ

$1ꢁꢀ

$1ꢁꢂ

$1ꢁꢁ

$1ꢁꢅ

$ꢁꢀ

$ꢂꢂ

$13 $13 $- #3

)ꢄ/ ꢀ

)ꢄ/ ꢂ

)ꢄ/ ꢁ

)ꢄ/ ꢅ

)ꢄ/ ꢀ

)ꢄ/ ꢂ

)ꢄ/ ꢁ

)ꢄ/ ꢅ

)ꢄ/ ꢀ

)ꢄ/ ꢂ

)ꢄ/ ꢁ

)ꢄ/ ꢅ

)ꢄ/ ꢀ

)ꢄ/ ꢂ

)ꢄ/ ꢁ

)ꢄ/ ꢅ

$13ꢂꢁ

$1ꢁꢃ

$1ꢁꢆ

$1ꢅꢀ

$1ꢅꢂ

$13ꢅ

$1ꢁꢉ

$1ꢁꢊ

$1ꢁꢇ

$1ꢁꢈ

$ꢁꢂ

$ꢂꢁ

$13 $13 $- #3

)ꢄ/ ꢀ

)ꢄ/ ꢂ

)ꢄ/ ꢁ

)ꢄ/ ꢅ

)ꢄ/ ꢀ

)ꢄ/ ꢂ

)ꢄ/ ꢁ

)ꢄ/ ꢅ

)ꢄ/ ꢀ

)ꢄ/ ꢂ

)ꢄ/ ꢁ

)ꢄ/ ꢅ

)ꢄ/ ꢀ

)ꢄ/ ꢂ

)ꢄ/ ꢁ

)ꢄ/ ꢅ

$13ꢂꢅ

$1ꢅꢇ

$1ꢅꢈ

$1ꢅꢃ

$1ꢅꢆ

$13ꢉ

$1ꢅꢁ

$1ꢅꢅ

$1ꢅꢉ

$1ꢅꢊ

$ꢁꢁ

$ꢂꢅ

$13 $13 $- #3

)ꢄ/ ꢀ

)ꢄ/ ꢂ

)ꢄ/ ꢁ

)ꢄ/ ꢅ

)ꢄ/ ꢀ

)ꢄ/ ꢂ

)ꢄ/ ꢁ

)ꢄ/ ꢅ

)ꢄ/ ꢀ

)ꢄ/ ꢂ

)ꢄ/ ꢁ

)ꢄ/ ꢅ

)ꢄ/ ꢀ

)ꢄ/ ꢂ

)ꢄ/ ꢁ

)ꢄ/ ꢅ

$13ꢊ

$1ꢉꢀ

$1ꢉꢂ

$1ꢉꢁ

$1ꢉꢅ

$13ꢂꢉ

$1ꢉꢉ

$1ꢉꢊ

$1ꢉꢇ

$1ꢉꢈ

$ꢂꢉ

$ꢁꢅ

$13 $13 $- #3

)ꢄ/ ꢀ

)ꢄ/ ꢂ

)ꢄ/ ꢁ

)ꢄ/ ꢅ

)ꢄ/ ꢀ

)ꢄ/ ꢂ

)ꢄ/ ꢁ

)ꢄ/ ꢅ

)ꢄ/ ꢀ

)ꢄ/ ꢂ

)ꢄ/ ꢁ

)ꢄ/ ꢅ

)ꢄ/ ꢀ

)ꢄ/ ꢂ

)ꢄ/ ꢁ

)ꢄ/ ꢅ

$13ꢇ

$1ꢉꢃ

$1ꢉꢆ

$1ꢊꢀ

$1ꢊꢂ

$13ꢂꢊ

$1ꢊꢁ

$1ꢊꢅ

$1ꢊꢉ

$1ꢊꢊ

$ꢁꢉ

$ꢂꢊ

$13 $13 $- #3

)ꢄ/ ꢀ

)ꢄ/ ꢂ

)ꢄ/ ꢁ

)ꢄ/ ꢅ

)ꢄ/ ꢀ

)ꢄ/ ꢂ

)ꢄ/ ꢁ

)ꢄ/ ꢅ

)ꢄ/ ꢀ

)ꢄ/ ꢂ

)ꢄ/ ꢁ

)ꢄ/ ꢅ

)ꢄ/ ꢀ

)ꢄ/ ꢂ

)ꢄ/ ꢁ

)ꢄ/ ꢅ

$13ꢈ

$1ꢊꢇ

$1ꢊꢈ

$1ꢊꢃ

$1ꢊꢆ

$13ꢂꢇ

$1ꢇꢀ

$1ꢇꢂ

$1ꢇꢁ

$1ꢇꢅ

$ꢂꢇ

$ꢁꢊ

$13 $13 $- #3

)ꢄ/ ꢀ

)ꢄ/ ꢂ

)ꢄ/ ꢁ

)ꢄ/ ꢅ

)ꢄ/ ꢀ

)ꢄ/ ꢂ

)ꢄ/ ꢁ

)ꢄ/ ꢅ

)ꢄ/ ꢀ

)ꢄ/ ꢂ

)ꢄ/ ꢁ

)ꢄ/ ꢅ

)ꢄ/ ꢀ

)ꢄ/ ꢂ

)ꢄ/ ꢁ

)ꢄ/ ꢅ

$13ꢂꢈ

#"ꢉ

$13ꢃ

#"ꢀ

$ꢁꢇ

$ꢂꢈ

$13 $13 $- #3

)ꢄ/ ꢀ

)ꢄ/ ꢂ

)ꢄ/ ꢁ

)ꢄ/ ꢅ

)ꢄ/ ꢀ

)ꢄ/ ꢂ

)ꢄ/ ꢁ

)ꢄ/ ꢅ

)ꢄ/ ꢀ

)ꢄ/ ꢂ

)ꢄ/ ꢁ

)ꢄ/ ꢅ

)ꢄ/ ꢀ

)ꢄ/ ꢂ

)ꢄ/ ꢁ

)ꢄ/ ꢅ

#"ꢊ

#"ꢂ

#"ꢇ

#"ꢁ

#"ꢈ

#"ꢅ

Figure 5

Block Diagram Raw Card J RDIMM (x72, 2Ranks, x4)

Notes

3. S0 connects to DCS and S1 Connects to CSR on a

pair of registers. S1 connects to DCS and S0

connects to CSR on another pair of registers.

4. RESET, PCK7 and PCK7 connect to all registers.

1. Unless otherwise noted, resistors are 22 Ω ± 5 %

2. RS0 and RS1 alternate between the bottom and

surface sides of the DIMM.

Data Sheet

21

Rev. 1.00, 2006-02

04212005-MF7V-DNO1

HYS72T[64/128/256]xx0]HP–[3S/3.7]–A

Registered DDR2 SDRAM Modules with parity

Pin Configuration and Block Diagrams

2EGISTER !ꢂ

2EGISTER !ꢃ

2EGISTER "ꢃ

2EGISTER "ꢂ

6₃₃

6_$$

6₃₃

6_$$

#ꢀ

#ꢂ

0!2?).

%RR?/UT

00/

1%22

00/

1%22

00/

1%22

00/

1%22

-0"4ꢀꢁꢀꢀ

Figure 6

Block Diagram Raw Card J Signal for Address and Command Parity Function

Data Sheet

22

Rev. 1.00, 2006-02

04212005-MF7V-DNO1

HYS72T[64/128/256]xx0]HP–[3S/3.7]–A

Registered DDR2 SDRAM Modules with parity

Pin Configuration and Block Diagrams

3ꢀ

3ꢂ

23ꢀ

#3ꢍ 3$2!-S $ꢀꢋ$ꢂꢈ

-0"4ꢀꢁꢂꢀ

ꢂꢍꢁ

23ꢂ

#3ꢍ 3$2!-S $ꢂꢃꢋ$ꢅꢊ

"!ꢀꢋ"!Nꢍ 3$2!-S $ꢀꢋ$ꢅꢊ

!ꢀꢋ!Nꢍ 3$2!-S $ꢀꢋ$ꢅꢊ

2!3ꢍ 3$2!-S $ꢀꢋ$ꢅꢊ

#!3ꢍ 3$2!-S $ꢀꢋ$ꢅꢊ

"!ꢀ ꢋ "!N

!ꢀ ꢋ !N

2!3

2"!ꢀꢋ2"!N

2!ꢀꢋ2!N

22!3

2#!3

27%

2#+%ꢀ

2#+%ꢂ

2/$4ꢀ

2/$4ꢂ

#+ꢀ

0,,

0#+ꢀꢋ0#+ꢇꢌ 0#+ꢃꢌ 0#+ꢆ

0#+ꢈ

#+ꢍ 3$2!-S $ꢀꢋ$ꢅꢊ

#+ꢍ 2EGISTER

2

%

'

)

3

4

%

2

#!3

7%

2%3%4

/%

0#+ꢈ

#+ꢍ 2EGISTER

7%ꢍ 3$2!-S $ꢀꢋ$ꢅꢊ

#+%ꢀꢍ 3$2!-S $ꢀꢋ$ꢂꢈ

#+%ꢂꢍ 3$2!-S $ꢂꢃꢋ$ꢅꢊ

/$4ꢀꢍ 3$2!-S $ꢀꢋ$ꢂꢈ

/$4ꢂꢍ 3$2!-S $ꢂꢃꢋ$ꢅꢊ

%ꢀ

#+%ꢀ

#+%ꢂ

/$4ꢀ

/$4ꢂ

0#+ꢈ

2%3%4

3#,

3$!

!ꢀ

3#,

3$!

3!ꢀ

3!ꢂ

3!ꢁ

6₃₃

6_$$ꢌ30$

6_$$ꢄ6_$$1

6_2%&

6_$$ꢍ 30$ %%02/- %ꢀ

6_$$ꢄ6_$$1ꢍ 3$2!-S $ꢀꢋ$ꢂꢈ

6_2%&ꢍ 3$2!-S $ꢀꢋ$ꢂꢈ

6₃₃ꢍ 3$2!-S $ꢀꢋ$ꢂꢈ

!ꢂ

!ꢁ

70

6₃₃

23ꢀ

23ꢂ

$13ꢆ

$1ꢉ

$13ꢀ

$1ꢀ

$ꢀ

$ꢂ

$ꢁ

$ꢅ

$ꢉ

$ꢊ

$ꢇ

$ꢈ

$ꢃ

$ꢂꢃ

$ꢆ

$ꢁꢈ

$ꢁꢃ

$ꢁꢆ

$ꢅꢀ

$ꢅꢂ

$ꢅꢁ

$ꢅꢅ

$ꢅꢉ

$ꢅꢊ

$13 $13 $- #3

)ꢄ/ ꢀ

)ꢄ/ ꢂ

)ꢄ/ ꢁ

)ꢄ/ ꢅ

)ꢄ/ ꢀ

)ꢄ/ ꢂ

)ꢄ/ ꢁ

)ꢄ/ ꢅ

)ꢄ/ ꢀ

)ꢄ/ ꢂ

)ꢄ/ ꢁ

)ꢄ/ ꢅ

)ꢄ/ ꢀ

)ꢄ/ ꢂ

)ꢄ/ ꢁ

)ꢄ/ ꢅ

$1ꢊ

$1ꢂ

$1ꢇ

$1ꢈ

$1ꢁ

$1ꢅ

$13ꢂ

$1ꢃ

$1ꢆ

$1ꢂꢀ

$1ꢂꢂ

$13ꢂꢀ

$1ꢂꢁ

$1ꢂꢅ

$1ꢂꢉ

$1ꢂꢊ

$ꢂꢀ

$ꢂꢆ

$13 $13 $- #3

)ꢄ/ ꢀ

)ꢄ/ ꢂ

)ꢄ/ ꢁ

)ꢄ/ ꢅ

)ꢄ/ ꢀ

)ꢄ/ ꢂ

)ꢄ/ ꢁ

)ꢄ/ ꢅ

)ꢄ/ ꢀ

)ꢄ/ ꢂ

)ꢄ/ ꢁ

)ꢄ/ ꢅ

)ꢄ/ ꢀ

)ꢄ/ ꢂ

)ꢄ/ ꢁ

)ꢄ/ ꢅ

$13ꢁ

$1ꢂꢇ

$1ꢂꢈ

$1ꢂꢃ

$1ꢂꢆ

$13ꢂꢂ

$1ꢁꢀ

$1ꢁꢂ

$1ꢁꢁ

$1ꢁꢅ

$ꢁꢀ

$ꢂꢂ

$13 $13 $- #3

)ꢄ/ ꢀ

)ꢄ/ ꢂ

)ꢄ/ ꢁ

)ꢄ/ ꢅ

)ꢄ/ ꢀ

)ꢄ/ ꢂ

)ꢄ/ ꢁ

)ꢄ/ ꢅ

)ꢄ/ ꢀ

)ꢄ/ ꢂ

)ꢄ/ ꢁ

)ꢄ/ ꢅ

)ꢄ/ ꢀ

)ꢄ/ ꢂ

)ꢄ/ ꢁ

)ꢄ/ ꢅ

$13ꢂꢁ

$1ꢁꢃ

$1ꢁꢆ

$1ꢅꢀ

$1ꢅꢂ

$13ꢅ

$1ꢁꢉ

$1ꢁꢊ

$1ꢁꢇ

$1ꢁꢈ

$ꢁꢂ

$ꢂꢁ

$13 $13 $- #3

)ꢄ/ ꢀ

)ꢄ/ ꢂ

)ꢄ/ ꢁ

)ꢄ/ ꢅ

)ꢄ/ ꢀ

)ꢄ/ ꢂ

)ꢄ/ ꢁ

)ꢄ/ ꢅ

)ꢄ/ ꢀ

)ꢄ/ ꢂ

)ꢄ/ ꢁ

)ꢄ/ ꢅ

)ꢄ/ ꢀ

)ꢄ/ ꢂ

)ꢄ/ ꢁ

)ꢄ/ ꢅ

$13ꢂꢅ

$1ꢅꢇ

$1ꢅꢈ

$1ꢅꢃ

$1ꢅꢆ

$13ꢉ

$1ꢅꢁ

$1ꢅꢅ

$1ꢅꢉ

$1ꢅꢊ

$ꢁꢁ

$ꢂꢅ

$13 $13 $- #3

)ꢄ/ ꢀ

)ꢄ/ ꢂ

)ꢄ/ ꢁ

)ꢄ/ ꢅ

)ꢄ/ ꢀ

)ꢄ/ ꢂ

)ꢄ/ ꢁ

)ꢄ/ ꢅ

)ꢄ/ ꢀ

)ꢄ/ ꢂ

)ꢄ/ ꢁ

)ꢄ/ ꢅ

)ꢄ/ ꢀ

)ꢄ/ ꢂ

)ꢄ/ ꢁ

)ꢄ/ ꢅ

$13ꢊ

$1ꢉꢀ

$1ꢉꢂ

$1ꢉꢁ

$1ꢉꢅ

$13ꢂꢉ

$1ꢉꢉ

$1ꢉꢊ

$1ꢉꢇ

$1ꢉꢈ

$ꢂꢉ

$ꢁꢅ

$13 $13 $- #3

)ꢄ/ ꢀ

)ꢄ/ ꢂ

)ꢄ/ ꢁ

)ꢄ/ ꢅ

)ꢄ/ ꢀ

)ꢄ/ ꢂ

)ꢄ/ ꢁ

)ꢄ/ ꢅ

)ꢄ/ ꢀ

)ꢄ/ ꢂ

)ꢄ/ ꢁ

)ꢄ/ ꢅ

)ꢄ/ ꢀ

)ꢄ/ ꢂ

)ꢄ/ ꢁ

)ꢄ/ ꢅ

$13ꢇ

$1ꢉꢃ

$1ꢉꢆ

$1ꢊꢀ

$1ꢊꢂ

$13ꢂꢊ

$1ꢊꢁ

$1ꢊꢅ

$1ꢊꢉ

$1ꢊꢊ

$ꢁꢉ

$ꢂꢊ

$13 $13 $- #3

)ꢄ/ ꢀ

)ꢄ/ ꢂ

)ꢄ/ ꢁ

)ꢄ/ ꢅ

)ꢄ/ ꢀ

)ꢄ/ ꢂ

)ꢄ/ ꢁ

)ꢄ/ ꢅ

)ꢄ/ ꢀ

)ꢄ/ ꢂ

)ꢄ/ ꢁ

)ꢄ/ ꢅ

)ꢄ/ ꢀ

)ꢄ/ ꢂ

)ꢄ/ ꢁ

)ꢄ/ ꢅ

$13ꢈ

$1ꢊꢇ

$1ꢊꢈ

$1ꢊꢃ

$1ꢊꢆ

$13ꢂꢇ

$1ꢇꢀ

$1ꢇꢂ

$1ꢇꢁ

$1ꢇꢅ

$ꢂꢇ

$ꢁꢊ

$13 $13 $- #3

)ꢄ/ ꢀ

)ꢄ/ ꢂ

)ꢄ/ ꢁ

)ꢄ/ ꢅ

)ꢄ/ ꢀ

)ꢄ/ ꢂ

)ꢄ/ ꢁ

)ꢄ/ ꢅ

)ꢄ/ ꢀ

)ꢄ/ ꢂ

)ꢄ/ ꢁ

)ꢄ/ ꢅ

)ꢄ/ ꢀ

)ꢄ/ ꢂ

)ꢄ/ ꢁ

)ꢄ/ ꢅ

$13ꢂꢈ

#"ꢉ

$13ꢃ

#"ꢀ

$ꢁꢇ

$ꢂꢈ

$13 $13 $- #3

)ꢄ/ ꢀ

)ꢄ/ ꢂ

)ꢄ/ ꢁ

)ꢄ/ ꢅ

)ꢄ/ ꢀ

)ꢄ/ ꢂ

)ꢄ/ ꢁ

)ꢄ/ ꢅ

)ꢄ/ ꢀ

)ꢄ/ ꢂ

)ꢄ/ ꢁ

)ꢄ/ ꢅ

)ꢄ/ ꢀ

)ꢄ/ ꢂ

)ꢄ/ ꢁ

)ꢄ/ ꢅ

#"ꢊ

#"ꢂ

#"ꢇ

#"ꢁ

#"ꢈ

#"ꢅ

Figure 7

Block Diagram Raw Card L RDIMM (x72, 2Ranks, x4)

Notes

3. S0 connects to DCS and S1 Connects to CSR on a

pair of registers. S1 connects to DCS and S0

connects to CSR on another pair of registers.

4. RESET, PCK7 and PCK7 connect to all registers.

1. Unless otherwise noted, resistors are 22 Ω ± 5 %

2. RS0 and RS1 alternate between the bottom and

surface sides of the DIMM.

Data Sheet

23

Rev. 1.00, 2006-02

04212005-MF7V-DNO1

HYS72T[64/128/256]xx0]HP–[3S/3.7]–A

Registered DDR2 SDRAM Modules with parity

Pin Configuration and Block Diagrams

2EGISTER 5ꢃ

2EGISTER 5ꢄ

0!2?).

0!2?).ꢂ 00/ꢂ

0!2?).ꢅ 00/ꢅ

0!2?).ꢂ 00/ꢂ

0!2?).ꢅ 00/ꢅ

%RR?/UT

094%22ꢂ

094%22ꢅ

094%22ꢂ

094%22ꢅ

-0"4ꢀꢁꢂꢀ

Figure 8

Block Diagram Raw Card L Signal for Address and Command Parity Function

Data Sheet

24

Rev. 1.00, 2006-02

04212005-MF7V-DNO1

HYS72T[64/128/256]xx0]HP–[3S/3.7]–A

Registered DDR2 SDRAM Modules with parity

Pin Configuration and Block Diagrams

3ꢀꢅꢌ

3ꢋꢅꢂ

23ꢀ

#3ꢉ 3$2!-S $ꢀꢃ$ꢆꢅ 23ꢌ

#3ꢉ 3$2!-S $ꢋꢆꢃ$ꢌꢄ

#3ꢉ 3$2!-S $ꢌꢈꢃ$ꢂꢊ

ꢋꢉꢌ

23ꢋ

#3ꢉ 3$2!-S $ꢇꢃ$ꢋꢈꢅ 23ꢂ

"!ꢀꢃ"!Nꢉ 3$2!-S $ꢀꢃ$ꢂꢊ

!ꢀꢃ!Nꢉ 3$2!-S $ꢀꢃ$ꢂꢊ

2!3ꢉ 3$2!-S $ꢀꢃ$ꢂꢊ

#!3ꢉ 3$2!-S $ꢀꢃ$ꢂꢊ

7%ꢉ 3$2!-S $ꢀꢃ$ꢂꢊ

"!ꢀꢃ"!N

!ꢀ ꢃ !N

2!3

2"!ꢀꢃ2"!N

2!ꢀꢃ2!N

22!3

2#!3

27%

2#+%ꢀ

2#+%ꢋ

2/$4ꢀ

2/$4ꢋ

2

%

'

)

3

4

%

2

#+ꢀ

0,,

0#+ꢀꢃ0#+ꢄꢅ 0#+ꢆꢅ 0#+ꢇ

#+ꢉ 3$2!-S $ꢀꢃ$ꢂꢊ

#+ꢉ 2EGISTER

0#+ꢀꢃ0#+ꢄꢅ 0#+ꢆꢅ 0#+ꢇ

#!3

7%

0#+ꢈ

2%3%4

/%

#+ꢉ 2EGISTER

#+%ꢀ

#+%ꢋ

/$4ꢀ

/$4ꢋ

0#+ꢈ

2%3%4

#+%ꢀꢉ 3$2!-S $ꢀꢃ$ꢋꢈ

#+%ꢀꢉ 3$2!-S $ꢋꢆꢃ$ꢂꢊ

/$4ꢀꢉ 3$2!-S $ꢀꢃ$ꢋꢈ

/$4ꢋꢉ 3$2!-S $ꢋꢆꢃ$ꢂꢊ

23ꢀ

23ꢋ

23ꢌ

$ꢇ

23ꢂ

$ꢌꢈ

$ꢌꢆ

$ꢌꢇ

$ꢂꢀ

$ꢂꢋ

$ꢂꢌ

$ꢂꢂ

$ꢂꢁ

$ꢂꢊ

$ꢀ

$ꢋ

$ꢌ

$ꢂ

$ꢁ

$ꢊ

$ꢄ

$ꢈ

$ꢆ

$ꢋꢆ

$ꢋꢇ

$ꢌꢀ

$ꢌꢋ

$ꢌꢌ

$ꢌꢂ

$ꢌꢁ

$ꢌꢊ

$ꢌꢄ

#3

$13

)ꢍ/ꢈꢃꢀ

$-

$13

)ꢍ/ꢈꢃꢀ

$-

$13

)ꢍ/ꢈꢃꢀ

$-

$13ꢀ

$1ꢈꢃꢀ

$-ꢀ

$13

)ꢍ/ꢈꢃꢀ

$-

6_$$ꢅ30$

6_$$ꢍ6_$$1

6_2%&

6_$$ꢉ 30$ %%02/- %ꢀ

6_$$ꢍ6_$$1ꢉ 3$2!-S $ꢀꢃ$ꢂꢊ

6_2%&ꢉ 3$2!-S $ꢀꢃ$ꢂꢊ

6₃₃ꢉ 3$2!-S $ꢀꢃ$ꢂꢊ

$ꢋꢀ

$ꢋꢋ

$ꢋꢌ

$ꢋꢂ

$ꢋꢁ

$ꢋꢊ

$ꢋꢄ

$ꢋꢈ

#3

$13

)ꢍ/ꢈꢃꢀ

$-

$13

)ꢍ/ꢈꢃꢀ

$-

$13

)ꢍ/ꢈꢃꢀ

$-

$13ꢋ

$1ꢋꢊꢃꢆ

$-ꢋ

$13

)ꢍ/ꢈꢃꢀ

$-

6₃₃

%ꢀ

3#,

3$!

3!ꢀ

3!ꢋ

3!ꢌ

6₃₃

$13

)ꢍ/ꢈꢃꢀ

$-

$13

)ꢍ/ꢈꢃꢀ

$-

$13

)ꢍ/ꢈꢃꢀ

$-

$13

)ꢍ/ꢈꢃꢀ

$-

$13ꢌ

$1ꢌꢂꢃꢋꢄ

$-ꢌ

3$!

!ꢀ

!ꢋ

!ꢌ

70

$13

)ꢍ/ꢈꢃꢀ

$-

$13

)ꢍ/ꢈꢃꢀ

$-

$13

)ꢍ/ꢈꢃꢀ

$-

$13

)ꢍ/ꢈꢃꢀ

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Figure 9

Block Diagram Raw Card N RDIMM (x72, 4Ranks, x8)

Notes

3. S2 and S3 have required pull up resistors (100K Ω),

not indicated here.

1. Unless otherwise noted, resistors are 22 Ω ± 5 %

2. S0 and S2 connects to DCS0, S1 and S3 to DCS1

on a Register A. S1 and S3 connects to DCS and

S0 and S2 connects to CSR on another pair of

Register.

4. A13-An have optional pull down resistors (100K Ω),

not indicated here.

5. RESET, PCK7 and PCK7 connect to all Registers.

Other signals connect to two of four Registers.

Data Sheet

25

Rev. 1.00, 2006-02

04212005-MF7V-DNO1

HYS72T[64/128/256]xx0]HP–[3S/3.7]–A

Registered DDR2 SDRAM Modules with parity

Electrical Characteristics

3

Electrical Characteristics

3.1

Absolute Maximum Ratings

Table 10

Absolute Maximum Ratings

Parameter

Symbol

Values

Min.

–0.5

–1.0

–0.5

5

Unit

Note/Test

Condition

Max.

2.3

95

Voltage on any pins relative to V_SS

Voltage on V_DDrelative to V_SS

Voltage on V_DDQrelative to V_SS

V_IN, V_OUT

V_DD

V_DDQ

V

%

Storage Humidity (without condensation)

H_STG

Attention: Stresses above the max. values listed here may cause permanent damage to the device.

Exposure to absolute maximum rating conditions for extended periods may affect device

reliability. Maximum ratings are absolute ratings; exceeding only one of these values maycause

irreversible damage to the integrated circuit.

3.2

DC Operating Conditions

Table 11

Operating Conditions

Parameter

Symbol

Values

Min.

0

Unit Notes

Max.

+55

+95

+100

+105

90

DIMM Module Operating Temperature Range (ambient)

DRAM Component Case Temperature Range

Storage Temperature

Barometric Pressure (operating & storage)

Operating Humidity (relative)

T_OPR

T_CASE

T_STG

PBar

H_OPR

°C

1)2)3)4)

0

–50

+69

10

°C

kPa

5)

%

1) DRAM Component Case Temperature is the surface temperature in the center on the top side of any of the DRAMs.

2) Within the DRAM Component Case Temperature range all DRAM specification will be supported.

3) Above 85 °C DRAM case temperature the Auto-Refresh command interval has to be reduced to t_REFI= 3.9 µs.

4) Self-Refresh period is hard-coded in the DRAMs and therefore it is imperative that the system ensures the DRAM is below

85 °C case temperature before initiating self-refresh operation.

5) Up to 3000 m

Data Sheet

26

Rev. 1.00, 2006-02

04212005-MF7V-DNO1

HYS72T[64/128/256]xx0]HP–[3S/3.7]–A

Registered DDR2 SDRAM Modules with parity

Electrical Characteristics

Table 12

Supply Voltage Levels and DC Operating Conditions

Parameter

Symbol

Values

Min.

1.7

0.49 x V_DDQ

1.7

Unit

Notes

Nom.

1.8

0.5 x V_DDQ

—

Max.

1.9

0.51 x V_DDQ

3.6

Device Supply Voltage

Output Supply Voltage

Input Reference Voltage

SPD Supply Voltage

DC Input Logic High

DC Input Logic Low

V_DD

V

µA

1)

2)

V_DDQ

V_REF

V_DDSPD

V_{IH (DC)}

V_{IL (DC)}

I_L

V

_REF+ 0.125

V

5

_DDQ+ 0.3

_REF– 0.125

–0.30

–5

3)

In / Output Leakage Current

1) Under all conditions, V_DDQmust be less than or equal to V_DD

2) Peak to peak AC noise on V_REFmay not exceed ± 2% V_REF(DC).V_REFis also expected to track noise variations in V_DDQ

.

3) Input voltage for any connector pin under test of 0 V ≤ V_IN≤ V_DDQ+ 0.3 V; all other pins at 0 V. Current is per pin

3.3

AC Characteristics

3.3.1

Table 13

Speed Grades Definitions

Speed Grade Definition Speed Bins for DDR2–667

Speed Grade

DDR2–667

Unit

Notes

IFX Sort Name

CAS-RCD-RP latencies

Parameter

–3S

5–5–5

Min.

5

3.75

3

45

60

15

t_CK

—

ns

Symbol

t_CK

Max.

8

1)2)3)4)

1)2)3)4)5)

1)2)3)4)

Clock Frequency

@ CL = 3

@ CL = 4

@ CL = 5

t_CK

8

Row Active Time

Row Cycle Time

RAS-CAS-Delay

Row Precharge Time

t_RAS

t_RC

t_RCD

t_RP

70000

—

1) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a

differential Slew Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. Timings are

further guaranteed for normal OCD drive strength (EMRS(1) A1 = 0) .

2) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS/DQS,

RDQS/RDQS, input reference level is the crosspoint when in differential strobe mode

3) Inputs are not recognized as valid until V_REFstabilizes. During the period before V_REFstabilizes, CKE = 0.2 x V_DDQis

recognized as low.

4) The output timing reference voltage level is V_TT.

5) t_RAS.MAXis calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is

equal to 9 x t_REFI

.

Data Sheet

27

Rev. 1.00, 2006-02

04212005-MF7V-DNO1

HYS72T[64/128/256]xx0]HP–[3S/3.7]–A

Registered DDR2 SDRAM Modules with parity

Electrical Characteristics

Table 14

Speed Grade Definition Speed Bins for DDR2-533

Speed Grade

DDR2–533C

–3.7

4–4–4

Unit

Note

IFX Sort Name

CAS-RCD-RP latencies

Parameter

t_CK

—

ns

Symbol

t_CK

Min.

5

Max.

8

1)2)3)4)

1)2)3)4)5)

1)2)3)4)

Clock Frequency

@ CL = 3

@ CL = 4

@ CL = 5

3.75

45

8

t_CK

Row Active Time

Row Cycle Time

RAS-CAS-Delay

Row Precharge Time

t_RAS

t_RC

t_RCD

t_RP

70000

—

60

15

—

15

—

1) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a

differential Slew Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. Timings are

further guaranteed for normal OCD drive strength (EMRS(1) A1 = 0) only.

2) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS / DQS,

RDQS / RDQS, input reference level is the crosspoint when in differential strobe mode

3) Inputs are not recognized as valid until V_REFstabilizes. During the period before V_REFstabilizes, CKE = 0.2 x V_DDQis

recognized as low.

4) The output timing reference voltage level is V_TT.

5) t_RAS.MAXis calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is

equal to 9 x t_REFI

.

Table 15

Speed Grade Definition Speed Bins for DDR2–400B

Speed Grade

DDR2–400B

–5

3–3–3

Unit

Note

IFX Sort Name

CAS-RCD-RP latencies

Parameter

t_CK

—

ns

Symbol

t_CK

Min.

5

Max.

8

1)2)3)4)

1)2)3)4)5)

1)2)3)4)

Clock Frequency

@ CL = 3

@ CL = 4

@ CL = 5

5

8

t_CK

5

8

Row Active Time

Row Cycle Time

RAS-CAS-Delay

Row Precharge Time

t_RAS

t_RC

t_RCD

t_RP

40

55

15

70000

—

1) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a

differential Slew Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. Timings are

further guaranteed for normal OCD drive strength (EMRS(1) A1 = 0) only.

2) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS / DQS,

RDQS / RDQS, input reference level is the crosspoint when in differential strobe mode

3) Inputs are not recognized as valid until V_REFstabilizes. During the period before V_REFstabilizes, CKE = 0.2 x V_DDQis

recognized as low.

4) The output timing reference voltage level is V_TT.

5) t_RAS.MAXis calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is

equal to 9 x t_REFI

.

Data Sheet

28

Rev. 1.00, 2006-02

04212005-MF7V-DNO1

HYS72T[64/128/256]xx0]HP–[3S/3.7]–A

Registered DDR2 SDRAM Modules with parity

Electrical Characteristics

3.3.2

AC Timing Parameters

List of AC Timing Tables

•

Table 16 “Timing Parameter by Speed Grade - DDR2–667” on Page 29

Table 17 “Timing Parameter by Speed Grade - DDR2-533” on Page 31

Table 18 “Timing Parameter by Speed Grade - DDR2-400” on Page 33

Table 16

Parameter

Timing Parameter by Speed Grade - DDR2–667

Symbol

DDR2–667

Unit

Notes^1)2)3)4)5)

6)7)

Min.

–450

2

0.45

3

0.45

WR + t_RP

Max.

+450

—

0.55

—

DQ output access time from CK / CK

CAS A to CAS B command period

CK, CK high-level width

CKE minimum high and low pulse width

CK, CK low-level width

t_AC

ps

t_CCD

t_CH

t_CKE

t_CL

t_CK

0.55

—

Auto-Precharge write recovery + precharge t_DAL

time

Minimum time clocks remain ON after CKE t_DELAY

t_IS+ t_CK+ t_IH

—

––

—

ns

ps

asynchronously drops LOW

DQ and DM input hold time (differential data t_DH(base)

175

––

strobe)

DQ and DM input hold time (single ended

data strobe)

t_DH1(base)

DQ and DM input pulse width (each input)

DQS output access time from CK / CK

DQS input low (high) pulse width (write cycle) t_DQSL,H

DQS-DQ skew (for DQS & associated DQ

signals)

t_DIPW

t_DQSCK

0.35

–400

0.35

—

+400

—

t_CK

ps

t_CK

ps

t_DQSQ

240

Write command to 1st DQS latching

transition

t_DQSS

– 0.25

100

––

+ 0.25

—

t_CK

ps

DQ and DM input setup time (differential data t_DS(base)

strobe)

DQ and DM input setup time (single ended

data strobe)

t

_DS1(base)

—

ps

DQS falling edge hold time from CK (write

cycle)

DQS falling edge to CK setup time (write

cycle)

t_DSH

t_DSS

t_HP

0.2

—

t_CK

0.2

—

Clock half period

MIN. (t_CL,t_CH)

Data-out high-impedance time from CK / CK t_HZ

—

275

0.6

t_AC.MAX

—

ps

t_CK

Address and control input hold time

t_IH(base)

Address and control input pulse width

(each input)

t_IPW

Address and control input setup time

DQ low-impedance time from CK / CK

t_IS(base)

t_LZ(DQ)

200

2 ×

t_AC.MIN

—

t_AC.MAX

ps

Data Sheet

29

Rev. 1.00, 2006-02

04212005-MF7V-DNO1

HYS72T[64/128/256]xx0]HP–[3S/3.7]–A

Registered DDR2 SDRAM Modules with parity

Electrical Characteristics

Table 16

Parameter

Timing Parameter by Speed Grade - DDR2–667 (cont’d)

Symbol

DDR2–667

Unit

Notes^1)2)3)4)5)

6)7)

Min.

t_AC.MIN

2

Max.

t_AC.MAX

—

12

—

340

7.8

3.9

—

DQS low-impedance from CK / CK

Mode register set command cycle time

OCD drive mode output delay

Data output hold time from DQS

Data hold skew factor

t_LZ(DQS)

t_MRD

t_OIT

ps

t_CK

ns

0

t_QH

t_QHS

t_REFI

t

—

_HPQ– t_QHS

ps

µs

ns

8)

9)

Average periodic refresh Interval

—

Auto-Refresh to Active/Auto-Refresh

command period

t_RFC

105

Precharge-All (4 banks) command period

Read preamble

Read postamble

Active bank A to Active bank B command

period

t_RP

—

ns

t_CK

ns

t_CK

ns

t_RPRE

t_RPST

t_RRD

0.9

0.40

7.5

10

7.5

0.35 x t_CK

0.40

15

1.1

0.60

—

0.60

—

Internal Read to Precharge command delay t_RTP

Write preamble

Write postamble

Write recovery time for write without Auto-

Precharge

t_WPRE

t_WPST

t_WR

Write recovery time for write with Auto-

Precharge

WR

t

_WR/t_CK

t_CK

Internal Write to Read command delay

Exit power down to any valid command

(other than NOP or Deselect)

t_WTR

t_XARD

7.5

2

—

ns

t_CK

Exit active power-down mode to Read

command (slow exit, lower power)

Exit precharge power-down to any valid

command (other than NOP or Deselect)

t_XARDS

t_XP

7 – AL

2

—

t_CK

Exit Self-Refresh to non-Read command

Exit Self-Refresh to Read command

t_XSNR

t_XSRD

t

_RFC+10

—

ns

t_CK

200

1) For details and notes see the relevant INFINEON component data sheet

2) V_DDQ= 1.8 V ± 0.1 V; V_DD= 1.8 V ± 0.1 V. See notes ^4)5)6)7)

3) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be

powered down and then restarted through the specified initialization sequence before normal operation can continue.

4) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a

differential Slew Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode.

5) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS/DQS,

RDQS/RDQS, input reference level is the crosspoint when in differential strobe mode.

6) Inputs are not recognized as valid until V_REFstabilizes. During the period before V_REFstabilizes, CKE = 0.2 x V_DDQis

recognized as low.

7) The output timing reference voltage level is V_TT.

8) 0 °C≤ T_CASE≤ 85 °C

9) 85 °C < T_CASE≤ 95 °C

Data Sheet

30

Rev. 1.00, 2006-02

04212005-MF7V-DNO1

HYS72T[64/128/256]xx0]HP–[3S/3.7]–A

Registered DDR2 SDRAM Modules with parity

Electrical Characteristics

Table 17

Parameter

Timing Parameter by Speed Grade - DDR2-533

Symbol

DDR2–533

Unit Notes^1)2)3)4)

5)6)7)

Min.

–500

2

0.45

3

0.45

WR + t_RP

Max.

+500

—

0.55

—

DQ output access time from CK / CK

CAS A to CAS B command period

CK, CK high-level width

CKE minimum high and low pulse width

CK, CK low-level width

t_AC

ps

t_CCD

t_CH

t_CKE

t_CL

t_CK

0.55

—

Auto-Precharge write recovery +

precharge time

t_DAL

Minimum time clocks remain ON after CKE t_DELAY

t_IS+ t_CK+ t_IH

225

––

—

ns

ps

asynchronously drops LOW

DQ and DM input hold time (differential

data strobe)

t_DH(base)

_DH1(base)

DQ and DM input hold time (single ended

data strobe)

t

–25

DQ and DM input pulse width (each input) t_DIPW

0.35

–450

0.35

—

+450

—

t_CK

ps

t_CK

DQS output access time from CK / CK

t_DQSCK

t_DQSL,H

DQS input low (high) pulse width (write

cycle)

DQS-DQ skew (for DQS & associated DQ t_DQSQ

—

300

+ 0.25

—

ps

t_CK

ps

t_CK

signals)

Write command to 1st DQS latching

transition

t_DQSS

– 0.25

100

–25

0.2

DQ and DM input setup time (differential

data strobe)

t_DS(base)

DQ and DM input setup time (single ended t_DS1(base)

—

data strobe)

DQS falling edge hold time from CK (write t_DSH

—

cycle)

DQS falling edge to CK setup time (write t_DSS

0.2

—

cycle)

Clock half period

t_HP

MIN. (t_CL,t_CH)

Data-out high-impedance time from CK / t_HZ

—

t_AC.MAX

ps

CK

Address and control input hold time

Address and control input pulse width

(each input)

t_IH(base)

t_IPW

375

0.6

—

ps

t_CK

Address and control input setup time

DQ low-impedance time from CK / CK

t_IS(base)

t_LZ(DQ)

250

2 ×

t_AC.MIN

—

t_AC.MAX

ps

DQS low-impedance from CK / CK

Mode register set command cycle time

OCD drive mode output delay

t_LZ(DQS)

t_MRD

t_OIT

t_AC.MIN

2

0

t_AC.MAX

—

12

ps

t_CK

ns

Data output hold time from DQS

t_QH

t

_HP–t_QHS

—

Data Sheet

31

Rev. 1.00, 2006-02

04212005-MF7V-DNO1

HYS72T[64/128/256]xx0]HP–[3S/3.7]–A

Registered DDR2 SDRAM Modules with parity

Electrical Characteristics

Table 17

Parameter

Timing Parameter by Speed Grade - DDR2-533 (cont’d)

Symbol

DDR2–533

Unit Notes^1)2)3)4)

5)6)7)

Min.

—

Max.

400

7.8

Data hold skew factor

Average periodic refresh Interval

t_QHS

t_REFI

ps

µs

8)

9)

—

3.9

µs

Auto-Refresh to Active/Auto-Refresh

command period

t_RFC

105

—

ns

Precharge-All (4 banks) command period t_RP

t_RP

0.9

0.40

7.5

10

—

ns

t_CK

ns

Read preamble

Read postamble

t_RPRE

t_RPST

1.1

0.60

—

Active bank A to Active bank B command t_RRD

period

Internal Read to Precharge command

delay

t_RTP

7.5

Write preamble

Write postamble

t_WPRE

t_WPST

0.25 x t_CK

0.40

15

—

0.60

—

t_CK

ns

Write recovery time for write without Auto- t_WR

Precharge

Write recovery time for write with Auto-

Precharge

WR

t

_WR/t_CK

t_CK

Internal Write to Read command delay

Exit power down to any valid command

(other than NOP or Deselect)

t_WTR

t_XARD

7.5

2

—

ns

t_CK

Exit active power-down mode to Read

command (slow exit, lower power)

Exit precharge power-down to any valid

command (other than NOP or Deselect)

t_XARDS

t_XP

6 – AL

2

—

t_CK

Exit Self-Refresh to non-Read command t_XSNR