HYS72T64020HP-3.7-A_技术文档

Data Sheet, Rev. 1.0, Mar 2006

HYS72T32000HP–[3S/3.7]–A

HYS72T64001HP–[3S/3.7]–A

HYS72T64020HP–[3S/3.7]–A

240-Pin Registered DDR2 SDRAM Modules

DDR2 SDRAM

RDIMM SDRAM

RoHs Compliant

Memory Products

Edition 2006-03

Published by Infineon Technologies AG,

St.-Martin-Strasse 53,

81669 München, Germany

Attention please!

The information herein is given to describe certain components and shall not be considered as a guarantee of

characteristics.

Terms of delivery and rights to technical change reserved.

We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding

circuits, descriptions and charts stated herein.

Information

For further information on technology, delivery terms and conditions and prices please contact your nearest

Infineon Technologies Office (www.infineon.com).

Warnings

Due to technical requirements components may contain dangerous substances. For information on the types in

question please contact your nearest Infineon Technologies Office.

Infineon Technologies Components may only be used in life-support devices or systems with the express written

approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure

of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support

devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain

and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may

be endangered.

HYS72T32000HP–[3S/3.7]–A, HYS72T64001HP–[3S/3.7]–A, HYS72T64020HP–[3S/3.7]–A

Revision History: 2006-03, Rev. 1.0

Page

Subjects (major changes since last revision)

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Template: mp_a4_s_rev321 / 3 / 2005-10-05

HYS72T[32/64]xxxHP–[3S/3.7]–A

Registered DDR2 SDRAM Modules

Table of Contents

1

1.1

1.2

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2

2.1

2.2

Pin Configuration and Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

3

3.1

3.2

3.3

3.3.1

3.3.2

3.3.3

3.4

3.4.1

3.4.2

Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

DC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Speed Grades Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

AC Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

ODT AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Currents Specifications and Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Currents Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

On Die Termination (ODT) Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

4

5

6

SPD Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Product Type Nomenclature (DDR2 DRAMs and DIMMs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Data Sheet

4

Rev. 1.0, 2006-03

02102006-0OKM-JLO7

240-Pin Registered DDR2 SDRAM Modules

DDR2 SDRAM

HYS72T32000HP–[3S/3.7]–A

HYS72T64001HP–[3S/3.7]–A

HYS72T64020HP–[3S/3.7]–A

1

Overview

This chapter gives an overview of the 240-pin Registered DDR2 SDRAM Modules with parity bit product family

and describes its main characteristics.

1.1

Features

•

240-pin PC2–5300 and PC2–4200 DDR2 SDRAM

memory modules.

One rank in 32M × 72, 64M x 72 and two rank in

64M × 72 module organization and 32M × 8,

64M × 4 chip organization

256M, 512 MByte modules are built with 256-Mbit

DDR2 SDRAMs in P-TFBGA-60 chipsize

packages.

Standard Double-Data-Rate-Two Synchronous

DRAMs (DDR2 SDRAM) with a single + 1.8 V

(± 0.1 V) power supply

•

Programmable CAS Latencies (3, 4 and 5), Burst

Length (4 & 8) and Burst Type

•

Auto Refresh (CBR) and Self Refresh

Average Refresh Period 7.8 µs at a T_CASElower

than 85 °C, 3.9 µs between 85 °C and 95 °C

Programmable self refresh rate via EMRS2 setting

All inputs and outputs SSTL_18 compatible

Off-Chip Driver Impedance Adjustment (OCD) and

On-Die Termination (ODT)

Serial Presence Detect with E²PROM

Based on standard reference layouts Raw Cards

“F”, “G” and “H”

•

All speed grades faster than DDR2-400 comply with

DDR2-400 timing specifications as well.

Registered DIMM with Parity bit for address and

control bus

•

RDIMM with parity bit Dimensions (nominal):

30.00 mm high, 133.35 mm wide

RoHS compliant products¹⁾

Table 1

Performance for PC2–5300–555

Product Type Speed Code

Speed Grade

–3S

Unit

PC2–5300 5–5–5

—

Max. Clock Frequency

@CL5

@CL4

@CL3

f_CK5

f_CK4

f_CK3

t_RCD

t_RP

333

266

200

15

MHz

ns

Min. RAS-CAS-Delay

Min. Row Precharge Time

Min. Row Active Time

Min. Row Cycle Time

15

ns

t_RAS

t_RC

45

ns

60

ns

1) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic

equipment as defined in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January

2003. These substances include mercury, lead, cadmium, hexavalent chromium, polybrominated biphenyls and

polybrominated biphenyl ethers.

Data Sheet

5

Rev. 1.0, 2006-03

02102006-0OKM-JLO7

HYS72T[32/64]xxxHP–[3S/3.7]–A

Registered DDR2 SDRAM Modules

OverviewFeatures

Table 2

Performance for PC2–4200–444

Product Type Speed Code

Speed Grade

–3.7

Unit

PC2–4200 4–4–4

—

Max. Clock Frequency

@CL5

@CL4

@CL3

f_CK5

f_CK4

f_CK3

t_RCD

t_RP

266

200

15

MHz

ns

Min. RAS-CAS-Delay

Min. Row Precharge Time

Min. Row Active Time

Min. Row Cycle Time

15

ns

t_RAS

t_RC

45

ns

60

ns

Table 3

Performance for PC2–3200–333

Product Type Speed Code

Speed Grade

–5

Units

PC2–3200 3–3–3

200

—

Max. Clock Frequency

@CL5

@CL4

@CL3

f_CK5

f_CK4

f_CK3

t_RCD

t_RP

MHz

ns

200

15

Min. RAS-CAS-Delay

Min. Row Precharge Time

Min. Row Active Time

Min. Row Cycle Time

15

ns

t_RAS

t_RC

40

ns

55

ns

Data Sheet

6

Rev. 1.0, 2006-03

02102006-0OKM-JLO7

HYS72T[32/64]xxxHP–[3S/3.7]–A

Registered DDR2 SDRAM Modules

OverviewDescription

1.2

Description

The INFINEON HYS72T[32/64]xxxHP–[3S/3.7]–A module family are Registered DIMM (RDIMM with parity) with

30.00 mm height based on DDR2 technology. DIMMs are available as ECC modules in 32M × 72 (256 Mbyte) and

64M x 72 (512 MByte) organization and density, intended for mounting into 240-Pin connector sockets.

The memory array is designed with 256-Mbit Double-Data-Rate-Two (DDR2) Synchronous DRAMs. All control

and address signals are re-driven on the DIMM using register devices and a PLL for the clock distribution. This

reduces capacitive loading to the system bus, but adds one cycle to the SDRAM timing. Decoupling capacitors

are mounted on the PCB board. The DIMMs feature serial presence detect based on a serial E²PROM device

using the 2-pin I²C protocol. The first 128 bytes are programmed with configuration data and the second 128 bytes

are available to the customer.

Table 4

Ordering Information for RoHS Compliant Products

Product Type¹⁾

Compliance Code²⁾

Description SDRAM Technology

PC2-5300

HYS72T32000HP–3S–A

HYS72T64001HP–3S–A

HYS72T64020HP–3S–A

PC2-4200

256MB 1R×8 PC2–5300P–555–12–F0

512MB 1R×4 PC2–5300P–555–12–H0

512MB 2R×8 PC2–5300P–555–12–G0

1 Rank, ECC 256 Mbit (×8)

1 Rank, ECC 256 Mbit (×4)

2 Rank, ECC 256 Mbit (×8)

HYS72T32000HP–3.7–A

HYS72T64001HP–3.7–A

HYS72T64020HP–3.7–A

256MB 1R×8 PC2–4200P–444–12–F0

512MB 1R×4 PC2–4200P–444–12–H0

512MB 2R×8 PC2–4200P–444–12–G0

1 Rank, ECC 256 Mbit (×8)

1 Rank, ECC 256 Mbit (×4)

2 Rank, ECC 256 Mbit (×8)

1) All Product Types end with a place code, designating the silicon die revision. Example: HYS72T64020HP–3.7–A, indicating

Rev. “A” dies are used for DDR2 SDRAM components. For all INFINEON DDR2 module and component nomenclature see

Chapter 6 of this data sheet.

2) The Compliance Code is printed on the module label and describes the speed grade, for example “PC2–4200P–444–

12–G0”, where 4200P means Very Low Profile Registered DIMM modules with 4.26 GB/sec Module Bandwidth and “444-

12” means Column Address Strobe (CAS) latency = 4, Row Column Delay (RCD) latency = 4 and Row Precharge (RP)

latency = 4 using the latest JEDEC SPD Revision 1.2 and produced on the Raw Card “G”

Table 5

Address Format

DIMM

Module

Memory ECC/

# of

# of row/bank/columns bits Raw Card

Density

Organization

Ranks

Non-ECC

SDRAMs

256 MB

512 MB

32M × 72

64M × 72

1

2

ECC

9

13/2/10

13/2/11

13/2/10

F

18

H

G

Table 6

Components on Modules ¹⁾

Product Type²⁾

DRAM Components²⁾

HYB18T256800AF

HYB18T256400AF

HYB18T256800AF

DRAM Density

256 Mbit

DRAM Organization

32M × 8

HYS72T32000HP

HYS72T64001HP

HYS72T64020HP

256 Mbit

64M × 4

256Mbit

32M × 8

1) For a detailed description of all available functions of the DRAM components on these modules see the component data

sheet.

2) Green Product

Data Sheet

7

Rev. 1.0, 2006-03

02102006-0OKM-JLO7

HYS72T[32/64]xxxHP–[3S/3.7]–A

Registered DDR2 SDRAM Modules

Pin Configuration and Block DiagramsPin Configuration

2

Pin Configuration and Block Diagrams

2.1

Pin Configuration

The pin configuration of the Registered DDR2 SDRAM explained in Table 8 and Table 9 respectively. The pin

DIMM is listed by function in Table 7 (240 pins). The numbering is depicted in Figure 1.

abbreviations used in columns Pin and Buffer Type are

Table 7

Pin Configuration of RDIMM

Pin or Ball No.

Name

Buffer Function

Type Type

Clock Signals

185

186

CK0

I

SSTL

Clock Signal CK0, Complementary Clock Signal CK0

The system clock inputs. All address and command lines are

sampled on the cross point of the rising edge of CK and the

falling edge of CK. A Delay Locked Loop (DLL) circuit is driven

from the clock inputs and output timing for read operations is

synchronized to the input clock.

52

CKE0

CKE1

I

SSTL

Clock Enables 1:0

Activates the DDR2 SDRAM CK signal when HIGH and

deactivates the CK signal when LOW. By deactivating the

clocks, CKE0 initiates the Power Down Mode or the Self

Refresh Mode.

171

Note: 2-Ranks module

Not Connected

NC

—

Note: 1-Rank module

Control Signals

193

76

S0

S1

I

SSTL

Chip Select Rank 1:0

Enables the associated DDR2 SDRAM command decoder

when LOW and disables the command decoder when HIGH.

When the command decoder is disabled, new commands are

ignored but previous operations continue. Rank 0 is selected by

S0; Rank 1 is selected by S1. The input signals also disable all

outputs (except CKE and ODT) of the register(s) on the DIMM

when both inputs are high. When S is HIGH, all register outputs

(except CK, ODT and Chip select) remain in the previous state.

Note: 2-Ranks module

Not Connected

NC

—

Note: 1-Rank module

192

74

RAS

CAS

WE

I

SSTL

Row Address Strobe (RAS), Column Address Strobe

(CAS), Write Enable (WE)

When sampled at the cross point of the rising edge of CK, and

falling edge of CK, RAS, CAS and WE define the operation to

be executed by the SDRAM.

73

Data Sheet

8

Rev. 1.0, 2006-03

02102006-0OKM-JLO7

HYS72T[32/64]xxxHP–[3S/3.7]–A

Registered DDR2 SDRAM Modules

Pin Configuration and Block DiagramsPin Configuration

Table 7

Pin Configuration of RDIMM (cont’d)

Pin or Ball No.

Name

Buffer Function

Type Type

18

RESET

I

CMOS Register Reset

The RESET pin is connected to the RST pin on the register and

to the OE pin on the PLL. When LOW, all register outputs will

be driven LOW and the PLL clocks to the DRAMs and the

register(s) will be set to low-level. The PLL will remain

synchronized with the input clock.

Address Signals

71

BA0

BA1

BA2

I

SSTL

Bank Address Bus 1:0

Selects internal SDRAM memory bank

190

54

Bank Address Bus 2

Greater than 512Mb DDR2 SDRAMS

NC

I

SSTL

Not Connected

Less than 1Gb DDR2 SDRAMS

188

183

63

A0

I

SSTL

Address Bus 12:0, Address Signal 10/AutoPrecharge

During a Bank Activate command cycle, defines the row

address when sampled at the crosspoint of the rising edge of

CK and falling edge of CK. During a Read or Write command

cycle, defines the column address when sampled at the cross

point of the rising edge of CK and falling edge of CK. In addition

to the column address, AP is used to invoke autoprecharge

operation at the end of the burst read or write cycle. If AP is

HIGH, autoprecharge is selected and BA[1:0] defines the bank

to be precharged. If AP is LOW, autoprecharge is disabled.

During a Precharge command cycle, AP is used in conjunction

with BA[1:0] to control which bank(s) to precharge. If AP is

HIGH, all banks will be precharged regardless of the state of

BA[1:0] inputs. If AP is LOW, then BA[1:0] are used to define

which bank to precharge.

A1

A2

182

61

A3

A4

60

A5

180

58

A6

A7

179

177

70

A8

A9

A10

AP

A11

A12

A13

57

176

196

Address Signal 13

Note: modules based on ×4, ×8

Not Connected

NC

A14

NC

I

—

Note: modules based on ×16

Address Signal 14

174

SSTL

—

Note: 2 Gbit based module

Not Connected

NC

Note: 1 Gbit based module or smaller

Data Sheet

9

Rev. 1.0, 2006-03

02102006-0OKM-JLO7

HYS72T[32/64]xxxHP–[3S/3.7]–A

Registered DDR2 SDRAM Modules

Pin Configuration and Block DiagramsPin Configuration

Table 7

Pin Configuration of RDIMM (cont’d)

Pin or Ball No.

Name

Buffer Function

Type Type

Data Signals

3

DQ0

I/O

SSTL

Data Bus 63:0

Data Input/Output pins

4

DQ1

9

DQ2

10

DQ3

122

123

128

129

12

DQ4

DQ5

DQ6

DQ7

DQ8

13

DQ9

21

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

DQ24

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

DQ32

DQ33

DQ34

DQ35

DQ36

DQ37

DQ38

22

131

132

140

141

24

25

30

31

143

144

149

150

33

34

39

40

152

153

158

159

80

81

86

87

199

200

205

Data Sheet

10

Rev. 1.0, 2006-03

02102006-0OKM-JLO7

HYS72T[32/64]xxxHP–[3S/3.7]–A

Registered DDR2 SDRAM Modules

Pin Configuration and Block DiagramsPin Configuration

Table 7

Pin Configuration of RDIMM (cont’d)

Pin or Ball No.

Name

Buffer Function

Type Type

206

89

DQ39

DQ40

DQ41

DQ42

DQ43

DQ44

DQ45

DQ46

DQ47

DQ48

DQ49

DQ50

DQ51

DQ52

DQ53

DQ54

DQ55

DQ56

DQ57

DQ58

DQ59

DQ60

DQ61

DQ62

DQ63

I/O

SSTL

Data Bus 63:0

90

95

96

208

209

214

215

98

99

107

108

217

218

226

227

110

111

116

117

229

230

235

236

Check Bits

42

CB0

CB1

CB2

CB3

CB4

CB5

CB6

CB7

I/O

SSTL

Check Bits 7:0

Check Bit Input / Output pins

43

Note: NC on Non-ECC module

48

49

161

162

167

168

Data Sheet

11

Rev. 1.0, 2006-03

02102006-0OKM-JLO7

HYS72T[32/64]xxxHP–[3S/3.7]–A

Registered DDR2 SDRAM Modules

Pin Configuration and Block DiagramsPin Configuration

Table 7

Pin Configuration of RDIMM (cont’d)

Pin or Ball No.

Name

Buffer Function

Type Type

Data Strobe Bus

7

DQS0

DQS1

DQS2

DQS3

DQS4

DQS5

DQS6

DQS7

DQS8

DQS9

DQS10

DQS11

DQS12

DQS13

DQS14

DQS15

DQS16

DQS17

I/O

SSTL

Data Strobes 17:0

The data strobes, associated with one data byte, sourced with

data transfers. In Write mode, the data strobe is sourced by the

controller and is centered in the data window. In Read mode the

data strobe is sourced by the DDR2 SDRAM and is sent at the

leading edge of the data window. DQS signals are

complements, and timing is relative to the crosspoint of

respective DQS and DQS. If the module is to be operated in

single ended strobe mode, all DQS signals must be tied on the

system board to V_SSthrough a 20 ohm to 10 Kohm resistor and

DDR2 SDRAM mode registers programmed appropriately.

6

16

15

28

27

37

36

84

83

Note: See block diagram for corresponding DQ signals

93

92

105

104

114

113

46

45

125

126

134

135

146

147

155

156

202

203

211

212

223

224

232

233

164

165

Data Sheet

12

Rev. 1.0, 2006-03

02102006-0OKM-JLO7

HYS72T[32/64]xxxHP–[3S/3.7]–A

Registered DDR2 SDRAM Modules

Pin Configuration and Block DiagramsPin Configuration

Table 7

Pin Configuration of RDIMM (cont’d)

Pin or Ball No.

Name

Buffer Function

Type Type

Data Mask

125

DM0

DM1

DM2

DM3

DM4

DM5

DM6

DM7

DM8

I

SSTL

Data Masks 7:0

The data write masks, associated with one data byte. In Write

mode, DM operates as a byte mask by allowing input data to be

written if it is LOW but blocks the write operation if it is HIGH. In

Read mode, DM lines have no effect.

134

146

155

202

Note: ×8 based module

211

223

232

164

EEPROM

120

SCL

SDA

I

CMOS Serial Bus Clock

This signal is used to clock data into and out of the SPD

EEPROM.

119

I/O

OD

Serial Bus Data

This is a bidirectional pin used to transfer data into or out of the

SPD EEPROM. A resistor must be connected from SDA to

V

_DDSPDon the motherboard to act as a pull-up.

239

240

101

Parity

55

SA0

SA1

SA2

I

CMOS Serial Address Select Bus 2:0

These signals are tied at the system planar to either V_SSor

_DDSPDto configure the serial SPD EEPROM address range

CMOS

V

ERR_OUT

PAR_IN

O

I

CMOS Parity bits

CMOS

Note: Only for modules with parity bit for address and control

bus. Not connected on non-parity registered modules.

Power Supplies

1

V_REF

AI

—

I/O Reference Voltage

Reference voltage for the SSTL-18 inputs.

238

V_DDSPD

PWR —

EEPROM Power Supply

Serial EEPROM positive power supply, wired to a separated

power pin at the connector which supports from 1.7 Volt to 3.6

Volt.

51, 56, 62, 72, 75, V_DDQ

78, 170, 175,,

181, 191, 194

PWR —

I/O Driver Power Supply

Power and ground for the DDR SDRAM

53, 59, 64, 67, 69, V_DD

172, 178, 184,,

Power Supply

Power and ground for the DDR SDRAM

187, 189, 197

Data Sheet

13

Rev. 1.0, 2006-03

02102006-0OKM-JLO7

HYS72T[32/64]xxxHP–[3S/3.7]–A

Registered DDR2 SDRAM Modules

Pin Configuration and Block DiagramsPin Configuration

Table 7

Pin Configuration of RDIMM (cont’d)

Name Pin Buffer Function

Pin or Ball No.

Type Type

2, 5, 8, 11, 14, 17, V_SS

20, 23, 26, 29, 32,

35, 38, 41, 44, 47,

50, 65, 66, 79, 82,

85, 88, 91, 94, 97,

100, 103, 106,

109, 112, 115,

118, 121, 124,

127, 130, 133,

136, 139, 142,

145, 148, 151,

154, 157, 160,

163, 166, 169,

198, 201, 204,

207, 210, 213,

216, 219, 222,

225, 228, 231,

234, 237

GND —

Ground Plane

Power and ground for the DDR SDRAM

Other Pins

19, 55, 68, 102,

137, 138, 173,

220, 221

NC

—

Not connected

Pins not connected on Infineon RDIMM’s

195

77

ODT0

ODT1

I

SSTL

On-Die Termination Control 1:0

Asserts on-die termination for DQ, DM, DQS, and DQS signals

if enabled via the DDR2 SDRAM mode register.

Note: 2-Ranks module

NC

—

Note: 1-Rank modules

Table 8

Abbreviations for Buffer Type

Description

Abbreviation

SSTL

Serial Stub Terminated Logic (SSTL_18)

CMOS Levels

CMOS

OD

Open Drain. The corresponding pin has 2 operational states, active low and

tristate, and allows multiple devices to share as a wire-OR.

Data Sheet

14

Rev. 1.0, 2006-03

02102006-0OKM-JLO7

HYS72T[32/64]xxxHP–[3S/3.7]–A

Registered DDR2 SDRAM Modules

Pin Configuration and Block DiagramsPin Configuration

Table 9

Abbreviations for Pin Type

Abbreviation

Description

I

Standard input-only pin. Digital levels.

Output. Digital levels.

I/O is a bidirectional input/output signal.

Input. Analog levels.

Power

O

I/O

AI

PWR

GND

NU

NC

Ground

Not Usable

Not Connected

Data Sheet

15

Rev. 1.0, 2006-03

02102006-0OKM-JLO7

ꢃ

HYS72T[32/64]xxxHP–[3S/3.7]–A

Registered DDR2 SDRAM Modules

Pin Configuration and Block DiagramsPin Configuration

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Figure 1

Pin Configuration for RDIMM (240 pins)

Data Sheet

16

Rev. 1.0, 2006-03

02102006-0OKM-JLO7

HYS72T[32/64]xxxHP–[3S/3.7]–A

Registered DDR2 SDRAM Modules

Pin Configuration and Block DiagramsBlock Diagram

2.2

Block Diagram

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Figure 2

Notes

Block Diagram RDIMM (x72, 1Rank, x8)

1. Unless otherwise noted, resistors are 22 Ω ± 5 %

2. S0 connects to DCS and V_DDconnects to CSR on the register.

Data Sheet

17

Rev. 1.0, 2006-03

02102006-0OKM-JLO7

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&%ꢅ

ꢄ,ꢌ2ꢄꢅ

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ꢄ,ꢌ2ꢄꢉ

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ꢄ,ꢌ2ꢄꢂ

&%ꢂ

ꢄ,ꢌ2ꢄꢂ

03%7ꢀꢁꢇꢀ

Figure 3

Notes

Block Diagram RDIMM (x72, 2Ranks, x8)

1. Unless otherwise noted, resistors are 22 Ω ± 5 %

2. RS0 and RS1 alternate between the back and front sides of the DIMM.

Data Sheet

18

Rev. 1.0, 2006-03

02102006-0OKM-JLO7

HYS72T[32/64]xxxHP–[3S/3.7]–A

Registered DDR2 SDRAM Modules

Pin Configuration and Block DiagramsBlock Diagram

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Figure 4

Block Diagram RDIMM (x72, 1Rank, x4)

Notes

1. Unless otherwise noted, resistors are 22 Ω ± 5 %

2. S0 connects to DCS of register1 and CSR of register2.

3. CSR of register1 and DCS of register2 connects to V_DD.

4. RESET, PCK7 and PCK7 connect to both registers.

Data Sheet

19

Rev. 1.0, 2006-03

02102006-0OKM-JLO7

HYS72T[32/64]xxxHP–[3S/3.7]–A

Registered DDR2 SDRAM Modules

Electrical CharacteristicsAbsolute Maximum Ratings

3

Electrical Characteristics

3.1

Absolute Maximum Ratings

Caution is needed not to exceed abolute maximum ratings of the DRAM device listed in Table 10 at any time.

Table 10

Absolute Maximum Ratings

Parameter

Symbol

Values

Min.

–0.5

–1.0

–0.5

5

Unit

Max.

2.3

95

Voltage on any pins relative to V_SS

Voltage on V_DDrelative to V_SS

V_IN, V_OUT

V_DD

V

%

Voltage on V_DDQrelative to V_SS

Storage Humidity (without condensation)

V_DDQ

H_STG

Attention: Stresses above the max. values listed here may cause permanent damage to the device.

Exposure to absolute maximum rating conditions for extended periods may affect device

reliability. Maximum ratings are absolute ratings; exceeding only one of these values may

cause irreversible damage to the integrated circuit.

3.2

DC Operating Conditions

Table 11

Operating Conditions

Parameter

Symbol

Values

Min.

0

Unit

Notes

Max.

+65

Operating temperature (ambient)

DRAM Case Temperature

T_OPR

T_CASE

T_STG

°C

kPa

%

1)2)3)4)

5)

0

+95

Storage Temperature

– 50

+69

10

+100

+105

90

Barometric Pressure (operating & storage)

Operating Humidity (relative)

PBar

H_OPR

1) DRAM Component Case Temperature is the surface temperature in the center on the top side of any of the DRAMs.

2) Within the DRAM Component Case Temperature Range all DRAM specifications will be supported

3) Above 85 °C DRAM Case Temperature the Auto-Refresh command interval has to be reduced to t_REFI= 3.9 µs

4)When operating this product in the 85 °C to 95 °C T_CASEtemperature range, the High Temperature Self Refresh

has to be enabled by setting EMR(2) bit A7 to 1. When the High Temperature Self Refresh is enabled there is an

increase of I_DD6by approximately 50%.

5) Up to 3000 m.

Data Sheet

20

Rev. 1.0, 2006-03

02102006-0OKM-JLO7

HYS72T[32/64]xxxHP–[3S/3.7]–A

Registered DDR2 SDRAM Modules

Electrical CharacteristicsDC Operating Conditions

Table 12

Supply Voltage Levels and DC Operating Conditions

Parameter

Symbol

Values

Min.

Unit

Notes

Typ.

Max.

1.9

Device Supply Voltage

Output Supply Voltage

Input Reference Voltage

SPD Supply Voltage

V_DD

1.7

1.8

V

1)

2)

V_DDQ

V_REF

1.7

1.8

1.9

V

0.49 × V_DDQ

1.7

0.5 × V_DDQ

0.51 × V_DDQ

3.6

V

V_DDSPD

V_IH(DC)

V_{IL (DC}

I_L

—

V

DC Input Logic High

V

_REF+ 0.125

V

5

_DDQ+ 0.3

V

DC Input Logic Low

)

– 0.30

– 5

_REF– 0.125

V

3)

In / Output Leakage Current

µA

1) Under all conditions, V_DDQmust be less than or equal to V_DD

2) Peak to peak AC noise on V_REFmay not exceed ± 2% V_REF(DC).V_REFis also expected to track noise in V_DDQ

3) Input voltage for any connector pin under test of 0 V ≤ V_IN≤ V_DDQ+ 0.3 V; all other pins at 0 V. Current is per pin

.

Data Sheet

21

Rev. 1.0, 2006-03

02102006-0OKM-JLO7

HYS72T[32/64]xxxHP–[3S/3.7]–A

Registered DDR2 SDRAM Modules

Electrical CharacteristicsAC Characteristics

3.3

AC Characteristics

3.3.1

Speed Grades Definitions

Table 13

Speed Grade Definition Speed Bins for DDR2–667D

Speed Grade

DDR2–667

Unit

Notes

IFX Sort Name

CAS-RCD-RP latencies

Parameter

–3S

5–5–5

Min.

5

t_CK

—

ns

Symbol

t_CK

Max.

8

1)2)3)4)

1)2)3)4)5)

1)2)3)4)

Clock Frequency

@ CL = 3

@ CL = 4

@ CL = 5

t_CK

3.75

3

8

t_CK

8

Row Active Time

Row Cycle Time

RAS-CAS-Delay

Row Precharge Time

t_RAS

t_RC

t_RCD

t_RP

45

70000

—

60

15

—

15

—

1) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a

differential Slew Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. Timings are

further guaranteed for normal OCD drive strength (EMRS(1) A1 = 0) only.

2) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS/DQS,

RDQS/RDQS, input reference level is the crosspoint when in differential strobe mode

3) Inputs are not recognized as valid until V_REFstabilizes. During the period before V_REFstabilizes, CKE = 0.2 x V_DDQis

recognized as low.

4) The output timing reference voltage level is V_TT.

5) t_RAS.MAXis calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is

equal to 9 x t_REFI

.

Data Sheet

22

Rev. 1.0, 2006-03

02102006-0OKM-JLO7

HYS72T[32/64]xxxHP–[3S/3.7]–A

Registered DDR2 SDRAM Modules

Electrical CharacteristicsAC Characteristics

Table 14

Speed Grade Definition Speed Bins for DDR2–533C

Speed Grade

DDR2–533

–3.7

Unit

Note

IFX Sort Name

CAS-RCD-RP latencies

Parameter

4–4–4

t_CK

—

ns

Symbol

t_CK

Min.

5

Max.

1)2)3)4)

1)2)3)4)5)

1)2)3)4)

Clock Frequency

@ CL = 3

@ CL = 4

@ CL = 5

8

t_CK

3.75

45

8

t_CK

8

Row Active Time

Row Cycle Time

RAS-CAS-Delay

Row Precharge Time

t_RAS

t_RC

t_RCD

t_RP

70000

—

60

15

—

15

—

1) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a

differential Slew Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. Timings are

further guaranteed for normal OCD drive strength (EMRS(1) A1 = 0) only.

2) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS / DQS,

RDQS / RDQS, input reference level is the crosspoint when in differential strobe mode

3) Inputs are not recognized as valid until V_REFstabilizes. During the period before V_REFstabilizes, CKE = 0.2 x V_DDQis

recognized as low.

4) The output timing reference voltage level is V_TT.

5) t_RAS.MAXis calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is

equal to 9 x t_REFI

.

Table 15

Speed Grade Definition Speed Bins for DDR2-400B

Speed Grade

DDR2–400B

–5

Unit

Note

IFX Sort Name

CAS-RCD-RP latencies

Parameter

3–3–3

t_CK

—

ns

Symbol

t_CK

Min.

5

Max.

1)2)3)4)

1)2)3)4)5)

1)2)3)4)

Clock Frequency

@ CL = 3

@ CL = 4

@ CL = 5

8

t_CK

5

8

t_CK

5

8

Row Active Time

Row Cycle Time

RAS-CAS-Delay

Row Precharge Time

t_RAS

t_RC

t_RCD

t_RP

40

55

15

70000

—

1) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a

differential Slew Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. Timings are

further guaranteed for normal OCD drive strength (EMRS(1) A1 = 0) only.

2) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS / DQS,

RDQS / RDQS, input reference level is the crosspoint when in differential strobe mode

3) Inputs are not recognized as valid until V_REFstabilizes. During the period before V_REFstabilizes, CKE = 0.2 x V_DDQis

recognized as low.

4) The output timing reference voltage level is V_TT.

5) t_RAS.MAXis calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is

equal to 9 x t_REFI

.

Data Sheet

23

Rev. 1.0, 2006-03

02102006-0OKM-JLO7

HYS72T[32/64]xxxHP–[3S/3.7]–A

Registered DDR2 SDRAM Modules

Electrical CharacteristicsAC Characteristics

3.3.2

AC Timing Parameters

Table 16

Timing Parameter by Speed Grade - DDR2-667

Parameter

Symbol

DDR2-667

Min.

Unit Note

1)2)3)4)5)6)

Max.

7)

DQ output access time from CK / CK

CAS A to CAS B command period

CK, CK high-level width

t_AC

t_CCD

t_CH

t_CKE

t_CL

t_DAL

t_DELAY

–450

2

+450

—

ps

t_CK

ns

0.45

3

0.55

—

CKE minimum high and low pulse width

CK, CK low-level width

0.45

WR + t_RP

0.55

—

Auto-Precharge write recovery + precharge time

Minimum time clocks remain ON after CKE

asynchronously drops LOW

t_IS+ t_CK+ t_IH––

DQ and DM input hold time (differential data strobe)

DQ and DM input pulse width (each input)

DQS output access time from CK / CK

t_DH(base)

t_DIPW

175

––

ps

t_CK

ps

t_CK

ps

0.35

–400

0.35

240

—

t_DQSCK

t_DQSL,H

t_DQSQ

t_DQSS

t_DS(base)

t_DSH

+400

—

DQS input low (high) pulse width (write cycle)

DQS-DQ skew (for DQS & associated DQ signals)

Write command to 1st DQS latching transition

DQ and DM input setup time (differential data strobe)

DQS falling edge hold time from CK (write cycle)

DQS falling edge to CK setup time (write cycle)

Clock half period

—

– 0.25

100

+ 0.25 t_CK

—

ps

0.2

t_CK

t_DSS

0.2

t_HP

MIN. (t_CL,t_CH)

— t_AC.MAXps

Data-out high-impedance time from CK / CK

Address and control input hold time

t_HZ

t_IH(base)

t_IPW

275

—

ps

Address and control input pulse width

(each input)

0.6

t_CK

Address and control input setup time

DQ low-impedance time from CK / CK

DQS low-impedance from CK / CK

Mode register set command cycle time

OCD drive mode output delay

t_IS(base)

t_LZ(DQ)

t_LZ(DQS)

t_MRD

200

—

ps

2 ξ t_AC.MIN

t_AC.MAXps

t_AC.MIN

2

0

—

t_CK

t_OIT

12

—

ns

Data output hold time from DQS

Data hold skew factor

t_QH

t_HP– t_QHS

t_QHS

340

—

ps

µs

ns

t_CK

ns

8)

9)

Average periodic refresh Interval

t_REFI

7.8

3.9

—

Auto-Refresh to Active/Auto-Refresh command period t_RFC

75

Precharge-All (4 banks) command period

Read preamble

t_RP

t

_RP+ 1t_CK

—

t_RPRE

t_RPST

t_RRD

0.9

0.40

7.5

10

1.1

0.60

—

Read postamble

10)

11)

Active bank A to Active bank B command period

—

Data Sheet

24

Rev. 1.0, 2006-03

02102006-0OKM-JLO7

HYS72T[32/64]xxxHP–[3S/3.7]–A

Registered DDR2 SDRAM Modules

Electrical CharacteristicsAC Characteristics

Table 16

Timing Parameter by Speed Grade - DDR2-667

Symbol

Parameter

DDR2-667

Min.

Unit Note

1)2)3)4)5)6)

Max.

7)

Internal Read to Precharge command delay

Write preamble

t_RTP

7.5

—

ns

t_WPRE

t_WPST

t_WR

0.35

0.40

15

—

t_CK

ns

Write postamble

0.60

—

Write recovery time for write without Auto-Precharge

Write recovery time for write with Auto-Precharge

Internal Write to Read command delay

WR

t

_WR/t_CK

t_CK

ns

t_WTR

t_XARD

7.5

2

—

Exit power down to any valid command

(other than NOP or Deselect)

t_CK

Exit active power-down mode to Read command (slow t_XARDS

exit, lower power)

7 – AL

2

—

t_CK

Exit precharge power-down to any valid command (other t_XP

than NOP or Deselect)

Exit Self-Refresh to non-Read command

Exit Self-Refresh to Read command

t_XSNR

t_XSRD

t

_RFC+10

—

ns

200

t_CK

1) For details and notes see the relevant INFINEON component data sheet

2) VDDQ = 1.8 V ± 0.1 V; VDD = 1.8 V ± 0.1 V. See notes ^4)5)6)7)

3) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be

powered down and then restarted through the specified initialization sequence before normal operation can continue.

4) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a

differential Slew Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode.

5) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross.

The DQS/DQS, RDQS/RDQS, input reference level is the crosspoint when in differential strobe mode

6) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is

recognized as low.

7) The output timing reference voltage level is VTT.

8) 0 ≤ T_CASE≤ 85 °C

9) 85 °C < T_CASE≤ 95 °C

10) x4 & x8

11) x16

Data Sheet

25

Rev. 1.0, 2006-03

02102006-0OKM-JLO7

HYS72T[32/64]xxxHP–[3S/3.7]–A

Registered DDR2 SDRAM Modules

Electrical CharacteristicsAC Characteristics

Table 17

Timing Parameter by Speed Grade - DDR2-533

Symbol

Parameter

DDR2–533

Min.

Unit Note¹⁾²⁾

3)4)5)6)7)

Max.

+500

—

DQ output access time from CK / CK

CAS A to CAS B command period

CK, CK high-level width

t_AC

–500

2

ps

t_CCD

t_CH

t_CKE

t_CL

t_DAL

t_DELAY

t_CK

ns

0.45

0.55

—

CKE minimum high and low pulse width

CK, CK low-level width

3

0.45

0.55

—

Auto-Precharge write recovery + precharge time

WR + t_RP

Minimum time clocks remain ON after CKE

asynchronously drops LOW

t_IS+ t_CK+ t_IH––

DQ and DM input hold time (differential data

strobe)

t_DH(base)

225

–25

––

—

ps

DQ and DM input hold time (single ended data

strobe)

t_DH1(base)

DQ and DM input pulse width (each input)

DQS output access time from CK / CK

DQS input low (high) pulse width (write cycle)

t_DIPW

0.35

–450

0.35

—

t_CK

ps

t_CK

ps

t_CK

ps

t_DQSCK

t_DQSL,H

+450

—

DQS-DQ skew (for DQS & associated DQ signals) t_DQSQ

300

+0.25

—

Write command to 1st DQS latching transition

t_DQSS

–0.25

100

DQ and DM input setup time (differential data

strobe)

t_DS(base)

DQ and DM input setup time (single ended data

strobe)

t

_DS1(base)

–25

—

ps

DQS falling edge hold time from CK (write cycle) t_DSH

0.2

—

t_CK

DQS falling edge to CK setup time (write cycle)

Clock half period

t_DSS

0.2

t_HP

MIN. (t_CL,t_CH)

Data-out high-impedance time from CK / CK

Address and control input hold time

t_HZ

—

t_AC.MAX

ps

t_CK

t_IH(base)

t_IPW

375

0.6

—

Address and control input pulse width

(each input)

—

Address and control input setup time

DQ low-impedance time from CK / CK

DQS low-impedance from CK / CK

Mode register set command cycle time

OCD drive mode output delay

t_IS(base)

t_LZ(DQ)

t_LZ(DQS)

t_MRD

250

—

ps

t_CK

ns

2 ° t_AC.MIN

t_AC.MAX

—

t_AC.MIN

2

0

t_OIT

12

Data output hold time from DQS

Data hold skew factor

t_QH

t

_HP– t_QHS

—

t_QHS

—

75

400

7.8

ps

8)

Average periodic refresh Interval

t_REFI

µs

9)

3.9

µs

Auto-Refresh to Active/Auto-Refresh command

period

t_RFC

t_RP

—

ns

Precharge-All (4 banks) command period

t

_RP+ 1t_CK

—

ns

Data Sheet

26

Rev. 1.0, 2006-03

02102006-0OKM-JLO7

HYS72T[32/64]xxxHP–[3S/3.7]–A

Registered DDR2 SDRAM Modules

Electrical CharacteristicsAC Characteristics

Table 17

Timing Parameter by Speed Grade - DDR2-533 (cont’d)

Parameter

Symbol

DDR2–533

Min.

0.9

Unit Note¹⁾²⁾

3)4)5)6)7)

Max.

1.1

0.60

—

Read preamble

Read postamble

t_RPRE

t_RPST

t_CK

0.40

7.5

10)

Active bank A to Active bank B command period t_RRD

ns

1)11)

10

—

ns

Internal Read to Precharge command delay

Write preamble

t_RTP

7.5

—

ns

t_CK

ns

t_WPRE

t_WPST

t_WR

0.35xt_CK

0.40

15

—

Write postamble

0.60

—

Write recovery time for write without Auto-

Precharge

Write recovery time for write with Auto-Precharge WR

t

_WR/t_CK

t_CK

ns

Internal Write to Read command delay

t_WTR

7.5

2

—

Exit power down to any valid command

(other than NOP or Deselect)

t_XARD

t_CK

Exit active power-down mode to Read command t_XARDS

(slow exit, lower power)

6 – AL

2

—

t_CK

Exit precharge power-down to any valid command t_XP

(other than NOP or Deselect)

Exit Self-Refresh to non-Read command

Exit Self-Refresh to Read command

t_XSNR

t_XSRD

t

_RFC+10

—

ns

200

t_CK

1) For details and notes see the relevant INFINEON component data sheet

2) V_DDQ= 1.8 V ± 0.1 V; V_DD= 1.8 V ± 0.1 V. See notes ^4)5)6)7)

3) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be

powered down and then restarted through the specified initialization sequence before normal operation can continue.

4) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a

differential Slew Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode.

5) The CK / CK input reference level (for timing reference to CK / CK) is the point at which CK and CK cross. The DQS / DQS,

RDQS/ RDQS, input reference level is the crosspoint when in differential strobe mode

6) Inputs are not recognized as valid until V_REFstabilizes. During the period before V_REFstabilizes, CKE = 0.2 x V_DDQis

recognized as low.

7) The output timing reference voltage level is V_TT.

8) 0 ≤ T_CASE≤ 85 °C

9) 85 < T_CASE≤ 95 °C

10) x4 & x8

11) x16

Data Sheet

27

Rev. 1.0, 2006-03

02102006-0OKM-JLO7

HYS72T[32/64]xxxHP–[3S/3.7]–A

Registered DDR2 SDRAM Modules

Electrical CharacteristicsAC Characteristics

Table 18

Timing Parameter by Speed Grade - DDR2-400

Symbol

Parameter

DDR2-400

Min.

Unit Note

1)2)3)4)5)6)7)

Max.

+600

—

DQ output access time from CK / CK

CAS A to CAS B command period

CK, CK high-level width

t_AC

t_CCD

t_CH

t_CKE

t_CL

t_DAL

t_DELAY

–600

2

ps

t_CK

ns

0.45

0.55

—

CKE minimum high and low pulse width

CK, CK low-level width

3

0.45

0.55

—

Auto-Precharge write recovery + precharge time

WR + t_RP

Minimum time clocks remain ON after CKE

asynchronously drops LOW

t_IS+ t_CK+ t_IH––

DQ and DM input hold time (differential data strobe)

DQ and DM input hold time (single-ended strobe)

DQ and DM input pulse width (each input)

DQS output access time from CK / CK

t_DH(base)

275

––

ps

t_CK

ps

t_CK

ps

t_CK

ps

t_CK

t

_DH1(base) 25

––

t_DIPW

0.35

–500

0.35

—

t_DQSCK

t_DQSL,H

t_DQSQ

t_DQSS

t_DS(base)

+500

—

DQS input low (high) pulse width (write cycle)

DQS-DQ skew (for DQS & associated DQ signals)

Write command to 1st DQS latching transition

DQ and DM input setup time (differential data strobe)

DQ and DM input setup time (single-ended strobe)

DQS falling edge hold time from CK (write cycle)

DQS falling edge to CK setup time (write cycle)

Clock half period

350

+0.25

—

–0.25

150

t

_DS1(base) 25

—

t_DSH

t_DSS

t_HP

0.2

—

0.2

—

MIN. (t_CL,t_CH)

Data-out high-impedance time from CK / CK

Address and control input hold time

t_HZ

—

t_AC.MAXps

t_IH(base)

t_IPW

475

0.6

—

ps

Address and control input pulse width

(each input)

t_CK

Address and control input setup time

DQ low-impedance time from CK / CK

DQS low-impedance from CK / CK

Mode register set command cycle time

OCD drive mode output delay

t_IS(base)

t_LZ(DQ)

t_LZ(DQS)

t_MRD

350

—

ps

2 ξ t_AC.MIN

t_AC.MAXps

t_AC.MIN

2

0

—

t_CK

t_OIT

12

—

ns

Data output hold time from DQS

Data hold skew factor

t_QH

t_HP– t_QHS

t_QHS

—

75

450

7.8

3.9

—

ps

µs

ns

t_CK

ns

8)

9)

Average periodic refresh Interval

t_REFI

Auto-Refresh to Active/Auto-Refresh command period t_RFC

Precharge-All (4 banks) command period

Read preamble

t_RP

t

_RP+ 1t_CK

—

t_RPRE

t_RPST

t_RRD

0.9

0.40

7.5

10

1.1

0.60

—

Read postamble

10)

11)

Active bank A to Active bank B command period

—

Internal Read to Precharge command delay

Data Sheet

t_RTP

7.5

—

28

Rev. 1.0, 2006-03

02102006-0OKM-JLO7

HYS72T[32/64]xxxHP–[3S/3.7]–A

Registered DDR2 SDRAM Modules

Electrical CharacteristicsAC Characteristics

Table 18

Timing Parameter by Speed Grade - DDR2-400

Symbol

Parameter

DDR2-400

Min.

Unit Note

1)2)3)4)5)6)7)

Max.

—

Write preamble

t_WPRE

t_WPST

t_WR

0.35

t_CK

ns

Write postamble

0.40

0.60

—

Write recovery time for write without Auto-Precharge

Write recovery time for write with Auto-Precharge

Internal Write to Read command delay

15

WR

t

_WR/t_CK

t_CK

ns

t_WTR

t_XARD

7.5

2

—

Exit power down to any valid command

(other than NOP or Deselect)

t_CK

Exit active power-down mode to Read command (slow t_XARDS

exit, lower power)

6 – AL

2

—

t_CK

Exit precharge power-down to any valid command

(other than NOP or Deselect)

t_XP