IAUZ40N08S5N100 [INFINEON]

车规级MOSFET;
IAUZ40N08S5N100
型号: IAUZ40N08S5N100
厂家: Infineon    Infineon
描述:

车规级MOSFET

文件: 总9页 (文件大小:826K)
中文:  中文翻译
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IAUZ40N08S5N100  
OptiMOS-5 Power-Transistor  
Product Summary  
VDS  
RDS(on)  
ID  
80  
10  
40  
V
Features  
mW  
A
• OptiMOS™ - power MOSFET for automotive applications  
• N-channel - Enhancement mode - Normal Level  
• MSL1 up to 260°C peak reflow  
• 175°C operating temperature  
PG-TSDSON-8  
• Green product (RoHS compliant)  
• 100% Avalanche tested  
1
Quality Features  
• Infineon Automotive Quality  
1
• Extended qualification beyond AEC Q101  
• Enhanced testing  
• Advanced adhesion against delamination  
• Complementary testing for board level reliability  
Type  
Package  
Marking  
PG-TSDSON-8  
5N08100  
IAUZ40N08S5N100  
Maximum ratings, at T j=25 °C, unless otherwise specified  
Value  
Parameter  
Symbol  
Conditions  
Unit  
T C=25°C,VGS=10V1)  
I D  
Continous drain current  
40  
40  
A
T C=100 °C,  
VGS=10 V2)  
Pulsed drain current2)  
I D,pulse  
EAS  
I AS  
T C=25°C  
160  
75  
Avalanche energy, single pulse2)  
Avalanche current, single pulse  
Gate source voltage  
I D=20 A  
mJ  
A
-
32  
VGS  
Ptot  
-
±20  
V
T C=25 °C  
Power dissipation  
68  
W
°C  
T j, T stg  
-
Operating and storage temperature  
IEC climatic category; DIN IEC 68-1  
-
-
-55 ... +175  
55/175/56  
Rev. 1.0  
page 1  
2019-09-16  
IAUZ40N08S5N100  
Values  
Parameter  
Symbol  
Conditions  
Unit  
min.  
typ.  
max.  
Thermal characteristics2)  
R thJC  
Thermal resistance, junction - case  
-
-
-
-
2.2  
-
K/W  
Thermal resistance,  
junction - ambient3)  
RthJA  
38.5  
Electrical characteristics, at T j=25 °C, unless otherwise specified  
Static characteristics  
V(BR)DSS VGS=0 V, I D=1 mA  
VGS(th) VDS=VGS, I D=27 µA  
Drain-source breakdown voltage  
Gate threshold voltage  
80  
-
-
V
2.2  
3
3.8  
VDS=80 V, VGS=0 V,  
T j=25 °C  
I DSS  
Zero gate voltage drain current  
-
-
-
-
1
µA  
VDS=80 V, VGS=0 V,  
T j=85 °C2)  
100  
I GSS  
VGS=20 V, VDS=0 V  
Gate-source leakage current  
-
-
-
-
-
100 nA  
14.5 mΩ  
10  
RDS(on) VGS=6 V, I D=10 A  
VGS=10 V, I D=20 A  
R G  
Drain-source on-state resistance  
11.6  
8.4  
1.2  
Gate resistance2)  
-
W
IAUZ40N08S5N100  
Values  
Parameter  
Symbol  
Conditions  
Unit  
min.  
typ.  
max.  
Dynamic characteristics2)  
Input capacitance  
Output capacitance  
Reverse transfer capacitance  
Turn-on delay time  
Rise time  
C iss  
C oss  
Crss  
t d(on)  
t r  
-
-
-
-
-
-
-
1224  
231  
13.5  
3
1591 pF  
300  
VGS=0 V, VDS=40 V,  
f =1 MHz  
20  
-
-
-
-
ns  
1
VDD=40 V, VGS=10 V,  
I D=40 A, R G=3.5 W  
t d(off)  
t f  
Turn-off delay time  
Fall time  
7
5
Gate Charge Characteristics2)  
Gate to source charge  
Gate to drain charge  
Gate charge total  
Q gs  
-
-
-
-
5.8  
4.5  
7.5  
6.8  
24.2  
-
nC  
Q gd  
VDD=40 V, I D=20 A,  
VGS=0 to 10 V  
Q g  
18.6  
4.8  
Vplateau  
Gate plateau voltage  
V
A
Reverse Diode  
Diode continous forward current2)  
Diode pulse current2)  
I S  
-
-
-
-
40  
T C=25 °C  
I S,pulse  
147  
VGS=0 V, I F=20 A,  
T j=25 °C  
VSD  
Diode forward voltage  
-
0.9  
1.2  
V
Reverse recovery time2)  
t rr  
-
-
37  
32  
-
-
ns  
VR=40 V, I F=40A,  
diF/dt =100 A/µs  
Reverse recovery charge2)  
Q rr  
nC  
1) Current is limited by bondwire; with an R thJC = 2.2 K/W the chip is able to carry 58A at 25°C.  
2) The parameter is not subject to production test - verified by design/chracterization.  
3) Device on four layer 2s2p PCB defined in accordance with JEDEC standards (JESD51-5-7).  
PCB is vertical in still air.  
Rev. 1.0  
page 3  
2019-09-16  
IAUZ40N08S5N100  
1 Power dissipation  
2 Drain current  
Ptot = f(T C); VGS ≥ 6 V  
I D = f(T C); VGS ≥ 6 V  
80  
70  
60  
50  
40  
30  
20  
10  
0
45  
40  
35  
30  
25  
20  
15  
10  
5
0
0
50  
100  
150  
200  
0
50  
100  
150  
200  
TC [°C]  
TC [°C]  
3 Safe operating area  
4 Max. transient thermal impedance  
Z thJC = f(t p)  
I D = f(VDS); T C = 25 °C; D = 0  
parameter: t p  
parameter: D =t p/T  
101  
1000  
100  
10  
1 µs  
0.5  
10 µs  
100  
100 µs  
0.1  
150 µs  
0.05  
10-1  
0.01  
single pulse  
10-2  
1
10-6  
10-5  
10-4  
10-3  
10-2  
10-1 100  
0.1  
1
10  
100  
VDS [V]  
tp [s]  
Rev. 1.0  
page 4  
2019-09-16  
IAUZ40N08S5N100  
5 Typ. output characteristics  
I D = f(VDS); T j = 25 °C  
parameter: VGS  
6 Typ. drain-source on-state resistance  
R DS(on) = (I D); T j = 25 °C  
parameter: VGS  
25  
300  
10 V  
23  
5.5 V  
5 V  
250  
6 V  
21  
6.5 V  
19  
17  
15  
13  
11  
9
200  
150  
100  
50  
7 V  
6.5 V  
6 V  
5.5 V  
5 V  
10 V  
7
5
0
0
50  
100  
150  
200  
250  
0
1
2
3
4
5
6
7
ID [A]  
VDS [V]  
7 Typ. transfer characteristics  
I D = f(VGS); VDS = 6V  
parameter: T j  
8 Typ. drain-source on-state resistance  
R DS(on) = f(T j); I D = 20 A; VGS = 10 V  
300  
250  
200  
150  
100  
50  
18  
16  
14  
12  
10  
8
-55 °C  
25 °C  
175 °C  
6
4
0
-60  
-20  
20  
60  
100  
140  
180  
2
3
4
5
6
7
Tj [°C]  
VGS [V]  
Rev. 1.0  
page 5  
2019-09-16  
IAUZ40N08S5N100  
9 Typ. gate threshold voltage  
VGS(th) = f(T j); VGS = VDS  
parameter: I D  
10 Typ. capacitances  
C = f(VDS); VGS = 0 V; f = 1 MHz  
104  
4
3.5  
3
Ciss  
270 µA  
103  
102  
101  
27 µA  
2.5  
Coss  
2
1.5  
1
Crss  
0
20  
40  
60  
80  
-60  
-20  
20  
60  
100  
140  
180  
Tj [°C]  
VDS [V]  
11 Typical forward diode characteristicis  
12 Typ. avalanche characteristics  
I AS = f(t AV  
IF = f(VSD)  
)
parameter: T j  
parameter: Tj(start)  
103  
100  
102  
25 °C  
175 °C  
25 °C  
100 °C  
10  
150 °C  
101  
100  
1
1
0
0.2 0.4 0.6 0.8  
1
1.2 1.4 1.6  
10  
100  
1000  
VSD [V]  
tAV [µs]  
Rev. 1.0  
page 6  
2019-09-16  
IAUZ40N08S5N100  
13 Typical avalanche energy  
EAS = f(T j)  
14 Drain-source breakdown voltage  
VBR(DSS) = f(T j); I D_typ = 1 mA  
parameter: I D  
87  
86  
85  
84  
83  
82  
81  
80  
79  
78  
77  
76  
160  
140  
10 A  
120  
100  
80  
20 A  
60  
40  
32 A  
20  
0
-60  
-20  
20  
60  
100  
140  
180  
25  
75  
125  
175  
Tj [°C]  
Tj [°C]  
15 Typ. gate charge  
16 Gate charge waveforms  
VGS = f(Q gate); I D = 20 A pulsed  
parameter: VDD  
10  
9
8
7
6
5
4
3
2
1
0
VGS  
16 V  
64 V  
40 V  
Qg  
Qgate  
Qgd  
Qgs  
0
5
10  
15  
20  
Qgate [nC]  
Rev. 1.0  
page 7  
2019-09-16  
IAUZ40N08S5N100  
PG-TSDSON-8: Outline  
Footprint  
Dimensions in mm  
Packaging  
Rev. 1.0  
page 8  
2019-09-16  
IAUZ40N08S5N100  
Published by  
Infineon Technologies AG  
85579 Neubiberg, Germany  
© Infineon Technologies AG 2019  
All Rights Reserved.  
Legal Disclaimer  
The information given in this document shall in no event be regarded as a guarantee of conditions  
or characteristics. With respect to any examples or hints given herein, any typical values stated  
herein and/or any information regarding the application of the device, Infineon Technologies hereby  
disclaims any and all warranties and liabilities of any kind, including without limitation, warranties  
of non-infringement of intellectual property rights of any third party.  
Information  
For further information on technology, delivery terms and conditions and prices, please contact  
the nearest Infineon Technologies Office (www.infineon.com).  
Warnings  
Due to technical requirements, components may contain dangerous substances.  
For information on the types in question, please contact the nearest Infineon Technologies Office.  
Infineon Technologies components may be used in life-support devices or systems only with the  
express written approval of Infineon Technologies, if a failure of such components can reasonably be  
expected to cause the failure of that life-support device or system or to affect the safety or  
effectiveness of that device or system. Life support devices or systems are intended to be implanted  
in the human body or to support and/or maintain and sustain and/or protect human life.  
If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.  
Rev. 1.0  
page 9  
2019-09-16  

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