IAUZ40N10S5N130 [INFINEON]

车规级MOSFET;
IAUZ40N10S5N130
型号: IAUZ40N10S5N130
厂家: Infineon    Infineon
描述:

车规级MOSFET

文件: 总10页 (文件大小:815K)
中文:  中文翻译
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IAUZ40N10S5N130  
OptiMOS-5 Power-Transistor  
Product Summary  
VDS  
100  
13  
V
RDS(on),max  
ID  
mW  
A
40  
Features  
PG-TSDSON-8-33  
• OptiMOS™ - power MOSFET for automotive applications  
• N-channel - Enhancement mode - Normal Level  
• AEC Q101 qualified  
1
• MSL1 up to 260°C peak reflow  
• 175°C operating temperature  
1
• Green Product (RoHS compliant)  
• 100% Avalanche tested  
• Feasible for automatic optical inspection (AOI)  
Type  
Package  
Marking  
IAUZ40N10S5N130  
PG-TSDSON-8-33 5N1N130  
Maximum ratings, at T j=25 °C, unless otherwise specified  
Value  
40  
Parameter  
Symbol  
Conditions  
Unit  
Continuous drain current1)2)  
I D  
T C=25°C, VGS=10V  
T C=100°C, VGS=10V  
A
35  
Pulsed drain current2)  
I D,pulse  
EAS  
I AS  
T C=25°C  
160  
60  
Avalanche energy, single pulse2)  
Avalanche current, single pulse  
Gate source voltage  
I D=20A  
mJ  
A
-
22  
VGS  
-
±20  
V
T C=25°C  
TJ =175°C  
Ptot  
Power dissipation  
68  
W
T j, T stg  
Operating and storage temperature  
-
-55 ... +175  
°C  
Rev. 1.0  
page 1  
2019-07-23  
IAUZ40N10S5N130  
Values  
Parameter  
Symbol  
Conditions  
Unit  
min.  
typ.  
max.  
Thermal characteristics2)  
R thJC  
Thermal resistance, junction - case  
-
-
-
-
-
2.2  
62  
K/W  
Thermal resistance, junction -  
ambient  
6 cm2 cooling area3)  
R thJA  
Electrical characteristics, at T j=25 °C, unless otherwise specified  
Static characteristics  
V(BR)DSS VGS=0V, I D= 1mA  
VGS(th) VDS=VGS, I D=27µA  
Drain-source breakdown voltage  
Gate threshold voltage  
100  
2.2  
-
-
V
3.0  
3.8  
VDS=100V, VGS=0V,  
T j=25°C  
I DSS  
Zero gate voltage drain current  
-
-
-
-
1
µA  
VDS=100V, VGS=0V,  
T j=125°C2)  
100  
I GSS  
VGS=20V, VDS=0V  
Gate-source leakage current  
-
-
-
-
-
100 nA  
R DS(on) VGS=6V, I D=10A  
VGS=10V, I D=20A  
R G  
Drain-source on-state resistance  
14  
17  
13  
-
mW  
10.8  
1.2  
Gate resistance2)  
W
Rev. 1.0  
page 2  
2019-07-23  
IAUZ40N10S5N130  
Values  
Parameter  
Symbol  
Conditions  
Unit  
min.  
typ.  
max.  
Dynamic characteristics2)  
Input capacitance  
Output capacitance  
Reverse transfer capacitance  
Turn-on delay time  
Rise time  
C iss  
C oss  
Crss  
t d(on)  
t r  
-
-
-
-
-
-
-
1173  
197  
11  
4
1525 pF  
256  
VGS=0V, VDS=50V,  
f =1MHz  
17  
-
-
-
-
ns  
1
VDD=50V, VGS=10V,  
I D=40A, R G=3.5W  
t d(off)  
t f  
Turn-off delay time  
Fall time  
6
5
Gate Charge Characteristics2)  
Gate to source charge  
Gate to drain charge  
Gate charge total  
Q gs  
-
-
-
-
5.5  
3.7  
17  
7.2  
6.0  
24  
-
nC  
Q gd  
VDD=50V, I D=20A,  
VGS=0 to 10V  
Q g  
Vplateau  
Gate plateau voltage  
4.7  
V
A
Reverse Diode  
Diode continous forward current2)  
Diode pulse current2)  
I S  
-
-
-
-
40  
T C=25°C  
I S,pulse  
160  
VGS=0V, I F=20A,  
T j=25°C  
VSD  
Diode forward voltage  
-
0.9  
1.1  
V
Reverse recovery time2)  
t rr  
-
-
40  
39  
-
-
ns  
VR=40V, I F=40A,  
diF/dt =100A/µs  
Reverse recovery charge2)  
Q rr  
nC  
1) Current is limited by package; with an R thJC = 2.2K/W the chip is able to carry 50A at 25°C.  
2) The parameter is not subject to production test- verified by design/characterization.  
3) Device on 40 mm x 40 mm x 1.5 mm epoxy PCB FR4 with 6 cm2 (one layer, 70 µm thick) copper area for drain  
connection. PCB is vertical in still air.  
Rev. 1.0  
page 3  
2019-07-23  
IAUZ40N10S5N130  
1 Power dissipation  
2 Drain current  
Ptot = f(T C); VGS = 10 V  
I D = f(T C); VGS = 10 V  
80  
60  
40  
20  
0
50  
40  
30  
20  
10  
0
0
50  
100  
150  
200  
0
50  
100  
150  
200  
TC [°C]  
TC [°C]  
3 Safe operating area  
4 Max. transient thermal impedance  
Z thJC = f(t p)  
I D = f(VDS); T C = 25 °C; D = 0  
parameter: t p  
parameter: D =t p/T  
101  
1000  
100  
10  
0.5  
1 µs  
100  
10 µs  
100 µs  
0.1  
150 µs  
0.05  
10-1  
0.01  
single pulse  
10-2  
1
10-6  
10-5  
10-4  
10-3  
10-2  
10-1 100  
0.1  
1
10  
100  
VDS [V]  
tp [s]  
Rev. 1.0  
page 4  
2019-07-23  
IAUZ40N10S5N130  
5 Typ. output characteristics  
I D = f(VDS); T j = 25 °C  
parameter: VGS  
6 Typ. drain-source on-state resistance  
R DS(on) = f(I D); T j = 25 °C  
parameter: VGS  
7 V  
10 V  
24  
160  
120  
80  
40  
0
5 V  
5.5 V  
6.5 V  
6 V  
22  
20  
18  
16  
14  
12  
10  
6.5 V  
6 V  
5.5 V  
5 V  
7 V  
10 V  
0
1
2
3
4
5
6
7
0
50  
100  
150  
VDS [V]  
ID [A]  
7 Typ. transfer characteristics  
I D = f(VGS); VDS = 6V  
parameter: T j  
8 Typ. drain-source on-state resistance  
R DS(on) = f(T j); I D = 20 A; VGS = 10 V  
160  
120  
80  
40  
0
25  
20  
15  
10  
5
-55 °C  
25 °C  
175 °C  
3
4
5
6
7
-60  
-20  
20  
60  
100  
140  
180  
VGS [V]  
Tj [°C]  
Rev. 1.0  
page 5  
2019-07-23  
IAUZ40N10S5N130  
9 Typ. gate threshold voltage  
VGS(th) = f(T j); VGS = VDS  
parameter: I D  
10 Typ. capacitances  
C = f(VDS); VGS = 0 V; f = 1 MHz  
3.8  
3.4  
3
104  
Ciss  
103  
Coss  
270 µA  
27 µA  
102  
2.6  
Crss  
2.2  
1.8  
1.4  
101  
100  
0
20  
40  
VDS [V]  
60  
80  
100  
-60  
-20  
20  
60  
100  
140  
180  
Tj [°C]  
11 Typical forward diode characteristics  
12 Avalanche characteristics  
I A S= f(t AV  
IF = f(VSD)  
)
parameter: T j  
parameter: Tj(start)  
103  
102  
101  
100  
25 °C  
10  
100 °C  
150 °C  
1
25 °C  
175 °C  
100  
0.1  
1
0
0.2  
0.4  
0.6  
0.8  
1
1.2  
1.4  
10  
100  
1000  
VSD [V]  
tAV [µs]  
Rev. 1.0  
page 6  
2019-07-23  
IAUZ40N10S5N130  
13 Avalanche energy  
EAS = f(T j)  
14 Drain-source breakdown voltage  
VBR(DSS) = f(T j); I D = 1 mA  
parameter: ID  
110  
108  
106  
104  
102  
100  
98  
250  
5.5 A  
200  
150  
11 A  
100  
22 A  
50  
96  
94  
0
-60  
-20  
20  
60  
100  
140  
180  
25  
75  
125  
175  
Tj [°C]  
Tj [°C]  
15 Typ. gate charge  
16 Gate charge waveforms  
VGS = f(Q gate); I D = 20 A pulsed  
parameter: VDD  
10  
9
8
7
6
5
4
3
2
1
0
V GS  
80 V  
Qg  
50 V  
20 V  
V gs(th)  
Qg(th)  
Qsw  
Qgd  
Qgate  
Qgs  
0
5
10  
Qgate [nC]  
15  
20  
Rev. 1.0  
page 7  
2019-07-23  
IAUZ40N10S5N130  
PG-TSDSON-8: Outline  
Footprint  
Dimensions in mm  
Packaging  
Rev. 1.0  
page 8  
2019-07-23  
IAUZ40N10S5N130  
Published by  
Infineon Technologies AG  
85579 Neubiberg, Germany  
© Infineon Technologies AG 2019  
All Rights Reserved.  
Legal Disclaimer  
The information given in this document shall in no event be regarded as a guarantee of conditions  
or characteristics. With respect to any examples or hints given herein, any typical values stated  
herein and/or any information regarding the application of the device, Infineon Technologies hereby  
disclaims any and all warranties and liabilities of any kind, including without limitation, warranties  
of non-infringement of intellectual property rights of any third party.  
Information  
For further information on technology, delivery terms and conditions and prices, please contact  
the nearest Infineon Technologies Office (www.infineon.com).  
Warnings  
Due to technical requirements, components may contain dangerous substances.  
For information on the types in question, please contact the nearest Infineon Technologies Office.  
Infineon Technologies components may be used in life-support devices or systems only with the  
express written approval of Infineon Technologies, if a failure of such components can reasonably be  
expected to cause the failure of that life-support device or system or to affect the safety or  
effectiveness of that device or system. Life support devices or systems are intended to be implanted  
in the human body or to support and/or maintain and sustain and/or protect human life.  
If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.  
Rev. 1.0  
page 9  
2019-07-23  
IAUZ40N10S5N130  
Revision History  
Version  
Date  
Changes  
Final Data Sheet  
Revision 1.0  
23.07.2019  
Rev. 1.0  
page 10  
2019-07-23  

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